256 lines
8.4 KiB
VHDL
Executable File
256 lines
8.4 KiB
VHDL
Executable File
----------------------------------------------------------------------------------
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--
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-- Spi controller for 6502 systems
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-- based on a design by A. Fachat
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity SpiController is
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Port (
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data_in : in STD_LOGIC_VECTOR (7 downto 0);
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data_out : out STD_LOGIC_VECTOR (7 downto 0);
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is_read : in STD_LOGIC;
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nreset : in STD_LOGIC;
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addr : in STD_LOGIC_VECTOR (1 downto 0);
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phi0 : in STD_LOGIC;
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ndev_sel : in STD_LOGIC;
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clk : in STD_LOGIC;
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miso: in std_logic;
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mosi : out STD_LOGIC;
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sclk : out STD_LOGIC;
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nsel : out STD_LOGIC;
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wp : in STD_LOGIC;
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card : in STD_LOGIC;
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pgm_en : out STD_LOGIC;
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led : out STD_LOGIC
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);
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end SpiController;
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architecture Behavioral of SpiController is
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--------------------------
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-- internal state
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signal spidatain: std_logic_vector (7 downto 0);
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signal spidataout: std_logic_vector (7 downto 0);
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signal sdhc: std_logic; -- is SDHC card
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signal inited: std_logic; -- card initialized
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signal pgmen: std_logic; -- enable EEPROM programming
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-- spi register flags
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signal tc: std_logic; -- transmission complete; cleared on spi data read
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signal bsy: std_logic; -- SPI busy
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signal frx: std_logic; -- fast receive mode
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signal ece: std_logic; -- external clock enable; 0=phi2, 1=external clock
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signal slavesel: std_logic := '1'; -- slave select output (0=selected)
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signal int_miso: std_logic;
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--------------------------
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-- helper signals
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-- shift engine
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signal start_shifting: std_logic := '0'; -- shifting data
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signal shifting2: std_logic := '0'; -- shifting data
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signal shiftdone: std_logic; -- shifting data done
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signal shiftcnt: std_logic_vector(3 downto 0); -- shift counter (5 bit)
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-- spi clock
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signal clksrc: std_logic; -- clock source (phi2 or clk_7m)
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signal shiftclk : std_logic;
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begin
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led <= not (bsy or not slavesel);
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bsy <= start_shifting or shifting2;
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process(start_shifting, shiftdone, shiftclk)
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begin
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if (rising_edge(shiftclk)) then
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if (shiftdone = '1') then
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shifting2 <= '0';
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else
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shifting2 <= start_shifting;
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end if;
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end if;
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end process;
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process(shiftcnt, nreset, shiftclk)
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begin
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if (nreset = '0') then
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shiftdone <= '0';
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elsif (rising_edge(shiftclk)) then
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if (shiftcnt = "1111") then
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shiftdone <= '1';
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else
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shiftdone <= '0';
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end if;
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end if;
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end process;
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process(nreset, shifting2, shiftcnt, shiftclk)
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begin
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if (nreset = '0') then
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shiftcnt <= (others => '0');
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elsif (rising_edge(shiftclk)) then
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if (shifting2 = '1') then
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-- count phase
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shiftcnt <= shiftcnt + 1;
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else
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shiftcnt <= (others => '0');
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end if;
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end if;
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end process;
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inproc: process(nreset, shifting2, shiftcnt, shiftclk, spidatain, miso)
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begin
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if (nreset = '0') then
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spidatain <= (others => '0');
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elsif (rising_edge(shiftclk)) then
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if (shifting2 = '1' and shiftcnt(0) = '1') then
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-- shift in to input register
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spidatain (7 downto 1) <= spidatain (6 downto 0);
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spidatain (0) <= int_miso;
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end if;
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end if;
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end process;
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outproc: process(nreset, shifting2, spidataout, shiftcnt, shiftclk)
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begin
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if (nreset = '0') then
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mosi <= '1';
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sclk <= '1';
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else
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-- clock is sync'd
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if (rising_edge(shiftclk)) then
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if (shifting2='0' or shiftdone = '1') then
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mosi <= '1';
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sclk <= '1';
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else
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-- output data directly from output register
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case shiftcnt(3 downto 1) is
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when "000" => mosi <= spidataout(7);
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when "001" => mosi <= spidataout(6);
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when "010" => mosi <= spidataout(5);
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when "011" => mosi <= spidataout(4);
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when "100" => mosi <= spidataout(3);
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when "101" => mosi <= spidataout(2);
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when "110" => mosi <= spidataout(1);
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when "111" => mosi <= spidataout(0);
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when others => mosi <= '1';
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end case;
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sclk <= shiftcnt(0);
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end if;
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end if;
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end if;
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end process;
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-- shift operation enable
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shiften: process(nreset, ndev_sel, is_read, addr, frx, shiftdone)
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begin
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-- start shifting
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if (nreset = '0' or shiftdone = '1') then
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start_shifting <= '0';
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elsif (rising_edge(ndev_sel) and addr="00" and (frx='1' or is_read='0')) then
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-- access to register 00, either write (is_read=0) or fast receive bit set (frx)
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-- then both types of access (write but also read)
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start_shifting <= '1';
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end if;
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end process;
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--------------------------
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-- spiclk - spi clock generation
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-- spiclk is still 2 times the freq. than sclk
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clksrc <= phi0 when (ece = '0') else clk;
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-- is a pulse signal to allow for divisor==0
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shiftclk <= clksrc when bsy = '1' else '0';
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--------------------------
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-- interface section
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-- inputs
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int_miso <= (miso and not slavesel);
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-- outputs
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nsel <= slavesel;
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pgm_en <= pgmen;
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tc_proc: process (ndev_sel, shiftdone)
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begin
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if (shiftdone = '1') then
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tc <= '1';
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elsif (rising_edge(ndev_sel) and addr="00") then
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tc <= '0';
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end if;
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end process;
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--------------------------
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-- cpu register section
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-- cpu read
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cpu_read: process(addr, spidatain, tc, bsy, frx, pgmen,
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ece, slavesel, wp, card, sdhc, inited)
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begin
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case addr is
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when "00" => -- read SPI data in
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data_out <= spidatain;
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when "01" => -- read status register
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data_out(0) <= pgmen;
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data_out(1) <= '0';
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data_out(2) <= ece;
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data_out(3) <= '0';
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data_out(4) <= frx;
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data_out(5) <= bsy;
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data_out(6) <= '0';
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data_out(7) <= tc;
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-- no register 2
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when "11" => -- read slave select / slave interrupt state
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data_out(0) <= slavesel;
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data_out(3 downto 1) <= (others => '0');
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data_out(4) <= sdhc;
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data_out(5) <= wp;
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data_out(6) <= card;
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data_out(7) <= inited;
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when others =>
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data_out <= (others => '0');
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end case;
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end process;
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-- cpu write
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cpu_write: process(nreset, ndev_sel, is_read, addr, data_in, card)
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begin
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if (nreset = '0') then
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ece <= '0';
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frx <= '0';
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slavesel <= '1';
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spidataout <= (others => '1');
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sdhc <= '0';
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inited <= '0';
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pgmen <= '0';
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elsif (card = '1') then
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sdhc <= '0';
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inited <= '0';
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elsif (rising_edge(ndev_sel) and is_read = '0') then
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case addr is
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when "00" => -- write SPI data out (see other process above)
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spidataout <= data_in;
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when "01" => -- write status register
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pgmen <= data_in(0);
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ece <= data_in(2);
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frx <= data_in(4);
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-- no bit 5 - 7
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-- no register 2
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when "11" => -- write slave select
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slavesel <= data_in(0);
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-- no bit 1 - 3
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sdhc <= data_in(4);
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-- no bit 5 - 6
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inited <= data_in(7);
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when others =>
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end case;
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end if;
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end process;
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end Behavioral;
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