56 lines
1.3 KiB
VHDL
56 lines
1.3 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 22:26:04 09/09/2017
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-- Design Name:
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-- Module Name: sr_latch - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity SR_Latch is
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Port ( S,R : in STD_LOGIC;
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Q : inout STD_LOGIC;
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Q_n : inout STD_LOGIC;
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Reset : in STD_LOGIC;
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Clk : in STD_LOGIC);
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end SR_Latch;
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architecture SR_Latch_arch of SR_Latch is
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begin
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process (S,R,Q,Q_n, Reset, Clk)
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begin
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if(rising_edge(Clk)) then
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if(Reset = '1') then
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Q <= '0';
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Q_n <= '1';
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else
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Q <= R NOR Q_n;
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Q_n <= S NOR Q;
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end if;
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end if;
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end process;
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end SR_Latch_arch;
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