Apple-2-HW/AppleIISd
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AppleIISd/Hardware/con-apple2.lbr
Florian Reitz aa90822a8f Rename in AII connector
2019-03-03 10:21:46 +01:00

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<?xml version="1.0" encoding="utf-8"?>
<!DOCTYPE eagle SYSTEM "eagle.dtd">
<eagle version="8.2.2">
<drawing>
<settings>
<setting alwaysvectorfont="no"/>
<setting verticaltext="up"/>
</settings>
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<library>
<description>&lt;b&gt;Apple ][ Expansion Card Templates&lt;/b&gt;
&lt;br /&gt;
Dimensions are taken from the Apple IIgs Tech Note #28</description>
<packages>
<package name="A2-50PIN-SL1-3">
<description>&lt;B&gt;Apple ][ Peripheral Card&lt;/B&gt;
&lt;br /&gt;
Standard 50-pin edge connector for Apple ][ systems
&lt;br /&gt;
Dimensions for slot #1 to #3
&lt;br /&gt;
Dimensions taken from Tech Note #28</description>
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<text x="-5.715" y="3.175" size="1.778" layer="25">&gt;NAME</text>
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<text x="-40.8432" y="-9.2964" size="1.778" layer="48">74.93 mm
2.950"</text>
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<package name="A2-50PIN-SL4-7">
<description>&lt;B&gt;Apple ][ Peripheral Card&lt;/B&gt;
&lt;br /&gt;
Standard 50-pin edge connector for Apple ][ systems
&lt;br /&gt;
Dimensions for slot #4 to #7
&lt;br /&gt;
Dimensions taken from Tech Note #28</description>
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<text x="-5.715" y="3.175" size="1.778" layer="25">&gt;NAME</text>
<text x="-94.5134" y="2.9718" size="1.778" layer="48">7,87 mm</text>
<text x="-40.8432" y="-9.2964" size="1.778" layer="48">74.93 mm
2.950"</text>
<text x="-5.715" y="-0.635" size="1.778" layer="27">&gt;VALUE</text>
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<package name="A2GS-44PIN-MEM">
<description>&lt;B&gt;Apple IIgs Memory Expansion Card&lt;/B&gt;
&lt;br /&gt;
The maximum PCB dimensions for an Apple IIgs Memory Expansion Card
&lt;br /&gt;
Dimensions taken from Tech Note #28</description>
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<smd name="39" x="-210.185" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
<smd name="40" x="-207.645" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
<smd name="41" x="-205.105" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
<smd name="42" x="-202.565" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
<smd name="43" x="-200.025" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
<smd name="44" x="-197.485" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
<smd name="22" x="-250.825" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
<smd name="21" x="-248.285" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
<smd name="20" x="-245.745" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
<smd name="19" x="-243.205" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
<smd name="18" x="-240.665" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
<smd name="17" x="-238.125" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
<smd name="16" x="-235.585" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
<smd name="15" x="-233.045" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
<smd name="14" x="-230.505" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
<smd name="13" x="-227.965" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
<smd name="12" x="-225.425" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
<smd name="11" x="-222.885" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
<smd name="10" x="-220.345" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
<smd name="09" x="-217.805" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
<smd name="08" x="-215.265" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
<smd name="07" x="-212.725" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
<smd name="06" x="-210.185" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
<smd name="05" x="-207.645" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
<smd name="04" x="-205.105" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
<smd name="03" x="-202.565" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
<smd name="02" x="-200.025" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
<smd name="01" x="-197.485" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
<text x="-280.035" y="4.445" size="1.778" layer="25">&gt;NAME</text>
<text x="-182.3466" y="2.9718" size="1.778" layer="48">7,87 mm</text>
<text x="-229.6668" y="-9.2964" size="1.778" layer="48">57,658 mm
2.270"</text>
<text x="-280.035" y="0.635" size="1.778" layer="27">&gt;VALUE</text>
<wire x1="-242.443" y1="77.597" x2="-185.293" y2="63.627" width="0.2032" layer="22"/>
<wire x1="-185.293" y1="63.627" x2="-185.293" y2="7.747" width="0.2032" layer="22"/>
</package>
</packages>
<symbols>
<symbol name="ATPIN">
<wire x1="0" y1="0.635" x2="3.175" y2="0.635" width="0.3048" layer="94"/>
<wire x1="3.175" y1="0.635" x2="3.175" y2="-0.635" width="0.3048" layer="94"/>
<wire x1="3.175" y1="-0.635" x2="0" y2="-0.635" width="0.3048" layer="94"/>
<wire x1="0" y1="-0.635" x2="0" y2="0.635" width="0.3048" layer="94"/>
<text x="4.445" y="-0.9652" size="1.778" layer="95">&gt;NAME</text>
<pin name="P" x="-2.54" y="0" visible="pad" length="short" swaplevel="1"/>
</symbol>
</symbols>
<devicesets>
<deviceset name="A2-50PIN">
<description>&lt;B&gt;Apple ][ Peripheral Card Connector&lt;/B&gt;
&lt;br /&gt;
This is the, default, 50-pin connector for slot #1 to #7
&lt;br /&gt;
Pins are laid out as seen from the top of the slot</description>
<gates>
<gate name="_+12V" symbol="ATPIN" x="-5.08" y="-38.1" addlevel="always"/>
<gate name="_D0" symbol="ATPIN" x="-5.08" y="-35.56" addlevel="always"/>
<gate name="_D1" symbol="ATPIN" x="-5.08" y="-33.02" addlevel="always"/>
<gate name="_D2" symbol="ATPIN" x="-5.08" y="-30.48" addlevel="always"/>
<gate name="_D3" symbol="ATPIN" x="-5.08" y="-27.94" addlevel="always"/>
<gate name="_D4" symbol="ATPIN" x="-5.08" y="-25.4" addlevel="always"/>
<gate name="_D5" symbol="ATPIN" x="-5.08" y="-22.86" addlevel="always"/>
<gate name="_D6" symbol="ATPIN" x="-5.08" y="-20.32" addlevel="always"/>
<gate name="_D7" symbol="ATPIN" x="-5.08" y="-17.78" addlevel="always"/>
<gate name="_!DEVSELECT" symbol="ATPIN" x="-5.08" y="-15.24" addlevel="always"/>
<gate name="_PHI0" symbol="ATPIN" x="-5.08" y="-12.7" addlevel="always"/>
<gate name="_USER1" symbol="ATPIN" x="-5.08" y="-10.16" addlevel="always"/>
<gate name="_PHI1" symbol="ATPIN" x="-5.08" y="-7.62" addlevel="always"/>
<gate name="_Q3" symbol="ATPIN" x="-5.08" y="-5.08" addlevel="always"/>
<gate name="_7M" symbol="ATPIN" x="-5.08" y="-2.54" addlevel="always"/>
<gate name="_NC@2" symbol="ATPIN" x="-5.08" y="0" addlevel="always"/>
<gate name="_-5V" symbol="ATPIN" x="-5.08" y="2.54" addlevel="always"/>
<gate name="_-12V" symbol="ATPIN" x="-5.08" y="5.08" addlevel="always"/>
<gate name="_!INH" symbol="ATPIN" x="-5.08" y="7.62" addlevel="always"/>
<gate name="_!RES" symbol="ATPIN" x="-5.08" y="10.16" addlevel="always"/>
<gate name="_!IRQ" symbol="ATPIN" x="-5.08" y="12.7" addlevel="always"/>
<gate name="_!NMI" symbol="ATPIN" x="-5.08" y="15.24" addlevel="always"/>
<gate name="_INT_IN" symbol="ATPIN" x="-5.08" y="17.78" addlevel="always"/>
<gate name="_DMA_IN" symbol="ATPIN" x="-5.08" y="20.32" addlevel="always"/>
<gate name="_GND" symbol="ATPIN" x="-5.08" y="22.86" addlevel="always"/>
<gate name="_!IOSELECT" symbol="ATPIN" x="27.94" y="-38.1" addlevel="always"/>
<gate name="_A00" symbol="ATPIN" x="27.94" y="-35.56" addlevel="always"/>
<gate name="_A01" symbol="ATPIN" x="27.94" y="-33.02" addlevel="always"/>
<gate name="_A02" symbol="ATPIN" x="27.94" y="-30.48" addlevel="always"/>
<gate name="_A03" symbol="ATPIN" x="27.94" y="-27.94" addlevel="always"/>
<gate name="_A04" symbol="ATPIN" x="27.94" y="-25.4" addlevel="always"/>
<gate name="_A05" symbol="ATPIN" x="27.94" y="-22.86" addlevel="always"/>
<gate name="_A06" symbol="ATPIN" x="27.94" y="-20.32" addlevel="always"/>
<gate name="_A07" symbol="ATPIN" x="27.94" y="-17.78" addlevel="always"/>
<gate name="_A08" symbol="ATPIN" x="27.94" y="-15.24" addlevel="always"/>
<gate name="_A09" symbol="ATPIN" x="27.94" y="-12.7" addlevel="always"/>
<gate name="_A10" symbol="ATPIN" x="27.94" y="-10.16" addlevel="always"/>
<gate name="_A11" symbol="ATPIN" x="27.94" y="-7.62" addlevel="always"/>
<gate name="_A12" symbol="ATPIN" x="27.94" y="-5.08" addlevel="always"/>
<gate name="_A13" symbol="ATPIN" x="27.94" y="-2.54" addlevel="always"/>
<gate name="_A14" symbol="ATPIN" x="27.94" y="0" addlevel="always"/>
<gate name="_A15" symbol="ATPIN" x="27.94" y="2.54" addlevel="always"/>
<gate name="_R!W" symbol="ATPIN" x="27.94" y="5.08" addlevel="always"/>
<gate name="_NC@1" symbol="ATPIN" x="27.94" y="7.62" addlevel="always"/>
<gate name="_!IOSTR" symbol="ATPIN" x="27.94" y="10.16" addlevel="always"/>
<gate name="_RDY" symbol="ATPIN" x="27.94" y="12.7" addlevel="always"/>
<gate name="_!DMA" symbol="ATPIN" x="27.94" y="15.24" addlevel="always"/>
<gate name="_INT_OUT" symbol="ATPIN" x="27.94" y="17.78" addlevel="always"/>
<gate name="_DMA_OUT" symbol="ATPIN" x="27.94" y="20.32" addlevel="always"/>
<gate name="_+5V" symbol="ATPIN" x="27.94" y="22.86" addlevel="always"/>
</gates>
<devices>
<device name="SLOT1-3" package="A2-50PIN-SL1-3">
<connects>
<connect gate="_!DEVSELECT" pin="P" pad="41"/>
<connect gate="_!DMA" pin="P" pad="22"/>
<connect gate="_!INH" pin="P" pad="32"/>
<connect gate="_!IOSELECT" pin="P" pad="01"/>
<connect gate="_!IOSTR" pin="P" pad="20"/>
<connect gate="_!IRQ" pin="P" pad="30"/>
<connect gate="_!NMI" pin="P" pad="29"/>
<connect gate="_!RES" pin="P" pad="31"/>
<connect gate="_+12V" pin="P" pad="50"/>
<connect gate="_+5V" pin="P" pad="25"/>
<connect gate="_-12V" pin="P" pad="33"/>
<connect gate="_-5V" pin="P" pad="34"/>
<connect gate="_7M" pin="P" pad="36"/>
<connect gate="_A00" pin="P" pad="02"/>
<connect gate="_A01" pin="P" pad="03"/>
<connect gate="_A02" pin="P" pad="04"/>
<connect gate="_A03" pin="P" pad="05"/>
<connect gate="_A04" pin="P" pad="06"/>
<connect gate="_A05" pin="P" pad="07"/>
<connect gate="_A06" pin="P" pad="08"/>
<connect gate="_A07" pin="P" pad="09"/>
<connect gate="_A08" pin="P" pad="10"/>
<connect gate="_A09" pin="P" pad="11"/>
<connect gate="_A10" pin="P" pad="12"/>
<connect gate="_A11" pin="P" pad="13"/>
<connect gate="_A12" pin="P" pad="14"/>
<connect gate="_A13" pin="P" pad="15"/>
<connect gate="_A14" pin="P" pad="16"/>
<connect gate="_A15" pin="P" pad="17"/>
<connect gate="_D0" pin="P" pad="49"/>
<connect gate="_D1" pin="P" pad="48"/>
<connect gate="_D2" pin="P" pad="47"/>
<connect gate="_D3" pin="P" pad="46"/>
<connect gate="_D4" pin="P" pad="45"/>
<connect gate="_D5" pin="P" pad="44"/>
<connect gate="_D6" pin="P" pad="43"/>
<connect gate="_D7" pin="P" pad="42"/>
<connect gate="_DMA_IN" pin="P" pad="27"/>
<connect gate="_DMA_OUT" pin="P" pad="24"/>
<connect gate="_GND" pin="P" pad="26"/>
<connect gate="_INT_IN" pin="P" pad="28"/>
<connect gate="_INT_OUT" pin="P" pad="23"/>
<connect gate="_NC@1" pin="P" pad="19"/>
<connect gate="_NC@2" pin="P" pad="35"/>
<connect gate="_PHI0" pin="P" pad="40"/>
<connect gate="_PHI1" pin="P" pad="38"/>
<connect gate="_Q3" pin="P" pad="37"/>
<connect gate="_R!W" pin="P" pad="18"/>
<connect gate="_RDY" pin="P" pad="21"/>
<connect gate="_USER1" pin="P" pad="39"/>
</connects>
<technologies>
<technology name=""/>
</technologies>
</device>
<device name="SLOT4-7" package="A2-50PIN-SL4-7">
<connects>
<connect gate="_!DEVSELECT" pin="P" pad="41"/>
<connect gate="_!DMA" pin="P" pad="22"/>
<connect gate="_!INH" pin="P" pad="32"/>
<connect gate="_!IOSELECT" pin="P" pad="01"/>
<connect gate="_!IOSTR" pin="P" pad="20"/>
<connect gate="_!IRQ" pin="P" pad="30"/>
<connect gate="_!NMI" pin="P" pad="29"/>
<connect gate="_!RES" pin="P" pad="31"/>
<connect gate="_+12V" pin="P" pad="50"/>
<connect gate="_+5V" pin="P" pad="25"/>
<connect gate="_-12V" pin="P" pad="33"/>
<connect gate="_-5V" pin="P" pad="34"/>
<connect gate="_7M" pin="P" pad="36"/>
<connect gate="_A00" pin="P" pad="02"/>
<connect gate="_A01" pin="P" pad="03"/>
<connect gate="_A02" pin="P" pad="04"/>
<connect gate="_A03" pin="P" pad="05"/>
<connect gate="_A04" pin="P" pad="06"/>
<connect gate="_A05" pin="P" pad="07"/>
<connect gate="_A06" pin="P" pad="08"/>
<connect gate="_A07" pin="P" pad="09"/>
<connect gate="_A08" pin="P" pad="10"/>
<connect gate="_A09" pin="P" pad="11"/>
<connect gate="_A10" pin="P" pad="12"/>
<connect gate="_A11" pin="P" pad="13"/>
<connect gate="_A12" pin="P" pad="14"/>
<connect gate="_A13" pin="P" pad="15"/>
<connect gate="_A14" pin="P" pad="16"/>
<connect gate="_A15" pin="P" pad="17"/>
<connect gate="_D0" pin="P" pad="49"/>
<connect gate="_D1" pin="P" pad="48"/>
<connect gate="_D2" pin="P" pad="47"/>
<connect gate="_D3" pin="P" pad="46"/>
<connect gate="_D4" pin="P" pad="45"/>
<connect gate="_D5" pin="P" pad="44"/>
<connect gate="_D6" pin="P" pad="43"/>
<connect gate="_D7" pin="P" pad="42"/>
<connect gate="_DMA_IN" pin="P" pad="27"/>
<connect gate="_DMA_OUT" pin="P" pad="24"/>
<connect gate="_GND" pin="P" pad="26"/>
<connect gate="_INT_IN" pin="P" pad="28"/>
<connect gate="_INT_OUT" pin="P" pad="23"/>
<connect gate="_NC@1" pin="P" pad="19"/>
<connect gate="_NC@2" pin="P" pad="35"/>
<connect gate="_PHI0" pin="P" pad="40"/>
<connect gate="_PHI1" pin="P" pad="38"/>
<connect gate="_Q3" pin="P" pad="37"/>
<connect gate="_R!W" pin="P" pad="18"/>
<connect gate="_RDY" pin="P" pad="21"/>
<connect gate="_USER1" pin="P" pad="39"/>
</connects>
<technologies>
<technology name=""/>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="A2GSRAM-44PIN" prefix="ST" uservalue="yes">
<description>&lt;B&gt;Apple IIgs Memory Expansion Slot 44-pin&lt;/B&gt;
&lt;br /&gt;
This is the 44-pin board dimensions for an Apple IIgs Memory Expansion Card
&lt;br /&gt;
Pins are laid out as seen from the top of the slot. Pin 1 is towards the front of the case/keyboard</description>
<gates>
<gate name="_GND@5" symbol="ATPIN" x="-5.08" y="-38.1" addlevel="always"/>
<gate name="_+5V@5" symbol="ATPIN" x="-5.08" y="-35.56" addlevel="always"/>
<gate name="_A15" symbol="ATPIN" x="-5.08" y="-33.02" addlevel="always"/>
<gate name="_A14" symbol="ATPIN" x="-5.08" y="-30.48" addlevel="always"/>
<gate name="_A13" symbol="ATPIN" x="-5.08" y="-27.94" addlevel="always"/>
<gate name="_A12" symbol="ATPIN" x="-5.08" y="-25.4" addlevel="always"/>
<gate name="_A11" symbol="ATPIN" x="-5.08" y="-22.86" addlevel="always"/>
<gate name="_A10" symbol="ATPIN" x="-5.08" y="-20.32" addlevel="always"/>
<gate name="_D1" symbol="ATPIN" x="-5.08" y="-17.78" addlevel="always"/>
<gate name="_CRAS\" symbol="ATPIN" x="-5.08" y="-15.24" addlevel="always"/>
<gate name="_GND@4" symbol="ATPIN" x="-5.08" y="-12.7" addlevel="always"/>
<gate name="_D3" symbol="ATPIN" x="-5.08" y="-10.16" addlevel="always"/>
<gate name="_ABORT" symbol="ATPIN" x="-5.08" y="-7.62" addlevel="always"/>
<gate name="_02" symbol="ATPIN" x="-5.08" y="-5.08" addlevel="always"/>
<gate name="_D5" symbol="ATPIN" x="-5.08" y="-2.54" addlevel="always"/>
<gate name="_D4" symbol="ATPIN" x="-5.08" y="0" addlevel="always"/>
<gate name="_D6" symbol="ATPIN" x="-5.08" y="2.54" addlevel="always"/>
<gate name="_MSIZE" symbol="ATPIN" x="-5.08" y="5.08" addlevel="always"/>
<gate name="_CSEL\" symbol="ATPIN" x="-5.08" y="7.62" addlevel="always"/>
<gate name="_GND@3" symbol="ATPIN" x="-5.08" y="10.16" addlevel="always"/>
<gate name="_+5V@4" symbol="ATPIN" x="-5.08" y="12.7" addlevel="always"/>
<gate name="_D0" symbol="ATPIN" x="-5.08" y="15.24" addlevel="always"/>
<gate name="_GND@1" symbol="ATPIN" x="27.94" y="-38.1" addlevel="always"/>
<gate name="_+5V@1" symbol="ATPIN" x="27.94" y="-35.56" addlevel="always"/>
<gate name="_FRA9" symbol="ATPIN" x="27.94" y="-33.02" addlevel="always"/>
<gate name="_FRA8" symbol="ATPIN" x="27.94" y="-30.48" addlevel="always"/>
<gate name="_D2" symbol="ATPIN" x="27.94" y="-27.94" addlevel="always"/>
<gate name="_FRA6" symbol="ATPIN" x="27.94" y="-25.4" addlevel="always"/>
<gate name="_FRA3" symbol="ATPIN" x="27.94" y="-22.86" addlevel="always"/>
<gate name="_FRA4" symbol="ATPIN" x="27.94" y="-20.32" addlevel="always"/>
<gate name="_FRA5" symbol="ATPIN" x="27.94" y="-17.78" addlevel="always"/>
<gate name="_FRA7" symbol="ATPIN" x="27.94" y="-15.24" addlevel="always"/>
<gate name="_+5V@2" symbol="ATPIN" x="27.94" y="-12.7" addlevel="always"/>
<gate name="_FR/W" symbol="ATPIN" x="27.94" y="-10.16" addlevel="always"/>
<gate name="_FRA0" symbol="ATPIN" x="27.94" y="-7.62" addlevel="always"/>
<gate name="_FRA2" symbol="ATPIN" x="27.94" y="-5.08" addlevel="always"/>
<gate name="_FRA1" symbol="ATPIN" x="27.94" y="-2.54" addlevel="always"/>
<gate name="_D7" symbol="ATPIN" x="27.94" y="0" addlevel="always"/>
<gate name="_CCAS\" symbol="ATPIN" x="27.94" y="2.54" addlevel="always"/>
<gate name="_CROW0" symbol="ATPIN" x="27.94" y="5.08" addlevel="always"/>
<gate name="_CROW1" symbol="ATPIN" x="27.94" y="7.62" addlevel="always"/>
<gate name="_CROMSEL\" symbol="ATPIN" x="27.94" y="10.16" addlevel="always"/>
<gate name="_+5V@3" symbol="ATPIN" x="27.94" y="12.7" addlevel="always"/>
<gate name="_GND@2" symbol="ATPIN" x="27.94" y="15.24" addlevel="always"/>
</gates>
<devices>
<device name="IIGS-RAM" package="A2GS-44PIN-MEM">
<connects>
<connect gate="_+5V@1" pin="P" pad="02"/>
<connect gate="_+5V@2" pin="P" pad="11"/>
<connect gate="_+5V@3" pin="P" pad="21"/>
<connect gate="_+5V@4" pin="P" pad="24"/>
<connect gate="_+5V@5" pin="P" pad="43"/>
<connect gate="_02" pin="P" pad="31"/>
<connect gate="_A10" pin="P" pad="37"/>
<connect gate="_A11" pin="P" pad="38"/>
<connect gate="_A12" pin="P" pad="39"/>
<connect gate="_A13" pin="P" pad="40"/>
<connect gate="_A14" pin="P" pad="41"/>
<connect gate="_A15" pin="P" pad="42"/>
<connect gate="_ABORT" pin="P" pad="32"/>
<connect gate="_CCAS\" pin="P" pad="17"/>
<connect gate="_CRAS\" pin="P" pad="35"/>
<connect gate="_CROMSEL\" pin="P" pad="20"/>
<connect gate="_CROW0" pin="P" pad="18"/>
<connect gate="_CROW1" pin="P" pad="19"/>
<connect gate="_CSEL\" pin="P" pad="26"/>
<connect gate="_D0" pin="P" pad="25"/>
<connect gate="_D1" pin="P" pad="36"/>
<connect gate="_D2" pin="P" pad="05"/>
<connect gate="_D3" pin="P" pad="33"/>
<connect gate="_D4" pin="P" pad="29"/>
<connect gate="_D5" pin="P" pad="30"/>
<connect gate="_D6" pin="P" pad="28"/>
<connect gate="_D7" pin="P" pad="16"/>
<connect gate="_FR/W" pin="P" pad="12"/>
<connect gate="_FRA0" pin="P" pad="13"/>
<connect gate="_FRA1" pin="P" pad="15"/>
<connect gate="_FRA2" pin="P" pad="14"/>
<connect gate="_FRA3" pin="P" pad="07"/>
<connect gate="_FRA4" pin="P" pad="08"/>
<connect gate="_FRA5" pin="P" pad="09"/>
<connect gate="_FRA6" pin="P" pad="06"/>
<connect gate="_FRA7" pin="P" pad="10"/>
<connect gate="_FRA8" pin="P" pad="04"/>
<connect gate="_FRA9" pin="P" pad="03"/>
<connect gate="_GND@1" pin="P" pad="01"/>
<connect gate="_GND@2" pin="P" pad="22"/>
<connect gate="_GND@3" pin="P" pad="23"/>
<connect gate="_GND@4" pin="P" pad="34"/>
<connect gate="_GND@5" pin="P" pad="44"/>
<connect gate="_MSIZE" pin="P" pad="27"/>
</connects>
<technologies>
<technology name=""/>
</technologies>
</device>
</devices>
</deviceset>
</devicesets>
</library>
</drawing>
<compatibility>
<note version="6.3" minversion="6.2.2" severity="warning">
Since Version 6.2.2 text objects can contain more than one line,
which will not be processed correctly with this version.
</note>
</compatibility>
</eagle>
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