222 lines
5.9 KiB
VHDL
222 lines
5.9 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 20:44:25 10/09/2017
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-- Design Name:
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-- Module Name: IO - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity AppleIISd is
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Port (
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ADD_HIGH : in std_logic_vector(11 downto 8);
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ADD_LOW : in std_logic_vector(1 downto 0);
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B : out std_logic_vector(10 downto 8);
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CARD : in std_logic;
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DATA : inout std_logic_vector (7 downto 0);
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CLK : in std_logic;
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LED : out std_logic;
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NDEV_SEL : in std_logic;
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NG : out std_logic;
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NIO_SEL : in std_logic;
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NIO_STB : in std_logic;
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NOE : out std_logic;
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NWE : out std_logic;
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PHI0 : in std_logic;
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NRESET : in std_logic;
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RNW : in std_logic;
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MISO : in std_logic;
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MOSI : out std_logic;
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NSEL : out std_logic;
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SCLK : out std_logic;
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WP : in std_logic
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-- synthesis translate_off
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;
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data_dbg : out std_logic_vector (7 downto 0);
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add_dbg : out std_logic_vector (1 downto 0);
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data_en_dbg : out std_logic
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-- synthesis translate_on
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);
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end AppleIISd;
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architecture Behavioral of AppleIISd is
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signal data_in : std_logic_vector (7 downto 0);
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signal data_out : std_logic_vector (7 downto 0);
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signal addr_low_int : std_logic_vector (1 downto 0);
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signal s_spi_data_in : std_logic_vector(7 downto 0);
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signal s_spi_data_out : std_logic_vector(7 downto 0);
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signal s_bsy : std_logic;
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signal s_tc : std_logic;
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signal s_ece : std_logic;
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signal s_frx : std_logic;
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signal data_en : std_logic;
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signal pgm_en : std_logic;
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component Registers is
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Port (
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ADDR : in STD_LOGIC_VECTOR (1 downto 0);
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BUS_DATA_IN : in STD_LOGIC_VECTOR (7 downto 0);
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BUS_DATA_OUT : out STD_LOGIC_VECTOR (7 downto 0);
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SPI_DATA_IN : in STD_LOGIC_VECTOR (7 downto 0);
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SPI_DATA_OUT : out STD_LOGIC_VECTOR (7 downto 0);
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PGMEN : out STD_LOGIC;
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ECE : out STD_LOGIC;
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FRX : out STD_LOGIC;
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SLAVESEL : out STD_LOGIC;
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LED : out STD_LOGIC;
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BSY : in STD_LOGIC;
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TC : in STD_LOGIC;
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WP : in STD_LOGIC;
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CARD : in STD_LOGIC;
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NRESET : in STD_LOGIC;
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NDEV_SEL : in STD_LOGIC;
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IS_READ : in STD_LOGIC
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);
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end component;
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component SpiController is
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Port (
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BUS_DATA : in STD_LOGIC_VECTOR (7 downto 0);
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SPI_DATA : out STD_LOGIC_VECTOR (7 downto 0);
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IS_READ : in STD_LOGIC;
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NRESET : in STD_LOGIC;
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ADDR : in STD_LOGIC_VECTOR (1 downto 0);
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CLK_SLOW : in STD_LOGIC;
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NDEV_SEL : in STD_LOGIC;
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CLK_FAST : in STD_LOGIC;
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MISO: in std_logic;
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MOSI : out STD_LOGIC;
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SCLK : out STD_LOGIC;
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BSY : out STD_LOGIC;
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TC : out STD_LOGIC;
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FRX : in std_logic;
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ECE : in std_logic
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);
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end component;
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component AddressDecoder
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Port (
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A : in std_logic_vector (11 downto 8);
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B : out std_logic_vector (10 downto 8);
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CLK : in std_logic;
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PHI0 : in std_logic;
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RNW : in std_logic;
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NDEV_SEL : in std_logic;
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NIO_SEL : in std_logic;
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NIO_STB : in std_logic;
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NRESET : in std_logic;
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DATA_EN : out std_logic;
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PGM_EN : in std_logic;
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NG : out std_logic;
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NOE : out std_logic;
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NWE : out std_logic
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);
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end component;
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begin
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regs: Registers port map(
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ADDR => addr_low_int,
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BUS_DATA_IN => data_in,
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BUS_DATA_OUT => data_out,
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SPI_DATA_IN => s_spi_data_in,
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SPI_DATA_OUT => s_spi_data_out,
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PGMEN => pgm_en,
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ECE => s_ece,
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FRX => s_frx,
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SLAVESEL => NSEL,
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LED => LED,
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BSY => s_bsy,
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TC => s_tc,
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WP => WP,
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CARD => CARD,
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NRESET => NRESET,
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NDEV_SEL => NDEV_SEL,
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IS_READ => RNW
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);
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spi: SpiController port map(
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BUS_DATA => s_spi_data_out,
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SPI_DATA => s_spi_data_in,
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IS_READ => RNW,
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NRESET => NRESET,
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ADDR => addr_low_int,
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CLK_SLOW => PHI0,
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CLK_FAST => CLK,
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NDEV_SEL => NDEV_SEL,
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MISO => MISO,
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MOSI => MOSI,
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SCLK => SCLK,
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BSY => s_bsy,
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TC => s_tc,
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FRX => s_frx,
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ECE => s_ece
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);
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addDec: AddressDecoder port map(
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A => ADD_HIGH,
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B => B,
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CLK => CLK,
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PHI0 => PHI0,
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RNW => RNW,
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NDEV_SEL => NDEV_SEL,
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NIO_SEL => NIO_SEL,
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NIO_STB => NIO_STB,
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NRESET => NRESET,
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DATA_EN => data_en,
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PGM_EN => pgm_en,
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NOE => NOE,
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NWE => NWE,
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NG => NG
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);
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DATA <= data_out when (data_en = '1') else (others => 'Z'); -- data bus tristate
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-- synthesis translate_off
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data_dbg <= data_in;
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add_dbg <= addr_low_int;
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data_en_dbg <= data_en;
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-- synthesis translate_on
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data_latch: process(CLK)
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begin
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if falling_edge(CLK) then
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addr_low_int <= ADD_LOW;
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if (NDEV_SEL = '0') then
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data_in <= DATA;
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end if;
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end if;
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end process;
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end Behavioral;
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