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add PS2 Keyboard
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Stefan
parent
cc4743296e
commit
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45
src/PS2/Debouncer.vhd
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45
src/PS2/Debouncer.vhd
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-- (C) Rui T. Sousa from http://sweet.ua.pt/~a16360
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity Debouncer is
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generic (Delay : positive);
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port (
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Clock : in STD_LOGIC;
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Reset : in STD_LOGIC;
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Input : in STD_LOGIC;
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Output : out STD_LOGIC
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);
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end Debouncer;
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architecture Behavioral of Debouncer is
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signal DelayCounter : natural range 0 to Delay;
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signal Internal : STD_LOGIC;
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begin
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process(Clock, Reset)
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begin
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if rising_edge(Clock) then
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if Reset = '1' then
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Output <= '0';
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Internal <= '0';
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DelayCounter <= 0;
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else
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if Input /= Internal then
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Internal <= Input;
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DelayCounter <= 0;
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elsif DelayCounter = Delay then
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Output <= Internal;
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else
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DelayCounter <= DelayCounter + 1;
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end if;
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end if;
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end if;
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end process;
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end Behavioral;
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166
src/PS2/KeyboardMapper.vhd
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166
src/PS2/KeyboardMapper.vhd
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-- (C) Rui T. Sousa from http://sweet.ua.pt/~a16360
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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entity KeyboardMapper is
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port (
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Clock : in std_logic;
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Reset : in std_logic;
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PS2Busy : in std_logic;
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PS2Error : in std_logic;
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DataReady : in std_logic;
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DataByte : in std_logic_vector(7 downto 0);
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Send : out std_logic;
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Command : out std_logic_vector(7 downto 0);
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CodeReady : out std_logic;
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ScanCode : out std_logic_vector(9 downto 0)
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);
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end KeyboardMapper;
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-- ScanCode(9) = 1 -> Extended
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-- = 0 -> Regular (Not Extended)
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-- ScanCode(8) = 1 -> Break
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-- = 0 -> Make
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-- ScanCode(7 downto 0) -> Key Code
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architecture Behavioral of KeyboardMapper is
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type StateType is (ResetKbd, ResetAck, WaitForBAT, Start, Extended, ExtendedBreak, Break, LEDs, CheckAck);
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signal State : StateType := Start;
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signal CapsLock : STD_LOGIC;
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signal NumLock : STD_LOGIC;
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signal ScrollLock : STD_LOGIC;
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-- signal PauseON : STD_LOGIC;
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begin
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process(Reset, PS2Error, Clock)
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begin
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if Reset = '1' or PS2Error = '1' then
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CapsLock <= '0';
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NumLock <= '0';
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ScrollLock <= '0';
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-- PauseON <= '0';
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Send <= '0';
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Command <= (others => '0');
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CodeReady <= '0';
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ScanCode <= (others => '0');
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State <= Start;
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elsif rising_edge(Clock) then
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case State is
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when ResetKbd =>
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if PS2Busy = '0' then
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Send <= '1';
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Command <= x"FF";
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State <= ResetAck;
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end if;
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when ResetAck =>
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Send <= '0';
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if Dataready = '1' then
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if DataByte = x"FA" then
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State <= WaitForBAT;
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else
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State <= ResetKbd;
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end if;
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end if;
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when WaitForBAT =>
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if DataReady = '1' then
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if DataByte = x"AA" then -- BAT(self test) completed successfully
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State <= Start;
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else
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State <= ResetKbd;
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end if;
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end if;
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when Start =>
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CodeReady <= '0';
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if DataReady = '1' then
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case DataByte is
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when x"E0" =>
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State <= Extended;
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when x"F0" =>
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State <= Break;
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when x"FA" => --Acknowledge
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null;
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when x"AA" =>
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State <= Start;
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when x"FC" =>
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State <= ResetKbd;
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when x"58" =>
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Send <= '1';
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Command <= x"ED";
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CapsLock <= not CapsLock;
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ScanCode <= "00" & DataByte;
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CodeReady <= '1';
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State <= LEDs;
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when x"77" =>
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Send <= '1';
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Command <= x"ED";
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NumLock <= not NumLock;
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ScanCode <= "00" & DataByte;
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CodeReady <= '1';
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State <= LEDs;
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when x"7E" =>
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Send <= '1';
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Command <= x"ED";
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ScrollLock <= not ScrollLock;
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ScanCode <= "00" & DataByte;
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CodeReady <= '1';
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State <= LEDs;
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when others =>
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ScanCode <= "00" & DataByte;
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CodeReady <= '1';
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State <= Start;
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end case;
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end if;
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when Extended =>
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if DataReady = '1' then
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if DataByte = x"F0" then
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State <= ExtendedBreak;
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else
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ScanCode <= "10" & DataByte;
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CodeReady <= '1';
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State <= Start;
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end if;
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end if;
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when ExtendedBreak =>
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if DataReady = '1' then
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ScanCode <= "11" & DataByte;
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CodeReady <= '1';
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State <= Start;
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end if;
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when Break =>
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if DataReady = '1' then
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ScanCode <= "01" & DataByte;
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CodeReady <= '1';
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State <= Start;
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end if;
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when LEDs =>
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Send <= '0';
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CodeReady <= '0';
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if Dataready = '1' then
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if DataByte = x"FA" then
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Send <= '1';
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Command <= "00000" & CapsLock & NumLock & ScrollLock;
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State <= CheckAck;
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elsif DataByte = x"FE" then
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Send <= '1';
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end if;
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end if;
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when CheckAck =>
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Send <= '0';
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if Dataready = '1' then
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if DataByte = x"FA" then
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State <= Start;
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elsif DataByte = x"FE" then
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Send <= '1';
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end if;
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end if;
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when others => null;
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end case;
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end if;
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end process;
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end Behavioral;
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211
src/PS2/PS2Controller.vhd
Normal file
211
src/PS2/PS2Controller.vhd
Normal file
@ -0,0 +1,211 @@
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-- (C) Rui T. Sousa from http://sweet.ua.pt/~a16360
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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entity PS2Controller is
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GENERIC(
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clk_freq : INTEGER := 32 );-- system clock frequency in MHz
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port (
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Reset : in std_logic;
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Clock : in std_logic;
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PS2Clock : inout std_logic;
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PS2Data : inout std_logic;
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Send : in std_logic;
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Command : in std_logic_vector(7 downto 0);
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PS2Busy : out std_logic;
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PS2Error : buffer std_logic;
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DataReady : out std_logic;
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DataByte : out std_logic_vector(7 downto 0)
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);
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end PS2Controller;
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architecture Behavioral of PS2Controller is
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constant ClockFreq : natural := clk_freq; -- MHz
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constant Time100us : natural := 100 * ClockFreq;
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constant Time20us : natural := 20 * ClockFreq;
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constant DebounceDelay : natural := 16;
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type StateType is (Idle, ReceiveData, InhibitComunication, RequestToSend, SendData, CheckAck, WaitRiseClock);
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signal State : StateType;
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signal BitsRead : natural range 0 to 10;
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signal BitsSent : natural range 0 to 10;
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signal Byte : std_logic_vector(7 downto 0);
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signal CountOnes : std_logic; -- One bit only to know if even or odd number of ones
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signal DReady : std_logic;
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signal PS2ClockPrevious : std_logic;
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signal PS2ClockOut : std_logic;
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signal PS2Clock_Z : std_logic;
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signal PS2Clock_D : std_logic;
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signal PS2DataOut : std_logic;
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signal PS2Data_Z : std_logic;
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signal PS2Data_D : std_logic;
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signal TimeCounter : natural range 0 to Time100us;
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begin
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DebounceClock: entity work.Debouncer
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generic map (Delay => DebounceDelay)
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port map (
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Clock => Clock,
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Reset => Reset,
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Input => PS2Clock,
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Output => PS2Clock_D
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);
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DebounceData: entity work.Debouncer
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generic map (Delay => DebounceDelay)
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port map (
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Clock => Clock,
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Reset => Reset,
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Input => PS2Data,
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Output => PS2Data_D
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);
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PS2Clock <= PS2ClockOut when PS2Clock_Z <= '0' else 'Z';
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PS2Data <= PS2DataOut when PS2Data_Z <= '0' else 'Z';
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process(Reset, Clock)
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begin
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if rising_edge(Clock) then
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if Reset = '1' then
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PS2Clock_Z <= '1';
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PS2ClockOut <= '1';
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PS2Data_Z <= '1';
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PS2DataOut <= '1';
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DataReady <= '0';
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DReady <= '0';
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DataByte <= (others => '0');
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PS2Busy <= '0';
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PS2Error <= '0';
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BitsRead <= 0;
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BitsSent <= 0;
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CountOnes <= '0';
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TimeCounter <= 0;
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PS2ClockPrevious <= '1';
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Byte <= x"FF";
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State <= InhibitComunication;
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else
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PS2ClockPrevious <= PS2Clock_D;
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case State is
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when Idle =>
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DataReady <= '0';
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DReady <= '0';
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BitsRead <= 0;
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PS2Error <= '0';
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CountOnes <= '0';
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if PS2Data_D = '0' then -- Start bit
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PS2Busy <= '1';
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State <= ReceiveData;
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elsif Send = '1' then
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Byte <= Command;
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PS2Busy <= '1';
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TimeCounter <= 0;
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State <= InhibitComunication;
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else
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State <= Idle;
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end if;
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when ReceiveData =>
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if PS2ClockPrevious = '1' and PS2Clock_D = '0' then -- falling edge
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case BitsRead is
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when 1 to 8 => -- 8 Data bits
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Byte(BitsRead - 1) <= PS2Data_D;
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if PS2Data_D = '1' then
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CountOnes <= not CountOnes;
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end if;
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when 9 => -- Parity bit
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case CountOnes is
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when '0' =>
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if PS2Data_D = '0' then
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PS2Error <= '1'; -- Error when CountOnes is even (0)
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else -- and parity bit is unasserted
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PS2Error <= '0';
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end if;
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when others =>
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if PS2Data_D = '1' then
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PS2Error <= '1'; -- Error when CountOnes is odd (1)
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else -- and parity bit is asserted
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PS2Error <= '0';
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end if;
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end case;
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when 10 => -- Stop bit
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if PS2Error = '0' then
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DataByte <= Byte;
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DReady <= '1';
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else
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DReady <= '0';
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end if;
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State <= WaitRiseClock;
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when others => null;
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end case;
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BitsRead <= BitsRead + 1;
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end if;
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when InhibitComunication =>
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PS2Clock_Z <= '0';
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PS2ClockOut <= '0';
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if TimeCounter = Time100us then
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TimeCounter <= 0;
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State <= RequestToSend;
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else
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TimeCounter <= TimeCounter + 1;
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end if;
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when RequestToSend =>
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PS2Clock_Z <= '1';
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PS2Data_Z <= '0';
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PS2DataOut <= '0'; -- Sets the start bit, valid when PS2Clock is high
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if TimeCounter = Time20us then
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TimeCounter <= 0;
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PS2ClockOut <= '1';
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BitsSent <= 1;
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State <= SendData;
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else
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TimeCounter <= TimeCounter + 1;
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end if;
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when SendData =>
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PS2Clock_Z <= '1';
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if PS2ClockPrevious = '1' and PS2Clock_D = '0' then -- falling edge
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case BitsSent is
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when 1 to 8 => -- 8 Data bits
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if Byte(BitsSent - 1) = '0' then
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PS2DataOut <= '0';
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else
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CountOnes <= not CountOnes;
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PS2DataOut <= '1';
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end if;
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when 9 => -- Parity bit
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if CountOnes = '0' then
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PS2DataOut <= '1';
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else
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PS2DataOut <= '0';
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end if;
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when 10 => -- Stop bit
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PS2DataOut <= '1';
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State <= CheckAck;
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when others => null;
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end case;
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BitsSent <= BitsSent + 1;
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end if;
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when CheckAck =>
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PS2Data_Z <= '1';
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if PS2ClockPrevious = '1' and PS2Clock_D = '0' then
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if PS2Data_D = '1' then -- no Acknowledge received
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PS2Error <= '1';
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end if;
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State <= WaitRiseClock;
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end if;
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when WaitRiseClock =>
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if PS2ClockPrevious = '0' and PS2Clock_D = '1' then
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PS2Busy <= '0';
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DataReady <= DReady;
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State <= Idle;
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end if;
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when others => null;
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end case;
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end if;
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end if;
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end process;
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end Behavioral;
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