mirror of
https://github.com/mandl/Apple_II_vhdl.git
synced 2025-02-19 00:30:25 +00:00
add new cpu T65
This commit is contained in:
parent
fd6c06bb83
commit
ee98dafec8
66
Apple2.xise
66
Apple2.xise
@ -17,27 +17,23 @@
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<files>
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<file xil_pn:name="src/cpu6502.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
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</file>
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<file xil_pn:name="src/character_rom.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
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</file>
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<file xil_pn:name="src/disk_ii_rom.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
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</file>
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<file xil_pn:name="src/disk_ii.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
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</file>
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<file xil_pn:name="src/main_roms.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
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</file>
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<file xil_pn:name="src/spi_controller.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
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</file>
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<file xil_pn:name="src/timing_testbench.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
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@ -47,46 +43,46 @@
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</file>
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<file xil_pn:name="src/vga_controller.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
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</file>
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<file xil_pn:name="src/video_generator.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
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</file>
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<file xil_pn:name="src/apple2.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
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</file>
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<file xil_pn:name="src/timing_generator.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
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</file>
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<file xil_pn:name="src/papilio_duo.ucf" xil_pn:type="FILE_UCF">
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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</file>
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<file xil_pn:name="src/dac.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
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</file>
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<file xil_pn:name="src/cpu_hexy.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="112"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
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</file>
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<file xil_pn:name="src/disk_disp.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="116"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
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</file>
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<file xil_pn:name="src/grp_debouncer.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="120"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
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</file>
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<file xil_pn:name="build/apple_II_auto_rom.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="126"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
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</file>
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<file xil_pn:name="src/keyboard_apple.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="83"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
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</file>
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<file xil_pn:name="src/PS2/Debouncer.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="84"/>
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@ -94,23 +90,43 @@
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</file>
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<file xil_pn:name="src/PS2/Keyboard.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="85"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
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</file>
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<file xil_pn:name="src/PS2/KeyboardMapper.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="86"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
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</file>
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<file xil_pn:name="src/PS2/PS2Controller.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="87"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
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</file>
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<file xil_pn:name="src/apple2_top_papilio_duo.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="90"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
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</file>
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<file xil_pn:name="src/dcm.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="84"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
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</file>
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<file xil_pn:name="build/bios_rom.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
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</file>
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<file xil_pn:name="src/cpu/t65/T65_ALU.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="78"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
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</file>
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<file xil_pn:name="src/cpu/t65/T65_MCode.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="79"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
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</file>
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<file xil_pn:name="src/cpu/t65/T65_Pack.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="80"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
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</file>
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<file xil_pn:name="src/cpu/t65/T65.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="81"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
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</file>
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</files>
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@ -297,7 +313,7 @@
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<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
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<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
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<property xil_pn:name="Package" xil_pn:value="tqg144" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Package" xil_pn:value="tqg144" xil_pn:valueState="default"/>
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<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
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@ -4,6 +4,7 @@ FPGAs.
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The source code is copied from
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Stephen A. Edwards, sedwards@cs.columbia.edu
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http://www1.cs.columbia.edu/~sedwards
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http://www1.cs.columbia.edu/~sedwards/apple2fpga/
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@ -13,14 +14,16 @@ http://www1.cs.columbia.edu/~sedwards/apple2fpga/
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Build ToDO
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- Download the Apple II roms from the web
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-
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Download the Apple II roms from the web
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F12 Switch debug info screen on/off
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F2 Track + 1
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F3 Track - 1
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F6 Switch b/w mode / colormode
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@ -30,7 +30,7 @@ begin
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PS2_Controller: entity work.PS2Controller
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generic map(
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clk_freq => 14
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clk_freq => 14 -- 14 MHz clock
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)
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port map (
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Reset => Reset,
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@ -12,14 +12,18 @@ use ieee.numeric_std.all;
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entity apple2 is
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generic (
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use_monitor_rom : boolean := true;
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use_auto_rom : boolean := false
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use_bios_rom : boolean := true; -- use test bios
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use_auto_rom : boolean := false; -- use apple II roms
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use_cpu65xx_core : boolean := false;
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use_T65_core : boolean := true
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);
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port (
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CLK_14M : in std_logic; -- 14.31818 MHz master clock
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CLK_2M : out std_logic;
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PRE_PHASE_ZERO : out std_logic;
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FLASH_CLK : in std_logic; -- approx. 2 Hz flashing char clock
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FLASH_CLK : in std_logic; -- approx. 2 Hz flashing char clock
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reset : in std_logic;
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ADDR : out unsigned(15 downto 0); -- CPU address
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ram_addr : out unsigned(15 downto 0); -- RAM address
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@ -79,7 +83,9 @@ architecture rtl of apple2 is
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-- CPU signals
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signal D_IN : unsigned(7 downto 0);
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signal A : unsigned(15 downto 0);
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signal A_BIG : unsigned(23 downto 0);
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signal we : std_logic;
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signal R_W_n : std_logic;
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-- Main ROM signals
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signal rom_out : unsigned(7 downto 0);
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@ -103,7 +109,8 @@ begin
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CLK_2M <= Q3;
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PRE_PHASE_ZERO <= PRE_PHASE_ZERO_sig;
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ram_addr <= A when PHASE_ZERO = '1' else VIDEO_ADDRESS;
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ram_we <= we and not RAS_N when PHASE_ZERO = '1' else '0';
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@ -266,6 +273,7 @@ begin
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VIDEO => VIDEO,
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COLOR_LINE => COLOR_LINE);
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cpu65xx_core: if use_cpu65xx_core generate
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cpu : entity work.cpu65xx
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generic map (
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pipelineOpcode => false,
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@ -288,23 +296,49 @@ begin
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debugY => debugY,
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debugS => debugS
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);
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end generate;
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T65_core: if use_T65_core generate
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cpu : entity work.T65 port map (
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Mode => "01",
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Abort_n => '1',
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SO_n => '1',
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Res_n => not reset,
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Enable => not PRE_PHASE_ZERO_sig,
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Clk => Q3,
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Rdy => '1',
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IRQ_n => '1',
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NMI_n => '1',
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R_W_n => R_W_n,
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Sync => open,
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unsigned(A(23 downto 0)) => A_BIG,
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DI(7 downto 0) => std_logic_vector(D_IN),
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unsigned(DO(7 downto 0)) => D
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);
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A <= A_BIG( 15 downto 0);
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we <= not R_W_n;
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end generate;
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-- Original Apple had asynchronous ROMs. We use a synchronous ROM
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-- that needs its address earlier, hence the odd clock.
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monitor_rom: if use_monitor_rom generate
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roms : entity work.main_roms port map (
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addr => rom_addr,
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clk => CLK_14M,
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dout => rom_out);
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end generate;
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auto_rom: if use_auto_rom generate
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-- apple II roms
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roms : entity work.apple_II_auto_rom port map (
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addr => std_logic_vector(rom_addr),
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clk => CLK_14M,
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unsigned(DATA) => rom_out);
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end generate;
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bios_rom: if use_bios_rom generate
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-- test bios
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roms : entity work.bios_rom port map (
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addr => std_logic_vector(rom_addr),
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clk => CLK_14M,
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unsigned(DATA) => rom_out);
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end generate;
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end rtl;
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@ -186,11 +186,12 @@ begin
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core : entity work.apple2
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generic map (
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use_monitor_rom => false,
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use_auto_rom => true
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)
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generic map(
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use_bios_rom => false,
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use_auto_rom => true
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)
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port map (
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CLK_14M => CLK_14M,
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|
539
src/character_rom.vhd
Normal file
539
src/character_rom.vhd
Normal file
@ -0,0 +1,539 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity character_rom is
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port (
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addr : in unsigned(8 downto 0);
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clk : in std_logic;
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dout : out unsigned(4 downto 0));
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end character_rom;
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architecture rtl of character_rom is
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type rom_array is array (0 to 511) of unsigned(4 downto 0);
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constant ROM : rom_array := (
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"01110",
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"10001",
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"10101",
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"11101",
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"01101",
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"00001",
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"11110",
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"00000",
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"00100",
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"01010",
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"10001",
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"10001",
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"11111",
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"10001",
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"10001",
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"00000",
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"01111",
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"10001",
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"10001",
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"01111",
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"10001",
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"10001",
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"01111",
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"00000",
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"01110",
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"10001",
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"00001",
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"00001",
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"00001",
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"10001",
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"01110",
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"00000",
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"01111",
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"10001",
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"10001",
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"10001",
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"10001",
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"10001",
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"01111",
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"00000",
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"11111",
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"00001",
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"00001",
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"01111",
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"00001",
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"00001",
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"11111",
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"00000",
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"11111",
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"00001",
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"00001",
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"01111",
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"00001",
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"00001",
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"00001",
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"00000",
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"11110",
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"00001",
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"00001",
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"00001",
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"11001",
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"10001",
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"11110",
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"00000",
|
||||
"10001",
|
||||
"10001",
|
||||
"10001",
|
||||
"11111",
|
||||
"10001",
|
||||
"10001",
|
||||
"10001",
|
||||
"00000",
|
||||
"01110",
|
||||
"00100",
|
||||
"00100",
|
||||
"00100",
|
||||
"00100",
|
||||
"00100",
|
||||
"01110",
|
||||
"00000",
|
||||
"10000",
|
||||
"10000",
|
||||
"10000",
|
||||
"10000",
|
||||
"10000",
|
||||
"10001",
|
||||
"01110",
|
||||
"00000",
|
||||
"10001",
|
||||
"01001",
|
||||
"00101",
|
||||
"00011",
|
||||
"00101",
|
||||
"01001",
|
||||
"10001",
|
||||
"00000",
|
||||
"00001",
|
||||
"00001",
|
||||
"00001",
|
||||
"00001",
|
||||
"00001",
|
||||
"00001",
|
||||
"11111",
|
||||
"00000",
|
||||
"10001",
|
||||
"11011",
|
||||
"10101",
|
||||
"10101",
|
||||
"10001",
|
||||
"10001",
|
||||
"10001",
|
||||
"00000",
|
||||
"10001",
|
||||
"10001",
|
||||
"10011",
|
||||
"10101",
|
||||
"11001",
|
||||
"10001",
|
||||
"10001",
|
||||
"00000",
|
||||
"01110",
|
||||
"10001",
|
||||
"10001",
|
||||
"10001",
|
||||
"10001",
|
||||
"10001",
|
||||
"01110",
|
||||
"00000",
|
||||
"01111",
|
||||
"10001",
|
||||
"10001",
|
||||
"01111",
|
||||
"00001",
|
||||
"00001",
|
||||
"00001",
|
||||
"00000",
|
||||
"01110",
|
||||
"10001",
|
||||
"10001",
|
||||
"10001",
|
||||
"10101",
|
||||
"01001",
|
||||
"10110",
|
||||
"00000",
|
||||
"01111",
|
||||
"10001",
|
||||
"10001",
|
||||
"01111",
|
||||
"00101",
|
||||
"01001",
|
||||
"10001",
|
||||
"00000",
|
||||
"01110",
|
||||
"10001",
|
||||
"00001",
|
||||
"01110",
|
||||
"10000",
|
||||
"10001",
|
||||
"01110",
|
||||
"00000",
|
||||
"11111",
|
||||
"00100",
|
||||
"00100",
|
||||
"00100",
|
||||
"00100",
|
||||
"00100",
|
||||
"00100",
|
||||
"00000",
|
||||
"10001",
|
||||
"10001",
|
||||
"10001",
|
||||
"10001",
|
||||
"10001",
|
||||
"10001",
|
||||
"01110",
|
||||
"00000",
|
||||
"10001",
|
||||
"10001",
|
||||
"10001",
|
||||
"10001",
|
||||
"10001",
|
||||
"01010",
|
||||
"00100",
|
||||
"00000",
|
||||
"10001",
|
||||
"10001",
|
||||
"10001",
|
||||
"10101",
|
||||
"10101",
|
||||
"11011",
|
||||
"10001",
|
||||
"00000",
|
||||
"10001",
|
||||
"10001",
|
||||
"01010",
|
||||
"00100",
|
||||
"01010",
|
||||
"10001",
|
||||
"10001",
|
||||
"00000",
|
||||
"10001",
|
||||
"10001",
|
||||
"01010",
|
||||
"00100",
|
||||
"00100",
|
||||
"00100",
|
||||
"00100",
|
||||
"00000",
|
||||
"11111",
|
||||
"10000",
|
||||
"01000",
|
||||
"00100",
|
||||
"00010",
|
||||
"00001",
|
||||
"11111",
|
||||
"00000",
|
||||
"11111",
|
||||
"00011",
|
||||
"00011",
|
||||
"00011",
|
||||
"00011",
|
||||
"00011",
|
||||
"11111",
|
||||
"00000",
|
||||
"00000",
|
||||
"00001",
|
||||
"00010",
|
||||
"00100",
|
||||
"01000",
|
||||
"10000",
|
||||
"00000",
|
||||
"00000",
|
||||
"11111",
|
||||
"11000",
|
||||
"11000",
|
||||
"11000",
|
||||
"11000",
|
||||
"11000",
|
||||
"11111",
|
||||
"00000",
|
||||
"00000",
|
||||
"00000",
|
||||
"00100",
|
||||
"01010",
|
||||
"10001",
|
||||
"00000",
|
||||
"00000",
|
||||
"00000",
|
||||
"00000",
|
||||
"00000",
|
||||
"00000",
|
||||
"00000",
|
||||
"00000",
|
||||
"00000",
|
||||
"11111",
|
||||
"00000",
|
||||
"00000",
|
||||
"00000",
|
||||
"00000",
|
||||
"00000",
|
||||
"00000",
|
||||
"00000",
|
||||
"00000",
|
||||
"00000",
|
||||
"00100",
|
||||
"00100",
|
||||
"00100",
|
||||
"00100",
|
||||
"00100",
|
||||
"00000",
|
||||
"00100",
|
||||
"00000",
|
||||
"01010",
|
||||
"01010",
|
||||
"01010",
|
||||
"00000",
|
||||
"00000",
|
||||
"00000",
|
||||
"00000",
|
||||
"00000",
|
||||
"01010",
|
||||
"01010",
|
||||
"11111",
|
||||
"01010",
|
||||
"11111",
|
||||
"01010",
|
||||
"01010",
|
||||
"00000",
|
||||
"00100",
|
||||
"11110",
|
||||
"00101",
|
||||
"01110",
|
||||
"10100",
|
||||
"01111",
|
||||
"00100",
|
||||
"00000",
|
||||
"00011",
|
||||
"10011",
|
||||
"01000",
|
||||
"00100",
|
||||
"00010",
|
||||
"11001",
|
||||
"11000",
|
||||
"00000",
|
||||
"00010",
|
||||
"00101",
|
||||
"00101",
|
||||
"00010",
|
||||
"10101",
|
||||
"01001",
|
||||
"10110",
|
||||
"00000",
|
||||
"00100",
|
||||
"00100",
|
||||
"00100",
|
||||
"00000",
|
||||
"00000",
|
||||
"00000",
|
||||
"00000",
|
||||
"00000",
|
||||
"00100",
|
||||
"00010",
|
||||
"00001",
|
||||
"00001",
|
||||
"00001",
|
||||
"00010",
|
||||
"00100",
|
||||
"00000",
|
||||
"00100",
|
||||
"01000",
|
||||
"10000",
|
||||
"10000",
|
||||
"10000",
|
||||
"01000",
|
||||
"00100",
|
||||
"00000",
|
||||
"00100",
|
||||
"10101",
|
||||
"01110",
|
||||
"00100",
|
||||
"01110",
|
||||
"10101",
|
||||
"00100",
|
||||
"00000",
|
||||
"00000",
|
||||
"00100",
|
||||
"00100",
|
||||
"11111",
|
||||
"00100",
|
||||
"00100",
|
||||
"00000",
|
||||
"00000",
|
||||
"00000",
|
||||
"00000",
|
||||
"00000",
|
||||
"00000",
|
||||
"00100",
|
||||
"00100",
|
||||
"00010",
|
||||
"00000",
|
||||
"00000",
|
||||
"00000",
|
||||
"00000",
|
||||
"11111",
|
||||
"00000",
|
||||
"00000",
|
||||
"00000",
|
||||
"00000",
|
||||
"00000",
|
||||
"00000",
|
||||
"00000",
|
||||
"00000",
|
||||
"00000",
|
||||
"00000",
|
||||
"00100",
|
||||
"00000",
|
||||
"00000",
|
||||
"10000",
|
||||
"01000",
|
||||
"00100",
|
||||
"00010",
|
||||
"00001",
|
||||
"00000",
|
||||
"00000",
|
||||
"01110",
|
||||
"10001",
|
||||
"11001",
|
||||
"10101",
|
||||
"10011",
|
||||
"10001",
|
||||
"01110",
|
||||
"00000",
|
||||
"00100",
|
||||
"00110",
|
||||
"00100",
|
||||
"00100",
|
||||
"00100",
|
||||
"00100",
|
||||
"01110",
|
||||
"00000",
|
||||
"01110",
|
||||
"10001",
|
||||
"10000",
|
||||
"01100",
|
||||
"00010",
|
||||
"00001",
|
||||
"11111",
|
||||
"00000",
|
||||
"11111",
|
||||
"10000",
|
||||
"01000",
|
||||
"01100",
|
||||
"10000",
|
||||
"10001",
|
||||
"01110",
|
||||
"00000",
|
||||
"01000",
|
||||
"01100",
|
||||
"01010",
|
||||
"01001",
|
||||
"11111",
|
||||
"01000",
|
||||
"01000",
|
||||
"00000",
|
||||
"11111",
|
||||
"00001",
|
||||
"01111",
|
||||
"10000",
|
||||
"10000",
|
||||
"10001",
|
||||
"01110",
|
||||
"00000",
|
||||
"11100",
|
||||
"00010",
|
||||
"00001",
|
||||
"01111",
|
||||
"10001",
|
||||
"10001",
|
||||
"01110",
|
||||
"00000",
|
||||
"11111",
|
||||
"10000",
|
||||
"01000",
|
||||
"00100",
|
||||
"00010",
|
||||
"00010",
|
||||
"00010",
|
||||
"00000",
|
||||
"01110",
|
||||
"10001",
|
||||
"10001",
|
||||
"01110",
|
||||
"10001",
|
||||
"10001",
|
||||
"01110",
|
||||
"00000",
|
||||
"01110",
|
||||
"10001",
|
||||
"10001",
|
||||
"11110",
|
||||
"10000",
|
||||
"01000",
|
||||
"00111",
|
||||
"00000",
|
||||
"00000",
|
||||
"00000",
|
||||
"00100",
|
||||
"00000",
|
||||
"00100",
|
||||
"00000",
|
||||
"00000",
|
||||
"00000",
|
||||
"00000",
|
||||
"00000",
|
||||
"00100",
|
||||
"00000",
|
||||
"00100",
|
||||
"00100",
|
||||
"00010",
|
||||
"00000",
|
||||
"01000",
|
||||
"00100",
|
||||
"00010",
|
||||
"00001",
|
||||
"00010",
|
||||
"00100",
|
||||
"01000",
|
||||
"00000",
|
||||
"00000",
|
||||
"00000",
|
||||
"11111",
|
||||
"00000",
|
||||
"11111",
|
||||
"00000",
|
||||
"00000",
|
||||
"00000",
|
||||
"00010",
|
||||
"00100",
|
||||
"01000",
|
||||
"10000",
|
||||
"01000",
|
||||
"00100",
|
||||
"00010",
|
||||
"00000",
|
||||
"01110",
|
||||
"10001",
|
||||
"01000",
|
||||
"00100",
|
||||
"00100",
|
||||
"00000",
|
||||
"00100",
|
||||
"00000");
|
||||
|
||||
begin
|
||||
|
||||
process (clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
dout <= ROM(TO_INTEGER(addr));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end rtl;
|
291
src/cpu/t65/T65_ALU.vhd
Normal file
291
src/cpu/t65/T65_ALU.vhd
Normal file
@ -0,0 +1,291 @@
|
||||
-- ****
|
||||
-- T65(b) core. In an effort to merge and maintain bug fixes ....
|
||||
--
|
||||
-- See list of changes in T65 top file (T65.vhd)...
|
||||
--
|
||||
-- ****
|
||||
-- 65xx compatible microprocessor core
|
||||
--
|
||||
-- FPGAARCADE SVN: $Id: T65_ALU.vhd 1234 2015-02-28 20:14:50Z wolfgang.scherr $
|
||||
--
|
||||
-- Copyright (c) 2002...2015
|
||||
-- Daniel Wallner (jesus <at> opencores <dot> org)
|
||||
-- Mike Johnson (mikej <at> fpgaarcade <dot> com)
|
||||
-- Wolfgang Scherr (WoS <at> pin4 <dot> at>
|
||||
-- Morten Leikvoll ()
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- Please report bugs to the author(s), but before you do so, please
|
||||
-- make sure that this is not a derivative work and that
|
||||
-- you have the latest version of this file.
|
||||
--
|
||||
-- Limitations :
|
||||
-- See in T65 top file (T65.vhd)...
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
use IEEE.numeric_std.all;
|
||||
use work.T65_Pack.all;
|
||||
|
||||
entity T65_ALU is
|
||||
port(
|
||||
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816
|
||||
Op : in T_ALU_OP;
|
||||
BusA : in std_logic_vector(7 downto 0);
|
||||
BusB : in std_logic_vector(7 downto 0);
|
||||
P_In : in std_logic_vector(7 downto 0);
|
||||
P_Out : out std_logic_vector(7 downto 0);
|
||||
Q : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end T65_ALU;
|
||||
|
||||
architecture rtl of T65_ALU is
|
||||
|
||||
-- AddSub variables (temporary signals)
|
||||
signal ADC_Z : std_logic;
|
||||
signal ADC_C : std_logic;
|
||||
signal ADC_V : std_logic;
|
||||
signal ADC_N : std_logic;
|
||||
signal ADC_Q : std_logic_vector(7 downto 0);
|
||||
signal SBC_Z : std_logic;
|
||||
signal SBC_C : std_logic;
|
||||
signal SBC_V : std_logic;
|
||||
signal SBC_N : std_logic;
|
||||
signal SBC_Q : std_logic_vector(7 downto 0);
|
||||
signal SBX_Q : std_logic_vector(7 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
process (P_In, BusA, BusB)
|
||||
variable AL : unsigned(6 downto 0);
|
||||
variable AH : unsigned(6 downto 0);
|
||||
variable C : std_logic;
|
||||
begin
|
||||
AL := resize(unsigned(BusA(3 downto 0) & P_In(Flag_C)), 7) + resize(unsigned(BusB(3 downto 0) & "1"), 7);
|
||||
AH := resize(unsigned(BusA(7 downto 4) & AL(5)), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7);
|
||||
|
||||
-- pragma translate_off
|
||||
if is_x(std_logic_vector(AL)) then AL := "0000000"; end if;
|
||||
if is_x(std_logic_vector(AH)) then AH := "0000000"; end if;
|
||||
-- pragma translate_on
|
||||
|
||||
if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then
|
||||
ADC_Z <= '1';
|
||||
else
|
||||
ADC_Z <= '0';
|
||||
end if;
|
||||
|
||||
if AL(5 downto 1) > 9 and P_In(Flag_D) = '1' then
|
||||
AL(6 downto 1) := AL(6 downto 1) + 6;
|
||||
end if;
|
||||
|
||||
C := AL(6) or AL(5);
|
||||
AH := resize(unsigned(BusA(7 downto 4) & C), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7);
|
||||
|
||||
ADC_N <= AH(4);
|
||||
ADC_V <= (AH(4) xor BusA(7)) and not (BusA(7) xor BusB(7));
|
||||
|
||||
-- pragma translate_off
|
||||
if is_x(std_logic_vector(AH)) then AH := "0000000"; end if;
|
||||
-- pragma translate_on
|
||||
|
||||
if AH(5 downto 1) > 9 and P_In(Flag_D) = '1' then
|
||||
AH(6 downto 1) := AH(6 downto 1) + 6;
|
||||
end if;
|
||||
|
||||
ADC_C <= AH(6) or AH(5);
|
||||
|
||||
ADC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));
|
||||
end process;
|
||||
|
||||
process (Op, P_In, BusA, BusB)
|
||||
variable AL : unsigned(6 downto 0);
|
||||
variable AH : unsigned(5 downto 0);
|
||||
variable C : std_logic;
|
||||
variable CT : std_logic;
|
||||
begin
|
||||
CT:='0';
|
||||
if( Op=ALU_OP_AND or --"0001" These OpCodes used to have LSB set
|
||||
Op=ALU_OP_ADC or --"0011"
|
||||
Op=ALU_OP_EQ2 or --"0101"
|
||||
Op=ALU_OP_SBC or --"0111"
|
||||
Op=ALU_OP_ROL or --"1001"
|
||||
Op=ALU_OP_ROR or --"1011"
|
||||
-- Op=ALU_OP_EQ3 or --"1101"
|
||||
Op=ALU_OP_INC --"1111"
|
||||
) then
|
||||
CT:='1';
|
||||
end if;
|
||||
|
||||
C := P_In(Flag_C) or not CT;--was: or not Op(0);
|
||||
AL := resize(unsigned(BusA(3 downto 0) & C), 7) - resize(unsigned(BusB(3 downto 0) & "1"), 6);
|
||||
AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(5)), 6);
|
||||
|
||||
-- pragma translate_off
|
||||
if is_x(std_logic_vector(AL)) then AL := "0000000"; end if;
|
||||
if is_x(std_logic_vector(AH)) then AH := "000000"; end if;
|
||||
-- pragma translate_on
|
||||
|
||||
if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then
|
||||
SBC_Z <= '1';
|
||||
else
|
||||
SBC_Z <= '0';
|
||||
end if;
|
||||
|
||||
SBC_C <= not AH(5);
|
||||
SBC_V <= (AH(4) xor BusA(7)) and (BusA(7) xor BusB(7));
|
||||
SBC_N <= AH(4);
|
||||
|
||||
SBX_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));
|
||||
|
||||
if P_In(Flag_D) = '1' then
|
||||
if AL(5) = '1' then
|
||||
AL(5 downto 1) := AL(5 downto 1) - 6;
|
||||
end if;
|
||||
AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(6)), 6);
|
||||
if AH(5) = '1' then
|
||||
AH(5 downto 1) := AH(5 downto 1) - 6;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
SBC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));
|
||||
end process;
|
||||
|
||||
process (Op, P_In, BusA, BusB,
|
||||
ADC_Z, ADC_C, ADC_V, ADC_N, ADC_Q,
|
||||
SBC_Z, SBC_C, SBC_V, SBC_N, SBC_Q)
|
||||
variable Q_t : std_logic_vector(7 downto 0);
|
||||
variable Q2_t : std_logic_vector(7 downto 0);
|
||||
begin
|
||||
-- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC
|
||||
-- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC
|
||||
P_Out <= P_In;
|
||||
Q_t := BusA;
|
||||
case Op is
|
||||
when ALU_OP_OR=>
|
||||
Q_t := BusA or BusB;
|
||||
when ALU_OP_AND=>
|
||||
Q_t := BusA and BusB;
|
||||
when ALU_OP_EOR=>
|
||||
Q_t := BusA xor BusB;
|
||||
when ALU_OP_ADC=>
|
||||
P_Out(Flag_V) <= ADC_V;
|
||||
P_Out(Flag_C) <= ADC_C;
|
||||
Q_t := ADC_Q;
|
||||
when ALU_OP_CMP=>
|
||||
P_Out(Flag_C) <= SBC_C;
|
||||
when ALU_OP_SAX=>
|
||||
P_Out(Flag_C) <= SBC_C;
|
||||
Q_t := SBX_Q; -- undoc: subtract (A & X) - (immediate)
|
||||
when ALU_OP_SBC=>
|
||||
P_Out(Flag_V) <= SBC_V;
|
||||
P_Out(Flag_C) <= SBC_C;
|
||||
Q_t := SBC_Q; -- undoc: subtract (A & X) - (immediate), then decimal correction
|
||||
when ALU_OP_ASL=>
|
||||
Q_t := BusA(6 downto 0) & "0";
|
||||
P_Out(Flag_C) <= BusA(7);
|
||||
when ALU_OP_ROL=>
|
||||
Q_t := BusA(6 downto 0) & P_In(Flag_C);
|
||||
P_Out(Flag_C) <= BusA(7);
|
||||
when ALU_OP_LSR=>
|
||||
Q_t := "0" & BusA(7 downto 1);
|
||||
P_Out(Flag_C) <= BusA(0);
|
||||
when ALU_OP_ROR=>
|
||||
Q_t := P_In(Flag_C) & BusA(7 downto 1);
|
||||
P_Out(Flag_C) <= BusA(0);
|
||||
when ALU_OP_ARR=>
|
||||
Q_t := P_In(Flag_C) & (BusA(7 downto 1) and BusB(7 downto 1));
|
||||
P_Out(Flag_V) <= Q_t(5) xor Q_t(6);
|
||||
Q2_t := Q_t;
|
||||
if P_In(Flag_D)='1' then
|
||||
if (BusA(3 downto 0) and BusB(3 downto 0)) > "0100" then
|
||||
Q2_t(3 downto 0) := std_logic_vector(unsigned(Q_t(3 downto 0)) + x"6");
|
||||
end if;
|
||||
if (BusA(7 downto 4) and BusB(7 downto 4)) > "0100" then
|
||||
Q2_t(7 downto 4) := std_logic_vector(unsigned(Q_t(7 downto 4)) + x"6");
|
||||
P_Out(Flag_C) <= '1';
|
||||
else
|
||||
P_Out(Flag_C) <= '0';
|
||||
end if;
|
||||
else
|
||||
P_Out(Flag_C) <= Q_t(6);
|
||||
end if;
|
||||
when ALU_OP_BIT=>
|
||||
P_Out(Flag_V) <= BusB(6);
|
||||
when ALU_OP_DEC=>
|
||||
Q_t := std_logic_vector(unsigned(BusA) - 1);
|
||||
when ALU_OP_INC=>
|
||||
Q_t := std_logic_vector(unsigned(BusA) + 1);
|
||||
when others =>
|
||||
null;
|
||||
--EQ1,EQ2,EQ3 passes BusA to Q_t and P_in to P_out
|
||||
end case;
|
||||
|
||||
case Op is
|
||||
when ALU_OP_ADC=>
|
||||
P_Out(Flag_N) <= ADC_N;
|
||||
P_Out(Flag_Z) <= ADC_Z;
|
||||
when ALU_OP_CMP|ALU_OP_SBC|ALU_OP_SAX=>
|
||||
P_Out(Flag_N) <= SBC_N;
|
||||
P_Out(Flag_Z) <= SBC_Z;
|
||||
when ALU_OP_EQ1=>--dont touch P
|
||||
when ALU_OP_BIT=>
|
||||
P_Out(Flag_N) <= BusB(7);
|
||||
if (BusA and BusB) = "00000000" then
|
||||
P_Out(Flag_Z) <= '1';
|
||||
else
|
||||
P_Out(Flag_Z) <= '0';
|
||||
end if;
|
||||
when ALU_OP_ANC=>
|
||||
P_Out(Flag_N) <= Q_t(7);
|
||||
P_Out(Flag_C) <= Q_t(7);
|
||||
if Q_t = "00000000" then
|
||||
P_Out(Flag_Z) <= '1';
|
||||
else
|
||||
P_Out(Flag_Z) <= '0';
|
||||
end if;
|
||||
when others =>
|
||||
P_Out(Flag_N) <= Q_t(7);
|
||||
if Q_t = "00000000" then
|
||||
P_Out(Flag_Z) <= '1';
|
||||
else
|
||||
P_Out(Flag_Z) <= '0';
|
||||
end if;
|
||||
end case;
|
||||
|
||||
if Op=ALU_OP_ARR then
|
||||
-- handled above in ARR code
|
||||
Q <= Q2_t;
|
||||
else
|
||||
Q <= Q_t;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end;
|
1239
src/cpu/t65/T65_MCode.vhd
Normal file
1239
src/cpu/t65/T65_MCode.vhd
Normal file
File diff suppressed because it is too large
Load Diff
180
src/cpu/t65/T65_Pack.vhd
Normal file
180
src/cpu/t65/T65_Pack.vhd
Normal file
@ -0,0 +1,180 @@
|
||||
-- ****
|
||||
-- T65(b) core. In an effort to merge and maintain bug fixes ....
|
||||
--
|
||||
-- See list of changes in T65 top file (T65.vhd)...
|
||||
--
|
||||
-- ****
|
||||
-- 65xx compatible microprocessor core
|
||||
--
|
||||
-- FPGAARCADE SVN: $Id: T65_Pack.vhd 1234 2015-02-28 20:14:50Z wolfgang.scherr $
|
||||
--
|
||||
-- Copyright (c) 2002...2015
|
||||
-- Daniel Wallner (jesus <at> opencores <dot> org)
|
||||
-- Mike Johnson (mikej <at> fpgaarcade <dot> com)
|
||||
-- Wolfgang Scherr (WoS <at> pin4 <dot> at>
|
||||
-- Morten Leikvoll ()
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- Please report bugs to the author(s), but before you do so, please
|
||||
-- make sure that this is not a derivative work and that
|
||||
-- you have the latest version of this file.
|
||||
--
|
||||
-- Limitations :
|
||||
-- See in T65 top file (T65.vhd)...
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
|
||||
package T65_Pack is
|
||||
|
||||
constant Flag_C : integer := 0;
|
||||
constant Flag_Z : integer := 1;
|
||||
constant Flag_I : integer := 2;
|
||||
constant Flag_D : integer := 3;
|
||||
constant Flag_B : integer := 4;
|
||||
constant Flag_1 : integer := 5;
|
||||
constant Flag_V : integer := 6;
|
||||
constant Flag_N : integer := 7;
|
||||
|
||||
subtype T_Lcycle is std_logic_vector(2 downto 0);
|
||||
constant Cycle_sync :T_Lcycle:="000";
|
||||
constant Cycle_1 :T_Lcycle:="001";
|
||||
constant Cycle_2 :T_Lcycle:="010";
|
||||
constant Cycle_3 :T_Lcycle:="011";
|
||||
constant Cycle_4 :T_Lcycle:="100";
|
||||
constant Cycle_5 :T_Lcycle:="101";
|
||||
constant Cycle_6 :T_Lcycle:="110";
|
||||
constant Cycle_7 :T_Lcycle:="111";
|
||||
|
||||
function CycleNext(c:T_Lcycle) return T_Lcycle;
|
||||
|
||||
type T_Set_BusA_To is
|
||||
(
|
||||
Set_BusA_To_DI,
|
||||
Set_BusA_To_ABC,
|
||||
Set_BusA_To_X,
|
||||
Set_BusA_To_Y,
|
||||
Set_BusA_To_S,
|
||||
Set_BusA_To_P,
|
||||
Set_BusA_To_DA,
|
||||
Set_BusA_To_DAO,
|
||||
Set_BusA_To_DAX,
|
||||
Set_BusA_To_AAX,
|
||||
Set_BusA_To_DONTCARE
|
||||
);
|
||||
|
||||
type T_Set_Addr_To is
|
||||
(
|
||||
Set_Addr_To_SP,
|
||||
Set_Addr_To_ZPG,
|
||||
Set_Addr_To_PBR,
|
||||
Set_Addr_To_BA
|
||||
);
|
||||
|
||||
type T_Write_Data is
|
||||
(
|
||||
Write_Data_DL,
|
||||
Write_Data_ABC,
|
||||
Write_Data_X,
|
||||
Write_Data_Y,
|
||||
Write_Data_S,
|
||||
Write_Data_P,
|
||||
Write_Data_PCL,
|
||||
Write_Data_PCH,
|
||||
Write_Data_AX,
|
||||
Write_Data_AXB,
|
||||
Write_Data_XB,
|
||||
Write_Data_YB,
|
||||
Write_Data_DONTCARE
|
||||
);
|
||||
|
||||
type T_ALU_OP is
|
||||
(
|
||||
ALU_OP_OR, --"0000"
|
||||
ALU_OP_AND, --"0001"
|
||||
ALU_OP_EOR, --"0010"
|
||||
ALU_OP_ADC, --"0011"
|
||||
ALU_OP_EQ1, --"0100" EQ1 does not change N,Z flags, EQ2/3 does.
|
||||
ALU_OP_EQ2, --"0101" Not sure yet whats the difference between EQ2&3. They seem to do the same ALU op
|
||||
ALU_OP_CMP, --"0110"
|
||||
ALU_OP_SBC, --"0111"
|
||||
ALU_OP_ASL, --"1000"
|
||||
ALU_OP_ROL, --"1001"
|
||||
ALU_OP_LSR, --"1010"
|
||||
ALU_OP_ROR, --"1011"
|
||||
ALU_OP_BIT, --"1100"
|
||||
-- ALU_OP_EQ3, --"1101"
|
||||
ALU_OP_DEC, --"1110"
|
||||
ALU_OP_INC, --"1111"
|
||||
ALU_OP_ARR,
|
||||
ALU_OP_ANC,
|
||||
ALU_OP_SAX,
|
||||
ALU_OP_XAA
|
||||
-- ALU_OP_UNDEF--"----"--may be replaced with any?
|
||||
);
|
||||
|
||||
type T_t65_dbg is record
|
||||
I : std_logic_vector(7 downto 0); -- instruction
|
||||
A : std_logic_vector(7 downto 0); -- A reg
|
||||
X : std_logic_vector(7 downto 0); -- X reg
|
||||
Y : std_logic_vector(7 downto 0); -- Y reg
|
||||
S : std_logic_vector(7 downto 0); -- stack pointer
|
||||
P : std_logic_vector(7 downto 0); -- processor flags
|
||||
end record;
|
||||
|
||||
end;
|
||||
|
||||
package body T65_Pack is
|
||||
|
||||
function CycleNext(c:T_Lcycle) return T_Lcycle is
|
||||
begin
|
||||
case(c) is
|
||||
when Cycle_sync=>
|
||||
return Cycle_1;
|
||||
when Cycle_1=>
|
||||
return Cycle_2;
|
||||
when Cycle_2=>
|
||||
return Cycle_3;
|
||||
when Cycle_3=>
|
||||
return Cycle_4;
|
||||
when Cycle_4=>
|
||||
return Cycle_5;
|
||||
when Cycle_5=>
|
||||
return Cycle_6;
|
||||
when Cycle_6=>
|
||||
return Cycle_7;
|
||||
when Cycle_7=>
|
||||
return Cycle_sync;
|
||||
when others=>
|
||||
return Cycle_sync;
|
||||
end case;
|
||||
end CycleNext;
|
||||
|
||||
end T65_Pack;
|
Loading…
x
Reference in New Issue
Block a user