63 lines
1.3 KiB
VHDL
63 lines
1.3 KiB
VHDL
-- (C) Rui T. Sousa from http://sweet.ua.pt/~a16360
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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entity Keyboard is
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port (
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Reset : in std_logic;
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Clock : in std_logic;
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PS2Clock : inout std_logic;
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PS2Data : inout std_logic;
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CodeReady : out std_logic;
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ScanCode : out std_logic_vector(9 downto 0)
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);
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end Keyboard;
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architecture Behavioral of Keyboard is
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signal Send : std_logic;
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signal Command : std_logic_vector(7 downto 0);
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signal PS2Busy : std_logic;
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signal PS2Error : std_logic;
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signal DataReady : std_logic;
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signal DataByte : std_logic_vector(7 downto 0);
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begin
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PS2_Controller: entity work.PS2Controller
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generic map(
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clk_freq => 14 -- 14 MHz clock
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)
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port map (
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Reset => Reset,
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Clock => Clock,
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PS2Clock => PS2Clock,
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PS2Data => PS2Data,
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Send => Send,
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Command => Command,
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PS2Busy => PS2Busy,
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PS2Error => PS2Error,
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DataReady => DataReady,
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DataByte => DataByte
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);
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Keyboard_Mapper: entity work.KeyboardMapper
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port map (
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Clock => Clock,
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Reset => Reset,
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PS2Busy => PS2Busy,
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PS2Error => PS2Error,
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DataReady => DataReady,
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DataByte => DataByte,
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Send => Send,
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Command => Command,
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CodeReady => CodeReady,
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ScanCode => ScanCode
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);
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end Behavioral;
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