180 lines
5.3 KiB
VHDL
180 lines
5.3 KiB
VHDL
-- ****
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-- T65(b) core. In an effort to merge and maintain bug fixes ....
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--
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-- See list of changes in T65 top file (T65.vhd)...
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--
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-- ****
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-- 65xx compatible microprocessor core
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--
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-- FPGAARCADE SVN: $Id: T65_Pack.vhd 1234 2015-02-28 20:14:50Z wolfgang.scherr $
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--
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-- Copyright (c) 2002...2015
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-- Daniel Wallner (jesus <at> opencores <dot> org)
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-- Mike Johnson (mikej <at> fpgaarcade <dot> com)
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-- Wolfgang Scherr (WoS <at> pin4 <dot> at>
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-- Morten Leikvoll ()
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--
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-- All rights reserved
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--
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-- Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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--
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-- Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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-- Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- Please report bugs to the author(s), but before you do so, please
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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--
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-- Limitations :
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-- See in T65 top file (T65.vhd)...
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library IEEE;
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use IEEE.std_logic_1164.all;
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package T65_Pack is
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constant Flag_C : integer := 0;
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constant Flag_Z : integer := 1;
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constant Flag_I : integer := 2;
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constant Flag_D : integer := 3;
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constant Flag_B : integer := 4;
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constant Flag_1 : integer := 5;
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constant Flag_V : integer := 6;
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constant Flag_N : integer := 7;
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subtype T_Lcycle is std_logic_vector(2 downto 0);
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constant Cycle_sync :T_Lcycle:="000";
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constant Cycle_1 :T_Lcycle:="001";
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constant Cycle_2 :T_Lcycle:="010";
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constant Cycle_3 :T_Lcycle:="011";
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constant Cycle_4 :T_Lcycle:="100";
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constant Cycle_5 :T_Lcycle:="101";
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constant Cycle_6 :T_Lcycle:="110";
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constant Cycle_7 :T_Lcycle:="111";
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function CycleNext(c:T_Lcycle) return T_Lcycle;
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type T_Set_BusA_To is
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(
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Set_BusA_To_DI,
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Set_BusA_To_ABC,
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Set_BusA_To_X,
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Set_BusA_To_Y,
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Set_BusA_To_S,
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Set_BusA_To_P,
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Set_BusA_To_DA,
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Set_BusA_To_DAO,
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Set_BusA_To_DAX,
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Set_BusA_To_AAX,
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Set_BusA_To_DONTCARE
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);
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type T_Set_Addr_To is
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(
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Set_Addr_To_SP,
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Set_Addr_To_ZPG,
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Set_Addr_To_PBR,
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Set_Addr_To_BA
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);
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type T_Write_Data is
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(
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Write_Data_DL,
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Write_Data_ABC,
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Write_Data_X,
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Write_Data_Y,
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Write_Data_S,
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Write_Data_P,
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Write_Data_PCL,
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Write_Data_PCH,
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Write_Data_AX,
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Write_Data_AXB,
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Write_Data_XB,
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Write_Data_YB,
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Write_Data_DONTCARE
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);
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type T_ALU_OP is
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(
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ALU_OP_OR, --"0000"
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ALU_OP_AND, --"0001"
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ALU_OP_EOR, --"0010"
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ALU_OP_ADC, --"0011"
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ALU_OP_EQ1, --"0100" EQ1 does not change N,Z flags, EQ2/3 does.
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ALU_OP_EQ2, --"0101" Not sure yet whats the difference between EQ2&3. They seem to do the same ALU op
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ALU_OP_CMP, --"0110"
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ALU_OP_SBC, --"0111"
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ALU_OP_ASL, --"1000"
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ALU_OP_ROL, --"1001"
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ALU_OP_LSR, --"1010"
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ALU_OP_ROR, --"1011"
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ALU_OP_BIT, --"1100"
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-- ALU_OP_EQ3, --"1101"
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ALU_OP_DEC, --"1110"
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ALU_OP_INC, --"1111"
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ALU_OP_ARR,
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ALU_OP_ANC,
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ALU_OP_SAX,
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ALU_OP_XAA
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-- ALU_OP_UNDEF--"----"--may be replaced with any?
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);
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type T_t65_dbg is record
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I : std_logic_vector(7 downto 0); -- instruction
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A : std_logic_vector(7 downto 0); -- A reg
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X : std_logic_vector(7 downto 0); -- X reg
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Y : std_logic_vector(7 downto 0); -- Y reg
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S : std_logic_vector(7 downto 0); -- stack pointer
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P : std_logic_vector(7 downto 0); -- processor flags
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end record;
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end;
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package body T65_Pack is
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function CycleNext(c:T_Lcycle) return T_Lcycle is
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begin
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case(c) is
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when Cycle_sync=>
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return Cycle_1;
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when Cycle_1=>
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return Cycle_2;
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when Cycle_2=>
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return Cycle_3;
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when Cycle_3=>
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return Cycle_4;
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when Cycle_4=>
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return Cycle_5;
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when Cycle_5=>
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return Cycle_6;
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when Cycle_6=>
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return Cycle_7;
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when Cycle_7=>
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return Cycle_sync;
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when others=>
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return Cycle_sync;
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end case;
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end CycleNext;
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end T65_Pack; |