205 lines
13 KiB
VHDL
205 lines
13 KiB
VHDL
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-- Author: Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com
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--
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-- Create Date: 09:56:30 07/06/2011
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-- Module Name: grp_debouncer - RTL
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-- Project Name: basic functions
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-- Target Devices: Spartan-6
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-- Tool versions: ISE 13.1
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-- Description:
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--
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-- This block is a generic multiple input debouncing circuit.
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-- It handles multiple inputs, like mechanical switch inputs, and outputs a debounced, stable registered version of the inputs.
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-- A 'new_data' one-cycle strobe is also available, to sync downstream logic.
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--
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-- CONCEPTUAL CIRCUIT
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-- ==================
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--
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-- W
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-- /----------------/----------------\
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-- | |
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-- | |
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-- | ______ ______ | _____
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-- | W | | W |fdr | W | W |cmp \
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-- \----/---| +1 |---/----| |--/--+----/----| \
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-- | | | | | \
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-- ------ | | \ |
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-- | | | = |-----\
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-- |> R | / | |
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-- ---+-- | / |
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-- | CNT_VAL---| / |
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-- | |____/ |
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-- | |
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-- \------------\ |
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-- | |
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-- N ____ | |
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-- /-------/---)) \ ____ | |
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-- | ))XOR |-----) \ | |
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-- | /------))___/ )OR |-----/ |
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-- | | /---)___/ |
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-- | | | |
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-- | | \----------\ |
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-- | | N | |
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-- | \--------/-----------\ +----------------------+---------\
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-- | | | |
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-- \---\ | | |
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-- ______ | ______ | | ______ |
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-- | fd | | | fd | | | |fde | |
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-- [data_i]----/-----| |---/---+---/----| |---/---+----)---| |---/---+---/-----------)------------------------[data_o]
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-- N | | N N | | N | | | | N | N |
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-- | | | | | \---|CE | | |
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-- | | | | | | | | |
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-- [clk_i]----> |> | |> | | |> | | | ____ ______
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-- ------ ------ | ------ | N ____ \---| \ | fd |
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-- | \---/---)) \ |AND |-----| |----[strb_o]
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-- | ))XOR |-----|___/ | |
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-- \-------------------------/---))___/ | |
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-- N | |
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-- |> |
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-- ------
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--
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--
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-- PIPELINE LOGIC
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-- ==============
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--
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-- This debouncer circuit detects edges in an input signal, and waits the signal to stabilize for the designated time
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-- before transferring the stable signal to the registered output.
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-- A one-clock-cyle strobe is pulsed at the output to signalize a new data available.
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-- The core clock should be the system clock, to optimize use of global clock resources.
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--
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-- GROUP DEBOUNCING
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-- ================
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--
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-- A change in state in any bit in the input word causes reload of the delay counter, and the output word is updated only
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-- when all bits are stable for the specified period. Therefore, the grouping of signals and delay selection should match
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-- behaviour of the selected signals.
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--
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-- RESOURCES USED
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-- ==============
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--
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-- The number of registers inferred is: 3*N + (LOG(CNT_VAL)/LOG(2)) + 1 registers.
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-- The number of LUTs inferred is roughly: ((4*N+2)/6)+2.
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-- The slice distribution will vary, and depends on the control set restrictions and LUT-FF pairs resulting from map+p&r.
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--
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-- This design was originally targeted to a Spartan-6 platform, synthesized with XST and normal constraints.
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-- Verification in silicon was done on a Digilent Atlys board with a Spartan-6 FPGA @100MHz clock.
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-- The VHDL dialect used is VHDL'93, accepted largely by all synthesis tools.
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--
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------------------------------ COPYRIGHT NOTICE -----------------------------------------------------------------------
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--
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--
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-- Author(s): Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com
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--
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-- Copyright (C) 2011 Jonny Doin
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-- -----------------------------
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--
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-- This source file may be used and distributed without restriction provided that this copyright statement is not
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-- removed from the file and that any derivative work contains the original copyright notice and the associated
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-- disclaimer.
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--
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-- This source file is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser
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-- General Public License as published by the Free Software Foundation; either version 2.1 of the License, or
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-- (at your option) any later version.
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--
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-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
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-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more
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-- details.
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--
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-- You should have received a copy of the GNU Lesser General Public License along with this source; if not, download
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-- it from http://www.gnu.org/licenses/lgpl.txt
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--
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------------------------------ REVISION HISTORY -----------------------------------------------------------------------
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--
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-- 2011/07/06 v0.01.0010 [JD] started development. verification of synthesis circuit inference.
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-- 2011/07/07 v1.00.0020 [JD] verification in silicon. operation at 100MHz, tested on the Atlys board (Spartan-6 LX45).
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-- 2011/08/10 v1.01.0025 [JD] added one pipeline delay to new data strobe output.
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-- 2011/09/19 v1.01.0030 [JD] changed range for internal counter (cnt_reg, cnt_next) to avoid adder flipover (Altera/ModelSim).
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--
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-----------------------------------------------------------------------------------------------------------------------
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-- TODO
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-- ====
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--
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-- The circuit can easily be extended to have a signature of which inputs changed at the data out port.
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--
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-----------------------------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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entity grp_debouncer is
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Generic (
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N : positive := 8; -- input bus width
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CNT_VAL : positive := 10000); -- clock counts for debounce period
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Port (
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clk_i : in std_logic := 'X'; -- system clock
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data_i : in std_logic_vector (N-1 downto 0) := (others => 'X'); -- noisy input data
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data_o : out std_logic_vector (N-1 downto 0); -- registered stable output data
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strb_o : out std_logic -- strobe for new data available
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);
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end grp_debouncer;
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architecture rtl of grp_debouncer is
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-- datapath pipeline
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signal reg_A, reg_B : std_logic_vector (N-1 downto 0) := (others => '0'); -- debounce edge detectors
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signal reg_out : std_logic_vector (N-1 downto 0) := (others => '0'); -- registered output
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signal dat_strb : std_logic := '0'; -- data transfer strobe
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signal strb_reg : std_logic := '0'; -- registered strobe
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signal strb_next : std_logic := '0'; -- lookahead strobe
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signal dat_diff : std_logic := '0'; -- edge detector
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-- debounce counter
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signal cnt_reg : integer range CNT_VAL + 1 downto 0 := 0; -- debounce period counter
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signal cnt_next : integer range CNT_VAL + 1 downto 0 := 0; -- combinatorial signal
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begin
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--=============================================================================================
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-- DEBOUNCE COUNTER LOGIC
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--=============================================================================================
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-- This counter is implemented as a up-counter with reset and final count detection via compare,
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-- instead of a down-counter with preset and final count detection via nonzero detection.
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-- This is better for Spartan-6 and Virtex-6 CLB architecture, because it uses less control sets.
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--
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-- cnt_reg register transfer logic
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cnt_reg_proc: process (clk_i) is
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begin
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if clk_i'event and clk_i = '1' then
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cnt_reg <= cnt_next;
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end if;
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end process cnt_reg_proc;
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-- cnt_next combinatorial logic
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cnt_next_proc: cnt_next <= 0 when dat_diff = '1' or dat_strb = '1' else cnt_reg + 1;
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-- final count combinatorial logic
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final_cnt_proc: dat_strb <= '1' when cnt_reg = CNT_VAL else '0';
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--=============================================================================================
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-- DATAPATH SIGNAL PIPELINE
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--=============================================================================================
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-- input pipeline logic
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pipeline_proc: process (clk_i) is
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begin
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if clk_i'event and clk_i = '1' then
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-- edge detection pipeline
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reg_A <= data_i;
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reg_B <= reg_A;
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-- new data strobe pipeline delay
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strb_reg <= strb_next;
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end if;
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-- output data pipeline
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if clk_i'event and clk_i = '1' then
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if dat_strb = '1' then
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reg_out <= reg_B;
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end if;
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end if;
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end process pipeline_proc;
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-- edge detector
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edge_detector_proc: dat_diff <= '1' when reg_A /= reg_B else '0';
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-- lookahead new data strobe
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next_strobe_proc: strb_next <= '1' when ((reg_out /= reg_B) and dat_strb = '1') else '0';
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--=============================================================================================
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-- OUTPUT LOGIC
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--=============================================================================================
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-- connect output ports
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data_o_proc: data_o <= reg_out;
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strb_o_proc: strb_o <= strb_reg;
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end rtl;
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