164 lines
4.7 KiB
VHDL
164 lines
4.7 KiB
VHDL
-- TestBench Template
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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ENTITY apple2_papilio_tb IS
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END apple2_papilio_tb;
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ARCHITECTURE behavior OF apple2_papilio_tb IS
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-- Component Declaration
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COMPONENT apple2_papilio
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port (
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-- Clocks
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CLK : in std_logic; -- 32 MHz
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RESET_I : in std_logic; -- reset positiv
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-- SRAM
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SRAM_DQ : inout unsigned(7 downto 0); -- Data bus 8 Bits
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SRAM_ADDR : out unsigned(20 downto 0); -- Address bus 21 Bits
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SRAM_WE_N, -- Write Enable
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SRAM_CE_N, -- Chip Enable
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SRAM_OE_N : out std_logic; -- Output Enable
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-- SD card interface
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SD_DAT : in std_logic; -- SD Card Data SD pin 7 "DAT 0/DataOut"
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SD_DAT3 : out std_logic; -- SD Card Data 3 SD pin 1 "DAT 3/nCS"
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SD_CMD : out std_logic; -- SD Card Command SD pin 2 "CMD/DataIn"
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SD_CLK : out std_logic; -- SD Card Clock SD pin 5 "CLK"
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-- Led
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LED : out std_logic_vector(3 downto 0);
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-- PS/2 port
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PS2_DAT, -- Data
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PS2_CLK : inout std_logic; -- Clock
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O_AUDIO_L : out std_logic; -- Audio out
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O_AUDIO_R : out std_logic; -- Ausdio out
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-- VGA output
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VGA_HS, -- H_SYNC
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VGA_VS : out std_logic; -- V_SYNC
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VGA_R, -- Red[3:0]
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VGA_G, -- Green[3:0]
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VGA_B : out unsigned(3 downto 0) -- Blue[3:0]
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);
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END COMPONENT;
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signal CLK_32M : std_logic;
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signal RESET_I : std_logic := '0'; -- reset positiv
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-- SRAM
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signal SRAM_DQ : unsigned(7 downto 0); -- Data bus 8 Bits
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signal SRAM_ADDR : unsigned(20 downto 0); -- Address bus 21 Bits
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signal SRAM_WE_N, -- Write Enable
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SRAM_CE_N, -- Chip Enable
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SRAM_OE_N : std_logic; -- Output Enable
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-- SD card interface
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signal SD_DAT : std_logic; -- SD Card Data SD pin 7 "DAT 0/DataOut"
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signal SD_DAT3 : std_logic; -- SD Card Data 3 SD pin 1 "DAT 3/nCS"
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signal SD_CMD : std_logic; -- SD Card Command SD pin 2 "CMD/DataIn"
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signal SD_CLK : std_logic; -- SD Card Clock SD pin 5 "CLK"
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-- Led
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signal LED : std_logic_vector(3 downto 0);
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-- PS/2 port
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signal PS2_DAT, -- Data
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PS2_CLK : std_logic; -- Clock
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signal O_AUDIO_L : std_logic; -- Audio out
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signal O_AUDIO_R : std_logic; -- Ausdio out
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-- VGA output
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signal VGA_HS, -- H_SYNC
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VGA_VS : std_logic; -- V_SYNC
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signal VGA_R, -- Red[3:0]
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VGA_G, -- Green[3:0]
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VGA_B : unsigned(3 downto 0); -- Blue[3:0]
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-- Clock period definitions
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constant CLK_32M_period : time := 32.25 ns;
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BEGIN
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-- Component Instantiation
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uut:apple2_papilio PORT MAP(
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-- Clocks
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CLK => CLK_32M, -- 32 MHz
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RESET_I => RESET_I, -- reset positiv
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-- SRAM
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SRAM_DQ => SRAM_DQ, -- Data bus 8 Bits
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SRAM_ADDR => SRAM_ADDR, -- Address bus 21 Bits
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SRAM_WE_N => SRAM_WE_N, -- Write Enable
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SRAM_CE_N => SRAM_CE_N, -- Chip Enable
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SRAM_OE_N => SRAM_OE_N, -- Output Enable
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-- SD card interface
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SD_DAT => SD_DAT, -- SD Card Data SD pin 7 "DAT 0/DataOut"
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SD_DAT3 => SD_DAT3, -- SD Card Data 3 SD pin 1 "DAT 3/nCS"
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SD_CMD => SD_CMD, -- SD Card Command SD pin 2 "CMD/DataIn"
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SD_CLK => SD_CLK, -- SD Card Clock SD pin 5 "CLK"
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-- Led
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LED => LED,
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-- PS/2 port
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PS2_DAT => PS2_DAT,
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PS2_CLK => PS2_CLK,
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O_AUDIO_L => O_AUDIO_L,
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O_AUDIO_R => O_AUDIO_R,
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-- VGA output
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VGA_HS => VGA_HS,
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VGA_VS => VGA_VS,
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VGA_R => VGA_R,
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VGA_G => VGA_G, -- Green[3:0]
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VGA_B => VGA_B
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);
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-- Clock process definitions
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CLK_32M_process :process
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begin
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CLK_32M <= '0';
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wait for CLK_32M_period/2;
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CLK_32M <= '1';
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wait for CLK_32M_period/2;
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end process;
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-- Test Bench Statements
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tb : PROCESS
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BEGIN
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wait for 100 ns; -- wait until global set/reset completes
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-- Add user defined stimulus here
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wait; -- will wait forever
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END PROCESS tb;
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-- End Test Bench
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END;
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