160 lines
4.2 KiB
VHDL
160 lines
4.2 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 21:41:31 01/06/2016
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-- Design Name:
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-- Module Name: /home/mandl/Entwicklung/Apple2/timing_tb2.vhd
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-- Project Name: Apple2
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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-- VHDL Test Bench Created by ISE for module: timing_generator
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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-- Notes:
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-- This testbench has been automatically generated using types std_logic and
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-- std_logic_vector for the ports of the unit under test. Xilinx recommends
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-- that these types always be used for the top-level I/O of a design in order
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- simulation model.
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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use ieee.numeric_std.all;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--USE ieee.numeric_std.ALL;
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ENTITY timing_tb2 IS
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END timing_tb2;
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ARCHITECTURE behavior OF timing_tb2 IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT timing_generator
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PORT(
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CLK_14M : IN std_logic;
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CLK_7M_out : OUT std_logic;
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Q3_out : OUT std_logic;
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RAS_N_out : OUT std_logic;
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CAS_N_out : OUT std_logic;
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AX_out : OUT std_logic;
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PHI0_out : OUT std_logic;
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PRE_PHI0_out : OUT std_logic;
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COLOR_REF_out : OUT std_logic;
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TEXT_MODE : IN std_logic;
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PAGE2 : IN std_logic;
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HIRES : IN std_logic;
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VIDEO_ADDRESS : OUT unsigned(15 downto 0);
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H0 : OUT std_logic;
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VA : OUT std_logic;
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VB : OUT std_logic;
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VC : OUT std_logic;
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V2 : OUT std_logic;
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V4 : OUT std_logic;
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HBL_out : OUT std_logic;
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VBL_out : OUT std_logic;
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BLANK : OUT std_logic;
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LDPS_N : OUT std_logic;
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LD194 : OUT std_logic
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);
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END COMPONENT;
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--Inputs
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signal CLK_14M : std_logic := '0';
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signal TEXT_MODE : std_logic := '0';
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signal PAGE2 : std_logic := '0';
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signal HIRES : std_logic := '0';
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--Outputs
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signal CLK_7M_out : std_logic;
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signal Q3_out : std_logic;
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signal RAS_N_out : std_logic;
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signal CAS_N_out : std_logic;
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signal AX_out : std_logic;
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signal PHI0_out : std_logic;
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signal PRE_PHI0_out : std_logic;
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signal COLOR_REF_out : std_logic;
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signal VIDEO_ADDRESS : std_logic_vector(15 downto 0);
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signal H0 : std_logic;
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signal VA : std_logic;
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signal VB : std_logic;
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signal VC : std_logic;
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signal V2 : std_logic;
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signal V4 : std_logic;
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signal HBL_out : std_logic;
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signal VBL_out : std_logic;
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signal BLANK : std_logic;
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signal LDPS_N : std_logic;
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signal LD194 : std_logic;
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-- Clock period definitions
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constant CLK_14M_period : time := 71.42 ns;
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: timing_generator PORT MAP (
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CLK_14M => CLK_14M,
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CLK_7M_out => CLK_7M_out,
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Q3_out => Q3_out,
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RAS_N_out => RAS_N_out,
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CAS_N_out => CAS_N_out,
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AX_out => AX_out,
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PHI0_out => PHI0_out,
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PRE_PHI0_out => PRE_PHI0_out,
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COLOR_REF_out => COLOR_REF_out,
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TEXT_MODE => TEXT_MODE,
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PAGE2 => PAGE2,
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HIRES => HIRES,
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std_logic_vector(VIDEO_ADDRESS) => VIDEO_ADDRESS,
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H0 => H0,
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VA => VA,
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VB => VB,
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VC => VC,
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V2 => V2,
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V4 => V4,
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HBL_out => HBL_out,
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VBL_out => VBL_out,
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BLANK => BLANK,
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LDPS_N => LDPS_N,
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LD194 => LD194
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);
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-- Clock process definitions
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CLK_14M_process :process
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begin
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CLK_14M <= '0';
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wait for CLK_14M_period/2;
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CLK_14M <= '1';
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wait for CLK_14M_period/2;
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end process;
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-- Stimulus process
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stim_proc: process
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begin
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-- hold reset state for 100 ns.
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wait for 100 ns;
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wait for CLK_14M_period*10;
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-- insert stimulus here
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wait;
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end process;
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END;
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