26 lines
422 B
VHDL
26 lines
422 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity timing_testbench is
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end timing_testbench;
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architecture behavioral of timing_testbench is
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signal CLK_14M : std_logic := '0';
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begin
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uut : entity work.timing_generator
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port map (
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CLK_14M => CLK_14M,
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TEXT_MODE => '1',
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PAGE2 => '0',
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HIRES => '1'
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);
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CLK_14M <= not CLK_14M after 34.920639355 ns;
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end behavioral;
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