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https://github.com/garrettsworkshop/GR8RAM.git
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Removed inhibit output
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@ -1,11 +1,12 @@
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module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
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module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
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A, RA, nWE, D, RD,
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A, RA, nWE, D, RD,
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nDEVSEL, nIOSEL, nIOSTRB, nINH,
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nDEVSEL, nIOSEL, nIOSTRB,
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nRAS, nCAS0, nCAS1, nRCS, nROE, nRWE);
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nRAS, nCAS0, nCAS1, nRCS, nROE, nRWE);
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/* Clock, Reset, Mode */
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/* Clock, Reset, Mode */
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input C7M, C7M_2, Q3, PHI0in, PHI1in; // Clock inputs
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input C7M, C7M_2, Q3, PHI0in, PHI1in; // Clock inputs
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input nRES, nMode; // Reset, mode
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input nRES, Mode;
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input Mode;
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/* PHI1 Delay */
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/* PHI1 Delay */
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wire [8:0] PHI1b;
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wire [8:0] PHI1b;
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@ -56,9 +57,6 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
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AddrMSELA ? Addr[15:8] :
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AddrMSELA ? Addr[15:8] :
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AddrLSELA ? Addr[7:0] : 8'h00;
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AddrLSELA ? Addr[7:0] : 8'h00;
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inout [7:0] D = DOE ? Dout : 8'bZ;
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inout [7:0] D = DOE ? Dout : 8'bZ;
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/* Inhibit output */
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output nINH = 1'bZ;
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/* DRAM and ROM Control Signals */
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/* DRAM and ROM Control Signals */
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output nRCS = ~((~nIOSEL | (~nIOSTRB & IOROMEN)) & CSEN); // ROM chip select
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output nRCS = ~((~nIOSEL | (~nIOSTRB & IOROMEN)) & CSEN); // ROM chip select
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