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@ -34,17 +34,26 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
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( nIOSTRB & CASel & nIOSEL) ? Addr[7:0] : 8'h00;
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( nIOSTRB & CASel & nIOSEL) ? Addr[7:0] : 8'h00;
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/* Select Signals */
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/* Select Signals */
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wire BankSELA = A[3:0]==4'hF;
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wire BankSELA = A[3:0]==4'hF;
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wire RAMSELA = A[3:0]==4'h3;
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wire MagicSELA = A[3:0]==4'hE;
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wire AddrHSELA = A[3:0]==4'h2;
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wire TCntHSELA = A[3:0]==4'hB;
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wire AddrMSELA = A[3:0]==4'h1;
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wire TCntLSELA = A[3:0]==4'hA;
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wire AddrLSELA = A[3:0]==4'h0;
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wire DestHSELA = A[3:0]==4'h9;
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LCELL BankWR_MC (.in(BankSELA & ~nWE & ~nDEVSEL & REGEN), .out(BankWR)); wire BankWR;
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wire DestLSELA = A[3:0]==4'h8;
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LCELL SetWR_MC (.in(SetSELA & ~nWE & ~nDEVSEL & REGEN), .out(SetWR)); wire SetWR;
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wire RAMSELA = A[3:0]==4'h3;
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LCELL RAMSEL_MC (.in(RAMSELA & ~nDEVSEL & REGEN), .out(RAMSEL)); wire RAMSEL;
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wire AddrHSELA = A[3:0]==4'h2;
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LCELL AddrHWR_MC (.in(AddrHSELA & ~nWE & ~nDEVSEL & REGEN), .out(AddrHWR)); wire AddrHWR;
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wire AddrMSELA = A[3:0]==4'h1;
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LCELL AddrMWR_MC (.in(AddrMSELA & ~nWE & ~nDEVSEL & REGEN), .out(AddrMWR)); wire AddrMWR;
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wire AddrLSELA = A[3:0]==4'h0;
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LCELL AddrLWR_MC (.in(AddrLSELA & ~nWE & ~nDEVSEL & REGEN), .out(AddrLWR)); wire AddrLWR;
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LCELL BankWR_MC (.in(BankSELA & ~nWE & ~nDEVSEL & REGEN), .out(BankWR)); wire BankWR;
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LCELL MagicWR_MC (.in(MagicSELA & ~nWE & ~nDEVSEL & REGEN), .out(MagicWR)); wire MagicWR;
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LCELL TCntHWR_MC (.in(TCntHSELA & ~nWE & ~nDEVSEL & REGEN), .out(TCntHWR)); wire TCntHWR;
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LCELL TCntLWR_MC (.in(TCntLSELA & ~nWE & ~nDEVSEL & REGEN), .out(TCntLWR)); wire TCntLWR;
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LCELL DestHWR_MC (.in(DestHSELA & ~nWE & ~nDEVSEL & REGEN), .out(DestHWR)); wire DestHWR;
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LCELL DestLWR_MC (.in(DestLSELA & ~nWE & ~nDEVSEL & REGEN), .out(DestLWR)); wire DestLWR;
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LCELL RAMSEL_MC (.in(RAMSELA & ~nDEVSEL & REGEN), .out(RAMSEL)); wire RAMSEL;
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LCELL AddrHWR_MC (.in(AddrHSELA & ~nWE & ~nDEVSEL & REGEN), .out(AddrHWR)); wire AddrHWR;
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LCELL AddrMWR_MC (.in(AddrMSELA & ~nWE & ~nDEVSEL & REGEN), .out(AddrMWR)); wire AddrMWR;
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LCELL AddrLWR_MC (.in(AddrLSELA & ~nWE & ~nDEVSEL & REGEN), .out(AddrLWR)); wire AddrLWR;
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/* Data Bus Routing */
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/* Data Bus Routing */
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// DRAM/ROM data bus
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// DRAM/ROM data bus
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@ -71,15 +80,20 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
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reg REGEN = 0; // Register enable
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reg REGEN = 0; // Register enable
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reg IOROMEN = 0; // IOSTRB ROM enable
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reg IOROMEN = 0; // IOSTRB ROM enable
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reg FullIOEN = 0; // Set to enable full I/O ROM space
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reg FullIOEN = 0; // Set to enable full I/O ROM space
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reg PDMARDEN = 0;
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reg PDMAWREN = 0;
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reg [7:0] Bank = 0; // Bank register for ROM access
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reg [7:0] Bank = 0; // Bank register for ROM access
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reg [23:0] Addr = 0; // RAM address register
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reg [23:0] Addr = 0; // RAM address register
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/* Increment Control */
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/* RAM Address Register Increment Control */
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reg IncAddrL = 0, IncAddrM = 0, IncAddrH = 0;
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reg IncAddrL = 0, IncAddrM = 0, IncAddrH = 0;
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/* Transfer Counters */
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/* Pseudo-DMA Transfer Counters */
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reg [15:0] TCnt = 0;
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reg [9:0] TCnt = 0;
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reg [15:0] Dest = 0;
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reg [15:0] Dest = 0;
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/* Transfer Counter Increment Control */
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reg PDMANext = 0, IncDestH = 0;
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/* CAS rising/falling edge components */
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/* CAS rising/falling edge components */
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// These are combined to create the CAS outputs.
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// These are combined to create the CAS outputs.
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@ -164,19 +178,21 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
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Addr <= 0;
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Addr <= 0;
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Bank <= 0;
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Bank <= 0;
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FullIOEN <= 0;
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FullIOEN <= 0;
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PDMARDEN <= 0;
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PDMAWREN <= 0;
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IncAddrL <= 0;
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IncAddrL <= 0;
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IncAddrM <= 0;
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IncAddrM <= 0;
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IncAddrH <= 0;
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IncAddrH <= 0;
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end else begin
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end else begin
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// Increment address register
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// Increment address register
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if (S==1 & IncAddrL) begin
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if (S==1 & IncAddrL) begin
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Addr[7:0] <= Addr[7:0]+1;
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IncAddrL <= 0;
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IncAddrL <= 0;
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Addr[7:0] <= Addr[7:0]+1;
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IncAddrM <= Addr[7:0] == 8'hFF;
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IncAddrM <= Addr[7:0] == 8'hFF;
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end
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end
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if (S==2 & IncAddrM) begin
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if (S==2 & IncAddrM) begin
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Addr[15:8] <= Addr[15:8]+1;
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IncAddrM <= 0;
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IncAddrM <= 0;
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Addr[15:8] <= Addr[15:8]+1;
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IncAddrH <= Addr[15:8] == 8'hFF;
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IncAddrH <= Addr[15:8] == 8'hFF;
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end
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end
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if (S==3 & IncAddrH) begin
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if (S==3 & IncAddrH) begin
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@ -186,8 +202,12 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
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// Set register in middle of S6 if accessed.
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// Set register in middle of S6 if accessed.
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if (S==6) begin
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if (S==6) begin
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if (BankWR) Bank[7:0] <= D[7:0]; // Bank
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if (BankWR) begin
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if (SetWR) FullIOEN <= D[7:0] == 8'hE5;
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Bank[7:0] <= D[7:0];
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PDMARDEN <= D[7:0]==8'h10 & FullIOEN;
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PDMAWREN <= D[7:0]==8'h10 & FullIOEN;
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end
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if (MagicWR) FullIOEN <= D[7:0] == 8'hE5;
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IncAddrL <= RAMSEL;
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IncAddrL <= RAMSEL;
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IncAddrM <= AddrLWR & Addr[7] & ~D[7];
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IncAddrM <= AddrLWR & Addr[7] & ~D[7];
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@ -200,6 +220,38 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
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end
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end
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end
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end
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/* Pseudo-DMA transfer counters */
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always @(negedge C7M, negedge nRES) begin
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if (~nRES) begin
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TCnt <= 0;
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Dest <= 0;
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PDMANext <= 0;
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IncDestH <= 0;
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end else begin
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// Increment destination pointer and decrement transfer counter
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if (S==1 & PDMANext) begin
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PDMANext <= 0;
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Dest[7:0] <= Dest[7:0]+1;
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IncDestH <= Dest[7:0] == 8'hFF;
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TCnt <= TCnt-1;
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end
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if (S==2 & IncDestH) begin
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IncDestH <= 0;
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Dest[15:8] <= Dest[15:8]+1;
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end
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// Set register in middle of S6 if accessed.
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if (S==6) begin
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PDMANext <= RAMSEL;
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if (TCntHWR) TCnt[15:8] <= D[7:0]; // TCnt hi
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if (TCntLWR) TCnt[7:0] <= D[7:0]; // TCnt lo
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if (DestHWR) Dest[15:8] <= D[7:0]; // Dest hi
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if (DestLWR) Dest[7:0] <= D[7:0]; // Dest lo
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end
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end
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end
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/* DRAM RAS/CAS */
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/* DRAM RAS/CAS */
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always @(posedge C7M) begin
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always @(posedge C7M) begin
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RASr <= (S==1 & Ref==0) | // Refresh
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RASr <= (S==1 & Ref==0) | // Refresh
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