diff --git a/cpld/GR8RAM.qws b/cpld/GR8RAM.qws index 7577533..c08b644 100755 Binary files a/cpld/GR8RAM.qws and b/cpld/GR8RAM.qws differ diff --git a/cpld/db/GR8RAM.(0).cnf.cdb b/cpld/db/GR8RAM.(0).cnf.cdb index 486984e..03d7ce8 100755 Binary files a/cpld/db/GR8RAM.(0).cnf.cdb and b/cpld/db/GR8RAM.(0).cnf.cdb differ diff --git a/cpld/db/GR8RAM.(0).cnf.hdb b/cpld/db/GR8RAM.(0).cnf.hdb index 42e2118..58fd575 100755 Binary files a/cpld/db/GR8RAM.(0).cnf.hdb and b/cpld/db/GR8RAM.(0).cnf.hdb differ diff --git a/cpld/db/GR8RAM.asm.qmsg b/cpld/db/GR8RAM.asm.qmsg index 976e937..95d4743 100755 --- a/cpld/db/GR8RAM.asm.qmsg +++ b/cpld/db/GR8RAM.asm.qmsg @@ -1,5 +1,5 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567909565827 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567909565827 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Sep 07 22:26:05 2019 " "Processing started: Sat Sep 07 22:26:05 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567909565827 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1567909565827 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1567909565827 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1567909565947 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4521 " "Peak virtual memory: 4521 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567909567106 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Sep 07 22:26:07 2019 " "Processing ended: Sat Sep 07 22:26:07 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567909567106 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567909567106 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567909567106 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1567909567106 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1571014478456 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571014478457 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Oct 13 20:54:38 2019 " "Processing started: Sun Oct 13 20:54:38 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1571014478457 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1571014478457 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1571014478457 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1571014478586 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4522 " "Peak virtual memory: 4522 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571014478743 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Oct 13 20:54:38 2019 " "Processing ended: Sun Oct 13 20:54:38 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571014478743 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571014478743 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571014478743 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1571014478743 ""} diff --git a/cpld/db/GR8RAM.asm.rdb b/cpld/db/GR8RAM.asm.rdb index 187c449..5535136 100755 Binary files a/cpld/db/GR8RAM.asm.rdb and b/cpld/db/GR8RAM.asm.rdb differ diff --git a/cpld/db/GR8RAM.cmp.cdb b/cpld/db/GR8RAM.cmp.cdb index 76f7803..c994ecd 100755 Binary files a/cpld/db/GR8RAM.cmp.cdb and b/cpld/db/GR8RAM.cmp.cdb differ diff --git a/cpld/db/GR8RAM.cmp.hdb b/cpld/db/GR8RAM.cmp.hdb index 26561f4..8f9b529 100755 Binary files a/cpld/db/GR8RAM.cmp.hdb and b/cpld/db/GR8RAM.cmp.hdb differ diff --git a/cpld/db/GR8RAM.cmp.rdb b/cpld/db/GR8RAM.cmp.rdb index 4443a1d..0aaadd2 100755 Binary files a/cpld/db/GR8RAM.cmp.rdb and b/cpld/db/GR8RAM.cmp.rdb differ diff --git a/cpld/db/GR8RAM.db_info b/cpld/db/GR8RAM.db_info index 60199ae..25b80cb 100755 --- a/cpld/db/GR8RAM.db_info +++ b/cpld/db/GR8RAM.db_info @@ -1,3 +1,3 @@ Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition Version_Index = 302049280 -Creation_Time = Sat Sep 07 22:06:23 2019 +Creation_Time = Sun Oct 13 20:54:29 2019 diff --git a/cpld/db/GR8RAM.fit.qmsg b/cpld/db/GR8RAM.fit.qmsg index 94492d8..f35646a 100755 --- a/cpld/db/GR8RAM.fit.qmsg +++ b/cpld/db/GR8RAM.fit.qmsg @@ -1,3 +1,3 @@ -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1567909564817 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1567909564817 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4708 " "Peak virtual memory: 4708 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567909564997 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Sep 07 22:26:04 2019 " "Processing ended: Sat Sep 07 22:26:04 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567909564997 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567909564997 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567909564997 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1567909564997 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1571014477034 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1571014477052 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4708 " "Peak virtual memory: 4708 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571014477434 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Oct 13 20:54:37 2019 " "Processing ended: Sun Oct 13 20:54:37 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571014477434 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571014477434 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571014477434 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1571014477434 ""} diff --git a/cpld/db/GR8RAM.hier_info b/cpld/db/GR8RAM.hier_info index b2d871f..a336be0 100755 --- a/cpld/db/GR8RAM.hier_info +++ b/cpld/db/GR8RAM.hier_info @@ -1,44 +1,9 @@ |GR8RAM +C7M => always1.IN0 C7M => CAS1r.CLK C7M => CAS0r.CLK C7M => RASr.CLK C7M => ASel.CLK -C7M => IncAddrH.CLK -C7M => IncAddrM.CLK -C7M => IncAddrL.CLK -C7M => FullIOEN.CLK -C7M => Bank[0].CLK -C7M => Bank[1].CLK -C7M => Bank[2].CLK -C7M => Bank[3].CLK -C7M => Bank[4].CLK -C7M => Bank[5].CLK -C7M => Bank[6].CLK -C7M => Bank[7].CLK -C7M => Addr[0].CLK -C7M => Addr[1].CLK -C7M => Addr[2].CLK -C7M => Addr[3].CLK -C7M => Addr[4].CLK -C7M => Addr[5].CLK -C7M => Addr[6].CLK -C7M => Addr[7].CLK -C7M => Addr[8].CLK -C7M => Addr[9].CLK -C7M => Addr[10].CLK -C7M => Addr[11].CLK -C7M => Addr[12].CLK -C7M => Addr[13].CLK -C7M => Addr[14].CLK -C7M => Addr[15].CLK -C7M => Addr[16].CLK -C7M => Addr[17].CLK -C7M => Addr[18].CLK -C7M => Addr[19].CLK -C7M => Addr[20].CLK -C7M => Addr[21].CLK -C7M => Addr[22].CLK -C7M => Addr[23].CLK C7M => CSDBEN.CLK C7M => IOROMEN.CLK C7M => REGEN.CLK @@ -51,7 +16,7 @@ C7M => S[1].CLK C7M => S[2].CLK C7M => PHI0seen.CLK C7M => PHI1reg.CLK -C7M_2 => always2.IN0 +C7M_2 => always3.IN0 Q3 => ~NO_FANOUT~ PHI0in => ~NO_FANOUT~ PHI1in => comb.IN0 diff --git a/cpld/db/GR8RAM.hif b/cpld/db/GR8RAM.hif index c3f673b..7182c18 100755 Binary files a/cpld/db/GR8RAM.hif and b/cpld/db/GR8RAM.hif differ diff --git a/cpld/db/GR8RAM.map.cdb b/cpld/db/GR8RAM.map.cdb index 0d646bd..d6d2da7 100755 Binary files a/cpld/db/GR8RAM.map.cdb and b/cpld/db/GR8RAM.map.cdb differ diff --git a/cpld/db/GR8RAM.map.hdb b/cpld/db/GR8RAM.map.hdb index 85b2c82..9907caf 100755 Binary files a/cpld/db/GR8RAM.map.hdb and b/cpld/db/GR8RAM.map.hdb differ diff --git a/cpld/db/GR8RAM.map.qmsg b/cpld/db/GR8RAM.map.qmsg index 836ddb5..ff618fd 100755 --- a/cpld/db/GR8RAM.map.qmsg +++ b/cpld/db/GR8RAM.map.qmsg @@ -1,34 +1,33 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567909562928 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567909562928 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Sep 07 22:26:02 2019 " "Processing started: Sat Sep 07 22:26:02 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567909562928 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1567909562928 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1567909562928 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1567909563131 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(52) " "Verilog HDL warning at GR8RAM.v(52): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 52 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1567909563157 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(60) " "Verilog HDL warning at GR8RAM.v(60): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 60 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1567909563157 ""} -{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "GR8RAM.v(190) " "Verilog HDL information at GR8RAM.v(190): always construct contains both blocking and non-blocking assignments" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 190 0 0 } } } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Quartus II" 0 -1 1567909563157 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1567909563167 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1567909563167 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1567909563197 ""} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(30) " "Verilog HDL assignment warning at GR8RAM.v(30): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567909563197 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 GR8RAM.v(133) " "Verilog HDL assignment warning at GR8RAM.v(133): truncated value with size 32 to match size of target (3)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 133 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567909563197 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(138) " "Verilog HDL assignment warning at GR8RAM.v(138): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 138 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567909563197 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(159) " "Verilog HDL assignment warning at GR8RAM.v(159): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 159 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567909563197 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(164) " "Verilog HDL assignment warning at GR8RAM.v(164): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 164 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567909563197 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(170) " "Verilog HDL assignment warning at GR8RAM.v(170): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 170 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567909563197 "|GR8RAM"} -{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "Ref_rtl_0 4 " "Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"Ref_rtl_0\"" { } { } 0 19001 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567909563267 ""} } { } 0 19000 "Inferred %1!d! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1567909563267 ""} -{ "Info" "ILPMS_INFERENCING_SUMMARY" "4 " "Inferred 4 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add0 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add0\"" { } { { "GR8RAM.v" "Add0" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567909563267 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add4 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add4\"" { } { { "GR8RAM.v" "Add4" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 164 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567909563267 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add3 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add3\"" { } { { "GR8RAM.v" "Add3" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 159 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567909563267 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add5 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add5\"" { } { { "GR8RAM.v" "Add5" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 170 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567909563267 ""} } { } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1567909563267 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter:Ref_rtl_0 " "Elaborated megafunction instantiation \"lpm_counter:Ref_rtl_0\"" { } { } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567909563296 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_counter:Ref_rtl_0 " "Instantiated megafunction \"lpm_counter:Ref_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 4 " "Parameter \"LPM_WIDTH\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567909563296 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION UP " "Parameter \"LPM_DIRECTION\" = \"UP\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567909563296 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_COUNTER " "Parameter \"LPM_TYPE\" = \"LPM_COUNTER\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567909563296 ""} } { } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567909563296 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567909563317 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add0 " "Instantiated megafunction \"lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 8 " "Parameter \"LPM_WIDTH\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567909563317 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Parameter \"LPM_DIRECTION\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567909563317 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567909563317 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567909563317 ""} } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567909563317 ""} -{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\] lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 260 9 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567909563327 ""} -{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 86 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567909563341 ""} -{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 178 5 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567909563341 ""} -{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|look_add:look_ahead_unit lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|look_add:look_ahead_unit\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 263 4 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567909563356 ""} -{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:result_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567909563366 ""} -{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 270 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567909563366 ""} -{ "Info" "IMLS_MLS_IGNORED_SUMMARY" "32 " "Ignored 32 buffer(s)" { { "Info" "IMLS_MLS_IGNORED_SOFT" "32 " "Ignored 32 SOFT buffer(s)" { } { } 0 13019 "Ignored %1!d! SOFT buffer(s)" 0 0 "Quartus II" 0 -1 1567909563436 ""} } { } 0 13014 "Ignored %1!d! buffer(s)" 0 0 "Quartus II" 0 -1 1567909563436 ""} -{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 131 -1 0 } } } 0 13000 "Registers with preset signals will power-up high" 0 0 "Quartus II" 0 -1 1567909563441 ""} -{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "C7M " "Promoted clock signal driven by pin \"C7M\" to global clock signal" { } { } 0 280014 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0 "Quartus II" 0 -1 1567909563527 ""} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "nRES " "Promoted clear signal driven by pin \"nRES\" to global clear signal" { } { } 0 280015 "Promoted clear signal driven by pin \"%1!s!\" to global clear signal" 0 0 "Quartus II" 0 -1 1567909563527 ""} } { } 0 280013 "Promoted pin-driven signal(s) to global signal" 0 0 "Quartus II" 0 -1 1567909563527 ""} -{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "8 " "Design contains 8 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "Q3 " "No output dependent on input pin \"Q3\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567909563709 "|GR8RAM|Q3"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "PHI0in " "No output dependent on input pin \"PHI0in\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567909563709 "|GR8RAM|PHI0in"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "nMode " "No output dependent on input pin \"nMode\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 8 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567909563709 "|GR8RAM|nMode"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[11\] " "No output dependent on input pin \"A\[11\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567909563709 "|GR8RAM|A[11]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[12\] " "No output dependent on input pin \"A\[12\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567909563709 "|GR8RAM|A[12]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[13\] " "No output dependent on input pin \"A\[13\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567909563709 "|GR8RAM|A[13]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[14\] " "No output dependent on input pin \"A\[14\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567909563709 "|GR8RAM|A[14]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[15\] " "No output dependent on input pin \"A\[15\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567909563709 "|GR8RAM|A[15]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1567909563709 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "168 " "Implemented 168 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "27 " "Implemented 27 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1567909563709 ""} { "Info" "ICUT_CUT_TM_OPINS" "18 " "Implemented 18 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1567909563709 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Implemented 16 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1567909563709 ""} { "Info" "ICUT_CUT_TM_MCELLS" "105 " "Implemented 105 macrocells" { } { } 0 21063 "Implemented %1!d! macrocells" 0 0 "Quartus II" 0 -1 1567909563709 ""} { "Info" "ICUT_CUT_TM_SEXPS" "2 " "Implemented 2 shareable expanders" { } { } 0 21073 "Implemented %1!d! shareable expanders" 0 0 "Quartus II" 0 -1 1567909563709 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1567909563709 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1567909563757 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 16 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 16 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4587 " "Peak virtual memory: 4587 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567909563787 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Sep 07 22:26:03 2019 " "Processing ended: Sat Sep 07 22:26:03 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567909563787 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567909563787 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567909563787 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567909563787 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1571014473956 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571014473956 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Oct 13 20:54:33 2019 " "Processing started: Sun Oct 13 20:54:33 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1571014473956 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1571014473956 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1571014473956 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1571014474336 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(52) " "Verilog HDL warning at GR8RAM.v(52): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 52 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1571014474390 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(60) " "Verilog HDL warning at GR8RAM.v(60): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 60 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1571014474391 ""} +{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "GR8RAM.v(195) " "Verilog HDL information at GR8RAM.v(195): always construct contains both blocking and non-blocking assignments" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 195 0 0 } } } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Quartus II" 0 -1 1571014474391 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1571014474392 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1571014474392 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1571014474549 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(30) " "Verilog HDL assignment warning at GR8RAM.v(30): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1571014474551 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 GR8RAM.v(127) " "Verilog HDL assignment warning at GR8RAM.v(127): truncated value with size 32 to match size of target (3)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 127 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1571014474552 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(132) " "Verilog HDL assignment warning at GR8RAM.v(132): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 132 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1571014474553 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(164) " "Verilog HDL assignment warning at GR8RAM.v(164): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 164 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1571014474553 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(169) " "Verilog HDL assignment warning at GR8RAM.v(169): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 169 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1571014474554 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(175) " "Verilog HDL assignment warning at GR8RAM.v(175): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 175 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1571014474554 "|GR8RAM"} +{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "Ref_rtl_0 4 " "Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"Ref_rtl_0\"" { } { } 0 19001 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571014474704 ""} } { } 0 19000 "Inferred %1!d! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1571014474704 ""} +{ "Info" "ILPMS_INFERENCING_SUMMARY" "4 " "Inferred 4 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add0 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add0\"" { } { { "GR8RAM.v" "Add0" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571014474704 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add4 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add4\"" { } { { "GR8RAM.v" "Add4" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 169 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571014474704 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add3 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add3\"" { } { { "GR8RAM.v" "Add3" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 164 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571014474704 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add5 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add5\"" { } { { "GR8RAM.v" "Add5" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 175 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571014474704 ""} } { } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1571014474704 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter:Ref_rtl_0 " "Elaborated megafunction instantiation \"lpm_counter:Ref_rtl_0\"" { } { } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571014474808 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_counter:Ref_rtl_0 " "Instantiated megafunction \"lpm_counter:Ref_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 4 " "Parameter \"LPM_WIDTH\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571014474808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION UP " "Parameter \"LPM_DIRECTION\" = \"UP\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571014474808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_COUNTER " "Parameter \"LPM_TYPE\" = \"LPM_COUNTER\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571014474808 ""} } { } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1571014474808 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571014474839 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add0 " "Instantiated megafunction \"lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 8 " "Parameter \"LPM_WIDTH\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571014474839 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Parameter \"LPM_DIRECTION\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571014474839 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571014474839 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571014474839 ""} } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1571014474839 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\] lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 260 9 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571014474861 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 86 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571014474941 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 178 5 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571014474958 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|look_add:look_ahead_unit lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|look_add:look_ahead_unit\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 263 4 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571014474976 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:result_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571014474993 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 270 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1571014475008 ""} +{ "Info" "IMLS_MLS_IGNORED_SUMMARY" "32 " "Ignored 32 buffer(s)" { { "Info" "IMLS_MLS_IGNORED_SOFT" "32 " "Ignored 32 SOFT buffer(s)" { } { } 0 13019 "Ignored %1!d! SOFT buffer(s)" 0 0 "Quartus II" 0 -1 1571014475152 ""} } { } 0 13014 "Ignored %1!d! buffer(s)" 0 0 "Quartus II" 0 -1 1571014475152 ""} +{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "C7M " "Promoted clock signal driven by pin \"C7M\" to global clock signal" { } { } 0 280014 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0 "Quartus II" 0 -1 1571014475258 ""} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "nRES " "Promoted clear signal driven by pin \"nRES\" to global clear signal" { } { } 0 280015 "Promoted clear signal driven by pin \"%1!s!\" to global clear signal" 0 0 "Quartus II" 0 -1 1571014475258 ""} } { } 0 280013 "Promoted pin-driven signal(s) to global signal" 0 0 "Quartus II" 0 -1 1571014475258 ""} +{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "8 " "Design contains 8 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "Q3 " "No output dependent on input pin \"Q3\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571014475471 "|GR8RAM|Q3"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "PHI0in " "No output dependent on input pin \"PHI0in\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571014475471 "|GR8RAM|PHI0in"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "nMode " "No output dependent on input pin \"nMode\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 8 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571014475471 "|GR8RAM|nMode"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[11\] " "No output dependent on input pin \"A\[11\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571014475471 "|GR8RAM|A[11]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[12\] " "No output dependent on input pin \"A\[12\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571014475471 "|GR8RAM|A[12]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[13\] " "No output dependent on input pin \"A\[13\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571014475471 "|GR8RAM|A[13]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[14\] " "No output dependent on input pin \"A\[14\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571014475471 "|GR8RAM|A[14]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[15\] " "No output dependent on input pin \"A\[15\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1571014475471 "|GR8RAM|A[15]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1571014475471 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "168 " "Implemented 168 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "27 " "Implemented 27 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1571014475472 ""} { "Info" "ICUT_CUT_TM_OPINS" "18 " "Implemented 18 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1571014475472 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Implemented 16 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1571014475472 ""} { "Info" "ICUT_CUT_TM_MCELLS" "105 " "Implemented 105 macrocells" { } { } 0 21063 "Implemented %1!d! macrocells" 0 0 "Quartus II" 0 -1 1571014475472 ""} { "Info" "ICUT_CUT_TM_SEXPS" "2 " "Implemented 2 shareable expanders" { } { } 0 21073 "Implemented %1!d! shareable expanders" 0 0 "Quartus II" 0 -1 1571014475472 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1571014475472 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1571014475667 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 16 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 16 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4587 " "Peak virtual memory: 4587 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571014475712 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Oct 13 20:54:35 2019 " "Processing ended: Sun Oct 13 20:54:35 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571014475712 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571014475712 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571014475712 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1571014475712 ""} diff --git a/cpld/db/GR8RAM.map.rdb b/cpld/db/GR8RAM.map.rdb index 58eaa34..8de912e 100755 Binary files a/cpld/db/GR8RAM.map.rdb and b/cpld/db/GR8RAM.map.rdb differ diff --git a/cpld/db/GR8RAM.pre_map.hdb b/cpld/db/GR8RAM.pre_map.hdb index 094fa59..284bc1b 100755 Binary files a/cpld/db/GR8RAM.pre_map.hdb and b/cpld/db/GR8RAM.pre_map.hdb differ diff --git a/cpld/db/GR8RAM.rtlv.hdb b/cpld/db/GR8RAM.rtlv.hdb index 369e9a4..461e2b1 100755 Binary files a/cpld/db/GR8RAM.rtlv.hdb and b/cpld/db/GR8RAM.rtlv.hdb differ diff --git a/cpld/db/GR8RAM.rtlv_sg.cdb b/cpld/db/GR8RAM.rtlv_sg.cdb index 8884f53..bcfd05c 100755 Binary files a/cpld/db/GR8RAM.rtlv_sg.cdb and b/cpld/db/GR8RAM.rtlv_sg.cdb differ diff --git a/cpld/db/GR8RAM.sgdiff.cdb b/cpld/db/GR8RAM.sgdiff.cdb index d5748ab..907198a 100755 Binary files a/cpld/db/GR8RAM.sgdiff.cdb and b/cpld/db/GR8RAM.sgdiff.cdb differ diff --git a/cpld/db/GR8RAM.sgdiff.hdb b/cpld/db/GR8RAM.sgdiff.hdb index 7e2ac15..c741de1 100755 Binary files a/cpld/db/GR8RAM.sgdiff.hdb and b/cpld/db/GR8RAM.sgdiff.hdb differ diff --git a/cpld/db/GR8RAM.sta.qmsg b/cpld/db/GR8RAM.sta.qmsg index 67363cd..aeb7ec3 100755 --- a/cpld/db/GR8RAM.sta.qmsg +++ b/cpld/db/GR8RAM.sta.qmsg @@ -1,22 +1,22 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567909568834 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567909568834 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Sep 07 22:26:08 2019 " "Processing started: Sat Sep 07 22:26:08 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567909568834 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1567909568834 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1567909568834 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1567909568889 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1567909568980 ""} -{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1567909568985 ""} -{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1567909568990 ""} -{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." { } { } 0 335095 "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." 0 0 "Quartus II" 0 -1 1567909569009 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1567909569019 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1567909569019 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M C7M " "create_clock -period 1.000 -name C7M C7M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567909569019 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M_2 C7M_2 " "create_clock -period 1.000 -name C7M_2 C7M_2" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567909569019 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567909569019 ""} -{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1567909569019 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1567909569029 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -47.000 " "Worst-case setup slack is -47.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567909569039 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567909569039 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -47.000 -2056.000 C7M " " -47.000 -2056.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567909569039 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -27.500 -33.000 C7M_2 " " -27.500 -33.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567909569039 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567909569039 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold -1.500 " "Worst-case hold slack is -1.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567909569039 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567909569039 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.500 -3.000 C7M_2 " " -1.500 -3.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567909569039 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 5.000 0.000 C7M " " 5.000 0.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567909569039 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567909569039 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567909569049 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567909569049 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -5.500 " "Worst-case minimum pulse width slack is -5.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567909569049 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567909569049 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.500 -22.000 C7M_2 " " -5.500 -22.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567909569049 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.500 -468.000 C7M " " -4.500 -468.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567909569049 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567909569049 ""} -{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1567909569219 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1567909569239 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1567909569239 ""} -{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4530 " "Peak virtual memory: 4530 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567909569380 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Sep 07 22:26:09 2019 " "Processing ended: Sat Sep 07 22:26:09 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567909569380 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567909569380 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567909569380 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567909569380 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1571014479898 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1571014479899 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Oct 13 20:54:39 2019 " "Processing started: Sun Oct 13 20:54:39 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1571014479899 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1571014479899 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1571014479899 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1571014479975 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1571014480068 ""} +{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1571014480077 ""} +{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1571014480080 ""} +{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." { } { } 0 335095 "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." 0 0 "Quartus II" 0 -1 1571014480114 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1571014480132 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1571014480132 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M C7M " "create_clock -period 1.000 -name C7M C7M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1571014480133 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M_2 C7M_2 " "create_clock -period 1.000 -name C7M_2 C7M_2" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1571014480133 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1571014480133 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1571014480135 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1571014480150 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -47.500 " "Worst-case setup slack is -47.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571014480155 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571014480155 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -47.500 -2074.000 C7M " " -47.500 -2074.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571014480155 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -27.500 -33.000 C7M_2 " " -27.500 -33.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571014480155 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1571014480155 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold -1.500 " "Worst-case hold slack is -1.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571014480161 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571014480161 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.500 -3.000 C7M_2 " " -1.500 -3.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571014480161 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 5.000 0.000 C7M " " 5.000 0.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571014480161 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1571014480161 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571014480165 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1571014480170 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -5.500 " "Worst-case minimum pulse width slack is -5.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571014480175 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571014480175 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.500 -22.000 C7M_2 " " -5.500 -22.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571014480175 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.500 -468.000 C7M " " -4.500 -468.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1571014480175 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1571014480175 ""} +{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1571014480251 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1571014480272 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1571014480273 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4530 " "Peak virtual memory: 4530 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1571014480340 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Oct 13 20:54:40 2019 " "Processing ended: Sun Oct 13 20:54:40 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1571014480340 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1571014480340 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1571014480340 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1571014480340 ""} diff --git a/cpld/db/GR8RAM.sta.rdb b/cpld/db/GR8RAM.sta.rdb index 1367dba..ef0fd24 100755 Binary files a/cpld/db/GR8RAM.sta.rdb and b/cpld/db/GR8RAM.sta.rdb differ diff --git a/cpld/db/GR8RAM.sta_cmp.15_slow.tdb b/cpld/db/GR8RAM.sta_cmp.15_slow.tdb index da868b4..e9a2969 100755 Binary files a/cpld/db/GR8RAM.sta_cmp.15_slow.tdb and b/cpld/db/GR8RAM.sta_cmp.15_slow.tdb differ diff --git a/cpld/db/GR8RAM.tmw_info b/cpld/db/GR8RAM.tmw_info index d00c6a7..432dd94 100755 --- a/cpld/db/GR8RAM.tmw_info +++ b/cpld/db/GR8RAM.tmw_info @@ -1,6 +1,6 @@ -start_full_compilation:s:00:00:07 -start_analysis_synthesis:s:00:00:02-start_full_compilation +start_full_compilation:s:00:00:08 +start_analysis_synthesis:s:00:00:04-start_full_compilation start_analysis_elaboration:s-start_full_compilation -start_fitter:s:00:00:01-start_full_compilation -start_assembler:s:00:00:03-start_full_compilation +start_fitter:s:00:00:02-start_full_compilation +start_assembler:s:00:00:01-start_full_compilation start_timing_analyzer:s:00:00:01-start_full_compilation diff --git a/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt b/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt index a8b0d9d..87e67ad 100755 Binary files a/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt and b/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt differ diff --git a/cpld/output_files/GR8RAM.asm.rpt b/cpld/output_files/GR8RAM.asm.rpt index 3d022fe..9e575cb 100755 --- a/cpld/output_files/GR8RAM.asm.rpt +++ b/cpld/output_files/GR8RAM.asm.rpt @@ -1,5 +1,5 @@ Assembler report for GR8RAM -Sat Sep 07 22:26:07 2019 +Sun Oct 13 20:54:38 2019 Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition @@ -37,7 +37,7 @@ applicable agreement for further details. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Sat Sep 07 22:26:07 2019 ; +; Assembler Status ; Successful - Sun Oct 13 20:54:38 2019 ; ; Revision Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ; ; Family ; MAX7000S ; @@ -89,7 +89,7 @@ applicable agreement for further details. +----------------+-----------------------------------------------------------------------------+ ; Device ; EPM7128SLC84-15 ; ; JTAG usercode ; 0x00000000 ; -; Checksum ; 0x0017D2F6 ; +; Checksum ; 0x0017D17D ; +----------------+-----------------------------------------------------------------------------+ @@ -99,13 +99,13 @@ applicable agreement for further details. Info: ******************************************************************* Info: Running Quartus II 64-Bit Assembler Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - Info: Processing started: Sat Sep 07 22:26:05 2019 + Info: Processing started: Sun Oct 13 20:54:38 2019 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM Info (115030): Assembler is generating device programming files Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 4521 megabytes - Info: Processing ended: Sat Sep 07 22:26:07 2019 - Info: Elapsed time: 00:00:02 + Info: Peak virtual memory: 4522 megabytes + Info: Processing ended: Sun Oct 13 20:54:38 2019 + Info: Elapsed time: 00:00:00 Info: Total CPU time (on all processors): 00:00:00 diff --git a/cpld/output_files/GR8RAM.done b/cpld/output_files/GR8RAM.done index 9848c54..3a6a2f0 100755 --- a/cpld/output_files/GR8RAM.done +++ b/cpld/output_files/GR8RAM.done @@ -1 +1 @@ -Sat Sep 07 22:26:09 2019 +Sun Oct 13 20:54:40 2019 diff --git a/cpld/output_files/GR8RAM.fit.rpt b/cpld/output_files/GR8RAM.fit.rpt index 618dbac..0238351 100755 --- a/cpld/output_files/GR8RAM.fit.rpt +++ b/cpld/output_files/GR8RAM.fit.rpt @@ -1,5 +1,5 @@ Fitter report for GR8RAM -Sat Sep 07 22:26:04 2019 +Sun Oct 13 20:54:37 2019 Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition @@ -55,7 +55,7 @@ applicable agreement for further details. +-----------------------------------------------------------------------------+ ; Fitter Summary ; +---------------------------+-------------------------------------------------+ -; Fitter Status ; Successful - Sat Sep 07 22:26:04 2019 ; +; Fitter Status ; Successful - Sun Oct 13 20:54:37 2019 ; ; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; ; Revision Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ; @@ -731,8 +731,8 @@ Warning (20028): Parallel compilation is not licensed and has been disabled Info (119006): Selected device EPM7128SLC84-15 for design "GR8RAM" Info: Quartus II 64-Bit Fitter was successful. 0 errors, 1 warning Info: Peak virtual memory: 4708 megabytes - Info: Processing ended: Sat Sep 07 22:26:04 2019 - Info: Elapsed time: 00:00:00 + Info: Processing ended: Sun Oct 13 20:54:37 2019 + Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 diff --git a/cpld/output_files/GR8RAM.fit.summary b/cpld/output_files/GR8RAM.fit.summary index 80d5751..d2e5ea7 100755 --- a/cpld/output_files/GR8RAM.fit.summary +++ b/cpld/output_files/GR8RAM.fit.summary @@ -1,4 +1,4 @@ -Fitter Status : Successful - Sat Sep 07 22:26:04 2019 +Fitter Status : Successful - Sun Oct 13 20:54:37 2019 Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition Revision Name : GR8RAM Top-level Entity Name : GR8RAM diff --git a/cpld/output_files/GR8RAM.flow.rpt b/cpld/output_files/GR8RAM.flow.rpt index 892e358..d90af59 100755 --- a/cpld/output_files/GR8RAM.flow.rpt +++ b/cpld/output_files/GR8RAM.flow.rpt @@ -1,5 +1,5 @@ Flow report for GR8RAM -Sat Sep 07 22:26:09 2019 +Sun Oct 13 20:54:40 2019 Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition @@ -40,7 +40,7 @@ applicable agreement for further details. +-----------------------------------------------------------------------------+ ; Flow Summary ; +---------------------------+-------------------------------------------------+ -; Flow Status ; Successful - Sat Sep 07 22:26:07 2019 ; +; Flow Status ; Successful - Sun Oct 13 20:54:38 2019 ; ; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; ; Revision Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ; @@ -57,7 +57,7 @@ applicable agreement for further details. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 09/07/2019 22:26:03 ; +; Start date & time ; 10/13/2019 20:54:34 ; ; Main task ; Compilation ; ; Revision Name ; GR8RAM ; +-------------------+---------------------+ @@ -72,7 +72,7 @@ applicable agreement for further details. ; AUTO_LCELL_INSERTION ; Off ; On ; -- ; -- ; ; AUTO_PARALLEL_EXPANDERS ; Off ; On ; -- ; -- ; ; AUTO_TURBO_BIT ; Off ; On ; -- ; -- ; -; COMPILER_SIGNATURE_ID ; 207120313862967.156790956319700 ; -- ; -- ; -- ; +; COMPILER_SIGNATURE_ID ; 207120313862967.157101447412556 ; -- ; -- ; -- ; ; ECO_OPTIMIZE_TIMING ; On ; Off ; -- ; -- ; ; ECO_REGENERATE_REPORT ; On ; Off ; -- ; -- ; ; EXTRACT_VERILOG_STATE_MACHINES ; Off ; On ; -- ; -- ; @@ -98,10 +98,10 @@ applicable agreement for further details. +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:01 ; 1.0 ; 4587 MB ; 00:00:01 ; -; Fitter ; 00:00:00 ; 1.0 ; 4708 MB ; 00:00:00 ; -; Assembler ; 00:00:02 ; 1.0 ; 4521 MB ; 00:00:00 ; -; TimeQuest Timing Analyzer ; 00:00:01 ; 1.0 ; 4530 MB ; 00:00:01 ; +; Analysis & Synthesis ; 00:00:02 ; 1.0 ; 4587 MB ; 00:00:01 ; +; Fitter ; 00:00:01 ; 1.0 ; 4708 MB ; 00:00:01 ; +; Assembler ; 00:00:00 ; 1.0 ; 4522 MB ; 00:00:00 ; +; TimeQuest Timing Analyzer ; 00:00:01 ; 1.0 ; 4530 MB ; 00:00:00 ; ; Total ; 00:00:04 ; -- ; -- ; 00:00:02 ; +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ diff --git a/cpld/output_files/GR8RAM.jdi b/cpld/output_files/GR8RAM.jdi index 79b2458..58a3c3a 100755 --- a/cpld/output_files/GR8RAM.jdi +++ b/cpld/output_files/GR8RAM.jdi @@ -1,6 +1,6 @@ - + diff --git a/cpld/output_files/GR8RAM.map.rpt b/cpld/output_files/GR8RAM.map.rpt index b226b9b..7dd90f8 100755 --- a/cpld/output_files/GR8RAM.map.rpt +++ b/cpld/output_files/GR8RAM.map.rpt @@ -1,5 +1,5 @@ Analysis & Synthesis report for GR8RAM -Sat Sep 07 22:26:03 2019 +Sun Oct 13 20:54:35 2019 Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition @@ -45,7 +45,7 @@ applicable agreement for further details. +-------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +-----------------------------+-------------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Sat Sep 07 22:26:03 2019 ; +; Analysis & Synthesis Status ; Successful - Sun Oct 13 20:54:35 2019 ; ; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; ; Revision Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ; @@ -331,18 +331,18 @@ Note: In order to hide this table in the UI and the text report file, please set Info: ******************************************************************* Info: Running Quartus II 64-Bit Analysis & Synthesis Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - Info: Processing started: Sat Sep 07 22:26:02 2019 + Info: Processing started: Sun Oct 13 20:54:33 2019 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM Warning (20028): Parallel compilation is not licensed and has been disabled Info (12021): Found 1 design units, including 1 entities, in source file gr8ram.v Info (12023): Found entity 1: GR8RAM Info (12127): Elaborating entity "GR8RAM" for the top level hierarchy Warning (10230): Verilog HDL assignment warning at GR8RAM.v(30): truncated value with size 32 to match size of target (8) -Warning (10230): Verilog HDL assignment warning at GR8RAM.v(133): truncated value with size 32 to match size of target (3) -Warning (10230): Verilog HDL assignment warning at GR8RAM.v(138): truncated value with size 32 to match size of target (4) -Warning (10230): Verilog HDL assignment warning at GR8RAM.v(159): truncated value with size 32 to match size of target (8) +Warning (10230): Verilog HDL assignment warning at GR8RAM.v(127): truncated value with size 32 to match size of target (3) +Warning (10230): Verilog HDL assignment warning at GR8RAM.v(132): truncated value with size 32 to match size of target (4) Warning (10230): Verilog HDL assignment warning at GR8RAM.v(164): truncated value with size 32 to match size of target (8) -Warning (10230): Verilog HDL assignment warning at GR8RAM.v(170): truncated value with size 32 to match size of target (8) +Warning (10230): Verilog HDL assignment warning at GR8RAM.v(169): truncated value with size 32 to match size of target (8) +Warning (10230): Verilog HDL assignment warning at GR8RAM.v(175): truncated value with size 32 to match size of target (8) Info (19000): Inferred 1 megafunctions from design logic Info (19001): Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "Ref_rtl_0" Info (278001): Inferred 4 megafunctions from design logic @@ -369,7 +369,6 @@ Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add0|altshift:r Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add0|altshift:carry_ext_latency_ffs", which is child of megafunction instantiation "lpm_add_sub:Add0" Info (13014): Ignored 32 buffer(s) Info (13019): Ignored 32 SOFT buffer(s) -Info (13000): Registers with preset signals will power-up high Info (280013): Promoted pin-driven signal(s) to global signal Info (280014): Promoted clock signal driven by pin "C7M" to global clock signal Info (280015): Promoted clear signal driven by pin "nRES" to global clear signal @@ -391,8 +390,8 @@ Info (21057): Implemented 168 device resources after synthesis - the final resou Info (144001): Generated suppressed messages file C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 16 warnings Info: Peak virtual memory: 4587 megabytes - Info: Processing ended: Sat Sep 07 22:26:03 2019 - Info: Elapsed time: 00:00:01 + Info: Processing ended: Sun Oct 13 20:54:35 2019 + Info: Elapsed time: 00:00:02 Info: Total CPU time (on all processors): 00:00:01 diff --git a/cpld/output_files/GR8RAM.map.smsg b/cpld/output_files/GR8RAM.map.smsg index be27b32..ec1071c 100755 --- a/cpld/output_files/GR8RAM.map.smsg +++ b/cpld/output_files/GR8RAM.map.smsg @@ -1,3 +1,3 @@ Warning (10273): Verilog HDL warning at GR8RAM.v(52): extended using "x" or "z" Warning (10273): Verilog HDL warning at GR8RAM.v(60): extended using "x" or "z" -Warning (10268): Verilog HDL information at GR8RAM.v(190): always construct contains both blocking and non-blocking assignments +Warning (10268): Verilog HDL information at GR8RAM.v(195): always construct contains both blocking and non-blocking assignments diff --git a/cpld/output_files/GR8RAM.map.summary b/cpld/output_files/GR8RAM.map.summary index 5ff776a..d04376e 100755 --- a/cpld/output_files/GR8RAM.map.summary +++ b/cpld/output_files/GR8RAM.map.summary @@ -1,4 +1,4 @@ -Analysis & Synthesis Status : Successful - Sat Sep 07 22:26:03 2019 +Analysis & Synthesis Status : Successful - Sun Oct 13 20:54:35 2019 Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition Revision Name : GR8RAM Top-level Entity Name : GR8RAM diff --git a/cpld/output_files/GR8RAM.pof b/cpld/output_files/GR8RAM.pof index 12dfa39..3784295 100755 Binary files a/cpld/output_files/GR8RAM.pof and b/cpld/output_files/GR8RAM.pof differ diff --git a/cpld/output_files/GR8RAM.sta.rpt b/cpld/output_files/GR8RAM.sta.rpt index 66f5111..ca44841 100755 --- a/cpld/output_files/GR8RAM.sta.rpt +++ b/cpld/output_files/GR8RAM.sta.rpt @@ -1,5 +1,5 @@ TimeQuest Timing Analyzer report for GR8RAM -Sat Sep 07 22:26:09 2019 +Sun Oct 13 20:54:40 2019 Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition @@ -99,7 +99,7 @@ Parallel compilation was disabled, but you have multiple processors available. E +-----------+-----------------+------------+------+ ; Fmax ; Restricted Fmax ; Clock Name ; Note ; +-----------+-----------------+------------+------+ -; 20.83 MHz ; 20.83 MHz ; C7M ; ; +; 10.42 MHz ; 10.42 MHz ; C7M ; ; +-----------+-----------------+------------+------+ This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. @@ -109,7 +109,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+---------+---------------+ ; Clock ; Slack ; End Point TNS ; +-------+---------+---------------+ -; C7M ; -47.000 ; -2056.000 ; +; C7M ; -47.500 ; -2074.000 ; ; C7M_2 ; -27.500 ; -33.000 ; +-------+---------+---------------+ @@ -151,106 +151,106 @@ No paths to report. +---------+-----------+----------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +---------+-----------+----------+--------------+-------------+--------------+------------+------------+ -; -47.000 ; REGEN ; IncAddrL ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; -; -47.000 ; REGEN ; Addr[0] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; -; -47.000 ; REGEN ; Addr[1] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; -; -47.000 ; REGEN ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; -; -47.000 ; REGEN ; IncAddrH ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; -; -47.000 ; REGEN ; Addr[16] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; -; -47.000 ; REGEN ; Addr[17] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; -; -47.000 ; REGEN ; Addr[9] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; -; -47.000 ; REGEN ; Addr[10] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; -; -47.000 ; REGEN ; Addr[18] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; -; -47.000 ; REGEN ; Addr[2] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; -; -47.000 ; REGEN ; Addr[3] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; -; -47.000 ; REGEN ; Addr[19] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; -; -47.000 ; REGEN ; Addr[11] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; -; -47.000 ; REGEN ; Addr[12] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; -; -47.000 ; REGEN ; Addr[20] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; -; -47.000 ; REGEN ; Addr[4] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; -; -47.000 ; REGEN ; Addr[5] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; -; -47.000 ; REGEN ; Addr[21] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; -; -47.000 ; REGEN ; Addr[13] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; -; -47.000 ; REGEN ; Addr[14] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; -; -47.000 ; REGEN ; Addr[22] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; -; -47.000 ; REGEN ; Addr[6] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; -; -47.000 ; REGEN ; Addr[7] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; -; -47.000 ; REGEN ; Addr[23] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; -; -47.000 ; REGEN ; IncAddrM ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; -; -47.000 ; REGEN ; Addr[8] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; +; -47.500 ; REGEN ; IncAddrL ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; +; -47.500 ; REGEN ; Addr[0] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; +; -47.500 ; REGEN ; Addr[1] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; +; -47.500 ; REGEN ; Addr[15] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; +; -47.500 ; REGEN ; IncAddrH ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; +; -47.500 ; REGEN ; Addr[16] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; +; -47.500 ; REGEN ; Addr[17] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; +; -47.500 ; REGEN ; Addr[9] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; +; -47.500 ; REGEN ; Addr[10] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; +; -47.500 ; REGEN ; Addr[18] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; +; -47.500 ; REGEN ; Addr[2] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; +; -47.500 ; REGEN ; Addr[3] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; +; -47.500 ; REGEN ; Addr[19] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; +; -47.500 ; REGEN ; Addr[11] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; +; -47.500 ; REGEN ; Addr[12] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; +; -47.500 ; REGEN ; Addr[20] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; +; -47.500 ; REGEN ; Addr[4] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; +; -47.500 ; REGEN ; Addr[5] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; +; -47.500 ; REGEN ; Addr[21] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; +; -47.500 ; REGEN ; Addr[13] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; +; -47.500 ; REGEN ; Addr[14] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; +; -47.500 ; REGEN ; Addr[22] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; +; -47.500 ; REGEN ; Addr[6] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; +; -47.500 ; REGEN ; Addr[7] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; +; -47.500 ; REGEN ; Addr[23] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; +; -47.500 ; REGEN ; IncAddrM ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; +; -47.500 ; REGEN ; Addr[8] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; +; -47.500 ; REGEN ; Bank[0] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; +; -47.500 ; REGEN ; Bank[1] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; +; -47.500 ; REGEN ; Bank[2] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; +; -47.500 ; REGEN ; Bank[3] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; +; -47.500 ; REGEN ; Bank[4] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; +; -47.500 ; REGEN ; Bank[5] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; +; -47.500 ; REGEN ; Bank[6] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; +; -47.500 ; REGEN ; Bank[7] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; ; -47.000 ; REGEN ; ASel ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; ; -47.000 ; REGEN ; RASr ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; -; -47.000 ; REGEN ; Bank[0] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; -; -47.000 ; REGEN ; Bank[1] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; -; -47.000 ; REGEN ; Bank[2] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; -; -47.000 ; REGEN ; Bank[3] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; -; -47.000 ; REGEN ; Bank[4] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; -; -47.000 ; REGEN ; Bank[5] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; ; -47.000 ; REGEN ; CAS0r ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; ; -47.000 ; REGEN ; CAS1r ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; -; -47.000 ; REGEN ; Bank[6] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; -; -47.000 ; REGEN ; Bank[7] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; -; -46.000 ; S[2] ; IncAddrH ; C7M ; C7M ; 1.000 ; 0.000 ; 43.000 ; -; -46.000 ; S[2] ; IncAddrM ; C7M ; C7M ; 1.000 ; 0.000 ; 43.000 ; +; -46.500 ; S[2] ; IncAddrH ; C7M ; C7M ; 0.500 ; 0.000 ; 43.000 ; +; -46.500 ; S[2] ; IncAddrM ; C7M ; C7M ; 0.500 ; 0.000 ; 43.000 ; +; -46.500 ; S[1] ; IncAddrH ; C7M ; C7M ; 0.500 ; 0.000 ; 43.000 ; +; -46.500 ; S[1] ; IncAddrM ; C7M ; C7M ; 0.500 ; 0.000 ; 43.000 ; ; -46.000 ; IncAddrM ; IncAddrH ; C7M ; C7M ; 1.000 ; 0.000 ; 43.000 ; -; -46.000 ; S[1] ; IncAddrH ; C7M ; C7M ; 1.000 ; 0.000 ; 43.000 ; -; -46.000 ; S[1] ; IncAddrM ; C7M ; C7M ; 1.000 ; 0.000 ; 43.000 ; -; -25.000 ; S[0] ; REGEN ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; -; -25.000 ; S[2] ; REGEN ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; -; -25.000 ; S[1] ; REGEN ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; -; -25.000 ; S[2] ; CSDBEN ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; -; -25.000 ; IncAddrL ; IncAddrL ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; -; -25.000 ; S[0] ; IncAddrL ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; -; -25.000 ; S[1] ; IncAddrL ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; -; -25.000 ; S[2] ; IncAddrL ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; -; -25.000 ; S[2] ; Addr[0] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; -; -25.000 ; S[1] ; Addr[0] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; -; -25.000 ; S[0] ; Addr[0] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; -; -25.000 ; Addr[0] ; Addr[0] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; -; -25.000 ; IncAddrL ; Addr[0] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; -; -25.000 ; S[2] ; Addr[1] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; -; -25.000 ; S[1] ; Addr[1] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; -; -25.000 ; S[0] ; Addr[1] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; -; -25.000 ; Addr[1] ; Addr[1] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; -; -25.000 ; Addr[0] ; Addr[1] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; -; -25.000 ; IncAddrL ; Addr[1] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; -; -25.000 ; S[1] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; -; -25.000 ; S[2] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; -; -25.000 ; S[0] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; -; -25.000 ; Addr[15] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; -; -25.000 ; IncAddrM ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; -; -25.000 ; Addr[14] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; -; -25.000 ; Addr[13] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; -; -25.000 ; Addr[12] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; -; -25.000 ; Addr[11] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; -; -25.000 ; Addr[10] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; -; -25.000 ; Addr[9] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; -; -25.000 ; Addr[8] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; -; -25.000 ; IncAddrH ; IncAddrH ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; -; -25.000 ; Addr[15] ; IncAddrH ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; -; -25.000 ; S[0] ; IncAddrH ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; -; -25.000 ; Addr[14] ; IncAddrH ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; -; -25.000 ; Addr[13] ; IncAddrH ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; -; -25.000 ; Addr[12] ; IncAddrH ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; -; -25.000 ; Addr[11] ; IncAddrH ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; -; -25.000 ; Addr[10] ; IncAddrH ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; -; -25.000 ; Addr[9] ; IncAddrH ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; -; -25.000 ; Addr[8] ; IncAddrH ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; -; -25.000 ; S[2] ; Addr[16] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; -; -25.000 ; S[1] ; Addr[16] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; -; -25.000 ; S[0] ; Addr[16] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; -; -25.000 ; Addr[16] ; Addr[16] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; -; -25.000 ; IncAddrH ; Addr[16] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; -; -25.000 ; S[2] ; Addr[17] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; -; -25.000 ; S[1] ; Addr[17] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; -; -25.000 ; S[0] ; Addr[17] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; -; -25.000 ; Addr[17] ; Addr[17] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; -; -25.000 ; IncAddrH ; Addr[17] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; -; -25.000 ; Addr[16] ; Addr[17] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; -; -25.000 ; S[1] ; Addr[9] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; -; -25.000 ; S[2] ; Addr[9] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; -; -25.000 ; S[0] ; Addr[9] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; -; -25.000 ; Addr[9] ; Addr[9] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.500 ; Addr[22] ; CAS0r ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; Addr[22] ; CAS1r ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[0] ; IncAddrL ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[1] ; IncAddrL ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[2] ; IncAddrL ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[2] ; Addr[0] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[1] ; Addr[0] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[0] ; Addr[0] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[2] ; Addr[1] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[1] ; Addr[1] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[0] ; Addr[1] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[1] ; Addr[15] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[2] ; Addr[15] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[0] ; Addr[15] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[0] ; IncAddrH ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[2] ; Addr[16] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[1] ; Addr[16] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[0] ; Addr[16] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[2] ; Addr[17] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[1] ; Addr[17] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[0] ; Addr[17] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[1] ; Addr[9] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[2] ; Addr[9] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[0] ; Addr[9] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[1] ; Addr[10] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[2] ; Addr[10] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[0] ; Addr[10] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[2] ; Addr[18] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[1] ; Addr[18] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[0] ; Addr[18] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[2] ; Addr[2] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[1] ; Addr[2] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[0] ; Addr[2] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[2] ; Addr[3] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[1] ; Addr[3] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[0] ; Addr[3] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[2] ; Addr[19] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[1] ; Addr[19] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[0] ; Addr[19] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[1] ; Addr[11] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[2] ; Addr[11] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[0] ; Addr[11] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[1] ; Addr[12] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[2] ; Addr[12] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[0] ; Addr[12] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[2] ; Addr[20] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[1] ; Addr[20] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[0] ; Addr[20] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[2] ; Addr[4] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[1] ; Addr[4] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[0] ; Addr[4] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[2] ; Addr[5] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[1] ; Addr[5] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[0] ; Addr[5] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[2] ; Addr[21] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +; -25.500 ; S[1] ; Addr[21] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; +---------+-----------+----------+--------------+-------------+--------------+------------+------------+ @@ -316,6 +316,9 @@ No paths to report. ; 5.000 ; S[0] ; IOROMEN ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; ; 5.000 ; S[2] ; IOROMEN ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; ; 5.000 ; S[1] ; IOROMEN ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; +; 5.000 ; lpm_counter:Ref_rtl_0|dffs[2] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; +; 5.000 ; lpm_counter:Ref_rtl_0|dffs[1] ; lpm_counter:Ref_rtl_0|dffs[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; +; 5.000 ; lpm_counter:Ref_rtl_0|dffs[0] ; lpm_counter:Ref_rtl_0|dffs[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; ; 5.000 ; Addr[0] ; Addr[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; ; 5.000 ; Addr[1] ; Addr[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; ; 5.000 ; Addr[15] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; @@ -340,63 +343,60 @@ No paths to report. ; 5.000 ; Addr[7] ; Addr[7] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; ; 5.000 ; Addr[23] ; Addr[23] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; ; 5.000 ; Addr[8] ; Addr[8] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; lpm_counter:Ref_rtl_0|dffs[2] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; lpm_counter:Ref_rtl_0|dffs[1] ; lpm_counter:Ref_rtl_0|dffs[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; lpm_counter:Ref_rtl_0|dffs[0] ; lpm_counter:Ref_rtl_0|dffs[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; ; 18.000 ; S[0] ; REGEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; ; 18.000 ; S[2] ; REGEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; ; 18.000 ; S[1] ; REGEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; ; 18.000 ; S[2] ; CSDBEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; lpm_counter:Ref_rtl_0|dffs[3] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; lpm_counter:Ref_rtl_0|dffs[1] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; lpm_counter:Ref_rtl_0|dffs[0] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; S[2] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; S[1] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; S[0] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; lpm_counter:Ref_rtl_0|dffs[3] ; lpm_counter:Ref_rtl_0|dffs[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; lpm_counter:Ref_rtl_0|dffs[0] ; lpm_counter:Ref_rtl_0|dffs[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; lpm_counter:Ref_rtl_0|dffs[2] ; lpm_counter:Ref_rtl_0|dffs[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; S[2] ; lpm_counter:Ref_rtl_0|dffs[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; S[1] ; lpm_counter:Ref_rtl_0|dffs[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; S[0] ; lpm_counter:Ref_rtl_0|dffs[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; lpm_counter:Ref_rtl_0|dffs[1] ; lpm_counter:Ref_rtl_0|dffs[3] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; lpm_counter:Ref_rtl_0|dffs[0] ; lpm_counter:Ref_rtl_0|dffs[3] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; lpm_counter:Ref_rtl_0|dffs[2] ; lpm_counter:Ref_rtl_0|dffs[3] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; lpm_counter:Ref_rtl_0|dffs[3] ; lpm_counter:Ref_rtl_0|dffs[3] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; S[2] ; lpm_counter:Ref_rtl_0|dffs[3] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; S[1] ; lpm_counter:Ref_rtl_0|dffs[3] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; S[0] ; lpm_counter:Ref_rtl_0|dffs[3] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; lpm_counter:Ref_rtl_0|dffs[3] ; lpm_counter:Ref_rtl_0|dffs[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; lpm_counter:Ref_rtl_0|dffs[2] ; lpm_counter:Ref_rtl_0|dffs[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; S[2] ; lpm_counter:Ref_rtl_0|dffs[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; S[1] ; lpm_counter:Ref_rtl_0|dffs[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; S[0] ; lpm_counter:Ref_rtl_0|dffs[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; S[2] ; ASel ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; S[1] ; ASel ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; S[0] ; RASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; S[2] ; RASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; S[1] ; RASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; S[2] ; CAS0r ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; lpm_counter:Ref_rtl_0|dffs[3] ; CAS0r ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; lpm_counter:Ref_rtl_0|dffs[2] ; CAS0r ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; lpm_counter:Ref_rtl_0|dffs[1] ; CAS0r ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; lpm_counter:Ref_rtl_0|dffs[0] ; CAS0r ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; S[1] ; CAS0r ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; S[0] ; CAS0r ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; S[2] ; CAS1r ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; lpm_counter:Ref_rtl_0|dffs[3] ; CAS1r ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; lpm_counter:Ref_rtl_0|dffs[2] ; CAS1r ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; lpm_counter:Ref_rtl_0|dffs[1] ; CAS1r ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; lpm_counter:Ref_rtl_0|dffs[0] ; CAS1r ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; S[1] ; CAS1r ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; S[0] ; CAS1r ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; ; 18.000 ; IncAddrL ; IncAddrL ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; S[0] ; IncAddrL ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; S[1] ; IncAddrL ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; S[2] ; IncAddrL ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; S[2] ; Addr[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; S[1] ; Addr[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; S[0] ; Addr[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; ; 18.000 ; IncAddrL ; Addr[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; S[2] ; Addr[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; S[1] ; Addr[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; S[0] ; Addr[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; ; 18.000 ; Addr[0] ; Addr[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; ; 18.000 ; IncAddrL ; Addr[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; S[1] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; S[2] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; S[0] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; ; 18.000 ; IncAddrM ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; ; 18.000 ; Addr[14] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; ; 18.000 ; Addr[13] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; Addr[12] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; Addr[11] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; Addr[10] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; Addr[9] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; Addr[8] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; S[2] ; IncAddrH ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; S[1] ; IncAddrH ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; IncAddrH ; IncAddrH ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; Addr[15] ; IncAddrH ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; S[0] ; IncAddrH ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; Addr[14] ; IncAddrH ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; Addr[13] ; IncAddrH ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; Addr[12] ; IncAddrH ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; Addr[11] ; IncAddrH ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; Addr[10] ; IncAddrH ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; Addr[9] ; IncAddrH ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; Addr[8] ; IncAddrH ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; IncAddrM ; IncAddrH ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; S[2] ; Addr[16] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; S[1] ; Addr[16] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; S[0] ; Addr[16] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; IncAddrH ; Addr[16] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; S[2] ; Addr[17] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; S[1] ; Addr[17] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; S[0] ; Addr[17] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; IncAddrH ; Addr[17] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; Addr[16] ; Addr[17] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; S[1] ; Addr[9] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; S[2] ; Addr[9] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; S[0] ; Addr[9] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; IncAddrM ; Addr[9] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +--------+-------------------------------+-------------------------------+--------------+-------------+--------------+------------+------------+ @@ -425,86 +425,86 @@ No paths to report. +--------+--------------+----------------+------------------+-------+------------+-------------------------------+ ; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; ASel ; ; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; ASel ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Addr[0] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Addr[0] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Addr[10] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Addr[10] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Addr[11] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Addr[11] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Addr[12] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Addr[12] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Addr[13] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Addr[13] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Addr[14] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Addr[14] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Addr[15] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Addr[15] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Addr[16] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Addr[16] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Addr[17] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Addr[17] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Addr[18] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Addr[18] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Addr[19] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Addr[19] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Addr[1] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Addr[1] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Addr[20] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Addr[20] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Addr[21] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Addr[21] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Addr[22] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Addr[22] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Addr[23] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Addr[23] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Addr[2] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Addr[2] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Addr[3] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Addr[3] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Addr[4] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Addr[4] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Addr[5] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Addr[5] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Addr[6] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Addr[6] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Addr[7] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Addr[7] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Addr[8] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Addr[8] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Addr[9] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Addr[9] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Bank[0] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Bank[0] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Bank[1] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Bank[1] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Bank[2] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Bank[2] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Bank[3] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Bank[3] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Bank[4] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Bank[4] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Bank[5] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Bank[5] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Bank[6] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Bank[6] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Bank[7] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Bank[7] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[0] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[0] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[10] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[10] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[11] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[11] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[12] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[12] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[13] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[13] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[14] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[14] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[15] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[15] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[16] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[16] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[17] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[17] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[18] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[18] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[19] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[19] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[1] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[1] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[20] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[20] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[21] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[21] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[22] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[22] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[23] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[23] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[2] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[2] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[3] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[3] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[4] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[4] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[5] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[5] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[6] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[6] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[7] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[7] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[8] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[8] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[9] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[9] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Bank[0] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Bank[0] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Bank[1] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Bank[1] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Bank[2] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Bank[2] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Bank[3] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Bank[3] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Bank[4] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Bank[4] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Bank[5] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Bank[5] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Bank[6] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Bank[6] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Bank[7] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Bank[7] ; ; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; CAS0r ; ; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; CAS0r ; ; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; CAS1r ; ; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; CAS1r ; ; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; CSDBEN ; ; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; CSDBEN ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; FullIOEN ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; FullIOEN ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; FullIOEN ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; FullIOEN ; ; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; IOROMEN ; ; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; IOROMEN ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; IncAddrH ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; IncAddrH ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; IncAddrL ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; IncAddrL ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; IncAddrM ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; IncAddrM ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; IncAddrH ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; IncAddrH ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; IncAddrL ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; IncAddrL ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; IncAddrM ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; IncAddrM ; ; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; PHI0seen ; ; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; PHI0seen ; ; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; PHI1reg ; @@ -543,20 +543,26 @@ No paths to report. ; A[8] ; C7M ; 11.000 ; 11.000 ; Rise ; C7M ; ; A[9] ; C7M ; 11.000 ; 11.000 ; Rise ; C7M ; ; A[10] ; C7M ; 11.000 ; 11.000 ; Rise ; C7M ; -; D[*] ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ; -; D[0] ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ; -; D[1] ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ; -; D[2] ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ; -; D[3] ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ; -; D[4] ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ; -; D[5] ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ; -; D[6] ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ; -; D[7] ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ; ; PHI1in ; C7M ; 101.000 ; 101.000 ; Rise ; C7M ; ; nDEVSEL ; C7M ; 46.000 ; 46.000 ; Rise ; C7M ; ; nIOSEL ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ; ; nIOSTRB ; C7M ; 11.000 ; 11.000 ; Rise ; C7M ; -; nWE ; C7M ; 46.000 ; 46.000 ; Rise ; C7M ; +; A[*] ; C7M ; 46.000 ; 46.000 ; Fall ; C7M ; +; A[0] ; C7M ; 46.000 ; 46.000 ; Fall ; C7M ; +; A[1] ; C7M ; 46.000 ; 46.000 ; Fall ; C7M ; +; A[2] ; C7M ; 46.000 ; 46.000 ; Fall ; C7M ; +; A[3] ; C7M ; 46.000 ; 46.000 ; Fall ; C7M ; +; D[*] ; C7M ; 24.000 ; 24.000 ; Fall ; C7M ; +; D[0] ; C7M ; 24.000 ; 24.000 ; Fall ; C7M ; +; D[1] ; C7M ; 24.000 ; 24.000 ; Fall ; C7M ; +; D[2] ; C7M ; 24.000 ; 24.000 ; Fall ; C7M ; +; D[3] ; C7M ; 24.000 ; 24.000 ; Fall ; C7M ; +; D[4] ; C7M ; 24.000 ; 24.000 ; Fall ; C7M ; +; D[5] ; C7M ; 24.000 ; 24.000 ; Fall ; C7M ; +; D[6] ; C7M ; 24.000 ; 24.000 ; Fall ; C7M ; +; D[7] ; C7M ; 24.000 ; 24.000 ; Fall ; C7M ; +; nDEVSEL ; C7M ; 46.000 ; 46.000 ; Fall ; C7M ; +; nWE ; C7M ; 46.000 ; 46.000 ; Fall ; C7M ; ; A[*] ; C7M_2 ; 26.000 ; 26.000 ; Fall ; C7M_2 ; ; A[0] ; C7M_2 ; 26.000 ; 26.000 ; Fall ; C7M_2 ; ; A[1] ; C7M_2 ; 26.000 ; 26.000 ; Fall ; C7M_2 ; @@ -584,20 +590,26 @@ No paths to report. ; A[8] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ; ; A[9] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ; ; A[10] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ; -; D[*] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ; -; D[0] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ; -; D[1] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ; -; D[2] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ; -; D[3] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ; -; D[4] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ; -; D[5] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ; -; D[6] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ; -; D[7] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ; ; PHI1in ; C7M ; -12.000 ; -12.000 ; Rise ; C7M ; -; nDEVSEL ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ; +; nDEVSEL ; C7M ; -38.000 ; -38.000 ; Rise ; C7M ; ; nIOSEL ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ; ; nIOSTRB ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ; -; nWE ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ; +; A[*] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ; +; A[0] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ; +; A[1] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ; +; A[2] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ; +; A[3] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ; +; D[*] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ; +; D[0] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ; +; D[1] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ; +; D[2] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ; +; D[3] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ; +; D[4] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ; +; D[5] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ; +; D[6] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ; +; D[7] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ; +; nDEVSEL ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ; +; nWE ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ; ; A[*] ; C7M_2 ; -18.000 ; -18.000 ; Fall ; C7M_2 ; ; A[0] ; C7M_2 ; -18.000 ; -18.000 ; Fall ; C7M_2 ; ; A[1] ; C7M_2 ; -18.000 ; -18.000 ; Fall ; C7M_2 ; @@ -613,15 +625,6 @@ No paths to report. +-----------+------------+--------+--------+------------+-----------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+--------+--------+------------+-----------------+ -; D[*] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; -; D[0] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; -; D[1] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; -; D[2] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; -; D[3] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; -; D[4] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; -; D[5] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; -; D[6] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; -; D[7] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; ; RA[*] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; ; RA[0] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; ; RA[1] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; @@ -638,6 +641,29 @@ No paths to report. ; nCAS1 ; C7M ; 56.000 ; 56.000 ; Rise ; C7M ; ; nRAS ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; ; nRCS ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; +; D[*] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; +; D[0] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; +; D[1] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; +; D[2] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; +; D[3] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; +; D[4] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; +; D[5] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; +; D[6] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; +; D[7] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; +; RA[*] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; +; RA[0] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; +; RA[1] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; +; RA[2] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; +; RA[3] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; +; RA[4] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; +; RA[5] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; +; RA[6] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; +; RA[7] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; +; RA[8] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; +; RA[9] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; +; RA[10] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; +; nCAS0 ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; +; nCAS1 ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; ; nCAS0 ; C7M_2 ; 54.000 ; 54.000 ; Fall ; C7M_2 ; ; nCAS1 ; C7M_2 ; 54.000 ; 54.000 ; Fall ; C7M_2 ; ; nRAS ; C7M_2 ; 54.000 ; 54.000 ; Fall ; C7M_2 ; @@ -649,15 +675,6 @@ No paths to report. +-----------+------------+--------+--------+------------+-----------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+--------+--------+------------+-----------------+ -; D[*] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; -; D[0] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; -; D[1] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; -; D[2] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; -; D[3] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; -; D[4] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; -; D[5] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; -; D[6] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; -; D[7] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; ; RA[*] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; ; RA[0] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; ; RA[1] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; @@ -674,6 +691,29 @@ No paths to report. ; nCAS1 ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; ; nRAS ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; ; nRCS ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; +; D[*] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; +; D[0] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; +; D[1] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; +; D[2] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; +; D[3] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; +; D[4] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; +; D[5] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; +; D[6] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; +; D[7] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; +; RA[*] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; +; RA[0] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; +; RA[1] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; +; RA[2] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; +; RA[3] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; +; RA[4] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; +; RA[5] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; +; RA[6] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; +; RA[7] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; +; RA[8] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; +; RA[9] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; +; RA[10] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; +; nCAS0 ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; +; nCAS1 ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; ; nCAS0 ; C7M_2 ; 54.000 ; 54.000 ; Fall ; C7M_2 ; ; nCAS1 ; C7M_2 ; 54.000 ; 54.000 ; Fall ; C7M_2 ; ; nRAS ; C7M_2 ; 54.000 ; 54.000 ; Fall ; C7M_2 ; @@ -1047,7 +1087,7 @@ No paths to report. +------------+----------+----------+----------+----------+----------+ ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; +------------+----------+----------+----------+----------+----------+ -; C7M ; C7M ; 644 ; 0 ; 0 ; 0 ; +; C7M ; C7M ; 98 ; 2 ; 334 ; 210 ; ; C7M ; C7M_2 ; 0 ; 0 ; 14 ; 0 ; +------------+----------+----------+----------+----------+----------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. @@ -1058,7 +1098,7 @@ Entries labeled "false path" only account for clock-to-clock false paths and not +------------+----------+----------+----------+----------+----------+ ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; +------------+----------+----------+----------+----------+----------+ -; C7M ; C7M ; 644 ; 0 ; 0 ; 0 ; +; C7M ; C7M ; 98 ; 2 ; 334 ; 210 ; ; C7M ; C7M_2 ; 0 ; 0 ; 14 ; 0 ; +------------+----------+----------+----------+----------+----------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. @@ -1096,7 +1136,7 @@ No dedicated SERDES Receiver circuitry present in device or used in design Info: ******************************************************************* Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - Info: Processing started: Sat Sep 07 22:26:08 2019 + Info: Processing started: Sun Oct 13 20:54:39 2019 Info: Command: quartus_sta GR8RAM -c GR8RAM Info: qsta_default_script.tcl version: #1 Warning (20028): Parallel compilation is not licensed and has been disabled @@ -1110,10 +1150,10 @@ Info (332105): Deriving Clocks Info (332105): create_clock -period 1.000 -name C7M_2 C7M_2 Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON Critical Warning (332148): Timing requirements not met -Info (332146): Worst-case setup slack is -47.000 +Info (332146): Worst-case setup slack is -47.500 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== - Info (332119): -47.000 -2056.000 C7M + Info (332119): -47.500 -2074.000 C7M Info (332119): -27.500 -33.000 C7M_2 Info (332146): Worst-case hold slack is -1.500 Info (332119): Slack End Point TNS Clock @@ -1132,8 +1172,8 @@ Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings Info: Peak virtual memory: 4530 megabytes - Info: Processing ended: Sat Sep 07 22:26:09 2019 + Info: Processing ended: Sun Oct 13 20:54:40 2019 Info: Elapsed time: 00:00:01 - Info: Total CPU time (on all processors): 00:00:01 + Info: Total CPU time (on all processors): 00:00:00 diff --git a/cpld/output_files/GR8RAM.sta.summary b/cpld/output_files/GR8RAM.sta.summary index 1163fd8..0c647be 100755 --- a/cpld/output_files/GR8RAM.sta.summary +++ b/cpld/output_files/GR8RAM.sta.summary @@ -3,8 +3,8 @@ TimeQuest Timing Analyzer Summary ------------------------------------------------------------ Type : Setup 'C7M' -Slack : -47.000 -TNS : -2056.000 +Slack : -47.500 +TNS : -2074.000 Type : Setup 'C7M_2' Slack : -27.500