diff --git a/cpld/GR8RAM.qws b/cpld/GR8RAM.qws new file mode 100755 index 0000000..38d1f45 Binary files /dev/null and b/cpld/GR8RAM.qws differ diff --git a/cpld/GR8RAM.v b/cpld/GR8RAM.v index 027eebd..7ddfc23 100644 --- a/cpld/GR8RAM.v +++ b/cpld/GR8RAM.v @@ -19,6 +19,29 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, nRESr <= nRESf[3] || nRESf[2] || nRESf[1] || nRESf[0]; end + /* Firmware select */ + input [1:0] SetFW; + reg [1:0] SetFWr; + reg SetFWLoaded = 0; + always @(posedge C25M) begin + if (~SetFWLoaded) begin + SetFWLoaded <= 1; + SetFWr[1:0] <= SetFW[1:0]; + end + end + wire [1:0] SetROM = ~SetFWr[1:0]; + wire SetEN16MB = SetROM[1:0]==2'b11; + wire SetEN24bit = SetROM[1]; + + /* State counter from PHI0 rising edge */ + reg [3:0] PS = 0; + wire PSStart = PS==0 && PHI0r1 && ~PHI0r2; + always @(posedge C25M) begin + if (PSStart) PS <= 1; + else if (PS==0) PS <= 0; + else PS <= PS+1; + end + /* Long state counter: counts from 0 to $3FFF */ reg [13:0] LS = 0; always @(posedge C25M) begin if (PS==15) LS <= LS+1; end @@ -133,7 +156,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, end end - /* SPI flash */ + /* SPI flash control signals */ output nFCS = FCKOE ? ~FCS : 1'bZ; reg FCS = 0; output FCK = FCKOE ? FCKout : 1'bZ; @@ -141,7 +164,6 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, reg FCKout = 0; inout MOSI = MOSIOE ? MOSIout : 1'bZ; reg MOSIOE = 0; - reg MOSIout = 0; input MISO; always @(posedge C25M) begin case (PS[3:0]) @@ -184,6 +206,8 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, FCKOE <= IS==1 || IS==4 || IS==5 || IS==6 || IS==7; end + /* SPI flash MOSI control */ + reg MOSIout = 0; always @(posedge C25M) begin case (PS[3:0]) 1: begin @@ -254,11 +278,6 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, endcase end - input [1:0] SetFW; - wire [1:0] SetROM = ~SetFW[1:0]; - wire SetEN16MB = SetROM[1:0]==2'b11; - wire SetEN24bit = SetROM[1]; - /* SDRAM data bus */ inout [7:0] SD = SDOE ? WRD[7:0] : 8'bZ; reg [7:0] WRD; @@ -305,15 +324,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, endcase end - reg [3:0] PS = 0; - wire PSStart = PS==0 && PHI0r1 && ~PHI0r2; - always @(posedge C25M) begin - if (PSStart) PS <= 1; - else if (PS==0) PS <= 0; - else PS <= PS+1; - end - - /* SDRAM address/command */ + /* SDRAM command */ output reg RCKE = 1; output reg nRCS = 1; output reg nRAS = 1; @@ -416,6 +427,8 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, end endcase end + + /* SDRAM address */ output reg DQML = 1; output reg DQMH = 1; output reg [1:0] SBA; diff --git a/cpld/db/GR8RAM.(0).cnf.cdb b/cpld/db/GR8RAM.(0).cnf.cdb index 214d760..2880c4f 100755 Binary files a/cpld/db/GR8RAM.(0).cnf.cdb and b/cpld/db/GR8RAM.(0).cnf.cdb differ diff --git a/cpld/db/GR8RAM.(0).cnf.hdb b/cpld/db/GR8RAM.(0).cnf.hdb index 3d61b3a..47938f6 100755 Binary files a/cpld/db/GR8RAM.(0).cnf.hdb and b/cpld/db/GR8RAM.(0).cnf.hdb differ diff --git a/cpld/db/GR8RAM.asm.qmsg b/cpld/db/GR8RAM.asm.qmsg index ba79548..06f5488 100755 --- a/cpld/db/GR8RAM.asm.qmsg +++ b/cpld/db/GR8RAM.asm.qmsg @@ -1,6 +1,6 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618905619262 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618905619262 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 04:00:18 2021 " "Processing started: Tue Apr 20 04:00:18 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618905619262 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1618905619262 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1618905619262 ""} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1618905620434 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1618905620465 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "293 " "Peak virtual memory: 293 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618905620872 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 04:00:20 2021 " "Processing ended: Tue Apr 20 04:00:20 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618905620872 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618905620872 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618905620872 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1618905620872 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618906796813 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618906796829 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 04:19:56 2021 " "Processing started: Tue Apr 20 04:19:56 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618906796829 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1618906796829 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1618906796829 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1618906798235 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1618906798282 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "293 " "Peak virtual memory: 293 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618906799032 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 04:19:59 2021 " "Processing ended: Tue Apr 20 04:19:59 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618906799032 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618906799032 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618906799032 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1618906799032 ""} diff --git a/cpld/db/GR8RAM.asm.rdb b/cpld/db/GR8RAM.asm.rdb index 476ad5b..2dcb4e1 100755 Binary files a/cpld/db/GR8RAM.asm.rdb and b/cpld/db/GR8RAM.asm.rdb differ diff --git a/cpld/db/GR8RAM.asm_labs.ddb b/cpld/db/GR8RAM.asm_labs.ddb index 1eadc87..8480148 100755 Binary files a/cpld/db/GR8RAM.asm_labs.ddb and b/cpld/db/GR8RAM.asm_labs.ddb differ diff --git a/cpld/db/GR8RAM.cmp.cdb b/cpld/db/GR8RAM.cmp.cdb index 0fb5a27..f41e376 100755 Binary files a/cpld/db/GR8RAM.cmp.cdb and b/cpld/db/GR8RAM.cmp.cdb differ diff --git a/cpld/db/GR8RAM.cmp.hdb b/cpld/db/GR8RAM.cmp.hdb index d0774b5..70fb348 100755 Binary files a/cpld/db/GR8RAM.cmp.hdb and b/cpld/db/GR8RAM.cmp.hdb differ diff --git a/cpld/db/GR8RAM.cmp.idb b/cpld/db/GR8RAM.cmp.idb index faf24da..0379a24 100755 Binary files a/cpld/db/GR8RAM.cmp.idb and b/cpld/db/GR8RAM.cmp.idb differ diff --git a/cpld/db/GR8RAM.cmp.rdb b/cpld/db/GR8RAM.cmp.rdb index 4918a28..096f455 100755 Binary files a/cpld/db/GR8RAM.cmp.rdb and b/cpld/db/GR8RAM.cmp.rdb differ diff --git a/cpld/db/GR8RAM.cmp0.ddb b/cpld/db/GR8RAM.cmp0.ddb index 9496680..443cfd1 100755 Binary files a/cpld/db/GR8RAM.cmp0.ddb and b/cpld/db/GR8RAM.cmp0.ddb differ diff --git a/cpld/db/GR8RAM.fit.qmsg b/cpld/db/GR8RAM.fit.qmsg index 6352083..5e214cc 100755 --- a/cpld/db/GR8RAM.fit.qmsg +++ b/cpld/db/GR8RAM.fit.qmsg @@ -1,39 +1,39 @@ -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1618905610825 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1618905610856 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618905611950 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618905611950 ""} -{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1618905612184 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1618905612231 ""} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618905612559 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618905612559 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618905612559 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618905612559 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618905612559 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1618905612559 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1618905612731 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1618905612731 ""} -{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1618905612747 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1618905612747 ""} -{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618905612747 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618905612747 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 C25M " " 1.000 C25M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618905612747 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI0 " " 1.000 PHI0" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618905612747 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1618905612747 ""} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618905612762 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618905612762 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618905612762 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618905612778 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI0 Global clock " "Automatically promoted some destinations of signal \"PHI0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~1 " "Destination \"comb~1\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618905612778 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI0r1 " "Destination \"PHI0r1\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618905612778 ""} } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618905612778 ""} -{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI0 " "Pin \"PHI0\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI0 } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "PHI0" } } } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 376 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1618905612794 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "nRESr Global clock " "Automatically promoted signal \"nRESr\" to use Global clock" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 16 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618905612794 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618905612794 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1618905612794 ""} -{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1618905612841 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1618905612934 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1618905612950 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1618905612950 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1618905612950 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618905612997 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1618905613309 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618905613637 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1618905613653 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1618905615075 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618905615075 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1618905615122 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "34 " "Router estimated average interconnect usage is 34% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "34 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1618905615637 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1618905615637 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618905616215 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.45 " "Total time spent on timing analysis during the Fitter is 0.45 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1618905616231 ""} -{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618905616231 ""} -{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1618905616262 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1618905616575 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "382 " "Peak virtual memory: 382 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618905616794 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 04:00:16 2021 " "Processing ended: Tue Apr 20 04:00:16 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618905616794 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618905616794 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618905616794 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1618905616794 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1618906787984 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1618906788015 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618906788219 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618906788219 ""} +{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1618906788531 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1618906788562 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618906788906 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618906788906 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618906788906 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618906788906 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618906788906 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1618906788906 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1618906789062 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1618906789062 ""} +{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1618906789078 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1618906789078 ""} +{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618906789078 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618906789078 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 C25M " " 1.000 C25M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618906789078 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI0 " " 1.000 PHI0" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618906789078 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1618906789078 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618906789094 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618906789094 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618906789094 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618906789125 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI0 Global clock " "Automatically promoted some destinations of signal \"PHI0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~1 " "Destination \"comb~1\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618906789140 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI0r1 " "Destination \"PHI0r1\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618906789140 ""} } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618906789140 ""} +{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI0 " "Pin \"PHI0\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI0 } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "PHI0" } } } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 379 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1618906789140 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "nRESr Global clock " "Automatically promoted signal \"nRESr\" to use Global clock" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 16 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618906789140 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618906789140 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1618906789140 ""} +{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1618906789203 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1618906789265 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1618906789265 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1618906789281 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1618906789281 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618906789328 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1618906789531 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618906790203 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1618906790234 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1618906791859 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:02 " "Fitter placement operations ending: elapsed time is 00:00:02" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618906791859 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1618906791922 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "36 " "Router estimated average interconnect usage is 36% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "36 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 36% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 36% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 36% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1618906792469 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1618906792469 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618906793250 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.56 " "Total time spent on timing analysis during the Fitter is 0.56 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1618906793281 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618906793281 ""} +{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1618906793344 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1618906793750 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "382 " "Peak virtual memory: 382 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618906794016 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 04:19:53 2021 " "Processing ended: Tue Apr 20 04:19:53 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618906794016 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618906794016 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618906794016 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1618906794016 ""} diff --git a/cpld/db/GR8RAM.hier_info b/cpld/db/GR8RAM.hier_info index 8bc9544..053429c 100755 --- a/cpld/db/GR8RAM.hier_info +++ b/cpld/db/GR8RAM.hier_info @@ -22,10 +22,6 @@ C25M => nCAS~reg0.CLK C25M => nRAS~reg0.CLK C25M => nRCS~reg0.CLK C25M => RCKE~reg0.CLK -C25M => PS[0].CLK -C25M => PS[1].CLK -C25M => PS[2].CLK -C25M => PS[3].CLK C25M => RDD[0].CLK C25M => RDD[1].CLK C25M => RDD[2].CLK @@ -92,6 +88,13 @@ C25M => LS[10].CLK C25M => LS[11].CLK C25M => LS[12].CLK C25M => LS[13].CLK +C25M => PS[0].CLK +C25M => PS[1].CLK +C25M => PS[2].CLK +C25M => PS[3].CLK +C25M => SetFWr[0].CLK +C25M => SetFWr[1].CLK +C25M => SetFWLoaded.CLK C25M => nRESr.CLK C25M => nRESf[0].CLK C25M => nRESf[1].CLK @@ -108,19 +111,8 @@ PHI0 => PHI0r1.DATAIN nRES => nRESf[0].DATAIN nRES => IOROMRES.IN1 nRESout <= nRESout~reg0.DB_MAX_OUTPUT_PORT_TYPE -SetFW[0] => Mux1.IN10 -SetFW[0] => Equal17.IN1 -SetFW[1] => comb.IN1 -SetFW[1] => RDD.OUTPUTSELECT -SetFW[1] => RDD.OUTPUTSELECT -SetFW[1] => RDD.OUTPUTSELECT -SetFW[1] => RDD.OUTPUTSELECT -SetFW[1] => SA.OUTPUTSELECT -SetFW[1] => SA.OUTPUTSELECT -SetFW[1] => SA.OUTPUTSELECT -SetFW[1] => SBA.OUTPUTSELECT -SetFW[1] => MOSIout.DATAB -SetFW[1] => Equal17.IN0 +SetFW[0] => SetFWr[0].DATAIN +SetFW[1] => SetFWr[1].DATAIN INTin => INTout.DATAIN INTout <= INTin.DB_MAX_OUTPUT_PORT_TYPE DMAin => DMAout.DATAIN @@ -132,60 +124,60 @@ nINHout <= RWout <= nDMAout <= RA[0] => DQML.DATAA -RA[0] => Equal8.IN3 -RA[0] => Equal9.IN3 -RA[0] => Equal10.IN2 +RA[0] => Equal10.IN3 RA[0] => Equal11.IN3 -RA[0] => Equal12.IN3 -RA[0] => Equal13.IN10 +RA[0] => Equal12.IN2 +RA[0] => Equal13.IN3 +RA[0] => Equal14.IN3 +RA[0] => Equal15.IN10 RA[0] => DQMH.DATAA RA[1] => SA.DATAA -RA[1] => Equal8.IN2 -RA[1] => Equal9.IN2 -RA[1] => Equal10.IN3 +RA[1] => Equal10.IN2 RA[1] => Equal11.IN2 -RA[1] => Equal12.IN2 -RA[1] => Equal13.IN9 +RA[1] => Equal12.IN3 +RA[1] => Equal13.IN2 +RA[1] => Equal14.IN2 +RA[1] => Equal15.IN9 RA[2] => SA.DATAA -RA[2] => Equal8.IN1 -RA[2] => Equal9.IN1 RA[2] => Equal10.IN1 RA[2] => Equal11.IN1 RA[2] => Equal12.IN1 -RA[2] => Equal13.IN8 +RA[2] => Equal13.IN1 +RA[2] => Equal14.IN1 +RA[2] => Equal15.IN8 RA[3] => SA.DATAA -RA[3] => Equal8.IN0 -RA[3] => Equal9.IN0 RA[3] => Equal10.IN0 RA[3] => Equal11.IN0 RA[3] => Equal12.IN0 -RA[3] => Equal13.IN7 +RA[3] => Equal13.IN0 +RA[3] => Equal14.IN0 +RA[3] => Equal15.IN7 RA[4] => SA.DATAA -RA[4] => Equal13.IN6 +RA[4] => Equal15.IN6 RA[5] => SA.DATAA -RA[5] => Equal13.IN5 +RA[5] => Equal15.IN5 RA[6] => SA.DATAA -RA[6] => Equal13.IN4 +RA[6] => Equal15.IN4 RA[7] => comb.IN1 RA[7] => SA.DATAA -RA[7] => Equal13.IN3 +RA[7] => Equal15.IN3 RA[8] => SA.DATAA -RA[8] => Equal7.IN3 -RA[8] => Equal13.IN2 +RA[8] => Equal9.IN3 +RA[8] => Equal15.IN2 RA[9] => SA.DATAA -RA[9] => Equal7.IN2 -RA[9] => Equal13.IN1 +RA[9] => Equal9.IN2 +RA[9] => Equal15.IN1 RA[10] => SA.DATAA -RA[10] => Equal7.IN1 -RA[10] => Equal13.IN0 +RA[10] => Equal9.IN1 +RA[10] => Equal15.IN0 RA[11] => comb.IN1 RA[11] => SA.DATAA RA[11] => comb.IN1 -RA[11] => Equal7.IN0 -RA[12] => Equal6.IN1 -RA[13] => Equal6.IN0 -RA[14] => Equal6.IN3 -RA[15] => Equal6.IN2 +RA[11] => Equal9.IN0 +RA[12] => Equal8.IN1 +RA[13] => Equal8.IN0 +RA[14] => Equal8.IN3 +RA[15] => Equal8.IN2 nWE => comb.IN1 nWE => comb.IN1 nWE => nWEr.DATAIN @@ -200,7 +192,7 @@ RD[7] <> RD[7] RAdir <= RDdir <= comb.DB_MAX_OUTPUT_PORT_TYPE nIOSEL => comb.IN0 -nIOSEL => always5.IN1 +nIOSEL => always7.IN1 nDEVSEL => comb.IN1 nDEVSEL => RAMSEL.IN1 nDEVSEL => comb.IN1 diff --git a/cpld/db/GR8RAM.hif b/cpld/db/GR8RAM.hif index 811c603..40796d9 100755 Binary files a/cpld/db/GR8RAM.hif and b/cpld/db/GR8RAM.hif differ diff --git a/cpld/db/GR8RAM.map.cdb b/cpld/db/GR8RAM.map.cdb index 8f5f177..e81467b 100755 Binary files a/cpld/db/GR8RAM.map.cdb and b/cpld/db/GR8RAM.map.cdb differ diff --git a/cpld/db/GR8RAM.map.hdb b/cpld/db/GR8RAM.map.hdb index 8604a63..cbc9472 100755 Binary files a/cpld/db/GR8RAM.map.hdb and b/cpld/db/GR8RAM.map.hdb differ diff --git a/cpld/db/GR8RAM.map.qmsg b/cpld/db/GR8RAM.map.qmsg index 7e1b66f..3b9d01c 100755 --- a/cpld/db/GR8RAM.map.qmsg +++ b/cpld/db/GR8RAM.map.qmsg @@ -1,19 +1,19 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618905600638 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618905600654 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 04:00:00 2021 " "Processing started: Tue Apr 20 04:00:00 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618905600654 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618905600654 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618905600654 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1618905602575 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(83) " "Verilog HDL warning at GR8RAM.v(83): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 83 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618905602903 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(263) " "Verilog HDL warning at GR8RAM.v(263): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 263 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618905602903 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1618905602903 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1618905602903 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1618905603013 ""} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(24) " "Verilog HDL assignment warning at GR8RAM.v(24): truncated value with size 32 to match size of target (14)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 24 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618905603013 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(107) " "Verilog HDL assignment warning at GR8RAM.v(107): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 107 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618905603013 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(115) " "Verilog HDL assignment warning at GR8RAM.v(115): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 115 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618905603013 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(122) " "Verilog HDL assignment warning at GR8RAM.v(122): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 122 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618905603013 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(313) " "Verilog HDL assignment warning at GR8RAM.v(313): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 313 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618905603013 "|GR8RAM"} -{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 -1 1618905605060 ""} -{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "nNMIout VCC " "Pin \"nNMIout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 540 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618905605482 "|GR8RAM|nNMIout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nIRQout VCC " "Pin \"nIRQout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 543 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618905605482 "|GR8RAM|nIRQout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nRDYout VCC " "Pin \"nRDYout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 542 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618905605482 "|GR8RAM|nRDYout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nINHout VCC " "Pin \"nINHout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 541 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618905605482 "|GR8RAM|nINHout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RWout VCC " "Pin \"RWout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 544 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618905605482 "|GR8RAM|RWout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nDMAout VCC " "Pin \"nDMAout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 539 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618905605482 "|GR8RAM|nDMAout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 538 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618905605482 "|GR8RAM|RAdir"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1618905605482 ""} -{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1618905605997 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "319 " "Implemented 319 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "28 " "Implemented 28 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1618905606044 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1618905606044 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1618905606044 ""} { "Info" "ICUT_CUT_TM_LCELLS" "239 " "Implemented 239 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1618905606044 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1618905606044 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1618905606294 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 13 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 13 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "301 " "Peak virtual memory: 301 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618905606450 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 04:00:06 2021 " "Processing ended: Tue Apr 20 04:00:06 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618905606450 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618905606450 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618905606450 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618905606450 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618906780187 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618906780202 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 04:19:39 2021 " "Processing started: Tue Apr 20 04:19:39 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618906780202 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618906780202 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618906780202 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1618906781718 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(106) " "Verilog HDL warning at GR8RAM.v(106): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 106 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618906781890 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(282) " "Verilog HDL warning at GR8RAM.v(282): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 282 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618906781890 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1618906781905 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1618906781905 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1618906782030 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(42) " "Verilog HDL assignment warning at GR8RAM.v(42): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 42 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618906782062 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(47) " "Verilog HDL assignment warning at GR8RAM.v(47): truncated value with size 32 to match size of target (14)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 47 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618906782062 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(130) " "Verilog HDL assignment warning at GR8RAM.v(130): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 130 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618906782062 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(138) " "Verilog HDL assignment warning at GR8RAM.v(138): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 138 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618906782062 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(145) " "Verilog HDL assignment warning at GR8RAM.v(145): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 145 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618906782062 "|GR8RAM"} +{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 -1 1618906783140 ""} +{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "nNMIout VCC " "Pin \"nNMIout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 553 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618906783406 "|GR8RAM|nNMIout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nIRQout VCC " "Pin \"nIRQout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 556 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618906783406 "|GR8RAM|nIRQout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nRDYout VCC " "Pin \"nRDYout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 555 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618906783406 "|GR8RAM|nRDYout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nINHout VCC " "Pin \"nINHout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 554 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618906783406 "|GR8RAM|nINHout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RWout VCC " "Pin \"RWout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 557 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618906783406 "|GR8RAM|RWout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nDMAout VCC " "Pin \"nDMAout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 552 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618906783406 "|GR8RAM|nDMAout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 551 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618906783406 "|GR8RAM|RAdir"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1618906783406 ""} +{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1618906783906 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "321 " "Implemented 321 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "28 " "Implemented 28 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1618906783968 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1618906783968 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1618906783968 ""} { "Info" "ICUT_CUT_TM_LCELLS" "241 " "Implemented 241 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1618906783968 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1618906783968 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1618906784124 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 13 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 13 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "301 " "Peak virtual memory: 301 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618906784281 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 04:19:44 2021 " "Processing ended: Tue Apr 20 04:19:44 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618906784281 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618906784281 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618906784281 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618906784281 ""} diff --git a/cpld/db/GR8RAM.map.rdb b/cpld/db/GR8RAM.map.rdb index 7cbfe41..470a060 100755 Binary files a/cpld/db/GR8RAM.map.rdb and b/cpld/db/GR8RAM.map.rdb differ diff --git a/cpld/db/GR8RAM.pre_map.hdb b/cpld/db/GR8RAM.pre_map.hdb index ff98bc3..f432588 100755 Binary files a/cpld/db/GR8RAM.pre_map.hdb and b/cpld/db/GR8RAM.pre_map.hdb differ diff --git a/cpld/db/GR8RAM.quiproj.3068.rdr.flock b/cpld/db/GR8RAM.quiproj.3068.rdr.flock deleted file mode 100755 index e69de29..0000000 diff --git a/cpld/db/GR8RAM.root_partition.map.reg_db.cdb b/cpld/db/GR8RAM.root_partition.map.reg_db.cdb index c8f31e4..01bfaa7 100755 Binary files a/cpld/db/GR8RAM.root_partition.map.reg_db.cdb and b/cpld/db/GR8RAM.root_partition.map.reg_db.cdb differ diff --git a/cpld/db/GR8RAM.routing.rdb b/cpld/db/GR8RAM.routing.rdb index 7e61603..7b34f68 100755 Binary files a/cpld/db/GR8RAM.routing.rdb and b/cpld/db/GR8RAM.routing.rdb differ diff --git a/cpld/db/GR8RAM.rtlv.hdb b/cpld/db/GR8RAM.rtlv.hdb index bcdf76e..a6820cf 100755 Binary files a/cpld/db/GR8RAM.rtlv.hdb and b/cpld/db/GR8RAM.rtlv.hdb differ diff --git a/cpld/db/GR8RAM.rtlv_sg.cdb b/cpld/db/GR8RAM.rtlv_sg.cdb index eef323f..272dde8 100755 Binary files a/cpld/db/GR8RAM.rtlv_sg.cdb and b/cpld/db/GR8RAM.rtlv_sg.cdb differ diff --git a/cpld/db/GR8RAM.sgdiff.cdb b/cpld/db/GR8RAM.sgdiff.cdb index cd286f3..7d0bd18 100755 Binary files a/cpld/db/GR8RAM.sgdiff.cdb and b/cpld/db/GR8RAM.sgdiff.cdb differ diff --git a/cpld/db/GR8RAM.sgdiff.hdb b/cpld/db/GR8RAM.sgdiff.hdb index a6a0ab3..58f1cf6 100755 Binary files a/cpld/db/GR8RAM.sgdiff.hdb and b/cpld/db/GR8RAM.sgdiff.hdb differ diff --git a/cpld/db/GR8RAM.sta.qmsg b/cpld/db/GR8RAM.sta.qmsg index 6b89ed7..38a0971 100755 --- a/cpld/db/GR8RAM.sta.qmsg +++ b/cpld/db/GR8RAM.sta.qmsg @@ -1,23 +1,23 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618905623543 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618905623559 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 04:00:22 2021 " "Processing started: Tue Apr 20 04:00:22 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618905623559 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618905623559 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618905623559 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1618905623762 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1618905624590 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618905624746 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618905624746 ""} -{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1618905624934 ""} -{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1618905625418 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1618905625559 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1618905625559 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C25M C25M " "create_clock -period 1.000 -name C25M C25M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618905625559 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI0 PHI0 " "create_clock -period 1.000 -name PHI0 PHI0" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618905625559 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618905625559 ""} -{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1618905625574 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1618905625668 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -9.480 " "Worst-case setup slack is -9.480" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905625668 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905625668 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.480 -695.573 C25M " " -9.480 -695.573 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905625668 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.522 -0.522 PHI0 " " -0.522 -0.522 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905625668 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618905625668 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.197 " "Worst-case hold slack is -0.197" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905625684 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905625684 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.197 -0.197 PHI0 " " -0.197 -0.197 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905625684 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.385 0.000 C25M " " 1.385 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905625684 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618905625684 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -4.399 " "Worst-case recovery slack is -4.399" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905625699 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905625699 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.399 -127.571 C25M " " -4.399 -127.571 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905625699 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618905625699 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "removal 4.845 " "Worst-case removal slack is 4.845" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905625699 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905625699 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.845 0.000 C25M " " 4.845 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905625699 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618905625699 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.289 " "Worst-case minimum pulse width slack is -2.289" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905625715 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905625715 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 C25M " " -2.289 -2.289 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905625715 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI0 " " -2.289 -2.289 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905625715 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618905625715 ""} -{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1618905625887 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618905625996 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618905625996 ""} -{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "278 " "Peak virtual memory: 278 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618905626246 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 04:00:26 2021 " "Processing ended: Tue Apr 20 04:00:26 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618905626246 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618905626246 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618905626246 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618905626246 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618906802095 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618906802110 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 04:20:00 2021 " "Processing started: Tue Apr 20 04:20:00 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618906802110 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618906802110 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618906802110 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1618906802314 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1618906803173 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618906803329 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618906803329 ""} +{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1618906803517 ""} +{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1618906804204 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1618906804392 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1618906804407 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C25M C25M " "create_clock -period 1.000 -name C25M C25M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804407 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI0 PHI0 " "create_clock -period 1.000 -name PHI0 PHI0" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804407 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804407 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1618906804423 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1618906804595 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -9.005 " "Worst-case setup slack is -9.005" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804611 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804611 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.005 -699.357 C25M " " -9.005 -699.357 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804611 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.425 -0.425 PHI0 " " -0.425 -0.425 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804611 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618906804611 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.248 " "Worst-case hold slack is -0.248" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804642 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804642 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.248 -0.248 PHI0 " " -0.248 -0.248 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804642 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.400 0.000 C25M " " 1.400 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804642 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618906804642 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -4.412 " "Worst-case recovery slack is -4.412" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804657 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804657 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.412 -127.948 C25M " " -4.412 -127.948 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804657 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618906804657 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "removal 4.858 " "Worst-case removal slack is 4.858" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804673 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804673 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.858 0.000 C25M " " 4.858 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804673 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618906804673 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.289 " "Worst-case minimum pulse width slack is -2.289" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804673 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804673 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 C25M " " -2.289 -2.289 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804673 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI0 " " -2.289 -2.289 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804673 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618906804673 ""} +{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1618906804876 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618906804986 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618906804986 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "278 " "Peak virtual memory: 278 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618906805220 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 04:20:05 2021 " "Processing ended: Tue Apr 20 04:20:05 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618906805220 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618906805220 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618906805220 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618906805220 ""} diff --git a/cpld/db/GR8RAM.sta.rdb b/cpld/db/GR8RAM.sta.rdb index 84c82eb..3578a35 100755 Binary files a/cpld/db/GR8RAM.sta.rdb and b/cpld/db/GR8RAM.sta.rdb differ diff --git a/cpld/db/GR8RAM.sta_cmp.5_slow.tdb b/cpld/db/GR8RAM.sta_cmp.5_slow.tdb index fbbe557..905feea 100755 Binary files a/cpld/db/GR8RAM.sta_cmp.5_slow.tdb and b/cpld/db/GR8RAM.sta_cmp.5_slow.tdb differ diff --git a/cpld/db/GR8RAM.tmw_info b/cpld/db/GR8RAM.tmw_info index 05b4338..51a8f52 100755 --- a/cpld/db/GR8RAM.tmw_info +++ b/cpld/db/GR8RAM.tmw_info @@ -1,6 +1,6 @@ start_full_compilation:s:00:00:28 -start_analysis_synthesis:s:00:00:08-start_full_compilation +start_analysis_synthesis:s:00:00:07-start_full_compilation start_analysis_elaboration:s-start_full_compilation start_fitter:s:00:00:10-start_full_compilation start_assembler:s:00:00:04-start_full_compilation -start_timing_analyzer:s:00:00:06-start_full_compilation +start_timing_analyzer:s:00:00:07-start_full_compilation diff --git a/cpld/db/GR8RAM.vpr.ammdb b/cpld/db/GR8RAM.vpr.ammdb index 7212bd8..c0ccc6d 100755 Binary files a/cpld/db/GR8RAM.vpr.ammdb and b/cpld/db/GR8RAM.vpr.ammdb differ diff --git a/cpld/db/logic_util_heursitic.dat b/cpld/db/logic_util_heursitic.dat index 6f3db1c..8fab785 100755 Binary files a/cpld/db/logic_util_heursitic.dat and b/cpld/db/logic_util_heursitic.dat differ diff --git a/cpld/db/prev_cmp_GR8RAM.qmsg b/cpld/db/prev_cmp_GR8RAM.qmsg index 9ed85c4..857f1ce 100755 --- a/cpld/db/prev_cmp_GR8RAM.qmsg +++ b/cpld/db/prev_cmp_GR8RAM.qmsg @@ -1,96 +1,95 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618905490360 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618905490376 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 03:58:08 2021 " "Processing started: Tue Apr 20 03:58:08 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618905490376 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618905490376 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618905490376 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1618905491798 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(83) " "Verilog HDL warning at GR8RAM.v(83): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 83 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618905491985 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(263) " "Verilog HDL warning at GR8RAM.v(263): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 263 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618905491985 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1618905491985 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1618905491985 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1618905492110 ""} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(24) " "Verilog HDL assignment warning at GR8RAM.v(24): truncated value with size 32 to match size of target (14)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 24 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618905492110 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(107) " "Verilog HDL assignment warning at GR8RAM.v(107): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 107 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618905492110 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(115) " "Verilog HDL assignment warning at GR8RAM.v(115): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 115 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618905492110 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(122) " "Verilog HDL assignment warning at GR8RAM.v(122): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 122 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618905492110 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(313) " "Verilog HDL assignment warning at GR8RAM.v(313): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 313 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618905492126 "|GR8RAM"} -{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 -1 1618905493501 ""} -{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "nNMIout VCC " "Pin \"nNMIout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 540 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618905493798 "|GR8RAM|nNMIout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nIRQout VCC " "Pin \"nIRQout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 543 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618905493798 "|GR8RAM|nIRQout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nRDYout VCC " "Pin \"nRDYout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 542 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618905493798 "|GR8RAM|nRDYout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nINHout VCC " "Pin \"nINHout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 541 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618905493798 "|GR8RAM|nINHout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RWout VCC " "Pin \"RWout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 544 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618905493798 "|GR8RAM|RWout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nDMAout VCC " "Pin \"nDMAout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 539 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618905493798 "|GR8RAM|nDMAout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 538 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618905493798 "|GR8RAM|RAdir"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1618905493798 ""} -{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1618905494188 ""} -{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SetFW\[0\] " "No output dependent on input pin \"SetFW\[0\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 257 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1618905494251 "|GR8RAM|SetFW[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SetFW\[1\] " "No output dependent on input pin \"SetFW\[1\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 257 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1618905494251 "|GR8RAM|SetFW[1]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1618905494251 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "311 " "Implemented 311 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "28 " "Implemented 28 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1618905494266 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1618905494266 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1618905494266 ""} { "Info" "ICUT_CUT_TM_LCELLS" "231 " "Implemented 231 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1618905494266 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1618905494266 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1618905494720 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 16 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 16 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "301 " "Peak virtual memory: 301 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618905495032 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 03:58:14 2021 " "Processing ended: Tue Apr 20 03:58:14 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618905495032 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618905495032 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618905495032 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618905495032 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618905504408 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 32-bit " "Running Quartus II 32-bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618905504423 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 03:58:23 2021 " "Processing started: Tue Apr 20 03:58:23 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618905504423 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1618905504423 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1618905504423 ""} -{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1618905504579 ""} -{ "Info" "0" "" "Project = GR8RAM" { } { } 0 0 "Project = GR8RAM" 0 0 "Fitter" 0 0 1618905504579 ""} -{ "Info" "0" "" "Revision = GR8RAM" { } { } 0 0 "Revision = GR8RAM" 0 0 "Fitter" 0 0 1618905504579 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1618905505423 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1618905505454 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618905507220 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618905507220 ""} -{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1618905510158 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1618905510205 ""} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618905510736 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618905510736 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618905510736 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618905510736 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618905510736 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1618905510736 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1618905511142 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1618905511158 ""} -{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1618905511158 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1618905511158 ""} -{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618905511173 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618905511173 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 C25M " " 1.000 C25M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618905511173 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI0 " " 1.000 PHI0" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618905511173 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1618905511173 ""} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618905511173 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618905511173 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618905511173 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618905511189 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI0 Global clock " "Automatically promoted some destinations of signal \"PHI0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~1 " "Destination \"comb~1\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618905511189 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI0r1 " "Destination \"PHI0r1\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618905511189 ""} } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618905511189 ""} -{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI0 " "Pin \"PHI0\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI0 } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "PHI0" } } } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 375 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1618905511205 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "nRESr Global clock " "Automatically promoted signal \"nRESr\" to use Global clock" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 16 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618905511205 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618905511205 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1618905511205 ""} -{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1618905511236 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1618905511298 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1618905511298 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1618905511298 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1618905511298 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618905511330 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1618905511970 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618905512283 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1618905512314 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1618905513392 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618905513392 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1618905513455 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "29 " "Router estimated average interconnect usage is 29% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "29 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 29% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 29% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 29% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1618905513908 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1618905513908 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618905514439 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.53 " "Total time spent on timing analysis during the Fitter is 0.53 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1618905514455 ""} -{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618905514455 ""} -{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1618905514486 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1618905514783 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "372 " "Peak virtual memory: 372 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618905514924 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 03:58:34 2021 " "Processing ended: Tue Apr 20 03:58:34 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618905514924 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618905514924 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:09 " "Total CPU time (on all processors): 00:00:09" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618905514924 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1618905514924 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1618905517830 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618905517846 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 03:58:37 2021 " "Processing started: Tue Apr 20 03:58:37 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618905517846 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1618905517846 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1618905517846 ""} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1618905520377 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1618905520393 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "293 " "Peak virtual memory: 293 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618905520783 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 03:58:40 2021 " "Processing ended: Tue Apr 20 03:58:40 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618905520783 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618905520783 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618905520783 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1618905520783 ""} -{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1618905521502 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1618905523627 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618905523627 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 03:58:42 2021 " "Processing started: Tue Apr 20 03:58:42 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618905523627 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618905523627 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618905523627 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1618905523799 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1618905524502 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618905524737 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618905524737 ""} -{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1618905524908 ""} -{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1618905525346 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1618905525502 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1618905525502 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C25M C25M " "create_clock -period 1.000 -name C25M C25M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618905525502 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI0 PHI0 " "create_clock -period 1.000 -name PHI0 PHI0" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618905525502 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618905525502 ""} -{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1618905525518 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1618905525658 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -9.202 " "Worst-case setup slack is -9.202" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905525674 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905525674 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.202 -651.252 C25M " " -9.202 -651.252 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905525674 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.202 0.000 PHI0 " " 0.202 0.000 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905525674 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618905525674 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.143 " "Worst-case hold slack is 0.143" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905525690 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905525690 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.143 0.000 PHI0 " " 0.143 0.000 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905525690 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.385 0.000 C25M " " 1.385 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905525690 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618905525690 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -4.416 " "Worst-case recovery slack is -4.416" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905525705 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905525705 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.416 -128.064 C25M " " -4.416 -128.064 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905525705 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618905525705 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "removal 4.862 " "Worst-case removal slack is 4.862" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905525721 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905525721 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.862 0.000 C25M " " 4.862 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905525721 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618905525721 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.289 " "Worst-case minimum pulse width slack is -2.289" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905525737 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905525737 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 C25M " " -2.289 -2.289 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905525737 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI0 " " -2.289 -2.289 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905525737 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618905525737 ""} -{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1618905525987 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618905526096 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618905526096 ""} -{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "283 " "Peak virtual memory: 283 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618905526268 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 03:58:46 2021 " "Processing ended: Tue Apr 20 03:58:46 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618905526268 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618905526268 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618905526268 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618905526268 ""} -{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 21 s " "Quartus II Full Compilation was successful. 0 errors, 21 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618905527362 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618906713072 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618906713088 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 04:18:32 2021 " "Processing started: Tue Apr 20 04:18:32 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618906713088 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618906713088 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618906713088 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1618906714666 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(106) " "Verilog HDL warning at GR8RAM.v(106): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 106 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618906714838 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(282) " "Verilog HDL warning at GR8RAM.v(282): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 282 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618906714854 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1618906714854 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1618906714854 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1618906714979 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(42) " "Verilog HDL assignment warning at GR8RAM.v(42): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 42 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618906714979 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(47) " "Verilog HDL assignment warning at GR8RAM.v(47): truncated value with size 32 to match size of target (14)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 47 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618906714979 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(130) " "Verilog HDL assignment warning at GR8RAM.v(130): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 130 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618906714979 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(138) " "Verilog HDL assignment warning at GR8RAM.v(138): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 138 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618906714979 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(145) " "Verilog HDL assignment warning at GR8RAM.v(145): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 145 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618906714994 "|GR8RAM"} +{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 -1 1618906716541 ""} +{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "nNMIout VCC " "Pin \"nNMIout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 553 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618906716822 "|GR8RAM|nNMIout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nIRQout VCC " "Pin \"nIRQout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 556 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618906716822 "|GR8RAM|nIRQout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nRDYout VCC " "Pin \"nRDYout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 555 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618906716822 "|GR8RAM|nRDYout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nINHout VCC " "Pin \"nINHout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 554 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618906716822 "|GR8RAM|nINHout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RWout VCC " "Pin \"RWout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 557 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618906716822 "|GR8RAM|RWout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nDMAout VCC " "Pin \"nDMAout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 552 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618906716822 "|GR8RAM|nDMAout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 551 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618906716822 "|GR8RAM|RAdir"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1618906716822 ""} +{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1618906717276 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "321 " "Implemented 321 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "28 " "Implemented 28 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1618906717307 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1618906717307 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1618906717307 ""} { "Info" "ICUT_CUT_TM_LCELLS" "241 " "Implemented 241 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1618906717307 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1618906717307 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1618906717510 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 13 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 13 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "301 " "Peak virtual memory: 301 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618906717666 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 04:18:37 2021 " "Processing ended: Tue Apr 20 04:18:37 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618906717666 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618906717666 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618906717666 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618906717666 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618906720682 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 32-bit " "Running Quartus II 32-bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618906720698 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 04:18:39 2021 " "Processing started: Tue Apr 20 04:18:39 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618906720698 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1618906720698 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1618906720698 ""} +{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1618906720885 ""} +{ "Info" "0" "" "Project = GR8RAM" { } { } 0 0 "Project = GR8RAM" 0 0 "Fitter" 0 0 1618906720885 ""} +{ "Info" "0" "" "Revision = GR8RAM" { } { } 0 0 "Revision = GR8RAM" 0 0 "Fitter" 0 0 1618906720885 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1618906721651 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1618906721682 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618906721948 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618906721948 ""} +{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1618906722260 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1618906722307 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618906722666 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618906722666 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618906722666 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618906722666 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618906722666 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1618906722666 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1618906722838 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1618906722854 ""} +{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1618906722885 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1618906722885 ""} +{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618906722932 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618906722932 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 C25M " " 1.000 C25M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618906722932 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI0 " " 1.000 PHI0" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618906722932 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1618906722932 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618906722932 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618906722948 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618906722948 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618906722979 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI0 Global clock " "Automatically promoted some destinations of signal \"PHI0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~1 " "Destination \"comb~1\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618906722979 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI0r1 " "Destination \"PHI0r1\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618906722979 ""} } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618906722979 ""} +{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI0 " "Pin \"PHI0\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI0 } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "PHI0" } } } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 380 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1618906722979 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "nRESr Global clock " "Automatically promoted signal \"nRESr\" to use Global clock" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 16 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618906722995 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618906722995 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1618906722995 ""} +{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1618906723026 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1618906723073 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1618906723088 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1618906723088 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1618906723088 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618906723135 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1618906723307 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618906723667 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1618906723682 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1618906725120 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618906725135 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1618906725214 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "36 " "Router estimated average interconnect usage is 36% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "36 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 36% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 36% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 36% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1618906725682 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1618906725682 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618906726260 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.67 " "Total time spent on timing analysis during the Fitter is 0.67 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1618906726276 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618906726276 ""} +{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1618906726307 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1618906726589 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "382 " "Peak virtual memory: 382 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618906726823 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 04:18:46 2021 " "Processing ended: Tue Apr 20 04:18:46 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618906726823 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618906726823 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618906726823 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1618906726823 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1618906729714 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618906729714 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 04:18:49 2021 " "Processing started: Tue Apr 20 04:18:49 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618906729714 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1618906729714 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1618906729714 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1618906730948 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1618906730979 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "293 " "Peak virtual memory: 293 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618906731745 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 04:18:51 2021 " "Processing ended: Tue Apr 20 04:18:51 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618906731745 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618906731745 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618906731745 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1618906731745 ""} +{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1618906732667 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1618906734839 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618906734839 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 04:18:53 2021 " "Processing started: Tue Apr 20 04:18:53 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618906734839 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618906734839 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618906734839 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1618906735042 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1618906735948 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618906736105 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618906736105 ""} +{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1618906736308 ""} +{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1618906737074 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1618906737308 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1618906737308 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C25M C25M " "create_clock -period 1.000 -name C25M C25M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737308 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI0 PHI0 " "create_clock -period 1.000 -name PHI0 PHI0" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737308 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737308 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1618906737324 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1618906737495 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -9.005 " "Worst-case setup slack is -9.005" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737495 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737495 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.005 -699.357 C25M " " -9.005 -699.357 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737495 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.425 -0.425 PHI0 " " -0.425 -0.425 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737495 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618906737495 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.248 " "Worst-case hold slack is -0.248" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737527 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737527 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.248 -0.248 PHI0 " " -0.248 -0.248 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737527 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.400 0.000 C25M " " 1.400 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737527 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618906737527 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -4.412 " "Worst-case recovery slack is -4.412" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737542 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737542 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.412 -127.948 C25M " " -4.412 -127.948 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737542 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618906737542 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "removal 4.858 " "Worst-case removal slack is 4.858" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737558 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737558 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.858 0.000 C25M " " 4.858 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737558 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618906737558 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.289 " "Worst-case minimum pulse width slack is -2.289" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737589 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737589 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 C25M " " -2.289 -2.289 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737589 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI0 " " -2.289 -2.289 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737589 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618906737589 ""} +{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1618906738136 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618906738246 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618906738246 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "278 " "Peak virtual memory: 278 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618906738496 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 04:18:58 2021 " "Processing ended: Tue Apr 20 04:18:58 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618906738496 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618906738496 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618906738496 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618906738496 ""} +{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 18 s " "Quartus II Full Compilation was successful. 0 errors, 18 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618906739949 ""} diff --git a/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt b/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt index 4f8958c..0798033 100755 Binary files a/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt and b/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt differ diff --git a/cpld/output_files/GR8RAM.asm.rpt b/cpld/output_files/GR8RAM.asm.rpt index 07cc802..609cd3a 100755 --- a/cpld/output_files/GR8RAM.asm.rpt +++ b/cpld/output_files/GR8RAM.asm.rpt @@ -1,5 +1,5 @@ Assembler report for GR8RAM -Tue Apr 20 04:00:20 2021 +Tue Apr 20 04:19:58 2021 Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition @@ -37,7 +37,7 @@ applicable agreement for further details. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Tue Apr 20 04:00:20 2021 ; +; Assembler Status ; Successful - Tue Apr 20 04:19:58 2021 ; ; Revision Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ; ; Family ; MAX II ; @@ -90,8 +90,8 @@ applicable agreement for further details. ; Option ; Setting ; +----------------+-------------------------------------------------------+ ; Device ; EPM240T100C5 ; -; JTAG usercode ; 0x0016534D ; -; Checksum ; 0x0016564D ; +; JTAG usercode ; 0x001644CE ; +; Checksum ; 0x0016484E ; +----------------+-------------------------------------------------------+ @@ -101,14 +101,14 @@ applicable agreement for further details. Info: ******************************************************************* Info: Running Quartus II 32-bit Assembler Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - Info: Processing started: Tue Apr 20 04:00:18 2021 + Info: Processing started: Tue Apr 20 04:19:56 2021 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM Info (115031): Writing out detailed assembly data for power analysis Info (115030): Assembler is generating device programming files Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings Info: Peak virtual memory: 293 megabytes - Info: Processing ended: Tue Apr 20 04:00:20 2021 - Info: Elapsed time: 00:00:02 + Info: Processing ended: Tue Apr 20 04:19:59 2021 + Info: Elapsed time: 00:00:03 Info: Total CPU time (on all processors): 00:00:02 diff --git a/cpld/output_files/GR8RAM.done b/cpld/output_files/GR8RAM.done index 09d1d95..7c4faa1 100755 --- a/cpld/output_files/GR8RAM.done +++ b/cpld/output_files/GR8RAM.done @@ -1 +1 @@ -Tue Apr 20 04:00:27 2021 +Tue Apr 20 04:20:06 2021 diff --git a/cpld/output_files/GR8RAM.fit.rpt b/cpld/output_files/GR8RAM.fit.rpt index 0973378..b4be352 100755 --- a/cpld/output_files/GR8RAM.fit.rpt +++ b/cpld/output_files/GR8RAM.fit.rpt @@ -1,5 +1,5 @@ Fitter report for GR8RAM -Tue Apr 20 04:00:16 2021 +Tue Apr 20 04:19:53 2021 Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition @@ -30,10 +30,8 @@ Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit 22. LAB Signals Sourced Out 23. LAB Distinct Inputs 24. Fitter Device Options - 25. Estimated Delay Added for Hold Timing Summary - 26. Estimated Delay Added for Hold Timing Details - 27. Fitter Messages - 28. Fitter Suppressed Messages + 25. Fitter Messages + 26. Fitter Suppressed Messages @@ -59,7 +57,7 @@ applicable agreement for further details. +-----------------------------------------------------------------------------+ ; Fitter Summary ; +---------------------------+-------------------------------------------------+ -; Fitter Status ; Successful - Tue Apr 20 04:00:16 2021 ; +; Fitter Status ; Successful - Tue Apr 20 04:19:53 2021 ; ; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; ; Revision Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ; @@ -151,26 +149,26 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin. ; Resource ; Usage ; +---------------------------------------------+--------------------+ ; Total logic elements ; 230 / 240 ( 96 % ) ; -; -- Combinational with no register ; 124 ; +; -- Combinational with no register ; 121 ; ; -- Register only ; 1 ; -; -- Combinational with a register ; 105 ; +; -- Combinational with a register ; 108 ; ; ; ; ; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 122 ; -; -- 3 input functions ; 37 ; -; -- 2 input functions ; 68 ; +; -- 4 input functions ; 119 ; +; -- 3 input functions ; 38 ; +; -- 2 input functions ; 69 ; ; -- 1 input functions ; 0 ; -; -- 0 input functions ; 2 ; +; -- 0 input functions ; 3 ; ; ; ; ; Logic elements by mode ; ; ; -- normal mode ; 197 ; ; -- arithmetic mode ; 33 ; -; -- qfbk mode ; 4 ; +; -- qfbk mode ; 6 ; ; -- register cascade mode ; 0 ; -; -- synchronous clear/load mode ; 52 ; +; -- synchronous clear/load mode ; 54 ; ; -- asynchronous clear/load mode ; 30 ; ; ; ; -; Total registers ; 106 / 240 ( 44 % ) ; +; Total registers ; 109 / 240 ( 45 % ) ; ; Total LABs ; 24 / 24 ( 100 % ) ; ; Logic elements in carry chains ; 37 ; ; Virtual pins ; 0 ; @@ -181,12 +179,12 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin. ; UFM blocks ; 0 / 1 ( 0 % ) ; ; Global clocks ; 3 / 4 ( 75 % ) ; ; JTAGs ; 0 / 1 ( 0 % ) ; -; Average interconnect usage (total/H/V) ; 44% / 48% / 39% ; -; Peak interconnect usage (total/H/V) ; 44% / 48% / 39% ; -; Maximum fan-out ; 103 ; +; Average interconnect usage (total/H/V) ; 44% / 49% / 38% ; +; Peak interconnect usage (total/H/V) ; 44% / 49% / 38% ; +; Maximum fan-out ; 106 ; ; Highest non-global fan-out ; 45 ; -; Total fan-out ; 1053 ; -; Average fan-out ; 3.40 ; +; Total fan-out ; 1050 ; +; Average fan-out ; 3.39 ; +---------------------------------------------+--------------------+ @@ -195,7 +193,7 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin. +----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+ ; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Location assigned by ; +----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+ -; C25M ; 64 ; 2 ; 8 ; 3 ; 4 ; 103 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; User ; +; C25M ; 64 ; 2 ; 8 ; 3 ; 4 ; 106 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; User ; ; DMAin ; 48 ; 1 ; 6 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; ; INTin ; 49 ; 1 ; 7 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; ; MISO ; 16 ; 1 ; 1 ; 2 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; @@ -216,8 +214,8 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin. ; RA[7] ; 6 ; 1 ; 1 ; 3 ; 0 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; ; RA[8] ; 7 ; 1 ; 1 ; 3 ; 1 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; ; RA[9] ; 8 ; 1 ; 1 ; 3 ; 2 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; SetFW[0] ; 96 ; 2 ; 3 ; 5 ; 2 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; SetFW[1] ; 95 ; 2 ; 3 ; 5 ; 1 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; +; SetFW[0] ; 96 ; 2 ; 3 ; 5 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; +; SetFW[1] ; 95 ; 2 ; 3 ; 5 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; ; nDEVSEL ; 40 ; 1 ; 5 ; 0 ; 2 ; 4 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; ; nIOSEL ; 39 ; 1 ; 5 ; 0 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; ; nIOSTRB ; 42 ; 1 ; 5 ; 0 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; @@ -233,7 +231,7 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin. +---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ ; DMAout ; 18 ; 1 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; ; DQMH ; 57 ; 2 ; 8 ; 2 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; -; DQML ; 85 ; 2 ; 5 ; 5 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; - ; - ; +; DQML ; 85 ; 2 ; 5 ; 5 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; ; FCK ; 12 ; 1 ; 1 ; 3 ; 3 ; no ; no ; no ; no ; yes ; yes ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; ; INTout ; 20 ; 1 ; 1 ; 1 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; ; RAdir ; 19 ; 1 ; 1 ; 1 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; @@ -241,7 +239,7 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin. ; RDdir ; 17 ; 1 ; 1 ; 2 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; ; RWout ; 33 ; 1 ; 3 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; ; SA[0] ; 75 ; 2 ; 7 ; 5 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; -; SA[10] ; 73 ; 2 ; 8 ; 4 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; +; SA[10] ; 73 ; 2 ; 8 ; 4 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; - ; - ; ; SA[11] ; 70 ; 2 ; 8 ; 4 ; 4 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; ; SA[12] ; 68 ; 2 ; 8 ; 3 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; ; SA[1] ; 81 ; 2 ; 6 ; 5 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; @@ -254,10 +252,10 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin. ; SA[8] ; 74 ; 2 ; 8 ; 4 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; ; SA[9] ; 72 ; 2 ; 8 ; 4 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; ; SBA[0] ; 69 ; 2 ; 8 ; 3 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; -; SBA[1] ; 71 ; 2 ; 8 ; 4 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; +; SBA[1] ; 71 ; 2 ; 8 ; 4 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; - ; - ; ; nCAS ; 61 ; 2 ; 8 ; 2 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; ; nDMAout ; 21 ; 1 ; 1 ; 1 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; -; nFCS ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; no ; no ; no ; yes ; no ; On ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; - ; - ; +; nFCS ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; no ; no ; no ; yes ; no ; On ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; ; nINHout ; 27 ; 1 ; 2 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; ; nIRQout ; 29 ; 1 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; ; nNMIout ; 26 ; 1 ; 2 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; @@ -283,12 +281,12 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin. ; RD[5] ; 91 ; 2 ; 4 ; 5 ; 2 ; 4 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; comb~1 ; - ; ; RD[6] ; 92 ; 2 ; 3 ; 5 ; 0 ; 4 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; comb~1 ; - ; ; RD[7] ; 99 ; 2 ; 2 ; 5 ; 1 ; 6 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; comb~1 ; - ; -; SD[0] ; 50 ; 1 ; 7 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; +; SD[0] ; 50 ; 1 ; 7 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; SDOE ; - ; ; SD[1] ; 47 ; 1 ; 6 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; ; SD[2] ; 56 ; 2 ; 8 ; 1 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; ; SD[3] ; 55 ; 2 ; 8 ; 1 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; ; SD[4] ; 51 ; 1 ; 7 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; -; SD[5] ; 52 ; 2 ; 8 ; 1 ; 4 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; +; SD[5] ; 52 ; 2 ; 8 ; 1 ; 4 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; SDOE ; - ; ; SD[6] ; 53 ; 2 ; 8 ; 1 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; ; SD[7] ; 54 ; 2 ; 8 ; 1 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; +-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ @@ -434,7 +432,7 @@ Note: User assignments will override these defaults. The user specified values a +----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+ ; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ; +----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+ -; |GR8RAM ; 230 (230) ; 106 ; 0 ; 80 ; 0 ; 124 (124) ; 1 (1) ; 105 (105) ; 37 (37) ; 8 (8) ; |GR8RAM ; work ; +; |GR8RAM ; 230 (230) ; 109 ; 0 ; 80 ; 0 ; 121 (121) ; 1 (1) ; 108 (108) ; 37 (37) ; 10 (10) ; |GR8RAM ; work ; +----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. @@ -464,12 +462,12 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; RA[9] ; Input ; (1) ; ; RA[10] ; Input ; (1) ; ; nRES ; Input ; (1) ; -; SetFW[1] ; Input ; (1) ; ; RA[11] ; Input ; (1) ; ; RA[14] ; Input ; (1) ; ; RA[15] ; Input ; (1) ; ; RA[12] ; Input ; (1) ; ; RA[13] ; Input ; (1) ; +; SetFW[1] ; Input ; (1) ; ; SetFW[0] ; Input ; (1) ; ; MISO ; Input ; (1) ; ; nRESout ; Output ; -- ; @@ -527,28 +525,29 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +----------+----------+---------------+ -+-------------------------------------------------------------------------------------------------------------------------------+ -; Control Signals ; -+------------+-------------+---------+---------------------------------------+--------+----------------------+------------------+ -; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; -+------------+-------------+---------+---------------------------------------+--------+----------------------+------------------+ -; C25M ; PIN_64 ; 103 ; Clock ; yes ; Global Clock ; GCLK3 ; -; Decoder1~0 ; LC_X7_Y3_N6 ; 8 ; Clock enable ; no ; -- ; -- ; -; Equal0~0 ; LC_X5_Y3_N3 ; 19 ; Clock enable ; no ; -- ; -- ; -; FCKOE ; LC_X2_Y1_N0 ; 2 ; Output enable ; no ; -- ; -- ; -; IOROMRES ; LC_X2_Y3_N9 ; 1 ; Async. clear ; no ; -- ; -- ; -; MOSIOE ; LC_X2_Y1_N7 ; 1 ; Output enable ; no ; -- ; -- ; -; PHI0 ; PIN_41 ; 5 ; Clock ; yes ; Global Clock ; GCLK1 ; -; PS[0] ; LC_X5_Y3_N2 ; 44 ; Clock enable, Sync. clear, Sync. load ; no ; -- ; -- ; -; PS[2] ; LC_X5_Y3_N4 ; 27 ; Sync. clear, Sync. load ; no ; -- ; -- ; -; SDOE ; LC_X7_Y1_N2 ; 8 ; Output enable ; no ; -- ; -- ; -; always5~1 ; LC_X2_Y3_N5 ; 2 ; Clock enable ; no ; -- ; -- ; -; always7~2 ; LC_X5_Y1_N9 ; 8 ; Sync. load ; no ; -- ; -- ; -; always7~3 ; LC_X4_Y1_N4 ; 9 ; Sync. load ; no ; -- ; -- ; -; always7~4 ; LC_X4_Y1_N9 ; 9 ; Sync. load ; no ; -- ; -- ; -; comb~1 ; LC_X6_Y4_N9 ; 9 ; Output enable ; no ; -- ; -- ; -; nRESr ; LC_X2_Y3_N8 ; 29 ; Async. clear ; yes ; Global Clock ; GCLK2 ; -+------------+-------------+---------+---------------------------------------+--------+----------------------+------------------+ ++--------------------------------------------------------------------------------------------------------------------------------+ +; Control Signals ; ++-------------+-------------+---------+---------------------------------------+--------+----------------------+------------------+ +; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; ++-------------+-------------+---------+---------------------------------------+--------+----------------------+------------------+ +; C25M ; PIN_64 ; 106 ; Clock ; yes ; Global Clock ; GCLK3 ; +; Decoder1~0 ; LC_X4_Y2_N5 ; 8 ; Clock enable ; no ; -- ; -- ; +; Equal2~0 ; LC_X3_Y2_N8 ; 19 ; Clock enable ; no ; -- ; -- ; +; FCKOE ; LC_X6_Y4_N4 ; 2 ; Output enable ; no ; -- ; -- ; +; IOROMRES ; LC_X2_Y3_N8 ; 1 ; Async. clear ; no ; -- ; -- ; +; MOSIOE ; LC_X6_Y4_N0 ; 1 ; Output enable ; no ; -- ; -- ; +; PHI0 ; PIN_41 ; 5 ; Clock ; yes ; Global Clock ; GCLK1 ; +; PS[0] ; LC_X4_Y2_N2 ; 44 ; Clock enable, Sync. clear, Sync. load ; no ; -- ; -- ; +; PS[2] ; LC_X4_Y2_N7 ; 26 ; Sync. clear, Sync. load ; no ; -- ; -- ; +; SDOE ; LC_X4_Y1_N6 ; 8 ; Output enable ; no ; -- ; -- ; +; SetFWLoaded ; LC_X4_Y2_N6 ; 2 ; Clock enable ; no ; -- ; -- ; +; always7~1 ; LC_X2_Y3_N1 ; 2 ; Clock enable ; no ; -- ; -- ; +; always9~2 ; LC_X2_Y2_N9 ; 8 ; Sync. load ; no ; -- ; -- ; +; always9~3 ; LC_X2_Y1_N8 ; 9 ; Sync. load ; no ; -- ; -- ; +; always9~4 ; LC_X7_Y2_N8 ; 9 ; Sync. load ; no ; -- ; -- ; +; comb~1 ; LC_X5_Y1_N6 ; 9 ; Output enable ; no ; -- ; -- ; +; nRESr ; LC_X2_Y3_N4 ; 29 ; Async. clear ; yes ; Global Clock ; GCLK2 ; ++-------------+-------------+---------+---------------------------------------+--------+----------------------+------------------+ +-------------------------------------------------------------------------+ @@ -556,9 +555,9 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +-------+-------------+---------+----------------------+------------------+ ; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; +-------+-------------+---------+----------------------+------------------+ -; C25M ; PIN_64 ; 103 ; Global Clock ; GCLK3 ; +; C25M ; PIN_64 ; 106 ; Global Clock ; GCLK3 ; ; PHI0 ; PIN_41 ; 5 ; Global Clock ; GCLK1 ; -; nRESr ; LC_X2_Y3_N8 ; 29 ; Global Clock ; GCLK2 ; +; nRESr ; LC_X2_Y3_N4 ; 29 ; Global Clock ; GCLK2 ; +-------+-------------+---------+----------------------+------------------+ @@ -568,10 +567,10 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; Name ; Fan-Out ; +---------------------+-----------+ ; PS[0] ; 45 ; -; PS[1] ; 31 ; -; PS[3] ; 29 ; -; PS[2] ; 27 ; -; Equal0~0 ; 19 ; +; PS[1] ; 30 ; +; PS[3] ; 28 ; +; PS[2] ; 26 ; +; Equal2~0 ; 19 ; ; IS.state_bit_0 ; 19 ; ; IS.110~0 ; 17 ; ; RAMSpecSELr ; 16 ; @@ -579,17 +578,17 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; LS[0] ; 13 ; ; RA[0] ; 9 ; ; RDD[1]~23 ; 9 ; -; always7~4 ; 9 ; -; always7~3 ; 9 ; +; always9~4 ; 9 ; +; always9~3 ; 9 ; ; comb~1 ; 9 ; -; SetFW[1] ; 8 ; ; RA[1] ; 8 ; ; RDD[1]~22 ; 8 ; ; Decoder1~0 ; 8 ; ; SDOE ; 8 ; -; always7~2 ; 8 ; +; always9~2 ; 8 ; ; IS.state_bit_2 ; 8 ; ; LS[2] ; 8 ; +; SetFWr[1] ; 7 ; ; SA[0]~8 ; 7 ; ; RD[7]~7 ; 6 ; ; SA[3]~17 ; 6 ; @@ -614,12 +613,10 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; RD[2]~2 ; 4 ; ; RD[1]~1 ; 4 ; ; nDEVSEL ; 4 ; -; always7~6 ; 4 ; +; always9~6 ; 4 ; ; RDD[4]~13 ; 4 ; ; LS[13] ; 4 ; -; Equal1~2 ; 4 ; -; nRCS~1 ; 4 ; -; Equal18~0 ; 4 ; +; Equal3~2 ; 4 ; ; Addr[9] ; 4 ; ; Addr[8] ; 4 ; ; Addr[7] ; 4 ; @@ -638,7 +635,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; SA[0]~7 ; 4 ; ; Addr[1] ; 4 ; ; Addr[10] ; 4 ; -; always5~0 ; 4 ; +; always7~0 ; 4 ; ; RA[11] ; 3 ; ; RA[10] ; 3 ; ; RA[9] ; 3 ; @@ -652,16 +649,16 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; WRD[2] ; 3 ; ; WRD[1] ; 3 ; ; WRD[0] ; 3 ; -; Equal2~0 ; 3 ; -; Equal3~0 ; 3 ; -; Equal1~3 ; 3 ; -; Equal18~1 ; 3 ; -; IS.111~0 ; 3 ; +; Equal4~0 ; 3 ; +; Equal5~0 ; 3 ; +; Equal3~3 ; 3 ; +; nRCS~1 ; 3 ; ; Addr[22] ; 3 ; ; Addr[21] ; 3 ; ; Addr[20]~41 ; 3 ; ; Addr[20] ; 3 ; ; SA~11 ; 3 ; +; Equal1~0 ; 3 ; ; Addr[19] ; 3 ; ; LS[9] ; 3 ; ; Addr[18] ; 3 ; @@ -678,29 +675,32 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; SA[0]~5 ; 3 ; ; LS[10] ; 3 ; ; SA[0]~4 ; 3 ; -; SetFW[0] ; 2 ; ; RA[6] ; 2 ; ; RA[5] ; 2 ; ; RA[4] ; 2 ; ; nIOSEL ; 2 ; ; nIOSTRB ; 2 ; +; PHI0r1 ; 2 ; ; WRD[7] ; 2 ; ; WRD[6] ; 2 ; ; AddrIncL ; 2 ; ; AddrIncM ; 2 ; +; SetFWLoaded ; 2 ; ; RAMRegSpecSEL ; 2 ; -; Equal7~0 ; 2 ; +; Equal9~0 ; 2 ; ; REGSpecSEL~0 ; 2 ; ; IS.state_bit_1~3 ; 2 ; ; IS.state_bit_1~0 ; 2 ; -; Equal3~1 ; 2 ; +; Equal5~1 ; 2 ; ; FCKOE ; 2 ; -; PS~0 ; 2 ; +; PHI0r2 ; 2 ; +; Equal1~1 ; 2 ; ; DQMH~0 ; 2 ; ; Mux12~2 ; 2 ; -; nRCS~3 ; 2 ; +; IS.111~0 ; 2 ; +; nRCS~4 ; 2 ; ; ROMSpecRDr ; 2 ; -; nRCS~2 ; 2 ; +; nRCS~3 ; 2 ; ; nWEr ; 2 ; ; Bank ; 2 ; ; LS[11]~5 ; 2 ; @@ -709,7 +709,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; Mux14~1 ; 2 ; ; Mux14~0 ; 2 ; ; nRESf[1] ; 2 ; -; always5~1 ; 2 ; +; always7~1 ; 2 ; ; nRESf[0] ; 2 ; ; comb~2 ; 2 ; ; IOROMEN ; 2 ; @@ -724,6 +724,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; SD[1]~1 ; 1 ; ; SD[0]~0 ; 1 ; ; MISO ; 1 ; +; SetFW[0] ; 1 ; +; SetFW[1] ; 1 ; ; RA[13] ; 1 ; ; RA[12] ; 1 ; ; RA[15] ; 1 ; @@ -731,8 +733,10 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; nRES ; 1 ; ; DMAin ; 1 ; ; INTin ; 1 ; +; Mux11~6 ; 1 ; ; Mux13~2 ; 1 ; ; Mux2~3 ; 1 ; +; SetFWr[0] ; 1 ; ; Mux2~2 ; 1 ; ; Mux2~1 ; 1 ; ; Mux2~0 ; 1 ; @@ -765,24 +769,22 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; ROMSpecRD~0 ; 1 ; ; IS.state_bit_2~1 ; 1 ; ; IS.state_bit_2~0 ; 1 ; -; Equal1~4 ; 1 ; +; Equal3~4 ; 1 ; ; AddrIncH ; 1 ; ; REGEN ; 1 ; ; IS.state_bit_1~2 ; 1 ; ; IS.state_bit_1~1 ; 1 ; ; IS.state_bit_0~5 ; 1 ; ; IS.state_bit_0~4 ; 1 ; -; Equal4~0 ; 1 ; -; Equal1~1 ; 1 ; -; Equal1~0 ; 1 ; +; Equal6~0 ; 1 ; +; Equal3~1 ; 1 ; +; Equal3~0 ; 1 ; ; FCKout ; 1 ; ; FCS ; 1 ; ; Mux11~4 ; 1 ; ; Mux11~3 ; 1 ; ; Mux11~2 ; 1 ; -; PHI0r1 ; 1 ; -; Mux11~1 ; 1 ; -; Mux11~0 ; 1 ; +; PS~0 ; 1 ; ; Selector2~0 ; 1 ; ; Selector1~0 ; 1 ; ; Addr[0]~47COUT1_92 ; 1 ; @@ -791,7 +793,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; Mux12~3 ; 1 ; ; Mux12~1 ; 1 ; ; Mux12~0 ; 1 ; -; IS.000~0 ; 1 ; +; nRCS~2 ; 1 ; ; nRCS~0 ; 1 ; ; Addr[22]~45COUT1_78 ; 1 ; ; Addr[22]~45 ; 1 ; @@ -906,7 +908,6 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; SA[0]~reg0 ; 1 ; ; SBA[1]~reg0 ; 1 ; ; SBA[0]~reg0 ; 1 ; -; PHI0r2 ; 1 ; ; comb~0 ; 1 ; +---------------------+-----------+ @@ -916,13 +917,13 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +-----------------------------+--------------------+ ; Other Routing Resource Type ; Usage ; +-----------------------------+--------------------+ -; C4s ; 251 / 784 ( 32 % ) ; -; Direct links ; 45 / 888 ( 5 % ) ; +; C4s ; 234 / 784 ( 30 % ) ; +; Direct links ; 69 / 888 ( 8 % ) ; ; Global clocks ; 3 / 4 ( 75 % ) ; ; LAB clocks ; 12 / 32 ( 38 % ) ; -; LUT chains ; 33 / 216 ( 15 % ) ; +; LUT chains ; 39 / 216 ( 18 % ) ; ; Local interconnects ; 436 / 888 ( 49 % ) ; -; R4s ; 284 / 704 ( 40 % ) ; +; R4s ; 282 / 704 ( 40 % ) ; +-----------------------------+--------------------+ @@ -932,54 +933,55 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; Number of Logic Elements (Average = 9.58) ; Number of LABs (Total = 24) ; +--------------------------------------------+------------------------------+ ; 1 ; 0 ; -; 2 ; 1 ; +; 2 ; 0 ; ; 3 ; 0 ; ; 4 ; 0 ; ; 5 ; 0 ; ; 6 ; 0 ; ; 7 ; 0 ; -; 8 ; 1 ; -; 9 ; 0 ; -; 10 ; 22 ; +; 8 ; 3 ; +; 9 ; 4 ; +; 10 ; 17 ; +--------------------------------------------+------------------------------+ +-------------------------------------------------------------------+ ; LAB-wide Signals ; +------------------------------------+------------------------------+ -; LAB-wide Signals (Average = 1.96) ; Number of LABs (Total = 24) ; +; LAB-wide Signals (Average = 1.83) ; Number of LABs (Total = 24) ; +------------------------------------+------------------------------+ ; 1 Async. clear ; 7 ; ; 1 Clock ; 22 ; ; 1 Clock enable ; 6 ; -; 1 Sync. clear ; 5 ; -; 1 Sync. load ; 5 ; +; 1 Sync. clear ; 4 ; +; 1 Sync. load ; 2 ; +; 2 Clock enables ; 1 ; ; 2 Clocks ; 2 ; +------------------------------------+------------------------------+ -+----------------------------------------------------------------------------+ -; LAB Signals Sourced ; -+---------------------------------------------+------------------------------+ -; Number of Signals Sourced (Average = 9.96) ; Number of LABs (Total = 24) ; -+---------------------------------------------+------------------------------+ -; 0 ; 0 ; -; 1 ; 0 ; -; 2 ; 1 ; -; 3 ; 0 ; -; 4 ; 0 ; -; 5 ; 0 ; -; 6 ; 0 ; -; 7 ; 0 ; -; 8 ; 1 ; -; 9 ; 0 ; -; 10 ; 18 ; -; 11 ; 2 ; -; 12 ; 1 ; -; 13 ; 0 ; -; 14 ; 0 ; -; 15 ; 1 ; -+---------------------------------------------+------------------------------+ ++-----------------------------------------------------------------------------+ +; LAB Signals Sourced ; ++----------------------------------------------+------------------------------+ +; Number of Signals Sourced (Average = 10.04) ; Number of LABs (Total = 24) ; ++----------------------------------------------+------------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 3 ; +; 9 ; 4 ; +; 10 ; 12 ; +; 11 ; 2 ; +; 12 ; 2 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 1 ; ++----------------------------------------------+------------------------------+ +--------------------------------------------------------------------------------+ @@ -989,46 +991,46 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +-------------------------------------------------+------------------------------+ ; 0 ; 0 ; ; 1 ; 0 ; -; 2 ; 1 ; -; 3 ; 1 ; -; 4 ; 2 ; -; 5 ; 5 ; +; 2 ; 0 ; +; 3 ; 3 ; +; 4 ; 4 ; +; 5 ; 2 ; ; 6 ; 2 ; -; 7 ; 2 ; -; 8 ; 2 ; -; 9 ; 4 ; +; 7 ; 1 ; +; 8 ; 3 ; +; 9 ; 3 ; ; 10 ; 5 ; +; 11 ; 1 ; +-------------------------------------------------+------------------------------+ +-----------------------------------------------------------------------------+ ; LAB Distinct Inputs ; +----------------------------------------------+------------------------------+ -; Number of Distinct Inputs (Average = 15.38) ; Number of LABs (Total = 24) ; +; Number of Distinct Inputs (Average = 15.54) ; Number of LABs (Total = 24) ; +----------------------------------------------+------------------------------+ ; 0 ; 0 ; ; 1 ; 0 ; ; 2 ; 0 ; ; 3 ; 0 ; -; 4 ; 0 ; +; 4 ; 1 ; ; 5 ; 0 ; -; 6 ; 2 ; +; 6 ; 0 ; ; 7 ; 0 ; ; 8 ; 1 ; ; 9 ; 0 ; ; 10 ; 0 ; -; 11 ; 1 ; -; 12 ; 0 ; -; 13 ; 4 ; -; 14 ; 1 ; -; 15 ; 4 ; -; 16 ; 1 ; -; 17 ; 1 ; -; 18 ; 3 ; -; 19 ; 1 ; -; 20 ; 2 ; -; 21 ; 0 ; -; 22 ; 3 ; +; 11 ; 0 ; +; 12 ; 3 ; +; 13 ; 2 ; +; 14 ; 2 ; +; 15 ; 3 ; +; 16 ; 2 ; +; 17 ; 2 ; +; 18 ; 1 ; +; 19 ; 2 ; +; 20 ; 1 ; +; 21 ; 4 ; +----------------------------------------------+------------------------------+ @@ -1047,25 +1049,6 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +----------------------------------------------+--------------------------+ -+------------------------------------------------------------+ -; Estimated Delay Added for Hold Timing Summary ; -+-----------------+----------------------+-------------------+ -; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ; -+-----------------+----------------------+-------------------+ -Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off. -This will disable optimization of problematic paths and expose them for further analysis using either the TimeQuest Timing Analyzer or the Classic Timing Analyzer. - - -+------------------------------------------------------------+ -; Estimated Delay Added for Hold Timing Details ; -+-----------------+----------------------+-------------------+ -; Source Register ; Destination Register ; Delay Added in ns ; -+-----------------+----------------------+-------------------+ -; PHI0 ; PHI0r1 ; 0.186 ; -+-----------------+----------------------+-------------------+ -Note: This table only shows the top 1 path(s) that have the largest delay added for hold. - - +-----------------+ ; Fitter Messages ; +-----------------+ @@ -1102,23 +1085,23 @@ Info (176234): Starting register packing Info (186468): Started processing fast register assignments Info (186469): Finished processing fast register assignments Info (176235): Finished register packing -Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00 +Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01 Info (170189): Fitter placement preparation operations beginning -Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01 Info (170191): Fitter placement operations beginning Info (170137): Fitter placement was successful -Info (170192): Fitter placement operations ending: elapsed time is 00:00:01 +Info (170192): Fitter placement operations ending: elapsed time is 00:00:02 Info (170193): Fitter routing operations beginning -Info (170195): Router estimated average interconnect usage is 34% of the available device resources - Info (170196): Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5 +Info (170195): Router estimated average interconnect usage is 36% of the available device resources + Info (170196): Router estimated peak interconnect usage is 36% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5 Info (170194): Fitter routing operations ending: elapsed time is 00:00:01 -Info (11888): Total time spent on timing analysis during the Fitter is 0.45 seconds. +Info (11888): Total time spent on timing analysis during the Fitter is 0.56 seconds. Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00 Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'. Info (144001): Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg Info: Quartus II 32-bit Fitter was successful. 0 errors, 3 warnings Info: Peak virtual memory: 382 megabytes - Info: Processing ended: Tue Apr 20 04:00:16 2021 + Info: Processing ended: Tue Apr 20 04:19:53 2021 Info: Elapsed time: 00:00:08 Info: Total CPU time (on all processors): 00:00:08 diff --git a/cpld/output_files/GR8RAM.fit.summary b/cpld/output_files/GR8RAM.fit.summary index c299461..18cf322 100755 --- a/cpld/output_files/GR8RAM.fit.summary +++ b/cpld/output_files/GR8RAM.fit.summary @@ -1,4 +1,4 @@ -Fitter Status : Successful - Tue Apr 20 04:00:16 2021 +Fitter Status : Successful - Tue Apr 20 04:19:53 2021 Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition Revision Name : GR8RAM Top-level Entity Name : GR8RAM diff --git a/cpld/output_files/GR8RAM.flow.rpt b/cpld/output_files/GR8RAM.flow.rpt index e828679..c322ed2 100755 --- a/cpld/output_files/GR8RAM.flow.rpt +++ b/cpld/output_files/GR8RAM.flow.rpt @@ -1,5 +1,5 @@ Flow report for GR8RAM -Tue Apr 20 04:00:26 2021 +Tue Apr 20 04:20:05 2021 Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition @@ -40,7 +40,7 @@ applicable agreement for further details. +-----------------------------------------------------------------------------+ ; Flow Summary ; +---------------------------+-------------------------------------------------+ -; Flow Status ; Successful - Tue Apr 20 04:00:20 2021 ; +; Flow Status ; Successful - Tue Apr 20 04:19:58 2021 ; ; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; ; Revision Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ; @@ -59,7 +59,7 @@ applicable agreement for further details. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 04/20/2021 04:00:02 ; +; Start date & time ; 04/20/2021 04:19:41 ; ; Main task ; Compilation ; ; Revision Name ; GR8RAM ; +-------------------+---------------------+ @@ -75,7 +75,7 @@ applicable agreement for further details. ; ALM_REGISTER_PACKING_EFFORT ; High ; Medium ; -- ; -- ; ; AUTO_PACKED_REGISTERS_MAXII ; Minimize Area ; Auto ; -- ; -- ; ; AUTO_RESOURCE_SHARING ; On ; Off ; -- ; -- ; -; COMPILER_SIGNATURE_ID ; 44085571633675.161890560102556 ; -- ; -- ; -- ; +; COMPILER_SIGNATURE_ID ; 44085571633675.161890678100176 ; -- ; -- ; -- ; ; FINAL_PLACEMENT_OPTIMIZATION ; Always ; Automatically ; -- ; -- ; ; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ; ; IOBANK_VCCIO ; 3.3V ; -- ; -- ; 1 ; @@ -102,11 +102,11 @@ applicable agreement for further details. +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:06 ; 1.0 ; 301 MB ; 00:00:05 ; -; Fitter ; 00:00:08 ; 1.2 ; 382 MB ; 00:00:08 ; +; Analysis & Synthesis ; 00:00:05 ; 1.0 ; 301 MB ; 00:00:04 ; +; Fitter ; 00:00:08 ; 1.2 ; 382 MB ; 00:00:07 ; ; Assembler ; 00:00:02 ; 1.0 ; 292 MB ; 00:00:02 ; -; TimeQuest Timing Analyzer ; 00:00:04 ; 1.0 ; 278 MB ; 00:00:04 ; -; Total ; 00:00:20 ; -- ; -- ; 00:00:19 ; +; TimeQuest Timing Analyzer ; 00:00:05 ; 1.0 ; 278 MB ; 00:00:04 ; +; Total ; 00:00:20 ; -- ; -- ; 00:00:17 ; +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ diff --git a/cpld/output_files/GR8RAM.jdi b/cpld/output_files/GR8RAM.jdi index e2079b0..5414390 100755 --- a/cpld/output_files/GR8RAM.jdi +++ b/cpld/output_files/GR8RAM.jdi @@ -1,6 +1,6 @@ - + diff --git a/cpld/output_files/GR8RAM.map.rpt b/cpld/output_files/GR8RAM.map.rpt index 5bc7bc2..008860b 100755 --- a/cpld/output_files/GR8RAM.map.rpt +++ b/cpld/output_files/GR8RAM.map.rpt @@ -1,5 +1,5 @@ Analysis & Synthesis report for GR8RAM -Tue Apr 20 04:00:06 2021 +Tue Apr 20 04:19:44 2021 Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition @@ -45,12 +45,12 @@ applicable agreement for further details. +-------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +-----------------------------+-------------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Tue Apr 20 04:00:06 2021 ; +; Analysis & Synthesis Status ; Successful - Tue Apr 20 04:19:44 2021 ; ; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; ; Revision Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ; ; Family ; MAX II ; -; Total logic elements ; 239 ; +; Total logic elements ; 241 ; ; Total pins ; 80 ; ; Total virtual pins ; 0 ; ; UFM blocks ; 0 / 1 ( 0 % ) ; @@ -161,33 +161,33 @@ applicable agreement for further details. +---------------------------------------------+-------+ ; Resource ; Usage ; +---------------------------------------------+-------+ -; Total logic elements ; 239 ; -; -- Combinational with no register ; 133 ; -; -- Register only ; 10 ; -; -- Combinational with a register ; 96 ; +; Total logic elements ; 241 ; +; -- Combinational with no register ; 132 ; +; -- Register only ; 12 ; +; -- Combinational with a register ; 97 ; ; ; ; ; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 122 ; -; -- 3 input functions ; 37 ; -; -- 2 input functions ; 68 ; +; -- 4 input functions ; 119 ; +; -- 3 input functions ; 38 ; +; -- 2 input functions ; 69 ; ; -- 1 input functions ; 0 ; -; -- 0 input functions ; 2 ; +; -- 0 input functions ; 3 ; ; ; ; ; Logic elements by mode ; ; -; -- normal mode ; 206 ; +; -- normal mode ; 208 ; ; -- arithmetic mode ; 33 ; ; -- qfbk mode ; 0 ; ; -- register cascade mode ; 0 ; ; -- synchronous clear/load mode ; 44 ; ; -- asynchronous clear/load mode ; 30 ; ; ; ; -; Total registers ; 106 ; +; Total registers ; 109 ; ; Total logic cells in carry chains ; 37 ; ; I/O pins ; 80 ; ; Maximum fan-out node ; C25M ; -; Maximum fan-out ; 103 ; +; Maximum fan-out ; 106 ; ; Total fan-out ; 1044 ; -; Average fan-out ; 3.27 ; +; Average fan-out ; 3.25 ; +---------------------------------------------+-------+ @@ -196,7 +196,7 @@ applicable agreement for further details. +----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+ ; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ; +----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+ -; |GR8RAM ; 239 (239) ; 106 ; 0 ; 80 ; 0 ; 133 (133) ; 10 (10) ; 96 (96) ; 37 (37) ; 0 (0) ; |GR8RAM ; work ; +; |GR8RAM ; 241 (241) ; 109 ; 0 ; 80 ; 0 ; 132 (132) ; 12 (12) ; 97 (97) ; 37 (37) ; 0 (0) ; |GR8RAM ; work ; +----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. @@ -231,12 +231,12 @@ Encoding Type: Minimal Bits +----------------------------------------------+-------+ ; Statistic ; Value ; +----------------------------------------------+-------+ -; Total registers ; 106 ; +; Total registers ; 109 ; ; Number of registers using Synchronous Clear ; 11 ; ; Number of registers using Synchronous Load ; 33 ; ; Number of registers using Asynchronous Clear ; 30 ; ; Number of registers using Asynchronous Load ; 0 ; -; Number of registers using Clock Enable ; 24 ; +; Number of registers using Clock Enable ; 26 ; ; Number of registers using Preset ; 0 ; +----------------------------------------------+-------+ @@ -262,7 +262,7 @@ Encoding Type: Minimal Bits +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ ; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ -; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |GR8RAM|PS[1] ; +; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |GR8RAM|PS[2] ; ; 5:1 ; 2 bits ; 6 LEs ; 2 LEs ; 4 LEs ; Yes ; |GR8RAM|SA[11]~reg0 ; ; 20:1 ; 6 bits ; 78 LEs ; 24 LEs ; 54 LEs ; Yes ; |GR8RAM|SA[3]~reg0 ; ; 20:1 ; 3 bits ; 39 LEs ; 18 LEs ; 21 LEs ; Yes ; |GR8RAM|SA[0]~reg0 ; @@ -280,17 +280,17 @@ Encoding Type: Minimal Bits Info: ******************************************************************* Info: Running Quartus II 32-bit Analysis & Synthesis Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - Info: Processing started: Tue Apr 20 04:00:00 2021 + Info: Processing started: Tue Apr 20 04:19:39 2021 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected Info (12021): Found 1 design units, including 1 entities, in source file gr8ram.v Info (12023): Found entity 1: GR8RAM Info (12127): Elaborating entity "GR8RAM" for the top level hierarchy -Warning (10230): Verilog HDL assignment warning at GR8RAM.v(24): truncated value with size 32 to match size of target (14) -Warning (10230): Verilog HDL assignment warning at GR8RAM.v(107): truncated value with size 32 to match size of target (8) -Warning (10230): Verilog HDL assignment warning at GR8RAM.v(115): truncated value with size 32 to match size of target (8) -Warning (10230): Verilog HDL assignment warning at GR8RAM.v(122): truncated value with size 32 to match size of target (8) -Warning (10230): Verilog HDL assignment warning at GR8RAM.v(313): truncated value with size 32 to match size of target (4) +Warning (10230): Verilog HDL assignment warning at GR8RAM.v(42): truncated value with size 32 to match size of target (4) +Warning (10230): Verilog HDL assignment warning at GR8RAM.v(47): truncated value with size 32 to match size of target (14) +Warning (10230): Verilog HDL assignment warning at GR8RAM.v(130): truncated value with size 32 to match size of target (8) +Warning (10230): Verilog HDL assignment warning at GR8RAM.v(138): truncated value with size 32 to match size of target (8) +Warning (10230): Verilog HDL assignment warning at GR8RAM.v(145): truncated value with size 32 to match size of target (8) Info (17026): Resynthesizing 0 WYSIWYG logic cells and I/Os using "area" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched Warning (13024): Output pins are stuck at VCC or GND Warning (13410): Pin "nNMIout" is stuck at VCC @@ -301,17 +301,17 @@ Warning (13024): Output pins are stuck at VCC or GND Warning (13410): Pin "nDMAout" is stuck at VCC Warning (13410): Pin "RAdir" is stuck at VCC Info (17049): 1 registers lost all their fanouts during netlist optimizations. -Info (21057): Implemented 319 device resources after synthesis - the final resource count might be different +Info (21057): Implemented 321 device resources after synthesis - the final resource count might be different Info (21058): Implemented 28 input pins Info (21059): Implemented 35 output pins Info (21060): Implemented 17 bidirectional pins - Info (21061): Implemented 239 logic cells + Info (21061): Implemented 241 logic cells Info (144001): Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 13 warnings Info: Peak virtual memory: 301 megabytes - Info: Processing ended: Tue Apr 20 04:00:06 2021 - Info: Elapsed time: 00:00:06 - Info: Total CPU time (on all processors): 00:00:05 + Info: Processing ended: Tue Apr 20 04:19:44 2021 + Info: Elapsed time: 00:00:05 + Info: Total CPU time (on all processors): 00:00:04 +------------------------------------------+ diff --git a/cpld/output_files/GR8RAM.map.smsg b/cpld/output_files/GR8RAM.map.smsg index 8d8b43e..ffbb919 100755 --- a/cpld/output_files/GR8RAM.map.smsg +++ b/cpld/output_files/GR8RAM.map.smsg @@ -1,2 +1,2 @@ -Warning (10273): Verilog HDL warning at GR8RAM.v(83): extended using "x" or "z" -Warning (10273): Verilog HDL warning at GR8RAM.v(263): extended using "x" or "z" +Warning (10273): Verilog HDL warning at GR8RAM.v(106): extended using "x" or "z" +Warning (10273): Verilog HDL warning at GR8RAM.v(282): extended using "x" or "z" diff --git a/cpld/output_files/GR8RAM.map.summary b/cpld/output_files/GR8RAM.map.summary index 1658f02..8eeb674 100755 --- a/cpld/output_files/GR8RAM.map.summary +++ b/cpld/output_files/GR8RAM.map.summary @@ -1,9 +1,9 @@ -Analysis & Synthesis Status : Successful - Tue Apr 20 04:00:06 2021 +Analysis & Synthesis Status : Successful - Tue Apr 20 04:19:44 2021 Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition Revision Name : GR8RAM Top-level Entity Name : GR8RAM Family : MAX II -Total logic elements : 239 +Total logic elements : 241 Total pins : 80 Total virtual pins : 0 UFM blocks : 0 / 1 ( 0 % ) diff --git a/cpld/output_files/GR8RAM.pof b/cpld/output_files/GR8RAM.pof index f206bca..7723661 100755 Binary files a/cpld/output_files/GR8RAM.pof and b/cpld/output_files/GR8RAM.pof differ diff --git a/cpld/output_files/GR8RAM.sta.rpt b/cpld/output_files/GR8RAM.sta.rpt index 59bf5b6..2aa7fff 100755 --- a/cpld/output_files/GR8RAM.sta.rpt +++ b/cpld/output_files/GR8RAM.sta.rpt @@ -1,5 +1,5 @@ TimeQuest Timing Analyzer report for GR8RAM -Tue Apr 20 04:00:26 2021 +Tue Apr 20 04:20:05 2021 Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition @@ -86,11 +86,11 @@ applicable agreement for further details. ; Maximum allowed ; 2 ; ; ; ; ; Average used ; 1.00 ; -; Maximum used ; 1 ; +; Maximum used ; 2 ; ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; -; Processor 2 ; 0.0% ; +; Processor 2 ; < 0.1% ; +----------------------------+-------------+ @@ -109,7 +109,7 @@ applicable agreement for further details. +------------+-----------------+------------+------+ ; Fmax ; Restricted Fmax ; Clock Name ; Note ; +------------+-----------------+------------+------+ -; 101.04 MHz ; 101.04 MHz ; C25M ; ; +; 103.27 MHz ; 103.27 MHz ; C25M ; ; +------------+-----------------+------------+------+ This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. @@ -119,8 +119,8 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +-------+--------+---------------+ -; C25M ; -9.480 ; -695.573 ; -; PHI0 ; -0.522 ; -0.522 ; +; C25M ; -9.005 ; -699.357 ; +; PHI0 ; -0.425 ; -0.425 ; +-------+--------+---------------+ @@ -129,8 +129,8 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +-------+--------+---------------+ -; PHI0 ; -0.197 ; -0.197 ; -; C25M ; 1.385 ; 0.000 ; +; PHI0 ; -0.248 ; -0.248 ; +; C25M ; 1.400 ; 0.000 ; +-------+--------+---------------+ @@ -139,7 +139,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +-------+--------+---------------+ -; C25M ; -4.399 ; -127.571 ; +; C25M ; -4.412 ; -127.948 ; +-------+--------+---------------+ @@ -148,7 +148,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +-------+-------+---------------+ -; C25M ; 4.845 ; 0.000 ; +; C25M ; 4.858 ; 0.000 ; +-------+-------+---------------+ @@ -167,106 +167,106 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +--------+----------------+----------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+----------------+----------------+--------------+-------------+--------------+------------+------------+ -; -9.480 ; RAMSpecSELr ; SA[5]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.770 ; 7.377 ; -; -9.226 ; RAMSpecSELr ; RCKE~reg0 ; PHI0 ; C25M ; 1.000 ; -2.770 ; 7.123 ; -; -9.117 ; nWEr ; nRCS~reg0 ; PHI0 ; C25M ; 1.000 ; -2.770 ; 7.014 ; -; -9.113 ; nWEr ; RCKE~reg0 ; PHI0 ; C25M ; 1.000 ; -2.770 ; 7.010 ; -; -9.094 ; ROMSpecRDr ; RCKE~reg0 ; PHI0 ; C25M ; 1.000 ; -2.770 ; 6.991 ; -; -8.985 ; RAMSpecSELr ; nRCS~reg0 ; PHI0 ; C25M ; 1.000 ; -2.770 ; 6.882 ; -; -8.897 ; IS.state_bit_0 ; SA[5]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.564 ; -; -8.742 ; RAMSpecSELr ; SA[8]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.770 ; 6.639 ; -; -8.660 ; RAMSpecSELr ; SA[0]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.770 ; 6.557 ; -; -8.653 ; RAMSpecSELr ; SA[1]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.770 ; 6.550 ; -; -8.647 ; RAMSpecSELr ; SA[6]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.770 ; 6.544 ; -; -8.644 ; RAMSpecSELr ; SA[4]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.770 ; 6.541 ; -; -8.619 ; ROMSpecRDr ; nRCS~reg0 ; PHI0 ; C25M ; 1.000 ; -2.770 ; 6.516 ; -; -8.573 ; IS.state_bit_1 ; RCKE~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.240 ; -; -8.539 ; RAMSpecSELr ; SA[7]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.770 ; 6.436 ; -; -8.522 ; PS[1] ; Addr[23] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.189 ; -; -8.522 ; PS[1] ; Addr[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.189 ; -; -8.522 ; PS[1] ; Addr[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.189 ; -; -8.522 ; PS[1] ; Addr[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.189 ; -; -8.522 ; PS[1] ; Addr[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.189 ; -; -8.522 ; PS[1] ; Addr[20] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.189 ; -; -8.522 ; PS[1] ; Addr[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.189 ; -; -8.522 ; PS[1] ; Addr[22] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.189 ; -; -8.492 ; Addr[8] ; RDD[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.159 ; -; -8.470 ; RAMSpecSELr ; SA[3]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.770 ; 6.367 ; -; -8.366 ; PS[2] ; RCKE~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.033 ; -; -8.364 ; IS.state_bit_0 ; SA[0]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.031 ; -; -8.357 ; IS.state_bit_0 ; SA[1]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.024 ; -; -8.319 ; IS.state_bit_1 ; SA[5]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.986 ; -; -8.314 ; IS.state_bit_0 ; RCKE~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.981 ; -; -8.296 ; nWEr ; SDOE ; PHI0 ; C25M ; 1.000 ; -2.770 ; 6.193 ; -; -8.263 ; PS[1] ; RCKE~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.930 ; -; -8.261 ; nWEr ; Addr[23] ; PHI0 ; C25M ; 1.000 ; -2.770 ; 6.158 ; -; -8.261 ; nWEr ; Addr[16] ; PHI0 ; C25M ; 1.000 ; -2.770 ; 6.158 ; -; -8.261 ; nWEr ; Addr[17] ; PHI0 ; C25M ; 1.000 ; -2.770 ; 6.158 ; -; -8.261 ; nWEr ; Addr[18] ; PHI0 ; C25M ; 1.000 ; -2.770 ; 6.158 ; -; -8.261 ; nWEr ; Addr[19] ; PHI0 ; C25M ; 1.000 ; -2.770 ; 6.158 ; -; -8.261 ; nWEr ; Addr[20] ; PHI0 ; C25M ; 1.000 ; -2.770 ; 6.158 ; -; -8.261 ; nWEr ; Addr[21] ; PHI0 ; C25M ; 1.000 ; -2.770 ; 6.158 ; -; -8.261 ; nWEr ; Addr[22] ; PHI0 ; C25M ; 1.000 ; -2.770 ; 6.158 ; -; -8.237 ; RAMSpecSELr ; SA[10]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.770 ; 6.134 ; -; -8.231 ; LS[9] ; IS.state_bit_1 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.898 ; -; -8.204 ; IS.state_bit_1 ; nRCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.871 ; -; -8.198 ; LS[11] ; IS.state_bit_1 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.865 ; -; -8.178 ; IS.state_bit_2 ; RCKE~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.845 ; -; -8.169 ; LS[9] ; IS.state_bit_0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.836 ; -; -8.169 ; RAMSpecSELr ; SBA[0]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.770 ; 6.066 ; -; -8.164 ; RAMSpecSELr ; SDOE ; PHI0 ; C25M ; 1.000 ; -2.770 ; 6.061 ; -; -8.162 ; LS[9] ; IS.state_bit_2 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.829 ; -; -8.159 ; IS.state_bit_0 ; SA[8]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.826 ; -; -8.143 ; PS[1] ; Addr[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.810 ; -; -8.143 ; PS[1] ; Addr[1] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.810 ; -; -8.143 ; PS[1] ; Addr[2] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.810 ; -; -8.143 ; PS[1] ; Addr[3] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.810 ; -; -8.143 ; PS[1] ; Addr[4] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.810 ; -; -8.143 ; PS[1] ; Addr[5] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.810 ; -; -8.143 ; PS[1] ; Addr[6] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.810 ; -; -8.143 ; PS[1] ; Addr[7] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.810 ; -; -8.136 ; LS[11] ; IS.state_bit_0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.803 ; -; -8.133 ; PS[0] ; RCKE~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.800 ; -; -8.130 ; LS[0] ; RCKE~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.797 ; -; -8.129 ; LS[11] ; IS.state_bit_2 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.796 ; -; -8.103 ; PS[3] ; Addr[23] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.770 ; -; -8.103 ; PS[3] ; Addr[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.770 ; -; -8.103 ; PS[3] ; Addr[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.770 ; -; -8.103 ; PS[3] ; Addr[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.770 ; -; -8.103 ; PS[3] ; Addr[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.770 ; -; -8.103 ; PS[3] ; Addr[20] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.770 ; -; -8.103 ; PS[3] ; Addr[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.770 ; -; -8.103 ; PS[3] ; Addr[22] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.770 ; -; -8.081 ; PS[3] ; SA[5]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.748 ; -; -8.080 ; PS[1] ; IS.state_bit_1 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.747 ; -; -8.064 ; IS.state_bit_0 ; SA[6]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.731 ; -; -8.061 ; IS.state_bit_0 ; SA[4]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.728 ; -; -8.044 ; RAMSpecSELr ; SA[2]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.770 ; 5.941 ; -; -8.022 ; LS[8] ; IS.state_bit_1 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.689 ; -; -7.969 ; PS[0] ; SA[5]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.636 ; -; -7.960 ; LS[8] ; IS.state_bit_0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.627 ; -; -7.956 ; IS.state_bit_0 ; SA[7]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.623 ; -; -7.953 ; LS[8] ; IS.state_bit_2 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.620 ; -; -7.945 ; IS.state_bit_0 ; nRCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.612 ; -; -7.905 ; PS[0] ; Addr[23] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.572 ; -; -7.905 ; PS[0] ; Addr[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.572 ; -; -7.905 ; PS[0] ; Addr[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.572 ; -; -7.905 ; PS[0] ; Addr[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.572 ; -; -7.905 ; PS[0] ; Addr[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.572 ; -; -7.905 ; PS[0] ; Addr[20] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.572 ; -; -7.905 ; PS[0] ; Addr[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.572 ; -; -7.905 ; PS[0] ; Addr[22] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.572 ; -; -7.882 ; nWEr ; Addr[0] ; PHI0 ; C25M ; 1.000 ; -2.770 ; 5.779 ; -; -7.882 ; nWEr ; Addr[1] ; PHI0 ; C25M ; 1.000 ; -2.770 ; 5.779 ; -; -7.882 ; nWEr ; Addr[2] ; PHI0 ; C25M ; 1.000 ; -2.770 ; 5.779 ; -; -7.882 ; nWEr ; Addr[3] ; PHI0 ; C25M ; 1.000 ; -2.770 ; 5.779 ; -; -7.882 ; nWEr ; Addr[4] ; PHI0 ; C25M ; 1.000 ; -2.770 ; 5.779 ; -; -7.882 ; nWEr ; Addr[5] ; PHI0 ; C25M ; 1.000 ; -2.770 ; 5.779 ; -; -7.882 ; nWEr ; Addr[6] ; PHI0 ; C25M ; 1.000 ; -2.770 ; 5.779 ; -; -7.882 ; nWEr ; Addr[7] ; PHI0 ; C25M ; 1.000 ; -2.770 ; 5.779 ; -; -7.878 ; RAMSpecSELr ; SBA[1]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.770 ; 5.775 ; -; -7.854 ; PS[1] ; SA[5]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.521 ; -; -7.844 ; REGEN ; Addr[23] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.511 ; +; -9.005 ; RAMSpecSELr ; SA[8]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.894 ; +; -8.961 ; RAMSpecSELr ; SA[6]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.850 ; +; -8.953 ; RAMSpecSELr ; SA[7]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.842 ; +; -8.919 ; nWEr ; RCKE~reg0 ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.808 ; +; -8.916 ; ROMSpecRDr ; RCKE~reg0 ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.805 ; +; -8.897 ; RAMSpecSELr ; SA[2]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.786 ; +; -8.683 ; IS.state_bit_1 ; SA[8]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.350 ; +; -8.631 ; IS.state_bit_1 ; SA[7]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.298 ; +; -8.625 ; IS.state_bit_1 ; SA[6]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.292 ; +; -8.571 ; RAMSpecSELr ; RCKE~reg0 ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.460 ; +; -8.495 ; RAMSpecSELr ; SA[1]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.384 ; +; -8.451 ; LS[10] ; IS.state_bit_0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.118 ; +; -8.428 ; RAMSpecSELr ; SA[5]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.317 ; +; -8.422 ; nWEr ; Addr[0] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.311 ; +; -8.422 ; nWEr ; Addr[1] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.311 ; +; -8.422 ; nWEr ; Addr[2] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.311 ; +; -8.422 ; nWEr ; Addr[3] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.311 ; +; -8.422 ; nWEr ; Addr[4] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.311 ; +; -8.422 ; nWEr ; Addr[5] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.311 ; +; -8.422 ; nWEr ; Addr[6] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.311 ; +; -8.422 ; nWEr ; Addr[7] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.311 ; +; -8.419 ; nWEr ; Addr[10] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.308 ; +; -8.419 ; nWEr ; Addr[11] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.308 ; +; -8.419 ; nWEr ; Addr[12] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.308 ; +; -8.419 ; nWEr ; Addr[13] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.308 ; +; -8.419 ; nWEr ; Addr[14] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.308 ; +; -8.419 ; nWEr ; Addr[15] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.308 ; +; -8.419 ; nWEr ; Addr[8] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.308 ; +; -8.419 ; nWEr ; Addr[9] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.308 ; +; -8.387 ; nWEr ; AddrIncH ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.276 ; +; -8.301 ; LS[11] ; IS.state_bit_0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.968 ; +; -8.289 ; IS.state_bit_0 ; SA[8]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.956 ; +; -8.284 ; nWEr ; nRCS~reg0 ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.173 ; +; -8.265 ; RAMSpecSELr ; SA[0]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.154 ; +; -8.261 ; nWEr ; Addr[23] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.150 ; +; -8.261 ; nWEr ; Addr[16] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.150 ; +; -8.261 ; nWEr ; Addr[17] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.150 ; +; -8.261 ; nWEr ; Addr[18] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.150 ; +; -8.261 ; nWEr ; Addr[19] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.150 ; +; -8.261 ; nWEr ; Addr[20] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.150 ; +; -8.261 ; nWEr ; Addr[21] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.150 ; +; -8.261 ; nWEr ; Addr[22] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.150 ; +; -8.245 ; ROMSpecRDr ; nRCS~reg0 ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.134 ; +; -8.237 ; IS.state_bit_0 ; SA[7]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.904 ; +; -8.231 ; IS.state_bit_0 ; SA[6]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.898 ; +; -8.226 ; RAMSpecSELr ; SA[9]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.115 ; +; -8.222 ; RAMSpecSELr ; SA[11]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.111 ; +; -8.222 ; RAMSpecSELr ; SA[12]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.111 ; +; -8.177 ; IS.state_bit_1 ; SA[2]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.844 ; +; -8.116 ; LS[9] ; IS.state_bit_0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.783 ; +; -8.115 ; PS[0] ; SA[2]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.782 ; +; -8.106 ; RAMSpecSELr ; SA[4]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.778 ; 5.995 ; +; -8.104 ; RAMSpecSELr ; SA[3]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.778 ; 5.993 ; +; -7.954 ; PS[0] ; SA[0]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.621 ; +; -7.928 ; IS.state_bit_1 ; SA[5]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.595 ; +; -7.900 ; RAMSpecSELr ; nRCS~reg0 ; PHI0 ; C25M ; 1.000 ; -2.778 ; 5.789 ; +; -7.896 ; PS[1] ; IS.state_bit_1 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.563 ; +; -7.878 ; PS[1] ; IOROMEN ; C25M ; C25M ; 1.000 ; 0.000 ; 8.545 ; +; -7.844 ; LS[1] ; nRCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.511 ; +; -7.817 ; IS.state_bit_1 ; RCKE~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.484 ; +; -7.817 ; PS[1] ; RCKE~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.484 ; +; -7.804 ; REGEN ; Addr[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.471 ; +; -7.804 ; REGEN ; Addr[1] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.471 ; +; -7.804 ; REGEN ; Addr[2] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.471 ; +; -7.804 ; REGEN ; Addr[3] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.471 ; +; -7.804 ; REGEN ; Addr[4] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.471 ; +; -7.804 ; REGEN ; Addr[5] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.471 ; +; -7.804 ; REGEN ; Addr[6] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.471 ; +; -7.804 ; REGEN ; Addr[7] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.471 ; +; -7.801 ; REGEN ; Addr[10] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.468 ; +; -7.801 ; REGEN ; Addr[11] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.468 ; +; -7.801 ; REGEN ; Addr[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.468 ; +; -7.801 ; REGEN ; Addr[13] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.468 ; +; -7.801 ; REGEN ; Addr[14] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.468 ; +; -7.801 ; REGEN ; Addr[15] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.468 ; +; -7.801 ; REGEN ; Addr[8] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.468 ; +; -7.801 ; REGEN ; Addr[9] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.468 ; +; -7.785 ; LS[10] ; IS.state_bit_2 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.452 ; +; -7.783 ; IS.state_bit_0 ; SA[2]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.450 ; +; -7.775 ; IS.state_bit_1 ; SA[1]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.442 ; +; -7.769 ; REGEN ; AddrIncH ; C25M ; C25M ; 1.000 ; 0.000 ; 8.436 ; +; -7.762 ; IS.state_bit_1 ; SA[4]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.429 ; +; -7.760 ; IS.state_bit_1 ; SA[3]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.427 ; +; -7.741 ; LS[8] ; IS.state_bit_0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.408 ; +; -7.706 ; PS[3] ; SA[8]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.373 ; +; -7.704 ; LS[7] ; IS.state_bit_0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.371 ; +; -7.680 ; IS.state_bit_1 ; SA[0]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.347 ; +; -7.668 ; PS[0] ; SA[1]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.335 ; +; -7.662 ; PS[3] ; SA[6]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.329 ; +; -7.654 ; PS[3] ; SA[7]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.321 ; +; -7.645 ; PS[1] ; REGEN ; C25M ; C25M ; 1.000 ; 0.000 ; 8.312 ; +; -7.643 ; REGEN ; Addr[23] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.310 ; +; -7.643 ; REGEN ; Addr[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.310 ; +; -7.643 ; REGEN ; Addr[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.310 ; +; -7.643 ; REGEN ; Addr[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.310 ; +; -7.643 ; REGEN ; Addr[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.310 ; +; -7.643 ; REGEN ; Addr[20] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.310 ; +; -7.643 ; REGEN ; Addr[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.310 ; +; -7.643 ; REGEN ; Addr[22] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.310 ; +; -7.642 ; LS[1] ; IS.state_bit_0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.309 ; +--------+----------------+----------------+--------------+-------------+--------------+------------+------------+ @@ -275,9 +275,11 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ -; -0.522 ; Addr[23] ; RAMSpecSELr ; C25M ; PHI0 ; 1.000 ; 2.770 ; 3.959 ; -; -0.319 ; REGEN ; RAMSpecSELr ; C25M ; PHI0 ; 1.000 ; 2.770 ; 3.756 ; -; 0.643 ; IOROMEN ; ROMSpecRDr ; C25M ; PHI0 ; 1.000 ; 2.770 ; 2.794 ; +; -0.425 ; Addr[23] ; RAMSpecSELr ; C25M ; PHI0 ; 1.000 ; 2.778 ; 3.870 ; +; -0.265 ; REGEN ; RAMSpecSELr ; C25M ; PHI0 ; 1.000 ; 2.778 ; 3.710 ; +; 0.296 ; IOROMEN ; ROMSpecRDr ; C25M ; PHI0 ; 1.000 ; 2.778 ; 3.149 ; +; 0.609 ; SetFWr[0] ; RAMSpecSELr ; C25M ; PHI0 ; 1.000 ; 2.778 ; 2.836 ; +; 0.694 ; SetFWr[1] ; RAMSpecSELr ; C25M ; PHI0 ; 1.000 ; 2.778 ; 2.751 ; +--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ @@ -286,9 +288,11 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ -; -0.197 ; IOROMEN ; ROMSpecRDr ; C25M ; PHI0 ; 0.000 ; 2.770 ; 2.794 ; -; 0.765 ; REGEN ; RAMSpecSELr ; C25M ; PHI0 ; 0.000 ; 2.770 ; 3.756 ; -; 0.968 ; Addr[23] ; RAMSpecSELr ; C25M ; PHI0 ; 0.000 ; 2.770 ; 3.959 ; +; -0.248 ; SetFWr[1] ; RAMSpecSELr ; C25M ; PHI0 ; 0.000 ; 2.778 ; 2.751 ; +; -0.163 ; SetFWr[0] ; RAMSpecSELr ; C25M ; PHI0 ; 0.000 ; 2.778 ; 2.836 ; +; 0.150 ; IOROMEN ; ROMSpecRDr ; C25M ; PHI0 ; 0.000 ; 2.778 ; 3.149 ; +; 0.711 ; REGEN ; RAMSpecSELr ; C25M ; PHI0 ; 0.000 ; 2.778 ; 3.710 ; +; 0.871 ; Addr[23] ; RAMSpecSELr ; C25M ; PHI0 ; 0.000 ; 2.778 ; 3.870 ; +--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ @@ -297,106 +301,106 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+----------------+----------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +-------+----------------+----------------+--------------+-------------+--------------+------------+------------+ -; 1.385 ; WRD[5] ; WRD[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.606 ; -; 1.402 ; WRD[6] ; WRD[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.623 ; -; 1.402 ; WRD[7] ; WRD[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.623 ; -; 1.412 ; WRD[1] ; WRD[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.633 ; -; 1.414 ; nRESf[1] ; nRESf[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.635 ; -; 1.421 ; nRESf[2] ; nRESf[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.642 ; -; 1.665 ; nRESf[3] ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 1.886 ; -; 1.670 ; PHI0 ; PHI0r1 ; PHI0 ; C25M ; 0.000 ; 3.458 ; 5.349 ; -; 1.738 ; IS.state_bit_2 ; MOSIOE ; C25M ; C25M ; 0.000 ; 0.000 ; 1.959 ; -; 1.849 ; WRD[2] ; WRD[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.070 ; -; 1.871 ; WRD[0] ; WRD[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.092 ; -; 1.907 ; nRESout~reg0 ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.128 ; -; 1.918 ; Bank ; Bank ; C25M ; C25M ; 0.000 ; 0.000 ; 2.139 ; -; 1.939 ; nRESf[2] ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 2.160 ; -; 1.946 ; Addr[7] ; AddrIncM ; C25M ; C25M ; 0.000 ; 0.000 ; 2.167 ; -; 1.961 ; IS.state_bit_0 ; IS.state_bit_0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.182 ; -; 2.011 ; PS[2] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.232 ; -; 2.111 ; WRD[2] ; WRD[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.332 ; +; 1.400 ; WRD[7] ; WRD[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.621 ; +; 1.411 ; WRD[4] ; WRD[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.632 ; +; 1.412 ; WRD[6] ; WRD[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.633 ; +; 1.414 ; nRESf[2] ; nRESf[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.635 ; +; 1.420 ; WRD[0] ; WRD[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.641 ; +; 1.420 ; WRD[3] ; WRD[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.641 ; +; 1.640 ; nRESout~reg0 ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 1.861 ; +; 1.782 ; WRD[2] ; WRD[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.003 ; +; 1.822 ; nRESf[1] ; nRESf[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.043 ; +; 1.930 ; Addr[7] ; AddrIncM ; C25M ; C25M ; 0.000 ; 0.000 ; 2.151 ; +; 1.933 ; nRESf[2] ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 2.154 ; +; 2.063 ; LS[13] ; LS[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.284 ; +; 2.075 ; nRESf[3] ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 2.296 ; +; 2.107 ; LS[7] ; LS[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.328 ; +; 2.117 ; Addr[10] ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; ; 2.117 ; Addr[1] ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; ; 2.117 ; Addr[2] ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; -; 2.117 ; Addr[17] ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; -; 2.117 ; Addr[18] ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; -; 2.118 ; Addr[15] ; Addr[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.339 ; -; 2.124 ; LS[7] ; LS[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.345 ; -; 2.125 ; Addr[16] ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.346 ; -; 2.126 ; Addr[23] ; Addr[23] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ; +; 2.117 ; Bank ; Bank ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; +; 2.117 ; Addr[15] ; Addr[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; +; 2.117 ; LS[8] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; +; 2.117 ; LS[9] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; +; 2.117 ; Addr[9] ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; +; 2.120 ; WRD[1] ; WRD[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.341 ; +; 2.123 ; WRD[2] ; WRD[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.344 ; +; 2.124 ; Addr[16] ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.345 ; +; 2.125 ; Addr[0] ; Addr[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.346 ; +; 2.126 ; LS[4] ; LS[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ; ; 2.126 ; LS[6] ; LS[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ; -; 2.126 ; LS[9] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ; -; 2.127 ; LS[4] ; LS[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.348 ; -; 2.128 ; nRESf[0] ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 2.349 ; -; 2.134 ; LS[8] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.355 ; -; 2.140 ; Addr[0] ; Addr[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.361 ; -; 2.143 ; Addr[9] ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.364 ; -; 2.145 ; Addr[10] ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.366 ; -; 2.154 ; Addr[7] ; Addr[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.375 ; -; 2.170 ; PHI0 ; PHI0r1 ; PHI0 ; C25M ; -0.500 ; 3.458 ; 5.349 ; -; 2.183 ; PS[0] ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.404 ; -; 2.188 ; PS[0] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.409 ; -; 2.196 ; PS[0] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.417 ; -; 2.221 ; Addr[3] ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.442 ; +; 2.126 ; Addr[17] ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ; +; 2.127 ; Addr[23] ; Addr[23] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.348 ; +; 2.127 ; Addr[18] ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.348 ; +; 2.137 ; Addr[7] ; Addr[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.358 ; +; 2.151 ; WRD[4] ; WRD[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.372 ; +; 2.155 ; nRESf[1] ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 2.376 ; +; 2.162 ; PS[2] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.383 ; +; 2.164 ; PS[3] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.385 ; +; 2.175 ; PS[3] ; nRAS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.396 ; +; 2.215 ; nRESf[0] ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 2.436 ; ; 2.222 ; Addr[19] ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.443 ; +; 2.226 ; PHI0 ; PHI0r1 ; PHI0 ; C25M ; 0.000 ; 3.458 ; 5.905 ; ; 2.228 ; AddrIncH ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.449 ; ; 2.230 ; Addr[5] ; Addr[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.451 ; ; 2.230 ; Addr[21] ; Addr[21] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.451 ; +; 2.231 ; Addr[3] ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; ; 2.231 ; Addr[4] ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; ; 2.231 ; Addr[6] ; Addr[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; ; 2.231 ; Addr[20] ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; ; 2.231 ; Addr[22] ; Addr[22] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; ; 2.232 ; LS[10] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.453 ; -; 2.232 ; LS[5] ; LS[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.453 ; +; 2.240 ; LS[3] ; LS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.461 ; ; 2.241 ; Addr[11] ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.462 ; -; 2.248 ; LS[3] ; LS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.469 ; -; 2.249 ; Addr[14] ; Addr[14] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.470 ; -; 2.249 ; LS[13] ; LS[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.470 ; -; 2.253 ; nRESf[1] ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 2.474 ; -; 2.253 ; WRD[1] ; WRD[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.474 ; -; 2.259 ; LS[2] ; LS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.480 ; -; 2.260 ; LS[12] ; LS[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.481 ; -; 2.261 ; Addr[12] ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.482 ; -; 2.261 ; Addr[13] ; Addr[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.482 ; -; 2.262 ; LS[1] ; LS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.483 ; -; 2.262 ; LS[11] ; LS[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.483 ; -; 2.298 ; WRD[3] ; WRD[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.519 ; -; 2.313 ; IS.state_bit_2 ; FCKOE ; C25M ; C25M ; 0.000 ; 0.000 ; 2.534 ; -; 2.334 ; PS[3] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.555 ; -; 2.337 ; PS[3] ; SA[10]~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.558 ; -; 2.342 ; PS[3] ; SBA[0]~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.563 ; -; 2.342 ; PS[2] ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.563 ; -; 2.372 ; LS[0] ; LS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.593 ; -; 2.410 ; nRESf[0] ; nRESf[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.631 ; -; 2.443 ; PHI0r1 ; PHI0r2 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.664 ; -; 2.460 ; WRD[4] ; WRD[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.681 ; -; 2.636 ; WRD[5] ; WRD[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.857 ; -; 2.707 ; WRD[0] ; WRD[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.928 ; -; 2.712 ; IS.state_bit_1 ; IS.state_bit_0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.933 ; -; 2.817 ; Addr[21] ; SA[11]~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.038 ; -; 2.835 ; Addr[0] ; RDD[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.056 ; -; 2.870 ; Addr[0] ; DQML~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.091 ; -; 2.885 ; PS[2] ; SBA[0]~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.106 ; -; 2.915 ; Addr[18] ; RDD[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.136 ; -; 2.939 ; IS.state_bit_2 ; IS.state_bit_2 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.160 ; -; 2.949 ; IS.state_bit_0 ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; +; 2.248 ; LS[12] ; LS[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.469 ; +; 2.249 ; Addr[12] ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.470 ; +; 2.249 ; LS[5] ; LS[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.470 ; +; 2.250 ; LS[11] ; LS[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.471 ; +; 2.251 ; LS[2] ; LS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.472 ; +; 2.251 ; LS[0] ; LS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.472 ; +; 2.252 ; LS[0] ; LS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.473 ; +; 2.260 ; Addr[13] ; Addr[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.481 ; +; 2.262 ; Addr[14] ; Addr[14] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.483 ; +; 2.263 ; WRD[3] ; WRD[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.484 ; +; 2.267 ; WRD[0] ; WRD[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.488 ; +; 2.285 ; WRD[5] ; WRD[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.506 ; +; 2.297 ; IS.state_bit_0 ; IS.state_bit_0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.518 ; +; 2.421 ; nRESf[0] ; nRESf[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.642 ; +; 2.423 ; WRD[1] ; WRD[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.644 ; +; 2.532 ; PS[0] ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.753 ; +; 2.534 ; PS[0] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.755 ; +; 2.537 ; PS[0] ; nRAS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.758 ; +; 2.538 ; PHI0r1 ; PHI0r2 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.759 ; +; 2.545 ; PS[0] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.766 ; +; 2.559 ; Addr[2] ; RDD[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.780 ; +; 2.606 ; AddrIncL ; Addr[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.827 ; +; 2.680 ; Addr[1] ; RDD[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.901 ; +; 2.699 ; PS[2] ; nRAS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.920 ; +; 2.702 ; PS[2] ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.923 ; +; 2.703 ; PS[2] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.924 ; +; 2.726 ; PHI0 ; PHI0r1 ; PHI0 ; C25M ; -0.500 ; 3.458 ; 5.905 ; +; 2.826 ; PHI0r1 ; RCKE~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.047 ; +; 2.860 ; Addr[3] ; RDD[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.081 ; +; 2.905 ; IS.state_bit_0 ; FCS ; C25M ; C25M ; 0.000 ; 0.000 ; 3.126 ; +; 2.939 ; LS[7] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.160 ; +; 2.949 ; Addr[9] ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; +; 2.949 ; LS[9] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; +; 2.949 ; Addr[10] ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; ; 2.949 ; Addr[1] ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; ; 2.949 ; Addr[2] ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; -; 2.949 ; Addr[17] ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; -; 2.949 ; Addr[18] ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; -; 2.956 ; LS[7] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.177 ; -; 2.957 ; Addr[16] ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.178 ; -; 2.958 ; LS[9] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.179 ; -; 2.958 ; IS.state_bit_0 ; FCKOE ; C25M ; C25M ; 0.000 ; 0.000 ; 3.179 ; -; 2.959 ; LS[4] ; LS[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.180 ; -; 2.966 ; LS[8] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.187 ; -; 2.972 ; Addr[0] ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.193 ; -; 2.975 ; Addr[9] ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.196 ; -; 2.977 ; Addr[10] ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.198 ; +; 2.949 ; LS[8] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; +; 2.956 ; Addr[16] ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.177 ; +; 2.957 ; Addr[0] ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.178 ; +; 2.958 ; LS[4] ; LS[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.179 ; +; 2.958 ; Addr[17] ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.179 ; +; 2.959 ; Addr[18] ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.180 ; +; 3.011 ; IS.state_bit_0 ; FCKOE ; C25M ; C25M ; 0.000 ; 0.000 ; 3.232 ; +; 3.014 ; IS.state_bit_0 ; MOSIOE ; C25M ; C25M ; 0.000 ; 0.000 ; 3.235 ; +; 3.050 ; LS[7] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.271 ; +; 3.060 ; LS[9] ; LS[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ; +; 3.060 ; Addr[10] ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ; ; 3.060 ; Addr[2] ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ; -; 3.060 ; Addr[18] ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ; -; 3.060 ; Addr[1] ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ; -; 3.060 ; Addr[17] ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ; -; 3.061 ; IS.state_bit_1 ; FCKOE ; C25M ; C25M ; 0.000 ; 0.000 ; 3.282 ; +; 3.060 ; LS[8] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ; +-------+----------------+----------------+--------------+-------------+--------------+------------+------------+ @@ -405,35 +409,35 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +--------+-----------+----------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+-----------+----------+--------------+-------------+--------------+------------+------------+ -; -4.399 ; nRESr ; Addr[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.066 ; -; -4.399 ; nRESr ; Addr[23] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.066 ; -; -4.399 ; nRESr ; Addr[10] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.066 ; -; -4.399 ; nRESr ; Addr[1] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.066 ; -; -4.399 ; nRESr ; Addr[11] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.066 ; -; -4.399 ; nRESr ; Addr[2] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.066 ; -; -4.399 ; nRESr ; Addr[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.066 ; -; -4.399 ; nRESr ; Bank ; C25M ; C25M ; 1.000 ; 0.000 ; 5.066 ; -; -4.399 ; nRESr ; Addr[3] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.066 ; -; -4.399 ; nRESr ; Addr[13] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.066 ; -; -4.399 ; nRESr ; Addr[4] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.066 ; -; -4.399 ; nRESr ; Addr[14] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.066 ; -; -4.399 ; nRESr ; Addr[5] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.066 ; -; -4.399 ; nRESr ; Addr[15] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.066 ; -; -4.399 ; nRESr ; Addr[6] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.066 ; -; -4.399 ; nRESr ; Addr[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.066 ; -; -4.399 ; nRESr ; Addr[7] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.066 ; -; -4.399 ; nRESr ; Addr[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.066 ; -; -4.399 ; nRESr ; Addr[8] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.066 ; -; -4.399 ; nRESr ; Addr[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.066 ; -; -4.399 ; nRESr ; Addr[9] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.066 ; -; -4.399 ; nRESr ; Addr[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.066 ; -; -4.399 ; nRESr ; Addr[20] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.066 ; -; -4.399 ; nRESr ; Addr[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.066 ; -; -4.399 ; nRESr ; Addr[22] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.066 ; -; -4.399 ; nRESr ; REGEN ; C25M ; C25M ; 1.000 ; 0.000 ; 5.066 ; -; -4.399 ; nRESr ; AddrIncH ; C25M ; C25M ; 1.000 ; 0.000 ; 5.066 ; -; -4.399 ; nRESr ; AddrIncM ; C25M ; C25M ; 1.000 ; 0.000 ; 5.066 ; -; -4.399 ; nRESr ; AddrIncL ; C25M ; C25M ; 1.000 ; 0.000 ; 5.066 ; +; -4.412 ; nRESr ; Addr[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; +; -4.412 ; nRESr ; Addr[23] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; +; -4.412 ; nRESr ; Addr[10] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; +; -4.412 ; nRESr ; Addr[1] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; +; -4.412 ; nRESr ; Addr[11] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; +; -4.412 ; nRESr ; Addr[2] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; +; -4.412 ; nRESr ; Addr[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; +; -4.412 ; nRESr ; Bank ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; +; -4.412 ; nRESr ; Addr[3] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; +; -4.412 ; nRESr ; Addr[13] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; +; -4.412 ; nRESr ; Addr[4] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; +; -4.412 ; nRESr ; Addr[14] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; +; -4.412 ; nRESr ; Addr[5] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; +; -4.412 ; nRESr ; Addr[15] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; +; -4.412 ; nRESr ; Addr[6] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; +; -4.412 ; nRESr ; Addr[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; +; -4.412 ; nRESr ; Addr[7] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; +; -4.412 ; nRESr ; Addr[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; +; -4.412 ; nRESr ; Addr[8] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; +; -4.412 ; nRESr ; Addr[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; +; -4.412 ; nRESr ; Addr[9] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; +; -4.412 ; nRESr ; Addr[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; +; -4.412 ; nRESr ; Addr[20] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; +; -4.412 ; nRESr ; Addr[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; +; -4.412 ; nRESr ; Addr[22] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; +; -4.412 ; nRESr ; REGEN ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; +; -4.412 ; nRESr ; AddrIncH ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; +; -4.412 ; nRESr ; AddrIncM ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; +; -4.412 ; nRESr ; AddrIncL ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; +--------+-----------+----------+--------------+-------------+--------------+------------+------------+ @@ -442,35 +446,35 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+-----------+----------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +-------+-----------+----------+--------------+-------------+--------------+------------+------------+ -; 4.845 ; nRESr ; Addr[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.066 ; -; 4.845 ; nRESr ; Addr[23] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.066 ; -; 4.845 ; nRESr ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.066 ; -; 4.845 ; nRESr ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.066 ; -; 4.845 ; nRESr ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.066 ; -; 4.845 ; nRESr ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.066 ; -; 4.845 ; nRESr ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.066 ; -; 4.845 ; nRESr ; Bank ; C25M ; C25M ; 0.000 ; 0.000 ; 5.066 ; -; 4.845 ; nRESr ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.066 ; -; 4.845 ; nRESr ; Addr[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.066 ; -; 4.845 ; nRESr ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.066 ; -; 4.845 ; nRESr ; Addr[14] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.066 ; -; 4.845 ; nRESr ; Addr[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.066 ; -; 4.845 ; nRESr ; Addr[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.066 ; -; 4.845 ; nRESr ; Addr[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.066 ; -; 4.845 ; nRESr ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.066 ; -; 4.845 ; nRESr ; Addr[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.066 ; -; 4.845 ; nRESr ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.066 ; -; 4.845 ; nRESr ; Addr[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.066 ; -; 4.845 ; nRESr ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.066 ; -; 4.845 ; nRESr ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.066 ; -; 4.845 ; nRESr ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.066 ; -; 4.845 ; nRESr ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.066 ; -; 4.845 ; nRESr ; Addr[21] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.066 ; -; 4.845 ; nRESr ; Addr[22] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.066 ; -; 4.845 ; nRESr ; REGEN ; C25M ; C25M ; 0.000 ; 0.000 ; 5.066 ; -; 4.845 ; nRESr ; AddrIncH ; C25M ; C25M ; 0.000 ; 0.000 ; 5.066 ; -; 4.845 ; nRESr ; AddrIncM ; C25M ; C25M ; 0.000 ; 0.000 ; 5.066 ; -; 4.845 ; nRESr ; AddrIncL ; C25M ; C25M ; 0.000 ; 0.000 ; 5.066 ; +; 4.858 ; nRESr ; Addr[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; +; 4.858 ; nRESr ; Addr[23] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; +; 4.858 ; nRESr ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; +; 4.858 ; nRESr ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; +; 4.858 ; nRESr ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; +; 4.858 ; nRESr ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; +; 4.858 ; nRESr ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; +; 4.858 ; nRESr ; Bank ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; +; 4.858 ; nRESr ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; +; 4.858 ; nRESr ; Addr[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; +; 4.858 ; nRESr ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; +; 4.858 ; nRESr ; Addr[14] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; +; 4.858 ; nRESr ; Addr[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; +; 4.858 ; nRESr ; Addr[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; +; 4.858 ; nRESr ; Addr[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; +; 4.858 ; nRESr ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; +; 4.858 ; nRESr ; Addr[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; +; 4.858 ; nRESr ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; +; 4.858 ; nRESr ; Addr[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; +; 4.858 ; nRESr ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; +; 4.858 ; nRESr ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; +; 4.858 ; nRESr ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; +; 4.858 ; nRESr ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; +; 4.858 ; nRESr ; Addr[21] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; +; 4.858 ; nRESr ; Addr[22] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; +; 4.858 ; nRESr ; REGEN ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; +; 4.858 ; nRESr ; AddrIncH ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; +; 4.858 ; nRESr ; AddrIncM ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; +; 4.858 ; nRESr ; AddrIncL ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; +-------+-----------+----------+--------------+-------------+--------------+------------+------------+ @@ -610,68 +614,65 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-----------+------------+--------+--------+------------+-----------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+--------+--------+------------+-----------------+ -; MISO ; C25M ; 3.647 ; 3.647 ; Rise ; C25M ; -; MOSI ; C25M ; 3.258 ; 3.258 ; Rise ; C25M ; -; PHI0 ; C25M ; 2.224 ; 2.224 ; Rise ; C25M ; -; RA[*] ; C25M ; 14.550 ; 14.550 ; Rise ; C25M ; -; RA[0] ; C25M ; 9.707 ; 9.707 ; Rise ; C25M ; -; RA[1] ; C25M ; 9.383 ; 9.383 ; Rise ; C25M ; -; RA[2] ; C25M ; 9.220 ; 9.220 ; Rise ; C25M ; -; RA[3] ; C25M ; 9.411 ; 9.411 ; Rise ; C25M ; -; RA[4] ; C25M ; 6.312 ; 6.312 ; Rise ; C25M ; -; RA[5] ; C25M ; 6.723 ; 6.723 ; Rise ; C25M ; -; RA[6] ; C25M ; 6.226 ; 6.226 ; Rise ; C25M ; -; RA[7] ; C25M ; 9.810 ; 9.810 ; Rise ; C25M ; -; RA[8] ; C25M ; 13.947 ; 13.947 ; Rise ; C25M ; -; RA[9] ; C25M ; 14.550 ; 14.550 ; Rise ; C25M ; -; RA[10] ; C25M ; 13.252 ; 13.252 ; Rise ; C25M ; -; RA[11] ; C25M ; 13.106 ; 13.106 ; Rise ; C25M ; -; RA[12] ; C25M ; 12.557 ; 12.557 ; Rise ; C25M ; -; RA[13] ; C25M ; 12.912 ; 12.912 ; Rise ; C25M ; -; RA[14] ; C25M ; 12.536 ; 12.536 ; Rise ; C25M ; -; RA[15] ; C25M ; 12.221 ; 12.221 ; Rise ; C25M ; -; RD[*] ; C25M ; 5.373 ; 5.373 ; Rise ; C25M ; -; RD[0] ; C25M ; 4.708 ; 4.708 ; Rise ; C25M ; -; RD[1] ; C25M ; 4.030 ; 4.030 ; Rise ; C25M ; -; RD[2] ; C25M ; 3.966 ; 3.966 ; Rise ; C25M ; -; RD[3] ; C25M ; 4.000 ; 4.000 ; Rise ; C25M ; -; RD[4] ; C25M ; 4.128 ; 4.128 ; Rise ; C25M ; -; RD[5] ; C25M ; 4.589 ; 4.589 ; Rise ; C25M ; -; RD[6] ; C25M ; 4.796 ; 4.796 ; Rise ; C25M ; -; RD[7] ; C25M ; 5.373 ; 5.373 ; Rise ; C25M ; -; SD[*] ; C25M ; 5.245 ; 5.245 ; Rise ; C25M ; -; SD[0] ; C25M ; 5.245 ; 5.245 ; Rise ; C25M ; -; SD[1] ; C25M ; 3.881 ; 3.881 ; Rise ; C25M ; -; SD[2] ; C25M ; 5.072 ; 5.072 ; Rise ; C25M ; -; SD[3] ; C25M ; 4.744 ; 4.744 ; Rise ; C25M ; -; SD[4] ; C25M ; 3.461 ; 3.461 ; Rise ; C25M ; -; SD[5] ; C25M ; 3.317 ; 3.317 ; Rise ; C25M ; -; SD[6] ; C25M ; 4.210 ; 4.210 ; Rise ; C25M ; -; SD[7] ; C25M ; 3.715 ; 3.715 ; Rise ; C25M ; -; SetFW[*] ; C25M ; 8.003 ; 8.003 ; Rise ; C25M ; -; SetFW[0] ; C25M ; 4.445 ; 4.445 ; Rise ; C25M ; -; SetFW[1] ; C25M ; 8.003 ; 8.003 ; Rise ; C25M ; -; nDEVSEL ; C25M ; 8.537 ; 8.537 ; Rise ; C25M ; -; nIOSEL ; C25M ; 7.483 ; 7.483 ; Rise ; C25M ; -; nRES ; C25M ; 5.821 ; 5.821 ; Rise ; C25M ; -; RA[*] ; PHI0 ; 7.025 ; 7.025 ; Rise ; PHI0 ; -; RA[0] ; PHI0 ; 3.368 ; 3.368 ; Rise ; PHI0 ; -; RA[1] ; PHI0 ; 3.076 ; 3.076 ; Rise ; PHI0 ; -; RA[2] ; PHI0 ; 3.235 ; 3.235 ; Rise ; PHI0 ; -; RA[3] ; PHI0 ; 3.426 ; 3.426 ; Rise ; PHI0 ; -; RA[7] ; PHI0 ; 2.285 ; 2.285 ; Rise ; PHI0 ; -; RA[8] ; PHI0 ; 6.422 ; 6.422 ; Rise ; PHI0 ; -; RA[9] ; PHI0 ; 7.025 ; 7.025 ; Rise ; PHI0 ; -; RA[10] ; PHI0 ; 5.727 ; 5.727 ; Rise ; PHI0 ; -; RA[11] ; PHI0 ; 5.581 ; 5.581 ; Rise ; PHI0 ; -; RA[12] ; PHI0 ; 5.032 ; 5.032 ; Rise ; PHI0 ; -; RA[13] ; PHI0 ; 5.387 ; 5.387 ; Rise ; PHI0 ; -; RA[14] ; PHI0 ; 5.011 ; 5.011 ; Rise ; PHI0 ; -; RA[15] ; PHI0 ; 4.696 ; 4.696 ; Rise ; PHI0 ; -; SetFW[*] ; PHI0 ; 2.529 ; 2.529 ; Rise ; PHI0 ; -; SetFW[0] ; PHI0 ; 0.787 ; 0.787 ; Rise ; PHI0 ; -; SetFW[1] ; PHI0 ; 2.529 ; 2.529 ; Rise ; PHI0 ; -; nWE ; PHI0 ; 1.133 ; 1.133 ; Rise ; PHI0 ; +; MISO ; C25M ; 4.236 ; 4.236 ; Rise ; C25M ; +; MOSI ; C25M ; 4.174 ; 4.174 ; Rise ; C25M ; +; PHI0 ; C25M ; 2.780 ; 2.780 ; Rise ; C25M ; +; RA[*] ; C25M ; 13.704 ; 13.704 ; Rise ; C25M ; +; RA[0] ; C25M ; 9.040 ; 9.040 ; Rise ; C25M ; +; RA[1] ; C25M ; 10.111 ; 10.111 ; Rise ; C25M ; +; RA[2] ; C25M ; 11.221 ; 11.221 ; Rise ; C25M ; +; RA[3] ; C25M ; 11.322 ; 11.322 ; Rise ; C25M ; +; RA[4] ; C25M ; 6.069 ; 6.069 ; Rise ; C25M ; +; RA[5] ; C25M ; 5.790 ; 5.790 ; Rise ; C25M ; +; RA[6] ; C25M ; 7.139 ; 7.139 ; Rise ; C25M ; +; RA[7] ; C25M ; 10.088 ; 10.088 ; Rise ; C25M ; +; RA[8] ; C25M ; 13.349 ; 13.349 ; Rise ; C25M ; +; RA[9] ; C25M ; 13.704 ; 13.704 ; Rise ; C25M ; +; RA[10] ; C25M ; 12.357 ; 12.357 ; Rise ; C25M ; +; RA[11] ; C25M ; 12.145 ; 12.145 ; Rise ; C25M ; +; RA[12] ; C25M ; 12.246 ; 12.246 ; Rise ; C25M ; +; RA[13] ; C25M ; 11.874 ; 11.874 ; Rise ; C25M ; +; RA[14] ; C25M ; 12.544 ; 12.544 ; Rise ; C25M ; +; RA[15] ; C25M ; 11.995 ; 11.995 ; Rise ; C25M ; +; RD[*] ; C25M ; 6.903 ; 6.903 ; Rise ; C25M ; +; RD[0] ; C25M ; 4.401 ; 4.401 ; Rise ; C25M ; +; RD[1] ; C25M ; 4.653 ; 4.653 ; Rise ; C25M ; +; RD[2] ; C25M ; 3.968 ; 3.968 ; Rise ; C25M ; +; RD[3] ; C25M ; 4.146 ; 4.146 ; Rise ; C25M ; +; RD[4] ; C25M ; 4.101 ; 4.101 ; Rise ; C25M ; +; RD[5] ; C25M ; 4.868 ; 4.868 ; Rise ; C25M ; +; RD[6] ; C25M ; 4.516 ; 4.516 ; Rise ; C25M ; +; RD[7] ; C25M ; 6.903 ; 6.903 ; Rise ; C25M ; +; SD[*] ; C25M ; 5.643 ; 5.643 ; Rise ; C25M ; +; SD[0] ; C25M ; 4.467 ; 4.467 ; Rise ; C25M ; +; SD[1] ; C25M ; 5.643 ; 5.643 ; Rise ; C25M ; +; SD[2] ; C25M ; 3.772 ; 3.772 ; Rise ; C25M ; +; SD[3] ; C25M ; 3.824 ; 3.824 ; Rise ; C25M ; +; SD[4] ; C25M ; 4.593 ; 4.593 ; Rise ; C25M ; +; SD[5] ; C25M ; 4.266 ; 4.266 ; Rise ; C25M ; +; SD[6] ; C25M ; 3.851 ; 3.851 ; Rise ; C25M ; +; SD[7] ; C25M ; 3.789 ; 3.789 ; Rise ; C25M ; +; SetFW[*] ; C25M ; 3.175 ; 3.175 ; Rise ; C25M ; +; SetFW[0] ; C25M ; 2.614 ; 2.614 ; Rise ; C25M ; +; SetFW[1] ; C25M ; 3.175 ; 3.175 ; Rise ; C25M ; +; nDEVSEL ; C25M ; 8.361 ; 8.361 ; Rise ; C25M ; +; nIOSEL ; C25M ; 6.803 ; 6.803 ; Rise ; C25M ; +; nRES ; C25M ; 3.239 ; 3.239 ; Rise ; C25M ; +; RA[*] ; PHI0 ; 6.165 ; 6.165 ; Rise ; PHI0 ; +; RA[0] ; PHI0 ; 3.454 ; 3.454 ; Rise ; PHI0 ; +; RA[1] ; PHI0 ; 2.966 ; 2.966 ; Rise ; PHI0 ; +; RA[2] ; PHI0 ; 4.328 ; 4.328 ; Rise ; PHI0 ; +; RA[3] ; PHI0 ; 4.429 ; 4.429 ; Rise ; PHI0 ; +; RA[7] ; PHI0 ; 2.549 ; 2.549 ; Rise ; PHI0 ; +; RA[8] ; PHI0 ; 5.810 ; 5.810 ; Rise ; PHI0 ; +; RA[9] ; PHI0 ; 6.165 ; 6.165 ; Rise ; PHI0 ; +; RA[10] ; PHI0 ; 4.818 ; 4.818 ; Rise ; PHI0 ; +; RA[11] ; PHI0 ; 4.606 ; 4.606 ; Rise ; PHI0 ; +; RA[12] ; PHI0 ; 4.707 ; 4.707 ; Rise ; PHI0 ; +; RA[13] ; PHI0 ; 4.335 ; 4.335 ; Rise ; PHI0 ; +; RA[14] ; PHI0 ; 5.005 ; 5.005 ; Rise ; PHI0 ; +; RA[15] ; PHI0 ; 4.456 ; 4.456 ; Rise ; PHI0 ; +; nWE ; PHI0 ; 1.098 ; 1.098 ; Rise ; PHI0 ; +-----------+------------+--------+--------+------------+-----------------+ @@ -680,68 +681,65 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-----------+------------+--------+--------+------------+-----------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+--------+--------+------------+-----------------+ -; MISO ; C25M ; -3.093 ; -3.093 ; Rise ; C25M ; -; MOSI ; C25M ; -2.704 ; -2.704 ; Rise ; C25M ; -; PHI0 ; C25M ; -1.670 ; -1.670 ; Rise ; C25M ; -; RA[*] ; C25M ; -3.926 ; -3.926 ; Rise ; C25M ; -; RA[0] ; C25M ; -5.435 ; -5.435 ; Rise ; C25M ; -; RA[1] ; C25M ; -4.639 ; -4.639 ; Rise ; C25M ; -; RA[2] ; C25M ; -4.352 ; -4.352 ; Rise ; C25M ; -; RA[3] ; C25M ; -6.076 ; -6.076 ; Rise ; C25M ; -; RA[4] ; C25M ; -5.758 ; -5.758 ; Rise ; C25M ; -; RA[5] ; C25M ; -6.169 ; -6.169 ; Rise ; C25M ; -; RA[6] ; C25M ; -5.672 ; -5.672 ; Rise ; C25M ; -; RA[7] ; C25M ; -5.342 ; -5.342 ; Rise ; C25M ; -; RA[8] ; C25M ; -4.277 ; -4.277 ; Rise ; C25M ; -; RA[9] ; C25M ; -4.193 ; -4.193 ; Rise ; C25M ; -; RA[10] ; C25M ; -4.568 ; -4.568 ; Rise ; C25M ; -; RA[11] ; C25M ; -3.926 ; -3.926 ; Rise ; C25M ; -; RA[12] ; C25M ; -9.369 ; -9.369 ; Rise ; C25M ; -; RA[13] ; C25M ; -9.724 ; -9.724 ; Rise ; C25M ; -; RA[14] ; C25M ; -9.348 ; -9.348 ; Rise ; C25M ; -; RA[15] ; C25M ; -9.033 ; -9.033 ; Rise ; C25M ; -; RD[*] ; C25M ; -2.089 ; -2.089 ; Rise ; C25M ; -; RD[0] ; C25M ; -2.153 ; -2.153 ; Rise ; C25M ; -; RD[1] ; C25M ; -2.194 ; -2.194 ; Rise ; C25M ; -; RD[2] ; C25M ; -2.124 ; -2.124 ; Rise ; C25M ; -; RD[3] ; C25M ; -2.089 ; -2.089 ; Rise ; C25M ; -; RD[4] ; C25M ; -2.109 ; -2.109 ; Rise ; C25M ; -; RD[5] ; C25M ; -2.138 ; -2.138 ; Rise ; C25M ; -; RD[6] ; C25M ; -2.661 ; -2.661 ; Rise ; C25M ; -; RD[7] ; C25M ; -3.452 ; -3.452 ; Rise ; C25M ; -; SD[*] ; C25M ; -2.763 ; -2.763 ; Rise ; C25M ; -; SD[0] ; C25M ; -4.691 ; -4.691 ; Rise ; C25M ; -; SD[1] ; C25M ; -3.327 ; -3.327 ; Rise ; C25M ; -; SD[2] ; C25M ; -4.518 ; -4.518 ; Rise ; C25M ; -; SD[3] ; C25M ; -4.190 ; -4.190 ; Rise ; C25M ; -; SD[4] ; C25M ; -2.907 ; -2.907 ; Rise ; C25M ; -; SD[5] ; C25M ; -2.763 ; -2.763 ; Rise ; C25M ; -; SD[6] ; C25M ; -3.656 ; -3.656 ; Rise ; C25M ; -; SD[7] ; C25M ; -3.161 ; -3.161 ; Rise ; C25M ; -; SetFW[*] ; C25M ; -3.891 ; -3.891 ; Rise ; C25M ; -; SetFW[0] ; C25M ; -3.891 ; -3.891 ; Rise ; C25M ; -; SetFW[1] ; C25M ; -4.150 ; -4.150 ; Rise ; C25M ; -; nDEVSEL ; C25M ; -3.415 ; -3.415 ; Rise ; C25M ; -; nIOSEL ; C25M ; -6.363 ; -6.363 ; Rise ; C25M ; -; nRES ; C25M ; -5.267 ; -5.267 ; Rise ; C25M ; -; RA[*] ; PHI0 ; -0.733 ; -0.733 ; Rise ; PHI0 ; -; RA[0] ; PHI0 ; -2.814 ; -2.814 ; Rise ; PHI0 ; -; RA[1] ; PHI0 ; -2.522 ; -2.522 ; Rise ; PHI0 ; -; RA[2] ; PHI0 ; -2.681 ; -2.681 ; Rise ; PHI0 ; -; RA[3] ; PHI0 ; -2.872 ; -2.872 ; Rise ; PHI0 ; -; RA[7] ; PHI0 ; -1.731 ; -1.731 ; Rise ; PHI0 ; -; RA[8] ; PHI0 ; -2.126 ; -2.126 ; Rise ; PHI0 ; -; RA[9] ; PHI0 ; -2.729 ; -2.729 ; Rise ; PHI0 ; -; RA[10] ; PHI0 ; -1.431 ; -1.431 ; Rise ; PHI0 ; -; RA[11] ; PHI0 ; -0.804 ; -0.804 ; Rise ; PHI0 ; -; RA[12] ; PHI0 ; -1.069 ; -1.069 ; Rise ; PHI0 ; -; RA[13] ; PHI0 ; -1.424 ; -1.424 ; Rise ; PHI0 ; -; RA[14] ; PHI0 ; -1.048 ; -1.048 ; Rise ; PHI0 ; -; RA[15] ; PHI0 ; -0.733 ; -0.733 ; Rise ; PHI0 ; -; SetFW[*] ; PHI0 ; -0.233 ; -0.233 ; Rise ; PHI0 ; -; SetFW[0] ; PHI0 ; -0.233 ; -0.233 ; Rise ; PHI0 ; -; SetFW[1] ; PHI0 ; -1.975 ; -1.975 ; Rise ; PHI0 ; -; nWE ; PHI0 ; 0.253 ; 0.253 ; Rise ; PHI0 ; +; MISO ; C25M ; -3.682 ; -3.682 ; Rise ; C25M ; +; MOSI ; C25M ; -3.620 ; -3.620 ; Rise ; C25M ; +; PHI0 ; C25M ; -2.226 ; -2.226 ; Rise ; C25M ; +; RA[*] ; C25M ; -3.852 ; -3.852 ; Rise ; C25M ; +; RA[0] ; C25M ; -4.647 ; -4.647 ; Rise ; C25M ; +; RA[1] ; C25M ; -4.783 ; -4.783 ; Rise ; C25M ; +; RA[2] ; C25M ; -4.332 ; -4.332 ; Rise ; C25M ; +; RA[3] ; C25M ; -3.852 ; -3.852 ; Rise ; C25M ; +; RA[4] ; C25M ; -5.515 ; -5.515 ; Rise ; C25M ; +; RA[5] ; C25M ; -5.236 ; -5.236 ; Rise ; C25M ; +; RA[6] ; C25M ; -6.585 ; -6.585 ; Rise ; C25M ; +; RA[7] ; C25M ; -4.632 ; -4.632 ; Rise ; C25M ; +; RA[8] ; C25M ; -4.901 ; -4.901 ; Rise ; C25M ; +; RA[9] ; C25M ; -5.857 ; -5.857 ; Rise ; C25M ; +; RA[10] ; C25M ; -5.398 ; -5.398 ; Rise ; C25M ; +; RA[11] ; C25M ; -4.066 ; -4.066 ; Rise ; C25M ; +; RA[12] ; C25M ; -9.038 ; -9.038 ; Rise ; C25M ; +; RA[13] ; C25M ; -8.666 ; -8.666 ; Rise ; C25M ; +; RA[14] ; C25M ; -9.336 ; -9.336 ; Rise ; C25M ; +; RA[15] ; C25M ; -8.787 ; -8.787 ; Rise ; C25M ; +; RD[*] ; C25M ; -2.106 ; -2.106 ; Rise ; C25M ; +; RD[0] ; C25M ; -2.689 ; -2.689 ; Rise ; C25M ; +; RD[1] ; C25M ; -2.558 ; -2.558 ; Rise ; C25M ; +; RD[2] ; C25M ; -2.686 ; -2.686 ; Rise ; C25M ; +; RD[3] ; C25M ; -2.620 ; -2.620 ; Rise ; C25M ; +; RD[4] ; C25M ; -2.645 ; -2.645 ; Rise ; C25M ; +; RD[5] ; C25M ; -2.677 ; -2.677 ; Rise ; C25M ; +; RD[6] ; C25M ; -2.106 ; -2.106 ; Rise ; C25M ; +; RD[7] ; C25M ; -2.154 ; -2.154 ; Rise ; C25M ; +; SD[*] ; C25M ; -3.218 ; -3.218 ; Rise ; C25M ; +; SD[0] ; C25M ; -3.913 ; -3.913 ; Rise ; C25M ; +; SD[1] ; C25M ; -5.089 ; -5.089 ; Rise ; C25M ; +; SD[2] ; C25M ; -3.218 ; -3.218 ; Rise ; C25M ; +; SD[3] ; C25M ; -3.270 ; -3.270 ; Rise ; C25M ; +; SD[4] ; C25M ; -4.039 ; -4.039 ; Rise ; C25M ; +; SD[5] ; C25M ; -3.712 ; -3.712 ; Rise ; C25M ; +; SD[6] ; C25M ; -3.297 ; -3.297 ; Rise ; C25M ; +; SD[7] ; C25M ; -3.235 ; -3.235 ; Rise ; C25M ; +; SetFW[*] ; C25M ; -2.060 ; -2.060 ; Rise ; C25M ; +; SetFW[0] ; C25M ; -2.060 ; -2.060 ; Rise ; C25M ; +; SetFW[1] ; C25M ; -2.621 ; -2.621 ; Rise ; C25M ; +; nDEVSEL ; C25M ; -2.931 ; -2.931 ; Rise ; C25M ; +; nIOSEL ; C25M ; -6.016 ; -6.016 ; Rise ; C25M ; +; nRES ; C25M ; -2.685 ; -2.685 ; Rise ; C25M ; +; RA[*] ; PHI0 ; -0.955 ; -0.955 ; Rise ; PHI0 ; +; RA[0] ; PHI0 ; -2.900 ; -2.900 ; Rise ; PHI0 ; +; RA[1] ; PHI0 ; -2.412 ; -2.412 ; Rise ; PHI0 ; +; RA[2] ; PHI0 ; -3.774 ; -3.774 ; Rise ; PHI0 ; +; RA[3] ; PHI0 ; -3.875 ; -3.875 ; Rise ; PHI0 ; +; RA[7] ; PHI0 ; -1.995 ; -1.995 ; Rise ; PHI0 ; +; RA[8] ; PHI0 ; -2.159 ; -2.159 ; Rise ; PHI0 ; +; RA[9] ; PHI0 ; -2.514 ; -2.514 ; Rise ; PHI0 ; +; RA[10] ; PHI0 ; -1.167 ; -1.167 ; Rise ; PHI0 ; +; RA[11] ; PHI0 ; -0.955 ; -0.955 ; Rise ; PHI0 ; +; RA[12] ; PHI0 ; -3.055 ; -3.055 ; Rise ; PHI0 ; +; RA[13] ; PHI0 ; -2.683 ; -2.683 ; Rise ; PHI0 ; +; RA[14] ; PHI0 ; -3.353 ; -3.353 ; Rise ; PHI0 ; +; RA[15] ; PHI0 ; -2.804 ; -2.804 ; Rise ; PHI0 ; +; nWE ; PHI0 ; -0.009 ; -0.009 ; Rise ; PHI0 ; +-----------+------------+--------+--------+------------+-----------------+ @@ -750,55 +748,55 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-----------+------------+--------+--------+------------+-----------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+--------+--------+------------+-----------------+ -; DQMH ; C25M ; 9.374 ; 9.374 ; Rise ; C25M ; -; DQML ; C25M ; 6.924 ; 6.924 ; Rise ; C25M ; -; FCK ; C25M ; 8.081 ; 8.081 ; Rise ; C25M ; -; MOSI ; C25M ; 8.903 ; 8.903 ; Rise ; C25M ; -; RCKE ; C25M ; 9.484 ; 9.484 ; Rise ; C25M ; -; RD[*] ; C25M ; 9.917 ; 9.917 ; Rise ; C25M ; -; RD[0] ; C25M ; 8.346 ; 8.346 ; Rise ; C25M ; -; RD[1] ; C25M ; 8.265 ; 8.265 ; Rise ; C25M ; -; RD[2] ; C25M ; 8.346 ; 8.346 ; Rise ; C25M ; -; RD[3] ; C25M ; 8.201 ; 8.201 ; Rise ; C25M ; -; RD[4] ; C25M ; 9.375 ; 9.375 ; Rise ; C25M ; -; RD[5] ; C25M ; 8.984 ; 8.984 ; Rise ; C25M ; -; RD[6] ; C25M ; 8.913 ; 8.913 ; Rise ; C25M ; -; RD[7] ; C25M ; 9.917 ; 9.917 ; Rise ; C25M ; -; RDdir ; C25M ; 16.629 ; 16.629 ; Rise ; C25M ; -; SA[*] ; C25M ; 9.394 ; 9.394 ; Rise ; C25M ; -; SA[0] ; C25M ; 8.606 ; 8.606 ; Rise ; C25M ; -; SA[1] ; C25M ; 8.584 ; 8.584 ; Rise ; C25M ; -; SA[2] ; C25M ; 8.798 ; 8.798 ; Rise ; C25M ; -; SA[3] ; C25M ; 8.651 ; 8.651 ; Rise ; C25M ; -; SA[4] ; C25M ; 8.242 ; 8.242 ; Rise ; C25M ; -; SA[5] ; C25M ; 8.647 ; 8.647 ; Rise ; C25M ; -; SA[6] ; C25M ; 8.669 ; 8.669 ; Rise ; C25M ; -; SA[7] ; C25M ; 8.116 ; 8.116 ; Rise ; C25M ; -; SA[8] ; C25M ; 8.234 ; 8.234 ; Rise ; C25M ; -; SA[9] ; C25M ; 7.567 ; 7.567 ; Rise ; C25M ; -; SA[10] ; C25M ; 9.394 ; 9.394 ; Rise ; C25M ; -; SA[11] ; C25M ; 8.116 ; 8.116 ; Rise ; C25M ; -; SA[12] ; C25M ; 7.570 ; 7.570 ; Rise ; C25M ; -; SBA[*] ; C25M ; 8.077 ; 8.077 ; Rise ; C25M ; -; SBA[0] ; C25M ; 8.073 ; 8.073 ; Rise ; C25M ; -; SBA[1] ; C25M ; 8.077 ; 8.077 ; Rise ; C25M ; -; SD[*] ; C25M ; 8.674 ; 8.674 ; Rise ; C25M ; -; SD[0] ; C25M ; 8.113 ; 8.113 ; Rise ; C25M ; -; SD[1] ; C25M ; 8.097 ; 8.097 ; Rise ; C25M ; -; SD[2] ; C25M ; 8.574 ; 8.574 ; Rise ; C25M ; -; SD[3] ; C25M ; 8.249 ; 8.249 ; Rise ; C25M ; -; SD[4] ; C25M ; 8.125 ; 8.125 ; Rise ; C25M ; -; SD[5] ; C25M ; 8.113 ; 8.113 ; Rise ; C25M ; -; SD[6] ; C25M ; 8.674 ; 8.674 ; Rise ; C25M ; -; SD[7] ; C25M ; 8.241 ; 8.241 ; Rise ; C25M ; -; nCAS ; C25M ; 8.329 ; 8.329 ; Rise ; C25M ; -; nFCS ; C25M ; 6.964 ; 6.964 ; Rise ; C25M ; -; nRAS ; C25M ; 8.349 ; 8.349 ; Rise ; C25M ; -; nRCS ; C25M ; 9.461 ; 9.461 ; Rise ; C25M ; -; nRESout ; C25M ; 8.159 ; 8.159 ; Rise ; C25M ; -; nSWE ; C25M ; 8.815 ; 8.815 ; Rise ; C25M ; -; RDdir ; PHI0 ; 11.026 ; 11.026 ; Rise ; PHI0 ; -; RDdir ; PHI0 ; 11.026 ; 11.026 ; Fall ; PHI0 ; +; DQMH ; C25M ; 9.305 ; 9.305 ; Rise ; C25M ; +; DQML ; C25M ; 9.483 ; 9.483 ; Rise ; C25M ; +; FCK ; C25M ; 9.008 ; 9.008 ; Rise ; C25M ; +; MOSI ; C25M ; 8.844 ; 8.844 ; Rise ; C25M ; +; RCKE ; C25M ; 9.013 ; 9.013 ; Rise ; C25M ; +; RD[*] ; C25M ; 9.287 ; 9.287 ; Rise ; C25M ; +; RD[0] ; C25M ; 8.456 ; 8.456 ; Rise ; C25M ; +; RD[1] ; C25M ; 8.246 ; 8.246 ; Rise ; C25M ; +; RD[2] ; C25M ; 8.212 ; 8.212 ; Rise ; C25M ; +; RD[3] ; C25M ; 8.920 ; 8.920 ; Rise ; C25M ; +; RD[4] ; C25M ; 8.200 ; 8.200 ; Rise ; C25M ; +; RD[5] ; C25M ; 8.222 ; 8.222 ; Rise ; C25M ; +; RD[6] ; C25M ; 8.841 ; 8.841 ; Rise ; C25M ; +; RD[7] ; C25M ; 9.287 ; 9.287 ; Rise ; C25M ; +; RDdir ; C25M ; 13.847 ; 13.847 ; Rise ; C25M ; +; SA[*] ; C25M ; 9.270 ; 9.270 ; Rise ; C25M ; +; SA[0] ; C25M ; 8.917 ; 8.917 ; Rise ; C25M ; +; SA[1] ; C25M ; 8.665 ; 8.665 ; Rise ; C25M ; +; SA[2] ; C25M ; 9.270 ; 9.270 ; Rise ; C25M ; +; SA[3] ; C25M ; 8.223 ; 8.223 ; Rise ; C25M ; +; SA[4] ; C25M ; 8.244 ; 8.244 ; Rise ; C25M ; +; SA[5] ; C25M ; 8.115 ; 8.115 ; Rise ; C25M ; +; SA[6] ; C25M ; 8.104 ; 8.104 ; Rise ; C25M ; +; SA[7] ; C25M ; 8.114 ; 8.114 ; Rise ; C25M ; +; SA[8] ; C25M ; 8.229 ; 8.229 ; Rise ; C25M ; +; SA[9] ; C25M ; 8.975 ; 8.975 ; Rise ; C25M ; +; SA[10] ; C25M ; 6.951 ; 6.951 ; Rise ; C25M ; +; SA[11] ; C25M ; 8.922 ; 8.922 ; Rise ; C25M ; +; SA[12] ; C25M ; 8.773 ; 8.773 ; Rise ; C25M ; +; SBA[*] ; C25M ; 8.182 ; 8.182 ; Rise ; C25M ; +; SBA[0] ; C25M ; 8.182 ; 8.182 ; Rise ; C25M ; +; SBA[1] ; C25M ; 6.923 ; 6.923 ; Rise ; C25M ; +; SD[*] ; C25M ; 9.179 ; 9.179 ; Rise ; C25M ; +; SD[0] ; C25M ; 6.937 ; 6.937 ; Rise ; C25M ; +; SD[1] ; C25M ; 9.179 ; 9.179 ; Rise ; C25M ; +; SD[2] ; C25M ; 7.562 ; 7.562 ; Rise ; C25M ; +; SD[3] ; C25M ; 7.576 ; 7.576 ; Rise ; C25M ; +; SD[4] ; C25M ; 8.135 ; 8.135 ; Rise ; C25M ; +; SD[5] ; C25M ; 6.944 ; 6.944 ; Rise ; C25M ; +; SD[6] ; C25M ; 7.570 ; 7.570 ; Rise ; C25M ; +; SD[7] ; C25M ; 7.556 ; 7.556 ; Rise ; C25M ; +; nCAS ; C25M ; 8.431 ; 8.431 ; Rise ; C25M ; +; nFCS ; C25M ; 8.772 ; 8.772 ; Rise ; C25M ; +; nRAS ; C25M ; 8.114 ; 8.114 ; Rise ; C25M ; +; nRCS ; C25M ; 9.195 ; 9.195 ; Rise ; C25M ; +; nRESout ; C25M ; 8.037 ; 8.037 ; Rise ; C25M ; +; nSWE ; C25M ; 8.335 ; 8.335 ; Rise ; C25M ; +; RDdir ; PHI0 ; 11.354 ; 11.354 ; Rise ; PHI0 ; +; RDdir ; PHI0 ; 11.354 ; 11.354 ; Fall ; PHI0 ; +-----------+------------+--------+--------+------------+-----------------+ @@ -807,55 +805,55 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-----------+------------+--------+--------+------------+-----------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+--------+--------+------------+-----------------+ -; DQMH ; C25M ; 9.374 ; 9.374 ; Rise ; C25M ; -; DQML ; C25M ; 6.924 ; 6.924 ; Rise ; C25M ; -; FCK ; C25M ; 8.081 ; 8.081 ; Rise ; C25M ; -; MOSI ; C25M ; 8.903 ; 8.903 ; Rise ; C25M ; -; RCKE ; C25M ; 9.484 ; 9.484 ; Rise ; C25M ; -; RD[*] ; C25M ; 8.201 ; 8.201 ; Rise ; C25M ; -; RD[0] ; C25M ; 8.346 ; 8.346 ; Rise ; C25M ; -; RD[1] ; C25M ; 8.265 ; 8.265 ; Rise ; C25M ; -; RD[2] ; C25M ; 8.346 ; 8.346 ; Rise ; C25M ; -; RD[3] ; C25M ; 8.201 ; 8.201 ; Rise ; C25M ; -; RD[4] ; C25M ; 9.375 ; 9.375 ; Rise ; C25M ; -; RD[5] ; C25M ; 8.984 ; 8.984 ; Rise ; C25M ; -; RD[6] ; C25M ; 8.913 ; 8.913 ; Rise ; C25M ; -; RD[7] ; C25M ; 9.917 ; 9.917 ; Rise ; C25M ; -; RDdir ; C25M ; 9.501 ; 9.501 ; Rise ; C25M ; -; SA[*] ; C25M ; 7.567 ; 7.567 ; Rise ; C25M ; -; SA[0] ; C25M ; 8.606 ; 8.606 ; Rise ; C25M ; -; SA[1] ; C25M ; 8.584 ; 8.584 ; Rise ; C25M ; -; SA[2] ; C25M ; 8.798 ; 8.798 ; Rise ; C25M ; -; SA[3] ; C25M ; 8.651 ; 8.651 ; Rise ; C25M ; -; SA[4] ; C25M ; 8.242 ; 8.242 ; Rise ; C25M ; -; SA[5] ; C25M ; 8.647 ; 8.647 ; Rise ; C25M ; -; SA[6] ; C25M ; 8.669 ; 8.669 ; Rise ; C25M ; -; SA[7] ; C25M ; 8.116 ; 8.116 ; Rise ; C25M ; -; SA[8] ; C25M ; 8.234 ; 8.234 ; Rise ; C25M ; -; SA[9] ; C25M ; 7.567 ; 7.567 ; Rise ; C25M ; -; SA[10] ; C25M ; 9.394 ; 9.394 ; Rise ; C25M ; -; SA[11] ; C25M ; 8.116 ; 8.116 ; Rise ; C25M ; -; SA[12] ; C25M ; 7.570 ; 7.570 ; Rise ; C25M ; -; SBA[*] ; C25M ; 8.073 ; 8.073 ; Rise ; C25M ; -; SBA[0] ; C25M ; 8.073 ; 8.073 ; Rise ; C25M ; -; SBA[1] ; C25M ; 8.077 ; 8.077 ; Rise ; C25M ; -; SD[*] ; C25M ; 8.097 ; 8.097 ; Rise ; C25M ; -; SD[0] ; C25M ; 8.113 ; 8.113 ; Rise ; C25M ; -; SD[1] ; C25M ; 8.097 ; 8.097 ; Rise ; C25M ; -; SD[2] ; C25M ; 8.574 ; 8.574 ; Rise ; C25M ; -; SD[3] ; C25M ; 8.249 ; 8.249 ; Rise ; C25M ; -; SD[4] ; C25M ; 8.125 ; 8.125 ; Rise ; C25M ; -; SD[5] ; C25M ; 8.113 ; 8.113 ; Rise ; C25M ; -; SD[6] ; C25M ; 8.674 ; 8.674 ; Rise ; C25M ; -; SD[7] ; C25M ; 8.241 ; 8.241 ; Rise ; C25M ; -; nCAS ; C25M ; 8.329 ; 8.329 ; Rise ; C25M ; -; nFCS ; C25M ; 6.964 ; 6.964 ; Rise ; C25M ; -; nRAS ; C25M ; 8.349 ; 8.349 ; Rise ; C25M ; -; nRCS ; C25M ; 9.461 ; 9.461 ; Rise ; C25M ; -; nRESout ; C25M ; 8.159 ; 8.159 ; Rise ; C25M ; -; nSWE ; C25M ; 8.815 ; 8.815 ; Rise ; C25M ; -; RDdir ; PHI0 ; 11.026 ; 11.026 ; Rise ; PHI0 ; -; RDdir ; PHI0 ; 11.026 ; 11.026 ; Fall ; PHI0 ; +; DQMH ; C25M ; 9.305 ; 9.305 ; Rise ; C25M ; +; DQML ; C25M ; 9.483 ; 9.483 ; Rise ; C25M ; +; FCK ; C25M ; 9.008 ; 9.008 ; Rise ; C25M ; +; MOSI ; C25M ; 8.844 ; 8.844 ; Rise ; C25M ; +; RCKE ; C25M ; 9.013 ; 9.013 ; Rise ; C25M ; +; RD[*] ; C25M ; 8.200 ; 8.200 ; Rise ; C25M ; +; RD[0] ; C25M ; 8.456 ; 8.456 ; Rise ; C25M ; +; RD[1] ; C25M ; 8.246 ; 8.246 ; Rise ; C25M ; +; RD[2] ; C25M ; 8.212 ; 8.212 ; Rise ; C25M ; +; RD[3] ; C25M ; 8.920 ; 8.920 ; Rise ; C25M ; +; RD[4] ; C25M ; 8.200 ; 8.200 ; Rise ; C25M ; +; RD[5] ; C25M ; 8.222 ; 8.222 ; Rise ; C25M ; +; RD[6] ; C25M ; 8.841 ; 8.841 ; Rise ; C25M ; +; RD[7] ; C25M ; 9.287 ; 9.287 ; Rise ; C25M ; +; RDdir ; C25M ; 11.009 ; 11.009 ; Rise ; C25M ; +; SA[*] ; C25M ; 6.951 ; 6.951 ; Rise ; C25M ; +; SA[0] ; C25M ; 8.917 ; 8.917 ; Rise ; C25M ; +; SA[1] ; C25M ; 8.665 ; 8.665 ; Rise ; C25M ; +; SA[2] ; C25M ; 9.270 ; 9.270 ; Rise ; C25M ; +; SA[3] ; C25M ; 8.223 ; 8.223 ; Rise ; C25M ; +; SA[4] ; C25M ; 8.244 ; 8.244 ; Rise ; C25M ; +; SA[5] ; C25M ; 8.115 ; 8.115 ; Rise ; C25M ; +; SA[6] ; C25M ; 8.104 ; 8.104 ; Rise ; C25M ; +; SA[7] ; C25M ; 8.114 ; 8.114 ; Rise ; C25M ; +; SA[8] ; C25M ; 8.229 ; 8.229 ; Rise ; C25M ; +; SA[9] ; C25M ; 8.975 ; 8.975 ; Rise ; C25M ; +; SA[10] ; C25M ; 6.951 ; 6.951 ; Rise ; C25M ; +; SA[11] ; C25M ; 8.922 ; 8.922 ; Rise ; C25M ; +; SA[12] ; C25M ; 8.773 ; 8.773 ; Rise ; C25M ; +; SBA[*] ; C25M ; 6.923 ; 6.923 ; Rise ; C25M ; +; SBA[0] ; C25M ; 8.182 ; 8.182 ; Rise ; C25M ; +; SBA[1] ; C25M ; 6.923 ; 6.923 ; Rise ; C25M ; +; SD[*] ; C25M ; 6.937 ; 6.937 ; Rise ; C25M ; +; SD[0] ; C25M ; 6.937 ; 6.937 ; Rise ; C25M ; +; SD[1] ; C25M ; 9.179 ; 9.179 ; Rise ; C25M ; +; SD[2] ; C25M ; 7.562 ; 7.562 ; Rise ; C25M ; +; SD[3] ; C25M ; 7.576 ; 7.576 ; Rise ; C25M ; +; SD[4] ; C25M ; 8.135 ; 8.135 ; Rise ; C25M ; +; SD[5] ; C25M ; 6.944 ; 6.944 ; Rise ; C25M ; +; SD[6] ; C25M ; 7.570 ; 7.570 ; Rise ; C25M ; +; SD[7] ; C25M ; 7.556 ; 7.556 ; Rise ; C25M ; +; nCAS ; C25M ; 8.431 ; 8.431 ; Rise ; C25M ; +; nFCS ; C25M ; 8.772 ; 8.772 ; Rise ; C25M ; +; nRAS ; C25M ; 8.114 ; 8.114 ; Rise ; C25M ; +; nRCS ; C25M ; 9.195 ; 9.195 ; Rise ; C25M ; +; nRESout ; C25M ; 8.037 ; 8.037 ; Rise ; C25M ; +; nSWE ; C25M ; 8.335 ; 8.335 ; Rise ; C25M ; +; RDdir ; PHI0 ; 11.354 ; 11.354 ; Rise ; PHI0 ; +; RDdir ; PHI0 ; 11.354 ; 11.354 ; Fall ; PHI0 ; +-----------+------------+--------+--------+------------+-----------------+ @@ -864,44 +862,44 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +------------+-------------+--------+----+----+--------+ ; Input Port ; Output Port ; RR ; RF ; FR ; FF ; +------------+-------------+--------+----+----+--------+ -; DMAin ; DMAout ; 8.656 ; ; ; 8.656 ; -; INTin ; INTout ; 8.937 ; ; ; 8.937 ; -; nDEVSEL ; RD[0] ; 14.969 ; ; ; 14.969 ; -; nDEVSEL ; RD[1] ; 14.969 ; ; ; 14.969 ; -; nDEVSEL ; RD[2] ; 14.969 ; ; ; 14.969 ; -; nDEVSEL ; RD[3] ; 14.969 ; ; ; 14.969 ; -; nDEVSEL ; RD[4] ; 14.969 ; ; ; 14.969 ; -; nDEVSEL ; RD[5] ; 14.969 ; ; ; 14.969 ; -; nDEVSEL ; RD[6] ; 14.980 ; ; ; 14.980 ; -; nDEVSEL ; RD[7] ; 14.980 ; ; ; 14.980 ; -; nDEVSEL ; RDdir ; 16.482 ; ; ; 16.482 ; -; nIOSEL ; RD[0] ; 14.415 ; ; ; 14.415 ; -; nIOSEL ; RD[1] ; 14.415 ; ; ; 14.415 ; -; nIOSEL ; RD[2] ; 14.415 ; ; ; 14.415 ; -; nIOSEL ; RD[3] ; 14.415 ; ; ; 14.415 ; -; nIOSEL ; RD[4] ; 14.415 ; ; ; 14.415 ; -; nIOSEL ; RD[5] ; 14.415 ; ; ; 14.415 ; -; nIOSEL ; RD[6] ; 14.426 ; ; ; 14.426 ; -; nIOSEL ; RD[7] ; 14.426 ; ; ; 14.426 ; -; nIOSEL ; RDdir ; 15.928 ; ; ; 15.928 ; -; nIOSTRB ; RD[0] ; 13.935 ; ; ; 13.935 ; -; nIOSTRB ; RD[1] ; 13.935 ; ; ; 13.935 ; -; nIOSTRB ; RD[2] ; 13.935 ; ; ; 13.935 ; -; nIOSTRB ; RD[3] ; 13.935 ; ; ; 13.935 ; -; nIOSTRB ; RD[4] ; 13.935 ; ; ; 13.935 ; -; nIOSTRB ; RD[5] ; 13.935 ; ; ; 13.935 ; -; nIOSTRB ; RD[6] ; 13.946 ; ; ; 13.946 ; -; nIOSTRB ; RD[7] ; 13.946 ; ; ; 13.946 ; -; nIOSTRB ; RDdir ; 15.448 ; ; ; 15.448 ; -; nWE ; RD[0] ; 9.870 ; ; ; 9.870 ; -; nWE ; RD[1] ; 9.870 ; ; ; 9.870 ; -; nWE ; RD[2] ; 9.870 ; ; ; 9.870 ; -; nWE ; RD[3] ; 9.870 ; ; ; 9.870 ; -; nWE ; RD[4] ; 9.870 ; ; ; 9.870 ; -; nWE ; RD[5] ; 9.870 ; ; ; 9.870 ; -; nWE ; RD[6] ; 9.881 ; ; ; 9.881 ; -; nWE ; RD[7] ; 9.881 ; ; ; 9.881 ; -; nWE ; RDdir ; 11.383 ; ; ; 11.383 ; +; DMAin ; DMAout ; 8.420 ; ; ; 8.420 ; +; INTin ; INTout ; 8.852 ; ; ; 8.852 ; +; nDEVSEL ; RD[0] ; 13.908 ; ; ; 13.908 ; +; nDEVSEL ; RD[1] ; 13.908 ; ; ; 13.908 ; +; nDEVSEL ; RD[2] ; 13.908 ; ; ; 13.908 ; +; nDEVSEL ; RD[3] ; 13.908 ; ; ; 13.908 ; +; nDEVSEL ; RD[4] ; 13.908 ; ; ; 13.908 ; +; nDEVSEL ; RD[5] ; 13.908 ; ; ; 13.908 ; +; nDEVSEL ; RD[6] ; 13.954 ; ; ; 13.954 ; +; nDEVSEL ; RD[7] ; 13.954 ; ; ; 13.954 ; +; nDEVSEL ; RDdir ; 15.512 ; ; ; 15.512 ; +; nIOSEL ; RD[0] ; 13.721 ; ; ; 13.721 ; +; nIOSEL ; RD[1] ; 13.721 ; ; ; 13.721 ; +; nIOSEL ; RD[2] ; 13.721 ; ; ; 13.721 ; +; nIOSEL ; RD[3] ; 13.721 ; ; ; 13.721 ; +; nIOSEL ; RD[4] ; 13.721 ; ; ; 13.721 ; +; nIOSEL ; RD[5] ; 13.721 ; ; ; 13.721 ; +; nIOSEL ; RD[6] ; 13.767 ; ; ; 13.767 ; +; nIOSEL ; RD[7] ; 13.767 ; ; ; 13.767 ; +; nIOSEL ; RDdir ; 15.325 ; ; ; 15.325 ; +; nIOSTRB ; RD[0] ; 13.574 ; ; ; 13.574 ; +; nIOSTRB ; RD[1] ; 13.574 ; ; ; 13.574 ; +; nIOSTRB ; RD[2] ; 13.574 ; ; ; 13.574 ; +; nIOSTRB ; RD[3] ; 13.574 ; ; ; 13.574 ; +; nIOSTRB ; RD[4] ; 13.574 ; ; ; 13.574 ; +; nIOSTRB ; RD[5] ; 13.574 ; ; ; 13.574 ; +; nIOSTRB ; RD[6] ; 13.620 ; ; ; 13.620 ; +; nIOSTRB ; RD[7] ; 13.620 ; ; ; 13.620 ; +; nIOSTRB ; RDdir ; 15.178 ; ; ; 15.178 ; +; nWE ; RD[0] ; 10.209 ; ; ; 10.209 ; +; nWE ; RD[1] ; 10.209 ; ; ; 10.209 ; +; nWE ; RD[2] ; 10.209 ; ; ; 10.209 ; +; nWE ; RD[3] ; 10.209 ; ; ; 10.209 ; +; nWE ; RD[4] ; 10.209 ; ; ; 10.209 ; +; nWE ; RD[5] ; 10.209 ; ; ; 10.209 ; +; nWE ; RD[6] ; 10.255 ; ; ; 10.255 ; +; nWE ; RD[7] ; 10.255 ; ; ; 10.255 ; +; nWE ; RDdir ; 11.813 ; ; ; 11.813 ; +------------+-------------+--------+----+----+--------+ @@ -910,44 +908,44 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +------------+-------------+--------+----+----+--------+ ; Input Port ; Output Port ; RR ; RF ; FR ; FF ; +------------+-------------+--------+----+----+--------+ -; DMAin ; DMAout ; 8.656 ; ; ; 8.656 ; -; INTin ; INTout ; 8.937 ; ; ; 8.937 ; -; nDEVSEL ; RD[0] ; 14.969 ; ; ; 14.969 ; -; nDEVSEL ; RD[1] ; 14.969 ; ; ; 14.969 ; -; nDEVSEL ; RD[2] ; 14.969 ; ; ; 14.969 ; -; nDEVSEL ; RD[3] ; 14.969 ; ; ; 14.969 ; -; nDEVSEL ; RD[4] ; 14.969 ; ; ; 14.969 ; -; nDEVSEL ; RD[5] ; 14.969 ; ; ; 14.969 ; -; nDEVSEL ; RD[6] ; 14.980 ; ; ; 14.980 ; -; nDEVSEL ; RD[7] ; 14.980 ; ; ; 14.980 ; -; nDEVSEL ; RDdir ; 16.482 ; ; ; 16.482 ; -; nIOSEL ; RD[0] ; 14.415 ; ; ; 14.415 ; -; nIOSEL ; RD[1] ; 14.415 ; ; ; 14.415 ; -; nIOSEL ; RD[2] ; 14.415 ; ; ; 14.415 ; -; nIOSEL ; RD[3] ; 14.415 ; ; ; 14.415 ; -; nIOSEL ; RD[4] ; 14.415 ; ; ; 14.415 ; -; nIOSEL ; RD[5] ; 14.415 ; ; ; 14.415 ; -; nIOSEL ; RD[6] ; 14.426 ; ; ; 14.426 ; -; nIOSEL ; RD[7] ; 14.426 ; ; ; 14.426 ; -; nIOSEL ; RDdir ; 15.928 ; ; ; 15.928 ; -; nIOSTRB ; RD[0] ; 13.935 ; ; ; 13.935 ; -; nIOSTRB ; RD[1] ; 13.935 ; ; ; 13.935 ; -; nIOSTRB ; RD[2] ; 13.935 ; ; ; 13.935 ; -; nIOSTRB ; RD[3] ; 13.935 ; ; ; 13.935 ; -; nIOSTRB ; RD[4] ; 13.935 ; ; ; 13.935 ; -; nIOSTRB ; RD[5] ; 13.935 ; ; ; 13.935 ; -; nIOSTRB ; RD[6] ; 13.946 ; ; ; 13.946 ; -; nIOSTRB ; RD[7] ; 13.946 ; ; ; 13.946 ; -; nIOSTRB ; RDdir ; 15.448 ; ; ; 15.448 ; -; nWE ; RD[0] ; 9.870 ; ; ; 9.870 ; -; nWE ; RD[1] ; 9.870 ; ; ; 9.870 ; -; nWE ; RD[2] ; 9.870 ; ; ; 9.870 ; -; nWE ; RD[3] ; 9.870 ; ; ; 9.870 ; -; nWE ; RD[4] ; 9.870 ; ; ; 9.870 ; -; nWE ; RD[5] ; 9.870 ; ; ; 9.870 ; -; nWE ; RD[6] ; 9.881 ; ; ; 9.881 ; -; nWE ; RD[7] ; 9.881 ; ; ; 9.881 ; -; nWE ; RDdir ; 11.383 ; ; ; 11.383 ; +; DMAin ; DMAout ; 8.420 ; ; ; 8.420 ; +; INTin ; INTout ; 8.852 ; ; ; 8.852 ; +; nDEVSEL ; RD[0] ; 13.908 ; ; ; 13.908 ; +; nDEVSEL ; RD[1] ; 13.908 ; ; ; 13.908 ; +; nDEVSEL ; RD[2] ; 13.908 ; ; ; 13.908 ; +; nDEVSEL ; RD[3] ; 13.908 ; ; ; 13.908 ; +; nDEVSEL ; RD[4] ; 13.908 ; ; ; 13.908 ; +; nDEVSEL ; RD[5] ; 13.908 ; ; ; 13.908 ; +; nDEVSEL ; RD[6] ; 13.954 ; ; ; 13.954 ; +; nDEVSEL ; RD[7] ; 13.954 ; ; ; 13.954 ; +; nDEVSEL ; RDdir ; 15.512 ; ; ; 15.512 ; +; nIOSEL ; RD[0] ; 13.721 ; ; ; 13.721 ; +; nIOSEL ; RD[1] ; 13.721 ; ; ; 13.721 ; +; nIOSEL ; RD[2] ; 13.721 ; ; ; 13.721 ; +; nIOSEL ; RD[3] ; 13.721 ; ; ; 13.721 ; +; nIOSEL ; RD[4] ; 13.721 ; ; ; 13.721 ; +; nIOSEL ; RD[5] ; 13.721 ; ; ; 13.721 ; +; nIOSEL ; RD[6] ; 13.767 ; ; ; 13.767 ; +; nIOSEL ; RD[7] ; 13.767 ; ; ; 13.767 ; +; nIOSEL ; RDdir ; 15.325 ; ; ; 15.325 ; +; nIOSTRB ; RD[0] ; 13.574 ; ; ; 13.574 ; +; nIOSTRB ; RD[1] ; 13.574 ; ; ; 13.574 ; +; nIOSTRB ; RD[2] ; 13.574 ; ; ; 13.574 ; +; nIOSTRB ; RD[3] ; 13.574 ; ; ; 13.574 ; +; nIOSTRB ; RD[4] ; 13.574 ; ; ; 13.574 ; +; nIOSTRB ; RD[5] ; 13.574 ; ; ; 13.574 ; +; nIOSTRB ; RD[6] ; 13.620 ; ; ; 13.620 ; +; nIOSTRB ; RD[7] ; 13.620 ; ; ; 13.620 ; +; nIOSTRB ; RDdir ; 15.178 ; ; ; 15.178 ; +; nWE ; RD[0] ; 10.209 ; ; ; 10.209 ; +; nWE ; RD[1] ; 10.209 ; ; ; 10.209 ; +; nWE ; RD[2] ; 10.209 ; ; ; 10.209 ; +; nWE ; RD[3] ; 10.209 ; ; ; 10.209 ; +; nWE ; RD[4] ; 10.209 ; ; ; 10.209 ; +; nWE ; RD[5] ; 10.209 ; ; ; 10.209 ; +; nWE ; RD[6] ; 10.255 ; ; ; 10.255 ; +; nWE ; RD[7] ; 10.255 ; ; ; 10.255 ; +; nWE ; RDdir ; 11.813 ; ; ; 11.813 ; +------------+-------------+--------+----+----+--------+ @@ -956,45 +954,45 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-----------+------------+--------+------+------------+-----------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+--------+------+------------+-----------------+ -; FCK ; C25M ; 8.571 ; ; Rise ; C25M ; -; MOSI ; C25M ; 7.845 ; ; Rise ; C25M ; -; RD[*] ; C25M ; 15.116 ; ; Rise ; C25M ; -; RD[0] ; C25M ; 15.116 ; ; Rise ; C25M ; -; RD[1] ; C25M ; 15.116 ; ; Rise ; C25M ; -; RD[2] ; C25M ; 15.116 ; ; Rise ; C25M ; -; RD[3] ; C25M ; 15.116 ; ; Rise ; C25M ; -; RD[4] ; C25M ; 15.116 ; ; Rise ; C25M ; -; RD[5] ; C25M ; 15.116 ; ; Rise ; C25M ; -; RD[6] ; C25M ; 15.127 ; ; Rise ; C25M ; -; RD[7] ; C25M ; 15.127 ; ; Rise ; C25M ; -; SD[*] ; C25M ; 6.442 ; ; Rise ; C25M ; -; SD[0] ; C25M ; 6.935 ; ; Rise ; C25M ; -; SD[1] ; C25M ; 6.935 ; ; Rise ; C25M ; -; SD[2] ; C25M ; 6.442 ; ; Rise ; C25M ; -; SD[3] ; C25M ; 6.442 ; ; Rise ; C25M ; -; SD[4] ; C25M ; 6.935 ; ; Rise ; C25M ; -; SD[5] ; C25M ; 6.442 ; ; Rise ; C25M ; -; SD[6] ; C25M ; 6.442 ; ; Rise ; C25M ; -; SD[7] ; C25M ; 6.442 ; ; Rise ; C25M ; -; nFCS ; C25M ; 7.793 ; ; Rise ; C25M ; -; RD[*] ; PHI0 ; 9.513 ; ; Rise ; PHI0 ; -; RD[0] ; PHI0 ; 9.513 ; ; Rise ; PHI0 ; -; RD[1] ; PHI0 ; 9.513 ; ; Rise ; PHI0 ; -; RD[2] ; PHI0 ; 9.513 ; ; Rise ; PHI0 ; -; RD[3] ; PHI0 ; 9.513 ; ; Rise ; PHI0 ; -; RD[4] ; PHI0 ; 9.513 ; ; Rise ; PHI0 ; -; RD[5] ; PHI0 ; 9.513 ; ; Rise ; PHI0 ; -; RD[6] ; PHI0 ; 9.524 ; ; Rise ; PHI0 ; -; RD[7] ; PHI0 ; 9.524 ; ; Rise ; PHI0 ; -; RD[*] ; PHI0 ; 9.513 ; ; Fall ; PHI0 ; -; RD[0] ; PHI0 ; 9.513 ; ; Fall ; PHI0 ; -; RD[1] ; PHI0 ; 9.513 ; ; Fall ; PHI0 ; -; RD[2] ; PHI0 ; 9.513 ; ; Fall ; PHI0 ; -; RD[3] ; PHI0 ; 9.513 ; ; Fall ; PHI0 ; -; RD[4] ; PHI0 ; 9.513 ; ; Fall ; PHI0 ; -; RD[5] ; PHI0 ; 9.513 ; ; Fall ; PHI0 ; -; RD[6] ; PHI0 ; 9.524 ; ; Fall ; PHI0 ; -; RD[7] ; PHI0 ; 9.524 ; ; Fall ; PHI0 ; +; FCK ; C25M ; 7.909 ; ; Rise ; C25M ; +; MOSI ; C25M ; 8.455 ; ; Rise ; C25M ; +; RD[*] ; C25M ; 12.243 ; ; Rise ; C25M ; +; RD[0] ; C25M ; 12.243 ; ; Rise ; C25M ; +; RD[1] ; C25M ; 12.243 ; ; Rise ; C25M ; +; RD[2] ; C25M ; 12.243 ; ; Rise ; C25M ; +; RD[3] ; C25M ; 12.243 ; ; Rise ; C25M ; +; RD[4] ; C25M ; 12.243 ; ; Rise ; C25M ; +; RD[5] ; C25M ; 12.243 ; ; Rise ; C25M ; +; RD[6] ; C25M ; 12.289 ; ; Rise ; C25M ; +; RD[7] ; C25M ; 12.289 ; ; Rise ; C25M ; +; SD[*] ; C25M ; 7.014 ; ; Rise ; C25M ; +; SD[0] ; C25M ; 7.446 ; ; Rise ; C25M ; +; SD[1] ; C25M ; 7.446 ; ; Rise ; C25M ; +; SD[2] ; C25M ; 7.014 ; ; Rise ; C25M ; +; SD[3] ; C25M ; 7.014 ; ; Rise ; C25M ; +; SD[4] ; C25M ; 7.446 ; ; Rise ; C25M ; +; SD[5] ; C25M ; 7.014 ; ; Rise ; C25M ; +; SD[6] ; C25M ; 7.014 ; ; Rise ; C25M ; +; SD[7] ; C25M ; 7.014 ; ; Rise ; C25M ; +; nFCS ; C25M ; 7.116 ; ; Rise ; C25M ; +; RD[*] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; +; RD[0] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; +; RD[1] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; +; RD[2] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; +; RD[3] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; +; RD[4] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; +; RD[5] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; +; RD[6] ; PHI0 ; 9.796 ; ; Rise ; PHI0 ; +; RD[7] ; PHI0 ; 9.796 ; ; Rise ; PHI0 ; +; RD[*] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; +; RD[0] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; +; RD[1] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; +; RD[2] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; +; RD[3] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; +; RD[4] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; +; RD[5] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; +; RD[6] ; PHI0 ; 9.796 ; ; Fall ; PHI0 ; +; RD[7] ; PHI0 ; 9.796 ; ; Fall ; PHI0 ; +-----------+------------+--------+------+------------+-----------------+ @@ -1003,45 +1001,45 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-----------+------------+-------+------+------------+-----------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+-------+------+------------+-----------------+ -; FCK ; C25M ; 8.571 ; ; Rise ; C25M ; -; MOSI ; C25M ; 7.845 ; ; Rise ; C25M ; -; RD[*] ; C25M ; 7.988 ; ; Rise ; C25M ; -; RD[0] ; C25M ; 7.988 ; ; Rise ; C25M ; -; RD[1] ; C25M ; 7.988 ; ; Rise ; C25M ; -; RD[2] ; C25M ; 7.988 ; ; Rise ; C25M ; -; RD[3] ; C25M ; 7.988 ; ; Rise ; C25M ; -; RD[4] ; C25M ; 7.988 ; ; Rise ; C25M ; -; RD[5] ; C25M ; 7.988 ; ; Rise ; C25M ; -; RD[6] ; C25M ; 7.999 ; ; Rise ; C25M ; -; RD[7] ; C25M ; 7.999 ; ; Rise ; C25M ; -; SD[*] ; C25M ; 6.442 ; ; Rise ; C25M ; -; SD[0] ; C25M ; 6.935 ; ; Rise ; C25M ; -; SD[1] ; C25M ; 6.935 ; ; Rise ; C25M ; -; SD[2] ; C25M ; 6.442 ; ; Rise ; C25M ; -; SD[3] ; C25M ; 6.442 ; ; Rise ; C25M ; -; SD[4] ; C25M ; 6.935 ; ; Rise ; C25M ; -; SD[5] ; C25M ; 6.442 ; ; Rise ; C25M ; -; SD[6] ; C25M ; 6.442 ; ; Rise ; C25M ; -; SD[7] ; C25M ; 6.442 ; ; Rise ; C25M ; -; nFCS ; C25M ; 7.793 ; ; Rise ; C25M ; -; RD[*] ; PHI0 ; 9.513 ; ; Rise ; PHI0 ; -; RD[0] ; PHI0 ; 9.513 ; ; Rise ; PHI0 ; -; RD[1] ; PHI0 ; 9.513 ; ; Rise ; PHI0 ; -; RD[2] ; PHI0 ; 9.513 ; ; Rise ; PHI0 ; -; RD[3] ; PHI0 ; 9.513 ; ; Rise ; PHI0 ; -; RD[4] ; PHI0 ; 9.513 ; ; Rise ; PHI0 ; -; RD[5] ; PHI0 ; 9.513 ; ; Rise ; PHI0 ; -; RD[6] ; PHI0 ; 9.524 ; ; Rise ; PHI0 ; -; RD[7] ; PHI0 ; 9.524 ; ; Rise ; PHI0 ; -; RD[*] ; PHI0 ; 9.513 ; ; Fall ; PHI0 ; -; RD[0] ; PHI0 ; 9.513 ; ; Fall ; PHI0 ; -; RD[1] ; PHI0 ; 9.513 ; ; Fall ; PHI0 ; -; RD[2] ; PHI0 ; 9.513 ; ; Fall ; PHI0 ; -; RD[3] ; PHI0 ; 9.513 ; ; Fall ; PHI0 ; -; RD[4] ; PHI0 ; 9.513 ; ; Fall ; PHI0 ; -; RD[5] ; PHI0 ; 9.513 ; ; Fall ; PHI0 ; -; RD[6] ; PHI0 ; 9.524 ; ; Fall ; PHI0 ; -; RD[7] ; PHI0 ; 9.524 ; ; Fall ; PHI0 ; +; FCK ; C25M ; 7.909 ; ; Rise ; C25M ; +; MOSI ; C25M ; 8.455 ; ; Rise ; C25M ; +; RD[*] ; C25M ; 9.405 ; ; Rise ; C25M ; +; RD[0] ; C25M ; 9.405 ; ; Rise ; C25M ; +; RD[1] ; C25M ; 9.405 ; ; Rise ; C25M ; +; RD[2] ; C25M ; 9.405 ; ; Rise ; C25M ; +; RD[3] ; C25M ; 9.405 ; ; Rise ; C25M ; +; RD[4] ; C25M ; 9.405 ; ; Rise ; C25M ; +; RD[5] ; C25M ; 9.405 ; ; Rise ; C25M ; +; RD[6] ; C25M ; 9.451 ; ; Rise ; C25M ; +; RD[7] ; C25M ; 9.451 ; ; Rise ; C25M ; +; SD[*] ; C25M ; 7.014 ; ; Rise ; C25M ; +; SD[0] ; C25M ; 7.446 ; ; Rise ; C25M ; +; SD[1] ; C25M ; 7.446 ; ; Rise ; C25M ; +; SD[2] ; C25M ; 7.014 ; ; Rise ; C25M ; +; SD[3] ; C25M ; 7.014 ; ; Rise ; C25M ; +; SD[4] ; C25M ; 7.446 ; ; Rise ; C25M ; +; SD[5] ; C25M ; 7.014 ; ; Rise ; C25M ; +; SD[6] ; C25M ; 7.014 ; ; Rise ; C25M ; +; SD[7] ; C25M ; 7.014 ; ; Rise ; C25M ; +; nFCS ; C25M ; 7.116 ; ; Rise ; C25M ; +; RD[*] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; +; RD[0] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; +; RD[1] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; +; RD[2] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; +; RD[3] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; +; RD[4] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; +; RD[5] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; +; RD[6] ; PHI0 ; 9.796 ; ; Rise ; PHI0 ; +; RD[7] ; PHI0 ; 9.796 ; ; Rise ; PHI0 ; +; RD[*] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; +; RD[0] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; +; RD[1] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; +; RD[2] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; +; RD[3] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; +; RD[4] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; +; RD[5] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; +; RD[6] ; PHI0 ; 9.796 ; ; Fall ; PHI0 ; +; RD[7] ; PHI0 ; 9.796 ; ; Fall ; PHI0 ; +-----------+------------+-------+------+------------+-----------------+ @@ -1050,45 +1048,45 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-----------+------------+-----------+-----------+------------+-----------------+ ; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; +-----------+------------+-----------+-----------+------------+-----------------+ -; FCK ; C25M ; 8.571 ; ; Rise ; C25M ; -; MOSI ; C25M ; 7.845 ; ; Rise ; C25M ; -; RD[*] ; C25M ; 15.116 ; ; Rise ; C25M ; -; RD[0] ; C25M ; 15.116 ; ; Rise ; C25M ; -; RD[1] ; C25M ; 15.116 ; ; Rise ; C25M ; -; RD[2] ; C25M ; 15.116 ; ; Rise ; C25M ; -; RD[3] ; C25M ; 15.116 ; ; Rise ; C25M ; -; RD[4] ; C25M ; 15.116 ; ; Rise ; C25M ; -; RD[5] ; C25M ; 15.116 ; ; Rise ; C25M ; -; RD[6] ; C25M ; 15.127 ; ; Rise ; C25M ; -; RD[7] ; C25M ; 15.127 ; ; Rise ; C25M ; -; SD[*] ; C25M ; 6.442 ; ; Rise ; C25M ; -; SD[0] ; C25M ; 6.935 ; ; Rise ; C25M ; -; SD[1] ; C25M ; 6.935 ; ; Rise ; C25M ; -; SD[2] ; C25M ; 6.442 ; ; Rise ; C25M ; -; SD[3] ; C25M ; 6.442 ; ; Rise ; C25M ; -; SD[4] ; C25M ; 6.935 ; ; Rise ; C25M ; -; SD[5] ; C25M ; 6.442 ; ; Rise ; C25M ; -; SD[6] ; C25M ; 6.442 ; ; Rise ; C25M ; -; SD[7] ; C25M ; 6.442 ; ; Rise ; C25M ; -; nFCS ; C25M ; 7.793 ; ; Rise ; C25M ; -; RD[*] ; PHI0 ; 9.513 ; ; Rise ; PHI0 ; -; RD[0] ; PHI0 ; 9.513 ; ; Rise ; PHI0 ; -; RD[1] ; PHI0 ; 9.513 ; ; Rise ; PHI0 ; -; RD[2] ; PHI0 ; 9.513 ; ; Rise ; PHI0 ; -; RD[3] ; PHI0 ; 9.513 ; ; Rise ; PHI0 ; -; RD[4] ; PHI0 ; 9.513 ; ; Rise ; PHI0 ; -; RD[5] ; PHI0 ; 9.513 ; ; Rise ; PHI0 ; -; RD[6] ; PHI0 ; 9.524 ; ; Rise ; PHI0 ; -; RD[7] ; PHI0 ; 9.524 ; ; Rise ; PHI0 ; -; RD[*] ; PHI0 ; 9.513 ; ; Fall ; PHI0 ; -; RD[0] ; PHI0 ; 9.513 ; ; Fall ; PHI0 ; -; RD[1] ; PHI0 ; 9.513 ; ; Fall ; PHI0 ; -; RD[2] ; PHI0 ; 9.513 ; ; Fall ; PHI0 ; -; RD[3] ; PHI0 ; 9.513 ; ; Fall ; PHI0 ; -; RD[4] ; PHI0 ; 9.513 ; ; Fall ; PHI0 ; -; RD[5] ; PHI0 ; 9.513 ; ; Fall ; PHI0 ; -; RD[6] ; PHI0 ; 9.524 ; ; Fall ; PHI0 ; -; RD[7] ; PHI0 ; 9.524 ; ; Fall ; PHI0 ; +; FCK ; C25M ; 7.909 ; ; Rise ; C25M ; +; MOSI ; C25M ; 8.455 ; ; Rise ; C25M ; +; RD[*] ; C25M ; 12.243 ; ; Rise ; C25M ; +; RD[0] ; C25M ; 12.243 ; ; Rise ; C25M ; +; RD[1] ; C25M ; 12.243 ; ; Rise ; C25M ; +; RD[2] ; C25M ; 12.243 ; ; Rise ; C25M ; +; RD[3] ; C25M ; 12.243 ; ; Rise ; C25M ; +; RD[4] ; C25M ; 12.243 ; ; Rise ; C25M ; +; RD[5] ; C25M ; 12.243 ; ; Rise ; C25M ; +; RD[6] ; C25M ; 12.289 ; ; Rise ; C25M ; +; RD[7] ; C25M ; 12.289 ; ; Rise ; C25M ; +; SD[*] ; C25M ; 7.014 ; ; Rise ; C25M ; +; SD[0] ; C25M ; 7.446 ; ; Rise ; C25M ; +; SD[1] ; C25M ; 7.446 ; ; Rise ; C25M ; +; SD[2] ; C25M ; 7.014 ; ; Rise ; C25M ; +; SD[3] ; C25M ; 7.014 ; ; Rise ; C25M ; +; SD[4] ; C25M ; 7.446 ; ; Rise ; C25M ; +; SD[5] ; C25M ; 7.014 ; ; Rise ; C25M ; +; SD[6] ; C25M ; 7.014 ; ; Rise ; C25M ; +; SD[7] ; C25M ; 7.014 ; ; Rise ; C25M ; +; nFCS ; C25M ; 7.116 ; ; Rise ; C25M ; +; RD[*] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; +; RD[0] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; +; RD[1] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; +; RD[2] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; +; RD[3] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; +; RD[4] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; +; RD[5] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; +; RD[6] ; PHI0 ; 9.796 ; ; Rise ; PHI0 ; +; RD[7] ; PHI0 ; 9.796 ; ; Rise ; PHI0 ; +; RD[*] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; +; RD[0] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; +; RD[1] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; +; RD[2] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; +; RD[3] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; +; RD[4] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; +; RD[5] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; +; RD[6] ; PHI0 ; 9.796 ; ; Fall ; PHI0 ; +; RD[7] ; PHI0 ; 9.796 ; ; Fall ; PHI0 ; +-----------+------------+-----------+-----------+------------+-----------------+ @@ -1097,45 +1095,45 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-----------+------------+-----------+-----------+------------+-----------------+ ; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; +-----------+------------+-----------+-----------+------------+-----------------+ -; FCK ; C25M ; 8.571 ; ; Rise ; C25M ; -; MOSI ; C25M ; 7.845 ; ; Rise ; C25M ; -; RD[*] ; C25M ; 7.988 ; ; Rise ; C25M ; -; RD[0] ; C25M ; 7.988 ; ; Rise ; C25M ; -; RD[1] ; C25M ; 7.988 ; ; Rise ; C25M ; -; RD[2] ; C25M ; 7.988 ; ; Rise ; C25M ; -; RD[3] ; C25M ; 7.988 ; ; Rise ; C25M ; -; RD[4] ; C25M ; 7.988 ; ; Rise ; C25M ; -; RD[5] ; C25M ; 7.988 ; ; Rise ; C25M ; -; RD[6] ; C25M ; 7.999 ; ; Rise ; C25M ; -; RD[7] ; C25M ; 7.999 ; ; Rise ; C25M ; -; SD[*] ; C25M ; 6.442 ; ; Rise ; C25M ; -; SD[0] ; C25M ; 6.935 ; ; Rise ; C25M ; -; SD[1] ; C25M ; 6.935 ; ; Rise ; C25M ; -; SD[2] ; C25M ; 6.442 ; ; Rise ; C25M ; -; SD[3] ; C25M ; 6.442 ; ; Rise ; C25M ; -; SD[4] ; C25M ; 6.935 ; ; Rise ; C25M ; -; SD[5] ; C25M ; 6.442 ; ; Rise ; C25M ; -; SD[6] ; C25M ; 6.442 ; ; Rise ; C25M ; -; SD[7] ; C25M ; 6.442 ; ; Rise ; C25M ; -; nFCS ; C25M ; 7.793 ; ; Rise ; C25M ; -; RD[*] ; PHI0 ; 9.513 ; ; Rise ; PHI0 ; -; RD[0] ; PHI0 ; 9.513 ; ; Rise ; PHI0 ; -; RD[1] ; PHI0 ; 9.513 ; ; Rise ; PHI0 ; -; RD[2] ; PHI0 ; 9.513 ; ; Rise ; PHI0 ; -; RD[3] ; PHI0 ; 9.513 ; ; Rise ; PHI0 ; -; RD[4] ; PHI0 ; 9.513 ; ; Rise ; PHI0 ; -; RD[5] ; PHI0 ; 9.513 ; ; Rise ; PHI0 ; -; RD[6] ; PHI0 ; 9.524 ; ; Rise ; PHI0 ; -; RD[7] ; PHI0 ; 9.524 ; ; Rise ; PHI0 ; -; RD[*] ; PHI0 ; 9.513 ; ; Fall ; PHI0 ; -; RD[0] ; PHI0 ; 9.513 ; ; Fall ; PHI0 ; -; RD[1] ; PHI0 ; 9.513 ; ; Fall ; PHI0 ; -; RD[2] ; PHI0 ; 9.513 ; ; Fall ; PHI0 ; -; RD[3] ; PHI0 ; 9.513 ; ; Fall ; PHI0 ; -; RD[4] ; PHI0 ; 9.513 ; ; Fall ; PHI0 ; -; RD[5] ; PHI0 ; 9.513 ; ; Fall ; PHI0 ; -; RD[6] ; PHI0 ; 9.524 ; ; Fall ; PHI0 ; -; RD[7] ; PHI0 ; 9.524 ; ; Fall ; PHI0 ; +; FCK ; C25M ; 7.909 ; ; Rise ; C25M ; +; MOSI ; C25M ; 8.455 ; ; Rise ; C25M ; +; RD[*] ; C25M ; 9.405 ; ; Rise ; C25M ; +; RD[0] ; C25M ; 9.405 ; ; Rise ; C25M ; +; RD[1] ; C25M ; 9.405 ; ; Rise ; C25M ; +; RD[2] ; C25M ; 9.405 ; ; Rise ; C25M ; +; RD[3] ; C25M ; 9.405 ; ; Rise ; C25M ; +; RD[4] ; C25M ; 9.405 ; ; Rise ; C25M ; +; RD[5] ; C25M ; 9.405 ; ; Rise ; C25M ; +; RD[6] ; C25M ; 9.451 ; ; Rise ; C25M ; +; RD[7] ; C25M ; 9.451 ; ; Rise ; C25M ; +; SD[*] ; C25M ; 7.014 ; ; Rise ; C25M ; +; SD[0] ; C25M ; 7.446 ; ; Rise ; C25M ; +; SD[1] ; C25M ; 7.446 ; ; Rise ; C25M ; +; SD[2] ; C25M ; 7.014 ; ; Rise ; C25M ; +; SD[3] ; C25M ; 7.014 ; ; Rise ; C25M ; +; SD[4] ; C25M ; 7.446 ; ; Rise ; C25M ; +; SD[5] ; C25M ; 7.014 ; ; Rise ; C25M ; +; SD[6] ; C25M ; 7.014 ; ; Rise ; C25M ; +; SD[7] ; C25M ; 7.014 ; ; Rise ; C25M ; +; nFCS ; C25M ; 7.116 ; ; Rise ; C25M ; +; RD[*] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; +; RD[0] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; +; RD[1] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; +; RD[2] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; +; RD[3] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; +; RD[4] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; +; RD[5] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; +; RD[6] ; PHI0 ; 9.796 ; ; Rise ; PHI0 ; +; RD[7] ; PHI0 ; 9.796 ; ; Rise ; PHI0 ; +; RD[*] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; +; RD[0] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; +; RD[1] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; +; RD[2] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; +; RD[3] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; +; RD[4] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; +; RD[5] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; +; RD[6] ; PHI0 ; 9.796 ; ; Fall ; PHI0 ; +; RD[7] ; PHI0 ; 9.796 ; ; Fall ; PHI0 ; +-----------+------------+-----------+-----------+------------+-----------------+ @@ -1144,9 +1142,9 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +------------+----------+----------+----------+----------+----------+ ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; +------------+----------+----------+----------+----------+----------+ -; C25M ; C25M ; 1378 ; 0 ; 0 ; 0 ; -; PHI0 ; C25M ; 84 ; 1 ; 0 ; 0 ; -; C25M ; PHI0 ; 3 ; 0 ; 0 ; 0 ; +; C25M ; C25M ; 1374 ; 0 ; 0 ; 0 ; +; PHI0 ; C25M ; 82 ; 1 ; 0 ; 0 ; +; C25M ; PHI0 ; 5 ; 0 ; 0 ; 0 ; +------------+----------+----------+----------+----------+----------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. @@ -1156,9 +1154,9 @@ Entries labeled "false path" only account for clock-to-clock false paths and not +------------+----------+----------+----------+----------+----------+ ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; +------------+----------+----------+----------+----------+----------+ -; C25M ; C25M ; 1378 ; 0 ; 0 ; 0 ; -; PHI0 ; C25M ; 84 ; 1 ; 0 ; 0 ; -; C25M ; PHI0 ; 3 ; 0 ; 0 ; 0 ; +; C25M ; C25M ; 1374 ; 0 ; 0 ; 0 ; +; PHI0 ; C25M ; 82 ; 1 ; 0 ; 0 ; +; C25M ; PHI0 ; 5 ; 0 ; 0 ; 0 ; +------------+----------+----------+----------+----------+----------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. @@ -1203,7 +1201,7 @@ No dedicated SERDES Receiver circuitry present in device or used in design ; Illegal Clocks ; 0 ; 0 ; ; Unconstrained Clocks ; 0 ; 0 ; ; Unconstrained Input Ports ; 44 ; 44 ; -; Unconstrained Input Port Paths ; 655 ; 655 ; +; Unconstrained Input Port Paths ; 645 ; 645 ; ; Unconstrained Output Ports ; 45 ; 45 ; ; Unconstrained Output Port Paths ; 118 ; 118 ; +---------------------------------+-------+------+ @@ -1215,7 +1213,7 @@ No dedicated SERDES Receiver circuitry present in device or used in design Info: ******************************************************************* Info: Running Quartus II 32-bit TimeQuest Timing Analyzer Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - Info: Processing started: Tue Apr 20 04:00:22 2021 + Info: Processing started: Tue Apr 20 04:20:00 2021 Info: Command: quartus_sta GR8RAM -c GR8RAM Info: qsta_default_script.tcl version: #1 Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected @@ -1230,24 +1228,24 @@ Info (332105): Deriving Clocks Info (332105): create_clock -period 1.000 -name PHI0 PHI0 Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON Critical Warning (332148): Timing requirements not met -Info (332146): Worst-case setup slack is -9.480 +Info (332146): Worst-case setup slack is -9.005 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== - Info (332119): -9.480 -695.573 C25M - Info (332119): -0.522 -0.522 PHI0 -Info (332146): Worst-case hold slack is -0.197 + Info (332119): -9.005 -699.357 C25M + Info (332119): -0.425 -0.425 PHI0 +Info (332146): Worst-case hold slack is -0.248 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== - Info (332119): -0.197 -0.197 PHI0 - Info (332119): 1.385 0.000 C25M -Info (332146): Worst-case recovery slack is -4.399 + Info (332119): -0.248 -0.248 PHI0 + Info (332119): 1.400 0.000 C25M +Info (332146): Worst-case recovery slack is -4.412 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== - Info (332119): -4.399 -127.571 C25M -Info (332146): Worst-case removal slack is 4.845 + Info (332119): -4.412 -127.948 C25M +Info (332146): Worst-case removal slack is 4.858 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== - Info (332119): 4.845 0.000 C25M + Info (332119): 4.858 0.000 C25M Info (332146): Worst-case minimum pulse width slack is -2.289 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== @@ -1258,8 +1256,8 @@ Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings Info: Peak virtual memory: 278 megabytes - Info: Processing ended: Tue Apr 20 04:00:26 2021 - Info: Elapsed time: 00:00:04 + Info: Processing ended: Tue Apr 20 04:20:05 2021 + Info: Elapsed time: 00:00:05 Info: Total CPU time (on all processors): 00:00:04 diff --git a/cpld/output_files/GR8RAM.sta.summary b/cpld/output_files/GR8RAM.sta.summary index 3fc566d..c650a04 100755 --- a/cpld/output_files/GR8RAM.sta.summary +++ b/cpld/output_files/GR8RAM.sta.summary @@ -3,27 +3,27 @@ TimeQuest Timing Analyzer Summary ------------------------------------------------------------ Type : Setup 'C25M' -Slack : -9.480 -TNS : -695.573 +Slack : -9.005 +TNS : -699.357 Type : Setup 'PHI0' -Slack : -0.522 -TNS : -0.522 +Slack : -0.425 +TNS : -0.425 Type : Hold 'PHI0' -Slack : -0.197 -TNS : -0.197 +Slack : -0.248 +TNS : -0.248 Type : Hold 'C25M' -Slack : 1.385 +Slack : 1.400 TNS : 0.000 Type : Recovery 'C25M' -Slack : -4.399 -TNS : -127.571 +Slack : -4.412 +TNS : -127.948 Type : Removal 'C25M' -Slack : 4.845 +Slack : 4.858 TNS : 0.000 Type : Minimum Pulse Width 'C25M'