diff --git a/cpld/GR8RAM.qws b/cpld/GR8RAM.qws deleted file mode 100755 index 28bd7ed..0000000 Binary files a/cpld/GR8RAM.qws and /dev/null differ diff --git a/cpld/GR8RAM.v b/cpld/GR8RAM.v index bccb1db..027eebd 100644 --- a/cpld/GR8RAM.v +++ b/cpld/GR8RAM.v @@ -12,8 +12,12 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, /* Reset/brown-out detect synchronized inputs */ input nRES; - reg nRESr0, nRESr; - always @(posedge C25M) begin nRESr0 <= nRES; nRESr <= nRESr0; end + reg [3:0] nRESf = 0; + reg nRESr = 0; + always @(posedge C25M) begin + nRESf[3:0] <= { nRESf[2:0], nRES }; + nRESr <= nRESf[3] || nRESf[2] || nRESf[1] || nRESf[0]; + end /* Long state counter: counts from 0 to $3FFF */ reg [13:0] LS = 0; @@ -251,7 +255,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, end input [1:0] SetFW; - wire [1:0] SetROM = 2'b11;//~SetFW[1:0]; + wire [1:0] SetROM = ~SetFW[1:0]; wire SetEN16MB = SetROM[1:0]==2'b11; wire SetEN24bit = SetROM[1]; diff --git a/cpld/db/GR8RAM.(0).cnf.cdb b/cpld/db/GR8RAM.(0).cnf.cdb index 23709ce..214d760 100755 Binary files a/cpld/db/GR8RAM.(0).cnf.cdb and b/cpld/db/GR8RAM.(0).cnf.cdb differ diff --git a/cpld/db/GR8RAM.(0).cnf.hdb b/cpld/db/GR8RAM.(0).cnf.hdb index 2ddf8ec..3d61b3a 100755 Binary files a/cpld/db/GR8RAM.(0).cnf.hdb and b/cpld/db/GR8RAM.(0).cnf.hdb differ diff --git a/cpld/db/GR8RAM.asm.qmsg b/cpld/db/GR8RAM.asm.qmsg index 381f231..ba79548 100755 --- a/cpld/db/GR8RAM.asm.qmsg +++ b/cpld/db/GR8RAM.asm.qmsg @@ -1,6 +1,6 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618810037113 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618810037113 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Apr 19 01:27:16 2021 " "Processing started: Mon Apr 19 01:27:16 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618810037113 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1618810037113 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1618810037113 ""} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1618810038270 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1618810038285 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "293 " "Peak virtual memory: 293 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618810038786 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 19 01:27:18 2021 " "Processing ended: Mon Apr 19 01:27:18 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618810038786 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618810038786 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618810038786 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1618810038786 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618905619262 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618905619262 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 04:00:18 2021 " "Processing started: Tue Apr 20 04:00:18 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618905619262 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1618905619262 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1618905619262 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1618905620434 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1618905620465 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "293 " "Peak virtual memory: 293 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618905620872 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 04:00:20 2021 " "Processing ended: Tue Apr 20 04:00:20 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618905620872 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618905620872 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618905620872 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1618905620872 ""} diff --git a/cpld/db/GR8RAM.asm.rdb b/cpld/db/GR8RAM.asm.rdb index 63807fb..476ad5b 100755 Binary files a/cpld/db/GR8RAM.asm.rdb and b/cpld/db/GR8RAM.asm.rdb differ diff --git a/cpld/db/GR8RAM.asm_labs.ddb b/cpld/db/GR8RAM.asm_labs.ddb index 5ee9452..1eadc87 100755 Binary files a/cpld/db/GR8RAM.asm_labs.ddb and b/cpld/db/GR8RAM.asm_labs.ddb differ diff --git a/cpld/db/GR8RAM.cmp.cdb b/cpld/db/GR8RAM.cmp.cdb index e60a210..0fb5a27 100755 Binary files a/cpld/db/GR8RAM.cmp.cdb and b/cpld/db/GR8RAM.cmp.cdb differ diff --git a/cpld/db/GR8RAM.cmp.hdb b/cpld/db/GR8RAM.cmp.hdb index 9b8cf56..d0774b5 100755 Binary files a/cpld/db/GR8RAM.cmp.hdb and b/cpld/db/GR8RAM.cmp.hdb differ diff --git a/cpld/db/GR8RAM.cmp.idb b/cpld/db/GR8RAM.cmp.idb index 0bcd05a..faf24da 100755 Binary files a/cpld/db/GR8RAM.cmp.idb and b/cpld/db/GR8RAM.cmp.idb differ diff --git a/cpld/db/GR8RAM.cmp.rdb b/cpld/db/GR8RAM.cmp.rdb index e3e658d..4918a28 100755 Binary files a/cpld/db/GR8RAM.cmp.rdb and b/cpld/db/GR8RAM.cmp.rdb differ diff --git a/cpld/db/GR8RAM.cmp0.ddb b/cpld/db/GR8RAM.cmp0.ddb index f52ca5a..9496680 100755 Binary files a/cpld/db/GR8RAM.cmp0.ddb and b/cpld/db/GR8RAM.cmp0.ddb differ diff --git a/cpld/db/GR8RAM.db_info b/cpld/db/GR8RAM.db_info index 6154700..0197121 100755 --- a/cpld/db/GR8RAM.db_info +++ b/cpld/db/GR8RAM.db_info @@ -1,3 +1,3 @@ Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition Version_Index = 302049280 -Creation_Time = Sun Apr 18 06:17:35 2021 +Creation_Time = Mon Apr 19 05:50:25 2021 diff --git a/cpld/db/GR8RAM.fit.qmsg b/cpld/db/GR8RAM.fit.qmsg index 34105c7..6352083 100755 --- a/cpld/db/GR8RAM.fit.qmsg +++ b/cpld/db/GR8RAM.fit.qmsg @@ -1,39 +1,39 @@ -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1618810028160 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1618810028175 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618810028331 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618810028331 ""} -{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1618810028597 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1618810028628 ""} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618810028972 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618810028972 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618810028972 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618810028972 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618810028972 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1618810028972 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1618810029144 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1618810029144 ""} -{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1618810029175 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1618810029175 ""} -{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618810029175 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618810029175 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 C25M " " 1.000 C25M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618810029175 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI0 " " 1.000 PHI0" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618810029175 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1618810029175 ""} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618810029175 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618810029191 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618810029191 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618810029207 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI0 Global clock " "Automatically promoted some destinations of signal \"PHI0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~1 " "Destination \"comb~1\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618810029207 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI0r1 " "Destination \"PHI0r1\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618810029207 ""} } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618810029207 ""} -{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI0 " "Pin \"PHI0\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI0 } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "PHI0" } } } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 371 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1618810029207 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "nRESr Global clock " "Automatically promoted signal \"nRESr\" to use Global clock" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 15 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618810029207 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618810029222 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1618810029222 ""} -{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1618810029253 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1618810029316 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1618810029332 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1618810029332 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1618810029332 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618810029363 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1618810030394 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618810030754 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1618810030769 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1618810031988 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618810031988 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1618810032051 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "35 " "Router estimated average interconnect usage is 35% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "35 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 35% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 35% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 35% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1618810032816 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1618810032816 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618810033519 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.53 " "Total time spent on timing analysis during the Fitter is 0.53 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1618810033551 ""} -{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618810033551 ""} -{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1618810033598 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1618810034223 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "372 " "Peak virtual memory: 372 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618810034441 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 19 01:27:14 2021 " "Processing ended: Mon Apr 19 01:27:14 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618810034441 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618810034441 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:09 " "Total CPU time (on all processors): 00:00:09" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618810034441 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1618810034441 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1618905610825 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1618905610856 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618905611950 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618905611950 ""} +{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1618905612184 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1618905612231 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618905612559 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618905612559 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618905612559 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618905612559 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618905612559 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1618905612559 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1618905612731 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1618905612731 ""} +{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1618905612747 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1618905612747 ""} +{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618905612747 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618905612747 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 C25M " " 1.000 C25M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618905612747 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI0 " " 1.000 PHI0" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618905612747 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1618905612747 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618905612762 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618905612762 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618905612762 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618905612778 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI0 Global clock " "Automatically promoted some destinations of signal \"PHI0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~1 " "Destination \"comb~1\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618905612778 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI0r1 " "Destination \"PHI0r1\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618905612778 ""} } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618905612778 ""} +{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI0 " "Pin \"PHI0\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI0 } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "PHI0" } } } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 376 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1618905612794 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "nRESr Global clock " "Automatically promoted signal \"nRESr\" to use Global clock" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 16 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618905612794 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618905612794 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1618905612794 ""} +{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1618905612841 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1618905612934 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1618905612950 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1618905612950 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1618905612950 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618905612997 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1618905613309 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618905613637 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1618905613653 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1618905615075 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618905615075 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1618905615122 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "34 " "Router estimated average interconnect usage is 34% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "34 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1618905615637 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1618905615637 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618905616215 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.45 " "Total time spent on timing analysis during the Fitter is 0.45 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1618905616231 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618905616231 ""} +{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1618905616262 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1618905616575 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "382 " "Peak virtual memory: 382 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618905616794 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 04:00:16 2021 " "Processing ended: Tue Apr 20 04:00:16 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618905616794 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618905616794 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618905616794 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1618905616794 ""} diff --git a/cpld/db/GR8RAM.hier_info b/cpld/db/GR8RAM.hier_info index 69887d7..8bc9544 100755 --- a/cpld/db/GR8RAM.hier_info +++ b/cpld/db/GR8RAM.hier_info @@ -93,7 +93,10 @@ C25M => LS[11].CLK C25M => LS[12].CLK C25M => LS[13].CLK C25M => nRESr.CLK -C25M => nRESr0.CLK +C25M => nRESf[0].CLK +C25M => nRESf[1].CLK +C25M => nRESf[2].CLK +C25M => nRESf[3].CLK C25M => PHI0r2.CLK C25M => PHI0r1.CLK C25M => IS~7.DATAIN @@ -102,11 +105,22 @@ PHI0 => nWEr.CLK PHI0 => RAMSpecSELr.CLK PHI0 => ROMSpecRDr.CLK PHI0 => PHI0r1.DATAIN -nRES => nRESr0.DATAIN +nRES => nRESf[0].DATAIN nRES => IOROMRES.IN1 nRESout <= nRESout~reg0.DB_MAX_OUTPUT_PORT_TYPE -SetFW[0] => ~NO_FANOUT~ -SetFW[1] => ~NO_FANOUT~ +SetFW[0] => Mux1.IN10 +SetFW[0] => Equal17.IN1 +SetFW[1] => comb.IN1 +SetFW[1] => RDD.OUTPUTSELECT +SetFW[1] => RDD.OUTPUTSELECT +SetFW[1] => RDD.OUTPUTSELECT +SetFW[1] => RDD.OUTPUTSELECT +SetFW[1] => SA.OUTPUTSELECT +SetFW[1] => SA.OUTPUTSELECT +SetFW[1] => SA.OUTPUTSELECT +SetFW[1] => SBA.OUTPUTSELECT +SetFW[1] => MOSIout.DATAB +SetFW[1] => Equal17.IN0 INTin => INTout.DATAIN INTout <= INTin.DB_MAX_OUTPUT_PORT_TYPE DMAin => DMAout.DATAIN diff --git a/cpld/db/GR8RAM.hif b/cpld/db/GR8RAM.hif index a16b34c..811c603 100755 Binary files a/cpld/db/GR8RAM.hif and b/cpld/db/GR8RAM.hif differ diff --git a/cpld/db/GR8RAM.map.cdb b/cpld/db/GR8RAM.map.cdb index 57548e3..8f5f177 100755 Binary files a/cpld/db/GR8RAM.map.cdb and b/cpld/db/GR8RAM.map.cdb differ diff --git a/cpld/db/GR8RAM.map.hdb b/cpld/db/GR8RAM.map.hdb index 67a001c..8604a63 100755 Binary files a/cpld/db/GR8RAM.map.hdb and b/cpld/db/GR8RAM.map.hdb differ diff --git a/cpld/db/GR8RAM.map.qmsg b/cpld/db/GR8RAM.map.qmsg index 597a4d0..7e1b66f 100755 --- a/cpld/db/GR8RAM.map.qmsg +++ b/cpld/db/GR8RAM.map.qmsg @@ -1,20 +1,19 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618810019690 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618810019690 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Apr 19 01:26:59 2021 " "Processing started: Mon Apr 19 01:26:59 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618810019690 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618810019690 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618810019690 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1618810021253 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(79) " "Verilog HDL warning at GR8RAM.v(79): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 79 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618810021425 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(259) " "Verilog HDL warning at GR8RAM.v(259): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 259 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618810021425 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1618810021440 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1618810021440 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1618810021550 ""} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(20) " "Verilog HDL assignment warning at GR8RAM.v(20): truncated value with size 32 to match size of target (14)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 20 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618810021565 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(103) " "Verilog HDL assignment warning at GR8RAM.v(103): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 103 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618810021565 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(111) " "Verilog HDL assignment warning at GR8RAM.v(111): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 111 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618810021565 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(118) " "Verilog HDL assignment warning at GR8RAM.v(118): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 118 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618810021565 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(309) " "Verilog HDL assignment warning at GR8RAM.v(309): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 309 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618810021565 "|GR8RAM"} -{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 -1 1618810022925 ""} -{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "nNMIout VCC " "Pin \"nNMIout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 536 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618810023222 "|GR8RAM|nNMIout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nIRQout VCC " "Pin \"nIRQout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 539 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618810023222 "|GR8RAM|nIRQout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nRDYout VCC " "Pin \"nRDYout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 538 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618810023222 "|GR8RAM|nRDYout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nINHout VCC " "Pin \"nINHout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 537 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618810023222 "|GR8RAM|nINHout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RWout VCC " "Pin \"RWout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 540 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618810023222 "|GR8RAM|RWout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nDMAout VCC " "Pin \"nDMAout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 535 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618810023222 "|GR8RAM|nDMAout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 534 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618810023222 "|GR8RAM|RAdir"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1618810023222 ""} -{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1618810023737 ""} -{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SetFW\[0\] " "No output dependent on input pin \"SetFW\[0\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 253 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1618810023784 "|GR8RAM|SetFW[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SetFW\[1\] " "No output dependent on input pin \"SetFW\[1\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 253 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1618810023784 "|GR8RAM|SetFW[1]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1618810023784 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "309 " "Implemented 309 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "28 " "Implemented 28 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1618810023784 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1618810023784 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1618810023784 ""} { "Info" "ICUT_CUT_TM_LCELLS" "229 " "Implemented 229 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1618810023784 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1618810023784 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1618810024034 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 16 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 16 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "301 " "Peak virtual memory: 301 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618810024253 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 19 01:27:04 2021 " "Processing ended: Mon Apr 19 01:27:04 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618810024253 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618810024253 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618810024253 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618810024253 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618905600638 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618905600654 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 04:00:00 2021 " "Processing started: Tue Apr 20 04:00:00 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618905600654 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618905600654 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618905600654 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1618905602575 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(83) " "Verilog HDL warning at GR8RAM.v(83): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 83 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618905602903 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(263) " "Verilog HDL warning at GR8RAM.v(263): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 263 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618905602903 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1618905602903 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1618905602903 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1618905603013 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(24) " "Verilog HDL assignment warning at GR8RAM.v(24): truncated value with size 32 to match size of target (14)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 24 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618905603013 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(107) " "Verilog HDL assignment warning at GR8RAM.v(107): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 107 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618905603013 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(115) " "Verilog HDL assignment warning at GR8RAM.v(115): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 115 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618905603013 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(122) " "Verilog HDL assignment warning at GR8RAM.v(122): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 122 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618905603013 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(313) " "Verilog HDL assignment warning at GR8RAM.v(313): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 313 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618905603013 "|GR8RAM"} +{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 -1 1618905605060 ""} +{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "nNMIout VCC " "Pin \"nNMIout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 540 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618905605482 "|GR8RAM|nNMIout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nIRQout VCC " "Pin \"nIRQout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 543 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618905605482 "|GR8RAM|nIRQout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nRDYout VCC " "Pin \"nRDYout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 542 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618905605482 "|GR8RAM|nRDYout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nINHout VCC " "Pin \"nINHout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 541 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618905605482 "|GR8RAM|nINHout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RWout VCC " "Pin \"RWout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 544 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618905605482 "|GR8RAM|RWout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nDMAout VCC " "Pin \"nDMAout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 539 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618905605482 "|GR8RAM|nDMAout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 538 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618905605482 "|GR8RAM|RAdir"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1618905605482 ""} +{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1618905605997 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "319 " "Implemented 319 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "28 " "Implemented 28 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1618905606044 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1618905606044 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1618905606044 ""} { "Info" "ICUT_CUT_TM_LCELLS" "239 " "Implemented 239 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1618905606044 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1618905606044 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1618905606294 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 13 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 13 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "301 " "Peak virtual memory: 301 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618905606450 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 04:00:06 2021 " "Processing ended: Tue Apr 20 04:00:06 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618905606450 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618905606450 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618905606450 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618905606450 ""} diff --git a/cpld/db/GR8RAM.map.rdb b/cpld/db/GR8RAM.map.rdb index 476c9ee..7cbfe41 100755 Binary files a/cpld/db/GR8RAM.map.rdb and b/cpld/db/GR8RAM.map.rdb differ diff --git a/cpld/db/GR8RAM.pre_map.hdb b/cpld/db/GR8RAM.pre_map.hdb index 83c3677..ff98bc3 100755 Binary files a/cpld/db/GR8RAM.pre_map.hdb and b/cpld/db/GR8RAM.pre_map.hdb differ diff --git a/cpld/db/GR8RAM.quiproj.3068.rdr.flock b/cpld/db/GR8RAM.quiproj.3068.rdr.flock new file mode 100755 index 0000000..e69de29 diff --git a/cpld/db/GR8RAM.root_partition.map.reg_db.cdb b/cpld/db/GR8RAM.root_partition.map.reg_db.cdb index 40014bc..c8f31e4 100755 Binary files a/cpld/db/GR8RAM.root_partition.map.reg_db.cdb and b/cpld/db/GR8RAM.root_partition.map.reg_db.cdb differ diff --git a/cpld/db/GR8RAM.routing.rdb b/cpld/db/GR8RAM.routing.rdb index 5c2267c..7e61603 100755 Binary files a/cpld/db/GR8RAM.routing.rdb and b/cpld/db/GR8RAM.routing.rdb differ diff --git a/cpld/db/GR8RAM.rtlv.hdb b/cpld/db/GR8RAM.rtlv.hdb index 1f4af35..bcdf76e 100755 Binary files a/cpld/db/GR8RAM.rtlv.hdb and b/cpld/db/GR8RAM.rtlv.hdb differ diff --git a/cpld/db/GR8RAM.rtlv_sg.cdb b/cpld/db/GR8RAM.rtlv_sg.cdb index 1eb59c7..eef323f 100755 Binary files a/cpld/db/GR8RAM.rtlv_sg.cdb and b/cpld/db/GR8RAM.rtlv_sg.cdb differ diff --git a/cpld/db/GR8RAM.sgdiff.cdb b/cpld/db/GR8RAM.sgdiff.cdb index affd34e..cd286f3 100755 Binary files a/cpld/db/GR8RAM.sgdiff.cdb and b/cpld/db/GR8RAM.sgdiff.cdb differ diff --git a/cpld/db/GR8RAM.sgdiff.hdb b/cpld/db/GR8RAM.sgdiff.hdb index a1588e2..a6a0ab3 100755 Binary files a/cpld/db/GR8RAM.sgdiff.hdb and b/cpld/db/GR8RAM.sgdiff.hdb differ diff --git a/cpld/db/GR8RAM.sta.qmsg b/cpld/db/GR8RAM.sta.qmsg index 040c775..6b89ed7 100755 --- a/cpld/db/GR8RAM.sta.qmsg +++ b/cpld/db/GR8RAM.sta.qmsg @@ -1,23 +1,23 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618810041817 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618810041817 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Apr 19 01:27:20 2021 " "Processing started: Mon Apr 19 01:27:20 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618810041817 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618810041817 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618810041817 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1618810042020 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1618810042786 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618810042958 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618810042958 ""} -{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1618810043145 ""} -{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1618810043645 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1618810043802 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1618810043817 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C25M C25M " "create_clock -period 1.000 -name C25M C25M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618810043817 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI0 PHI0 " "create_clock -period 1.000 -name PHI0 PHI0" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618810043817 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618810043817 ""} -{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1618810043833 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1618810043942 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -9.468 " "Worst-case setup slack is -9.468" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618810043958 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618810043958 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.468 -696.810 C25M " " -9.468 -696.810 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618810043958 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.212 0.000 PHI0 " " 0.212 0.000 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618810043958 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618810043958 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.265 " "Worst-case hold slack is -0.265" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618810043973 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618810043973 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.265 -0.265 PHI0 " " -0.265 -0.265 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618810043973 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.374 0.000 C25M " " 1.374 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618810043973 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618810043973 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -4.404 " "Worst-case recovery slack is -4.404" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618810043989 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618810043989 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.404 -127.716 C25M " " -4.404 -127.716 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618810043989 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618810043989 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "removal 4.850 " "Worst-case removal slack is 4.850" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618810044005 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618810044005 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.850 0.000 C25M " " 4.850 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618810044005 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618810044005 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.289 " "Worst-case minimum pulse width slack is -2.289" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618810044020 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618810044020 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 C25M " " -2.289 -2.289 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618810044020 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI0 " " -2.289 -2.289 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618810044020 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618810044020 ""} -{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1618810044317 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618810044442 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618810044442 ""} -{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "283 " "Peak virtual memory: 283 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618810044786 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 19 01:27:24 2021 " "Processing ended: Mon Apr 19 01:27:24 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618810044786 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618810044786 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618810044786 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618810044786 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618905623543 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618905623559 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 04:00:22 2021 " "Processing started: Tue Apr 20 04:00:22 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618905623559 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618905623559 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618905623559 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1618905623762 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1618905624590 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618905624746 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618905624746 ""} +{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1618905624934 ""} +{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1618905625418 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1618905625559 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1618905625559 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C25M C25M " "create_clock -period 1.000 -name C25M C25M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618905625559 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI0 PHI0 " "create_clock -period 1.000 -name PHI0 PHI0" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618905625559 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618905625559 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1618905625574 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1618905625668 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -9.480 " "Worst-case setup slack is -9.480" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905625668 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905625668 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.480 -695.573 C25M " " -9.480 -695.573 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905625668 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.522 -0.522 PHI0 " " -0.522 -0.522 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905625668 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618905625668 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.197 " "Worst-case hold slack is -0.197" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905625684 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905625684 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.197 -0.197 PHI0 " " -0.197 -0.197 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905625684 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.385 0.000 C25M " " 1.385 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905625684 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618905625684 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -4.399 " "Worst-case recovery slack is -4.399" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905625699 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905625699 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.399 -127.571 C25M " " -4.399 -127.571 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905625699 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618905625699 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "removal 4.845 " "Worst-case removal slack is 4.845" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905625699 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905625699 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.845 0.000 C25M " " 4.845 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905625699 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618905625699 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.289 " "Worst-case minimum pulse width slack is -2.289" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905625715 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905625715 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 C25M " " -2.289 -2.289 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905625715 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI0 " " -2.289 -2.289 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905625715 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618905625715 ""} +{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1618905625887 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618905625996 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618905625996 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "278 " "Peak virtual memory: 278 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618905626246 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 04:00:26 2021 " "Processing ended: Tue Apr 20 04:00:26 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618905626246 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618905626246 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618905626246 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618905626246 ""} diff --git a/cpld/db/GR8RAM.sta.rdb b/cpld/db/GR8RAM.sta.rdb index c8a53e9..84c82eb 100755 Binary files a/cpld/db/GR8RAM.sta.rdb and b/cpld/db/GR8RAM.sta.rdb differ diff --git a/cpld/db/GR8RAM.sta_cmp.5_slow.tdb b/cpld/db/GR8RAM.sta_cmp.5_slow.tdb index b4b7569..fbbe557 100755 Binary files a/cpld/db/GR8RAM.sta_cmp.5_slow.tdb and b/cpld/db/GR8RAM.sta_cmp.5_slow.tdb differ diff --git a/cpld/db/GR8RAM.vpr.ammdb b/cpld/db/GR8RAM.vpr.ammdb index b472823..7212bd8 100755 Binary files a/cpld/db/GR8RAM.vpr.ammdb and b/cpld/db/GR8RAM.vpr.ammdb differ diff --git a/cpld/db/logic_util_heursitic.dat b/cpld/db/logic_util_heursitic.dat index 04ce9a9..6f3db1c 100755 Binary files a/cpld/db/logic_util_heursitic.dat and b/cpld/db/logic_util_heursitic.dat differ diff --git a/cpld/db/prev_cmp_GR8RAM.qmsg b/cpld/db/prev_cmp_GR8RAM.qmsg index 245b754..9ed85c4 100755 --- a/cpld/db/prev_cmp_GR8RAM.qmsg +++ b/cpld/db/prev_cmp_GR8RAM.qmsg @@ -1,96 +1,96 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618809604705 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618809604705 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Apr 19 01:20:04 2021 " "Processing started: Mon Apr 19 01:20:04 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618809604705 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618809604705 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618809604705 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1618809606627 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(79) " "Verilog HDL warning at GR8RAM.v(79): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 79 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618809606924 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(259) " "Verilog HDL warning at GR8RAM.v(259): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 259 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618809606924 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1618809606939 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1618809606939 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1618809607064 ""} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(20) " "Verilog HDL assignment warning at GR8RAM.v(20): truncated value with size 32 to match size of target (14)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 20 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618809607064 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(103) " "Verilog HDL assignment warning at GR8RAM.v(103): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 103 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618809607064 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(111) " "Verilog HDL assignment warning at GR8RAM.v(111): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 111 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618809607064 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(118) " "Verilog HDL assignment warning at GR8RAM.v(118): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 118 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618809607064 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(309) " "Verilog HDL assignment warning at GR8RAM.v(309): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 309 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618809607064 "|GR8RAM"} -{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 -1 1618809608674 ""} -{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "nNMIout VCC " "Pin \"nNMIout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 536 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618809609002 "|GR8RAM|nNMIout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nIRQout VCC " "Pin \"nIRQout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 539 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618809609002 "|GR8RAM|nIRQout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nRDYout VCC " "Pin \"nRDYout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 538 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618809609002 "|GR8RAM|nRDYout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nINHout VCC " "Pin \"nINHout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 537 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618809609002 "|GR8RAM|nINHout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RWout VCC " "Pin \"RWout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 540 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618809609002 "|GR8RAM|RWout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nDMAout VCC " "Pin \"nDMAout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 535 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618809609002 "|GR8RAM|nDMAout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 534 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618809609002 "|GR8RAM|RAdir"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1618809609002 ""} -{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1618809610173 ""} -{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SetFW\[0\] " "No output dependent on input pin \"SetFW\[0\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 253 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1618809610220 "|GR8RAM|SetFW[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SetFW\[1\] " "No output dependent on input pin \"SetFW\[1\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 253 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1618809610220 "|GR8RAM|SetFW[1]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1618809610220 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "309 " "Implemented 309 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "28 " "Implemented 28 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1618809610236 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1618809610236 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1618809610236 ""} { "Info" "ICUT_CUT_TM_LCELLS" "229 " "Implemented 229 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1618809610236 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1618809610236 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1618809610455 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 16 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 16 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "301 " "Peak virtual memory: 301 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618809610595 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 19 01:20:10 2021 " "Processing ended: Mon Apr 19 01:20:10 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618809610595 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618809610595 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618809610595 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618809610595 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618809613704 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 32-bit " "Running Quartus II 32-bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618809613720 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Apr 19 01:20:12 2021 " "Processing started: Mon Apr 19 01:20:12 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618809613720 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1618809613720 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1618809613720 ""} -{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1618809613876 ""} -{ "Info" "0" "" "Project = GR8RAM" { } { } 0 0 "Project = GR8RAM" 0 0 "Fitter" 0 0 1618809613876 ""} -{ "Info" "0" "" "Revision = GR8RAM" { } { } 0 0 "Revision = GR8RAM" 0 0 "Fitter" 0 0 1618809613876 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1618809614454 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1618809614486 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618809614657 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618809614657 ""} -{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1618809614923 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1618809614954 ""} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618809615251 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618809615251 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618809615251 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618809615251 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618809615251 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1618809615251 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1618809615376 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1618809615392 ""} -{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1618809615392 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1618809615392 ""} -{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618809615407 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618809615407 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 C25M " " 1.000 C25M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618809615407 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI0 " " 1.000 PHI0" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618809615407 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1618809615407 ""} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618809615407 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618809615407 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618809615407 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618809615439 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI0 Global clock " "Automatically promoted some destinations of signal \"PHI0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~1 " "Destination \"comb~1\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618809615439 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI0r1 " "Destination \"PHI0r1\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618809615439 ""} } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618809615439 ""} -{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI0 " "Pin \"PHI0\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI0 } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "PHI0" } } } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 372 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1618809615439 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "nRESr Global clock " "Automatically promoted signal \"nRESr\" to use Global clock" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 15 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618809615439 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618809615439 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1618809615439 ""} -{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1618809615470 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1618809615517 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1618809615517 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1618809615517 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1618809615517 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618809615548 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1618809615970 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618809616298 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1618809616313 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1618809617485 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618809617485 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1618809617548 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "35 " "Router estimated average interconnect usage is 35% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "35 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 35% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 35% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 35% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1618809618266 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1618809618266 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618809618923 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.58 " "Total time spent on timing analysis during the Fitter is 0.58 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1618809618938 ""} -{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618809618954 ""} -{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1618809618985 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1618809619391 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "378 " "Peak virtual memory: 378 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618809619579 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 19 01:20:19 2021 " "Processing ended: Mon Apr 19 01:20:19 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618809619579 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618809619579 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618809619579 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1618809619579 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1618809622188 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618809622188 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Apr 19 01:20:21 2021 " "Processing started: Mon Apr 19 01:20:21 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618809622188 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1618809622188 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1618809622188 ""} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1618809623282 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1618809623313 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "293 " "Peak virtual memory: 293 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618809623813 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 19 01:20:23 2021 " "Processing ended: Mon Apr 19 01:20:23 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618809623813 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618809623813 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618809623813 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1618809623813 ""} -{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1618809624578 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1618809628937 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618809629016 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Apr 19 01:20:26 2021 " "Processing started: Mon Apr 19 01:20:26 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618809629016 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618809629016 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618809629141 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1618809630109 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1618809632281 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618809632593 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618809632593 ""} -{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1618809632843 ""} -{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1618809633593 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1618809633812 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1618809633828 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C25M C25M " "create_clock -period 1.000 -name C25M C25M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618809633828 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI0 PHI0 " "create_clock -period 1.000 -name PHI0 PHI0" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618809633828 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618809633828 ""} -{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1618809633843 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1618809634000 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -9.468 " "Worst-case setup slack is -9.468" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618809634046 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618809634046 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.468 -696.810 C25M " " -9.468 -696.810 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618809634046 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.212 0.000 PHI0 " " 0.212 0.000 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618809634046 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618809634046 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.265 " "Worst-case hold slack is -0.265" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618809634062 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618809634062 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.265 -0.265 PHI0 " " -0.265 -0.265 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618809634062 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.374 0.000 C25M " " 1.374 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618809634062 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618809634062 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -4.404 " "Worst-case recovery slack is -4.404" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618809634078 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618809634078 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.404 -127.716 C25M " " -4.404 -127.716 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618809634078 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618809634078 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "removal 4.850 " "Worst-case removal slack is 4.850" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618809634093 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618809634093 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.850 0.000 C25M " " 4.850 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618809634093 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618809634093 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.289 " "Worst-case minimum pulse width slack is -2.289" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618809634140 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618809634140 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 C25M " " -2.289 -2.289 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618809634140 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI0 " " -2.289 -2.289 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618809634140 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618809634140 ""} -{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1618809634921 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618809635265 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618809635265 ""} -{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "283 " "Peak virtual memory: 283 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618809635624 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 19 01:20:35 2021 " "Processing ended: Mon Apr 19 01:20:35 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618809635624 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618809635624 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618809635624 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618809635624 ""} -{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 21 s " "Quartus II Full Compilation was successful. 0 errors, 21 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618809636734 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618905490360 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618905490376 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 03:58:08 2021 " "Processing started: Tue Apr 20 03:58:08 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618905490376 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618905490376 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618905490376 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1618905491798 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(83) " "Verilog HDL warning at GR8RAM.v(83): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 83 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618905491985 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(263) " "Verilog HDL warning at GR8RAM.v(263): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 263 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618905491985 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1618905491985 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1618905491985 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1618905492110 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(24) " "Verilog HDL assignment warning at GR8RAM.v(24): truncated value with size 32 to match size of target (14)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 24 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618905492110 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(107) " "Verilog HDL assignment warning at GR8RAM.v(107): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 107 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618905492110 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(115) " "Verilog HDL assignment warning at GR8RAM.v(115): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 115 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618905492110 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(122) " "Verilog HDL assignment warning at GR8RAM.v(122): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 122 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618905492110 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(313) " "Verilog HDL assignment warning at GR8RAM.v(313): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 313 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618905492126 "|GR8RAM"} +{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 -1 1618905493501 ""} +{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "nNMIout VCC " "Pin \"nNMIout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 540 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618905493798 "|GR8RAM|nNMIout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nIRQout VCC " "Pin \"nIRQout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 543 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618905493798 "|GR8RAM|nIRQout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nRDYout VCC " "Pin \"nRDYout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 542 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618905493798 "|GR8RAM|nRDYout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nINHout VCC " "Pin \"nINHout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 541 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618905493798 "|GR8RAM|nINHout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RWout VCC " "Pin \"RWout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 544 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618905493798 "|GR8RAM|RWout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nDMAout VCC " "Pin \"nDMAout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 539 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618905493798 "|GR8RAM|nDMAout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 538 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618905493798 "|GR8RAM|RAdir"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1618905493798 ""} +{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1618905494188 ""} +{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SetFW\[0\] " "No output dependent on input pin \"SetFW\[0\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 257 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1618905494251 "|GR8RAM|SetFW[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SetFW\[1\] " "No output dependent on input pin \"SetFW\[1\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 257 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1618905494251 "|GR8RAM|SetFW[1]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1618905494251 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "311 " "Implemented 311 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "28 " "Implemented 28 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1618905494266 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1618905494266 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1618905494266 ""} { "Info" "ICUT_CUT_TM_LCELLS" "231 " "Implemented 231 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1618905494266 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1618905494266 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1618905494720 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 16 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 16 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "301 " "Peak virtual memory: 301 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618905495032 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 03:58:14 2021 " "Processing ended: Tue Apr 20 03:58:14 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618905495032 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618905495032 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618905495032 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618905495032 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618905504408 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 32-bit " "Running Quartus II 32-bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618905504423 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 03:58:23 2021 " "Processing started: Tue Apr 20 03:58:23 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618905504423 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1618905504423 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1618905504423 ""} +{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1618905504579 ""} +{ "Info" "0" "" "Project = GR8RAM" { } { } 0 0 "Project = GR8RAM" 0 0 "Fitter" 0 0 1618905504579 ""} +{ "Info" "0" "" "Revision = GR8RAM" { } { } 0 0 "Revision = GR8RAM" 0 0 "Fitter" 0 0 1618905504579 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1618905505423 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1618905505454 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618905507220 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618905507220 ""} +{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1618905510158 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1618905510205 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618905510736 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618905510736 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618905510736 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618905510736 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618905510736 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1618905510736 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1618905511142 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1618905511158 ""} +{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1618905511158 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1618905511158 ""} +{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618905511173 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618905511173 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 C25M " " 1.000 C25M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618905511173 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI0 " " 1.000 PHI0" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618905511173 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1618905511173 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618905511173 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618905511173 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618905511173 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618905511189 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI0 Global clock " "Automatically promoted some destinations of signal \"PHI0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~1 " "Destination \"comb~1\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618905511189 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI0r1 " "Destination \"PHI0r1\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618905511189 ""} } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618905511189 ""} +{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI0 " "Pin \"PHI0\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI0 } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "PHI0" } } } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 375 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1618905511205 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "nRESr Global clock " "Automatically promoted signal \"nRESr\" to use Global clock" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 16 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618905511205 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618905511205 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1618905511205 ""} +{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1618905511236 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1618905511298 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1618905511298 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1618905511298 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1618905511298 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618905511330 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1618905511970 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618905512283 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1618905512314 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1618905513392 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618905513392 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1618905513455 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "29 " "Router estimated average interconnect usage is 29% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "29 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 29% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 29% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 29% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1618905513908 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1618905513908 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618905514439 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.53 " "Total time spent on timing analysis during the Fitter is 0.53 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1618905514455 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618905514455 ""} +{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1618905514486 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1618905514783 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "372 " "Peak virtual memory: 372 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618905514924 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 03:58:34 2021 " "Processing ended: Tue Apr 20 03:58:34 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618905514924 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618905514924 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:09 " "Total CPU time (on all processors): 00:00:09" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618905514924 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1618905514924 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1618905517830 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618905517846 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 03:58:37 2021 " "Processing started: Tue Apr 20 03:58:37 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618905517846 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1618905517846 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1618905517846 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1618905520377 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1618905520393 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "293 " "Peak virtual memory: 293 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618905520783 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 03:58:40 2021 " "Processing ended: Tue Apr 20 03:58:40 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618905520783 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618905520783 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618905520783 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1618905520783 ""} +{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1618905521502 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1618905523627 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618905523627 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 03:58:42 2021 " "Processing started: Tue Apr 20 03:58:42 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618905523627 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618905523627 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618905523627 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1618905523799 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1618905524502 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618905524737 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618905524737 ""} +{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1618905524908 ""} +{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1618905525346 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1618905525502 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1618905525502 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C25M C25M " "create_clock -period 1.000 -name C25M C25M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618905525502 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI0 PHI0 " "create_clock -period 1.000 -name PHI0 PHI0" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618905525502 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618905525502 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1618905525518 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1618905525658 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -9.202 " "Worst-case setup slack is -9.202" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905525674 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905525674 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.202 -651.252 C25M " " -9.202 -651.252 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905525674 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.202 0.000 PHI0 " " 0.202 0.000 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905525674 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618905525674 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.143 " "Worst-case hold slack is 0.143" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905525690 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905525690 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.143 0.000 PHI0 " " 0.143 0.000 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905525690 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.385 0.000 C25M " " 1.385 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905525690 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618905525690 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -4.416 " "Worst-case recovery slack is -4.416" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905525705 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905525705 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.416 -128.064 C25M " " -4.416 -128.064 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905525705 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618905525705 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "removal 4.862 " "Worst-case removal slack is 4.862" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905525721 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905525721 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.862 0.000 C25M " " 4.862 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905525721 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618905525721 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.289 " "Worst-case minimum pulse width slack is -2.289" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905525737 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905525737 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 C25M " " -2.289 -2.289 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905525737 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI0 " " -2.289 -2.289 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618905525737 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618905525737 ""} +{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1618905525987 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618905526096 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618905526096 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "283 " "Peak virtual memory: 283 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618905526268 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 03:58:46 2021 " "Processing ended: Tue Apr 20 03:58:46 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618905526268 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618905526268 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618905526268 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618905526268 ""} +{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 21 s " "Quartus II Full Compilation was successful. 0 errors, 21 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618905527362 ""} diff --git a/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt b/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt index 741c2ff..4f8958c 100755 Binary files a/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt and b/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt differ diff --git a/cpld/output_files/GR8RAM.asm.rpt b/cpld/output_files/GR8RAM.asm.rpt index 9f44fdf..07cc802 100755 --- a/cpld/output_files/GR8RAM.asm.rpt +++ b/cpld/output_files/GR8RAM.asm.rpt @@ -1,5 +1,5 @@ Assembler report for GR8RAM -Mon Apr 19 01:27:18 2021 +Tue Apr 20 04:00:20 2021 Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition @@ -37,7 +37,7 @@ applicable agreement for further details. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Mon Apr 19 01:27:18 2021 ; +; Assembler Status ; Successful - Tue Apr 20 04:00:20 2021 ; ; Revision Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ; ; Family ; MAX II ; @@ -90,8 +90,8 @@ applicable agreement for further details. ; Option ; Setting ; +----------------+-------------------------------------------------------+ ; Device ; EPM240T100C5 ; -; JTAG usercode ; 0x00163FE1 ; -; Checksum ; 0x001642D1 ; +; JTAG usercode ; 0x0016534D ; +; Checksum ; 0x0016564D ; +----------------+-------------------------------------------------------+ @@ -101,13 +101,13 @@ applicable agreement for further details. Info: ******************************************************************* Info: Running Quartus II 32-bit Assembler Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - Info: Processing started: Mon Apr 19 01:27:16 2021 + Info: Processing started: Tue Apr 20 04:00:18 2021 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM Info (115031): Writing out detailed assembly data for power analysis Info (115030): Assembler is generating device programming files Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings Info: Peak virtual memory: 293 megabytes - Info: Processing ended: Mon Apr 19 01:27:18 2021 + Info: Processing ended: Tue Apr 20 04:00:20 2021 Info: Elapsed time: 00:00:02 Info: Total CPU time (on all processors): 00:00:02 diff --git a/cpld/output_files/GR8RAM.done b/cpld/output_files/GR8RAM.done index cf64c93..09d1d95 100755 --- a/cpld/output_files/GR8RAM.done +++ b/cpld/output_files/GR8RAM.done @@ -1 +1 @@ -Mon Apr 19 01:27:26 2021 +Tue Apr 20 04:00:27 2021 diff --git a/cpld/output_files/GR8RAM.fit.rpt b/cpld/output_files/GR8RAM.fit.rpt index 1338016..0973378 100755 --- a/cpld/output_files/GR8RAM.fit.rpt +++ b/cpld/output_files/GR8RAM.fit.rpt @@ -1,5 +1,5 @@ Fitter report for GR8RAM -Mon Apr 19 01:27:14 2021 +Tue Apr 20 04:00:16 2021 Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition @@ -59,14 +59,14 @@ applicable agreement for further details. +-----------------------------------------------------------------------------+ ; Fitter Summary ; +---------------------------+-------------------------------------------------+ -; Fitter Status ; Successful - Mon Apr 19 01:27:14 2021 ; +; Fitter Status ; Successful - Tue Apr 20 04:00:16 2021 ; ; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; ; Revision Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ; ; Family ; MAX II ; ; Device ; EPM240T100C5 ; ; Timing Models ; Final ; -; Total logic elements ; 222 / 240 ( 93 % ) ; +; Total logic elements ; 230 / 240 ( 96 % ) ; ; Total pins ; 80 / 80 ( 100 % ) ; ; Total virtual pins ; 0 ; ; UFM blocks ; 0 / 1 ( 0 % ) ; @@ -130,11 +130,12 @@ applicable agreement for further details. ; Number detected on machine ; 2 ; ; Maximum allowed ; 2 ; ; ; ; -; Average used ; 2.00 ; +; Average used ; 1.20 ; ; Maximum used ; 2 ; ; ; ; ; Usage by Processor ; % Time Used ; -; Processors 1-2 ; 100.0% ; +; Processor 1 ; 100.0% ; +; Processor 2 ; 20.0% ; +----------------------------+-------------+ @@ -149,27 +150,27 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin. +---------------------------------------------+--------------------+ ; Resource ; Usage ; +---------------------------------------------+--------------------+ -; Total logic elements ; 222 / 240 ( 93 % ) ; -; -- Combinational with no register ; 119 ; +; Total logic elements ; 230 / 240 ( 96 % ) ; +; -- Combinational with no register ; 124 ; ; -- Register only ; 1 ; -; -- Combinational with a register ; 102 ; +; -- Combinational with a register ; 105 ; ; ; ; ; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 123 ; -; -- 3 input functions ; 27 ; -; -- 2 input functions ; 69 ; +; -- 4 input functions ; 122 ; +; -- 3 input functions ; 37 ; +; -- 2 input functions ; 68 ; ; -- 1 input functions ; 0 ; ; -- 0 input functions ; 2 ; ; ; ; ; Logic elements by mode ; ; -; -- normal mode ; 189 ; +; -- normal mode ; 197 ; ; -- arithmetic mode ; 33 ; -; -- qfbk mode ; 3 ; +; -- qfbk mode ; 4 ; ; -- register cascade mode ; 0 ; -; -- synchronous clear/load mode ; 49 ; +; -- synchronous clear/load mode ; 52 ; ; -- asynchronous clear/load mode ; 30 ; ; ; ; -; Total registers ; 103 / 240 ( 43 % ) ; +; Total registers ; 106 / 240 ( 44 % ) ; ; Total LABs ; 24 / 24 ( 100 % ) ; ; Logic elements in carry chains ; 37 ; ; Virtual pins ; 0 ; @@ -180,12 +181,12 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin. ; UFM blocks ; 0 / 1 ( 0 % ) ; ; Global clocks ; 3 / 4 ( 75 % ) ; ; JTAGs ; 0 / 1 ( 0 % ) ; -; Average interconnect usage (total/H/V) ; 45% / 51% / 38% ; -; Peak interconnect usage (total/H/V) ; 45% / 51% / 38% ; -; Maximum fan-out ; 100 ; -; Highest non-global fan-out ; 47 ; -; Total fan-out ; 1023 ; -; Average fan-out ; 3.39 ; +; Average interconnect usage (total/H/V) ; 44% / 48% / 39% ; +; Peak interconnect usage (total/H/V) ; 44% / 48% / 39% ; +; Maximum fan-out ; 103 ; +; Highest non-global fan-out ; 45 ; +; Total fan-out ; 1053 ; +; Average fan-out ; 3.40 ; +---------------------------------------------+--------------------+ @@ -194,19 +195,19 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin. +----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+ ; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Location assigned by ; +----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+ -; C25M ; 64 ; 2 ; 8 ; 3 ; 4 ; 100 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; User ; +; C25M ; 64 ; 2 ; 8 ; 3 ; 4 ; 103 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; User ; ; DMAin ; 48 ; 1 ; 6 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; ; INTin ; 49 ; 1 ; 7 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; ; MISO ; 16 ; 1 ; 1 ; 2 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; ; PHI0 ; 41 ; 1 ; 5 ; 0 ; 1 ; 5 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; RA[0] ; 100 ; 2 ; 2 ; 5 ; 2 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; +; RA[0] ; 100 ; 2 ; 2 ; 5 ; 2 ; 9 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; ; RA[10] ; 14 ; 1 ; 1 ; 2 ; 0 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; ; RA[11] ; 34 ; 1 ; 3 ; 0 ; 1 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; ; RA[12] ; 35 ; 1 ; 3 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; ; RA[13] ; 36 ; 1 ; 4 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; ; RA[14] ; 37 ; 1 ; 4 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; ; RA[15] ; 38 ; 1 ; 4 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; RA[1] ; 98 ; 2 ; 2 ; 5 ; 0 ; 7 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; +; RA[1] ; 98 ; 2 ; 2 ; 5 ; 0 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; ; RA[2] ; 97 ; 2 ; 3 ; 5 ; 3 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; ; RA[3] ; 4 ; 1 ; 1 ; 4 ; 2 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; ; RA[4] ; 1 ; 2 ; 2 ; 5 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; @@ -215,8 +216,8 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin. ; RA[7] ; 6 ; 1 ; 1 ; 3 ; 0 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; ; RA[8] ; 7 ; 1 ; 1 ; 3 ; 1 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; ; RA[9] ; 8 ; 1 ; 1 ; 3 ; 2 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; SetFW[0] ; 96 ; 2 ; 3 ; 5 ; 2 ; 0 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; SetFW[1] ; 95 ; 2 ; 3 ; 5 ; 1 ; 0 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; +; SetFW[0] ; 96 ; 2 ; 3 ; 5 ; 2 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; +; SetFW[1] ; 95 ; 2 ; 3 ; 5 ; 1 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; ; nDEVSEL ; 40 ; 1 ; 5 ; 0 ; 2 ; 4 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; ; nIOSEL ; 39 ; 1 ; 5 ; 0 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; ; nIOSTRB ; 42 ; 1 ; 5 ; 0 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; @@ -232,7 +233,7 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin. +---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ ; DMAout ; 18 ; 1 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; ; DQMH ; 57 ; 2 ; 8 ; 2 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; -; DQML ; 85 ; 2 ; 5 ; 5 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; +; DQML ; 85 ; 2 ; 5 ; 5 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; - ; - ; ; FCK ; 12 ; 1 ; 1 ; 3 ; 3 ; no ; no ; no ; no ; yes ; yes ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; ; INTout ; 20 ; 1 ; 1 ; 1 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; ; RAdir ; 19 ; 1 ; 1 ; 1 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; @@ -256,7 +257,7 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin. ; SBA[1] ; 71 ; 2 ; 8 ; 4 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; ; nCAS ; 61 ; 2 ; 8 ; 2 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; ; nDMAout ; 21 ; 1 ; 1 ; 1 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; -; nFCS ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; no ; no ; no ; yes ; no ; On ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; +; nFCS ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; no ; no ; no ; yes ; no ; On ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; - ; - ; ; nINHout ; 27 ; 1 ; 2 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; ; nIRQout ; 29 ; 1 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; ; nNMIout ; 26 ; 1 ; 2 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; @@ -289,7 +290,7 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin. ; SD[4] ; 51 ; 1 ; 7 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; ; SD[5] ; 52 ; 2 ; 8 ; 1 ; 4 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; ; SD[6] ; 53 ; 2 ; 8 ; 1 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; -; SD[7] ; 54 ; 2 ; 8 ; 1 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; SDOE ; - ; +; SD[7] ; 54 ; 2 ; 8 ; 1 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; +-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ @@ -433,7 +434,7 @@ Note: User assignments will override these defaults. The user specified values a +----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+ ; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ; +----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+ -; |GR8RAM ; 222 (222) ; 103 ; 0 ; 80 ; 0 ; 119 (119) ; 1 (1) ; 102 (102) ; 37 (37) ; 5 (5) ; |GR8RAM ; work ; +; |GR8RAM ; 230 (230) ; 106 ; 0 ; 80 ; 0 ; 124 (124) ; 1 (1) ; 105 (105) ; 37 (37) ; 8 (8) ; |GR8RAM ; work ; +----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. @@ -443,8 +444,6 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +----------+----------+---------------+ ; Name ; Pin Type ; Pad to Core 0 ; +----------+----------+---------------+ -; SetFW[0] ; Input ; (0) ; -; SetFW[1] ; Input ; (0) ; ; INTin ; Input ; (1) ; ; DMAin ; Input ; (1) ; ; nIOSTRB ; Input ; (1) ; @@ -465,11 +464,13 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; RA[9] ; Input ; (1) ; ; RA[10] ; Input ; (1) ; ; nRES ; Input ; (1) ; +; SetFW[1] ; Input ; (1) ; ; RA[11] ; Input ; (1) ; ; RA[14] ; Input ; (1) ; ; RA[15] ; Input ; (1) ; ; RA[12] ; Input ; (1) ; ; RA[13] ; Input ; (1) ; +; SetFW[0] ; Input ; (1) ; ; MISO ; Input ; (1) ; ; nRESout ; Output ; -- ; ; INTout ; Output ; -- ; @@ -531,22 +532,22 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +------------+-------------+---------+---------------------------------------+--------+----------------------+------------------+ ; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; +------------+-------------+---------+---------------------------------------+--------+----------------------+------------------+ -; C25M ; PIN_64 ; 100 ; Clock ; yes ; Global Clock ; GCLK3 ; -; Decoder1~0 ; LC_X6_Y1_N8 ; 8 ; Clock enable ; no ; -- ; -- ; -; Equal0~0 ; LC_X5_Y2_N9 ; 19 ; Clock enable ; no ; -- ; -- ; -; FCKOE ; LC_X3_Y4_N7 ; 2 ; Output enable ; no ; -- ; -- ; -; IOROMRES ; LC_X2_Y3_N6 ; 1 ; Async. clear ; no ; -- ; -- ; -; MOSIOE ; LC_X3_Y4_N6 ; 1 ; Output enable ; no ; -- ; -- ; +; C25M ; PIN_64 ; 103 ; Clock ; yes ; Global Clock ; GCLK3 ; +; Decoder1~0 ; LC_X7_Y3_N6 ; 8 ; Clock enable ; no ; -- ; -- ; +; Equal0~0 ; LC_X5_Y3_N3 ; 19 ; Clock enable ; no ; -- ; -- ; +; FCKOE ; LC_X2_Y1_N0 ; 2 ; Output enable ; no ; -- ; -- ; +; IOROMRES ; LC_X2_Y3_N9 ; 1 ; Async. clear ; no ; -- ; -- ; +; MOSIOE ; LC_X2_Y1_N7 ; 1 ; Output enable ; no ; -- ; -- ; ; PHI0 ; PIN_41 ; 5 ; Clock ; yes ; Global Clock ; GCLK1 ; -; PS[0] ; LC_X4_Y3_N6 ; 46 ; Clock enable, Sync. clear, Sync. load ; no ; -- ; -- ; -; PS[2] ; LC_X3_Y3_N5 ; 29 ; Sync. clear, Sync. load ; no ; -- ; -- ; -; SDOE ; LC_X5_Y1_N6 ; 8 ; Output enable ; no ; -- ; -- ; -; always5~1 ; LC_X2_Y3_N9 ; 2 ; Clock enable ; no ; -- ; -- ; -; always7~2 ; LC_X2_Y3_N2 ; 8 ; Sync. load ; no ; -- ; -- ; -; always7~3 ; LC_X2_Y3_N5 ; 9 ; Sync. load ; no ; -- ; -- ; -; always7~4 ; LC_X2_Y3_N1 ; 9 ; Sync. load ; no ; -- ; -- ; -; comb~1 ; LC_X4_Y1_N8 ; 9 ; Output enable ; no ; -- ; -- ; -; nRESr ; LC_X2_Y3_N9 ; 29 ; Async. clear ; yes ; Global Clock ; GCLK2 ; +; PS[0] ; LC_X5_Y3_N2 ; 44 ; Clock enable, Sync. clear, Sync. load ; no ; -- ; -- ; +; PS[2] ; LC_X5_Y3_N4 ; 27 ; Sync. clear, Sync. load ; no ; -- ; -- ; +; SDOE ; LC_X7_Y1_N2 ; 8 ; Output enable ; no ; -- ; -- ; +; always5~1 ; LC_X2_Y3_N5 ; 2 ; Clock enable ; no ; -- ; -- ; +; always7~2 ; LC_X5_Y1_N9 ; 8 ; Sync. load ; no ; -- ; -- ; +; always7~3 ; LC_X4_Y1_N4 ; 9 ; Sync. load ; no ; -- ; -- ; +; always7~4 ; LC_X4_Y1_N9 ; 9 ; Sync. load ; no ; -- ; -- ; +; comb~1 ; LC_X6_Y4_N9 ; 9 ; Output enable ; no ; -- ; -- ; +; nRESr ; LC_X2_Y3_N8 ; 29 ; Async. clear ; yes ; Global Clock ; GCLK2 ; +------------+-------------+---------+---------------------------------------+--------+----------------------+------------------+ @@ -555,9 +556,9 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +-------+-------------+---------+----------------------+------------------+ ; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; +-------+-------------+---------+----------------------+------------------+ -; C25M ; PIN_64 ; 100 ; Global Clock ; GCLK3 ; +; C25M ; PIN_64 ; 103 ; Global Clock ; GCLK3 ; ; PHI0 ; PIN_41 ; 5 ; Global Clock ; GCLK1 ; -; nRESr ; LC_X2_Y3_N9 ; 29 ; Global Clock ; GCLK2 ; +; nRESr ; LC_X2_Y3_N8 ; 29 ; Global Clock ; GCLK2 ; +-------+-------------+---------+----------------------+------------------+ @@ -566,42 +567,46 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +---------------------+-----------+ ; Name ; Fan-Out ; +---------------------+-----------+ -; PS[0] ; 47 ; -; PS[1] ; 33 ; -; PS[2] ; 29 ; -; PS[3] ; 28 ; -; IS.state_bit_0 ; 20 ; +; PS[0] ; 45 ; +; PS[1] ; 31 ; +; PS[3] ; 29 ; +; PS[2] ; 27 ; ; Equal0~0 ; 19 ; +; IS.state_bit_0 ; 19 ; ; IS.110~0 ; 17 ; -; IS.state_bit_1 ; 17 ; +; RAMSpecSELr ; 16 ; +; IS.state_bit_1 ; 16 ; ; LS[0] ; 13 ; -; RDD[1]~18 ; 12 ; -; AddrMSpecSEL ; 12 ; -; RAMSpecSELr ; 11 ; +; RA[0] ; 9 ; +; RDD[1]~23 ; 9 ; ; always7~4 ; 9 ; ; always7~3 ; 9 ; ; comb~1 ; 9 ; -; RA[0] ; 8 ; +; SetFW[1] ; 8 ; +; RA[1] ; 8 ; +; RDD[1]~22 ; 8 ; ; Decoder1~0 ; 8 ; ; SDOE ; 8 ; ; always7~2 ; 8 ; ; IS.state_bit_2 ; 8 ; -; SA[7]~8 ; 8 ; ; LS[2] ; 8 ; -; RA[1] ; 7 ; +; SA[0]~8 ; 7 ; ; RD[7]~7 ; 6 ; -; SA[7]~16 ; 6 ; -; Equal18~0 ; 6 ; -; SA[7]~10 ; 6 ; -; SA[7]~9 ; 6 ; +; SA[3]~17 ; 6 ; +; SA[3]~10 ; 6 ; +; SA[3]~9 ; 6 ; ; LS[1] ; 6 ; ; RD[0]~0 ; 5 ; ; RA[3] ; 5 ; ; RA[2] ; 5 ; +; RDD[4]~12 ; 5 ; +; RAMRegSpecSEL~0 ; 5 ; +; REGSpecSEL~1 ; 5 ; ; Addr[0] ; 5 ; ; LS[6]~17 ; 5 ; ; LS[1]~3 ; 5 ; -; Mux14~6 ; 5 ; +; Mux14~3 ; 5 ; +; Addr[23] ; 5 ; ; RD[6]~6 ; 4 ; ; RD[5]~5 ; 4 ; ; RD[4]~4 ; 4 ; @@ -610,11 +615,11 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; RD[1]~1 ; 4 ; ; nDEVSEL ; 4 ; ; always7~6 ; 4 ; -; REGSpecSEL~1 ; 4 ; -; RAMRegSpecSEL~0 ; 4 ; +; RDD[4]~13 ; 4 ; ; LS[13] ; 4 ; ; Equal1~2 ; 4 ; ; nRCS~1 ; 4 ; +; Equal18~0 ; 4 ; ; Addr[9] ; 4 ; ; Addr[8] ; 4 ; ; Addr[7] ; 4 ; @@ -630,10 +635,9 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; Addr[12] ; 4 ; ; Addr[2] ; 4 ; ; Addr[11] ; 4 ; -; SA[2]~7 ; 4 ; +; SA[0]~7 ; 4 ; ; Addr[1] ; 4 ; ; Addr[10] ; 4 ; -; Addr[23] ; 4 ; ; always5~0 ; 4 ; ; RA[11] ; 3 ; ; RA[10] ; 3 ; @@ -641,7 +645,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; RA[8] ; 3 ; ; RA[7] ; 3 ; ; nWE ; 3 ; -; SA[2]~15 ; 3 ; +; SA[0]~16 ; 3 ; ; WRD[5] ; 3 ; ; WRD[4] ; 3 ; ; WRD[3] ; 3 ; @@ -657,6 +661,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; Addr[21] ; 3 ; ; Addr[20]~41 ; 3 ; ; Addr[20] ; 3 ; +; SA~11 ; 3 ; ; Addr[19] ; 3 ; ; LS[9] ; 3 ; ; Addr[18] ; 3 ; @@ -670,9 +675,10 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; LS[12] ; 3 ; ; Addr[12]~11 ; 3 ; ; LS[11] ; 3 ; -; SA[2]~5 ; 3 ; +; SA[0]~5 ; 3 ; ; LS[10] ; 3 ; -; SA[2]~4 ; 3 ; +; SA[0]~4 ; 3 ; +; SetFW[0] ; 2 ; ; RA[6] ; 2 ; ; RA[5] ; 2 ; ; RA[4] ; 2 ; @@ -682,6 +688,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; WRD[6] ; 2 ; ; AddrIncL ; 2 ; ; AddrIncM ; 2 ; +; RAMRegSpecSEL ; 2 ; ; Equal7~0 ; 2 ; ; REGSpecSEL~0 ; 2 ; ; IS.state_bit_1~3 ; 2 ; @@ -695,12 +702,15 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; ROMSpecRDr ; 2 ; ; nRCS~2 ; 2 ; ; nWEr ; 2 ; -; SA[2]~12 ; 2 ; ; Bank ; 2 ; ; LS[11]~5 ; 2 ; -; SA[2]~6 ; 2 ; -; Mux14~4 ; 2 ; +; SA[0]~6 ; 2 ; +; nRESf[2] ; 2 ; +; Mux14~1 ; 2 ; +; Mux14~0 ; 2 ; +; nRESf[1] ; 2 ; ; always5~1 ; 2 ; +; nRESf[0] ; 2 ; ; comb~2 ; 2 ; ; IOROMEN ; 2 ; ; nRESout~reg0 ; 2 ; @@ -721,17 +731,20 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; nRES ; 1 ; ; DMAin ; 1 ; ; INTin ; 1 ; -; Mux14~7 ; 1 ; +; Mux13~2 ; 1 ; +; Mux2~3 ; 1 ; +; Mux2~2 ; 1 ; ; Mux2~1 ; 1 ; ; Mux2~0 ; 1 ; +; SA[0]~15 ; 1 ; +; RDD~20 ; 1 ; +; RDD~18 ; 1 ; ; RDD~16 ; 1 ; ; RDD~14 ; 1 ; -; RDD~12 ; 1 ; ; RDD~10 ; 1 ; ; RDD~8 ; 1 ; ; RDD~6 ; 1 ; ; RDD~4 ; 1 ; -; RDD~2 ; 1 ; ; AddrIncM~2 ; 1 ; ; AddrIncM~1 ; 1 ; ; AddrIncM~0 ; 1 ; @@ -754,7 +767,6 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; IS.state_bit_2~0 ; 1 ; ; Equal1~4 ; 1 ; ; AddrIncH ; 1 ; -; RAMRegSpecSEL ; 1 ; ; REGEN ; 1 ; ; IS.state_bit_1~2 ; 1 ; ; IS.state_bit_1~1 ; 1 ; @@ -785,6 +797,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; Addr[22]~45 ; 1 ; ; Addr[21]~43COUT1_76 ; 1 ; ; Addr[21]~43 ; 1 ; +; Mux15~1 ; 1 ; ; Mux15~0 ; 1 ; ; Addr[19]~39COUT1_74 ; 1 ; ; Addr[19]~39 ; 1 ; @@ -865,9 +878,9 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; LS[10]~1 ; 1 ; ; Addr[10]~3COUT1_84 ; 1 ; ; Addr[10]~3 ; 1 ; -; Mux13~0 ; 1 ; -; Mux14~5 ; 1 ; -; nRESr0 ; 1 ; +; Mux14~4 ; 1 ; +; nRESf[3] ; 1 ; +; Mux14~2 ; 1 ; ; IOROMRES ; 1 ; ; comb~4 ; 1 ; ; comb~3 ; 1 ; @@ -903,31 +916,31 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +-----------------------------+--------------------+ ; Other Routing Resource Type ; Usage ; +-----------------------------+--------------------+ -; C4s ; 248 / 784 ( 32 % ) ; -; Direct links ; 55 / 888 ( 6 % ) ; +; C4s ; 251 / 784 ( 32 % ) ; +; Direct links ; 45 / 888 ( 5 % ) ; ; Global clocks ; 3 / 4 ( 75 % ) ; ; LAB clocks ; 12 / 32 ( 38 % ) ; -; LUT chains ; 27 / 216 ( 13 % ) ; -; Local interconnects ; 429 / 888 ( 48 % ) ; -; R4s ; 300 / 704 ( 43 % ) ; +; LUT chains ; 33 / 216 ( 15 % ) ; +; Local interconnects ; 436 / 888 ( 49 % ) ; +; R4s ; 284 / 704 ( 40 % ) ; +-----------------------------+--------------------+ +---------------------------------------------------------------------------+ ; LAB Logic Elements ; +--------------------------------------------+------------------------------+ -; Number of Logic Elements (Average = 9.25) ; Number of LABs (Total = 24) ; +; Number of Logic Elements (Average = 9.58) ; Number of LABs (Total = 24) ; +--------------------------------------------+------------------------------+ ; 1 ; 0 ; -; 2 ; 0 ; +; 2 ; 1 ; ; 3 ; 0 ; -; 4 ; 1 ; +; 4 ; 0 ; ; 5 ; 0 ; -; 6 ; 2 ; +; 6 ; 0 ; ; 7 ; 0 ; ; 8 ; 1 ; -; 9 ; 2 ; -; 10 ; 18 ; +; 9 ; 0 ; +; 10 ; 22 ; +--------------------------------------------+------------------------------+ @@ -938,9 +951,9 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +------------------------------------+------------------------------+ ; 1 Async. clear ; 7 ; ; 1 Clock ; 22 ; -; 1 Clock enable ; 7 ; +; 1 Clock enable ; 6 ; ; 1 Sync. clear ; 5 ; -; 1 Sync. load ; 4 ; +; 1 Sync. load ; 5 ; ; 2 Clocks ; 2 ; +------------------------------------+------------------------------+ @@ -948,43 +961,43 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +----------------------------------------------------------------------------+ ; LAB Signals Sourced ; +---------------------------------------------+------------------------------+ -; Number of Signals Sourced (Average = 9.54) ; Number of LABs (Total = 24) ; +; Number of Signals Sourced (Average = 9.96) ; Number of LABs (Total = 24) ; +---------------------------------------------+------------------------------+ ; 0 ; 0 ; ; 1 ; 0 ; -; 2 ; 0 ; +; 2 ; 1 ; ; 3 ; 0 ; -; 4 ; 1 ; +; 4 ; 0 ; ; 5 ; 0 ; -; 6 ; 2 ; +; 6 ; 0 ; ; 7 ; 0 ; ; 8 ; 1 ; -; 9 ; 2 ; -; 10 ; 14 ; +; 9 ; 0 ; +; 10 ; 18 ; ; 11 ; 2 ; ; 12 ; 1 ; -; 13 ; 1 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 1 ; +---------------------------------------------+------------------------------+ +--------------------------------------------------------------------------------+ ; LAB Signals Sourced Out ; +-------------------------------------------------+------------------------------+ -; Number of Signals Sourced Out (Average = 6.79) ; Number of LABs (Total = 24) ; +; Number of Signals Sourced Out (Average = 6.92) ; Number of LABs (Total = 24) ; +-------------------------------------------------+------------------------------+ ; 0 ; 0 ; ; 1 ; 0 ; ; 2 ; 1 ; ; 3 ; 1 ; -; 4 ; 4 ; -; 5 ; 3 ; +; 4 ; 2 ; +; 5 ; 5 ; ; 6 ; 2 ; -; 7 ; 3 ; +; 7 ; 2 ; ; 8 ; 2 ; ; 9 ; 4 ; -; 10 ; 3 ; -; 11 ; 0 ; -; 12 ; 1 ; +; 10 ; 5 ; +-------------------------------------------------+------------------------------+ @@ -997,25 +1010,25 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; 1 ; 0 ; ; 2 ; 0 ; ; 3 ; 0 ; -; 4 ; 1 ; +; 4 ; 0 ; ; 5 ; 0 ; -; 6 ; 0 ; +; 6 ; 2 ; ; 7 ; 0 ; -; 8 ; 2 ; +; 8 ; 1 ; ; 9 ; 0 ; ; 10 ; 0 ; -; 11 ; 2 ; -; 12 ; 3 ; -; 13 ; 0 ; -; 14 ; 0 ; -; 15 ; 2 ; -; 16 ; 3 ; -; 17 ; 2 ; -; 18 ; 2 ; -; 19 ; 2 ; -; 20 ; 1 ; -; 21 ; 3 ; -; 22 ; 1 ; +; 11 ; 1 ; +; 12 ; 0 ; +; 13 ; 4 ; +; 14 ; 1 ; +; 15 ; 4 ; +; 16 ; 1 ; +; 17 ; 1 ; +; 18 ; 3 ; +; 19 ; 1 ; +; 20 ; 2 ; +; 21 ; 0 ; +; 22 ; 3 ; +----------------------------------------------+------------------------------+ @@ -1048,7 +1061,7 @@ This will disable optimization of problematic paths and expose them for further +-----------------+----------------------+-------------------+ ; Source Register ; Destination Register ; Delay Added in ns ; +-----------------+----------------------+-------------------+ -; PHI0 ; PHI0r1 ; 0.507 ; +; PHI0 ; PHI0r1 ; 0.186 ; +-----------------+----------------------+-------------------+ Note: This table only shows the top 1 path(s) that have the largest delay added for hold. @@ -1089,25 +1102,25 @@ Info (176234): Starting register packing Info (186468): Started processing fast register assignments Info (186469): Finished processing fast register assignments Info (176235): Finished register packing -Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01 +Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00 Info (170189): Fitter placement preparation operations beginning Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 Info (170191): Fitter placement operations beginning Info (170137): Fitter placement was successful Info (170192): Fitter placement operations ending: elapsed time is 00:00:01 Info (170193): Fitter routing operations beginning -Info (170195): Router estimated average interconnect usage is 35% of the available device resources - Info (170196): Router estimated peak interconnect usage is 35% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5 +Info (170195): Router estimated average interconnect usage is 34% of the available device resources + Info (170196): Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5 Info (170194): Fitter routing operations ending: elapsed time is 00:00:01 -Info (11888): Total time spent on timing analysis during the Fitter is 0.53 seconds. +Info (11888): Total time spent on timing analysis during the Fitter is 0.45 seconds. Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00 Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'. Info (144001): Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg Info: Quartus II 32-bit Fitter was successful. 0 errors, 3 warnings - Info: Peak virtual memory: 372 megabytes - Info: Processing ended: Mon Apr 19 01:27:14 2021 - Info: Elapsed time: 00:00:09 - Info: Total CPU time (on all processors): 00:00:09 + Info: Peak virtual memory: 382 megabytes + Info: Processing ended: Tue Apr 20 04:00:16 2021 + Info: Elapsed time: 00:00:08 + Info: Total CPU time (on all processors): 00:00:08 +----------------------------+ diff --git a/cpld/output_files/GR8RAM.fit.summary b/cpld/output_files/GR8RAM.fit.summary index 75b2259..c299461 100755 --- a/cpld/output_files/GR8RAM.fit.summary +++ b/cpld/output_files/GR8RAM.fit.summary @@ -1,11 +1,11 @@ -Fitter Status : Successful - Mon Apr 19 01:27:14 2021 +Fitter Status : Successful - Tue Apr 20 04:00:16 2021 Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition Revision Name : GR8RAM Top-level Entity Name : GR8RAM Family : MAX II Device : EPM240T100C5 Timing Models : Final -Total logic elements : 222 / 240 ( 93 % ) +Total logic elements : 230 / 240 ( 96 % ) Total pins : 80 / 80 ( 100 % ) Total virtual pins : 0 UFM blocks : 0 / 1 ( 0 % ) diff --git a/cpld/output_files/GR8RAM.flow.rpt b/cpld/output_files/GR8RAM.flow.rpt index b05c4f8..e828679 100755 --- a/cpld/output_files/GR8RAM.flow.rpt +++ b/cpld/output_files/GR8RAM.flow.rpt @@ -1,5 +1,5 @@ Flow report for GR8RAM -Mon Apr 19 01:27:24 2021 +Tue Apr 20 04:00:26 2021 Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition @@ -40,14 +40,14 @@ applicable agreement for further details. +-----------------------------------------------------------------------------+ ; Flow Summary ; +---------------------------+-------------------------------------------------+ -; Flow Status ; Successful - Mon Apr 19 01:27:18 2021 ; +; Flow Status ; Successful - Tue Apr 20 04:00:20 2021 ; ; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; ; Revision Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ; ; Family ; MAX II ; ; Device ; EPM240T100C5 ; ; Timing Models ; Final ; -; Total logic elements ; 222 / 240 ( 93 % ) ; +; Total logic elements ; 230 / 240 ( 96 % ) ; ; Total pins ; 80 / 80 ( 100 % ) ; ; Total virtual pins ; 0 ; ; UFM blocks ; 0 / 1 ( 0 % ) ; @@ -59,7 +59,7 @@ applicable agreement for further details. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 04/19/2021 01:27:01 ; +; Start date & time ; 04/20/2021 04:00:02 ; ; Main task ; Compilation ; ; Revision Name ; GR8RAM ; +-------------------+---------------------+ @@ -75,7 +75,7 @@ applicable agreement for further details. ; ALM_REGISTER_PACKING_EFFORT ; High ; Medium ; -- ; -- ; ; AUTO_PACKED_REGISTERS_MAXII ; Minimize Area ; Auto ; -- ; -- ; ; AUTO_RESOURCE_SHARING ; On ; Off ; -- ; -- ; -; COMPILER_SIGNATURE_ID ; 44085571633675.161881002002548 ; -- ; -- ; -- ; +; COMPILER_SIGNATURE_ID ; 44085571633675.161890560102556 ; -- ; -- ; -- ; ; FINAL_PLACEMENT_OPTIMIZATION ; Always ; Automatically ; -- ; -- ; ; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ; ; IOBANK_VCCIO ; 3.3V ; -- ; -- ; 1 ; @@ -102,11 +102,11 @@ applicable agreement for further details. +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:04 ; 1.0 ; 301 MB ; 00:00:04 ; -; Fitter ; 00:00:09 ; 2.0 ; 372 MB ; 00:00:08 ; +; Analysis & Synthesis ; 00:00:06 ; 1.0 ; 301 MB ; 00:00:05 ; +; Fitter ; 00:00:08 ; 1.2 ; 382 MB ; 00:00:08 ; ; Assembler ; 00:00:02 ; 1.0 ; 292 MB ; 00:00:02 ; -; TimeQuest Timing Analyzer ; 00:00:04 ; 1.0 ; 283 MB ; 00:00:04 ; -; Total ; 00:00:19 ; -- ; -- ; 00:00:18 ; +; TimeQuest Timing Analyzer ; 00:00:04 ; 1.0 ; 278 MB ; 00:00:04 ; +; Total ; 00:00:20 ; -- ; -- ; 00:00:19 ; +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ diff --git a/cpld/output_files/GR8RAM.jdi b/cpld/output_files/GR8RAM.jdi index 7b766c8..e2079b0 100755 --- a/cpld/output_files/GR8RAM.jdi +++ b/cpld/output_files/GR8RAM.jdi @@ -1,6 +1,6 @@ - + diff --git a/cpld/output_files/GR8RAM.map.rpt b/cpld/output_files/GR8RAM.map.rpt index e165956..5bc7bc2 100755 --- a/cpld/output_files/GR8RAM.map.rpt +++ b/cpld/output_files/GR8RAM.map.rpt @@ -1,5 +1,5 @@ Analysis & Synthesis report for GR8RAM -Mon Apr 19 01:27:04 2021 +Tue Apr 20 04:00:06 2021 Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition @@ -45,12 +45,12 @@ applicable agreement for further details. +-------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +-----------------------------+-------------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Mon Apr 19 01:27:03 2021 ; +; Analysis & Synthesis Status ; Successful - Tue Apr 20 04:00:06 2021 ; ; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; ; Revision Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ; ; Family ; MAX II ; -; Total logic elements ; 229 ; +; Total logic elements ; 239 ; ; Total pins ; 80 ; ; Total virtual pins ; 0 ; ; UFM blocks ; 0 / 1 ( 0 % ) ; @@ -161,33 +161,33 @@ applicable agreement for further details. +---------------------------------------------+-------+ ; Resource ; Usage ; +---------------------------------------------+-------+ -; Total logic elements ; 229 ; -; -- Combinational with no register ; 126 ; -; -- Register only ; 8 ; -; -- Combinational with a register ; 95 ; +; Total logic elements ; 239 ; +; -- Combinational with no register ; 133 ; +; -- Register only ; 10 ; +; -- Combinational with a register ; 96 ; ; ; ; ; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 123 ; -; -- 3 input functions ; 27 ; -; -- 2 input functions ; 69 ; +; -- 4 input functions ; 122 ; +; -- 3 input functions ; 37 ; +; -- 2 input functions ; 68 ; ; -- 1 input functions ; 0 ; ; -- 0 input functions ; 2 ; ; ; ; ; Logic elements by mode ; ; -; -- normal mode ; 196 ; +; -- normal mode ; 206 ; ; -- arithmetic mode ; 33 ; ; -- qfbk mode ; 0 ; ; -- register cascade mode ; 0 ; ; -- synchronous clear/load mode ; 44 ; ; -- asynchronous clear/load mode ; 30 ; ; ; ; -; Total registers ; 103 ; +; Total registers ; 106 ; ; Total logic cells in carry chains ; 37 ; ; I/O pins ; 80 ; ; Maximum fan-out node ; C25M ; -; Maximum fan-out ; 100 ; -; Total fan-out ; 1015 ; -; Average fan-out ; 3.28 ; +; Maximum fan-out ; 103 ; +; Total fan-out ; 1044 ; +; Average fan-out ; 3.27 ; +---------------------------------------------+-------+ @@ -196,7 +196,7 @@ applicable agreement for further details. +----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+ ; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ; +----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+ -; |GR8RAM ; 229 (229) ; 103 ; 0 ; 80 ; 0 ; 126 (126) ; 8 (8) ; 95 (95) ; 37 (37) ; 0 (0) ; |GR8RAM ; work ; +; |GR8RAM ; 239 (239) ; 106 ; 0 ; 80 ; 0 ; 133 (133) ; 10 (10) ; 96 (96) ; 37 (37) ; 0 (0) ; |GR8RAM ; work ; +----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. @@ -231,7 +231,7 @@ Encoding Type: Minimal Bits +----------------------------------------------+-------+ ; Statistic ; Value ; +----------------------------------------------+-------+ -; Total registers ; 103 ; +; Total registers ; 106 ; ; Number of registers using Synchronous Clear ; 11 ; ; Number of registers using Synchronous Load ; 33 ; ; Number of registers using Asynchronous Clear ; 30 ; @@ -263,11 +263,12 @@ Encoding Type: Minimal Bits ; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ ; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |GR8RAM|PS[1] ; -; 4:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |GR8RAM|SA[9]~reg0 ; -; 20:1 ; 6 bits ; 78 LEs ; 24 LEs ; 54 LEs ; Yes ; |GR8RAM|SA[7]~reg0 ; -; 20:1 ; 3 bits ; 39 LEs ; 18 LEs ; 21 LEs ; Yes ; |GR8RAM|SA[2]~reg0 ; +; 5:1 ; 2 bits ; 6 LEs ; 2 LEs ; 4 LEs ; Yes ; |GR8RAM|SA[11]~reg0 ; +; 20:1 ; 6 bits ; 78 LEs ; 24 LEs ; 54 LEs ; Yes ; |GR8RAM|SA[3]~reg0 ; +; 20:1 ; 3 bits ; 39 LEs ; 18 LEs ; 21 LEs ; Yes ; |GR8RAM|SA[0]~reg0 ; ; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |GR8RAM|WRD[7] ; -; 4:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |GR8RAM|RDD[1] ; +; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |GR8RAM|RDD[1] ; +; 5:1 ; 4 bits ; 12 LEs ; 8 LEs ; 4 LEs ; Yes ; |GR8RAM|RDD[4] ; ; 18:1 ; 2 bits ; 24 LEs ; 8 LEs ; 16 LEs ; Yes ; |GR8RAM|DQMH~reg0 ; ; 8:1 ; 5 bits ; 25 LEs ; 20 LEs ; 5 LEs ; No ; |GR8RAM|IS ; +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ @@ -279,17 +280,17 @@ Encoding Type: Minimal Bits Info: ******************************************************************* Info: Running Quartus II 32-bit Analysis & Synthesis Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - Info: Processing started: Mon Apr 19 01:26:59 2021 + Info: Processing started: Tue Apr 20 04:00:00 2021 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected Info (12021): Found 1 design units, including 1 entities, in source file gr8ram.v Info (12023): Found entity 1: GR8RAM Info (12127): Elaborating entity "GR8RAM" for the top level hierarchy -Warning (10230): Verilog HDL assignment warning at GR8RAM.v(20): truncated value with size 32 to match size of target (14) -Warning (10230): Verilog HDL assignment warning at GR8RAM.v(103): truncated value with size 32 to match size of target (8) -Warning (10230): Verilog HDL assignment warning at GR8RAM.v(111): truncated value with size 32 to match size of target (8) -Warning (10230): Verilog HDL assignment warning at GR8RAM.v(118): truncated value with size 32 to match size of target (8) -Warning (10230): Verilog HDL assignment warning at GR8RAM.v(309): truncated value with size 32 to match size of target (4) +Warning (10230): Verilog HDL assignment warning at GR8RAM.v(24): truncated value with size 32 to match size of target (14) +Warning (10230): Verilog HDL assignment warning at GR8RAM.v(107): truncated value with size 32 to match size of target (8) +Warning (10230): Verilog HDL assignment warning at GR8RAM.v(115): truncated value with size 32 to match size of target (8) +Warning (10230): Verilog HDL assignment warning at GR8RAM.v(122): truncated value with size 32 to match size of target (8) +Warning (10230): Verilog HDL assignment warning at GR8RAM.v(313): truncated value with size 32 to match size of target (4) Info (17026): Resynthesizing 0 WYSIWYG logic cells and I/Os using "area" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched Warning (13024): Output pins are stuck at VCC or GND Warning (13410): Pin "nNMIout" is stuck at VCC @@ -300,19 +301,16 @@ Warning (13024): Output pins are stuck at VCC or GND Warning (13410): Pin "nDMAout" is stuck at VCC Warning (13410): Pin "RAdir" is stuck at VCC Info (17049): 1 registers lost all their fanouts during netlist optimizations. -Warning (21074): Design contains 2 input pin(s) that do not drive logic - Warning (15610): No output dependent on input pin "SetFW[0]" - Warning (15610): No output dependent on input pin "SetFW[1]" -Info (21057): Implemented 309 device resources after synthesis - the final resource count might be different +Info (21057): Implemented 319 device resources after synthesis - the final resource count might be different Info (21058): Implemented 28 input pins Info (21059): Implemented 35 output pins Info (21060): Implemented 17 bidirectional pins - Info (21061): Implemented 229 logic cells + Info (21061): Implemented 239 logic cells Info (144001): Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg -Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 16 warnings +Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 13 warnings Info: Peak virtual memory: 301 megabytes - Info: Processing ended: Mon Apr 19 01:27:04 2021 - Info: Elapsed time: 00:00:05 + Info: Processing ended: Tue Apr 20 04:00:06 2021 + Info: Elapsed time: 00:00:06 Info: Total CPU time (on all processors): 00:00:05 diff --git a/cpld/output_files/GR8RAM.map.smsg b/cpld/output_files/GR8RAM.map.smsg index f40de6b..8d8b43e 100755 --- a/cpld/output_files/GR8RAM.map.smsg +++ b/cpld/output_files/GR8RAM.map.smsg @@ -1,2 +1,2 @@ -Warning (10273): Verilog HDL warning at GR8RAM.v(79): extended using "x" or "z" -Warning (10273): Verilog HDL warning at GR8RAM.v(259): extended using "x" or "z" +Warning (10273): Verilog HDL warning at GR8RAM.v(83): extended using "x" or "z" +Warning (10273): Verilog HDL warning at GR8RAM.v(263): extended using "x" or "z" diff --git a/cpld/output_files/GR8RAM.map.summary b/cpld/output_files/GR8RAM.map.summary index fb1c00f..1658f02 100755 --- a/cpld/output_files/GR8RAM.map.summary +++ b/cpld/output_files/GR8RAM.map.summary @@ -1,9 +1,9 @@ -Analysis & Synthesis Status : Successful - Mon Apr 19 01:27:03 2021 +Analysis & Synthesis Status : Successful - Tue Apr 20 04:00:06 2021 Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition Revision Name : GR8RAM Top-level Entity Name : GR8RAM Family : MAX II -Total logic elements : 229 +Total logic elements : 239 Total pins : 80 Total virtual pins : 0 UFM blocks : 0 / 1 ( 0 % ) diff --git a/cpld/output_files/GR8RAM.pof b/cpld/output_files/GR8RAM.pof index 0872853..f206bca 100755 Binary files a/cpld/output_files/GR8RAM.pof and b/cpld/output_files/GR8RAM.pof differ diff --git a/cpld/output_files/GR8RAM.sta.rpt b/cpld/output_files/GR8RAM.sta.rpt index 96d55fa..59bf5b6 100755 --- a/cpld/output_files/GR8RAM.sta.rpt +++ b/cpld/output_files/GR8RAM.sta.rpt @@ -1,5 +1,5 @@ TimeQuest Timing Analyzer report for GR8RAM -Mon Apr 19 01:27:24 2021 +Tue Apr 20 04:00:26 2021 Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition @@ -86,11 +86,11 @@ applicable agreement for further details. ; Maximum allowed ; 2 ; ; ; ; ; Average used ; 1.00 ; -; Maximum used ; 2 ; +; Maximum used ; 1 ; ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; -; Processor 2 ; < 0.1% ; +; Processor 2 ; 0.0% ; +----------------------------+-------------+ @@ -109,7 +109,7 @@ applicable agreement for further details. +------------+-----------------+------------+------+ ; Fmax ; Restricted Fmax ; Clock Name ; Note ; +------------+-----------------+------------+------+ -; 100.46 MHz ; 100.46 MHz ; C25M ; ; +; 101.04 MHz ; 101.04 MHz ; C25M ; ; +------------+-----------------+------------+------+ This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. @@ -119,8 +119,8 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +-------+--------+---------------+ -; C25M ; -9.468 ; -696.810 ; -; PHI0 ; 0.212 ; 0.000 ; +; C25M ; -9.480 ; -695.573 ; +; PHI0 ; -0.522 ; -0.522 ; +-------+--------+---------------+ @@ -129,8 +129,8 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +-------+--------+---------------+ -; PHI0 ; -0.265 ; -0.265 ; -; C25M ; 1.374 ; 0.000 ; +; PHI0 ; -0.197 ; -0.197 ; +; C25M ; 1.385 ; 0.000 ; +-------+--------+---------------+ @@ -139,7 +139,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +-------+--------+---------------+ -; C25M ; -4.404 ; -127.716 ; +; C25M ; -4.399 ; -127.571 ; +-------+--------+---------------+ @@ -148,7 +148,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +-------+-------+---------------+ -; C25M ; 4.850 ; 0.000 ; +; C25M ; 4.845 ; 0.000 ; +-------+-------+---------------+ @@ -167,117 +167,118 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +--------+----------------+----------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+----------------+----------------+--------------+-------------+--------------+------------+------------+ -; -9.468 ; RAMSpecSELr ; SA[1]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.791 ; 7.344 ; -; -9.201 ; RAMSpecSELr ; RCKE~reg0 ; PHI0 ; C25M ; 1.000 ; -2.791 ; 7.077 ; -; -9.122 ; nWEr ; Addr[0] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.998 ; -; -9.122 ; nWEr ; Addr[1] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.998 ; -; -9.122 ; nWEr ; Addr[2] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.998 ; -; -9.122 ; nWEr ; Addr[3] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.998 ; -; -9.122 ; nWEr ; Addr[4] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.998 ; -; -9.122 ; nWEr ; Addr[5] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.998 ; -; -9.122 ; nWEr ; Addr[6] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.998 ; -; -9.122 ; nWEr ; Addr[7] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.998 ; -; -9.097 ; RAMSpecSELr ; SA[0]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.973 ; -; -9.073 ; nWEr ; RCKE~reg0 ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.949 ; -; -9.028 ; nWEr ; Addr[23] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.904 ; -; -9.028 ; nWEr ; Addr[16] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.904 ; -; -9.028 ; nWEr ; Addr[17] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.904 ; -; -9.028 ; nWEr ; Addr[18] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.904 ; -; -9.028 ; nWEr ; Addr[19] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.904 ; -; -9.028 ; nWEr ; Addr[20] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.904 ; -; -9.028 ; nWEr ; Addr[21] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.904 ; -; -9.028 ; nWEr ; Addr[22] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.904 ; -; -8.999 ; RAMSpecSELr ; SA[7]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.875 ; -; -8.954 ; PS[0] ; SA[2]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.621 ; -; -8.925 ; nWEr ; Addr[10] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.801 ; -; -8.925 ; nWEr ; Addr[11] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.801 ; -; -8.925 ; nWEr ; Addr[12] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.801 ; -; -8.925 ; nWEr ; Addr[13] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.801 ; -; -8.925 ; nWEr ; Addr[14] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.801 ; -; -8.925 ; nWEr ; Addr[15] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.801 ; -; -8.925 ; nWEr ; Addr[8] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.801 ; -; -8.925 ; nWEr ; Addr[9] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.801 ; -; -8.873 ; RAMSpecSELr ; SA[5]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.749 ; -; -8.872 ; PS[0] ; Addr[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.539 ; -; -8.872 ; PS[0] ; Addr[1] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.539 ; -; -8.872 ; PS[0] ; Addr[2] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.539 ; -; -8.872 ; PS[0] ; Addr[3] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.539 ; -; -8.872 ; PS[0] ; Addr[4] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.539 ; -; -8.872 ; PS[0] ; Addr[5] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.539 ; -; -8.872 ; PS[0] ; Addr[6] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.539 ; -; -8.872 ; PS[0] ; Addr[7] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.539 ; -; -8.795 ; RAMSpecSELr ; SA[8]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.671 ; -; -8.778 ; PS[0] ; Addr[23] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.445 ; -; -8.778 ; PS[0] ; Addr[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.445 ; -; -8.778 ; PS[0] ; Addr[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.445 ; -; -8.778 ; PS[0] ; Addr[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.445 ; -; -8.778 ; PS[0] ; Addr[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.445 ; -; -8.778 ; PS[0] ; Addr[20] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.445 ; -; -8.778 ; PS[0] ; Addr[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.445 ; -; -8.778 ; PS[0] ; Addr[22] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.445 ; -; -8.765 ; nWEr ; nRCS~reg0 ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.641 ; -; -8.729 ; ROMSpecRDr ; RCKE~reg0 ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.605 ; -; -8.728 ; PS[1] ; IS.state_bit_2 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.395 ; -; -8.675 ; PS[0] ; Addr[10] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.342 ; -; -8.675 ; PS[0] ; Addr[11] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.342 ; -; -8.675 ; PS[0] ; Addr[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.342 ; -; -8.675 ; PS[0] ; Addr[13] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.342 ; -; -8.675 ; PS[0] ; Addr[14] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.342 ; -; -8.675 ; PS[0] ; Addr[15] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.342 ; -; -8.675 ; PS[0] ; Addr[8] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.342 ; -; -8.675 ; PS[0] ; Addr[9] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.342 ; -; -8.610 ; PS[2] ; Addr[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.277 ; -; -8.610 ; PS[2] ; Addr[1] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.277 ; -; -8.610 ; PS[2] ; Addr[2] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.277 ; -; -8.610 ; PS[2] ; Addr[3] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.277 ; -; -8.610 ; PS[2] ; Addr[4] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.277 ; -; -8.610 ; PS[2] ; Addr[5] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.277 ; -; -8.610 ; PS[2] ; Addr[6] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.277 ; -; -8.610 ; PS[2] ; Addr[7] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.277 ; -; -8.590 ; RAMSpecSELr ; SA[6]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.466 ; -; -8.589 ; RAMSpecSELr ; SA[4]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.465 ; -; -8.579 ; RAMSpecSELr ; SA[3]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.455 ; -; -8.559 ; RAMSpecSELr ; SA[2]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.435 ; -; -8.516 ; PS[2] ; Addr[23] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.183 ; -; -8.516 ; PS[2] ; Addr[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.183 ; -; -8.516 ; PS[2] ; Addr[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.183 ; -; -8.516 ; PS[2] ; Addr[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.183 ; -; -8.516 ; PS[2] ; Addr[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.183 ; -; -8.516 ; PS[2] ; Addr[20] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.183 ; -; -8.516 ; PS[2] ; Addr[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.183 ; -; -8.516 ; PS[2] ; Addr[22] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.183 ; -; -8.469 ; RAMSpecSELr ; nRCS~reg0 ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.345 ; -; -8.461 ; PS[1] ; Addr[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.128 ; -; -8.461 ; PS[1] ; Addr[1] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.128 ; -; -8.461 ; PS[1] ; Addr[2] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.128 ; -; -8.461 ; PS[1] ; Addr[3] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.128 ; -; -8.461 ; PS[1] ; Addr[4] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.128 ; -; -8.461 ; PS[1] ; Addr[5] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.128 ; -; -8.461 ; PS[1] ; Addr[6] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.128 ; -; -8.461 ; PS[1] ; Addr[7] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.128 ; -; -8.413 ; PS[2] ; Addr[10] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.080 ; -; -8.413 ; PS[2] ; Addr[11] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.080 ; -; -8.413 ; PS[2] ; Addr[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.080 ; -; -8.413 ; PS[2] ; Addr[13] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.080 ; -; -8.413 ; PS[2] ; Addr[14] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.080 ; -; -8.413 ; PS[2] ; Addr[15] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.080 ; -; -8.413 ; PS[2] ; Addr[8] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.080 ; -; -8.413 ; PS[2] ; Addr[9] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.080 ; -; -8.403 ; IS.state_bit_0 ; SA[1]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.070 ; -; -8.384 ; nWEr ; SDOE ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.260 ; -; -8.367 ; PS[1] ; Addr[23] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.034 ; -; -8.367 ; PS[1] ; Addr[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.034 ; +; -9.480 ; RAMSpecSELr ; SA[5]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.770 ; 7.377 ; +; -9.226 ; RAMSpecSELr ; RCKE~reg0 ; PHI0 ; C25M ; 1.000 ; -2.770 ; 7.123 ; +; -9.117 ; nWEr ; nRCS~reg0 ; PHI0 ; C25M ; 1.000 ; -2.770 ; 7.014 ; +; -9.113 ; nWEr ; RCKE~reg0 ; PHI0 ; C25M ; 1.000 ; -2.770 ; 7.010 ; +; -9.094 ; ROMSpecRDr ; RCKE~reg0 ; PHI0 ; C25M ; 1.000 ; -2.770 ; 6.991 ; +; -8.985 ; RAMSpecSELr ; nRCS~reg0 ; PHI0 ; C25M ; 1.000 ; -2.770 ; 6.882 ; +; -8.897 ; IS.state_bit_0 ; SA[5]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.564 ; +; -8.742 ; RAMSpecSELr ; SA[8]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.770 ; 6.639 ; +; -8.660 ; RAMSpecSELr ; SA[0]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.770 ; 6.557 ; +; -8.653 ; RAMSpecSELr ; SA[1]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.770 ; 6.550 ; +; -8.647 ; RAMSpecSELr ; SA[6]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.770 ; 6.544 ; +; -8.644 ; RAMSpecSELr ; SA[4]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.770 ; 6.541 ; +; -8.619 ; ROMSpecRDr ; nRCS~reg0 ; PHI0 ; C25M ; 1.000 ; -2.770 ; 6.516 ; +; -8.573 ; IS.state_bit_1 ; RCKE~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.240 ; +; -8.539 ; RAMSpecSELr ; SA[7]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.770 ; 6.436 ; +; -8.522 ; PS[1] ; Addr[23] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.189 ; +; -8.522 ; PS[1] ; Addr[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.189 ; +; -8.522 ; PS[1] ; Addr[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.189 ; +; -8.522 ; PS[1] ; Addr[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.189 ; +; -8.522 ; PS[1] ; Addr[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.189 ; +; -8.522 ; PS[1] ; Addr[20] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.189 ; +; -8.522 ; PS[1] ; Addr[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.189 ; +; -8.522 ; PS[1] ; Addr[22] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.189 ; +; -8.492 ; Addr[8] ; RDD[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.159 ; +; -8.470 ; RAMSpecSELr ; SA[3]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.770 ; 6.367 ; +; -8.366 ; PS[2] ; RCKE~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.033 ; +; -8.364 ; IS.state_bit_0 ; SA[0]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.031 ; +; -8.357 ; IS.state_bit_0 ; SA[1]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.024 ; +; -8.319 ; IS.state_bit_1 ; SA[5]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.986 ; +; -8.314 ; IS.state_bit_0 ; RCKE~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.981 ; +; -8.296 ; nWEr ; SDOE ; PHI0 ; C25M ; 1.000 ; -2.770 ; 6.193 ; +; -8.263 ; PS[1] ; RCKE~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.930 ; +; -8.261 ; nWEr ; Addr[23] ; PHI0 ; C25M ; 1.000 ; -2.770 ; 6.158 ; +; -8.261 ; nWEr ; Addr[16] ; PHI0 ; C25M ; 1.000 ; -2.770 ; 6.158 ; +; -8.261 ; nWEr ; Addr[17] ; PHI0 ; C25M ; 1.000 ; -2.770 ; 6.158 ; +; -8.261 ; nWEr ; Addr[18] ; PHI0 ; C25M ; 1.000 ; -2.770 ; 6.158 ; +; -8.261 ; nWEr ; Addr[19] ; PHI0 ; C25M ; 1.000 ; -2.770 ; 6.158 ; +; -8.261 ; nWEr ; Addr[20] ; PHI0 ; C25M ; 1.000 ; -2.770 ; 6.158 ; +; -8.261 ; nWEr ; Addr[21] ; PHI0 ; C25M ; 1.000 ; -2.770 ; 6.158 ; +; -8.261 ; nWEr ; Addr[22] ; PHI0 ; C25M ; 1.000 ; -2.770 ; 6.158 ; +; -8.237 ; RAMSpecSELr ; SA[10]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.770 ; 6.134 ; +; -8.231 ; LS[9] ; IS.state_bit_1 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.898 ; +; -8.204 ; IS.state_bit_1 ; nRCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.871 ; +; -8.198 ; LS[11] ; IS.state_bit_1 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.865 ; +; -8.178 ; IS.state_bit_2 ; RCKE~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.845 ; +; -8.169 ; LS[9] ; IS.state_bit_0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.836 ; +; -8.169 ; RAMSpecSELr ; SBA[0]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.770 ; 6.066 ; +; -8.164 ; RAMSpecSELr ; SDOE ; PHI0 ; C25M ; 1.000 ; -2.770 ; 6.061 ; +; -8.162 ; LS[9] ; IS.state_bit_2 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.829 ; +; -8.159 ; IS.state_bit_0 ; SA[8]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.826 ; +; -8.143 ; PS[1] ; Addr[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.810 ; +; -8.143 ; PS[1] ; Addr[1] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.810 ; +; -8.143 ; PS[1] ; Addr[2] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.810 ; +; -8.143 ; PS[1] ; Addr[3] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.810 ; +; -8.143 ; PS[1] ; Addr[4] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.810 ; +; -8.143 ; PS[1] ; Addr[5] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.810 ; +; -8.143 ; PS[1] ; Addr[6] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.810 ; +; -8.143 ; PS[1] ; Addr[7] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.810 ; +; -8.136 ; LS[11] ; IS.state_bit_0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.803 ; +; -8.133 ; PS[0] ; RCKE~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.800 ; +; -8.130 ; LS[0] ; RCKE~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.797 ; +; -8.129 ; LS[11] ; IS.state_bit_2 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.796 ; +; -8.103 ; PS[3] ; Addr[23] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.770 ; +; -8.103 ; PS[3] ; Addr[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.770 ; +; -8.103 ; PS[3] ; Addr[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.770 ; +; -8.103 ; PS[3] ; Addr[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.770 ; +; -8.103 ; PS[3] ; Addr[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.770 ; +; -8.103 ; PS[3] ; Addr[20] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.770 ; +; -8.103 ; PS[3] ; Addr[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.770 ; +; -8.103 ; PS[3] ; Addr[22] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.770 ; +; -8.081 ; PS[3] ; SA[5]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.748 ; +; -8.080 ; PS[1] ; IS.state_bit_1 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.747 ; +; -8.064 ; IS.state_bit_0 ; SA[6]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.731 ; +; -8.061 ; IS.state_bit_0 ; SA[4]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.728 ; +; -8.044 ; RAMSpecSELr ; SA[2]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.770 ; 5.941 ; +; -8.022 ; LS[8] ; IS.state_bit_1 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.689 ; +; -7.969 ; PS[0] ; SA[5]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.636 ; +; -7.960 ; LS[8] ; IS.state_bit_0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.627 ; +; -7.956 ; IS.state_bit_0 ; SA[7]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.623 ; +; -7.953 ; LS[8] ; IS.state_bit_2 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.620 ; +; -7.945 ; IS.state_bit_0 ; nRCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.612 ; +; -7.905 ; PS[0] ; Addr[23] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.572 ; +; -7.905 ; PS[0] ; Addr[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.572 ; +; -7.905 ; PS[0] ; Addr[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.572 ; +; -7.905 ; PS[0] ; Addr[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.572 ; +; -7.905 ; PS[0] ; Addr[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.572 ; +; -7.905 ; PS[0] ; Addr[20] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.572 ; +; -7.905 ; PS[0] ; Addr[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.572 ; +; -7.905 ; PS[0] ; Addr[22] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.572 ; +; -7.882 ; nWEr ; Addr[0] ; PHI0 ; C25M ; 1.000 ; -2.770 ; 5.779 ; +; -7.882 ; nWEr ; Addr[1] ; PHI0 ; C25M ; 1.000 ; -2.770 ; 5.779 ; +; -7.882 ; nWEr ; Addr[2] ; PHI0 ; C25M ; 1.000 ; -2.770 ; 5.779 ; +; -7.882 ; nWEr ; Addr[3] ; PHI0 ; C25M ; 1.000 ; -2.770 ; 5.779 ; +; -7.882 ; nWEr ; Addr[4] ; PHI0 ; C25M ; 1.000 ; -2.770 ; 5.779 ; +; -7.882 ; nWEr ; Addr[5] ; PHI0 ; C25M ; 1.000 ; -2.770 ; 5.779 ; +; -7.882 ; nWEr ; Addr[6] ; PHI0 ; C25M ; 1.000 ; -2.770 ; 5.779 ; +; -7.882 ; nWEr ; Addr[7] ; PHI0 ; C25M ; 1.000 ; -2.770 ; 5.779 ; +; -7.878 ; RAMSpecSELr ; SBA[1]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.770 ; 5.775 ; +; -7.854 ; PS[1] ; SA[5]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.521 ; +; -7.844 ; REGEN ; Addr[23] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.511 ; +--------+----------------+----------------+--------------+-------------+--------------+------------+------------+ -+-------------------------------------------------------------------------------------------------------+ -; Setup: 'PHI0' ; -+-------+-----------+-------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+-------+-----------+-------------+--------------+-------------+--------------+------------+------------+ -; 0.212 ; REGEN ; RAMSpecSELr ; C25M ; PHI0 ; 1.000 ; 2.791 ; 3.246 ; -; 0.711 ; IOROMEN ; ROMSpecRDr ; C25M ; PHI0 ; 1.000 ; 2.791 ; 2.747 ; -+-------+-----------+-------------+--------------+-------------+--------------+------------+------------+ ++--------------------------------------------------------------------------------------------------------+ +; Setup: 'PHI0' ; ++--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ +; -0.522 ; Addr[23] ; RAMSpecSELr ; C25M ; PHI0 ; 1.000 ; 2.770 ; 3.959 ; +; -0.319 ; REGEN ; RAMSpecSELr ; C25M ; PHI0 ; 1.000 ; 2.770 ; 3.756 ; +; 0.643 ; IOROMEN ; ROMSpecRDr ; C25M ; PHI0 ; 1.000 ; 2.770 ; 2.794 ; ++--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ +--------------------------------------------------------------------------------------------------------+ @@ -285,8 +286,9 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ -; -0.265 ; IOROMEN ; ROMSpecRDr ; C25M ; PHI0 ; 0.000 ; 2.791 ; 2.747 ; -; 0.234 ; REGEN ; RAMSpecSELr ; C25M ; PHI0 ; 0.000 ; 2.791 ; 3.246 ; +; -0.197 ; IOROMEN ; ROMSpecRDr ; C25M ; PHI0 ; 0.000 ; 2.770 ; 2.794 ; +; 0.765 ; REGEN ; RAMSpecSELr ; C25M ; PHI0 ; 0.000 ; 2.770 ; 3.756 ; +; 0.968 ; Addr[23] ; RAMSpecSELr ; C25M ; PHI0 ; 0.000 ; 2.770 ; 3.959 ; +--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ @@ -295,106 +297,106 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+----------------+----------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +-------+----------------+----------------+--------------+-------------+--------------+------------+------------+ -; 1.374 ; WRD[6] ; WRD[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.595 ; -; 1.375 ; WRD[7] ; WRD[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.596 ; -; 1.396 ; nRESr0 ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 1.617 ; -; 1.518 ; PHI0 ; PHI0r1 ; PHI0 ; C25M ; 0.000 ; 3.458 ; 5.197 ; -; 1.653 ; WRD[0] ; WRD[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.874 ; -; 1.653 ; WRD[5] ; WRD[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.874 ; -; 1.654 ; WRD[2] ; WRD[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.875 ; -; 1.657 ; nRESout~reg0 ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 1.878 ; -; 1.693 ; PS[1] ; PS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.914 ; -; 1.768 ; WRD[2] ; WRD[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.989 ; -; 1.783 ; PHI0r1 ; PHI0r2 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.004 ; -; 1.827 ; WRD[5] ; WRD[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.048 ; -; 1.836 ; WRD[3] ; WRD[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.057 ; -; 1.837 ; WRD[1] ; WRD[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.058 ; -; 1.942 ; PS[2] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.163 ; -; 2.004 ; IS.state_bit_0 ; IS.state_bit_0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.225 ; -; 2.018 ; PHI0 ; PHI0r1 ; PHI0 ; C25M ; -0.500 ; 3.458 ; 5.197 ; -; 2.084 ; LS[13] ; LS[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.305 ; -; 2.107 ; LS[7] ; LS[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.328 ; -; 2.117 ; Addr[10] ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; +; 1.385 ; WRD[5] ; WRD[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.606 ; +; 1.402 ; WRD[6] ; WRD[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.623 ; +; 1.402 ; WRD[7] ; WRD[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.623 ; +; 1.412 ; WRD[1] ; WRD[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.633 ; +; 1.414 ; nRESf[1] ; nRESf[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.635 ; +; 1.421 ; nRESf[2] ; nRESf[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.642 ; +; 1.665 ; nRESf[3] ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 1.886 ; +; 1.670 ; PHI0 ; PHI0r1 ; PHI0 ; C25M ; 0.000 ; 3.458 ; 5.349 ; +; 1.738 ; IS.state_bit_2 ; MOSIOE ; C25M ; C25M ; 0.000 ; 0.000 ; 1.959 ; +; 1.849 ; WRD[2] ; WRD[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.070 ; +; 1.871 ; WRD[0] ; WRD[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.092 ; +; 1.907 ; nRESout~reg0 ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.128 ; +; 1.918 ; Bank ; Bank ; C25M ; C25M ; 0.000 ; 0.000 ; 2.139 ; +; 1.939 ; nRESf[2] ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 2.160 ; +; 1.946 ; Addr[7] ; AddrIncM ; C25M ; C25M ; 0.000 ; 0.000 ; 2.167 ; +; 1.961 ; IS.state_bit_0 ; IS.state_bit_0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.182 ; +; 2.011 ; PS[2] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.232 ; +; 2.111 ; WRD[2] ; WRD[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.332 ; ; 2.117 ; Addr[1] ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; ; 2.117 ; Addr[2] ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; -; 2.117 ; Addr[9] ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; -; 2.121 ; WRD[3] ; WRD[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.342 ; -; 2.124 ; Addr[16] ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.345 ; -; 2.125 ; Addr[8] ; Addr[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.346 ; -; 2.126 ; Bank ; Bank ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ; -; 2.126 ; LS[4] ; LS[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ; -; 2.126 ; Addr[15] ; Addr[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ; -; 2.126 ; Addr[17] ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ; -; 2.126 ; Addr[18] ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ; -; 2.127 ; Addr[23] ; Addr[23] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.348 ; -; 2.131 ; PS[2] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.352 ; -; 2.135 ; Addr[7] ; Addr[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.356 ; -; 2.137 ; PS[3] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.358 ; -; 2.142 ; Addr[0] ; Addr[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.363 ; -; 2.144 ; LS[6] ; LS[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.365 ; -; 2.144 ; LS[8] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.365 ; -; 2.144 ; LS[9] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.365 ; -; 2.144 ; LS[0] ; LS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.365 ; -; 2.147 ; LS[0] ; LS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.368 ; -; 2.165 ; PS[1] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.386 ; -; 2.212 ; Addr[19] ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.433 ; -; 2.213 ; WRD[4] ; WRD[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.434 ; +; 2.117 ; Addr[17] ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; +; 2.117 ; Addr[18] ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; +; 2.118 ; Addr[15] ; Addr[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.339 ; +; 2.124 ; LS[7] ; LS[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.345 ; +; 2.125 ; Addr[16] ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.346 ; +; 2.126 ; Addr[23] ; Addr[23] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ; +; 2.126 ; LS[6] ; LS[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ; +; 2.126 ; LS[9] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ; +; 2.127 ; LS[4] ; LS[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.348 ; +; 2.128 ; nRESf[0] ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 2.349 ; +; 2.134 ; LS[8] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.355 ; +; 2.140 ; Addr[0] ; Addr[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.361 ; +; 2.143 ; Addr[9] ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.364 ; +; 2.145 ; Addr[10] ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.366 ; +; 2.154 ; Addr[7] ; Addr[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.375 ; +; 2.170 ; PHI0 ; PHI0r1 ; PHI0 ; C25M ; -0.500 ; 3.458 ; 5.349 ; +; 2.183 ; PS[0] ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.404 ; +; 2.188 ; PS[0] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.409 ; +; 2.196 ; PS[0] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.417 ; +; 2.221 ; Addr[3] ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.442 ; +; 2.222 ; Addr[19] ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.443 ; +; 2.228 ; AddrIncH ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.449 ; +; 2.230 ; Addr[5] ; Addr[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.451 ; ; 2.230 ; Addr[21] ; Addr[21] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.451 ; +; 2.231 ; Addr[4] ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; +; 2.231 ; Addr[6] ; Addr[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; ; 2.231 ; Addr[20] ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; ; 2.231 ; Addr[22] ; Addr[22] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; -; 2.232 ; Addr[11] ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.453 ; +; 2.232 ; LS[10] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.453 ; ; 2.232 ; LS[5] ; LS[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.453 ; -; 2.241 ; Addr[3] ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.462 ; -; 2.248 ; LS[12] ; LS[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.469 ; +; 2.241 ; Addr[11] ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.462 ; +; 2.248 ; LS[3] ; LS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.469 ; ; 2.249 ; Addr[14] ; Addr[14] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.470 ; -; 2.249 ; Addr[5] ; Addr[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.470 ; -; 2.250 ; LS[11] ; LS[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.471 ; -; 2.251 ; LS[2] ; LS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.472 ; -; 2.251 ; Addr[6] ; Addr[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.472 ; -; 2.252 ; LS[1] ; LS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.473 ; -; 2.253 ; LS[10] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.474 ; +; 2.249 ; LS[13] ; LS[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.470 ; +; 2.253 ; nRESf[1] ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 2.474 ; +; 2.253 ; WRD[1] ; WRD[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.474 ; +; 2.259 ; LS[2] ; LS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.480 ; +; 2.260 ; LS[12] ; LS[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.481 ; ; 2.261 ; Addr[12] ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.482 ; ; 2.261 ; Addr[13] ; Addr[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.482 ; -; 2.269 ; WRD[4] ; WRD[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.490 ; -; 2.280 ; PS[0] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.501 ; -; 2.325 ; IS.state_bit_1 ; IS.state_bit_0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.546 ; -; 2.350 ; WRD[0] ; WRD[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.571 ; -; 2.529 ; Addr[12] ; RDD[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.750 ; -; 2.545 ; PS[0] ; PS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.766 ; -; 2.551 ; Addr[4] ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.772 ; -; 2.621 ; PS[0] ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.842 ; -; 2.627 ; LS[3] ; LS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.848 ; -; 2.675 ; WRD[1] ; WRD[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.896 ; -; 2.701 ; PS[2] ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.922 ; -; 2.751 ; IS.state_bit_1 ; IS.state_bit_1 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.972 ; -; 2.848 ; PS[0] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.069 ; -; 2.939 ; LS[7] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.160 ; -; 2.949 ; Addr[9] ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; -; 2.949 ; Addr[10] ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; +; 2.262 ; LS[1] ; LS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.483 ; +; 2.262 ; LS[11] ; LS[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.483 ; +; 2.298 ; WRD[3] ; WRD[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.519 ; +; 2.313 ; IS.state_bit_2 ; FCKOE ; C25M ; C25M ; 0.000 ; 0.000 ; 2.534 ; +; 2.334 ; PS[3] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.555 ; +; 2.337 ; PS[3] ; SA[10]~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.558 ; +; 2.342 ; PS[3] ; SBA[0]~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.563 ; +; 2.342 ; PS[2] ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.563 ; +; 2.372 ; LS[0] ; LS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.593 ; +; 2.410 ; nRESf[0] ; nRESf[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.631 ; +; 2.443 ; PHI0r1 ; PHI0r2 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.664 ; +; 2.460 ; WRD[4] ; WRD[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.681 ; +; 2.636 ; WRD[5] ; WRD[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.857 ; +; 2.707 ; WRD[0] ; WRD[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.928 ; +; 2.712 ; IS.state_bit_1 ; IS.state_bit_0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.933 ; +; 2.817 ; Addr[21] ; SA[11]~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.038 ; +; 2.835 ; Addr[0] ; RDD[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.056 ; +; 2.870 ; Addr[0] ; DQML~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.091 ; +; 2.885 ; PS[2] ; SBA[0]~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.106 ; +; 2.915 ; Addr[18] ; RDD[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.136 ; +; 2.939 ; IS.state_bit_2 ; IS.state_bit_2 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.160 ; +; 2.949 ; IS.state_bit_0 ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; ; 2.949 ; Addr[1] ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; ; 2.949 ; Addr[2] ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; -; 2.956 ; Addr[16] ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.177 ; -; 2.957 ; Addr[8] ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.178 ; -; 2.958 ; LS[4] ; LS[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.179 ; -; 2.958 ; Addr[17] ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.179 ; -; 2.958 ; Addr[18] ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.179 ; -; 2.964 ; PS[2] ; SA[5]~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.185 ; -; 2.974 ; Addr[0] ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.195 ; -; 2.976 ; LS[9] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.197 ; -; 2.976 ; LS[8] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.197 ; -; 3.050 ; LS[7] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.271 ; -; 3.060 ; Addr[10] ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ; +; 2.949 ; Addr[17] ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; +; 2.949 ; Addr[18] ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; +; 2.956 ; LS[7] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.177 ; +; 2.957 ; Addr[16] ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.178 ; +; 2.958 ; LS[9] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.179 ; +; 2.958 ; IS.state_bit_0 ; FCKOE ; C25M ; C25M ; 0.000 ; 0.000 ; 3.179 ; +; 2.959 ; LS[4] ; LS[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.180 ; +; 2.966 ; LS[8] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.187 ; +; 2.972 ; Addr[0] ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.193 ; +; 2.975 ; Addr[9] ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.196 ; +; 2.977 ; Addr[10] ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.198 ; ; 3.060 ; Addr[2] ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ; -; 3.060 ; Addr[9] ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ; +; 3.060 ; Addr[18] ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ; ; 3.060 ; Addr[1] ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ; -; 3.067 ; Addr[16] ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.288 ; -; 3.068 ; Addr[8] ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.289 ; -; 3.069 ; LS[4] ; LS[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.290 ; -; 3.069 ; Addr[18] ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.290 ; -; 3.069 ; Addr[17] ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.290 ; -; 3.085 ; Addr[0] ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.306 ; -; 3.087 ; LS[9] ; LS[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.308 ; -; 3.087 ; LS[8] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.308 ; +; 3.060 ; Addr[17] ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ; +; 3.061 ; IS.state_bit_1 ; FCKOE ; C25M ; C25M ; 0.000 ; 0.000 ; 3.282 ; +-------+----------------+----------------+--------------+-------------+--------------+------------+------------+ @@ -403,35 +405,35 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +--------+-----------+----------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+-----------+----------+--------------+-------------+--------------+------------+------------+ -; -4.404 ; nRESr ; Addr[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.071 ; -; -4.404 ; nRESr ; Addr[23] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.071 ; -; -4.404 ; nRESr ; Addr[10] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.071 ; -; -4.404 ; nRESr ; Addr[1] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.071 ; -; -4.404 ; nRESr ; Addr[11] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.071 ; -; -4.404 ; nRESr ; Addr[2] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.071 ; -; -4.404 ; nRESr ; Addr[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.071 ; -; -4.404 ; nRESr ; Bank ; C25M ; C25M ; 1.000 ; 0.000 ; 5.071 ; -; -4.404 ; nRESr ; Addr[3] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.071 ; -; -4.404 ; nRESr ; Addr[13] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.071 ; -; -4.404 ; nRESr ; Addr[4] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.071 ; -; -4.404 ; nRESr ; Addr[14] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.071 ; -; -4.404 ; nRESr ; Addr[5] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.071 ; -; -4.404 ; nRESr ; Addr[15] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.071 ; -; -4.404 ; nRESr ; Addr[6] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.071 ; -; -4.404 ; nRESr ; Addr[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.071 ; -; -4.404 ; nRESr ; Addr[7] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.071 ; -; -4.404 ; nRESr ; Addr[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.071 ; -; -4.404 ; nRESr ; Addr[8] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.071 ; -; -4.404 ; nRESr ; Addr[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.071 ; -; -4.404 ; nRESr ; Addr[9] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.071 ; -; -4.404 ; nRESr ; Addr[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.071 ; -; -4.404 ; nRESr ; Addr[20] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.071 ; -; -4.404 ; nRESr ; Addr[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.071 ; -; -4.404 ; nRESr ; Addr[22] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.071 ; -; -4.404 ; nRESr ; REGEN ; C25M ; C25M ; 1.000 ; 0.000 ; 5.071 ; -; -4.404 ; nRESr ; AddrIncH ; C25M ; C25M ; 1.000 ; 0.000 ; 5.071 ; -; -4.404 ; nRESr ; AddrIncM ; C25M ; C25M ; 1.000 ; 0.000 ; 5.071 ; -; -4.404 ; nRESr ; AddrIncL ; C25M ; C25M ; 1.000 ; 0.000 ; 5.071 ; +; -4.399 ; nRESr ; Addr[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.066 ; +; -4.399 ; nRESr ; Addr[23] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.066 ; +; -4.399 ; nRESr ; Addr[10] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.066 ; +; -4.399 ; nRESr ; Addr[1] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.066 ; +; -4.399 ; nRESr ; Addr[11] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.066 ; +; -4.399 ; nRESr ; Addr[2] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.066 ; +; -4.399 ; nRESr ; Addr[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.066 ; +; -4.399 ; nRESr ; Bank ; C25M ; C25M ; 1.000 ; 0.000 ; 5.066 ; +; -4.399 ; nRESr ; Addr[3] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.066 ; +; -4.399 ; nRESr ; Addr[13] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.066 ; +; -4.399 ; nRESr ; Addr[4] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.066 ; +; -4.399 ; nRESr ; Addr[14] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.066 ; +; -4.399 ; nRESr ; Addr[5] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.066 ; +; -4.399 ; nRESr ; Addr[15] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.066 ; +; -4.399 ; nRESr ; Addr[6] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.066 ; +; -4.399 ; nRESr ; Addr[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.066 ; +; -4.399 ; nRESr ; Addr[7] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.066 ; +; -4.399 ; nRESr ; Addr[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.066 ; +; -4.399 ; nRESr ; Addr[8] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.066 ; +; -4.399 ; nRESr ; Addr[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.066 ; +; -4.399 ; nRESr ; Addr[9] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.066 ; +; -4.399 ; nRESr ; Addr[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.066 ; +; -4.399 ; nRESr ; Addr[20] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.066 ; +; -4.399 ; nRESr ; Addr[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.066 ; +; -4.399 ; nRESr ; Addr[22] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.066 ; +; -4.399 ; nRESr ; REGEN ; C25M ; C25M ; 1.000 ; 0.000 ; 5.066 ; +; -4.399 ; nRESr ; AddrIncH ; C25M ; C25M ; 1.000 ; 0.000 ; 5.066 ; +; -4.399 ; nRESr ; AddrIncM ; C25M ; C25M ; 1.000 ; 0.000 ; 5.066 ; +; -4.399 ; nRESr ; AddrIncL ; C25M ; C25M ; 1.000 ; 0.000 ; 5.066 ; +--------+-----------+----------+--------------+-------------+--------------+------------+------------+ @@ -440,35 +442,35 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+-----------+----------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +-------+-----------+----------+--------------+-------------+--------------+------------+------------+ -; 4.850 ; nRESr ; Addr[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.071 ; -; 4.850 ; nRESr ; Addr[23] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.071 ; -; 4.850 ; nRESr ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.071 ; -; 4.850 ; nRESr ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.071 ; -; 4.850 ; nRESr ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.071 ; -; 4.850 ; nRESr ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.071 ; -; 4.850 ; nRESr ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.071 ; -; 4.850 ; nRESr ; Bank ; C25M ; C25M ; 0.000 ; 0.000 ; 5.071 ; -; 4.850 ; nRESr ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.071 ; -; 4.850 ; nRESr ; Addr[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.071 ; -; 4.850 ; nRESr ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.071 ; -; 4.850 ; nRESr ; Addr[14] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.071 ; -; 4.850 ; nRESr ; Addr[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.071 ; -; 4.850 ; nRESr ; Addr[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.071 ; -; 4.850 ; nRESr ; Addr[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.071 ; -; 4.850 ; nRESr ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.071 ; -; 4.850 ; nRESr ; Addr[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.071 ; -; 4.850 ; nRESr ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.071 ; -; 4.850 ; nRESr ; Addr[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.071 ; -; 4.850 ; nRESr ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.071 ; -; 4.850 ; nRESr ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.071 ; -; 4.850 ; nRESr ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.071 ; -; 4.850 ; nRESr ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.071 ; -; 4.850 ; nRESr ; Addr[21] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.071 ; -; 4.850 ; nRESr ; Addr[22] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.071 ; -; 4.850 ; nRESr ; REGEN ; C25M ; C25M ; 0.000 ; 0.000 ; 5.071 ; -; 4.850 ; nRESr ; AddrIncH ; C25M ; C25M ; 0.000 ; 0.000 ; 5.071 ; -; 4.850 ; nRESr ; AddrIncM ; C25M ; C25M ; 0.000 ; 0.000 ; 5.071 ; -; 4.850 ; nRESr ; AddrIncL ; C25M ; C25M ; 0.000 ; 0.000 ; 5.071 ; +; 4.845 ; nRESr ; Addr[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.066 ; +; 4.845 ; nRESr ; Addr[23] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.066 ; +; 4.845 ; nRESr ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.066 ; +; 4.845 ; nRESr ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.066 ; +; 4.845 ; nRESr ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.066 ; +; 4.845 ; nRESr ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.066 ; +; 4.845 ; nRESr ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.066 ; +; 4.845 ; nRESr ; Bank ; C25M ; C25M ; 0.000 ; 0.000 ; 5.066 ; +; 4.845 ; nRESr ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.066 ; +; 4.845 ; nRESr ; Addr[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.066 ; +; 4.845 ; nRESr ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.066 ; +; 4.845 ; nRESr ; Addr[14] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.066 ; +; 4.845 ; nRESr ; Addr[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.066 ; +; 4.845 ; nRESr ; Addr[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.066 ; +; 4.845 ; nRESr ; Addr[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.066 ; +; 4.845 ; nRESr ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.066 ; +; 4.845 ; nRESr ; Addr[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.066 ; +; 4.845 ; nRESr ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.066 ; +; 4.845 ; nRESr ; Addr[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.066 ; +; 4.845 ; nRESr ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.066 ; +; 4.845 ; nRESr ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.066 ; +; 4.845 ; nRESr ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.066 ; +; 4.845 ; nRESr ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.066 ; +; 4.845 ; nRESr ; Addr[21] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.066 ; +; 4.845 ; nRESr ; Addr[22] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.066 ; +; 4.845 ; nRESr ; REGEN ; C25M ; C25M ; 0.000 ; 0.000 ; 5.066 ; +; 4.845 ; nRESr ; AddrIncH ; C25M ; C25M ; 0.000 ; 0.000 ; 5.066 ; +; 4.845 ; nRESr ; AddrIncM ; C25M ; C25M ; 0.000 ; 0.000 ; 5.066 ; +; 4.845 ; nRESr ; AddrIncL ; C25M ; C25M ; 0.000 ; 0.000 ; 5.066 ; +-------+-----------+----------+--------------+-------------+--------------+------------+------------+ @@ -608,62 +610,68 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-----------+------------+--------+--------+------------+-----------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+--------+--------+------------+-----------------+ -; MISO ; C25M ; 4.861 ; 4.861 ; Rise ; C25M ; -; MOSI ; C25M ; 5.054 ; 5.054 ; Rise ; C25M ; -; PHI0 ; C25M ; 2.072 ; 2.072 ; Rise ; C25M ; -; RA[*] ; C25M ; 13.938 ; 13.938 ; Rise ; C25M ; -; RA[0] ; C25M ; 8.513 ; 8.513 ; Rise ; C25M ; -; RA[1] ; C25M ; 8.082 ; 8.082 ; Rise ; C25M ; -; RA[2] ; C25M ; 8.927 ; 8.927 ; Rise ; C25M ; -; RA[3] ; C25M ; 9.459 ; 9.459 ; Rise ; C25M ; -; RA[4] ; C25M ; 6.718 ; 6.718 ; Rise ; C25M ; -; RA[5] ; C25M ; 8.293 ; 8.293 ; Rise ; C25M ; -; RA[6] ; C25M ; 6.561 ; 6.561 ; Rise ; C25M ; -; RA[7] ; C25M ; 11.859 ; 11.859 ; Rise ; C25M ; -; RA[8] ; C25M ; 12.000 ; 12.000 ; Rise ; C25M ; -; RA[9] ; C25M ; 12.068 ; 12.068 ; Rise ; C25M ; -; RA[10] ; C25M ; 13.578 ; 13.578 ; Rise ; C25M ; -; RA[11] ; C25M ; 13.170 ; 13.170 ; Rise ; C25M ; -; RA[12] ; C25M ; 13.525 ; 13.525 ; Rise ; C25M ; -; RA[13] ; C25M ; 13.254 ; 13.254 ; Rise ; C25M ; -; RA[14] ; C25M ; 13.903 ; 13.903 ; Rise ; C25M ; -; RA[15] ; C25M ; 13.938 ; 13.938 ; Rise ; C25M ; -; RD[*] ; C25M ; 6.255 ; 6.255 ; Rise ; C25M ; -; RD[0] ; C25M ; 5.390 ; 5.390 ; Rise ; C25M ; -; RD[1] ; C25M ; 5.017 ; 5.017 ; Rise ; C25M ; -; RD[2] ; C25M ; 4.088 ; 4.088 ; Rise ; C25M ; -; RD[3] ; C25M ; 4.968 ; 4.968 ; Rise ; C25M ; -; RD[4] ; C25M ; 4.673 ; 4.673 ; Rise ; C25M ; -; RD[5] ; C25M ; 5.287 ; 5.287 ; Rise ; C25M ; -; RD[6] ; C25M ; 3.485 ; 3.485 ; Rise ; C25M ; -; RD[7] ; C25M ; 6.255 ; 6.255 ; Rise ; C25M ; -; SD[*] ; C25M ; 7.093 ; 7.093 ; Rise ; C25M ; -; SD[0] ; C25M ; 5.171 ; 5.171 ; Rise ; C25M ; -; SD[1] ; C25M ; 4.574 ; 4.574 ; Rise ; C25M ; -; SD[2] ; C25M ; 3.868 ; 3.868 ; Rise ; C25M ; -; SD[3] ; C25M ; 7.093 ; 7.093 ; Rise ; C25M ; -; SD[4] ; C25M ; 5.421 ; 5.421 ; Rise ; C25M ; -; SD[5] ; C25M ; 4.486 ; 4.486 ; Rise ; C25M ; -; SD[6] ; C25M ; 5.447 ; 5.447 ; Rise ; C25M ; -; SD[7] ; C25M ; 4.770 ; 4.770 ; Rise ; C25M ; -; nDEVSEL ; C25M ; 9.132 ; 9.132 ; Rise ; C25M ; -; nIOSEL ; C25M ; 7.291 ; 7.291 ; Rise ; C25M ; -; nRES ; C25M ; 3.835 ; 3.835 ; Rise ; C25M ; -; RA[*] ; PHI0 ; 5.752 ; 5.752 ; Rise ; PHI0 ; -; RA[0] ; PHI0 ; 2.416 ; 2.416 ; Rise ; PHI0 ; -; RA[1] ; PHI0 ; 1.738 ; 1.738 ; Rise ; PHI0 ; -; RA[2] ; PHI0 ; 2.742 ; 2.742 ; Rise ; PHI0 ; -; RA[3] ; PHI0 ; 3.681 ; 3.681 ; Rise ; PHI0 ; -; RA[7] ; PHI0 ; 3.673 ; 3.673 ; Rise ; PHI0 ; -; RA[8] ; PHI0 ; 3.814 ; 3.814 ; Rise ; PHI0 ; -; RA[9] ; PHI0 ; 3.882 ; 3.882 ; Rise ; PHI0 ; -; RA[10] ; PHI0 ; 5.392 ; 5.392 ; Rise ; PHI0 ; -; RA[11] ; PHI0 ; 4.984 ; 4.984 ; Rise ; PHI0 ; -; RA[12] ; PHI0 ; 5.339 ; 5.339 ; Rise ; PHI0 ; -; RA[13] ; PHI0 ; 5.068 ; 5.068 ; Rise ; PHI0 ; -; RA[14] ; PHI0 ; 5.717 ; 5.717 ; Rise ; PHI0 ; -; RA[15] ; PHI0 ; 5.752 ; 5.752 ; Rise ; PHI0 ; -; nWE ; PHI0 ; 1.031 ; 1.031 ; Rise ; PHI0 ; +; MISO ; C25M ; 3.647 ; 3.647 ; Rise ; C25M ; +; MOSI ; C25M ; 3.258 ; 3.258 ; Rise ; C25M ; +; PHI0 ; C25M ; 2.224 ; 2.224 ; Rise ; C25M ; +; RA[*] ; C25M ; 14.550 ; 14.550 ; Rise ; C25M ; +; RA[0] ; C25M ; 9.707 ; 9.707 ; Rise ; C25M ; +; RA[1] ; C25M ; 9.383 ; 9.383 ; Rise ; C25M ; +; RA[2] ; C25M ; 9.220 ; 9.220 ; Rise ; C25M ; +; RA[3] ; C25M ; 9.411 ; 9.411 ; Rise ; C25M ; +; RA[4] ; C25M ; 6.312 ; 6.312 ; Rise ; C25M ; +; RA[5] ; C25M ; 6.723 ; 6.723 ; Rise ; C25M ; +; RA[6] ; C25M ; 6.226 ; 6.226 ; Rise ; C25M ; +; RA[7] ; C25M ; 9.810 ; 9.810 ; Rise ; C25M ; +; RA[8] ; C25M ; 13.947 ; 13.947 ; Rise ; C25M ; +; RA[9] ; C25M ; 14.550 ; 14.550 ; Rise ; C25M ; +; RA[10] ; C25M ; 13.252 ; 13.252 ; Rise ; C25M ; +; RA[11] ; C25M ; 13.106 ; 13.106 ; Rise ; C25M ; +; RA[12] ; C25M ; 12.557 ; 12.557 ; Rise ; C25M ; +; RA[13] ; C25M ; 12.912 ; 12.912 ; Rise ; C25M ; +; RA[14] ; C25M ; 12.536 ; 12.536 ; Rise ; C25M ; +; RA[15] ; C25M ; 12.221 ; 12.221 ; Rise ; C25M ; +; RD[*] ; C25M ; 5.373 ; 5.373 ; Rise ; C25M ; +; RD[0] ; C25M ; 4.708 ; 4.708 ; Rise ; C25M ; +; RD[1] ; C25M ; 4.030 ; 4.030 ; Rise ; C25M ; +; RD[2] ; C25M ; 3.966 ; 3.966 ; Rise ; C25M ; +; RD[3] ; C25M ; 4.000 ; 4.000 ; Rise ; C25M ; +; RD[4] ; C25M ; 4.128 ; 4.128 ; Rise ; C25M ; +; RD[5] ; C25M ; 4.589 ; 4.589 ; Rise ; C25M ; +; RD[6] ; C25M ; 4.796 ; 4.796 ; Rise ; C25M ; +; RD[7] ; C25M ; 5.373 ; 5.373 ; Rise ; C25M ; +; SD[*] ; C25M ; 5.245 ; 5.245 ; Rise ; C25M ; +; SD[0] ; C25M ; 5.245 ; 5.245 ; Rise ; C25M ; +; SD[1] ; C25M ; 3.881 ; 3.881 ; Rise ; C25M ; +; SD[2] ; C25M ; 5.072 ; 5.072 ; Rise ; C25M ; +; SD[3] ; C25M ; 4.744 ; 4.744 ; Rise ; C25M ; +; SD[4] ; C25M ; 3.461 ; 3.461 ; Rise ; C25M ; +; SD[5] ; C25M ; 3.317 ; 3.317 ; Rise ; C25M ; +; SD[6] ; C25M ; 4.210 ; 4.210 ; Rise ; C25M ; +; SD[7] ; C25M ; 3.715 ; 3.715 ; Rise ; C25M ; +; SetFW[*] ; C25M ; 8.003 ; 8.003 ; Rise ; C25M ; +; SetFW[0] ; C25M ; 4.445 ; 4.445 ; Rise ; C25M ; +; SetFW[1] ; C25M ; 8.003 ; 8.003 ; Rise ; C25M ; +; nDEVSEL ; C25M ; 8.537 ; 8.537 ; Rise ; C25M ; +; nIOSEL ; C25M ; 7.483 ; 7.483 ; Rise ; C25M ; +; nRES ; C25M ; 5.821 ; 5.821 ; Rise ; C25M ; +; RA[*] ; PHI0 ; 7.025 ; 7.025 ; Rise ; PHI0 ; +; RA[0] ; PHI0 ; 3.368 ; 3.368 ; Rise ; PHI0 ; +; RA[1] ; PHI0 ; 3.076 ; 3.076 ; Rise ; PHI0 ; +; RA[2] ; PHI0 ; 3.235 ; 3.235 ; Rise ; PHI0 ; +; RA[3] ; PHI0 ; 3.426 ; 3.426 ; Rise ; PHI0 ; +; RA[7] ; PHI0 ; 2.285 ; 2.285 ; Rise ; PHI0 ; +; RA[8] ; PHI0 ; 6.422 ; 6.422 ; Rise ; PHI0 ; +; RA[9] ; PHI0 ; 7.025 ; 7.025 ; Rise ; PHI0 ; +; RA[10] ; PHI0 ; 5.727 ; 5.727 ; Rise ; PHI0 ; +; RA[11] ; PHI0 ; 5.581 ; 5.581 ; Rise ; PHI0 ; +; RA[12] ; PHI0 ; 5.032 ; 5.032 ; Rise ; PHI0 ; +; RA[13] ; PHI0 ; 5.387 ; 5.387 ; Rise ; PHI0 ; +; RA[14] ; PHI0 ; 5.011 ; 5.011 ; Rise ; PHI0 ; +; RA[15] ; PHI0 ; 4.696 ; 4.696 ; Rise ; PHI0 ; +; SetFW[*] ; PHI0 ; 2.529 ; 2.529 ; Rise ; PHI0 ; +; SetFW[0] ; PHI0 ; 0.787 ; 0.787 ; Rise ; PHI0 ; +; SetFW[1] ; PHI0 ; 2.529 ; 2.529 ; Rise ; PHI0 ; +; nWE ; PHI0 ; 1.133 ; 1.133 ; Rise ; PHI0 ; +-----------+------------+--------+--------+------------+-----------------+ @@ -672,62 +680,68 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-----------+------------+--------+--------+------------+-----------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+--------+--------+------------+-----------------+ -; MISO ; C25M ; -4.307 ; -4.307 ; Rise ; C25M ; -; MOSI ; C25M ; -4.500 ; -4.500 ; Rise ; C25M ; -; PHI0 ; C25M ; -1.518 ; -1.518 ; Rise ; C25M ; -; RA[*] ; C25M ; -4.651 ; -4.651 ; Rise ; C25M ; -; RA[0] ; C25M ; -4.868 ; -4.868 ; Rise ; C25M ; -; RA[1] ; C25M ; -4.755 ; -4.755 ; Rise ; C25M ; -; RA[2] ; C25M ; -4.651 ; -4.651 ; Rise ; C25M ; -; RA[3] ; C25M ; -5.587 ; -5.587 ; Rise ; C25M ; -; RA[4] ; C25M ; -6.164 ; -6.164 ; Rise ; C25M ; -; RA[5] ; C25M ; -7.739 ; -7.739 ; Rise ; C25M ; -; RA[6] ; C25M ; -6.007 ; -6.007 ; Rise ; C25M ; -; RA[7] ; C25M ; -7.911 ; -7.911 ; Rise ; C25M ; -; RA[8] ; C25M ; -5.340 ; -5.340 ; Rise ; C25M ; -; RA[9] ; C25M ; -5.100 ; -5.100 ; Rise ; C25M ; -; RA[10] ; C25M ; -5.525 ; -5.525 ; Rise ; C25M ; -; RA[11] ; C25M ; -6.207 ; -6.207 ; Rise ; C25M ; -; RA[12] ; C25M ; -9.577 ; -9.577 ; Rise ; C25M ; -; RA[13] ; C25M ; -9.306 ; -9.306 ; Rise ; C25M ; -; RA[14] ; C25M ; -9.955 ; -9.955 ; Rise ; C25M ; -; RA[15] ; C25M ; -9.990 ; -9.990 ; Rise ; C25M ; -; RD[*] ; C25M ; -2.060 ; -2.060 ; Rise ; C25M ; -; RD[0] ; C25M ; -2.698 ; -2.698 ; Rise ; C25M ; -; RD[1] ; C25M ; -2.624 ; -2.624 ; Rise ; C25M ; -; RD[2] ; C25M ; -2.734 ; -2.734 ; Rise ; C25M ; -; RD[3] ; C25M ; -2.609 ; -2.609 ; Rise ; C25M ; -; RD[4] ; C25M ; -2.625 ; -2.625 ; Rise ; C25M ; -; RD[5] ; C25M ; -2.663 ; -2.663 ; Rise ; C25M ; -; RD[6] ; C25M ; -2.060 ; -2.060 ; Rise ; C25M ; -; RD[7] ; C25M ; -2.167 ; -2.167 ; Rise ; C25M ; -; SD[*] ; C25M ; -3.314 ; -3.314 ; Rise ; C25M ; -; SD[0] ; C25M ; -4.617 ; -4.617 ; Rise ; C25M ; -; SD[1] ; C25M ; -4.020 ; -4.020 ; Rise ; C25M ; -; SD[2] ; C25M ; -3.314 ; -3.314 ; Rise ; C25M ; -; SD[3] ; C25M ; -6.539 ; -6.539 ; Rise ; C25M ; -; SD[4] ; C25M ; -4.867 ; -4.867 ; Rise ; C25M ; -; SD[5] ; C25M ; -3.932 ; -3.932 ; Rise ; C25M ; -; SD[6] ; C25M ; -4.893 ; -4.893 ; Rise ; C25M ; -; SD[7] ; C25M ; -4.216 ; -4.216 ; Rise ; C25M ; -; nDEVSEL ; C25M ; -3.398 ; -3.398 ; Rise ; C25M ; -; nIOSEL ; C25M ; -6.712 ; -6.712 ; Rise ; C25M ; -; nRES ; C25M ; -3.281 ; -3.281 ; Rise ; C25M ; -; RA[*] ; PHI0 ; -1.124 ; -1.124 ; Rise ; PHI0 ; -; RA[0] ; PHI0 ; -1.862 ; -1.862 ; Rise ; PHI0 ; -; RA[1] ; PHI0 ; -1.184 ; -1.184 ; Rise ; PHI0 ; -; RA[2] ; PHI0 ; -2.188 ; -2.188 ; Rise ; PHI0 ; -; RA[3] ; PHI0 ; -3.127 ; -3.127 ; Rise ; PHI0 ; -; RA[7] ; PHI0 ; -3.119 ; -3.119 ; Rise ; PHI0 ; -; RA[8] ; PHI0 ; -1.376 ; -1.376 ; Rise ; PHI0 ; -; RA[9] ; PHI0 ; -1.444 ; -1.444 ; Rise ; PHI0 ; -; RA[10] ; PHI0 ; -2.954 ; -2.954 ; Rise ; PHI0 ; -; RA[11] ; PHI0 ; -1.124 ; -1.124 ; Rise ; PHI0 ; -; RA[12] ; PHI0 ; -3.628 ; -3.628 ; Rise ; PHI0 ; -; RA[13] ; PHI0 ; -3.357 ; -3.357 ; Rise ; PHI0 ; -; RA[14] ; PHI0 ; -4.006 ; -4.006 ; Rise ; PHI0 ; -; RA[15] ; PHI0 ; -4.041 ; -4.041 ; Rise ; PHI0 ; -; nWE ; PHI0 ; 0.091 ; 0.091 ; Rise ; PHI0 ; +; MISO ; C25M ; -3.093 ; -3.093 ; Rise ; C25M ; +; MOSI ; C25M ; -2.704 ; -2.704 ; Rise ; C25M ; +; PHI0 ; C25M ; -1.670 ; -1.670 ; Rise ; C25M ; +; RA[*] ; C25M ; -3.926 ; -3.926 ; Rise ; C25M ; +; RA[0] ; C25M ; -5.435 ; -5.435 ; Rise ; C25M ; +; RA[1] ; C25M ; -4.639 ; -4.639 ; Rise ; C25M ; +; RA[2] ; C25M ; -4.352 ; -4.352 ; Rise ; C25M ; +; RA[3] ; C25M ; -6.076 ; -6.076 ; Rise ; C25M ; +; RA[4] ; C25M ; -5.758 ; -5.758 ; Rise ; C25M ; +; RA[5] ; C25M ; -6.169 ; -6.169 ; Rise ; C25M ; +; RA[6] ; C25M ; -5.672 ; -5.672 ; Rise ; C25M ; +; RA[7] ; C25M ; -5.342 ; -5.342 ; Rise ; C25M ; +; RA[8] ; C25M ; -4.277 ; -4.277 ; Rise ; C25M ; +; RA[9] ; C25M ; -4.193 ; -4.193 ; Rise ; C25M ; +; RA[10] ; C25M ; -4.568 ; -4.568 ; Rise ; C25M ; +; RA[11] ; C25M ; -3.926 ; -3.926 ; Rise ; C25M ; +; RA[12] ; C25M ; -9.369 ; -9.369 ; Rise ; C25M ; +; RA[13] ; C25M ; -9.724 ; -9.724 ; Rise ; C25M ; +; RA[14] ; C25M ; -9.348 ; -9.348 ; Rise ; C25M ; +; RA[15] ; C25M ; -9.033 ; -9.033 ; Rise ; C25M ; +; RD[*] ; C25M ; -2.089 ; -2.089 ; Rise ; C25M ; +; RD[0] ; C25M ; -2.153 ; -2.153 ; Rise ; C25M ; +; RD[1] ; C25M ; -2.194 ; -2.194 ; Rise ; C25M ; +; RD[2] ; C25M ; -2.124 ; -2.124 ; Rise ; C25M ; +; RD[3] ; C25M ; -2.089 ; -2.089 ; Rise ; C25M ; +; RD[4] ; C25M ; -2.109 ; -2.109 ; Rise ; C25M ; +; RD[5] ; C25M ; -2.138 ; -2.138 ; Rise ; C25M ; +; RD[6] ; C25M ; -2.661 ; -2.661 ; Rise ; C25M ; +; RD[7] ; C25M ; -3.452 ; -3.452 ; Rise ; C25M ; +; SD[*] ; C25M ; -2.763 ; -2.763 ; Rise ; C25M ; +; SD[0] ; C25M ; -4.691 ; -4.691 ; Rise ; C25M ; +; SD[1] ; C25M ; -3.327 ; -3.327 ; Rise ; C25M ; +; SD[2] ; C25M ; -4.518 ; -4.518 ; Rise ; C25M ; +; SD[3] ; C25M ; -4.190 ; -4.190 ; Rise ; C25M ; +; SD[4] ; C25M ; -2.907 ; -2.907 ; Rise ; C25M ; +; SD[5] ; C25M ; -2.763 ; -2.763 ; Rise ; C25M ; +; SD[6] ; C25M ; -3.656 ; -3.656 ; Rise ; C25M ; +; SD[7] ; C25M ; -3.161 ; -3.161 ; Rise ; C25M ; +; SetFW[*] ; C25M ; -3.891 ; -3.891 ; Rise ; C25M ; +; SetFW[0] ; C25M ; -3.891 ; -3.891 ; Rise ; C25M ; +; SetFW[1] ; C25M ; -4.150 ; -4.150 ; Rise ; C25M ; +; nDEVSEL ; C25M ; -3.415 ; -3.415 ; Rise ; C25M ; +; nIOSEL ; C25M ; -6.363 ; -6.363 ; Rise ; C25M ; +; nRES ; C25M ; -5.267 ; -5.267 ; Rise ; C25M ; +; RA[*] ; PHI0 ; -0.733 ; -0.733 ; Rise ; PHI0 ; +; RA[0] ; PHI0 ; -2.814 ; -2.814 ; Rise ; PHI0 ; +; RA[1] ; PHI0 ; -2.522 ; -2.522 ; Rise ; PHI0 ; +; RA[2] ; PHI0 ; -2.681 ; -2.681 ; Rise ; PHI0 ; +; RA[3] ; PHI0 ; -2.872 ; -2.872 ; Rise ; PHI0 ; +; RA[7] ; PHI0 ; -1.731 ; -1.731 ; Rise ; PHI0 ; +; RA[8] ; PHI0 ; -2.126 ; -2.126 ; Rise ; PHI0 ; +; RA[9] ; PHI0 ; -2.729 ; -2.729 ; Rise ; PHI0 ; +; RA[10] ; PHI0 ; -1.431 ; -1.431 ; Rise ; PHI0 ; +; RA[11] ; PHI0 ; -0.804 ; -0.804 ; Rise ; PHI0 ; +; RA[12] ; PHI0 ; -1.069 ; -1.069 ; Rise ; PHI0 ; +; RA[13] ; PHI0 ; -1.424 ; -1.424 ; Rise ; PHI0 ; +; RA[14] ; PHI0 ; -1.048 ; -1.048 ; Rise ; PHI0 ; +; RA[15] ; PHI0 ; -0.733 ; -0.733 ; Rise ; PHI0 ; +; SetFW[*] ; PHI0 ; -0.233 ; -0.233 ; Rise ; PHI0 ; +; SetFW[0] ; PHI0 ; -0.233 ; -0.233 ; Rise ; PHI0 ; +; SetFW[1] ; PHI0 ; -1.975 ; -1.975 ; Rise ; PHI0 ; +; nWE ; PHI0 ; 0.253 ; 0.253 ; Rise ; PHI0 ; +-----------+------------+--------+--------+------------+-----------------+ @@ -736,55 +750,55 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-----------+------------+--------+--------+------------+-----------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+--------+--------+------------+-----------------+ -; DQMH ; C25M ; 8.306 ; 8.306 ; Rise ; C25M ; -; DQML ; C25M ; 8.935 ; 8.935 ; Rise ; C25M ; -; FCK ; C25M ; 8.986 ; 8.986 ; Rise ; C25M ; -; MOSI ; C25M ; 8.773 ; 8.773 ; Rise ; C25M ; -; RCKE ; C25M ; 9.311 ; 9.311 ; Rise ; C25M ; -; RD[*] ; C25M ; 9.599 ; 9.599 ; Rise ; C25M ; -; RD[0] ; C25M ; 8.289 ; 8.289 ; Rise ; C25M ; -; RD[1] ; C25M ; 8.191 ; 8.191 ; Rise ; C25M ; -; RD[2] ; C25M ; 8.316 ; 8.316 ; Rise ; C25M ; -; RD[3] ; C25M ; 9.599 ; 9.599 ; Rise ; C25M ; -; RD[4] ; C25M ; 8.790 ; 8.790 ; Rise ; C25M ; -; RD[5] ; C25M ; 8.643 ; 8.643 ; Rise ; C25M ; -; RD[6] ; C25M ; 8.747 ; 8.747 ; Rise ; C25M ; -; RD[7] ; C25M ; 8.857 ; 8.857 ; Rise ; C25M ; -; RDdir ; C25M ; 14.351 ; 14.351 ; Rise ; C25M ; -; SA[*] ; C25M ; 8.845 ; 8.845 ; Rise ; C25M ; -; SA[0] ; C25M ; 8.193 ; 8.193 ; Rise ; C25M ; -; SA[1] ; C25M ; 8.141 ; 8.141 ; Rise ; C25M ; -; SA[2] ; C25M ; 8.105 ; 8.105 ; Rise ; C25M ; -; SA[3] ; C25M ; 8.558 ; 8.558 ; Rise ; C25M ; -; SA[4] ; C25M ; 8.552 ; 8.552 ; Rise ; C25M ; -; SA[5] ; C25M ; 8.678 ; 8.678 ; Rise ; C25M ; -; SA[6] ; C25M ; 8.540 ; 8.540 ; Rise ; C25M ; -; SA[7] ; C25M ; 8.566 ; 8.566 ; Rise ; C25M ; -; SA[8] ; C25M ; 8.225 ; 8.225 ; Rise ; C25M ; -; SA[9] ; C25M ; 8.043 ; 8.043 ; Rise ; C25M ; -; SA[10] ; C25M ; 8.058 ; 8.058 ; Rise ; C25M ; -; SA[11] ; C25M ; 7.991 ; 7.991 ; Rise ; C25M ; -; SA[12] ; C25M ; 8.845 ; 8.845 ; Rise ; C25M ; -; SBA[*] ; C25M ; 8.866 ; 8.866 ; Rise ; C25M ; -; SBA[0] ; C25M ; 8.821 ; 8.821 ; Rise ; C25M ; -; SBA[1] ; C25M ; 8.866 ; 8.866 ; Rise ; C25M ; -; SD[*] ; C25M ; 8.494 ; 8.494 ; Rise ; C25M ; -; SD[0] ; C25M ; 8.488 ; 8.488 ; Rise ; C25M ; -; SD[1] ; C25M ; 8.053 ; 8.053 ; Rise ; C25M ; -; SD[2] ; C25M ; 8.494 ; 8.494 ; Rise ; C25M ; -; SD[3] ; C25M ; 7.584 ; 7.584 ; Rise ; C25M ; -; SD[4] ; C25M ; 8.442 ; 8.442 ; Rise ; C25M ; -; SD[5] ; C25M ; 7.562 ; 7.562 ; Rise ; C25M ; -; SD[6] ; C25M ; 8.445 ; 8.445 ; Rise ; C25M ; -; SD[7] ; C25M ; 6.950 ; 6.950 ; Rise ; C25M ; -; nCAS ; C25M ; 8.325 ; 8.325 ; Rise ; C25M ; -; nFCS ; C25M ; 8.074 ; 8.074 ; Rise ; C25M ; -; nRAS ; C25M ; 8.416 ; 8.416 ; Rise ; C25M ; -; nRCS ; C25M ; 10.070 ; 10.070 ; Rise ; C25M ; -; nRESout ; C25M ; 8.766 ; 8.766 ; Rise ; C25M ; -; nSWE ; C25M ; 9.380 ; 9.380 ; Rise ; C25M ; -; RDdir ; PHI0 ; 10.495 ; 10.495 ; Rise ; PHI0 ; -; RDdir ; PHI0 ; 10.495 ; 10.495 ; Fall ; PHI0 ; +; DQMH ; C25M ; 9.374 ; 9.374 ; Rise ; C25M ; +; DQML ; C25M ; 6.924 ; 6.924 ; Rise ; C25M ; +; FCK ; C25M ; 8.081 ; 8.081 ; Rise ; C25M ; +; MOSI ; C25M ; 8.903 ; 8.903 ; Rise ; C25M ; +; RCKE ; C25M ; 9.484 ; 9.484 ; Rise ; C25M ; +; RD[*] ; C25M ; 9.917 ; 9.917 ; Rise ; C25M ; +; RD[0] ; C25M ; 8.346 ; 8.346 ; Rise ; C25M ; +; RD[1] ; C25M ; 8.265 ; 8.265 ; Rise ; C25M ; +; RD[2] ; C25M ; 8.346 ; 8.346 ; Rise ; C25M ; +; RD[3] ; C25M ; 8.201 ; 8.201 ; Rise ; C25M ; +; RD[4] ; C25M ; 9.375 ; 9.375 ; Rise ; C25M ; +; RD[5] ; C25M ; 8.984 ; 8.984 ; Rise ; C25M ; +; RD[6] ; C25M ; 8.913 ; 8.913 ; Rise ; C25M ; +; RD[7] ; C25M ; 9.917 ; 9.917 ; Rise ; C25M ; +; RDdir ; C25M ; 16.629 ; 16.629 ; Rise ; C25M ; +; SA[*] ; C25M ; 9.394 ; 9.394 ; Rise ; C25M ; +; SA[0] ; C25M ; 8.606 ; 8.606 ; Rise ; C25M ; +; SA[1] ; C25M ; 8.584 ; 8.584 ; Rise ; C25M ; +; SA[2] ; C25M ; 8.798 ; 8.798 ; Rise ; C25M ; +; SA[3] ; C25M ; 8.651 ; 8.651 ; Rise ; C25M ; +; SA[4] ; C25M ; 8.242 ; 8.242 ; Rise ; C25M ; +; SA[5] ; C25M ; 8.647 ; 8.647 ; Rise ; C25M ; +; SA[6] ; C25M ; 8.669 ; 8.669 ; Rise ; C25M ; +; SA[7] ; C25M ; 8.116 ; 8.116 ; Rise ; C25M ; +; SA[8] ; C25M ; 8.234 ; 8.234 ; Rise ; C25M ; +; SA[9] ; C25M ; 7.567 ; 7.567 ; Rise ; C25M ; +; SA[10] ; C25M ; 9.394 ; 9.394 ; Rise ; C25M ; +; SA[11] ; C25M ; 8.116 ; 8.116 ; Rise ; C25M ; +; SA[12] ; C25M ; 7.570 ; 7.570 ; Rise ; C25M ; +; SBA[*] ; C25M ; 8.077 ; 8.077 ; Rise ; C25M ; +; SBA[0] ; C25M ; 8.073 ; 8.073 ; Rise ; C25M ; +; SBA[1] ; C25M ; 8.077 ; 8.077 ; Rise ; C25M ; +; SD[*] ; C25M ; 8.674 ; 8.674 ; Rise ; C25M ; +; SD[0] ; C25M ; 8.113 ; 8.113 ; Rise ; C25M ; +; SD[1] ; C25M ; 8.097 ; 8.097 ; Rise ; C25M ; +; SD[2] ; C25M ; 8.574 ; 8.574 ; Rise ; C25M ; +; SD[3] ; C25M ; 8.249 ; 8.249 ; Rise ; C25M ; +; SD[4] ; C25M ; 8.125 ; 8.125 ; Rise ; C25M ; +; SD[5] ; C25M ; 8.113 ; 8.113 ; Rise ; C25M ; +; SD[6] ; C25M ; 8.674 ; 8.674 ; Rise ; C25M ; +; SD[7] ; C25M ; 8.241 ; 8.241 ; Rise ; C25M ; +; nCAS ; C25M ; 8.329 ; 8.329 ; Rise ; C25M ; +; nFCS ; C25M ; 6.964 ; 6.964 ; Rise ; C25M ; +; nRAS ; C25M ; 8.349 ; 8.349 ; Rise ; C25M ; +; nRCS ; C25M ; 9.461 ; 9.461 ; Rise ; C25M ; +; nRESout ; C25M ; 8.159 ; 8.159 ; Rise ; C25M ; +; nSWE ; C25M ; 8.815 ; 8.815 ; Rise ; C25M ; +; RDdir ; PHI0 ; 11.026 ; 11.026 ; Rise ; PHI0 ; +; RDdir ; PHI0 ; 11.026 ; 11.026 ; Fall ; PHI0 ; +-----------+------------+--------+--------+------------+-----------------+ @@ -793,55 +807,55 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-----------+------------+--------+--------+------------+-----------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+--------+--------+------------+-----------------+ -; DQMH ; C25M ; 8.306 ; 8.306 ; Rise ; C25M ; -; DQML ; C25M ; 8.935 ; 8.935 ; Rise ; C25M ; -; FCK ; C25M ; 8.986 ; 8.986 ; Rise ; C25M ; -; MOSI ; C25M ; 8.773 ; 8.773 ; Rise ; C25M ; -; RCKE ; C25M ; 9.311 ; 9.311 ; Rise ; C25M ; -; RD[*] ; C25M ; 8.191 ; 8.191 ; Rise ; C25M ; -; RD[0] ; C25M ; 8.289 ; 8.289 ; Rise ; C25M ; -; RD[1] ; C25M ; 8.191 ; 8.191 ; Rise ; C25M ; -; RD[2] ; C25M ; 8.316 ; 8.316 ; Rise ; C25M ; -; RD[3] ; C25M ; 9.599 ; 9.599 ; Rise ; C25M ; -; RD[4] ; C25M ; 8.790 ; 8.790 ; Rise ; C25M ; -; RD[5] ; C25M ; 8.643 ; 8.643 ; Rise ; C25M ; -; RD[6] ; C25M ; 8.747 ; 8.747 ; Rise ; C25M ; -; RD[7] ; C25M ; 8.857 ; 8.857 ; Rise ; C25M ; -; RDdir ; C25M ; 9.747 ; 9.747 ; Rise ; C25M ; -; SA[*] ; C25M ; 7.991 ; 7.991 ; Rise ; C25M ; -; SA[0] ; C25M ; 8.193 ; 8.193 ; Rise ; C25M ; -; SA[1] ; C25M ; 8.141 ; 8.141 ; Rise ; C25M ; -; SA[2] ; C25M ; 8.105 ; 8.105 ; Rise ; C25M ; -; SA[3] ; C25M ; 8.558 ; 8.558 ; Rise ; C25M ; -; SA[4] ; C25M ; 8.552 ; 8.552 ; Rise ; C25M ; -; SA[5] ; C25M ; 8.678 ; 8.678 ; Rise ; C25M ; -; SA[6] ; C25M ; 8.540 ; 8.540 ; Rise ; C25M ; -; SA[7] ; C25M ; 8.566 ; 8.566 ; Rise ; C25M ; -; SA[8] ; C25M ; 8.225 ; 8.225 ; Rise ; C25M ; -; SA[9] ; C25M ; 8.043 ; 8.043 ; Rise ; C25M ; -; SA[10] ; C25M ; 8.058 ; 8.058 ; Rise ; C25M ; -; SA[11] ; C25M ; 7.991 ; 7.991 ; Rise ; C25M ; -; SA[12] ; C25M ; 8.845 ; 8.845 ; Rise ; C25M ; -; SBA[*] ; C25M ; 8.821 ; 8.821 ; Rise ; C25M ; -; SBA[0] ; C25M ; 8.821 ; 8.821 ; Rise ; C25M ; -; SBA[1] ; C25M ; 8.866 ; 8.866 ; Rise ; C25M ; -; SD[*] ; C25M ; 6.950 ; 6.950 ; Rise ; C25M ; -; SD[0] ; C25M ; 8.488 ; 8.488 ; Rise ; C25M ; -; SD[1] ; C25M ; 8.053 ; 8.053 ; Rise ; C25M ; -; SD[2] ; C25M ; 8.494 ; 8.494 ; Rise ; C25M ; -; SD[3] ; C25M ; 7.584 ; 7.584 ; Rise ; C25M ; -; SD[4] ; C25M ; 8.442 ; 8.442 ; Rise ; C25M ; -; SD[5] ; C25M ; 7.562 ; 7.562 ; Rise ; C25M ; -; SD[6] ; C25M ; 8.445 ; 8.445 ; Rise ; C25M ; -; SD[7] ; C25M ; 6.950 ; 6.950 ; Rise ; C25M ; -; nCAS ; C25M ; 8.325 ; 8.325 ; Rise ; C25M ; -; nFCS ; C25M ; 8.074 ; 8.074 ; Rise ; C25M ; -; nRAS ; C25M ; 8.416 ; 8.416 ; Rise ; C25M ; -; nRCS ; C25M ; 10.070 ; 10.070 ; Rise ; C25M ; -; nRESout ; C25M ; 8.766 ; 8.766 ; Rise ; C25M ; -; nSWE ; C25M ; 9.380 ; 9.380 ; Rise ; C25M ; -; RDdir ; PHI0 ; 10.495 ; 10.495 ; Rise ; PHI0 ; -; RDdir ; PHI0 ; 10.495 ; 10.495 ; Fall ; PHI0 ; +; DQMH ; C25M ; 9.374 ; 9.374 ; Rise ; C25M ; +; DQML ; C25M ; 6.924 ; 6.924 ; Rise ; C25M ; +; FCK ; C25M ; 8.081 ; 8.081 ; Rise ; C25M ; +; MOSI ; C25M ; 8.903 ; 8.903 ; Rise ; C25M ; +; RCKE ; C25M ; 9.484 ; 9.484 ; Rise ; C25M ; +; RD[*] ; C25M ; 8.201 ; 8.201 ; Rise ; C25M ; +; RD[0] ; C25M ; 8.346 ; 8.346 ; Rise ; C25M ; +; RD[1] ; C25M ; 8.265 ; 8.265 ; Rise ; C25M ; +; RD[2] ; C25M ; 8.346 ; 8.346 ; Rise ; C25M ; +; RD[3] ; C25M ; 8.201 ; 8.201 ; Rise ; C25M ; +; RD[4] ; C25M ; 9.375 ; 9.375 ; Rise ; C25M ; +; RD[5] ; C25M ; 8.984 ; 8.984 ; Rise ; C25M ; +; RD[6] ; C25M ; 8.913 ; 8.913 ; Rise ; C25M ; +; RD[7] ; C25M ; 9.917 ; 9.917 ; Rise ; C25M ; +; RDdir ; C25M ; 9.501 ; 9.501 ; Rise ; C25M ; +; SA[*] ; C25M ; 7.567 ; 7.567 ; Rise ; C25M ; +; SA[0] ; C25M ; 8.606 ; 8.606 ; Rise ; C25M ; +; SA[1] ; C25M ; 8.584 ; 8.584 ; Rise ; C25M ; +; SA[2] ; C25M ; 8.798 ; 8.798 ; Rise ; C25M ; +; SA[3] ; C25M ; 8.651 ; 8.651 ; Rise ; C25M ; +; SA[4] ; C25M ; 8.242 ; 8.242 ; Rise ; C25M ; +; SA[5] ; C25M ; 8.647 ; 8.647 ; Rise ; C25M ; +; SA[6] ; C25M ; 8.669 ; 8.669 ; Rise ; C25M ; +; SA[7] ; C25M ; 8.116 ; 8.116 ; Rise ; C25M ; +; SA[8] ; C25M ; 8.234 ; 8.234 ; Rise ; C25M ; +; SA[9] ; C25M ; 7.567 ; 7.567 ; Rise ; C25M ; +; SA[10] ; C25M ; 9.394 ; 9.394 ; Rise ; C25M ; +; SA[11] ; C25M ; 8.116 ; 8.116 ; Rise ; C25M ; +; SA[12] ; C25M ; 7.570 ; 7.570 ; Rise ; C25M ; +; SBA[*] ; C25M ; 8.073 ; 8.073 ; Rise ; C25M ; +; SBA[0] ; C25M ; 8.073 ; 8.073 ; Rise ; C25M ; +; SBA[1] ; C25M ; 8.077 ; 8.077 ; Rise ; C25M ; +; SD[*] ; C25M ; 8.097 ; 8.097 ; Rise ; C25M ; +; SD[0] ; C25M ; 8.113 ; 8.113 ; Rise ; C25M ; +; SD[1] ; C25M ; 8.097 ; 8.097 ; Rise ; C25M ; +; SD[2] ; C25M ; 8.574 ; 8.574 ; Rise ; C25M ; +; SD[3] ; C25M ; 8.249 ; 8.249 ; Rise ; C25M ; +; SD[4] ; C25M ; 8.125 ; 8.125 ; Rise ; C25M ; +; SD[5] ; C25M ; 8.113 ; 8.113 ; Rise ; C25M ; +; SD[6] ; C25M ; 8.674 ; 8.674 ; Rise ; C25M ; +; SD[7] ; C25M ; 8.241 ; 8.241 ; Rise ; C25M ; +; nCAS ; C25M ; 8.329 ; 8.329 ; Rise ; C25M ; +; nFCS ; C25M ; 6.964 ; 6.964 ; Rise ; C25M ; +; nRAS ; C25M ; 8.349 ; 8.349 ; Rise ; C25M ; +; nRCS ; C25M ; 9.461 ; 9.461 ; Rise ; C25M ; +; nRESout ; C25M ; 8.159 ; 8.159 ; Rise ; C25M ; +; nSWE ; C25M ; 8.815 ; 8.815 ; Rise ; C25M ; +; RDdir ; PHI0 ; 11.026 ; 11.026 ; Rise ; PHI0 ; +; RDdir ; PHI0 ; 11.026 ; 11.026 ; Fall ; PHI0 ; +-----------+------------+--------+--------+------------+-----------------+ @@ -850,44 +864,44 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +------------+-------------+--------+----+----+--------+ ; Input Port ; Output Port ; RR ; RF ; FR ; FF ; +------------+-------------+--------+----+----+--------+ -; DMAin ; DMAout ; 8.238 ; ; ; 8.238 ; -; INTin ; INTout ; 9.741 ; ; ; 9.741 ; -; nDEVSEL ; RD[0] ; 13.931 ; ; ; 13.931 ; -; nDEVSEL ; RD[1] ; 13.931 ; ; ; 13.931 ; -; nDEVSEL ; RD[2] ; 13.931 ; ; ; 13.931 ; -; nDEVSEL ; RD[3] ; 13.932 ; ; ; 13.932 ; -; nDEVSEL ; RD[4] ; 13.932 ; ; ; 13.932 ; -; nDEVSEL ; RD[5] ; 13.932 ; ; ; 13.932 ; -; nDEVSEL ; RD[6] ; 13.367 ; ; ; 13.367 ; -; nDEVSEL ; RD[7] ; 13.367 ; ; ; 13.367 ; -; nDEVSEL ; RDdir ; 14.924 ; ; ; 14.924 ; -; nIOSEL ; RD[0] ; 13.917 ; ; ; 13.917 ; -; nIOSEL ; RD[1] ; 13.917 ; ; ; 13.917 ; -; nIOSEL ; RD[2] ; 13.917 ; ; ; 13.917 ; -; nIOSEL ; RD[3] ; 13.918 ; ; ; 13.918 ; -; nIOSEL ; RD[4] ; 13.918 ; ; ; 13.918 ; -; nIOSEL ; RD[5] ; 13.918 ; ; ; 13.918 ; -; nIOSEL ; RD[6] ; 13.353 ; ; ; 13.353 ; -; nIOSEL ; RD[7] ; 13.353 ; ; ; 13.353 ; -; nIOSEL ; RDdir ; 14.910 ; ; ; 14.910 ; -; nIOSTRB ; RD[0] ; 13.766 ; ; ; 13.766 ; -; nIOSTRB ; RD[1] ; 13.766 ; ; ; 13.766 ; -; nIOSTRB ; RD[2] ; 13.766 ; ; ; 13.766 ; -; nIOSTRB ; RD[3] ; 13.767 ; ; ; 13.767 ; -; nIOSTRB ; RD[4] ; 13.767 ; ; ; 13.767 ; -; nIOSTRB ; RD[5] ; 13.767 ; ; ; 13.767 ; -; nIOSTRB ; RD[6] ; 13.202 ; ; ; 13.202 ; -; nIOSTRB ; RD[7] ; 13.202 ; ; ; 13.202 ; -; nIOSTRB ; RDdir ; 14.759 ; ; ; 14.759 ; -; nWE ; RD[0] ; 11.850 ; ; ; 11.850 ; -; nWE ; RD[1] ; 11.850 ; ; ; 11.850 ; -; nWE ; RD[2] ; 11.850 ; ; ; 11.850 ; -; nWE ; RD[3] ; 11.851 ; ; ; 11.851 ; -; nWE ; RD[4] ; 11.851 ; ; ; 11.851 ; -; nWE ; RD[5] ; 11.851 ; ; ; 11.851 ; -; nWE ; RD[6] ; 11.286 ; ; ; 11.286 ; -; nWE ; RD[7] ; 11.286 ; ; ; 11.286 ; -; nWE ; RDdir ; 12.843 ; ; ; 12.843 ; +; DMAin ; DMAout ; 8.656 ; ; ; 8.656 ; +; INTin ; INTout ; 8.937 ; ; ; 8.937 ; +; nDEVSEL ; RD[0] ; 14.969 ; ; ; 14.969 ; +; nDEVSEL ; RD[1] ; 14.969 ; ; ; 14.969 ; +; nDEVSEL ; RD[2] ; 14.969 ; ; ; 14.969 ; +; nDEVSEL ; RD[3] ; 14.969 ; ; ; 14.969 ; +; nDEVSEL ; RD[4] ; 14.969 ; ; ; 14.969 ; +; nDEVSEL ; RD[5] ; 14.969 ; ; ; 14.969 ; +; nDEVSEL ; RD[6] ; 14.980 ; ; ; 14.980 ; +; nDEVSEL ; RD[7] ; 14.980 ; ; ; 14.980 ; +; nDEVSEL ; RDdir ; 16.482 ; ; ; 16.482 ; +; nIOSEL ; RD[0] ; 14.415 ; ; ; 14.415 ; +; nIOSEL ; RD[1] ; 14.415 ; ; ; 14.415 ; +; nIOSEL ; RD[2] ; 14.415 ; ; ; 14.415 ; +; nIOSEL ; RD[3] ; 14.415 ; ; ; 14.415 ; +; nIOSEL ; RD[4] ; 14.415 ; ; ; 14.415 ; +; nIOSEL ; RD[5] ; 14.415 ; ; ; 14.415 ; +; nIOSEL ; RD[6] ; 14.426 ; ; ; 14.426 ; +; nIOSEL ; RD[7] ; 14.426 ; ; ; 14.426 ; +; nIOSEL ; RDdir ; 15.928 ; ; ; 15.928 ; +; nIOSTRB ; RD[0] ; 13.935 ; ; ; 13.935 ; +; nIOSTRB ; RD[1] ; 13.935 ; ; ; 13.935 ; +; nIOSTRB ; RD[2] ; 13.935 ; ; ; 13.935 ; +; nIOSTRB ; RD[3] ; 13.935 ; ; ; 13.935 ; +; nIOSTRB ; RD[4] ; 13.935 ; ; ; 13.935 ; +; nIOSTRB ; RD[5] ; 13.935 ; ; ; 13.935 ; +; nIOSTRB ; RD[6] ; 13.946 ; ; ; 13.946 ; +; nIOSTRB ; RD[7] ; 13.946 ; ; ; 13.946 ; +; nIOSTRB ; RDdir ; 15.448 ; ; ; 15.448 ; +; nWE ; RD[0] ; 9.870 ; ; ; 9.870 ; +; nWE ; RD[1] ; 9.870 ; ; ; 9.870 ; +; nWE ; RD[2] ; 9.870 ; ; ; 9.870 ; +; nWE ; RD[3] ; 9.870 ; ; ; 9.870 ; +; nWE ; RD[4] ; 9.870 ; ; ; 9.870 ; +; nWE ; RD[5] ; 9.870 ; ; ; 9.870 ; +; nWE ; RD[6] ; 9.881 ; ; ; 9.881 ; +; nWE ; RD[7] ; 9.881 ; ; ; 9.881 ; +; nWE ; RDdir ; 11.383 ; ; ; 11.383 ; +------------+-------------+--------+----+----+--------+ @@ -896,44 +910,44 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +------------+-------------+--------+----+----+--------+ ; Input Port ; Output Port ; RR ; RF ; FR ; FF ; +------------+-------------+--------+----+----+--------+ -; DMAin ; DMAout ; 8.238 ; ; ; 8.238 ; -; INTin ; INTout ; 9.741 ; ; ; 9.741 ; -; nDEVSEL ; RD[0] ; 13.931 ; ; ; 13.931 ; -; nDEVSEL ; RD[1] ; 13.931 ; ; ; 13.931 ; -; nDEVSEL ; RD[2] ; 13.931 ; ; ; 13.931 ; -; nDEVSEL ; RD[3] ; 13.932 ; ; ; 13.932 ; -; nDEVSEL ; RD[4] ; 13.932 ; ; ; 13.932 ; -; nDEVSEL ; RD[5] ; 13.932 ; ; ; 13.932 ; -; nDEVSEL ; RD[6] ; 13.367 ; ; ; 13.367 ; -; nDEVSEL ; RD[7] ; 13.367 ; ; ; 13.367 ; -; nDEVSEL ; RDdir ; 14.924 ; ; ; 14.924 ; -; nIOSEL ; RD[0] ; 13.917 ; ; ; 13.917 ; -; nIOSEL ; RD[1] ; 13.917 ; ; ; 13.917 ; -; nIOSEL ; RD[2] ; 13.917 ; ; ; 13.917 ; -; nIOSEL ; RD[3] ; 13.918 ; ; ; 13.918 ; -; nIOSEL ; RD[4] ; 13.918 ; ; ; 13.918 ; -; nIOSEL ; RD[5] ; 13.918 ; ; ; 13.918 ; -; nIOSEL ; RD[6] ; 13.353 ; ; ; 13.353 ; -; nIOSEL ; RD[7] ; 13.353 ; ; ; 13.353 ; -; nIOSEL ; RDdir ; 14.910 ; ; ; 14.910 ; -; nIOSTRB ; RD[0] ; 13.766 ; ; ; 13.766 ; -; nIOSTRB ; RD[1] ; 13.766 ; ; ; 13.766 ; -; nIOSTRB ; RD[2] ; 13.766 ; ; ; 13.766 ; -; nIOSTRB ; RD[3] ; 13.767 ; ; ; 13.767 ; -; nIOSTRB ; RD[4] ; 13.767 ; ; ; 13.767 ; -; nIOSTRB ; RD[5] ; 13.767 ; ; ; 13.767 ; -; nIOSTRB ; RD[6] ; 13.202 ; ; ; 13.202 ; -; nIOSTRB ; RD[7] ; 13.202 ; ; ; 13.202 ; -; nIOSTRB ; RDdir ; 14.759 ; ; ; 14.759 ; -; nWE ; RD[0] ; 11.850 ; ; ; 11.850 ; -; nWE ; RD[1] ; 11.850 ; ; ; 11.850 ; -; nWE ; RD[2] ; 11.850 ; ; ; 11.850 ; -; nWE ; RD[3] ; 11.851 ; ; ; 11.851 ; -; nWE ; RD[4] ; 11.851 ; ; ; 11.851 ; -; nWE ; RD[5] ; 11.851 ; ; ; 11.851 ; -; nWE ; RD[6] ; 11.286 ; ; ; 11.286 ; -; nWE ; RD[7] ; 11.286 ; ; ; 11.286 ; -; nWE ; RDdir ; 12.843 ; ; ; 12.843 ; +; DMAin ; DMAout ; 8.656 ; ; ; 8.656 ; +; INTin ; INTout ; 8.937 ; ; ; 8.937 ; +; nDEVSEL ; RD[0] ; 14.969 ; ; ; 14.969 ; +; nDEVSEL ; RD[1] ; 14.969 ; ; ; 14.969 ; +; nDEVSEL ; RD[2] ; 14.969 ; ; ; 14.969 ; +; nDEVSEL ; RD[3] ; 14.969 ; ; ; 14.969 ; +; nDEVSEL ; RD[4] ; 14.969 ; ; ; 14.969 ; +; nDEVSEL ; RD[5] ; 14.969 ; ; ; 14.969 ; +; nDEVSEL ; RD[6] ; 14.980 ; ; ; 14.980 ; +; nDEVSEL ; RD[7] ; 14.980 ; ; ; 14.980 ; +; nDEVSEL ; RDdir ; 16.482 ; ; ; 16.482 ; +; nIOSEL ; RD[0] ; 14.415 ; ; ; 14.415 ; +; nIOSEL ; RD[1] ; 14.415 ; ; ; 14.415 ; +; nIOSEL ; RD[2] ; 14.415 ; ; ; 14.415 ; +; nIOSEL ; RD[3] ; 14.415 ; ; ; 14.415 ; +; nIOSEL ; RD[4] ; 14.415 ; ; ; 14.415 ; +; nIOSEL ; RD[5] ; 14.415 ; ; ; 14.415 ; +; nIOSEL ; RD[6] ; 14.426 ; ; ; 14.426 ; +; nIOSEL ; RD[7] ; 14.426 ; ; ; 14.426 ; +; nIOSEL ; RDdir ; 15.928 ; ; ; 15.928 ; +; nIOSTRB ; RD[0] ; 13.935 ; ; ; 13.935 ; +; nIOSTRB ; RD[1] ; 13.935 ; ; ; 13.935 ; +; nIOSTRB ; RD[2] ; 13.935 ; ; ; 13.935 ; +; nIOSTRB ; RD[3] ; 13.935 ; ; ; 13.935 ; +; nIOSTRB ; RD[4] ; 13.935 ; ; ; 13.935 ; +; nIOSTRB ; RD[5] ; 13.935 ; ; ; 13.935 ; +; nIOSTRB ; RD[6] ; 13.946 ; ; ; 13.946 ; +; nIOSTRB ; RD[7] ; 13.946 ; ; ; 13.946 ; +; nIOSTRB ; RDdir ; 15.448 ; ; ; 15.448 ; +; nWE ; RD[0] ; 9.870 ; ; ; 9.870 ; +; nWE ; RD[1] ; 9.870 ; ; ; 9.870 ; +; nWE ; RD[2] ; 9.870 ; ; ; 9.870 ; +; nWE ; RD[3] ; 9.870 ; ; ; 9.870 ; +; nWE ; RD[4] ; 9.870 ; ; ; 9.870 ; +; nWE ; RD[5] ; 9.870 ; ; ; 9.870 ; +; nWE ; RD[6] ; 9.881 ; ; ; 9.881 ; +; nWE ; RD[7] ; 9.881 ; ; ; 9.881 ; +; nWE ; RDdir ; 11.383 ; ; ; 11.383 ; +------------+-------------+--------+----+----+--------+ @@ -942,45 +956,45 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-----------+------------+--------+------+------------+-----------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+--------+------+------------+-----------------+ -; FCK ; C25M ; 7.684 ; ; Rise ; C25M ; -; MOSI ; C25M ; 7.765 ; ; Rise ; C25M ; -; RD[*] ; C25M ; 12.794 ; ; Rise ; C25M ; -; RD[0] ; C25M ; 13.358 ; ; Rise ; C25M ; -; RD[1] ; C25M ; 13.358 ; ; Rise ; C25M ; -; RD[2] ; C25M ; 13.358 ; ; Rise ; C25M ; -; RD[3] ; C25M ; 13.359 ; ; Rise ; C25M ; -; RD[4] ; C25M ; 13.359 ; ; Rise ; C25M ; -; RD[5] ; C25M ; 13.359 ; ; Rise ; C25M ; -; RD[6] ; C25M ; 12.794 ; ; Rise ; C25M ; -; RD[7] ; C25M ; 12.794 ; ; Rise ; C25M ; -; SD[*] ; C25M ; 6.992 ; ; Rise ; C25M ; -; SD[0] ; C25M ; 7.401 ; ; Rise ; C25M ; -; SD[1] ; C25M ; 7.009 ; ; Rise ; C25M ; -; SD[2] ; C25M ; 6.992 ; ; Rise ; C25M ; -; SD[3] ; C25M ; 6.992 ; ; Rise ; C25M ; -; SD[4] ; C25M ; 7.401 ; ; Rise ; C25M ; -; SD[5] ; C25M ; 6.992 ; ; Rise ; C25M ; -; SD[6] ; C25M ; 6.992 ; ; Rise ; C25M ; -; SD[7] ; C25M ; 6.992 ; ; Rise ; C25M ; -; nFCS ; C25M ; 7.093 ; ; Rise ; C25M ; -; RD[*] ; PHI0 ; 8.938 ; ; Rise ; PHI0 ; -; RD[0] ; PHI0 ; 9.502 ; ; Rise ; PHI0 ; -; RD[1] ; PHI0 ; 9.502 ; ; Rise ; PHI0 ; -; RD[2] ; PHI0 ; 9.502 ; ; Rise ; PHI0 ; -; RD[3] ; PHI0 ; 9.503 ; ; Rise ; PHI0 ; -; RD[4] ; PHI0 ; 9.503 ; ; Rise ; PHI0 ; -; RD[5] ; PHI0 ; 9.503 ; ; Rise ; PHI0 ; -; RD[6] ; PHI0 ; 8.938 ; ; Rise ; PHI0 ; -; RD[7] ; PHI0 ; 8.938 ; ; Rise ; PHI0 ; -; RD[*] ; PHI0 ; 8.938 ; ; Fall ; PHI0 ; -; RD[0] ; PHI0 ; 9.502 ; ; Fall ; PHI0 ; -; RD[1] ; PHI0 ; 9.502 ; ; Fall ; PHI0 ; -; RD[2] ; PHI0 ; 9.502 ; ; Fall ; PHI0 ; -; RD[3] ; PHI0 ; 9.503 ; ; Fall ; PHI0 ; -; RD[4] ; PHI0 ; 9.503 ; ; Fall ; PHI0 ; -; RD[5] ; PHI0 ; 9.503 ; ; Fall ; PHI0 ; -; RD[6] ; PHI0 ; 8.938 ; ; Fall ; PHI0 ; -; RD[7] ; PHI0 ; 8.938 ; ; Fall ; PHI0 ; +; FCK ; C25M ; 8.571 ; ; Rise ; C25M ; +; MOSI ; C25M ; 7.845 ; ; Rise ; C25M ; +; RD[*] ; C25M ; 15.116 ; ; Rise ; C25M ; +; RD[0] ; C25M ; 15.116 ; ; Rise ; C25M ; +; RD[1] ; C25M ; 15.116 ; ; Rise ; C25M ; +; RD[2] ; C25M ; 15.116 ; ; Rise ; C25M ; +; RD[3] ; C25M ; 15.116 ; ; Rise ; C25M ; +; RD[4] ; C25M ; 15.116 ; ; Rise ; C25M ; +; RD[5] ; C25M ; 15.116 ; ; Rise ; C25M ; +; RD[6] ; C25M ; 15.127 ; ; Rise ; C25M ; +; RD[7] ; C25M ; 15.127 ; ; Rise ; C25M ; +; SD[*] ; C25M ; 6.442 ; ; Rise ; C25M ; +; SD[0] ; C25M ; 6.935 ; ; Rise ; C25M ; +; SD[1] ; C25M ; 6.935 ; ; Rise ; C25M ; +; SD[2] ; C25M ; 6.442 ; ; Rise ; C25M ; +; SD[3] ; C25M ; 6.442 ; ; Rise ; C25M ; +; SD[4] ; C25M ; 6.935 ; ; Rise ; C25M ; +; SD[5] ; C25M ; 6.442 ; ; Rise ; C25M ; +; SD[6] ; C25M ; 6.442 ; ; Rise ; C25M ; +; SD[7] ; C25M ; 6.442 ; ; Rise ; C25M ; +; nFCS ; C25M ; 7.793 ; ; Rise ; C25M ; +; RD[*] ; PHI0 ; 9.513 ; ; Rise ; PHI0 ; +; RD[0] ; PHI0 ; 9.513 ; ; Rise ; PHI0 ; +; RD[1] ; PHI0 ; 9.513 ; ; Rise ; PHI0 ; +; RD[2] ; PHI0 ; 9.513 ; ; Rise ; PHI0 ; +; RD[3] ; PHI0 ; 9.513 ; ; Rise ; PHI0 ; +; RD[4] ; PHI0 ; 9.513 ; ; Rise ; PHI0 ; +; RD[5] ; PHI0 ; 9.513 ; ; Rise ; PHI0 ; +; RD[6] ; PHI0 ; 9.524 ; ; Rise ; PHI0 ; +; RD[7] ; PHI0 ; 9.524 ; ; Rise ; PHI0 ; +; RD[*] ; PHI0 ; 9.513 ; ; Fall ; PHI0 ; +; RD[0] ; PHI0 ; 9.513 ; ; Fall ; PHI0 ; +; RD[1] ; PHI0 ; 9.513 ; ; Fall ; PHI0 ; +; RD[2] ; PHI0 ; 9.513 ; ; Fall ; PHI0 ; +; RD[3] ; PHI0 ; 9.513 ; ; Fall ; PHI0 ; +; RD[4] ; PHI0 ; 9.513 ; ; Fall ; PHI0 ; +; RD[5] ; PHI0 ; 9.513 ; ; Fall ; PHI0 ; +; RD[6] ; PHI0 ; 9.524 ; ; Fall ; PHI0 ; +; RD[7] ; PHI0 ; 9.524 ; ; Fall ; PHI0 ; +-----------+------------+--------+------+------------+-----------------+ @@ -989,45 +1003,45 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-----------+------------+-------+------+------------+-----------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+-------+------+------------+-----------------+ -; FCK ; C25M ; 7.684 ; ; Rise ; C25M ; -; MOSI ; C25M ; 7.765 ; ; Rise ; C25M ; -; RD[*] ; C25M ; 8.190 ; ; Rise ; C25M ; -; RD[0] ; C25M ; 8.754 ; ; Rise ; C25M ; -; RD[1] ; C25M ; 8.754 ; ; Rise ; C25M ; -; RD[2] ; C25M ; 8.754 ; ; Rise ; C25M ; -; RD[3] ; C25M ; 8.755 ; ; Rise ; C25M ; -; RD[4] ; C25M ; 8.755 ; ; Rise ; C25M ; -; RD[5] ; C25M ; 8.755 ; ; Rise ; C25M ; -; RD[6] ; C25M ; 8.190 ; ; Rise ; C25M ; -; RD[7] ; C25M ; 8.190 ; ; Rise ; C25M ; -; SD[*] ; C25M ; 6.992 ; ; Rise ; C25M ; -; SD[0] ; C25M ; 7.401 ; ; Rise ; C25M ; -; SD[1] ; C25M ; 7.009 ; ; Rise ; C25M ; -; SD[2] ; C25M ; 6.992 ; ; Rise ; C25M ; -; SD[3] ; C25M ; 6.992 ; ; Rise ; C25M ; -; SD[4] ; C25M ; 7.401 ; ; Rise ; C25M ; -; SD[5] ; C25M ; 6.992 ; ; Rise ; C25M ; -; SD[6] ; C25M ; 6.992 ; ; Rise ; C25M ; -; SD[7] ; C25M ; 6.992 ; ; Rise ; C25M ; -; nFCS ; C25M ; 7.093 ; ; Rise ; C25M ; -; RD[*] ; PHI0 ; 8.938 ; ; Rise ; PHI0 ; -; RD[0] ; PHI0 ; 9.502 ; ; Rise ; PHI0 ; -; RD[1] ; PHI0 ; 9.502 ; ; Rise ; PHI0 ; -; RD[2] ; PHI0 ; 9.502 ; ; Rise ; PHI0 ; -; RD[3] ; PHI0 ; 9.503 ; ; Rise ; PHI0 ; -; RD[4] ; PHI0 ; 9.503 ; ; Rise ; PHI0 ; -; RD[5] ; PHI0 ; 9.503 ; ; Rise ; PHI0 ; -; RD[6] ; PHI0 ; 8.938 ; ; Rise ; PHI0 ; -; RD[7] ; PHI0 ; 8.938 ; ; Rise ; PHI0 ; -; RD[*] ; PHI0 ; 8.938 ; ; Fall ; PHI0 ; -; RD[0] ; PHI0 ; 9.502 ; ; Fall ; PHI0 ; -; RD[1] ; PHI0 ; 9.502 ; ; Fall ; PHI0 ; -; RD[2] ; PHI0 ; 9.502 ; ; Fall ; PHI0 ; -; RD[3] ; PHI0 ; 9.503 ; ; Fall ; PHI0 ; -; RD[4] ; PHI0 ; 9.503 ; ; Fall ; PHI0 ; -; RD[5] ; PHI0 ; 9.503 ; ; Fall ; PHI0 ; -; RD[6] ; PHI0 ; 8.938 ; ; Fall ; PHI0 ; -; RD[7] ; PHI0 ; 8.938 ; ; Fall ; PHI0 ; +; FCK ; C25M ; 8.571 ; ; Rise ; C25M ; +; MOSI ; C25M ; 7.845 ; ; Rise ; C25M ; +; RD[*] ; C25M ; 7.988 ; ; Rise ; C25M ; +; RD[0] ; C25M ; 7.988 ; ; Rise ; C25M ; +; RD[1] ; C25M ; 7.988 ; ; Rise ; C25M ; +; RD[2] ; C25M ; 7.988 ; ; Rise ; C25M ; +; RD[3] ; C25M ; 7.988 ; ; Rise ; C25M ; +; RD[4] ; C25M ; 7.988 ; ; Rise ; C25M ; +; RD[5] ; C25M ; 7.988 ; ; Rise ; C25M ; +; RD[6] ; C25M ; 7.999 ; ; Rise ; C25M ; +; RD[7] ; C25M ; 7.999 ; ; Rise ; C25M ; +; SD[*] ; C25M ; 6.442 ; ; Rise ; C25M ; +; SD[0] ; C25M ; 6.935 ; ; Rise ; C25M ; +; SD[1] ; C25M ; 6.935 ; ; Rise ; C25M ; +; SD[2] ; C25M ; 6.442 ; ; Rise ; C25M ; +; SD[3] ; C25M ; 6.442 ; ; Rise ; C25M ; +; SD[4] ; C25M ; 6.935 ; ; Rise ; C25M ; +; SD[5] ; C25M ; 6.442 ; ; Rise ; C25M ; +; SD[6] ; C25M ; 6.442 ; ; Rise ; C25M ; +; SD[7] ; C25M ; 6.442 ; ; Rise ; C25M ; +; nFCS ; C25M ; 7.793 ; ; Rise ; C25M ; +; RD[*] ; PHI0 ; 9.513 ; ; Rise ; PHI0 ; +; RD[0] ; PHI0 ; 9.513 ; ; Rise ; PHI0 ; +; RD[1] ; PHI0 ; 9.513 ; ; Rise ; PHI0 ; +; RD[2] ; PHI0 ; 9.513 ; ; Rise ; PHI0 ; +; RD[3] ; PHI0 ; 9.513 ; ; Rise ; PHI0 ; +; RD[4] ; PHI0 ; 9.513 ; ; Rise ; PHI0 ; +; RD[5] ; PHI0 ; 9.513 ; ; Rise ; PHI0 ; +; RD[6] ; PHI0 ; 9.524 ; ; Rise ; PHI0 ; +; RD[7] ; PHI0 ; 9.524 ; ; Rise ; PHI0 ; +; RD[*] ; PHI0 ; 9.513 ; ; Fall ; PHI0 ; +; RD[0] ; PHI0 ; 9.513 ; ; Fall ; PHI0 ; +; RD[1] ; PHI0 ; 9.513 ; ; Fall ; PHI0 ; +; RD[2] ; PHI0 ; 9.513 ; ; Fall ; PHI0 ; +; RD[3] ; PHI0 ; 9.513 ; ; Fall ; PHI0 ; +; RD[4] ; PHI0 ; 9.513 ; ; Fall ; PHI0 ; +; RD[5] ; PHI0 ; 9.513 ; ; Fall ; PHI0 ; +; RD[6] ; PHI0 ; 9.524 ; ; Fall ; PHI0 ; +; RD[7] ; PHI0 ; 9.524 ; ; Fall ; PHI0 ; +-----------+------------+-------+------+------------+-----------------+ @@ -1036,45 +1050,45 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-----------+------------+-----------+-----------+------------+-----------------+ ; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; +-----------+------------+-----------+-----------+------------+-----------------+ -; FCK ; C25M ; 7.684 ; ; Rise ; C25M ; -; MOSI ; C25M ; 7.765 ; ; Rise ; C25M ; -; RD[*] ; C25M ; 12.794 ; ; Rise ; C25M ; -; RD[0] ; C25M ; 13.358 ; ; Rise ; C25M ; -; RD[1] ; C25M ; 13.358 ; ; Rise ; C25M ; -; RD[2] ; C25M ; 13.358 ; ; Rise ; C25M ; -; RD[3] ; C25M ; 13.359 ; ; Rise ; C25M ; -; RD[4] ; C25M ; 13.359 ; ; Rise ; C25M ; -; RD[5] ; C25M ; 13.359 ; ; Rise ; C25M ; -; RD[6] ; C25M ; 12.794 ; ; Rise ; C25M ; -; RD[7] ; C25M ; 12.794 ; ; Rise ; C25M ; -; SD[*] ; C25M ; 6.992 ; ; Rise ; C25M ; -; SD[0] ; C25M ; 7.401 ; ; Rise ; C25M ; -; SD[1] ; C25M ; 7.009 ; ; Rise ; C25M ; -; SD[2] ; C25M ; 6.992 ; ; Rise ; C25M ; -; SD[3] ; C25M ; 6.992 ; ; Rise ; C25M ; -; SD[4] ; C25M ; 7.401 ; ; Rise ; C25M ; -; SD[5] ; C25M ; 6.992 ; ; Rise ; C25M ; -; SD[6] ; C25M ; 6.992 ; ; Rise ; C25M ; -; SD[7] ; C25M ; 6.992 ; ; Rise ; C25M ; -; nFCS ; C25M ; 7.093 ; ; Rise ; C25M ; -; RD[*] ; PHI0 ; 8.938 ; ; Rise ; PHI0 ; -; RD[0] ; PHI0 ; 9.502 ; ; Rise ; PHI0 ; -; RD[1] ; PHI0 ; 9.502 ; ; Rise ; PHI0 ; -; RD[2] ; PHI0 ; 9.502 ; ; Rise ; PHI0 ; -; RD[3] ; PHI0 ; 9.503 ; ; Rise ; PHI0 ; -; RD[4] ; PHI0 ; 9.503 ; ; Rise ; PHI0 ; -; RD[5] ; PHI0 ; 9.503 ; ; Rise ; PHI0 ; -; RD[6] ; PHI0 ; 8.938 ; ; Rise ; PHI0 ; -; RD[7] ; PHI0 ; 8.938 ; ; Rise ; PHI0 ; -; RD[*] ; PHI0 ; 8.938 ; ; Fall ; PHI0 ; -; RD[0] ; PHI0 ; 9.502 ; ; Fall ; PHI0 ; -; RD[1] ; PHI0 ; 9.502 ; ; Fall ; PHI0 ; -; RD[2] ; PHI0 ; 9.502 ; ; Fall ; PHI0 ; -; RD[3] ; PHI0 ; 9.503 ; ; Fall ; PHI0 ; -; RD[4] ; PHI0 ; 9.503 ; ; Fall ; PHI0 ; -; RD[5] ; PHI0 ; 9.503 ; ; Fall ; PHI0 ; -; RD[6] ; PHI0 ; 8.938 ; ; Fall ; PHI0 ; -; RD[7] ; PHI0 ; 8.938 ; ; Fall ; PHI0 ; +; FCK ; C25M ; 8.571 ; ; Rise ; C25M ; +; MOSI ; C25M ; 7.845 ; ; Rise ; C25M ; +; RD[*] ; C25M ; 15.116 ; ; Rise ; C25M ; +; RD[0] ; C25M ; 15.116 ; ; Rise ; C25M ; +; RD[1] ; C25M ; 15.116 ; ; Rise ; C25M ; +; RD[2] ; C25M ; 15.116 ; ; Rise ; C25M ; +; RD[3] ; C25M ; 15.116 ; ; Rise ; C25M ; +; RD[4] ; C25M ; 15.116 ; ; Rise ; C25M ; +; RD[5] ; C25M ; 15.116 ; ; Rise ; C25M ; +; RD[6] ; C25M ; 15.127 ; ; Rise ; C25M ; +; RD[7] ; C25M ; 15.127 ; ; Rise ; C25M ; +; SD[*] ; C25M ; 6.442 ; ; Rise ; C25M ; +; SD[0] ; C25M ; 6.935 ; ; Rise ; C25M ; +; SD[1] ; C25M ; 6.935 ; ; Rise ; C25M ; +; SD[2] ; C25M ; 6.442 ; ; Rise ; C25M ; +; SD[3] ; C25M ; 6.442 ; ; Rise ; C25M ; +; SD[4] ; C25M ; 6.935 ; ; Rise ; C25M ; +; SD[5] ; C25M ; 6.442 ; ; Rise ; C25M ; +; SD[6] ; C25M ; 6.442 ; ; Rise ; C25M ; +; SD[7] ; C25M ; 6.442 ; ; Rise ; C25M ; +; nFCS ; C25M ; 7.793 ; ; Rise ; C25M ; +; RD[*] ; PHI0 ; 9.513 ; ; Rise ; PHI0 ; +; RD[0] ; PHI0 ; 9.513 ; ; Rise ; PHI0 ; +; RD[1] ; PHI0 ; 9.513 ; ; Rise ; PHI0 ; +; RD[2] ; PHI0 ; 9.513 ; ; Rise ; PHI0 ; +; RD[3] ; PHI0 ; 9.513 ; ; Rise ; PHI0 ; +; RD[4] ; PHI0 ; 9.513 ; ; Rise ; PHI0 ; +; RD[5] ; PHI0 ; 9.513 ; ; Rise ; PHI0 ; +; RD[6] ; PHI0 ; 9.524 ; ; Rise ; PHI0 ; +; RD[7] ; PHI0 ; 9.524 ; ; Rise ; PHI0 ; +; RD[*] ; PHI0 ; 9.513 ; ; Fall ; PHI0 ; +; RD[0] ; PHI0 ; 9.513 ; ; Fall ; PHI0 ; +; RD[1] ; PHI0 ; 9.513 ; ; Fall ; PHI0 ; +; RD[2] ; PHI0 ; 9.513 ; ; Fall ; PHI0 ; +; RD[3] ; PHI0 ; 9.513 ; ; Fall ; PHI0 ; +; RD[4] ; PHI0 ; 9.513 ; ; Fall ; PHI0 ; +; RD[5] ; PHI0 ; 9.513 ; ; Fall ; PHI0 ; +; RD[6] ; PHI0 ; 9.524 ; ; Fall ; PHI0 ; +; RD[7] ; PHI0 ; 9.524 ; ; Fall ; PHI0 ; +-----------+------------+-----------+-----------+------------+-----------------+ @@ -1083,45 +1097,45 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-----------+------------+-----------+-----------+------------+-----------------+ ; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; +-----------+------------+-----------+-----------+------------+-----------------+ -; FCK ; C25M ; 7.684 ; ; Rise ; C25M ; -; MOSI ; C25M ; 7.765 ; ; Rise ; C25M ; -; RD[*] ; C25M ; 8.190 ; ; Rise ; C25M ; -; RD[0] ; C25M ; 8.754 ; ; Rise ; C25M ; -; RD[1] ; C25M ; 8.754 ; ; Rise ; C25M ; -; RD[2] ; C25M ; 8.754 ; ; Rise ; C25M ; -; RD[3] ; C25M ; 8.755 ; ; Rise ; C25M ; -; RD[4] ; C25M ; 8.755 ; ; Rise ; C25M ; -; RD[5] ; C25M ; 8.755 ; ; Rise ; C25M ; -; RD[6] ; C25M ; 8.190 ; ; Rise ; C25M ; -; RD[7] ; C25M ; 8.190 ; ; Rise ; C25M ; -; SD[*] ; C25M ; 6.992 ; ; Rise ; C25M ; -; SD[0] ; C25M ; 7.401 ; ; Rise ; C25M ; -; SD[1] ; C25M ; 7.009 ; ; Rise ; C25M ; -; SD[2] ; C25M ; 6.992 ; ; Rise ; C25M ; -; SD[3] ; C25M ; 6.992 ; ; Rise ; C25M ; -; SD[4] ; C25M ; 7.401 ; ; Rise ; C25M ; -; SD[5] ; C25M ; 6.992 ; ; Rise ; C25M ; -; SD[6] ; C25M ; 6.992 ; ; Rise ; C25M ; -; SD[7] ; C25M ; 6.992 ; ; Rise ; C25M ; -; nFCS ; C25M ; 7.093 ; ; Rise ; C25M ; -; RD[*] ; PHI0 ; 8.938 ; ; Rise ; PHI0 ; -; RD[0] ; PHI0 ; 9.502 ; ; Rise ; PHI0 ; -; RD[1] ; PHI0 ; 9.502 ; ; Rise ; PHI0 ; -; RD[2] ; PHI0 ; 9.502 ; ; Rise ; PHI0 ; -; RD[3] ; PHI0 ; 9.503 ; ; Rise ; PHI0 ; -; RD[4] ; PHI0 ; 9.503 ; ; Rise ; PHI0 ; -; RD[5] ; PHI0 ; 9.503 ; ; Rise ; PHI0 ; -; RD[6] ; PHI0 ; 8.938 ; ; Rise ; PHI0 ; -; RD[7] ; PHI0 ; 8.938 ; ; Rise ; PHI0 ; -; RD[*] ; PHI0 ; 8.938 ; ; Fall ; PHI0 ; -; RD[0] ; PHI0 ; 9.502 ; ; Fall ; PHI0 ; -; RD[1] ; PHI0 ; 9.502 ; ; Fall ; PHI0 ; -; RD[2] ; PHI0 ; 9.502 ; ; Fall ; PHI0 ; -; RD[3] ; PHI0 ; 9.503 ; ; Fall ; PHI0 ; -; RD[4] ; PHI0 ; 9.503 ; ; Fall ; PHI0 ; -; RD[5] ; PHI0 ; 9.503 ; ; Fall ; PHI0 ; -; RD[6] ; PHI0 ; 8.938 ; ; Fall ; PHI0 ; -; RD[7] ; PHI0 ; 8.938 ; ; Fall ; PHI0 ; +; FCK ; C25M ; 8.571 ; ; Rise ; C25M ; +; MOSI ; C25M ; 7.845 ; ; Rise ; C25M ; +; RD[*] ; C25M ; 7.988 ; ; Rise ; C25M ; +; RD[0] ; C25M ; 7.988 ; ; Rise ; C25M ; +; RD[1] ; C25M ; 7.988 ; ; Rise ; C25M ; +; RD[2] ; C25M ; 7.988 ; ; Rise ; C25M ; +; RD[3] ; C25M ; 7.988 ; ; Rise ; C25M ; +; RD[4] ; C25M ; 7.988 ; ; Rise ; C25M ; +; RD[5] ; C25M ; 7.988 ; ; Rise ; C25M ; +; RD[6] ; C25M ; 7.999 ; ; Rise ; C25M ; +; RD[7] ; C25M ; 7.999 ; ; Rise ; C25M ; +; SD[*] ; C25M ; 6.442 ; ; Rise ; C25M ; +; SD[0] ; C25M ; 6.935 ; ; Rise ; C25M ; +; SD[1] ; C25M ; 6.935 ; ; Rise ; C25M ; +; SD[2] ; C25M ; 6.442 ; ; Rise ; C25M ; +; SD[3] ; C25M ; 6.442 ; ; Rise ; C25M ; +; SD[4] ; C25M ; 6.935 ; ; Rise ; C25M ; +; SD[5] ; C25M ; 6.442 ; ; Rise ; C25M ; +; SD[6] ; C25M ; 6.442 ; ; Rise ; C25M ; +; SD[7] ; C25M ; 6.442 ; ; Rise ; C25M ; +; nFCS ; C25M ; 7.793 ; ; Rise ; C25M ; +; RD[*] ; PHI0 ; 9.513 ; ; Rise ; PHI0 ; +; RD[0] ; PHI0 ; 9.513 ; ; Rise ; PHI0 ; +; RD[1] ; PHI0 ; 9.513 ; ; Rise ; PHI0 ; +; RD[2] ; PHI0 ; 9.513 ; ; Rise ; PHI0 ; +; RD[3] ; PHI0 ; 9.513 ; ; Rise ; PHI0 ; +; RD[4] ; PHI0 ; 9.513 ; ; Rise ; PHI0 ; +; RD[5] ; PHI0 ; 9.513 ; ; Rise ; PHI0 ; +; RD[6] ; PHI0 ; 9.524 ; ; Rise ; PHI0 ; +; RD[7] ; PHI0 ; 9.524 ; ; Rise ; PHI0 ; +; RD[*] ; PHI0 ; 9.513 ; ; Fall ; PHI0 ; +; RD[0] ; PHI0 ; 9.513 ; ; Fall ; PHI0 ; +; RD[1] ; PHI0 ; 9.513 ; ; Fall ; PHI0 ; +; RD[2] ; PHI0 ; 9.513 ; ; Fall ; PHI0 ; +; RD[3] ; PHI0 ; 9.513 ; ; Fall ; PHI0 ; +; RD[4] ; PHI0 ; 9.513 ; ; Fall ; PHI0 ; +; RD[5] ; PHI0 ; 9.513 ; ; Fall ; PHI0 ; +; RD[6] ; PHI0 ; 9.524 ; ; Fall ; PHI0 ; +; RD[7] ; PHI0 ; 9.524 ; ; Fall ; PHI0 ; +-----------+------------+-----------+-----------+------------+-----------------+ @@ -1130,9 +1144,9 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +------------+----------+----------+----------+----------+----------+ ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; +------------+----------+----------+----------+----------+----------+ -; C25M ; C25M ; 1369 ; 0 ; 0 ; 0 ; +; C25M ; C25M ; 1378 ; 0 ; 0 ; 0 ; ; PHI0 ; C25M ; 84 ; 1 ; 0 ; 0 ; -; C25M ; PHI0 ; 2 ; 0 ; 0 ; 0 ; +; C25M ; PHI0 ; 3 ; 0 ; 0 ; 0 ; +------------+----------+----------+----------+----------+----------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. @@ -1142,9 +1156,9 @@ Entries labeled "false path" only account for clock-to-clock false paths and not +------------+----------+----------+----------+----------+----------+ ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; +------------+----------+----------+----------+----------+----------+ -; C25M ; C25M ; 1369 ; 0 ; 0 ; 0 ; +; C25M ; C25M ; 1378 ; 0 ; 0 ; 0 ; ; PHI0 ; C25M ; 84 ; 1 ; 0 ; 0 ; -; C25M ; PHI0 ; 2 ; 0 ; 0 ; 0 ; +; C25M ; PHI0 ; 3 ; 0 ; 0 ; 0 ; +------------+----------+----------+----------+----------+----------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. @@ -1188,8 +1202,8 @@ No dedicated SERDES Receiver circuitry present in device or used in design +---------------------------------+-------+------+ ; Illegal Clocks ; 0 ; 0 ; ; Unconstrained Clocks ; 0 ; 0 ; -; Unconstrained Input Ports ; 42 ; 42 ; -; Unconstrained Input Port Paths ; 643 ; 643 ; +; Unconstrained Input Ports ; 44 ; 44 ; +; Unconstrained Input Port Paths ; 655 ; 655 ; ; Unconstrained Output Ports ; 45 ; 45 ; ; Unconstrained Output Port Paths ; 118 ; 118 ; +---------------------------------+-------+------+ @@ -1201,7 +1215,7 @@ No dedicated SERDES Receiver circuitry present in device or used in design Info: ******************************************************************* Info: Running Quartus II 32-bit TimeQuest Timing Analyzer Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - Info: Processing started: Mon Apr 19 01:27:20 2021 + Info: Processing started: Tue Apr 20 04:00:22 2021 Info: Command: quartus_sta GR8RAM -c GR8RAM Info: qsta_default_script.tcl version: #1 Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected @@ -1216,24 +1230,24 @@ Info (332105): Deriving Clocks Info (332105): create_clock -period 1.000 -name PHI0 PHI0 Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON Critical Warning (332148): Timing requirements not met -Info (332146): Worst-case setup slack is -9.468 +Info (332146): Worst-case setup slack is -9.480 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== - Info (332119): -9.468 -696.810 C25M - Info (332119): 0.212 0.000 PHI0 -Info (332146): Worst-case hold slack is -0.265 + Info (332119): -9.480 -695.573 C25M + Info (332119): -0.522 -0.522 PHI0 +Info (332146): Worst-case hold slack is -0.197 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== - Info (332119): -0.265 -0.265 PHI0 - Info (332119): 1.374 0.000 C25M -Info (332146): Worst-case recovery slack is -4.404 + Info (332119): -0.197 -0.197 PHI0 + Info (332119): 1.385 0.000 C25M +Info (332146): Worst-case recovery slack is -4.399 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== - Info (332119): -4.404 -127.716 C25M -Info (332146): Worst-case removal slack is 4.850 + Info (332119): -4.399 -127.571 C25M +Info (332146): Worst-case removal slack is 4.845 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== - Info (332119): 4.850 0.000 C25M + Info (332119): 4.845 0.000 C25M Info (332146): Worst-case minimum pulse width slack is -2.289 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== @@ -1243,8 +1257,8 @@ Info (332001): The selected device family is not supported by the report_metasta Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings - Info: Peak virtual memory: 283 megabytes - Info: Processing ended: Mon Apr 19 01:27:24 2021 + Info: Peak virtual memory: 278 megabytes + Info: Processing ended: Tue Apr 20 04:00:26 2021 Info: Elapsed time: 00:00:04 Info: Total CPU time (on all processors): 00:00:04 diff --git a/cpld/output_files/GR8RAM.sta.summary b/cpld/output_files/GR8RAM.sta.summary index 353f12e..3fc566d 100755 --- a/cpld/output_files/GR8RAM.sta.summary +++ b/cpld/output_files/GR8RAM.sta.summary @@ -3,27 +3,27 @@ TimeQuest Timing Analyzer Summary ------------------------------------------------------------ Type : Setup 'C25M' -Slack : -9.468 -TNS : -696.810 +Slack : -9.480 +TNS : -695.573 Type : Setup 'PHI0' -Slack : 0.212 -TNS : 0.000 +Slack : -0.522 +TNS : -0.522 Type : Hold 'PHI0' -Slack : -0.265 -TNS : -0.265 +Slack : -0.197 +TNS : -0.197 Type : Hold 'C25M' -Slack : 1.374 +Slack : 1.385 TNS : 0.000 Type : Recovery 'C25M' -Slack : -4.404 -TNS : -127.716 +Slack : -4.399 +TNS : -127.571 Type : Removal 'C25M' -Slack : 4.850 +Slack : 4.845 TNS : 0.000 Type : Minimum Pulse Width 'C25M'