Apple-2-HW/GR8RAM
1
0
Fork 1
mirror of https://github.com/garrettsworkshop/GR8RAM.git synced 2025-03-03 03:30:39 +00:00
Code Issues Projects Releases Wiki Activity

Cleanup

Browse Source
This commit is contained in:
Zane Kaminski 2020-02-26 03:15:36 -05:00
parent 04be5a0257
commit 490fcfb8e7
1 changed files with 1 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
cpld/GR8RAM.v
View File

@ -34,7 +34,6 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
/* Select Signals */ /* Select Signals */
wire BankSELA = A[3:0]==4'hF; wire BankSELA = A[3:0]==4'hF;
wire SetSELA = A[3:0]==4'hE;
wire RAMSELA = A[3:0]==4'h3; wire RAMSELA = A[3:0]==4'h3;
wire AddrHSELA = A[3:0]==4'h2; wire AddrHSELA = A[3:0]==4'h2;
wire AddrMSELA = A[3:0]==4'h1; wire AddrMSELA = A[3:0]==4'h1;
@ -53,7 +52,7 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
wire DOE = DBEN & nWE & wire DOE = DBEN & nWE &
((~nDEVSEL & REGEN) | ~nIOSEL | (~nIOSTRB & IOROMEN)); ((~nDEVSEL & REGEN) | ~nIOSEL | (~nIOSTRB & IOROMEN));
wire [7:0] Dout = (nDEVSEL | RAMSELA) ? RD[7:0] : wire [7:0] Dout = (nDEVSEL | RAMSELA) ? RD[7:0] :
AddrHSELA ? {Addr[23:16]} : AddrHSELA ? Addr[23:16] :
AddrMSELA ? Addr[15:8] : AddrMSELA ? Addr[15:8] :
AddrLSELA ? Addr[7:0] : 8'h00; AddrLSELA ? Addr[7:0] : 8'h00;
inout [7:0] D = DOE ? Dout : 8'bZ; inout [7:0] D = DOE ? Dout : 8'bZ;