diff --git a/Documentation/Initialization Sequence b/Documentation/Initialization Sequence index 5f0d459..84abe2d 100644 --- a/Documentation/Initialization Sequence +++ b/Documentation/Initialization Sequence @@ -1,164 +1,3 @@ -Init sequence - -Init State SDRAM Flash IS Other --------------------------------------------------------------------------------- -$000000-$0FFFBF Wait for Vcc Wait for Vcc 0 -$000000 NOP CKE /CS hi, CLK lo -... -$0FFF90 NOP CKE /CS hi, CLK lo InitActv <= ~BODf -.... -$0FFFA0 NOP CKE /CS lo, CLK lo -... -$0FFFAF NOP CKE /CS lo, CLK lo - -$0FFFB0-$0FFFBF Init: Precharge Send read cmd ($03) 1 -$0FFFB0 NOP CKE CLK lo, MOSI 0 (b7) -$0FFFB1 NOP CKE CLK hi -$0FFFB2 NOP CKE CLK lo, MOSI 0 (b6) -$0FFFB3 PC all CLK hi -$0FFFB4 NOP CKE CLK lo, MOSI 0 (b5) -$0FFFB5 NOP CKE CLK hi -$0FFFB6 NOP CKE CLK lo, MOSI 0 (b4) -$0FFFB7 NOP CKE CLK hi -$0FFFB8 NOP CKE CLK lo, MOSI 0 (b3) -$0FFFB9 NOP CKE CLK hi -$0FFFBA NOP CKE CLK lo, MOSI 0 (b2) -$0FFFBB Load mode CLK hi -$0FFFBC NOP CKE CLK lo, MOSI 1 (b1) -$0FFFBD NOP CKE CLK hi -$0FFFBE NOP CKE CLK lo, MOSI 1 (b0) -$0FFFBF NOP CKE CLK hi - -$0FFFC0-$0FFFEF Init: mode & ref Send address ($000000) 2 -$0FFFC0 NOP CKE CLK lo, MOSI 0 (b23) -$0FFFC1 NOP CKE CLK hi -$0FFFC2 NOP CKE CLK lo, MOSI 0 (b22) -$0FFFC3 AREF CLK hi -$0FFFC4 NOP CKE CLK lo, MOSI Firmware[1] (b21) -$0FFFC5 NOP CKE CLK hi -$0FFFC6 NOP CKE CLK lo, MOSI Firmware[0] (b20) -$0FFFC7 NOP CKE CLK hi -$0FFFC8 NOP CKE CLK lo, MOSI 0 (b19) -$0FFFC9 NOP CKE CLK hi -$0FFFCA NOP CKE CLK lo, MOSI 0 (b18) -$0FFFCB AREF CLK hi -$0FFFCC NOP CKE CLK lo, MOSI 0 (b17) -$0FFFCD NOP CKE CLK hi -$0FFFCE NOP CKE CLK lo, MOSI 0 (b16) -$0FFFCF NOP CKE CLK hi -$0FFFD0 NOP CKE CLK lo, MOSI 0 (b15) -$0FFFD1 NOP CKE CLK hi -$0FFFD2 NOP CKE CLK lo, MOSI 0 (b14) -$0FFFD3 AREF CLK hi -$0FFFD4 NOP CKE CLK lo, MOSI 0 (b13) -$0FFFD5 NOP CKE CLK hi -$0FFFD6 NOP CKE CLK lo, MOSI 0 (b12) -$0FFFD7 NOP CKE CLK hi -$0FFFD8 NOP CKE CLK lo, MOSI 0 (b11) -$0FFFD9 NOP CKE CLK hi -$0FFFDA NOP CKE CLK lo, MOSI 0 (b10) -$0FFFDB AREF CLK hi -$0FFFDC NOP CKE CLK lo, MOSI 0 (b9) -$0FFFDD NOP CKE CLK hi -$0FFFDE NOP CKE CLK lo, MOSI 0 (b8) -$0FFFDF NOP CKE CLK hi -$0FFFE0 NOP CKE CLK lo, MOSI 0 (b7) -$0FFFE1 NOP CKE CLK hi -$0FFFE2 NOP CKE CLK lo, MOSI 0 (b6) -$0FFFE3 AREF CLK hi -$0FFFE4 NOP CKE CLK lo, MOSI 0 (b5) -$0FFFE5 NOP CKE CLK hi -$0FFFE6 NOP CKE CLK lo, MOSI 0 (b4) -$0FFFE7 NOP CKE CLK hi -$0FFFE8 NOP CKE CLK lo, MOSI 0 (b3) -$0FFFE9 NOP CKE CLK hi -$0FFFEA NOP CKE CLK lo, MOSI 0 (b2) -$0FFFEB AREF CLK hi -$0FFFEC NOP CKE CLK lo, MOSI 0 (b1) -$0FFFED NOP CKE CLK hi -$0FFFEE NOP CKE CLK lo, MOSI 0 (b0) -$0FFFEF NOP CKE CLK hi - -$0FFFF0-$0FFFFF Init: mode & ref 8 dummy clocks 2 -$0FFFF0 NOP CKE CLK lo, MOSIOE 0 -$0FFFF1 NOP CKE CLK hi -$0FFFF2 NOP CKE CLK lo -$0FFFF3 AREF CLK hi -$0FFFF4 NOP CKE CLK lo -$0FFFF5 NOP CKE CLK hi -$0FFFF6 NOP CKE CLK lo -$0FFFF7 NOP CKE CLK hi -$0FFFF8 NOP CKE CLK lo -$0FFFF9 NOP CKE CLK hi -$0FFFFA NOP CKE CLK lo -$0FFFFB AREF CLK hi -$0FFFFC NOP CKE CLK lo -$0FFFFD NOP CKE CLK hi -$0FFFFE NOP CKE CLK lo -$0FFFFF NOP CKE CLK hi - -$100000-$503FFF Write ROM data Shift in read data 3 -$100000 NOP CKE CLK lo -$100001 NOP CKE CLK hi, get b7:6 of $000000 -$100002 NOP CKE CLK lo -$100003 AREF CLK hi, get b5:4 of $000000 -$100004 NOP CKE CLK lo -$100005 ACT CLK hi, get b3:2 of $000000 -$100006 NOP CKE CLK lo -$100007 WR AP CLK hi, get b1:0 of $000000 -$100008 NOP CKE CLK lo -$100009 NOP CKE CLK hi, get b7:6 of $000001 -$10000A NOP CKE CLK lo -$10000B AREF CLK hi, get b5:4 of $000001 -$10000C NOP CKE CLK lo -$10000D ACT CLK hi, get b3:2 of $000001 -$10000E NOP CKE CLK lo -$10000F WR AP CLK hi, get b1:0 of $000001 -... -$503FF0 NOP CKE CLK lo -$503FF1 NOP CKE CLK hi, get b7:6 of $0807FE -$503FF2 NOP CKE CLK lo -$503FF3 AREF CLK hi, get b5:4 of $0807FE -$503FF4 NOP CKE CLK lo -$503FF5 ACT CLK hi, get b3:2 of $0807FE -$503FF6 NOP CKE CLK lo -$503FF7 WR AP CLK hi, get b1:0 of $0807FE -$503FF8 NOP CKE CLK lo -$503FF9 NOP CKE CLK hi, get b7:6 of $0807FF -$503FFA NOP CKE CLK lo -$503FFB AREF CLK hi, get b5:4 of $0807FF -$503FFC NOP CKE CLK lo -$503FFD ACT CLK hi, get b3:2 of $0807FF -$503FFE NOP CKE CLK lo -$503FFF WR AP CLK hi, get b1:0 of $0807FF - -$504000 NOP CKE CLK lo, /CS hi 3 -$504001 NOP CKE CLK lo, /CS hi 3 -$504002 NOP CKE CLK lo, /CS hi 3 SDRAMActv <= InitActv && ~InitInterrupted -... -$5F5E0F flip 1hz, wrap - - - - - - - - - - - - - - - - - - - - - - Init sequence Init State SDRAM Flash IS Other @@ -191,7 +30,7 @@ $0FFBE NOP CKE CLK lo, MOSI 1 (b0) $0FFBF NOP CKE CLK hi $0FFC0-$0FFEF Init: mode & ref Send address ($000000) 2 -$0FFC0 NOP CKE CLK lo, MOSI 0 (b23) +$0FFC0 NOP CKE CLK lo, MOSI 0 (b23) $0FFC1 NOP CKE CLK hi $0FFC2 NOP CKE CLK lo, MOSI 0 (b22) $0FFC3 AREF CLK hi diff --git a/Documentation/Settings b/Documentation/Settings index 518fbe1..b16569d 100644 --- a/Documentation/Settings +++ b/Documentation/Settings @@ -1,7 +1,6 @@ GR8RAM Settings (not applicable to Library Card!) Settings[15] SetValid (1 = invalid, 0 = valid) -Settings[14] SetFW[1] (1 = RAMFactor, 0 = Slinky) -Settings[13] SetFW[0] -Settings[12] SetLim8M -Settings[11:0] Reserved \ No newline at end of file +Settings[14] SetFW (1 = RAMFactor, 0 = Slinky) +Settings[13] SetLim8M +Settings[12:0] Reserved \ No newline at end of file diff --git a/Documentation/UFM Load b/Documentation/UFM Load index 15398c9..af91c7d 100644 --- a/Documentation/UFM Load +++ b/Documentation/UFM Load @@ -78,62 +78,30 @@ $1004 0 0 1 1 SetLoaded <= Dout $1005 0 0 1 1 $1006 0 0 0 1 $1007 0 0 0 1 -$1008 0 0 1 1 latch DR[14] (nSetFW[1]) +$1008 0 0 1 1 latch DR[14] (SetFW) $1009 0 0 1 1 $100A 0 0 0 1 $100B 0 0 0 1 -$100C 0 0 1 1 latch DR[13] (nSetFW[0]) -$100D 0 0 1 1 -$100E 0 0 0 1 -$100F 0 0 0 1 -$1010 0 0 0 1 latch DR[12] (nSetLim8M) -$1011 0 0 0 1 -$1012 0 0 0 1 -$1013 0 0 0 1 -$1014 0 0 0 1 -$1015 0 0 0 1 -$1016 0 0 0 1 -$1017 0 0 0 1 -$1018 0 0 0 1 -$1019 0 0 0 1 -$101A 0 0 0 1 -$101B 0 0 0 1 -$101C 1 0 0 1 Increment address -$101D 1 0 0 1 -$101E 0 0 0 1 -$101F 0 0 0 1 +$100C 1 0 0 1 latch DR[13] (SetLim8M) +$100D 1 0 0 1 +$100E 0 0 0 0 +$100F 0 0 0 0 ... -$2FE0 0 0 1 0 parallel load into DR -$2FE1 0 0 1 0 -$2FE2 0 0 0 1 -$2FE3 0 0 0 1 -$2FE4 0 0 1 1 SetLoaded <= Dout -$2FE5 0 0 1 1 -$2FE6 0 0 0 1 -$2FE7 0 0 0 1 -$2FE8 0 0 1 1 latch DR[14] (nSetFW[1]) -$2FE9 0 0 1 1 -$2FEA 0 0 0 1 -$2FEB 0 0 0 1 -$2FEC 0 0 1 1 latch DR[13] (nSetFW[0]) -$2FED 0 0 1 1 -$2FEE 0 0 0 1 -$2FEF 0 0 0 1 -$2FF0 0 0 0 1 latch DR[12] (nSetLim8M) -$2FF1 0 0 0 1 -$2FF2 0 0 0 1 -$2FF3 0 0 0 1 -$2FF4 0 0 0 1 -$2FF5 0 0 0 1 -$2FF6 0 0 0 1 -$2FF7 0 0 0 1 -$2FF8 0 0 0 1 -$2FF9 0 0 0 1 -$2FFA 0 0 0 1 -$2FFB 0 0 0 1 -$2FFC 1 0 0 1 Increment address -$2FFD 1 0 0 1 -$2FFE 0 0 0 1 -$2FFF 0 0 0 1 +$1FF0 0 0 1 0 parallel load into DR +$1FF1 0 0 1 0 +$1FF2 0 0 0 1 +$1FF3 0 0 0 1 +$1FF4 0 0 1 1 SetLoaded <= Dout +$1FF5 0 0 1 1 +$1FF6 0 0 0 1 +$1FF7 0 0 0 1 +$1FF8 0 0 1 1 latch DR[14] (SetFW) +$1FF9 0 0 1 1 +$1FFA 0 0 0 1 +$1FFB 0 0 0 1 +$1FFC 1 0 0 1 latch DR[13] (SetLim8M) +$1FFD 1 0 0 1 +$1FFE 0 0 0 0 +$1FFF 0 0 0 0 -$3000 0 0 0 0 Everything 0, set SetLoaded +$2000 0 0 0 0 Everything 0, set SetLoaded diff --git a/cpld/GR8RAM.v b/cpld/GR8RAM.v index f2c95cb..208b090 100644 --- a/cpld/GR8RAM.v +++ b/cpld/GR8RAM.v @@ -1,8 +1,6 @@ -module GR8RAM(C25M, PHI0, nBOD, nRES, +module GR8RAM(C25M, PHI0, nBOD, nRES, nRESout, nIOSEL, nDEVSEL, nIOSTRB, - RA, nWE, RAdir, - RD, RDdir, - DMAin, DMAout, INTin, INTout, nRESout, + RA, nWE, RAdir, RD, RDdir, SBA, SA, nRCS, nRAS, nCAS, nSWE, DQML, DQMH, RCKE, SD, nFCS, FCK, MISO, MOSI); @@ -14,50 +12,46 @@ module GR8RAM(C25M, PHI0, nBOD, nRES, always @(posedge C25M) begin PHI0r1 <= PHI0r0; PHI0r2 <= PHI0r1; end /* Reset/brown-out detect synchronized inputs */ - /* Outputs: nRESr, nPBODr, nBODf */ + /* Outputs: nRESr, nBODf */ input nRES, nBOD; reg nRESr0, nRESr; reg nBODr0, nBODr, nBODf0, nBODf; + always @(negedge C25M) begin nBODr0 <= nBOD; nRESr0 <= nRES; end + always @(posedge C25M) begin nBODr <= nBODr0; nRESr <= nRESr0; end always @(posedge C25M) begin - // Double-synchronize nBOD, nPBOD, nRES - nBODr0 <= nBOD; nRESr0 <= nRES; - nBODr <= nBODr0; nRESr <= nRESr0; - // Filter nBODr to get nBODf. Output hi when hi for $10000 cycles - if (LS[15:0]==16'hFFFF) begin // When LS low-order is $FFFF + if (LS[15:0]==16'hFF00) begin // When LS low-order is $FFF0 nBODf0 <= nBODr; // "Precharge" nBODf0 - nBODf <= nBODf0; // "Evaluate" computed nBODf0 into nBODf + nBODf <= nBODf0; // Move computed nBODf0 into nBODf end else if (nBODr) begin // Else AND nBODf0 with nBODr - nBODf0 <= nBODf0 && nBODr; + nBODf0 <= nBODf0 && nBODr; // "Evaluate" by ANDing end end /* Long state counter: counts from 0 to $3FFFF */ - /* Outputs: LS, CSec */ + /* Outputs: LS */ reg [17:0] LS = 0; - always @(posedge C25M) begin - LS <= LS+1; - end + always @(posedge C25M) begin LS <= LS+1; end /* Init state */ output reg nRESout = 0; reg InitActv = 0; reg InitIntr = 0; - reg CmdActv = 0; reg SDRAMActv = 0; always @(posedge C25M) begin if (~nBODf) begin nRESout <= 0; InitIntr <= 1; - CmdActv <= 0; - end else if (LS[17:0]==18'h0FF10) begin - InitActv <= ~CmdActv; + end else if (~nRESr && LS[17:0]==18'h0FF00) begin + nRESout <= 0; + InitActv <= 1; InitIntr <= 0; - end else if (LS[17:0]==18'h30010) begin - nRESout <= InitActv && ~InitIntr; + end else if (LS[17:0]==18'h30002) begin InitActv <= 0; - CmdActv <= InitActv && ~InitIntr; - if (InitActv && ~InitIntr) SDRAMActv <= 1; + if (InitActv && ~InitIntr) begin + SDRAMActv <= 1; + nRESout <= 1; + end end end @@ -74,11 +68,6 @@ module GR8RAM(C25M, PHI0, nBOD, nRES, DEVSELr <= DEVSELr0; IOSELr <= IOSELr0; IOSTRBr <= IOSTRBr0; end - /* DMA/IRQ daisy chain */ - input DMAin, INTin; - output DMAout = DMAin; - output INTout = INTin; - /* Apple address bus */ /* Outputs: RACr, RAcur, nWEcur, RAdir */ input [15:0] RA; @@ -87,7 +76,7 @@ module GR8RAM(C25M, PHI0, nBOD, nRES, reg [11:0] RAcur; reg nWEcur; output RAdir = 1; always @(posedge C25M) begin - if (S==0 && PHI0r1 && ~PHI0r2) begin + if (PSStart) begin RACr <= RA[15:12]==4'hC; RAcur[11:0] <= RA[11:0]; nWEcur <= nWE; @@ -95,17 +84,11 @@ module GR8RAM(C25M, PHI0, nBOD, nRES, end /* Apple select signals */ - /* Outputs: ROMSpecRD, RAMSpecSEL, RAMSpecRD, RAMSpecWR, RAMSEL */ + /* Outputs: ROMSpecRD, RAMSpecSEL, RAMSpecRD, RAMSpecWR */ wire ROMSpecRD = RACr && RAcur[11:8]!=4'h0 && nWEcur; - wire RAMSpecSEL = RACr && RAcur[11:8]==4'h0 && RAcur[3:0]==4'h3; + wire RAMSpecSEL = RACr && RAcur[11:8]==4'h0 && RAcur[7] && RAcur[3:0]==4'h3; wire RAMSpecRD = RAMSpecSEL && nWEcur; wire RAMSpecWR = RAMSpecSEL && ~nWEcur; - reg RAMSEL = 0; - wire RAMWR = RAMSEL && ~nWEcur; - always @(posedge C25M) begin - if (S==5) RAMSEL <= RAMSpecSEL && DEVSELr; - else if (S==0) RAMSEL <= 0; - end /* IOROMEN and REGEN control */ reg IOROMEN = 0; @@ -114,9 +97,9 @@ module GR8RAM(C25M, PHI0, nBOD, nRES, if (~nRESr) begin IOROMEN <= 0; REGEN <= 0; - end else if (S==7 && IOSTRBr && RAcur[10:0]==11'h7FF) begin + end else if (PS==7 && IOSTRBr && RAcur[10:0]==11'h7FF) begin IOROMEN <= 0; - end else if (S==7 && IOSELr) begin + end else if (PS==7 && IOSELr) begin IOROMEN <= 1; REGEN <= 1; end @@ -125,9 +108,8 @@ module GR8RAM(C25M, PHI0, nBOD, nRES, /* Apple data bus */ inout [7:0] RD = RDdir ? 8'bZ : RDout[7:0]; reg [7:0] RDout; - reg RDOE = 0; - output RDdir = ~((~nDEVSEL || ~nIOSEL || (~nIOSTRB && IOROMEN)) && - PHI0 && PHI0r2 && nWE && RDOE && nBODf); + output RDdir = ~(PHI0 && PHI0r2 && nWE && nRESr && + ((~nDEVSEL && REGEN) || ~nIOSEL || (~nIOSTRB && IOROMEN))); /* Slinky address registers */ reg [23:0] Addr = 0; @@ -138,26 +120,25 @@ module GR8RAM(C25M, PHI0, nBOD, nRES, if (~nRESr) begin Addr[23:20] <= SetFW[1] ? 4'h0 : 4'hF; Addr[19:0] <= 20'h00000; - end else if (S==7 && DEVSELr) begin - if (AddrHSpecSEL && ~nWEcur) begin - Addr[23:16] <= { SetFW[1] ? RD[7:4] : 4'hF, RD[3:0] }; - end else if ((RAMSEL && Addr[15:0]==16'hFFFF) || - (AddrMSpecSEL && Addr[15] && ~RD[7] && ~nWEcur) || - (AddrLSpecSEL && Addr[7] && ~RD[7] && Addr[15:8]==8'hFF && ~nWEcur)) begin - Addr[23:16] <= Addr[23:16]+1; - end - - if (AddrMSpecSEL && ~nWEcur) begin - Addr[15:8] <= RD[7:0]; - end else if ((RAMSEL && Addr[7:0]==8'hFF) || - (AddrLSpecSEL && Addr[7] && ~RD[7] && ~nWEcur)) begin - Addr[15:8] <= Addr[15:8]+1; - end - - if (AddrLSpecSEL && ~nWEcur) begin + end else if (PS==7 && REGEN && DEVSELr) begin + if (RAMSpecSEL) begin + if (SetFW[1]) Addr[23:0] <= Addr[23:0]+1; + else Addr[23:0] <= { 4'hF, Addr[19:0]+1 }; + end else if (AddrLSpecSEL && ~nWEcur) begin Addr[7:0] <= RD[7:0]; - end else if (RAMSEL) begin - Addr[7:0] <= Addr[7:0]+1; + if (~RD[7] && Addr[7]) begin + if (SetFW[1]) Addr[23:8] <= Addr[23:8]+1; + else Addr[23:8] <= { 4'hF, Addr[19:8]+1 }; + end + end else if (AddrMSpecSEL && ~nWEcur) begin + Addr[15:8] <= RD[7:0]; + if (~RD[7] && Addr[15]) begin + if (SetFW[1]) Addr[23:16] <= Addr[23:16]+1; + else Addr[23:16] <= { 4'hF, Addr[19:16]+1 }; + end + end else if (AddrHSpecSEL && ~nWEcur) begin + if (SetFW[1]) Addr[23:16] <= RD[7:0]; + else Addr[23:16] <= { 4'hF, RD[3:0] }; end end end @@ -166,9 +147,8 @@ module GR8RAM(C25M, PHI0, nBOD, nRES, reg [1:0] Bank = 0; wire BankSpecSEL = RAcur[3:0]==4'hF; always @(posedge C25M) begin - if (~nRESr) begin - Bank <= 0; - end else if (S==7 && DEVSELr && BankSpecSEL && ~nWEcur) begin + if (~nRESr) Bank <= 0; + else if (PS==7 && DEVSELr && BankSpecSEL && ~nWEcur) begin Bank[1:0] <= RD[1:0]; end end @@ -185,35 +165,35 @@ module GR8RAM(C25M, PHI0, nBOD, nRES, /* SPI flash control */ always @(posedge C25M) begin - FCK <= FCKEN && LS[0]; + FCK <= (FCKEN && LS[0]) || (nRESr && FCKEN); end always @(posedge C25M) begin if (InitActv) begin - // Pulse clock from init states $0FFC0 to $2FFFF - if (LS[17:0]==18'h0FFB0) FCKEN <= 1'b0; - else if (LS[17:0]==18'h0FFC0) FCKEN <= 1'b1; - else if (LS[17:0]==18'h30000) FCKEN <= 1'b0; - // Flash /CS enabled from init states $0FFB0 to $2FFFF - if (LS[17:0]==18'h0FFA0) FCS <= 1'b0; - else if (LS[17:0]==18'h0FFB0) FCS <= 1'b1; + if (LS[17:0]==18'h0FF90) FCS <= 1'b0; + else if (LS[17:0]==18'h0FFA0) FCS <= 1'b1; else if (LS[17:0]==18'h30000) FCS <= 1'b0; + // Pulse clock from init states $0FFC0 to $2FFFF + if (LS[17:0]==18'h0FF90) FCKEN <= 1'b0; + else if (LS[17:0]==18'h0FFB0) FCKEN <= 1'b1; + else if (LS[17:0]==18'h30000) FCKEN <= 1'b0; + // Send command $3B (read) (MSB first) - /*if (LS[17:0]==18'h0FFB0 || LS[17:0]==18'h0FFB1) MOSIout <= 0; + if (LS[17:0]==18'h0FFB0 || LS[17:0]==18'h0FFB1) MOSIout <= 0; else if (LS[17:0]==18'h0FFB2 || LS[17:0]==18'h0FFB3) MOSIout <= 0; - else*/ if (LS[17:0]==18'h0FFB4 || LS[17:0]==18'h0FFB5) MOSIout <= 1; + else if (LS[17:0]==18'h0FFB4 || LS[17:0]==18'h0FFB5) MOSIout <= 1; else if (LS[17:0]==18'h0FFB6 || LS[17:0]==18'h0FFB7) MOSIout <= 1; else if (LS[17:0]==18'h0FFB8 || LS[17:0]==18'h0FFB9) MOSIout <= 1; - /*else if (LS[17:0]==18'h0FFBA || LS[17:0]==18'h0FFBB) MOSIout <= 0;*/ + else if (LS[17:0]==18'h0FFBA || LS[17:0]==18'h0FFBB) MOSIout <= 0; else if (LS[17:0]==18'h0FFBC || LS[17:0]==18'h0FFBD) MOSIout <= 1; else if (LS[17:0]==18'h0FFBE || LS[17:0]==18'h0FFBF) MOSIout <= 1; // Send 24-bit address (MSB first) - /*else if (LS[17:0]==18'h0FFC0 || LS[17:0]==18'h0FFC1) MOSIout <= 0; - else if (LS[17:0]==18'h0FFC2 || LS[17:0]==18'h0FFC3) MOSIout <= 0;*/ - else if (LS[17:0]==18'h0FFC4 || LS[17:0]==18'h0FFC5) MOSIout <= SetFW[1]; - else if (LS[17:0]==18'h0FFC6 || LS[17:0]==18'h0FFC7) MOSIout <= SetFW[0]; - /*else if (LS[17:0]==18'h0FFC8 || LS[17:0]==18'h0FFC9) MOSIout <= 0; + else if (LS[17:0]==18'h0FFC0 || LS[17:0]==18'h0FFC1) MOSIout <= 0; + else if (LS[17:0]==18'h0FFC2 || LS[17:0]==18'h0FFC3) MOSIout <= 0; + else if (LS[17:0]==18'h0FFC4 || LS[17:0]==18'h0FFC5) MOSIout <= 0; + else if (LS[17:0]==18'h0FFC6 || LS[17:0]==18'h0FFC7) MOSIout <= SetFW; + else if (LS[17:0]==18'h0FFC8 || LS[17:0]==18'h0FFC9) MOSIout <= 0; else if (LS[17:0]==18'h0FFCA || LS[17:0]==18'h0FFCB) MOSIout <= 0; else if (LS[17:0]==18'h0FFCC || LS[17:0]==18'h0FFCD) MOSIout <= 0; else if (LS[17:0]==18'h0FFCE || LS[17:0]==18'h0FFCF) MOSIout <= 0; @@ -232,25 +212,22 @@ module GR8RAM(C25M, PHI0, nBOD, nRES, else if (LS[17:0]==18'h0FFE8 || LS[17:0]==18'h0FFE9) MOSIout <= 0; else if (LS[17:0]==18'h0FFEA || LS[17:0]==18'h0FFEB) MOSIout <= 0; else if (LS[17:0]==18'h0FFEC || LS[17:0]==18'h0FFED) MOSIout <= 0; - else if (LS[17:0]==18'h0FFEE || LS[17:0]==18'h0FFEF) MOSIout <= 0;*/ + else if (LS[17:0]==18'h0FFEE || LS[17:0]==18'h0FFEF) MOSIout <= 0; else MOSIout <= 0; - if (LS[17:0]==18'h0FFA0) MOSIOE <= 1'b0; - else if (LS[17:0]==18'h0FFB0) MOSIOE <= 1'b1; + if (LS[17:0]==18'h0FF90) MOSIOE <= 1'b1; else if (LS[17:0]==18'h0FFF0) MOSIOE <= 1'b0; - end else if (CmdActv) begin + end else if (nRESr) begin //TODO: control these with Apple II FCS <= 0; FCKEN <= 0; MOSIout <= 0; MOSIOE <= 0; - //TODO? sample nMenu when MOSI not outputting? end end /* UFM control */ reg ARCLK = 0; // UFM address register clock - // UFM address register data input tied to 0 reg ARShift = 0; // 1 to Shift UFM address in, 0 to increment reg DRCLK = 0; // UFM data register clock reg DRDIn = 0; // UFM data register input @@ -280,16 +257,14 @@ module GR8RAM(C25M, PHI0, nBOD, nRES, reg UFMBr = 0; // UFMBusy registered to sync with C25M reg RTPBr0 = 0; // RTPBusy registered to sync with C25M reg RTPBr = 0; // RTPBusy registered to sync with C25M - always @(posedge C25M) begin - UFMBr <= UFMBr0; UFMBr0 <= UFMB; - RTPBr <= RTPBr0; RTPBr0 <= RTPB; - end + always @(negedge C25M) begin UFMBr0 <= UFMB; RTPBr0 <= RTPB; end + always @(posedge C25M) begin UFMBr <= UFMBr0; RTPBr <= RTPBr0; end reg SetLoaded = 0; reg [1:0] SetFW; reg SetLim8M; always @(posedge C25M) begin if (~SetLoaded) begin - if (LS[15:0]<=16'h0FBF) begin + if (LS[15:0]<=16'h0FB0) begin ARCLK <= 0; ARShift <= 1; DRCLK <= 0; @@ -301,106 +276,61 @@ module GR8RAM(C25M, PHI0, nBOD, nRES, DRShift <= 0; SetFW[1:0] <= 2'b11; SetLim8M <= 1'b1; - end else if (LS[15:0]<=16'h2FFF) begin - if (LS[4:0]==5'h00 || LS[4:0]==5'h01) begin - ARCLK <= 0; - ARShift <= 0; - DRCLK <= 1; - DRShift <= 0; - end else if (LS[4:0]==5'h02 || LS[4:0]==5'h03) begin - ARCLK <= 0; - ARShift <= 0; - DRCLK <= 0; - DRShift <= 1; - end else if (LS[4:0]==5'h04 || LS[4:0]==5'h05) begin - ARCLK <= 0; - ARShift <= 0; - DRCLK <= 1; - DRShift <= 1; - if (LS[4:0]==5'h04 && DRDOut) SetLoaded <= 1; - end else if (LS[4:0]==5'h06 || LS[4:0]==5'h07) begin - ARCLK <= 0; - ARShift <= 0; - DRCLK <= 0; - DRShift <= 1; - end else if (LS[4:0]==5'h08 || LS[4:0]==5'h09) begin - ARCLK <= 0; - ARShift <= 0; - DRCLK <= 1; - DRShift <= 1; - if (LS[4:0]==5'h08) SetFW[1] <= DRDOut; - end else if (LS[4:0]==5'h0A || LS[4:0]==5'h0B) begin - ARCLK <= 0; - ARShift <= 0; - DRCLK <= 0; - DRShift <= 1; - end else if (LS[4:0]==5'h0C || LS[4:0]==5'h0D) begin - ARCLK <= 0; - ARShift <= 0; - DRCLK <= 1; - DRShift <= 1; - if (LS[4:0]==5'h0C) SetFW[0] <= DRDOut; - end else if (LS[4:0]==5'h0E || LS[4:0]==5'h0F) begin - ARCLK <= 0; - ARShift <= 0; - DRCLK <= 0; - DRShift <= 1; - end else if (LS[4:0]==5'h10 || LS[4:0]==5'h11) begin - ARCLK <= 0; - ARShift <= 0; - DRCLK <= 0; - DRShift <= 1; - if (LS[4:0]==5'h10) SetLim8M <= DRDOut; - end else if (LS[4:0]==5'h12 || LS[4:0]==5'h13) begin - ARCLK <= 0; - ARShift <= 0; - DRCLK <= 0; - DRShift <= 1; - end else if (LS[4:0]==5'h14 || LS[4:0]==5'h15) begin - ARCLK <= 0; - ARShift <= 0; - DRCLK <= 0; - DRShift <= 1; - end else if (LS[4:0]==5'h16 || LS[4:0]==5'h17) begin - ARCLK <= 0; - ARShift <= 0; - DRCLK <= 0; - DRShift <= 1; - end else if (LS[4:0]==5'h18 || LS[4:0]==5'h19) begin - ARCLK <= 0; - ARShift <= 0; - DRCLK <= 0; - DRShift <= 1; - end else if (LS[4:0]==5'h1A || LS[4:0]==5'h1B) begin - ARCLK <= 0; - ARShift <= 0; - DRCLK <= 0; - DRShift <= 1; - end else if (LS[4:0]==5'h1C || LS[4:0]==5'h1D) begin - ARCLK <= 1; - ARShift <= 0; - DRCLK <= 0; - DRShift <= 1; - end else if (LS[4:0]==5'h1E || LS[4:0]==5'h1F) begin - ARCLK <= 0; - ARShift <= 0; - DRCLK <= 0; - DRShift <= 1; - end + end else if (LS[15:0]<=16'h1FFF) begin + case (LS[3:1]) + 3'h0: begin + ARCLK <= 0; + ARShift <= 0; + DRCLK <= 1; + DRShift <= 0; + end 3'h1: begin + ARCLK <= 0; + ARShift <= 0; + DRCLK <= 0; + DRShift <= 1; + end 3'h2: begin + ARCLK <= 0; + ARShift <= 0; + DRCLK <= 1; + DRShift <= 1; + if (LS[3:0]==4'h2 && DRDOut) SetLoaded <= 1; + end 3'h3: begin + ARCLK <= 0; + ARShift <= 0; + DRCLK <= 0; + DRShift <= 1; + end 3'h4: begin + ARCLK <= 0; + ARShift <= 0; + DRCLK <= 1; + DRShift <= 1; + if (LS[3:0]==4'h4) SetFW <= DRDOut; + end 3'h5: begin + ARCLK <= 0; + ARShift <= 0; + DRCLK <= 0; + DRShift <= 1; + end 3'h6: begin + ARCLK <= 1; + ARShift <= 0; + DRCLK <= 0; + DRShift <= 1; + if (LS[3:0]==4'h6) SetLim8M <= DRDOut; + end 3'h7: begin + ARCLK <= 0; + ARShift <= 0; + DRCLK <= 0; + DRShift <= 0; + end + endcase end else SetLoaded <= 1; DRDIn <= 0; - end else if (CmdActv) begin + end else if (PS==7 /* && ... FIXME */) begin ARCLK <= 0; ARShift <= 0; DRShift <= 1; - DRCLK <= 0; - DRDIn <= 0; - end else begin - ARCLK <= 0; - ARShift <= 0; - DRShift <= 1; DRCLK <= 0; DRDIn <= 0; end @@ -412,25 +342,18 @@ module GR8RAM(C25M, PHI0, nBOD, nRES, reg SDOE = 0; always @(posedge C25M) begin // Shift { MISO, MOSI } in when InitActv. When ready, synchronize RD - if (InitActv) if (LS[1]) WRD[7:0] <= { MISO, MOSI, WRD[5:0] }; - else WRD[7:0] <= RD[7:0]; + if (InitActv && LS[1]) WRD[7:0] <= { MISO, MOSI, WRD[5:0] }; + else if (PS==8) WRD[7:0] <= RD[7:0]; // Output data on SDRAM data bus only during init and when writing - SDOE <= InitActv || (RAMSEL && nWEcur && S==6); + SDOE <= InitActv || (RAMSpecWR && PS==8); end - /* State counters */ - reg [3:0] S = 0; + reg [2:0] PS = 0; + wire PSStart = ~InitActv && nRESr && PS==0 && PHI0r1 && ~PHI0r2; always @(posedge C25M) begin - if (~InitActv && SDRAMActv && S==0 && PHI0r1 && ~PHI0r2 && nRESr && nBODf) S <= 1; - else if (S==0) S <= 0; - else S <= S+1; - end - - /* Refresh state */ - reg RefDone = 0; - always @(posedge C25M) begin - if (LS[6:0]==7'h00) RefDone <= 0; // Reset RefDone every 128 C25M cycles (5.12 us) - else if (S==0 && ~RefDone && ~(PHI0r1 && ~PHI0r2)) RefDone <= 1; + if (PSStart) PS <= 1; + else if (PS==0) PS <= 0; + else PS <= PS+1; end reg [1:0] IS = 0; @@ -442,325 +365,295 @@ module GR8RAM(C25M, PHI0, nBOD, nRES, end else IS <= 0; end + /* Refresh state */ + reg RefReqd = 0; + reg RefReady = 0; + always @(posedge C25M) begin + if (LS[6:0]==7'h00) RefReqd <= SDRAMActv; // Reset RefDone every 128 C25M cycles (5.12 us) + else if (PS==0 && ~RefReqd) RefReqd <= 0; + end + /* SDRAM address/command */ - output reg [1:0] SBA; - output reg [12:0] SA; + output [1:0] SBA; assign SBA[1:0] = + Amux[2:0]==2'h0 ? 2'b00 : // mode register / "all" + Amux[2:0]==2'h1 ? 2'b00 : // FIXME: init row / col + Amux[2:0]==2'h2 ? 2'b10 : // ROM row / col + /* 2'h3 */ { 1'b0, Addr[23] }; // RAM col + output [12:0] SA; assign SA[12:0] = + Amux[2:0]==3'h0 ? 13'b0001000100000 : // mode register + Amux[2:0]==3'h1 ? 13'b0011000100000 : // "all" + Amux[2:0]==3'h2 ? 13'b0011000100000 : // FIXME: init row + Amux[2:0]==3'h3 ? 13'b0011000100000 : // FIXME: init col + Amux[2:0]==3'h4 ? { 9'b000000000, Bank[1:0], RAcur[11:10] } : // ROM row + Amux[2:0]==3'h5 ? { 4'b0000, RAcur[9:1]} : // ROM col + Amux[2:0]==3'h6 ? { Addr[22:10] } : // RAM row + /* 3'h7 */ { 4'b0000, Addr[9:1] }; // RAM col + output DQML; assign DQML = + Amux[2:0]==3'h0 ? 1'b1 : // mode register + Amux[2:0]==3'h1 ? 1'b1 : // "all" + Amux[2:0]==3'h2 ? 1'b1 : // FIXME: init row + Amux[2:0]==3'h3 ? LS[3] : // FIXME: init col + Amux[2:0]==3'h4 ? 1'b1 : // ROM row + Amux[2:0]==3'h5 ? RAcur[0]: // ROM col + Amux[2:0]==3'h6 ? 1'b1 : // RAM row + /* 3'h7 */ Addr[0]; // RAM col + output DQMH; assign DQMH = + Amux[2:0]==3'h0 ? 1'b1 : // mode register + Amux[2:0]==3'h1 ? 1'b1 : // "all" + Amux[2:0]==3'h2 ? 1'b1 : // FIXME: init row + Amux[2:0]==3'h3 ? ~LS[3] : // FIXME: init col + Amux[2:0]==3'h4 ? 1'b1 : // ROM row + Amux[2:0]==3'h5 ? ~RAcur[0]: // ROM col + Amux[2:0]==3'h6 ? 1'b1 : // RAM row + /* 3'h7 */ ~Addr[0]; // RAM col + reg [2:0] Amux = 0; output reg RCKE = 1; output reg nRCS = 1; output reg nRAS = 1; output reg nCAS = 1; output reg nSWE = 1; - output reg DQMH = 1; - output reg DQML = 1; always @(posedge C25M) begin - if (S==0 && InitActv) begin - if (IS[1:0]==2'h0) begin - // NOP CKE - RCKE <= 1'b1; - nRCS <= 1'b1; - nRAS <= 1'b1; - nCAS <= 1'b1; - nSWE <= 1'b1; - DQMH <= 1'b1; - DQML <= 1'b1; - SBA[1:0] <= 2'b00; - SA[12:11] <= 2'b00; - SA[10] <= 1'b1; - SA[9:0] <= 10'b1000100000; - end else if (IS[1:0]==2'h1) begin - if (LS[3:0]==4'h3) begin - // PC all - RCKE <= 1'b1; - nRCS <= 1'b0; - nRAS <= 1'b0; - nCAS <= 1'b1; - nSWE <= 1'b0; - DQMH <= 1'b1; - DQML <= 1'b1; - SA[10] <= 1'b1; // "all" - end else if (LS[3:0]==4'hB) begin - // Load mode register - RCKE <= 1'b1; - nRCS <= 1'b0; - nRAS <= 1'b0; - nCAS <= 1'b0; - nSWE <= 1'b0; - DQMH <= 1'b1; - DQML <= 1'b1; - SA[10] <= 1'b0; // reserved in mode register - end - SBA[1:0] <= 2'b00; // reserved in mode register - SA[12:11] <= 2'b00; // reserved in mode register - SA[9] <= 1'b1; // single write mode - SA[8] <= 1'b0; // reserved in mode register - SA[7] <= 1'b0; // don't enter test mode - SA[6:4] <= 2'b010; // CAS latency 2 - SA[3] <= 1'b0; // sequential addressing mode - SA[2:0] <= 3'b000; // burst length 1 - end else if (IS[1:0]==2'h2) begin - if (LS[2:0]==3'h3) begin - // AREF - RCKE <= 1'b1; - nRCS <= 1'b0; - nRAS <= 1'b0; - nCAS <= 1'b0; - nSWE <= 1'b1; - DQMH <= 1'b1; - DQML <= 1'b1; - end else begin + case (PS[2:0]) + 0: begin + if (InitActv) begin + case (IS[1:0]) + 0: begin + // NOP CKE + RCKE <= 1'b1; + nRCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nSWE <= 1'b1; + Amux <= 3'b000; + end 1: begin + if (LS[3:0]==4'h3) begin + // PC all + RCKE <= 1'b1; + nRCS <= 1'b0; + nRAS <= 1'b0; + nCAS <= 1'b1; + nSWE <= 1'b0; + Amux <= 3'b001; + end else if (LS[3:0]==4'hB) begin + // Load mode + RCKE <= 1'b1; + nRCS <= 1'b0; + nRAS <= 1'b0; + nCAS <= 1'b0; + nSWE <= 1'b0; + Amux <= 3'b000; + end else begin + // NOP CKE + RCKE <= 1'b1; + nRCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nSWE <= 1'b1; + Amux <= 3'b000; + end + end 2: begin + if (LS[2:0]==3'h3) begin + // AREF + RCKE <= 1'b1; + nRCS <= 1'b0; + nRAS <= 1'b0; + nCAS <= 1'b0; + nSWE <= 1'b1; + Amux <= 3'b000; + end else begin + // NOP CKE + RCKE <= 1'b1; + nRCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nSWE <= 1'b1; + Amux <= 3'b000; + end + end 3: begin + if (LS[2:0]==3'h3) begin + // AREF + RCKE <= 1'b1; + nRCS <= 1'b0; + nRAS <= 1'b0; + nCAS <= 1'b0; + nSWE <= 1'b1; + Amux <= 3'b010; + end else if (LS[2:0]==3'h5) begin + // ACT + RCKE <= 1'b1; + nRCS <= 1'b0; + nRAS <= 1'b0; + nCAS <= 1'b1; + nSWE <= 1'b1; + Amux <= 3'b010; + end else if (LS[2:0]==3'h7) begin + // WR AP + RCKE <= 1'b1; + nRCS <= 1'b0; + nRAS <= 1'b1; + nCAS <= 1'b0; + nSWE <= 1'b0; + Amux <= 3'b011; + end else begin + // NOP CKE + RCKE <= 1'b1; + nRCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nSWE <= 1'b1; + Amux <= 3'b010; + end + end + endcase + end else if (PSStart) begin // NOP CKE RCKE <= 1'b1; nRCS <= 1'b1; nRAS <= 1'b1; nCAS <= 1'b1; nSWE <= 1'b1; - DQMH <= 1'b1; - DQML <= 1'b1; - end - SBA[1:0] <= 2'b10; - SA[12:11] <= 2'b00; - SA[10] <= 1'b1; - SA[9:0] <= 10'b1000100000; - end else if (IS[1:0]==2'h3) begin - if (LS[2:0]==3'h3) begin - // AREF - RCKE <= 1'b1; - nRCS <= 1'b0; - nRAS <= 1'b0; - nCAS <= 1'b0; + Amux <= 3'b001; + end else if (RefReqd) begin + if (RCKE) begin + // AREF + RCKE <= 1'b1; + nRCS <= 1'b0; + nRAS <= 1'b0; + nCAS <= 1'b0; + nSWE <= 1'b1; + Amux <= 3'b001; + end else begin + // NOP CKE + RCKE <= 1'b1; + nRCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nSWE <= 1'b1; + Amux <= 3'b001; + end + end else begin + // NOP CKD + RCKE <= 1'b0; + nRCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; nSWE <= 1'b1; - DQMH <= 1'b1; - DQML <= 1'b1; - SBA[1:0] <= 2'b10; - SA[12:11] <= 2'b00; - SA[10] <= 1'b1; - SA[9:0] <= 10'b1000100000; - end else if (LS[2:0]==3'h5) begin + Amux <= 3'b001; + end + end 1: begin + if (ROMSpecRD || RAMSpecSEL) begin // ACT RCKE <= 1'b1; nRCS <= 1'b0; nRAS <= 1'b0; nCAS <= 1'b1; nSWE <= 1'b1; - SBA[1:0] <= 1'b10; - SA[12:10] <= 3'b001; - SA[9:4] <= 10'b100010; - SA[3:0] <= { ~LS[17], LS[16:14] }; - DQMH <= 1'b1; - DQML <= 1'b1; - end else if (LS[2:0]==3'h7) begin - // WR auto-PC + end else begin + // NOP CKD + RCKE <= 1'b0; + nRCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nSWE <= 1'b1; + end + if (ROMSpecRD) Amux <= 3'b100; + else Amux <= 3'b110; + end 2: begin + if (ROMSpecRD || RAMSpecRD) begin + // RD RCKE <= 1'b1; nRCS <= 1'b0; - nRAS <= 1'b1; - nCAS <= 1'b0; - nSWE <= 1'b0; - SBA[1:0] <= 1'b10; - SA[12:11] <= 2'b00; // don't care - SA[10] <= 1'b1; // auto-precharge - SA[9:0] <= LS[13:4]; - DQML <= LS[3]; - DQMH <= ~LS[3]; + nRAS <= 1'b0; + nCAS <= 1'b1; + nSWE <= 1'b1; end else begin + // NOP CKD + RCKE <= 1'b0; + nRCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nSWE <= 1'b1; + end + + if (ROMSpecRD) Amux <= 3'b101; + else Amux <= 3'b111; + end 3: begin + if (ROMSpecRD || RAMSpecRD) begin // NOP CKE RCKE <= 1'b1; nRCS <= 1'b1; nRAS <= 1'b1; nCAS <= 1'b1; nSWE <= 1'b1; - DQMH <= 1'b1; - DQML <= 1'b1; - SBA[1:0] <= 2'b10; - SA[12:11] <= 2'b00; - SA[10] <= 1'b1; - SA[9:0] <= 10'b1000100000; - end - end - end else if (S==0 && ~RefDone) begin - // AREF - RCKE <= 1'b1; - nRCS <= 1'b0; - nRAS <= 1'b0; - nCAS <= 1'b0; - nSWE <= 1'b1; - DQMH <= 1'b1; - DQML <= 1'b1; - SBA[1:0] <= 2'b10; - SA[12:11] <= 2'b00; - SA[10] <= 1'b1; - SA[9:0] <= 10'b1000100000; - end else if (S==0) begin - // NOP CKE - RCKE <= 1'b1; - nRCS <= 1'b1; - nRAS <= 1'b1; - nCAS <= 1'b1; - nSWE <= 1'b1; - DQMH <= 1'b1; - DQML <= 1'b1; - SBA[1:0] <= 2'b10; - SA[12:11] <= 2'b00; - SA[10] <= 1'b1; - SA[9:0] <= 10'b1000100000; - end else if (S==4'h1) begin - if (ROMSpecRD || RAMSpecRD) begin - // ACT - RCKE <= 1'b1; - nRCS <= 1'b0; - nRAS <= 1'b0; - nCAS <= 1'b1; - nSWE <= 1'b1; - DQMH <= 1'b1; - DQML <= 1'b1; - end else begin - // NOP CKE - RCKE <= 1'b1; - nRCS <= 1'b1; - nRAS <= 1'b1; - nCAS <= 1'b1; - nSWE <= 1'b1; - DQMH <= 1'b1; - DQML <= 1'b1; - end - - if (RAMSpecRD) begin - SBA[1] <= 1'b0; - SBA[0] <= Addr[23] & ~SetLim8M; - SA[12:0] <= Addr[22:10]; - end else begin - SBA[1] <= 1'b1; - SBA[0] <= 1'b0; - SA[12:11] <= 2'b00; - SA[10] <= 1'b1; - SA[9:4] <= 10'b100010; - SA[9:1] <= Bank[1:0]; - SA[1:0] <= RAcur[11:10]; - end - end else if (S==4'h2) begin - if (ROMSpecRD || RAMSpecRD) begin - // RD auto-PC - RCKE <= 1'b1; - nRCS <= 1'b0; - nRAS <= 1'b1; - nCAS <= 1'b0; - nSWE <= 1'b1; - if (RAMSpecRD) begin - DQMH <= ~Addr[0]; - DQML <= Addr[0]; end else begin - DQMH <= ~RAcur[0]; - DQML <= RAcur[0]; + // NOP CKD + RCKE <= 1'b0; + nRCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nSWE <= 1'b1; end - end else begin - // NOP CKE - RCKE <= 1'b1; + Amux <= 3'b001; + end 4: begin + if (RAMSpecWR && DEVSELr) begin + // NOP CKE + RCKE <= 1'b1; + nRCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nSWE <= 1'b1; + end else begin + // NOP CKD + RCKE <= 1'b0; + nRCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nSWE <= 1'b1; + end + Amux <= 3'b001; + end 5: begin + if (RAMSpecWR && DEVSELr) begin + // WR AP + RCKE <= 1'b1; + nRCS <= 1'b0; + nRAS <= 1'b1; + nCAS <= 1'b0; + nSWE <= 1'b0; + end else begin + // NOP CKD + RCKE <= 1'b0; + nRCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nSWE <= 1'b1; + end + Amux <= 3'b111; + end 6: begin + // NOP CKE if ACT'd, else CKD + RCKE <= ROMSpecRD || RAMSpecSEL; nRCS <= 1'b1; nRAS <= 1'b1; nCAS <= 1'b1; nSWE <= 1'b1; - DQMH <= 1'b1; - DQML <= 1'b1; + Amux <= 3'b001; + end 7: begin + if (ROMSpecRD || RAMSpecSEL) begin + // PC all CKD + RCKE <= 1'b0; + nRCS <= 1'b0; + nRAS <= 1'b0; + nCAS <= 1'b1; + nSWE <= 1'b0; + end else begin + // NOP CKD + RCKE <= 1'b0; + nRCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nSWE <= 1'b1; + end + Amux <= 3'b001; end - - SA[12:11] <= 2'b00; // don't care - SA[10] <= 1'b1; // auto-precharge - SA[9] <= 1'b1; // don't care - if (RAMSpecRD) begin - SBA[1] <= 1'b0; - SBA[0] <= Addr[23]; - SA[8:0] <= Addr[9:1]; - end else begin - SBA[1] <= 1'b1; - SBA[0] <= 1'b0; - SA[8:0] <= RAcur[9:1]; - end - end else if (S==4'h3) begin - // NOP CKE - RCKE <= 1'B1; - nRCS <= 1'b1; - nRAS <= 1'b1; - nCAS <= 1'b1; - nSWE <= 1'b1; - DQMH <= 1'b1; - DQML <= 1'b1; - SBA[1:0] <= 2'b10; - SA[12:11] <= 2'b00; - SA[10] <= 1'b1; - SA[9:0] <= 10'b1000100000; - end else if (S==4'h4) begin - // NOP CKE - RCKE <= 1'b1; - nRCS <= 1'b1; - nRAS <= 1'b1; - nCAS <= 1'b1; - nSWE <= 1'b1; - DQMH <= 1'b1; - DQML <= 1'b1; - SBA[1] <= 1'b0; - SBA[0] <= Addr[23]; - SA[12:0] <= Addr[22:10]; - end else if (S==4'h5) begin - if (RAMSpecWR && DEVSELr) begin - // ACT - RCKE <= 1'b1; - nRCS <= 1'b0; - nRAS <= 1'b0; - nCAS <= 1'b1; - nSWE <= 1'b1; - DQMH <= 1'b1; - DQML <= 1'b1; - end else begin - // NOP CKE - RCKE <= 1'b1; - nRCS <= 1'b1; - nRAS <= 1'b1; - nCAS <= 1'b1; - nSWE <= 1'b1; - DQMH <= 1'b1; - DQML <= 1'b1; - end - SBA[1] <= 1'b0; - SBA[0] <= Addr[23]; - SA[12:0] <= Addr[22:10]; - end else if (S==4'h6) begin - if (RAMWR) begin - // WR auto-PC - RCKE <= 1'b1; - nRCS <= 1'b0; - nRAS <= 1'b1; - nCAS <= 1'b0; - nSWE <= 1'b0; - DQMH <= ~Addr[10]; - DQML <= Addr[10]; - end else begin - // NOP CKE - RCKE <= 1'b1; - nRCS <= 1'b1; - nRAS <= 1'b1; - nCAS <= 1'b1; - nSWE <= 1'b1; - DQMH <= 1'b1; - DQML <= 1'b1; - end - SBA[1] <= 1'b0; - SBA[0] <= Addr[23]; - SA[12:11] <= 2'b00; // don't care - SA[10] <= 1'b1; // auto-precharge - SA[9:0] <= Addr[9:0]; - end else if (S==4'h7) begin - // NOP CKE - RCKE <= 1'b1; - nRCS <= 1'b1; - nRAS <= 1'b1; - nCAS <= 1'b1; - nSWE <= 1'b1; - DQMH <= 1'b1; - DQML <= 1'b1; - SBA[1] <= 1'b0; - SBA[0] <= Addr[23]; - SA[12:11] <= 2'b00; // don't care - SA[10] <= 1'b1; // auto-precharge - SA[9:0] <= Addr[9:0]; - end + endcase end endmodule diff --git a/cpld/db/GR8RAM.(0).cnf.cdb b/cpld/db/GR8RAM.(0).cnf.cdb index e0d9099..602b5ce 100755 Binary files a/cpld/db/GR8RAM.(0).cnf.cdb and b/cpld/db/GR8RAM.(0).cnf.cdb differ diff --git a/cpld/db/GR8RAM.(0).cnf.hdb b/cpld/db/GR8RAM.(0).cnf.hdb index 18aa0ef..c010d84 100755 Binary files a/cpld/db/GR8RAM.(0).cnf.hdb and b/cpld/db/GR8RAM.(0).cnf.hdb differ diff --git a/cpld/db/GR8RAM.asm.qmsg b/cpld/db/GR8RAM.asm.qmsg index 27abf7e..aba5320 100755 --- a/cpld/db/GR8RAM.asm.qmsg +++ b/cpld/db/GR8RAM.asm.qmsg @@ -1,6 +1,6 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616056850427 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616056850443 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 18 04:40:50 2021 " "Processing started: Thu Mar 18 04:40:50 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616056850443 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1616056850443 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1616056850443 ""} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1616056851802 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1616056851833 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "293 " "Peak virtual memory: 293 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616056852411 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 18 04:40:52 2021 " "Processing ended: Thu Mar 18 04:40:52 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616056852411 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616056852411 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616056852411 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1616056852411 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616146132498 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616146132498 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 19 05:28:52 2021 " "Processing started: Fri Mar 19 05:28:52 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616146132498 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1616146132498 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1616146132498 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1616146133795 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1616146133889 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "293 " "Peak virtual memory: 293 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616146134545 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 19 05:28:54 2021 " "Processing ended: Fri Mar 19 05:28:54 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616146134545 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616146134545 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616146134545 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1616146134545 ""} diff --git a/cpld/db/GR8RAM.asm.rdb b/cpld/db/GR8RAM.asm.rdb index b84971f..dc1f18f 100755 Binary files a/cpld/db/GR8RAM.asm.rdb and b/cpld/db/GR8RAM.asm.rdb differ diff --git a/cpld/db/GR8RAM.cmp.cdb b/cpld/db/GR8RAM.cmp.cdb index 25204dc..a38118b 100755 Binary files a/cpld/db/GR8RAM.cmp.cdb and b/cpld/db/GR8RAM.cmp.cdb differ diff --git a/cpld/db/GR8RAM.cmp.hdb b/cpld/db/GR8RAM.cmp.hdb index 911a7ab..12e0ff7 100755 Binary files a/cpld/db/GR8RAM.cmp.hdb and b/cpld/db/GR8RAM.cmp.hdb differ diff --git a/cpld/db/GR8RAM.cmp.idb b/cpld/db/GR8RAM.cmp.idb index 9ebb049..96e47cf 100755 Binary files a/cpld/db/GR8RAM.cmp.idb and b/cpld/db/GR8RAM.cmp.idb differ diff --git a/cpld/db/GR8RAM.cmp.rdb b/cpld/db/GR8RAM.cmp.rdb index 09cbe67..6ad876c 100755 Binary files a/cpld/db/GR8RAM.cmp.rdb and b/cpld/db/GR8RAM.cmp.rdb differ diff --git a/cpld/db/GR8RAM.fit.qmsg b/cpld/db/GR8RAM.fit.qmsg index 97ecbf4..b4cb68f 100755 --- a/cpld/db/GR8RAM.fit.qmsg +++ b/cpld/db/GR8RAM.fit.qmsg @@ -1,58 +1,57 @@ -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1616136954485 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1616136954516 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1616136955094 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1616136955094 ""} -{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1616136955407 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1616136955438 ""} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1616136955813 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1616136955813 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1616136955813 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1616136955813 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1616136955813 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1616136955813 ""} -{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "73 73 " "No exact pin location assignment(s) for 73 pins of 73 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nIOSEL " "Pin nIOSEL not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nIOSEL } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 66 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nIOSEL } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 358 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nIOSTRB " "Pin nIOSTRB not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nIOSTRB } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 66 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nIOSTRB } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 360 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RAdir " "Pin RAdir not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RAdir } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 88 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RAdir } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 362 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RDdir " "Pin RDdir not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RDdir } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 130 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RDdir } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 363 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DMAout " "Pin DMAout not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { DMAout } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 79 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { DMAout } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 365 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "INTout " "Pin INTout not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { INTout } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 80 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { INTout } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 367 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nRESout " "Pin nRESout not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nRESout } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 43 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nRESout } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 203 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SBA\[0\] " "Pin SBA\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SBA[0] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 455 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SBA[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 64 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SBA\[1\] " "Pin SBA\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SBA[1] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 455 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SBA[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 62 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[0\] " "Pin SA\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[0] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 455 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 91 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[1\] " "Pin SA\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[1] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 455 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 89 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[2\] " "Pin SA\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[2] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 455 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 87 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[3\] " "Pin SA\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[3] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 455 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 84 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[4\] " "Pin SA\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[4] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 455 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 82 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[5\] " "Pin SA\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[5] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 455 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 80 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[6\] " "Pin SA\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[6] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 455 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 78 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[7\] " "Pin SA\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[7] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 455 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 76 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[8\] " "Pin SA\[8\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[8] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 455 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 74 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[9\] " "Pin SA\[9\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[9] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 455 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 72 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[10\] " "Pin SA\[10\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[10] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 455 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 70 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[11\] " "Pin SA\[11\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[11] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 455 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 68 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[12\] " "Pin SA\[12\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[12] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 455 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 66 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nRCS " "Pin nRCS not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nRCS } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 449 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nRCS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 323 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nRAS " "Pin nRAS not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nRAS } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 450 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nRAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 324 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nCAS " "Pin nCAS not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nCAS } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 451 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nCAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 325 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nSWE " "Pin nSWE not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nSWE } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 452 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nSWE } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 209 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DQML " "Pin DQML not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { DQML } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 454 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { DQML } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 236 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DQMH " "Pin DQMH not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { DQMH } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 453 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { DQMH } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 228 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RCKE " "Pin RCKE not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RCKE } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 448 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RCKE } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 322 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nFCS " "Pin nFCS not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nFCS } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 177 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nFCS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 368 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "FCK " "Pin FCK not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { FCK } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 179 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { FCK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 240 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "MOSI " "Pin MOSI not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { MOSI } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 181 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { MOSI } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 344 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[0\] " "Pin RD\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[0] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 126 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 140 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[1\] " "Pin RD\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[1] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 126 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 141 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[2\] " "Pin RD\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[2] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 126 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 142 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[3\] " "Pin RD\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[3] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 126 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 143 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[4\] " "Pin RD\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[4] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 126 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 144 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[5\] " "Pin RD\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[5] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 126 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 55 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[6\] " "Pin RD\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[6] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 126 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 57 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[7\] " "Pin RD\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[7] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 126 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 59 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[0\] " "Pin SD\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[0] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 410 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 106 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[1\] " "Pin SD\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[1] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 410 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 107 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[2\] " "Pin SD\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[2] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 410 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 108 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[3\] " "Pin SD\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[3] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 410 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 109 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[4\] " "Pin SD\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[4] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 410 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 110 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[5\] " "Pin SD\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[5] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 410 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 111 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[6\] " "Pin SD\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[6] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 410 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 112 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[7\] " "Pin SD\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[7] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 410 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 113 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DMAin " "Pin DMAin not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { DMAin } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 78 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { DMAin } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 364 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "INTin " "Pin INTin not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { INTin } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 78 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { INTin } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 366 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "C25M " "Pin C25M not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { C25M } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 11 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { C25M } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 354 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nWE " "Pin nWE not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nWE } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 85 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nWE } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 361 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[8\] " "Pin RA\[8\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[8] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 84 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 187 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[9\] " "Pin RA\[9\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[9] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 84 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 188 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[10\] " "Pin RA\[10\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[10] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 84 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 189 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[11\] " "Pin RA\[11\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[11] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 84 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 190 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[14\] " "Pin RA\[14\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[14] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 84 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 193 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[15\] " "Pin RA\[15\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[15] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 84 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 194 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[12\] " "Pin RA\[12\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[12] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 84 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 191 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[13\] " "Pin RA\[13\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[13] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 84 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 192 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[1\] " "Pin RA\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[1] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 84 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 180 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[0\] " "Pin RA\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[0] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 84 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 179 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[2\] " "Pin RA\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[2] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 84 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 181 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[3\] " "Pin RA\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[3] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 84 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 182 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[4\] " "Pin RA\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[4] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 84 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 183 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[5\] " "Pin RA\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[5] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 84 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 184 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[6\] " "Pin RA\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[6] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 84 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 185 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[7\] " "Pin RA\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[7] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 84 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 186 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nDEVSEL " "Pin nDEVSEL not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nDEVSEL } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 66 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nDEVSEL } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 359 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "MISO " "Pin MISO not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { MISO } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 184 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { MISO } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 369 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nRES " "Pin nRES not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nRES } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 18 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nRES } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 357 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "PHI0 " "Pin PHI0 not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI0 } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 11 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 355 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nBOD " "Pin nBOD not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nBOD } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 18 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nBOD } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 356 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616136955829 ""} } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1616136955829 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1616136955985 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1616136956001 ""} -{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1616136956016 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1616136956016 ""} -{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 3 clocks " "Found 3 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1616136956016 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1616136956016 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 ARCLK " " 1.000 ARCLK" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1616136956016 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 C25M " " 1.000 C25M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1616136956016 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 DRCLK " " 1.000 DRCLK" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1616136956016 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1616136956016 ""} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1616136956032 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1616136956032 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1616136956032 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 14 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 14" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 11 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1616136956063 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1616136956063 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1616136956063 ""} -{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0 186391 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "Fitter" 0 -1 1616136956126 ""} -{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1616136956126 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1616136956204 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1616136956219 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1616136956219 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1616136956219 ""} -{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "72 unused 3.3V 26 30 16 " "Number of I/O pins in group: 72 (unused VREF, 3.3V VCCIO, 26 input, 30 output, 16 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "I/O standards used: 3.3-V LVTTL." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1616136956251 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1616136956251 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1616136956251 ""} -{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 1 37 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 37 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1616136956251 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 42 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 42 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1616136956251 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1616136956251 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1616136956251 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1616136956282 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1616136956594 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1616136956626 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.05 " "Total time spent on timing analysis during the Fitter is 0.05 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1616136956626 ""} -{ "Info" "IFITAPI_FITAPI_INFO_FITTER_RETRY_TIGHTER_LUT_REG_PACKING" "" "Fitter cannot place all nodes on current device -- Fitter will automatically make another fitting attempt and tightly pack logic elements" { } { } 0 170216 "Fitter cannot place all nodes on current device -- Fitter will automatically make another fitting attempt and tightly pack logic elements" 0 0 "Fitter" 0 -1 1616136956641 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1616136956641 ""} -{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Minimize Area " "Fitter is using Minimize Area packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0 186391 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "Fitter" 0 -1 1616136956657 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1616136956751 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1616136956751 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1616136956751 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1616136956751 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1616136956751 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1616136956907 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1616136956938 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.02 " "Total time spent on timing analysis during the Fitter is 0.02 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1616136956938 ""} -{ "Info" "IFITAPI_FITAPI_INFO_FITTER_RETRY_TIGHTER_LUT_REG_PACKING" "" "Fitter cannot place all nodes on current device -- Fitter will automatically make another fitting attempt and tightly pack logic elements" { } { } 0 170216 "Fitter cannot place all nodes on current device -- Fitter will automatically make another fitting attempt and tightly pack logic elements" 0 0 "Fitter" 0 -1 1616136956938 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1616136956938 ""} -{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Minimize Area with Chains " "Fitter is using Minimize Area with Chains packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0 186391 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "Fitter" 0 -1 1616136956938 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1616136956954 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1616136956954 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1616136956954 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1616136956954 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1616136956954 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1616136957266 ""} -{ "Error" "EFITAPI_FITAPI_VPR_STATUS_FAILED_TOO_MANY_BLES" "313 240 logic cell " "Design contains 313 blocks of type logic cell. However, device contains only 240." { } { { "c:/altera/13.0sp1/quartus/common/advisors/oa_resource_table.xml" "" { Advisor "Z:/Repos/GR8RAM/cpld/" "LE" } } } 0 170011 "Design contains %1!d! blocks of type %3!s!. However, device contains only %2!d!." 0 0 "Fitter" 0 -1 1616136957297 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1616136957297 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.02 " "Total time spent on timing analysis during the Fitter is 0.02 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1616136957297 ""} -{ "Error" "EFITCC_FITCC_FAIL" "" "Can't fit design in device" { } { } 0 171000 "Can't fit design in device" 0 0 "Fitter" 0 -1 1616136957407 ""} -{ "Warning" "WFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE" "8 " "Following 8 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "RD\[0\] a permanently disabled " "Pin RD\[0\] has a permanently disabled output enable" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[0] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 126 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 140 9224 9983 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1616136957422 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "RD\[1\] a permanently disabled " "Pin RD\[1\] has a permanently disabled output enable" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[1] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 126 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 141 9224 9983 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1616136957422 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "RD\[2\] a permanently disabled " "Pin RD\[2\] has a permanently disabled output enable" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[2] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 126 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 142 9224 9983 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1616136957422 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "RD\[3\] a permanently disabled " "Pin RD\[3\] has a permanently disabled output enable" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[3] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 126 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 143 9224 9983 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1616136957422 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "RD\[4\] a permanently disabled " "Pin RD\[4\] has a permanently disabled output enable" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[4] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 126 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 144 9224 9983 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1616136957422 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "RD\[5\] a permanently disabled " "Pin RD\[5\] has a permanently disabled output enable" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[5] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 126 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 55 9224 9983 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1616136957422 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "RD\[6\] a permanently disabled " "Pin RD\[6\] has a permanently disabled output enable" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[6] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 126 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 57 9224 9983 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1616136957422 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "RD\[7\] a permanently disabled " "Pin RD\[7\] has a permanently disabled output enable" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[7] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 126 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 59 9224 9983 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1616136957422 ""} } { } 0 169064 "Following %1!d! pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" 0 0 "Fitter" 0 -1 1616136957422 ""} -{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1616136957422 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1616136957594 ""} -{ "Error" "EQEXE_ERROR_COUNT" "Fitter 2 s 5 s Quartus II 32-bit " "Quartus II 32-bit Fitter was unsuccessful. 2 errors, 5 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "367 " "Peak virtual memory: 367 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616136957797 ""} { "Error" "EQEXE_END_BANNER_TIME" "Fri Mar 19 02:55:57 2021 " "Processing ended: Fri Mar 19 02:55:57 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616136957797 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616136957797 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616136957797 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1616136957797 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1616150639150 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1616150639165 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1616150639353 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1616150639353 ""} +{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1616150639634 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1616150639665 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1616150639994 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1616150639994 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1616150639994 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1616150639994 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1616150639994 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1616150639994 ""} +{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "69 69 " "No exact pin location assignment(s) for 69 pins of 69 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nRESout " "Pin nRESout not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nRESout } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 37 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nRESout } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 153 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RAdir " "Pin RAdir not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RAdir } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 77 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RAdir } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 276 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RDdir " "Pin RDdir not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RDdir } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 112 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RDdir } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 277 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SBA\[0\] " "Pin SBA\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SBA[0] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 270 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SBA[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 126 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SBA\[1\] " "Pin SBA\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SBA[1] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 270 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SBA[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 127 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[0\] " "Pin SA\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[0] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 275 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 128 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[1\] " "Pin SA\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[1] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 275 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 129 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[2\] " "Pin SA\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[2] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 275 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 130 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[3\] " "Pin SA\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[3] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 275 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 131 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[4\] " "Pin SA\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[4] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 275 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 132 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[5\] " "Pin SA\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[5] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 275 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 133 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[6\] " "Pin SA\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[6] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 275 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 134 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[7\] " "Pin SA\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[7] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 275 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 135 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[8\] " "Pin SA\[8\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[8] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 275 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 136 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[9\] " "Pin SA\[9\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[9] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 275 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 137 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[10\] " "Pin SA\[10\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[10] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 275 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 138 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[11\] " "Pin SA\[11\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[11] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 275 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 139 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[12\] " "Pin SA\[12\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[12] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 275 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 140 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nRCS " "Pin nRCS not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nRCS } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 304 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nRCS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 239 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nRAS " "Pin nRAS not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nRAS } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 305 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nRAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 245 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nCAS " "Pin nCAS not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nCAS } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 306 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nCAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 240 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nSWE " "Pin nSWE not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nSWE } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 307 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nSWE } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 249 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DQML " "Pin DQML not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { DQML } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 284 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { DQML } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 235 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DQMH " "Pin DQMH not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { DQMH } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 293 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { DQMH } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 236 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RCKE " "Pin RCKE not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RCKE } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 303 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RCKE } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 241 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nFCS " "Pin nFCS not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nFCS } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 157 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nFCS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 278 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "FCK " "Pin FCK not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { FCK } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 159 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { FCK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 181 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "MOSI " "Pin MOSI not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { MOSI } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 161 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { MOSI } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 214 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[0\] " "Pin RD\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[0] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 109 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 59 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[1\] " "Pin RD\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[1] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 109 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 58 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[2\] " "Pin RD\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[2] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 109 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 57 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[3\] " "Pin RD\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[3] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 109 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 56 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[4\] " "Pin RD\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[4] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 109 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 55 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[5\] " "Pin RD\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[5] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 109 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 54 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[6\] " "Pin RD\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[6] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 109 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 53 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[7\] " "Pin RD\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[7] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 109 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 21 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[0\] " "Pin SD\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[0] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 233 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 94 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[1\] " "Pin SD\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[1] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 233 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 91 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[2\] " "Pin SD\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[2] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 233 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 90 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[3\] " "Pin SD\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[3] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 233 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 89 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[4\] " "Pin SD\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[4] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 233 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 88 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[5\] " "Pin SD\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[5] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 233 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 87 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[6\] " "Pin SD\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[6] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 233 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 86 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[7\] " "Pin SD\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[7] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 233 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 85 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "PHI0 " "Pin PHI0 not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI0 } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 9 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 269 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nWE " "Pin nWE not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nWE } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 74 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nWE } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 275 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nDEVSEL " "Pin nDEVSEL not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nDEVSEL } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 60 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nDEVSEL } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 273 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nIOSTRB " "Pin nIOSTRB not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nIOSTRB } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 60 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nIOSTRB } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 274 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nIOSEL " "Pin nIOSEL not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nIOSEL } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 60 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nIOSEL } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 272 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "C25M " "Pin C25M not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { C25M } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 9 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { C25M } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 268 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[1\] " "Pin RA\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[1] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 73 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 111 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[10\] " "Pin RA\[10\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[10] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 73 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 120 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[2\] " "Pin RA\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[2] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 73 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 112 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[11\] " "Pin RA\[11\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[11] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 73 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 121 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[3\] " "Pin RA\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[3] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 73 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 113 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[4\] " "Pin RA\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[4] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 73 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 114 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[5\] " "Pin RA\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[5] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 73 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 115 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[6\] " "Pin RA\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[6] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 73 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 116 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[7\] " "Pin RA\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[7] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 73 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 117 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[8\] " "Pin RA\[8\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[8] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 73 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 118 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[9\] " "Pin RA\[9\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[9] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 73 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 119 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[0\] " "Pin RA\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[0] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 73 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 110 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nRES " "Pin nRES not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nRES } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 16 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nRES } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 271 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[14\] " "Pin RA\[14\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[14] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 73 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 124 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[15\] " "Pin RA\[15\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[15] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 73 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 125 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[12\] " "Pin RA\[12\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[12] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 73 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 122 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[13\] " "Pin RA\[13\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[13] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 73 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 123 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "MISO " "Pin MISO not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { MISO } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 164 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { MISO } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 279 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nBOD " "Pin nBOD not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nBOD } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 16 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nBOD } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 270 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616150640009 ""} } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1616150640009 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1616150640197 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1616150640197 ""} +{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1616150640244 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1616150640244 ""} +{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1616150640244 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1616150640244 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 C25M " " 1.000 C25M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1616150640244 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1616150640244 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1616150640259 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1616150640259 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1616150640275 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 14 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 14" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 9 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1616150640306 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1616150640306 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1616150640322 ""} +{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0 186391 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "Fitter" 0 -1 1616150640384 ""} +{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1616150640384 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1616150640462 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1616150640478 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1616150640478 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1616150640478 ""} +{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "68 unused 3.3V 24 28 16 " "Number of I/O pins in group: 68 (unused VREF, 3.3V VCCIO, 24 input, 28 output, 16 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "I/O standards used: 3.3-V LVTTL." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1616150640494 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1616150640494 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1616150640494 ""} +{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 1 37 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 37 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1616150640509 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 42 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 42 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1616150640509 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1616150640509 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1616150640509 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1616150640541 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1616150640806 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1616150640853 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.03 " "Total time spent on timing analysis during the Fitter is 0.03 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1616150640853 ""} +{ "Info" "IFITAPI_FITAPI_INFO_FITTER_RETRY_TIGHTER_LUT_REG_PACKING" "" "Fitter cannot place all nodes on current device -- Fitter will automatically make another fitting attempt and tightly pack logic elements" { } { } 0 170216 "Fitter cannot place all nodes on current device -- Fitter will automatically make another fitting attempt and tightly pack logic elements" 0 0 "Fitter" 0 -1 1616150640853 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1616150640853 ""} +{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Minimize Area " "Fitter is using Minimize Area packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0 186391 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "Fitter" 0 -1 1616150640869 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1616150640931 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1616150640931 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1616150640931 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1616150640931 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1616150640931 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1616150641072 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1616150641103 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.00 " "Total time spent on timing analysis during the Fitter is 0.00 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1616150641103 ""} +{ "Info" "IFITAPI_FITAPI_INFO_FITTER_RETRY_TIGHTER_LUT_REG_PACKING" "" "Fitter cannot place all nodes on current device -- Fitter will automatically make another fitting attempt and tightly pack logic elements" { } { } 0 170216 "Fitter cannot place all nodes on current device -- Fitter will automatically make another fitting attempt and tightly pack logic elements" 0 0 "Fitter" 0 -1 1616150641103 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1616150641103 ""} +{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Minimize Area with Chains " "Fitter is using Minimize Area with Chains packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0 186391 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "Fitter" 0 -1 1616150641119 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1616150641119 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1616150641119 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1616150641119 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1616150641119 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1616150641119 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1616150641353 ""} +{ "Error" "EFITAPI_FITAPI_VPR_STATUS_FAILED_TOO_MANY_BLES" "250 240 logic cell " "Design contains 250 blocks of type logic cell. However, device contains only 240." { } { { "c:/altera/13.0sp1/quartus/common/advisors/oa_resource_table.xml" "" { Advisor "Z:/Repos/GR8RAM/cpld/" "LE" } } } 0 170011 "Design contains %1!d! blocks of type %3!s!. However, device contains only %2!d!." 0 0 "Fitter" 0 -1 1616150641384 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1616150641384 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.02 " "Total time spent on timing analysis during the Fitter is 0.02 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1616150641384 ""} +{ "Error" "EFITCC_FITCC_FAIL" "" "Can't fit design in device" { } { } 0 171000 "Can't fit design in device" 0 0 "Fitter" 0 -1 1616150641478 ""} +{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1616150641478 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1616150641650 ""} +{ "Error" "EQEXE_ERROR_COUNT" "Fitter 2 s 4 s Quartus II 32-bit " "Quartus II 32-bit Fitter was unsuccessful. 2 errors, 4 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "359 " "Peak virtual memory: 359 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616150641822 ""} { "Error" "EQEXE_END_BANNER_TIME" "Fri Mar 19 06:44:01 2021 " "Processing ended: Fri Mar 19 06:44:01 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616150641822 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616150641822 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616150641822 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1616150641822 ""} diff --git a/cpld/db/GR8RAM.hier_info b/cpld/db/GR8RAM.hier_info index 18e97e0..5be5cb9 100755 --- a/cpld/db/GR8RAM.hier_info +++ b/cpld/db/GR8RAM.hier_info @@ -1,56 +1,27 @@ |GR8RAM -C25M => SA[0]~reg0.CLK -C25M => SA[1]~reg0.CLK -C25M => SA[2]~reg0.CLK -C25M => SA[3]~reg0.CLK -C25M => SA[4]~reg0.CLK -C25M => SA[5]~reg0.CLK -C25M => SA[6]~reg0.CLK -C25M => SA[7]~reg0.CLK -C25M => SA[8]~reg0.CLK -C25M => SA[9]~reg0.CLK -C25M => SA[10]~reg0.CLK -C25M => SA[11]~reg0.CLK -C25M => SA[12]~reg0.CLK -C25M => SBA[0]~reg0.CLK -C25M => SBA[1]~reg0.CLK -C25M => DQML~reg0.CLK -C25M => DQMH~reg0.CLK +C25M => Amux[0].CLK +C25M => Amux[1].CLK +C25M => Amux[2].CLK C25M => nSWE~reg0.CLK C25M => nCAS~reg0.CLK C25M => nRAS~reg0.CLK C25M => nRCS~reg0.CLK C25M => RCKE~reg0.CLK +C25M => RefReqd.CLK C25M => IS[0].CLK C25M => IS[1].CLK -C25M => RefDone.CLK -C25M => S[0].CLK -C25M => S[1].CLK -C25M => S[2].CLK -C25M => S[3].CLK +C25M => PS[0].CLK +C25M => PS[1].CLK +C25M => PS[2].CLK C25M => SDOE.CLK -C25M => WRD[0].CLK -C25M => WRD[1].CLK -C25M => WRD[2].CLK -C25M => WRD[3].CLK -C25M => WRD[4].CLK -C25M => WRD[5].CLK C25M => WRD[6].CLK C25M => WRD[7].CLK -C25M => DRDIn.CLK -C25M => SetLoaded.CLK -C25M => SetLim8M.CLK -C25M => SetFW[0].CLK -C25M => SetFW[1].CLK -C25M => DRShift.CLK -C25M => DRCLK.CLK -C25M => ARShift.CLK -C25M => ARCLK.CLK C25M => MOSIOE.CLK C25M => MOSIout.CLK -C25M => FCS.CLK C25M => FCKEN.CLK +C25M => FCS.CLK C25M => FCK~reg0.CLK +C25M => Bank[0].CLK C25M => Bank[1].CLK C25M => Addr[0].CLK C25M => Addr[1].CLK @@ -76,7 +47,8 @@ C25M => Addr[20].CLK C25M => Addr[21].CLK C25M => Addr[22].CLK C25M => Addr[23].CLK -C25M => RAMSEL.CLK +C25M => REGEN.CLK +C25M => IOROMEN.CLK C25M => nWEcur.CLK C25M => RAcur[0].CLK C25M => RAcur[1].CLK @@ -91,10 +63,11 @@ C25M => RAcur[9].CLK C25M => RAcur[10].CLK C25M => RAcur[11].CLK C25M => RACr.CLK +C25M => IOSTRBr.CLK +C25M => IOSELr.CLK C25M => DEVSELr.CLK C25M => SDRAMActv.CLK C25M => InitActv.CLK -C25M => CmdActv.CLK C25M => InitIntr.CLK C25M => nRESout~reg0.CLK C25M => LS[0].CLK @@ -119,18 +92,25 @@ C25M => nBODf.CLK C25M => nBODf0.CLK C25M => nRESr.CLK C25M => nBODr.CLK -C25M => nRESr0.CLK -C25M => nBODr0.CLK C25M => PHI0r2.CLK C25M => PHI0r1.CLK C25M => PHI0r0.CLK +C25M => nRESr0.CLK +C25M => nBODr0.CLK +C25M => IOSTRBr0.CLK +C25M => IOSELr0.CLK C25M => DEVSELr0.CLK +PHI0 => comb.IN1 PHI0 => PHI0r0.DATAIN nBOD => nBODr0.DATAIN nRES => nRESr0.DATAIN -nIOSEL => ~NO_FANOUT~ +nRESout <= nRESout~reg0.DB_MAX_OUTPUT_PORT_TYPE +nIOSEL => comb.IN1 +nIOSEL => IOSELr0.DATAIN +nDEVSEL => comb.IN1 nDEVSEL => DEVSELr0.DATAIN -nIOSTRB => ~NO_FANOUT~ +nIOSTRB => comb.IN1 +nIOSTRB => IOSTRBr0.DATAIN RA[0] => RAcur[0].DATAIN RA[1] => RAcur[1].DATAIN RA[2] => RAcur[2].DATAIN @@ -147,6 +127,7 @@ RA[12] => Equal3.IN3 RA[13] => Equal3.IN2 RA[14] => Equal3.IN1 RA[15] => Equal3.IN0 +nWE => comb.IN1 nWE => nWEcur.DATAIN RAdir <= RD[0] <> RD[0] @@ -157,33 +138,28 @@ RD[4] <> RD[4] RD[5] <> RD[5] RD[6] <> RD[6] RD[7] <> RD[7] -RDdir <= -DMAin => DMAout.DATAIN -DMAout <= DMAin.DB_MAX_OUTPUT_PORT_TYPE -INTin => INTout.DATAIN -INTout <= INTin.DB_MAX_OUTPUT_PORT_TYPE -nRESout <= nRESout~reg0.DB_MAX_OUTPUT_PORT_TYPE -SBA[0] <= SBA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -SBA[1] <= SBA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -SA[0] <= SA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -SA[1] <= SA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -SA[2] <= SA[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -SA[3] <= SA[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -SA[4] <= SA[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -SA[5] <= SA[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -SA[6] <= SA[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -SA[7] <= SA[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -SA[8] <= SA[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -SA[9] <= SA[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -SA[10] <= SA[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -SA[11] <= SA[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -SA[12] <= SA[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +RDdir <= comb.DB_MAX_OUTPUT_PORT_TYPE +SBA[0] <= SBA.DB_MAX_OUTPUT_PORT_TYPE +SBA[1] <= SBA.DB_MAX_OUTPUT_PORT_TYPE +SA[0] <= SA.DB_MAX_OUTPUT_PORT_TYPE +SA[1] <= SA.DB_MAX_OUTPUT_PORT_TYPE +SA[2] <= SA.DB_MAX_OUTPUT_PORT_TYPE +SA[3] <= SA.DB_MAX_OUTPUT_PORT_TYPE +SA[4] <= SA.DB_MAX_OUTPUT_PORT_TYPE +SA[5] <= SA.DB_MAX_OUTPUT_PORT_TYPE +SA[6] <= SA.DB_MAX_OUTPUT_PORT_TYPE +SA[7] <= SA.DB_MAX_OUTPUT_PORT_TYPE +SA[8] <= SA.DB_MAX_OUTPUT_PORT_TYPE +SA[9] <= SA.DB_MAX_OUTPUT_PORT_TYPE +SA[10] <= SA.DB_MAX_OUTPUT_PORT_TYPE +SA[11] <= SA.DB_MAX_OUTPUT_PORT_TYPE +SA[12] <= SA.DB_MAX_OUTPUT_PORT_TYPE nRCS <= nRCS~reg0.DB_MAX_OUTPUT_PORT_TYPE nRAS <= nRAS~reg0.DB_MAX_OUTPUT_PORT_TYPE nCAS <= nCAS~reg0.DB_MAX_OUTPUT_PORT_TYPE nSWE <= nSWE~reg0.DB_MAX_OUTPUT_PORT_TYPE -DQML <= DQML~reg0.DB_MAX_OUTPUT_PORT_TYPE -DQMH <= DQMH~reg0.DB_MAX_OUTPUT_PORT_TYPE +DQML <= DQML.DB_MAX_OUTPUT_PORT_TYPE +DQMH <= DQMH.DB_MAX_OUTPUT_PORT_TYPE RCKE <= RCKE~reg0.DB_MAX_OUTPUT_PORT_TYPE SD[0] <> SD[0] SD[1] <> SD[1] @@ -195,39 +171,7 @@ SD[6] <> SD[6] SD[7] <> SD[7] nFCS <= FCS.DB_MAX_OUTPUT_PORT_TYPE FCK <= FCK~reg0.DB_MAX_OUTPUT_PORT_TYPE -MISO => WRD.DATAB +MISO => WRD[7].DATAIN MOSI <= MOSI.DB_MAX_OUTPUT_PORT_TYPE -|GR8RAM|UFM:UFM_inst -arclk => arclk.IN1 -ardin => ardin.IN1 -arshft => arshft.IN1 -drclk => drclk.IN1 -drdin => drdin.IN1 -drshft => drshft.IN1 -erase => erase.IN1 -oscena => oscena.IN1 -program => program.IN1 -busy <= UFM_altufm_none_0ep:UFM_altufm_none_0ep_component.busy -drdout <= UFM_altufm_none_0ep:UFM_altufm_none_0ep_component.drdout -osc <= UFM_altufm_none_0ep:UFM_altufm_none_0ep_component.osc -rtpbusy <= UFM_altufm_none_0ep:UFM_altufm_none_0ep_component.rtpbusy - - -|GR8RAM|UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component -arclk => maxii_ufm_block1.ARCLK -ardin => maxii_ufm_block1.ARDIN -arshft => maxii_ufm_block1.ARSHFT -busy <= maxii_ufm_block1.BUSY -drclk => maxii_ufm_block1.DRCLK -drdin => maxii_ufm_block1.DRDIN -drdout <= maxii_ufm_block1.DRDOUT -drshft => maxii_ufm_block1.DRSHFT -erase => maxii_ufm_block1.ERASE -osc <= maxii_ufm_block1.OSC -oscena => maxii_ufm_block1.OSCENA -program => maxii_ufm_block1.PROGRAM -rtpbusy <= maxii_ufm_block1.BGPBUSY - - diff --git a/cpld/db/GR8RAM.hif b/cpld/db/GR8RAM.hif index 457b030..5166530 100755 Binary files a/cpld/db/GR8RAM.hif and b/cpld/db/GR8RAM.hif differ diff --git a/cpld/db/GR8RAM.ipinfo b/cpld/db/GR8RAM.ipinfo index fd31def..6ff9cf3 100755 Binary files a/cpld/db/GR8RAM.ipinfo and b/cpld/db/GR8RAM.ipinfo differ diff --git a/cpld/db/GR8RAM.lpc.html b/cpld/db/GR8RAM.lpc.html index 6be76eb..fbc5ab5 100755 --- a/cpld/db/GR8RAM.lpc.html +++ b/cpld/db/GR8RAM.lpc.html @@ -15,36 +15,4 @@ Input only Bidir Output only Bidir - -UFM_inst|UFM_altufm_none_0ep_component -9 -0 -0 -0 -4 -0 -0 -0 -0 -0 -0 -0 -0 - - -UFM_inst -9 -2 -0 -2 -4 -2 -2 -2 -0 -0 -0 -0 -0 - diff --git a/cpld/db/GR8RAM.lpc.rdb b/cpld/db/GR8RAM.lpc.rdb index 82430f2..f46ce48 100755 Binary files a/cpld/db/GR8RAM.lpc.rdb and b/cpld/db/GR8RAM.lpc.rdb differ diff --git a/cpld/db/GR8RAM.lpc.txt b/cpld/db/GR8RAM.lpc.txt index 9336d5d..a463804 100755 --- a/cpld/db/GR8RAM.lpc.txt +++ b/cpld/db/GR8RAM.lpc.txt @@ -1,8 +1,5 @@ -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Legal Partition Candidates ; -+----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ -; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; -+----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ -; UFM_inst|UFM_altufm_none_0ep_component ; 9 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; UFM_inst ; 9 ; 2 ; 0 ; 2 ; 4 ; 2 ; 2 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; -+----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Legal Partition Candidates ; ++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; ++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ diff --git a/cpld/db/GR8RAM.map.cdb b/cpld/db/GR8RAM.map.cdb index d53620a..dee997a 100755 Binary files a/cpld/db/GR8RAM.map.cdb and b/cpld/db/GR8RAM.map.cdb differ diff --git a/cpld/db/GR8RAM.map.hdb b/cpld/db/GR8RAM.map.hdb index 0fbe365..2f8e340 100755 Binary files a/cpld/db/GR8RAM.map.hdb and b/cpld/db/GR8RAM.map.hdb differ diff --git a/cpld/db/GR8RAM.map.qmsg b/cpld/db/GR8RAM.map.qmsg index ea2c0e4..878a0ea 100755 --- a/cpld/db/GR8RAM.map.qmsg +++ b/cpld/db/GR8RAM.map.qmsg @@ -1,35 +1,31 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616136944860 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616136944860 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 19 02:55:44 2021 " "Processing started: Fri Mar 19 02:55:44 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616136944860 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1616136944860 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1616136944860 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1616136946282 ""} -{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 72 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1616136946532 ""} -{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 188 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1616136946548 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_0ep " "Found entity 1: UFM_altufm_none_0ep" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616136946548 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616136946548 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1616136946548 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "gr8ram.v(126) " "Verilog HDL warning at gr8ram.v(126): extended using \"x\" or \"z\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 126 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1616136946845 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "gr8ram.v(410) " "Verilog HDL warning at gr8ram.v(410): extended using \"x\" or \"z\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 410 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1616136946845 ""} -{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "1 gr8ram.v(545) " "Verilog HDL Expression warning at gr8ram.v(545): truncated literal to match 1 bits" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 545 0 0 } } } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "Quartus II" 0 -1 1616136946845 ""} -{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "1 gr8ram.v(558) " "Verilog HDL Expression warning at gr8ram.v(558): truncated literal to match 1 bits" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 558 0 0 } } } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "Quartus II" 0 -1 1616136946845 ""} -{ "Warning" "WSGN_SEARCH_FILE" "gr8ram.v 1 1 " "Using design file gr8ram.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616136946860 ""} } { } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Quartus II" 0 -1 1616136946860 ""} -{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "UFMB gr8ram.v(275) " "Verilog HDL Implicit Net warning at gr8ram.v(275): created implicit net for \"UFMB\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 275 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1616136946860 ""} -{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "RTPB gr8ram.v(278) " "Verilog HDL Implicit Net warning at gr8ram.v(278): created implicit net for \"RTPB\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 278 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1616136946860 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1616136946892 ""} -{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "REGEN gr8ram.v(112) " "Verilog HDL or VHDL warning at gr8ram.v(112): object \"REGEN\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 112 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616136946907 "|GR8RAM"} -{ "Warning" "WVRFX_VERI_2106_UNCONVERTED" "RDout gr8ram.v(127) " "Verilog HDL warning at gr8ram.v(127): object RDout used but never assigned" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 127 0 0 } } } 0 10858 "Verilog HDL warning at %2!s!: object %1!s! used but never assigned" 0 0 "Quartus II" 0 -1 1616136946907 "|GR8RAM"} -{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "UFMBr gr8ram.v(280) " "Verilog HDL or VHDL warning at gr8ram.v(280): object \"UFMBr\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 280 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616136946907 "|GR8RAM"} -{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "RTPBr gr8ram.v(282) " "Verilog HDL or VHDL warning at gr8ram.v(282): object \"RTPBr\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 282 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616136946907 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 gr8ram.v(39) " "Verilog HDL assignment warning at gr8ram.v(39): truncated value with size 32 to match size of target (18)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 39 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136946907 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 gr8ram.v(147) " "Verilog HDL assignment warning at gr8ram.v(147): truncated value with size 32 to match size of target (8)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 147 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136946907 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 gr8ram.v(154) " "Verilog HDL assignment warning at gr8ram.v(154): truncated value with size 32 to match size of target (8)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 154 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136946907 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 gr8ram.v(160) " "Verilog HDL assignment warning at gr8ram.v(160): truncated value with size 32 to match size of target (8)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 160 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136946923 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 gr8ram.v(426) " "Verilog HDL assignment warning at gr8ram.v(426): truncated value with size 32 to match size of target (4)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 426 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136946923 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "10 6 gr8ram.v(547) " "Verilog HDL assignment warning at gr8ram.v(547): truncated value with size 10 to match size of target (6)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 547 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136946923 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "10 6 gr8ram.v(635) " "Verilog HDL assignment warning at gr8ram.v(635): truncated value with size 10 to match size of target (6)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 635 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136946938 "|GR8RAM"} -{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "RDout 0 gr8ram.v(127) " "Net \"RDout\" at gr8ram.v(127) has no driver or initial value, using a default initial value '0'" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 127 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Quartus II" 0 -1 1616136946938 "|GR8RAM"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "gr8ram.v" "UFM_inst" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 278 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1616136947142 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_0ep UFM:UFM_inst\|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component " "Elaborating entity \"UFM_altufm_none_0ep\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component\"" { } { { "UFM.v" "UFM_altufm_none_0ep_component" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 216 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1616136947204 ""} -{ "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR_HDR" "" "Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "MOSI WRD " "Converted the fan-out from the tri-state buffer \"MOSI\" to the node \"WRD\" into an OR gate" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 181 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1616136948751 ""} } { } 0 13046 "Tri-state node(s) do not directly drive top-level pin(s)" 0 0 "Quartus II" 0 -1 1616136948751 ""} -{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 88 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616136949454 "|GR8RAM|RAdir"} { "Warning" "WMLS_MLS_STUCK_PIN" "RDdir VCC " "Pin \"RDdir\" is stuck at VCC" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 130 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616136949454 "|GR8RAM|RDdir"} { "Warning" "WMLS_MLS_STUCK_PIN" "RCKE VCC " "Pin \"RCKE\" is stuck at VCC" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 448 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616136949454 "|GR8RAM|RCKE"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1616136949454 ""} -{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "nIOSEL " "No output dependent on input pin \"nIOSEL\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 66 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1616136950063 "|GR8RAM|nIOSEL"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "nIOSTRB " "No output dependent on input pin \"nIOSTRB\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 66 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1616136950063 "|GR8RAM|nIOSTRB"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1616136950063 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "417 " "Implemented 417 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "27 " "Implemented 27 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1616136950095 ""} { "Info" "ICUT_CUT_TM_OPINS" "30 " "Implemented 30 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1616136950095 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Implemented 16 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1616136950095 ""} { "Info" "ICUT_CUT_TM_LCELLS" "343 " "Implemented 343 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1616136950095 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Quartus II" 0 -1 1616136950095 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1616136950095 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1616136950376 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 26 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 26 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "301 " "Peak virtual memory: 301 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616136950579 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 19 02:55:50 2021 " "Processing ended: Fri Mar 19 02:55:50 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616136950579 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616136950579 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616136950579 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1616136950579 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616150630415 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616150630431 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 19 06:43:50 2021 " "Processing started: Fri Mar 19 06:43:50 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616150630431 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1616150630431 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1616150630431 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1616150631900 ""} +{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 72 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1616150632103 ""} +{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 188 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1616150632103 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_0ep " "Found entity 1: UFM_altufm_none_0ep" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616150632118 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616150632118 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1616150632118 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "gr8ram.v(109) " "Verilog HDL warning at gr8ram.v(109): extended using \"x\" or \"z\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 109 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1616150632353 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "gr8ram.v(233) " "Verilog HDL warning at gr8ram.v(233): extended using \"x\" or \"z\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 233 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1616150632353 ""} +{ "Warning" "WSGN_SEARCH_FILE" "gr8ram.v 1 1 " "Using design file gr8ram.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616150632353 ""} } { } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Quartus II" 0 -1 1616150632353 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1616150632384 ""} +{ "Warning" "WVRFX_VERI_2106_UNCONVERTED" "RDout gr8ram.v(110) " "Verilog HDL warning at gr8ram.v(110): object RDout used but never assigned" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 110 0 0 } } } 0 10858 "Verilog HDL warning at %2!s!: object %1!s! used but never assigned" 0 0 "Quartus II" 0 -1 1616150632384 "|GR8RAM"} +{ "Warning" "WVRFX_VERI_2106_UNCONVERTED" "SetFW gr8ram.v(230) " "Verilog HDL warning at gr8ram.v(230): object SetFW used but never assigned" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 230 0 0 } } } 0 10858 "Verilog HDL warning at %2!s!: object %1!s! used but never assigned" 0 0 "Quartus II" 0 -1 1616150632384 "|GR8RAM"} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "RefReady gr8ram.v(263) " "Verilog HDL or VHDL warning at gr8ram.v(263): object \"RefReady\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 263 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616150632384 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 gr8ram.v(34) " "Verilog HDL assignment warning at gr8ram.v(34): truncated value with size 32 to match size of target (18)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 34 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616150632384 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 24 gr8ram.v(125) " "Verilog HDL assignment warning at gr8ram.v(125): truncated value with size 32 to match size of target (24)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 125 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616150632384 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "36 24 gr8ram.v(126) " "Verilog HDL assignment warning at gr8ram.v(126): truncated value with size 36 to match size of target (24)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 126 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616150632384 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 gr8ram.v(130) " "Verilog HDL assignment warning at gr8ram.v(130): truncated value with size 32 to match size of target (16)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 130 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616150632384 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "36 16 gr8ram.v(131) " "Verilog HDL assignment warning at gr8ram.v(131): truncated value with size 36 to match size of target (16)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 131 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616150632384 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 gr8ram.v(136) " "Verilog HDL assignment warning at gr8ram.v(136): truncated value with size 32 to match size of target (8)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 136 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616150632384 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "36 8 gr8ram.v(137) " "Verilog HDL assignment warning at gr8ram.v(137): truncated value with size 36 to match size of target (8)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 137 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616150632384 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 gr8ram.v(195) " "Verilog HDL assignment warning at gr8ram.v(195): truncated value with size 2 to match size of target (1)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 195 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616150632400 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 gr8ram.v(249) " "Verilog HDL assignment warning at gr8ram.v(249): truncated value with size 32 to match size of target (3)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 249 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616150632400 "|GR8RAM"} +{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "RDout 0 gr8ram.v(110) " "Net \"RDout\" at gr8ram.v(110) has no driver or initial value, using a default initial value '0'" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 110 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Quartus II" 0 -1 1616150632415 "|GR8RAM"} +{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "SetFW 0 gr8ram.v(230) " "Net \"SetFW\" at gr8ram.v(230) has no driver or initial value, using a default initial value '0'" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 230 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Quartus II" 0 -1 1616150632415 "|GR8RAM"} +{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "WRD\[5..0\] 0 gr8ram.v(234) " "Net \"WRD\[5..0\]\" at gr8ram.v(234) has no driver or initial value, using a default initial value '0'" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 234 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Quartus II" 0 -1 1616150632415 "|GR8RAM"} +{ "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR_HDR" "" "Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "MOSI WRD\[6\] " "Converted the fan-out from the tri-state buffer \"MOSI\" to the node \"WRD\[6\]\" into an OR gate" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 161 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1616150633900 ""} } { } 0 13046 "Tri-state node(s) do not directly drive top-level pin(s)" 0 0 "Quartus II" 0 -1 1616150633900 ""} +{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 77 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616150634400 "|GR8RAM|RAdir"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1616150634400 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "350 " "Implemented 350 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "25 " "Implemented 25 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1616150634962 ""} { "Info" "ICUT_CUT_TM_OPINS" "28 " "Implemented 28 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1616150634962 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Implemented 16 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1616150634962 ""} { "Info" "ICUT_CUT_TM_LCELLS" "281 " "Implemented 281 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1616150634962 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1616150634962 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1616150635150 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 20 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 20 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "301 " "Peak virtual memory: 301 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616150635415 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 19 06:43:55 2021 " "Processing ended: Fri Mar 19 06:43:55 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616150635415 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616150635415 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616150635415 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1616150635415 ""} diff --git a/cpld/db/GR8RAM.map.rdb b/cpld/db/GR8RAM.map.rdb index d26ae76..248299b 100755 Binary files a/cpld/db/GR8RAM.map.rdb and b/cpld/db/GR8RAM.map.rdb differ diff --git a/cpld/db/GR8RAM.pre_map.hdb b/cpld/db/GR8RAM.pre_map.hdb index 4f5fd3b..2483a37 100755 Binary files a/cpld/db/GR8RAM.pre_map.hdb and b/cpld/db/GR8RAM.pre_map.hdb differ diff --git a/cpld/db/GR8RAM.root_partition.map.reg_db.cdb b/cpld/db/GR8RAM.root_partition.map.reg_db.cdb index 4021fd9..f982b75 100755 Binary files a/cpld/db/GR8RAM.root_partition.map.reg_db.cdb and b/cpld/db/GR8RAM.root_partition.map.reg_db.cdb differ diff --git a/cpld/db/GR8RAM.routing.rdb b/cpld/db/GR8RAM.routing.rdb index 9c791d1..2276e61 100755 Binary files a/cpld/db/GR8RAM.routing.rdb and b/cpld/db/GR8RAM.routing.rdb differ diff --git a/cpld/db/GR8RAM.rtlv.hdb b/cpld/db/GR8RAM.rtlv.hdb index 7c27119..6ba5306 100755 Binary files a/cpld/db/GR8RAM.rtlv.hdb and b/cpld/db/GR8RAM.rtlv.hdb differ diff --git a/cpld/db/GR8RAM.rtlv_sg.cdb b/cpld/db/GR8RAM.rtlv_sg.cdb index dd24739..4e8db38 100755 Binary files a/cpld/db/GR8RAM.rtlv_sg.cdb and b/cpld/db/GR8RAM.rtlv_sg.cdb differ diff --git a/cpld/db/GR8RAM.rtlv_sg_swap.cdb b/cpld/db/GR8RAM.rtlv_sg_swap.cdb index e3dd269..e6e4232 100755 Binary files a/cpld/db/GR8RAM.rtlv_sg_swap.cdb and b/cpld/db/GR8RAM.rtlv_sg_swap.cdb differ diff --git a/cpld/db/GR8RAM.sgdiff.cdb b/cpld/db/GR8RAM.sgdiff.cdb index a13cae4..4aafbe2 100755 Binary files a/cpld/db/GR8RAM.sgdiff.cdb and b/cpld/db/GR8RAM.sgdiff.cdb differ diff --git a/cpld/db/GR8RAM.sgdiff.hdb b/cpld/db/GR8RAM.sgdiff.hdb index d1f8d76..75b8f78 100755 Binary files a/cpld/db/GR8RAM.sgdiff.hdb and b/cpld/db/GR8RAM.sgdiff.hdb differ diff --git a/cpld/db/GR8RAM.sta.qmsg b/cpld/db/GR8RAM.sta.qmsg index ff7e2a5..0fc335c 100755 --- a/cpld/db/GR8RAM.sta.qmsg +++ b/cpld/db/GR8RAM.sta.qmsg @@ -1,23 +1,23 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616056855068 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616056855083 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 18 04:40:54 2021 " "Processing started: Thu Mar 18 04:40:54 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616056855083 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1616056855083 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1616056855099 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1616056855286 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1616056856161 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1616056856365 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1616056856365 ""} -{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1616056856536 ""} -{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1616056856896 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1616056857052 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1616056857052 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857068 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857068 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C25M C25M " "create_clock -period 1.000 -name C25M C25M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857068 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857068 ""} -{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1616056857115 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1616056857240 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857271 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857271 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 ARCLK " " -99.000 -99.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857271 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 DRCLK " " -99.000 -99.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857271 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -8.447 -415.877 C25M " " -8.447 -415.877 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857271 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1616056857271 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold -16.286 " "Worst-case hold slack is -16.286" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857318 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857318 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.286 -16.286 DRCLK " " -16.286 -16.286 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857318 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.276 -16.276 ARCLK " " -16.276 -16.276 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857318 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.579 -1.579 C25M " " -1.579 -1.579 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857318 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1616056857318 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1616056857333 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1616056857365 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857380 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857380 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 ARCLK " " -29.500 -59.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857380 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 DRCLK " " -29.500 -59.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857380 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 C25M " " -2.289 -2.289 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616056857380 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1616056857380 ""} -{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1616056857677 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1616056857833 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1616056857833 ""} -{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "286 " "Peak virtual memory: 286 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616056858099 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 18 04:40:58 2021 " "Processing ended: Thu Mar 18 04:40:58 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616056858099 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616056858099 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616056858099 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1616056858099 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616146137780 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616146137811 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 19 05:28:56 2021 " "Processing started: Fri Mar 19 05:28:56 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616146137811 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1616146137811 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1616146137811 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1616146138030 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1616146138936 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1616146139139 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1616146139139 ""} +{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1616146139342 ""} +{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1616146139686 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1616146139874 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1616146139874 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1616146139889 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1616146139889 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C25M C25M " "create_clock -period 1.000 -name C25M C25M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1616146139889 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1616146139889 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1616146139921 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1616146140030 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616146140061 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616146140061 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 ARCLK " " -99.000 -99.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616146140061 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 DRCLK " " -99.000 -99.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616146140061 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.598 -485.527 C25M " " -9.598 -485.527 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616146140061 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1616146140061 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold -16.296 " "Worst-case hold slack is -16.296" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616146140077 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616146140077 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.296 -16.296 ARCLK " " -16.296 -16.296 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616146140077 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.276 -16.276 DRCLK " " -16.276 -16.276 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616146140077 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.031 -1.031 C25M " " -1.031 -1.031 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616146140077 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1616146140077 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1616146140108 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1616146140124 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616146140139 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616146140139 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 ARCLK " " -29.500 -59.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616146140139 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 DRCLK " " -29.500 -59.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616146140139 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 C25M " " -2.289 -2.289 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616146140139 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1616146140139 ""} +{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1616146140483 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1616146140592 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1616146140592 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "275 " "Peak virtual memory: 275 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616146140842 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 19 05:29:00 2021 " "Processing ended: Fri Mar 19 05:29:00 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616146140842 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616146140842 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616146140842 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1616146140842 ""} diff --git a/cpld/db/GR8RAM.sta.rdb b/cpld/db/GR8RAM.sta.rdb index 8c48ab0..de372fa 100755 Binary files a/cpld/db/GR8RAM.sta.rdb and b/cpld/db/GR8RAM.sta.rdb differ diff --git a/cpld/db/GR8RAM.vpr.ammdb b/cpld/db/GR8RAM.vpr.ammdb index c0f8c8f..147f5b8 100755 Binary files a/cpld/db/GR8RAM.vpr.ammdb and b/cpld/db/GR8RAM.vpr.ammdb differ diff --git a/cpld/db/prev_cmp_GR8RAM.qmsg b/cpld/db/prev_cmp_GR8RAM.qmsg index b4c8ba2..2eeb684 100755 --- a/cpld/db/prev_cmp_GR8RAM.qmsg +++ b/cpld/db/prev_cmp_GR8RAM.qmsg @@ -1,33 +1,19 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616136912610 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616136912625 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 19 02:55:12 2021 " "Processing started: Fri Mar 19 02:55:12 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616136912625 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1616136912625 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1616136912625 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1616136914344 ""} -{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 72 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1616136914672 ""} -{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 188 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1616136914672 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_0ep " "Found entity 1: UFM_altufm_none_0ep" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616136914672 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616136914672 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1616136914672 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "gr8ram.v(126) " "Verilog HDL warning at gr8ram.v(126): extended using \"x\" or \"z\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 126 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1616136914954 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "gr8ram.v(410) " "Verilog HDL warning at gr8ram.v(410): extended using \"x\" or \"z\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 410 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1616136914954 ""} -{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "1 gr8ram.v(545) " "Verilog HDL Expression warning at gr8ram.v(545): truncated literal to match 1 bits" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 545 0 0 } } } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "Quartus II" 0 -1 1616136914954 ""} -{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "1 gr8ram.v(558) " "Verilog HDL Expression warning at gr8ram.v(558): truncated literal to match 1 bits" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 558 0 0 } } } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "Quartus II" 0 -1 1616136914954 ""} -{ "Warning" "WSGN_SEARCH_FILE" "gr8ram.v 1 1 " "Using design file gr8ram.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616136914954 ""} } { } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Quartus II" 0 -1 1616136914954 ""} -{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "UFMB gr8ram.v(275) " "Verilog HDL Implicit Net warning at gr8ram.v(275): created implicit net for \"UFMB\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 275 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1616136914954 ""} -{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "RTPB gr8ram.v(278) " "Verilog HDL Implicit Net warning at gr8ram.v(278): created implicit net for \"RTPB\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 278 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1616136914954 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1616136914985 ""} -{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "REGEN gr8ram.v(112) " "Verilog HDL or VHDL warning at gr8ram.v(112): object \"REGEN\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 112 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616136914985 "|GR8RAM"} -{ "Warning" "WVRFX_VERI_2106_UNCONVERTED" "RDout gr8ram.v(127) " "Verilog HDL warning at gr8ram.v(127): object RDout used but never assigned" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 127 0 0 } } } 0 10858 "Verilog HDL warning at %2!s!: object %1!s! used but never assigned" 0 0 "Quartus II" 0 -1 1616136914985 "|GR8RAM"} -{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "UFMBr gr8ram.v(280) " "Verilog HDL or VHDL warning at gr8ram.v(280): object \"UFMBr\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 280 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616136914985 "|GR8RAM"} -{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "RTPBr gr8ram.v(282) " "Verilog HDL or VHDL warning at gr8ram.v(282): object \"RTPBr\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 282 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616136914985 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 gr8ram.v(39) " "Verilog HDL assignment warning at gr8ram.v(39): truncated value with size 32 to match size of target (18)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 39 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136914985 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 gr8ram.v(147) " "Verilog HDL assignment warning at gr8ram.v(147): truncated value with size 32 to match size of target (8)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 147 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136914985 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 gr8ram.v(154) " "Verilog HDL assignment warning at gr8ram.v(154): truncated value with size 32 to match size of target (8)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 154 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136915000 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 gr8ram.v(160) " "Verilog HDL assignment warning at gr8ram.v(160): truncated value with size 32 to match size of target (8)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 160 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136915000 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 gr8ram.v(426) " "Verilog HDL assignment warning at gr8ram.v(426): truncated value with size 32 to match size of target (4)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 426 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136915000 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "10 6 gr8ram.v(547) " "Verilog HDL assignment warning at gr8ram.v(547): truncated value with size 10 to match size of target (6)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 547 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136915000 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "10 6 gr8ram.v(635) " "Verilog HDL assignment warning at gr8ram.v(635): truncated value with size 10 to match size of target (6)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 635 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616136915000 "|GR8RAM"} -{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "RDout 0 gr8ram.v(127) " "Net \"RDout\" at gr8ram.v(127) has no driver or initial value, using a default initial value '0'" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 127 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Quartus II" 0 -1 1616136915000 "|GR8RAM"} -{ "Error" "EVRFX_VDB_NET_MULTIPLE_DRIVERS" "FCK gr8ram.v(190) " "Can't resolve multiple constant drivers for net \"FCK\" at gr8ram.v(190)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 190 0 0 } } } 0 10028 "Can't resolve multiple constant drivers for net \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1616136915016 ""} -{ "Error" "EVRFX_VDB_NET_ANOTHER_DRIVER" "gr8ram.v(187) " "Constant driver at gr8ram.v(187)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 187 0 0 } } } 0 10029 "Constant driver at %1!s!" 0 0 "Quartus II" 0 -1 1616136915016 ""} -{ "Error" "ESGN_TOP_HIER_ELABORATION_FAILURE" "" "Can't elaborate top-level user hierarchy" { } { } 0 12153 "Can't elaborate top-level user hierarchy" 0 0 "Quartus II" 0 -1 1616136915016 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1616136915188 ""} -{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 3 s 17 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was unsuccessful. 3 errors, 17 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "296 " "Peak virtual memory: 296 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616136915532 ""} { "Error" "EQEXE_END_BANNER_TIME" "Fri Mar 19 02:55:15 2021 " "Processing ended: Fri Mar 19 02:55:15 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616136915532 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616136915532 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616136915532 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1616136915532 ""} -{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 5 s 17 s " "Quartus II Full Compilation was unsuccessful. 5 errors, 17 warnings" { } { } 0 293001 "Quartus II %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1616136916625 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616150602476 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616150602492 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 19 06:43:22 2021 " "Processing started: Fri Mar 19 06:43:22 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616150602492 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1616150602492 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1616150602492 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1616150604133 ""} +{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 72 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1616150604383 ""} +{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 188 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1616150604383 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_0ep " "Found entity 1: UFM_altufm_none_0ep" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616150604383 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616150604383 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1616150604383 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "gr8ram.v(109) " "Verilog HDL warning at gr8ram.v(109): extended using \"x\" or \"z\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 109 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1616150604680 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "gr8ram.v(230) " "Verilog HDL warning at gr8ram.v(230): extended using \"x\" or \"z\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 230 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1616150604695 ""} +{ "Warning" "WSGN_SEARCH_FILE" "gr8ram.v 1 1 " "Using design file gr8ram.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616150604695 ""} } { } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Quartus II" 0 -1 1616150604695 ""} +{ "Error" "EVRFX_VERI_UNDECLARED_OBJECT" "SetFW gr8ram.v(121) " "Verilog HDL error at gr8ram.v(121): object \"SetFW\" is not declared" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 121 0 0 } } } 0 10161 "Verilog HDL error at %2!s!: object \"%1!s!\" is not declared" 0 0 "Quartus II" 0 -1 1616150604695 ""} +{ "Error" "EVRFX_VERI_UNDECLARED_OBJECT" "SetFW gr8ram.v(125) " "Verilog HDL error at gr8ram.v(125): object \"SetFW\" is not declared" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 125 0 0 } } } 0 10161 "Verilog HDL error at %2!s!: object \"%1!s!\" is not declared" 0 0 "Quartus II" 0 -1 1616150604695 ""} +{ "Error" "EVRFX_VERI_UNDECLARED_OBJECT" "SetFW gr8ram.v(130) " "Verilog HDL error at gr8ram.v(130): object \"SetFW\" is not declared" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 130 0 0 } } } 0 10161 "Verilog HDL error at %2!s!: object \"%1!s!\" is not declared" 0 0 "Quartus II" 0 -1 1616150604695 ""} +{ "Error" "EVRFX_VERI_UNDECLARED_OBJECT" "SetFW gr8ram.v(136) " "Verilog HDL error at gr8ram.v(136): object \"SetFW\" is not declared" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 136 0 0 } } } 0 10161 "Verilog HDL error at %2!s!: object \"%1!s!\" is not declared" 0 0 "Quartus II" 0 -1 1616150604711 ""} +{ "Error" "EVRFX_VERI_UNDECLARED_OBJECT" "SetFW gr8ram.v(140) " "Verilog HDL error at gr8ram.v(140): object \"SetFW\" is not declared" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 140 0 0 } } } 0 10161 "Verilog HDL error at %2!s!: object \"%1!s!\" is not declared" 0 0 "Quartus II" 0 -1 1616150604711 ""} +{ "Error" "EVRFX_VERI_UNDECLARED_OBJECT" "SetFW gr8ram.v(195) " "Verilog HDL error at gr8ram.v(195): object \"SetFW\" is not declared" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 195 0 0 } } } 0 10161 "Verilog HDL error at %2!s!: object \"%1!s!\" is not declared" 0 0 "Quartus II" 0 -1 1616150604711 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1616150604914 ""} +{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 6 s 1 Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was unsuccessful. 6 errors, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "297 " "Peak virtual memory: 297 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616150605101 ""} { "Error" "EQEXE_END_BANNER_TIME" "Fri Mar 19 06:43:25 2021 " "Processing ended: Fri Mar 19 06:43:25 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616150605101 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616150605101 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616150605101 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1616150605101 ""} +{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 8 s 1 " "Quartus II Full Compilation was unsuccessful. 8 errors, 1 warning" { } { } 0 293001 "Quartus II %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1616150605976 ""} diff --git a/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt b/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt index 19022e4..7d9fb22 100755 Binary files a/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt and b/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt differ diff --git a/cpld/output_files/GR8RAM.asm.rpt b/cpld/output_files/GR8RAM.asm.rpt index 35484a4..86126fb 100755 --- a/cpld/output_files/GR8RAM.asm.rpt +++ b/cpld/output_files/GR8RAM.asm.rpt @@ -1,5 +1,5 @@ Assembler report for GR8RAM -Thu Mar 18 04:40:52 2021 +Fri Mar 19 05:28:54 2021 Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition @@ -37,7 +37,7 @@ applicable agreement for further details. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Thu Mar 18 04:40:52 2021 ; +; Assembler Status ; Successful - Fri Mar 19 05:28:54 2021 ; ; Revision Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ; ; Family ; MAX II ; @@ -90,8 +90,8 @@ applicable agreement for further details. ; Option ; Setting ; +----------------+-------------------------------------------------------+ ; Device ; EPM240T100C5 ; -; JTAG usercode ; 0x00178E81 ; -; Checksum ; 0x001792F1 ; +; JTAG usercode ; 0x0016E052 ; +; Checksum ; 0x0016E4CA ; +----------------+-------------------------------------------------------+ @@ -101,13 +101,13 @@ applicable agreement for further details. Info: ******************************************************************* Info: Running Quartus II 32-bit Assembler Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - Info: Processing started: Thu Mar 18 04:40:50 2021 + Info: Processing started: Fri Mar 19 05:28:52 2021 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM Info (115031): Writing out detailed assembly data for power analysis Info (115030): Assembler is generating device programming files Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings Info: Peak virtual memory: 293 megabytes - Info: Processing ended: Thu Mar 18 04:40:52 2021 + Info: Processing ended: Fri Mar 19 05:28:54 2021 Info: Elapsed time: 00:00:02 Info: Total CPU time (on all processors): 00:00:02 diff --git a/cpld/output_files/GR8RAM.done b/cpld/output_files/GR8RAM.done index 8fb9de0..5e09f4e 100755 --- a/cpld/output_files/GR8RAM.done +++ b/cpld/output_files/GR8RAM.done @@ -1 +1 @@ -Fri Mar 19 02:49:01 2021 +Fri Mar 19 05:29:01 2021 diff --git a/cpld/output_files/GR8RAM.fit.rpt b/cpld/output_files/GR8RAM.fit.rpt index f3f960a..fbefcec 100755 --- a/cpld/output_files/GR8RAM.fit.rpt +++ b/cpld/output_files/GR8RAM.fit.rpt @@ -1,5 +1,5 @@ Fitter report for GR8RAM -Fri Mar 19 02:55:57 2021 +Fri Mar 19 06:44:01 2021 Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition @@ -50,17 +50,17 @@ applicable agreement for further details. +-----------------------------------------------------------------------------+ ; Fitter Summary ; +---------------------------+-------------------------------------------------+ -; Fitter Status ; Failed - Fri Mar 19 02:55:57 2021 ; +; Fitter Status ; Failed - Fri Mar 19 06:44:01 2021 ; ; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; ; Revision Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ; ; Family ; MAX II ; ; Device ; EPM240T100C5 ; ; Timing Models ; Final ; -; Total logic elements ; 313 / 240 ( 130 % ) ; -; Total pins ; 73 / 80 ( 91 % ) ; +; Total logic elements ; 250 / 240 ( 104 % ) ; +; Total pins ; 69 / 80 ( 86 % ) ; ; Total virtual pins ; 0 ; -; UFM blocks ; 1 / 1 ( 100 % ) ; +; UFM blocks ; 0 / 1 ( 0 % ) ; +---------------------------+-------------------------------------------------+ @@ -138,19 +138,19 @@ applicable agreement for further details. ; Total logic elements ; Not available ; ; ; ; ; Total LABs ; Not available ; -; Logic elements in carry chains ; 41 ; +; Logic elements in carry chains ; 51 ; ; Virtual pins ; 0 ; -; I/O pins ; 73 / 80 ( 91 % ) ; +; I/O pins ; 69 / 80 ( 86 % ) ; ; -- Clock pins ; 0 / 4 ( 0 % ) ; ; ; ; ; Global signals ; 1 ; -; UFM blocks ; 1 / 1 ( 100 % ) ; +; UFM blocks ; 0 / 1 ( 0 % ) ; ; Global clocks ; 1 / 4 ( 25 % ) ; ; JTAGs ; 0 / 1 ( 0 % ) ; -; Maximum fan-out ; 123 ; -; Highest non-global fan-out ; 33 ; -; Total fan-out ; 1329 ; -; Average fan-out ; 3.43 ; +; Maximum fan-out ; 99 ; +; Highest non-global fan-out ; 36 ; +; Total fan-out ; 1002 ; +; Average fan-out ; 3.14 ; +--------------------------------+------------------+ @@ -159,11 +159,9 @@ applicable agreement for further details. +---------+------------+----------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+ ; Name ; Pin # ; I/O Bank ; Combinational Fan-Out ; Registered Fan-Out ; Global ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Location assigned by ; +---------+------------+----------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+ -; C25M ; Unassigned ; -- ; 123 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; -; DMAin ; Unassigned ; -- ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; -; INTin ; Unassigned ; -- ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; +; C25M ; Unassigned ; -- ; 99 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; ; MISO ; Unassigned ; -- ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; -; PHI0 ; Unassigned ; -- ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; +; PHI0 ; Unassigned ; -- ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; ; RA[0] ; Unassigned ; -- ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; ; RA[10] ; Unassigned ; -- ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; ; RA[11] ; Unassigned ; -- ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; @@ -181,11 +179,11 @@ applicable agreement for further details. ; RA[8] ; Unassigned ; -- ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; ; RA[9] ; Unassigned ; -- ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; ; nBOD ; Unassigned ; -- ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; -; nDEVSEL ; Unassigned ; -- ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; -; nIOSEL ; Unassigned ; -- ; 0 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; -; nIOSTRB ; Unassigned ; -- ; 0 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; +; nDEVSEL ; Unassigned ; -- ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; +; nIOSEL ; Unassigned ; -- ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; +; nIOSTRB ; Unassigned ; -- ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; ; nRES ; Unassigned ; -- ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; -; nWE ; Unassigned ; -- ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; +; nWE ; Unassigned ; -- ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; +---------+------------+----------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+ @@ -194,11 +192,9 @@ applicable agreement for further details. +---------+------------+----------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ ; Name ; Pin # ; I/O Bank ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ; +---------+------------+----------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ -; DMAout ; Unassigned ; -- ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; - ; - ; ; DQMH ; Unassigned ; -- ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; - ; - ; ; DQML ; Unassigned ; -- ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; - ; - ; ; FCK ; Unassigned ; -- ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; - ; - ; -; INTout ; Unassigned ; -- ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; - ; - ; ; MOSI ; Unassigned ; -- ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; - ; - ; ; RAdir ; Unassigned ; -- ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; - ; - ; ; RCKE ; Unassigned ; -- ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; - ; - ; @@ -232,20 +228,20 @@ applicable agreement for further details. +-------+------------+----------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ ; Name ; Pin # ; I/O Bank ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ; +-------+------------+----------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ -; RD[0] ; Unassigned ; -- ; 4 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; - ; - ; -; RD[1] ; Unassigned ; -- ; 5 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; - ; - ; -; RD[2] ; Unassigned ; -- ; 4 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; - ; - ; -; RD[3] ; Unassigned ; -- ; 4 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; - ; - ; -; RD[4] ; Unassigned ; -- ; 4 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; - ; - ; -; RD[5] ; Unassigned ; -- ; 4 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; - ; - ; -; RD[6] ; Unassigned ; -- ; 4 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; - ; - ; -; RD[7] ; Unassigned ; -- ; 6 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; - ; - ; -; SD[0] ; Unassigned ; -- ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; SDOE ; - ; -; SD[1] ; Unassigned ; -- ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; SDOE ; - ; -; SD[2] ; Unassigned ; -- ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; SDOE ; - ; -; SD[3] ; Unassigned ; -- ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; SDOE ; - ; -; SD[4] ; Unassigned ; -- ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; SDOE ; - ; -; SD[5] ; Unassigned ; -- ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; SDOE ; - ; +; RD[0] ; Unassigned ; -- ; 4 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; comb~2 (inverted) ; - ; +; RD[1] ; Unassigned ; -- ; 4 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; comb~2 (inverted) ; - ; +; RD[2] ; Unassigned ; -- ; 3 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; comb~2 (inverted) ; - ; +; RD[3] ; Unassigned ; -- ; 3 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; comb~2 (inverted) ; - ; +; RD[4] ; Unassigned ; -- ; 2 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; comb~2 (inverted) ; - ; +; RD[5] ; Unassigned ; -- ; 2 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; comb~2 (inverted) ; - ; +; RD[6] ; Unassigned ; -- ; 2 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; comb~2 (inverted) ; - ; +; RD[7] ; Unassigned ; -- ; 4 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; comb~2 (inverted) ; - ; +; SD[0] ; Unassigned ; -- ; 0 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; SDOE ; - ; +; SD[1] ; Unassigned ; -- ; 0 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; SDOE ; - ; +; SD[2] ; Unassigned ; -- ; 0 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; SDOE ; - ; +; SD[3] ; Unassigned ; -- ; 0 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; SDOE ; - ; +; SD[4] ; Unassigned ; -- ; 0 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; SDOE ; - ; +; SD[5] ; Unassigned ; -- ; 0 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; SDOE ; - ; ; SD[6] ; Unassigned ; -- ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; SDOE ; - ; ; SD[7] ; Unassigned ; -- ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; SDOE ; - ; +-------+------------+----------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ @@ -258,7 +254,7 @@ applicable agreement for further details. +----------+----------------+---------------+--------------+ ; 1 ; 0 / 38 ( 0 % ) ; 3.3V ; -- ; ; 2 ; 0 / 42 ( 0 % ) ; 3.3V ; -- ; -; Unknown ; 73 ; -- ; ; +; Unknown ; 69 ; -- ; ; +----------+----------------+---------------+--------------+ @@ -387,15 +383,13 @@ Note: Pin directions (input, output or bidir) are based on device operating in u Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables. -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Fitter Resource Utilization by Entity ; -+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+ -; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ; -+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+ -; |GR8RAM ; 313 (313) ; 123 ; 1 ; 73 ; 0 ; 190 (190) ; 0 (0) ; 123 (123) ; 41 (41) ; 30 (30) ; |GR8RAM ; work ; -; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |GR8RAM|UFM:UFM_inst ; work ; -; |UFM_altufm_none_0ep:UFM_altufm_none_0ep_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |GR8RAM|UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component ; work ; -+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+ ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ; ++----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+ +; |GR8RAM ; 250 (250) ; 99 ; 0 ; 69 ; 0 ; 151 (151) ; 0 (0) ; 99 (99) ; 51 (51) ; 27 (27) ; |GR8RAM ; work ; ++----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. @@ -404,38 +398,34 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +---------+----------+---------------+ ; Name ; Pin Type ; Pad to Core 0 ; +---------+----------+---------------+ -; nIOSEL ; Input ; 0 ; -; nIOSTRB ; Input ; 0 ; -; DMAin ; Input ; 0 ; -; INTin ; Input ; 0 ; -; C25M ; Input ; 0 ; +; PHI0 ; Input ; 0 ; ; nWE ; Input ; 0 ; -; RA[8] ; Input ; 0 ; -; RA[9] ; Input ; 0 ; -; RA[10] ; Input ; 0 ; -; RA[11] ; Input ; 0 ; -; RA[14] ; Input ; 0 ; -; RA[15] ; Input ; 0 ; -; RA[12] ; Input ; 0 ; -; RA[13] ; Input ; 0 ; +; nDEVSEL ; Input ; 0 ; +; nIOSTRB ; Input ; 0 ; +; nIOSEL ; Input ; 0 ; +; C25M ; Input ; 0 ; ; RA[1] ; Input ; 0 ; -; RA[0] ; Input ; 0 ; +; RA[10] ; Input ; 0 ; ; RA[2] ; Input ; 0 ; +; RA[11] ; Input ; 0 ; ; RA[3] ; Input ; 0 ; ; RA[4] ; Input ; 0 ; ; RA[5] ; Input ; 0 ; ; RA[6] ; Input ; 0 ; ; RA[7] ; Input ; 0 ; -; nDEVSEL ; Input ; 0 ; -; MISO ; Input ; 0 ; +; RA[8] ; Input ; 0 ; +; RA[9] ; Input ; 0 ; +; RA[0] ; Input ; 0 ; ; nRES ; Input ; 0 ; -; PHI0 ; Input ; 0 ; +; RA[14] ; Input ; 0 ; +; RA[15] ; Input ; 0 ; +; RA[12] ; Input ; 0 ; +; RA[13] ; Input ; 0 ; +; MISO ; Input ; 0 ; ; nBOD ; Input ; 0 ; +; nRESout ; Output ; -- ; ; RAdir ; Output ; -- ; ; RDdir ; Output ; -- ; -; DMAout ; Output ; -- ; -; INTout ; Output ; -- ; -; nRESout ; Output ; -- ; ; SBA[0] ; Output ; -- ; ; SBA[1] ; Output ; -- ; ; SA[0] ; Output ; -- ; @@ -480,29 +470,27 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +---------+----------+---------------+ -+------------------------------------------------------------------------------------------------------------------+ -; Control Signals ; -+------------+------------+---------+---------------------------+--------+----------------------+------------------+ -; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; -+------------+------------+---------+---------------------------+--------+----------------------+------------------+ -; Addr[23]~2 ; Unassigned ; 8 ; Clock enable ; no ; -- ; -- ; -; Addr[2]~3 ; Unassigned ; 8 ; Clock enable ; no ; -- ; -- ; -; Addr[8]~5 ; Unassigned ; 8 ; Clock enable ; no ; -- ; -- ; -; C25M ; Unassigned ; 123 ; Clock ; yes ; Global Clock ; Not Available ; -; DQMH~8 ; Unassigned ; 2 ; Clock enable ; no ; -- ; -- ; -; DRShift~0 ; Unassigned ; 6 ; Clock enable ; no ; -- ; -- ; -; DRShift~2 ; Unassigned ; 3 ; Clock enable ; no ; -- ; -- ; -; Equal0~0 ; Unassigned ; 2 ; Clock enable ; no ; -- ; -- ; -; IS[1]~2 ; Unassigned ; 1 ; Clock enable ; no ; -- ; -- ; -; InitActv ; Unassigned ; 25 ; Clock enable, Sync. clear ; no ; -- ; -- ; -; MOSIOE ; Unassigned ; 3 ; Output enable ; no ; -- ; -- ; -; MOSIOE~0 ; Unassigned ; 2 ; Clock enable ; no ; -- ; -- ; -; SDOE ; Unassigned ; 8 ; Output enable ; no ; -- ; -- ; -; S[3] ; Unassigned ; 26 ; Clock enable ; no ; -- ; -- ; -; WRD[0]~0 ; Unassigned ; 6 ; Clock enable ; no ; -- ; -- ; -; always7~0 ; Unassigned ; 15 ; Clock enable ; no ; -- ; -- ; -; nRESr ; Unassigned ; 28 ; Sync. clear, Sync. load ; no ; -- ; -- ; -+------------+------------+---------+---------------------------+--------+----------------------+------------------+ ++-----------------------------------------------------------------------------------------------------------------+ +; Control Signals ; ++-------------+------------+---------+-------------------------+--------+----------------------+------------------+ +; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; ++-------------+------------+---------+-------------------------+--------+----------------------+------------------+ +; Addr[14]~8 ; Unassigned ; 8 ; Clock enable ; no ; -- ; -- ; +; Addr[17]~19 ; Unassigned ; 4 ; Clock enable ; no ; -- ; -- ; +; Addr[4]~10 ; Unassigned ; 8 ; Clock enable ; no ; -- ; -- ; +; Bank[0]~1 ; Unassigned ; 2 ; Clock enable ; no ; -- ; -- ; +; C25M ; Unassigned ; 99 ; Clock ; yes ; Global Clock ; Not Available ; +; Equal0~3 ; Unassigned ; 3 ; Clock enable ; no ; -- ; -- ; +; IS[0]~4 ; Unassigned ; 2 ; Clock enable ; no ; -- ; -- ; +; InitActv ; Unassigned ; 23 ; Sync. clear ; no ; -- ; -- ; +; MOSIOE ; Unassigned ; 3 ; Output enable ; no ; -- ; -- ; +; MOSIout~2 ; Unassigned ; 2 ; Clock enable ; no ; -- ; -- ; +; PSStart~2 ; Unassigned ; 18 ; Clock enable ; no ; -- ; -- ; +; PS[2] ; Unassigned ; 17 ; Sync. load ; no ; -- ; -- ; +; SDOE ; Unassigned ; 8 ; Output enable ; no ; -- ; -- ; +; always15~0 ; Unassigned ; 2 ; Clock enable ; no ; -- ; -- ; +; nRESr ; Unassigned ; 36 ; Sync. clear, Sync. load ; no ; -- ; -- ; ++-------------+------------+---------+-------------------------+--------+----------------------+------------------+ +-----------------------------------------------------------------------+ @@ -510,425 +498,372 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +------+------------+---------+----------------------+------------------+ ; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; +------+------------+---------+----------------------+------------------+ -; C25M ; Unassigned ; 123 ; Global Clock ; Not Available ; +; C25M ; Unassigned ; 99 ; Global Clock ; Not Available ; +------+------------+---------+----------------------+------------------+ -+-------------------------------------------------------------------------------------------------------+ -; Non-Global High Fan-Out Signals ; -+---------------------------------------------------------------------------------------------+---------+ -; Name ; Fan-Out ; -+---------------------------------------------------------------------------------------------+---------+ -; nWEcur ; 33 ; -; nRESr ; 28 ; -; S[3] ; 26 ; -; S[2] ; 26 ; -; always20~1 ; 25 ; -; InitActv ; 25 ; -; LS[1] ; 25 ; -; S[1] ; 22 ; -; LS[4] ; 22 ; -; S[0] ; 20 ; -; LS[2] ; 20 ; -; IS[1] ; 18 ; -; LS[0] ; 18 ; -; LS[3] ; 16 ; -; always7~0 ; 15 ; -; IS[0] ; 15 ; -; Equal79~0 ; 13 ; -; LS[6] ; 13 ; -; Equal8~2 ; 10 ; -; Equal78~0 ; 10 ; -; LS[5] ; 10 ; -; Equal9~0 ; 9 ; -; always10~2 ; 9 ; -; RAMSpecSEL~0 ; 9 ; -; LessThan1~0 ; 9 ; -; SDOE ; 8 ; -; Addr[8]~5 ; 8 ; -; Addr[2]~3 ; 8 ; -; Addr[23]~2 ; 8 ; -; SA[7]~48 ; 8 ; -; SA[7]~47 ; 8 ; -; Equal17~0 ; 7 ; -; RAMSEL ; 7 ; -; LS[13] ; 7 ; -; LS[12] ; 7 ; -; RD[7]~7 ; 6 ; -; WRD[0]~0 ; 6 ; -; DRShift~1 ; 6 ; -; DRShift~0 ; 6 ; -; DQMH~5 ; 6 ; -; Equal73~0 ; 6 ; -; SA~25 ; 6 ; -; RAcur[0] ; 6 ; -; LS[17] ; 6 ; -; LS[16] ; 6 ; -; LS[15] ; 6 ; -; LS[14] ; 6 ; -; CmdActv ; 6 ; -; RD[1]~1 ; 5 ; -; SA[7]~84 ; 5 ; -; nBODf ; 5 ; -; RAcur[2] ; 5 ; -; Equal68~0 ; 5 ; -; SetLoaded ; 5 ; -; always20~2 ; 5 ; -; Addr[7] ; 5 ; -; RAcur[3] ; 5 ; -; Addr[10] ; 5 ; -; Addr[0] ; 5 ; -; always20~0 ; 5 ; -; RAcur[1] ; 5 ; -; Equal1~5 ; 5 ; -; LS[7] ; 5 ; -; Equal1~0 ; 5 ; -; SetFW[1]~_wirecell ; 4 ; -; RD[6]~6 ; 4 ; -; RD[5]~5 ; 4 ; -; RD[4]~4 ; 4 ; -; RD[3]~3 ; 4 ; -; RD[2]~2 ; 4 ; -; RD[0]~0 ; 4 ; -; always10~3 ; 4 ; -; MOSIout~0 ; 4 ; -; DEVSELr ; 4 ; -; Addr[9] ; 4 ; -; Addr[8] ; 4 ; -; Addr[6] ; 4 ; -; Addr[15] ; 4 ; -; Addr[5] ; 4 ; -; Addr[4] ; 4 ; -; Addr[3] ; 4 ; -; Addr[2] ; 4 ; -; SA[12]~21 ; 4 ; -; Addr[1] ; 4 ; -; SBA~5 ; 4 ; -; RefDone ; 4 ; -; RAMSpecRD ; 4 ; -; LS[11] ; 4 ; -; LS[10] ; 4 ; -; LS[9] ; 4 ; -; LS[8] ; 4 ; -; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|wire_maxii_ufm_block1_drdout ; 4 ; -; SA[2]~80 ; 3 ; -; Equal17~2 ; 3 ; -; Equal31~1 ; 3 ; -; SetFW[1] ; 3 ; -; DRShift~2 ; 3 ; -; MOSIOE ; 3 ; -; RAMSEL~0 ; 3 ; -; Equal84~0 ; 3 ; -; Addr[14] ; 3 ; -; Addr[13] ; 3 ; -; SA~38 ; 3 ; -; Addr[12] ; 3 ; -; Addr[11] ; 3 ; -; SA[2]~26 ; 3 ; -; SA[2]~22 ; 3 ; -; SA[2]~18 ; 3 ; -; SA[2]~17 ; 3 ; -; SA[2]~16 ; 3 ; -; Equal2~2 ; 3 ; -; Equal1~3 ; 3 ; -; Equal1~2 ; 3 ; -; Equal1~1 ; 3 ; -; nSWE~reg0 ; 3 ; -; nCAS~reg0 ; 3 ; -; nRAS~reg0 ; 3 ; -; nRCS~reg0 ; 3 ; -; SA[10]~reg0 ; 3 ; -; SA[9]~reg0 ; 3 ; -; SA[3]~reg0 ; 3 ; -; always10~11 ; 2 ; -; DQMH~12 ; 2 ; -; Equal33~1 ; 2 ; -; SetFW~0 ; 2 ; -; MOSIOE~0 ; 2 ; -; SetFW[0] ; 2 ; -; IS[1]~0 ; 2 ; -; Equal67~1 ; 2 ; -; SDRAMActv ; 2 ; -; PHI0r1 ; 2 ; -; always10~7 ; 2 ; -; Equal0~0 ; 2 ; -; Equal17~1 ; 2 ; -; MOSIout ; 2 ; -; FCKEN ; 2 ; -; Equal30~0 ; 2 ; -; Equal67~0 ; 2 ; -; Equal31~0 ; 2 ; -; LessThan0~0 ; 2 ; -; FCS~1 ; 2 ; -; FCS~0 ; 2 ; -; DQMH~8 ; 2 ; -; DQMH~6 ; 2 ; -; DQMH~4 ; 2 ; -; Addr[22] ; 2 ; -; Addr[21] ; 2 ; -; Addr[20] ; 2 ; -; Addr[19] ; 2 ; -; Addr[18] ; 2 ; -; Addr[17] ; 2 ; -; Addr[16] ; 2 ; -; SDOE~0 ; 2 ; -; Bank[1] ; 2 ; -; Equal77~1 ; 2 ; -; Equal77~0 ; 2 ; -; SBA~6 ; 2 ; -; SBA~2 ; 2 ; -; SetLim8M ; 2 ; -; RACr ; 2 ; -; Equal4~0 ; 2 ; -; Addr[23] ; 2 ; -; SDRAMActv~0 ; 2 ; -; InitIntr ; 2 ; -; Equal2~1 ; 2 ; -; ARCLK ; 2 ; -; FCS ; 2 ; -; SBA[1]~reg0 ; 2 ; -; SBA[0]~reg0 ; 2 ; -; nBOD ; 1 ; -; PHI0 ; 1 ; -; nRES ; 1 ; -; MISO ; 1 ; -; nDEVSEL ; 1 ; -; RA[7] ; 1 ; -; RA[6] ; 1 ; -; RA[5] ; 1 ; -; RA[4] ; 1 ; -; RA[3] ; 1 ; -; RA[2] ; 1 ; -; RA[0] ; 1 ; -; RA[1] ; 1 ; -; RA[13] ; 1 ; -; RA[12] ; 1 ; -; RA[15] ; 1 ; -; RA[14] ; 1 ; -; RA[11] ; 1 ; -; RA[10] ; 1 ; -; RA[9] ; 1 ; -; RA[8] ; 1 ; -; nWE ; 1 ; -; INTin ; 1 ; -; DMAin ; 1 ; -; ~GND ; 1 ; -; ARShift~3 ; 1 ; -; DQMH~13 ; 1 ; -; DQML~5 ; 1 ; -; SA~83 ; 1 ; -; SA~82 ; 1 ; -; SA~81 ; 1 ; -; SDOE~1 ; 1 ; -; SetFW~3 ; 1 ; -; SetFW~1 ; 1 ; -; SetLoaded~1 ; 1 ; -; SetLoaded~0 ; 1 ; -; WRD[7] ; 1 ; -; WRD[6] ; 1 ; -; Equal32~0 ; 1 ; -; Equal18~0 ; 1 ; -; Equal17~3 ; 1 ; -; Equal19~0 ; 1 ; -; MOSIout~4 ; 1 ; -; MOSIout~3 ; 1 ; -; MOSIout~2 ; 1 ; -; MOSIout~1 ; 1 ; -; FCKEN~1 ; 1 ; -; FCKEN~0 ; 1 ; -; DEVSELr0 ; 1 ; -; Equal84~1 ; 1 ; -; Add1~37 ; 1 ; -; Add1~35 ; 1 ; -; Add1~32 ; 1 ; -; Add1~30 ; 1 ; -; Add1~27 ; 1 ; -; Add1~25 ; 1 ; -; Add1~22 ; 1 ; -; Add1~20 ; 1 ; -; Add2~37 ; 1 ; -; Add2~35 ; 1 ; -; Add1~17 ; 1 ; -; Add1~15 ; 1 ; -; Add2~32 ; 1 ; -; Add2~30 ; 1 ; -; Add1~12 ; 1 ; -; Add1~10 ; 1 ; -; Add3~35 ; 1 ; -; Add1~7 ; 1 ; -; Add1~5 ; 1 ; -; Add3~32 ; 1 ; -; Add3~30 ; 1 ; -; Add2~25 ; 1 ; -; Add3~27 ; 1 ; -; Add3~25 ; 1 ; -; Add2~22 ; 1 ; -; Add2~20 ; 1 ; -; Add2~17 ; 1 ; -; Add2~15 ; 1 ; -; Add3~22 ; 1 ; -; Add3~20 ; 1 ; -; Add2~12 ; 1 ; -; Add2~10 ; 1 ; -; always11~1 ; 1 ; -; always11~0 ; 1 ; -; Add3~17 ; 1 ; -; Add3~15 ; 1 ; -; Add2~7 ; 1 ; -; Add2~5 ; 1 ; -; Add3~12 ; 1 ; -; Add3~10 ; 1 ; -; Addr[8]~4 ; 1 ; -; Add2~2 ; 1 ; -; Add2~0 ; 1 ; -; Add3~7 ; 1 ; -; Add3~5 ; 1 ; -; Add3~2 ; 1 ; -; Add3~0 ; 1 ; -; IS[1]~2 ; 1 ; -; Equal68~1 ; 1 ; -; Equal1~6 ; 1 ; -; PHI0r2 ; 1 ; -; RefDone~0 ; 1 ; -; S~1 ; 1 ; -; SetLim8M~0 ; 1 ; -; Addr[23]~1 ; 1 ; -; always10~10 ; 1 ; -; always10~9 ; 1 ; -; always10~8 ; 1 ; -; always10~6 ; 1 ; -; always10~5 ; 1 ; -; Addr[23]~0 ; 1 ; -; always10~4 ; 1 ; -; Equal8~1 ; 1 ; -; Add1~0 ; 1 ; -; InitActv~0 ; 1 ; -; Equal33~0 ; 1 ; -; ARCLK~1 ; 1 ; -; ARCLK~0 ; 1 ; -; always15~0 ; 1 ; -; FCS~2 ; 1 ; -; DQMH~10 ; 1 ; -; DQMH~9 ; 1 ; -; DQMH~7 ; 1 ; -; DQML~3 ; 1 ; -; DQML~2 ; 1 ; -; nSWE~2 ; 1 ; -; nSWE~1 ; 1 ; -; nSWE~0 ; 1 ; -; nCAS~4 ; 1 ; -; nCAS~3 ; 1 ; -; nCAS~2 ; 1 ; -; nCAS~1 ; 1 ; -; nCAS~0 ; 1 ; -; nRAS~3 ; 1 ; -; nRAS~2 ; 1 ; -; nRAS~1 ; 1 ; -; nRAS~0 ; 1 ; -; nRCS~4 ; 1 ; -; nRCS~3 ; 1 ; -; nRCS~2 ; 1 ; -; nRCS~1 ; 1 ; -; nRCS~0 ; 1 ; -; SA~78 ; 1 ; -; SA~77 ; 1 ; -; SA~76 ; 1 ; -; SA~74 ; 1 ; -; SA~73 ; 1 ; -; SA~72 ; 1 ; -; SA~71 ; 1 ; -; SA~70 ; 1 ; -; SA~68 ; 1 ; -; SA~67 ; 1 ; -; RAcur[9] ; 1 ; -; SA~66 ; 1 ; -; SA~64 ; 1 ; -; SA~63 ; 1 ; -; SA~62 ; 1 ; -; SA~60 ; 1 ; -; SA~59 ; 1 ; -; SA~58 ; 1 ; -; SA~56 ; 1 ; -; SA~55 ; 1 ; -; SA~54 ; 1 ; -; SA~53 ; 1 ; -; SA~51 ; 1 ; -; SA~50 ; 1 ; -; SA~49 ; 1 ; -; SA~45 ; 1 ; -; SA~44 ; 1 ; -; SA~43 ; 1 ; -; SA~42 ; 1 ; -; SA~41 ; 1 ; -; SA~40 ; 1 ; -; SA~39 ; 1 ; -; SA~36 ; 1 ; -; SA~35 ; 1 ; -; SA~34 ; 1 ; -; SA~33 ; 1 ; -; SA~31 ; 1 ; -; SA~30 ; 1 ; -; SA~29 ; 1 ; -; RAcur[11] ; 1 ; -; SA~28 ; 1 ; -; SA~24 ; 1 ; -; SA~23 ; 1 ; -; SA~20 ; 1 ; -; RAcur[10] ; 1 ; -; SA~19 ; 1 ; -; nBODr0 ; 1 ; -; PHI0r0 ; 1 ; -; nRESr0 ; 1 ; -; SBA~7 ; 1 ; -; nBODr ; 1 ; -; WRD[5] ; 1 ; -; WRD[4] ; 1 ; -; SBA~4 ; 1 ; -; WRD[3] ; 1 ; -; SBA~1 ; 1 ; -; SBA~0 ; 1 ; -; Equal8~0 ; 1 ; -; RAcur[8] ; 1 ; -; WRD[2] ; 1 ; -; WRD[1] ; 1 ; -; CmdActv~0 ; 1 ; -; WRD[0] ; 1 ; -; Equal2~0 ; 1 ; -; nBODf0 ; 1 ; -; Equal1~4 ; 1 ; -; LS[16]~31 ; 1 ; -; LS[4]~29 ; 1 ; -; LS[15]~27 ; 1 ; -; LS[14]~25 ; 1 ; -; LS[13]~23 ; 1 ; -; LS[12]~21 ; 1 ; -; LS[11]~19 ; 1 ; -; LS[10]~17 ; 1 ; -; LS[9]~15 ; 1 ; -; LS[8]~13 ; 1 ; -; LS[6]~11 ; 1 ; -; LS[5]~9 ; 1 ; -; LS[7]~7 ; 1 ; -; LS[3]~5 ; 1 ; -; LS[2]~3 ; 1 ; -; LS[1]~1 ; 1 ; -; ARShift ; 1 ; -; DRShift ; 1 ; -; DRCLK ; 1 ; -; FCK~reg0 ; 1 ; -; DQMH~reg0 ; 1 ; -; DQML~reg0 ; 1 ; -; SA[12]~reg0 ; 1 ; -; SA[11]~reg0 ; 1 ; -; SA[8]~reg0 ; 1 ; -; SA[7]~reg0 ; 1 ; -; SA[6]~reg0 ; 1 ; -; SA[5]~reg0 ; 1 ; -; SA[4]~reg0 ; 1 ; -; SA[2]~reg0 ; 1 ; -; SA[1]~reg0 ; 1 ; -; SA[0]~reg0 ; 1 ; -+---------------------------------------------------------------------------------------------+---------+ ++---------------------------------+ +; Non-Global High Fan-Out Signals ; ++--------------+------------------+ +; Name ; Fan-Out ; ++--------------+------------------+ +; nRESr ; 36 ; +; InitActv ; 23 ; +; RAMSpecSEL~4 ; 19 ; +; PS[1] ; 19 ; +; Amux[1] ; 19 ; +; PSStart~2 ; 18 ; +; Amux[0] ; 18 ; +; PS[2] ; 17 ; +; Amux[2] ; 17 ; +; PS[0] ; 16 ; +; RAcur[0] ; 15 ; +; always11~0 ; 13 ; +; LS[2] ; 12 ; +; LS[1] ; 12 ; +; LS[0] ; 11 ; +; LS[3] ; 11 ; +; LS[4] ; 9 ; +; comb~2 ; 9 ; +; Addr[4]~10 ; 8 ; +; Addr[14]~8 ; 8 ; +; RAMSpecSEL~2 ; 8 ; +; LS[5] ; 8 ; +; SDOE ; 8 ; +; Addr[17] ; 7 ; +; Addr[16] ; 7 ; +; Addr[4]~9 ; 7 ; +; IS[1] ; 7 ; +; RAMSpecSEL~3 ; 7 ; +; nWEcur ; 6 ; +; Addr[18] ; 6 ; +; Addr[17]~16 ; 6 ; +; Equal15~0 ; 5 ; +; Addr[19] ; 5 ; +; IS[0] ; 5 ; +; always11~1 ; 5 ; +; LS[6] ; 5 ; +; Equal36~1 ; 5 ; +; RD[7]~7 ; 4 ; +; RD[1]~1 ; 4 ; +; RD[0]~0 ; 4 ; +; Equal16~1 ; 4 ; +; always19~1 ; 4 ; +; Mux6~3 ; 4 ; +; Addr[17]~19 ; 4 ; +; RACr ; 4 ; +; RAcur[1] ; 4 ; +; Equal7~0 ; 4 ; +; Equal16~0 ; 4 ; +; nBODf ; 4 ; +; LS[17] ; 4 ; +; LS[16] ; 4 ; +; LS[7] ; 4 ; +; Equal2~0 ; 4 ; +; Addr[7] ; 4 ; +; Addr[15] ; 4 ; +; Addr[23] ; 4 ; +; RD[3]~3 ; 3 ; +; RD[2]~2 ; 3 ; +; Equal33~0 ; 3 ; +; Equal30~0 ; 3 ; +; MOSIOE ; 3 ; +; Equal12~0 ; 3 ; +; nRCS~0 ; 3 ; +; RefReqd ; 3 ; +; Addr~4 ; 3 ; +; RAcur[2] ; 3 ; +; RAcur[3] ; 3 ; +; always6~0 ; 3 ; +; Equal0~3 ; 3 ; +; Equal2~4 ; 3 ; +; LS[15] ; 3 ; +; LS[14] ; 3 ; +; LS[13] ; 3 ; +; LS[12] ; 3 ; +; LS[11] ; 3 ; +; LS[10] ; 3 ; +; LS[9] ; 3 ; +; LS[8] ; 3 ; +; Addr[20] ; 3 ; +; Addr[9] ; 3 ; +; Addr[8] ; 3 ; +; Addr[14] ; 3 ; +; Addr[13] ; 3 ; +; Addr[12] ; 3 ; +; Addr[11] ; 3 ; +; Addr[10] ; 3 ; +; REGEN ; 3 ; +; RD[6]~6 ; 2 ; +; RD[5]~5 ; 2 ; +; RD[4]~4 ; 2 ; +; nIOSEL ; 2 ; +; nIOSTRB ; 2 ; +; nDEVSEL ; 2 ; +; nWE ; 2 ; +; PHI0 ; 2 ; +; IS[0]~4 ; 2 ; +; always15~0 ; 2 ; +; MOSIout~2 ; 2 ; +; Equal15~2 ; 2 ; +; SDRAMActv ; 2 ; +; Equal15~1 ; 2 ; +; MOSIout ; 2 ; +; FCKEN ; 2 ; +; Equal0~4 ; 2 ; +; FCS~3 ; 2 ; +; FCS~2 ; 2 ; +; Mux7~1 ; 2 ; +; Mux7~0 ; 2 ; +; always19~0 ; 2 ; +; Bank[0]~1 ; 2 ; +; Mux11~0 ; 2 ; +; DEVSELr ; 2 ; +; RAcur[7] ; 2 ; +; RAcur[10] ; 2 ; +; RAMSpecSEL~1 ; 2 ; +; always10~3 ; 2 ; +; always10~0 ; 2 ; +; RAMSpecSEL~0 ; 2 ; +; IOSELr ; 2 ; +; Equal0~2 ; 2 ; +; Equal35~0 ; 2 ; +; SDRAMActv~0 ; 2 ; +; InitIntr ; 2 ; +; Equal2~6 ; 2 ; +; FCS ; 2 ; +; RCKE~reg0 ; 2 ; +; DQML~1 ; 2 ; +; DQML~0 ; 2 ; +; Addr[0] ; 2 ; +; SA~24 ; 2 ; +; RAcur[9] ; 2 ; +; RAcur[8] ; 2 ; +; Addr[6] ; 2 ; +; Addr[5] ; 2 ; +; Addr[4] ; 2 ; +; Addr[3] ; 2 ; +; Addr[2] ; 2 ; +; Addr[1] ; 2 ; +; IOROMEN ; 2 ; +; nRESout~reg0 ; 2 ; +; nBOD ; 1 ; +; MISO ; 1 ; +; RA[13] ; 1 ; +; RA[12] ; 1 ; +; RA[15] ; 1 ; +; RA[14] ; 1 ; +; nRES ; 1 ; +; RA[0] ; 1 ; +; RA[9] ; 1 ; +; RA[8] ; 1 ; +; RA[7] ; 1 ; +; RA[6] ; 1 ; +; RA[5] ; 1 ; +; RA[4] ; 1 ; +; RA[3] ; 1 ; +; RA[11] ; 1 ; +; RA[2] ; 1 ; +; RA[10] ; 1 ; +; RA[1] ; 1 ; +; MOSIout~3 ; 1 ; +; Equal17~2 ; 1 ; +; Addr~31 ; 1 ; +; WRD[6] ; 1 ; +; Equal31~0 ; 1 ; +; Equal16~2 ; 1 ; +; FCKEN~1 ; 1 ; +; Equal30~1 ; 1 ; +; DEVSELr0 ; 1 ; +; IOSTRBr0 ; 1 ; +; IOSELr0 ; 1 ; +; FCKEN~0 ; 1 ; +; FCS~4 ; 1 ; +; Mux5~2 ; 1 ; +; Mux5~1 ; 1 ; +; Mux5~0 ; 1 ; +; Add1~102 ; 1 ; +; Add1~100 ; 1 ; +; Mux9~1 ; 1 ; +; Mux9~0 ; 1 ; +; Mux8~1 ; 1 ; +; Mux8~0 ; 1 ; +; Mux6~6 ; 1 ; +; Mux7~5 ; 1 ; +; Mux7~4 ; 1 ; +; Mux7~3 ; 1 ; +; Mux7~2 ; 1 ; +; Mux6~4 ; 1 ; +; Mux6~2 ; 1 ; +; Mux6~1 ; 1 ; +; Mux6~0 ; 1 ; +; Addr~30 ; 1 ; +; Addr~29 ; 1 ; +; Add2~60 ; 1 ; +; Addr~28 ; 1 ; +; Add1~95 ; 1 ; +; Add1~92 ; 1 ; +; Add1~90 ; 1 ; +; Addr~26 ; 1 ; +; Add3~2 ; 1 ; +; Add2~57 ; 1 ; +; Add2~55 ; 1 ; +; Add1~87 ; 1 ; +; Add1~85 ; 1 ; +; Addr~24 ; 1 ; +; Add2~52 ; 1 ; +; Add2~50 ; 1 ; +; Add3~1 ; 1 ; +; Add1~82 ; 1 ; +; Add1~80 ; 1 ; +; Addr~23 ; 1 ; +; Add2~47 ; 1 ; +; Add2~45 ; 1 ; +; Add1~77 ; 1 ; +; Add1~75 ; 1 ; +; Addr~21 ; 1 ; +; Add3~0 ; 1 ; +; Add2~42 ; 1 ; +; Add2~40 ; 1 ; +; Add1~72 ; 1 ; +; Add1~70 ; 1 ; +; Addr~20 ; 1 ; +; Add2~37 ; 1 ; +; Add2~35 ; 1 ; +; Add1~67 ; 1 ; +; Add1~65 ; 1 ; +; Addr~17 ; 1 ; +; Add2~32 ; 1 ; +; Add2~30 ; 1 ; +; Add1~62 ; 1 ; +; Add1~60 ; 1 ; +; Add1~57 ; 1 ; +; Add1~55 ; 1 ; +; Addr~15 ; 1 ; +; Add2~27 ; 1 ; +; Add2~25 ; 1 ; +; Add1~52 ; 1 ; +; Add1~50 ; 1 ; +; Add1~47 ; 1 ; +; Add1~45 ; 1 ; +; Addr~14 ; 1 ; +; Add2~22 ; 1 ; +; Add2~20 ; 1 ; +; Add1~42 ; 1 ; +; Add1~40 ; 1 ; +; Add1~37 ; 1 ; +; Add1~35 ; 1 ; +; Add1~32 ; 1 ; +; Add1~30 ; 1 ; +; Addr~13 ; 1 ; +; Add2~17 ; 1 ; +; Add2~15 ; 1 ; +; Add1~27 ; 1 ; +; Add1~25 ; 1 ; +; Add1~22 ; 1 ; +; Add1~20 ; 1 ; +; Addr~12 ; 1 ; +; Add2~12 ; 1 ; +; Add2~10 ; 1 ; +; Add1~17 ; 1 ; +; Add1~15 ; 1 ; +; Add1~12 ; 1 ; +; Add1~10 ; 1 ; +; Addr~11 ; 1 ; +; Add2~7 ; 1 ; +; Add2~5 ; 1 ; +; Add1~7 ; 1 ; +; Add1~5 ; 1 ; +; Addr[14]~7 ; 1 ; +; Add1~2 ; 1 ; +; Add1~0 ; 1 ; +; Addr~6 ; 1 ; +; Add2~2 ; 1 ; +; Add2~0 ; 1 ; +; PHI0r1 ; 1 ; +; PSStart~1 ; 1 ; +; WideOr0~2 ; 1 ; +; WideOr0~1 ; 1 ; +; ROMSpecRD ; 1 ; +; Mux10~0 ; 1 ; +; PSStart~0 ; 1 ; +; Mux11~1 ; 1 ; +; Addr~5 ; 1 ; +; Addr~3 ; 1 ; +; Addr~2 ; 1 ; +; RAcur[4] ; 1 ; +; always10~2 ; 1 ; +; always10~1 ; 1 ; +; nBODf0 ; 1 ; +; Equal0~1 ; 1 ; +; Equal0~0 ; 1 ; +; LS[4]~33 ; 1 ; +; Equal2~5 ; 1 ; +; LS[2]~31 ; 1 ; +; LS[1]~29 ; 1 ; +; Equal2~3 ; 1 ; +; LS[15]~27 ; 1 ; +; LS[14]~25 ; 1 ; +; LS[16]~21 ; 1 ; +; Equal2~2 ; 1 ; +; LS[13]~19 ; 1 ; +; LS[12]~17 ; 1 ; +; LS[11]~15 ; 1 ; +; LS[10]~13 ; 1 ; +; Equal2~1 ; 1 ; +; LS[9]~11 ; 1 ; +; LS[8]~9 ; 1 ; +; LS[7]~7 ; 1 ; +; LS[5]~5 ; 1 ; +; LS[6]~3 ; 1 ; +; FCK~reg0 ; 1 ; +; DQMH~0 ; 1 ; +; DQML~2 ; 1 ; +; LS[3]~1 ; 1 ; +; nSWE~reg0 ; 1 ; +; nCAS~reg0 ; 1 ; +; nRAS~reg0 ; 1 ; +; nRCS~reg0 ; 1 ; +; SA~23 ; 1 ; +; SA~22 ; 1 ; +; SA~21 ; 1 ; +; SA~20 ; 1 ; +; SA~19 ; 1 ; +; SA~18 ; 1 ; +; SA~17 ; 1 ; +; SA~16 ; 1 ; +; SA~15 ; 1 ; +; RAcur[6] ; 1 ; +; SA~14 ; 1 ; +; SA~13 ; 1 ; +; RAcur[5] ; 1 ; +; SA~12 ; 1 ; +; nBODr0 ; 1 ; +; SA~11 ; 1 ; +; SA~10 ; 1 ; +; SA~9 ; 1 ; +; Bank[1] ; 1 ; +; nBODr ; 1 ; +; SA~8 ; 1 ; +; SA~7 ; 1 ; +; SA~6 ; 1 ; +; Bank[0] ; 1 ; +; WRD[7] ; 1 ; +; SA~5 ; 1 ; +; SA~4 ; 1 ; +; RAcur[11] ; 1 ; +; SA~3 ; 1 ; +; SA~2 ; 1 ; +; SA~1 ; 1 ; +; SA~0 ; 1 ; +; PHI0r0 ; 1 ; +; Equal36~0 ; 1 ; +; SBA~0 ; 1 ; +; nRESr0 ; 1 ; +; comb~1 ; 1 ; +; PHI0r2 ; 1 ; +; comb~0 ; 1 ; ++--------------+------------------+ +-------------------------------------------------------------------------+ @@ -961,14 +896,10 @@ Info (176444): Device migration not selected. If you intend to use device migrat Info (176445): Device EPM570T100C5 is compatible Info (176445): Device EPM570T100I5 is compatible Info (176445): Device EPM570T100A5 is compatible -Critical Warning (169085): No exact pin location assignment(s) for 73 pins of 73 total pins - Info (169086): Pin nIOSEL not assigned to an exact location on the device - Info (169086): Pin nIOSTRB not assigned to an exact location on the device +Critical Warning (169085): No exact pin location assignment(s) for 69 pins of 69 total pins + Info (169086): Pin nRESout not assigned to an exact location on the device Info (169086): Pin RAdir not assigned to an exact location on the device Info (169086): Pin RDdir not assigned to an exact location on the device - Info (169086): Pin DMAout not assigned to an exact location on the device - Info (169086): Pin INTout not assigned to an exact location on the device - Info (169086): Pin nRESout not assigned to an exact location on the device Info (169086): Pin SBA[0] not assigned to an exact location on the device Info (169086): Pin SBA[1] not assigned to an exact location on the device Info (169086): Pin SA[0] not assigned to an exact location on the device @@ -1010,41 +941,39 @@ Critical Warning (169085): No exact pin location assignment(s) for 73 pins of 73 Info (169086): Pin SD[5] not assigned to an exact location on the device Info (169086): Pin SD[6] not assigned to an exact location on the device Info (169086): Pin SD[7] not assigned to an exact location on the device - Info (169086): Pin DMAin not assigned to an exact location on the device - Info (169086): Pin INTin not assigned to an exact location on the device - Info (169086): Pin C25M not assigned to an exact location on the device + Info (169086): Pin PHI0 not assigned to an exact location on the device Info (169086): Pin nWE not assigned to an exact location on the device - Info (169086): Pin RA[8] not assigned to an exact location on the device - Info (169086): Pin RA[9] not assigned to an exact location on the device - Info (169086): Pin RA[10] not assigned to an exact location on the device - Info (169086): Pin RA[11] not assigned to an exact location on the device - Info (169086): Pin RA[14] not assigned to an exact location on the device - Info (169086): Pin RA[15] not assigned to an exact location on the device - Info (169086): Pin RA[12] not assigned to an exact location on the device - Info (169086): Pin RA[13] not assigned to an exact location on the device + Info (169086): Pin nDEVSEL not assigned to an exact location on the device + Info (169086): Pin nIOSTRB not assigned to an exact location on the device + Info (169086): Pin nIOSEL not assigned to an exact location on the device + Info (169086): Pin C25M not assigned to an exact location on the device Info (169086): Pin RA[1] not assigned to an exact location on the device - Info (169086): Pin RA[0] not assigned to an exact location on the device + Info (169086): Pin RA[10] not assigned to an exact location on the device Info (169086): Pin RA[2] not assigned to an exact location on the device + Info (169086): Pin RA[11] not assigned to an exact location on the device Info (169086): Pin RA[3] not assigned to an exact location on the device Info (169086): Pin RA[4] not assigned to an exact location on the device Info (169086): Pin RA[5] not assigned to an exact location on the device Info (169086): Pin RA[6] not assigned to an exact location on the device Info (169086): Pin RA[7] not assigned to an exact location on the device - Info (169086): Pin nDEVSEL not assigned to an exact location on the device - Info (169086): Pin MISO not assigned to an exact location on the device + Info (169086): Pin RA[8] not assigned to an exact location on the device + Info (169086): Pin RA[9] not assigned to an exact location on the device + Info (169086): Pin RA[0] not assigned to an exact location on the device Info (169086): Pin nRES not assigned to an exact location on the device - Info (169086): Pin PHI0 not assigned to an exact location on the device + Info (169086): Pin RA[14] not assigned to an exact location on the device + Info (169086): Pin RA[15] not assigned to an exact location on the device + Info (169086): Pin RA[12] not assigned to an exact location on the device + Info (169086): Pin RA[13] not assigned to an exact location on the device + Info (169086): Pin MISO not assigned to an exact location on the device Info (169086): Pin nBOD not assigned to an exact location on the device Critical Warning (332012): Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. Info (332144): No user constrained base clocks found in the design Info (332128): Timing requirements not specified -- optimizing circuit to achieve the following default global requirements Info (332127): Assuming a default timing requirement -Info (332111): Found 3 clocks +Info (332111): Found 1 clocks Info (332111): Period Clock Name Info (332111): ======== ============ - Info (332111): 1.000 ARCLK Info (332111): 1.000 C25M - Info (332111): 1.000 DRCLK Info (186079): Completed User Assigned Global Signals Promotion Operation Info (186215): Automatically promoted signal "C25M" to use Global clock in PIN 14 Info (186079): Completed Auto Global Promotion Operation @@ -1054,7 +983,7 @@ Info (186468): Started processing fast register assignments Info (186469): Finished processing fast register assignments Info (176235): Finished register packing Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement - Info (176211): Number of I/O pins in group: 72 (unused VREF, 3.3V VCCIO, 26 input, 30 output, 16 bidirectional) + Info (176211): Number of I/O pins in group: 68 (unused VREF, 3.3V VCCIO, 24 input, 28 output, 16 bidirectional) Info (176212): I/O standards used: 3.3-V LVTTL. Info (176215): I/O bank details before I/O pin placement Info (176214): Statistics of I/O banks @@ -1063,7 +992,7 @@ Info (176215): I/O bank details before I/O pin placement Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01 Info (170189): Fitter placement preparation operations beginning Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 -Info (11888): Total time spent on timing analysis during the Fitter is 0.05 seconds. +Info (11888): Total time spent on timing analysis during the Fitter is 0.03 seconds. Info (170216): Fitter cannot place all nodes on current device -- Fitter will automatically make another fitting attempt and tightly pack logic elements Info (176234): Starting register packing Info (186391): Fitter is using Minimize Area packing mode for logic elements with Auto setting for Auto Packed Registers logic option @@ -1073,7 +1002,7 @@ Info (176235): Finished register packing Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00 Info (170189): Fitter placement preparation operations beginning Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 -Info (11888): Total time spent on timing analysis during the Fitter is 0.02 seconds. +Info (11888): Total time spent on timing analysis during the Fitter is 0.00 seconds. Info (170216): Fitter cannot place all nodes on current device -- Fitter will automatically make another fitting attempt and tightly pack logic elements Info (176234): Starting register packing Info (186391): Fitter is using Minimize Area with Chains packing mode for logic elements with Auto setting for Auto Packed Registers logic option @@ -1082,26 +1011,17 @@ Info (186469): Finished processing fast register assignments Info (176235): Finished register packing Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00 Info (170189): Fitter placement preparation operations beginning -Error (170011): Design contains 313 blocks of type logic cell. However, device contains only 240. +Error (170011): Design contains 250 blocks of type logic cell. However, device contains only 240. Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 Info (11888): Total time spent on timing analysis during the Fitter is 0.02 seconds. Error (171000): Can't fit design in device -Warning (169064): Following 8 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results - Info (169065): Pin RD[0] has a permanently disabled output enable - Info (169065): Pin RD[1] has a permanently disabled output enable - Info (169065): Pin RD[2] has a permanently disabled output enable - Info (169065): Pin RD[3] has a permanently disabled output enable - Info (169065): Pin RD[4] has a permanently disabled output enable - Info (169065): Pin RD[5] has a permanently disabled output enable - Info (169065): Pin RD[6] has a permanently disabled output enable - Info (169065): Pin RD[7] has a permanently disabled output enable Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'. Info (144001): Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg -Error: Quartus II 32-bit Fitter was unsuccessful. 2 errors, 5 warnings - Error: Peak virtual memory: 367 megabytes - Error: Processing ended: Fri Mar 19 02:55:57 2021 +Error: Quartus II 32-bit Fitter was unsuccessful. 2 errors, 4 warnings + Error: Peak virtual memory: 359 megabytes + Error: Processing ended: Fri Mar 19 06:44:01 2021 Error: Elapsed time: 00:00:05 - Error: Total CPU time (on all processors): 00:00:06 + Error: Total CPU time (on all processors): 00:00:05 +----------------------------+ diff --git a/cpld/output_files/GR8RAM.fit.summary b/cpld/output_files/GR8RAM.fit.summary index 1603663..78008c2 100755 --- a/cpld/output_files/GR8RAM.fit.summary +++ b/cpld/output_files/GR8RAM.fit.summary @@ -1,11 +1,11 @@ -Fitter Status : Failed - Fri Mar 19 02:55:57 2021 +Fitter Status : Failed - Fri Mar 19 06:44:01 2021 Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition Revision Name : GR8RAM Top-level Entity Name : GR8RAM Family : MAX II Device : EPM240T100C5 Timing Models : Final -Total logic elements : 313 / 240 ( 130 % ) -Total pins : 73 / 80 ( 91 % ) +Total logic elements : 250 / 240 ( 104 % ) +Total pins : 69 / 80 ( 86 % ) Total virtual pins : 0 -UFM blocks : 1 / 1 ( 100 % ) +UFM blocks : 0 / 1 ( 0 % ) diff --git a/cpld/output_files/GR8RAM.flow.rpt b/cpld/output_files/GR8RAM.flow.rpt index b25704e..c3ef97b 100755 --- a/cpld/output_files/GR8RAM.flow.rpt +++ b/cpld/output_files/GR8RAM.flow.rpt @@ -1,5 +1,5 @@ Flow report for GR8RAM -Fri Mar 19 02:55:57 2021 +Fri Mar 19 06:44:01 2021 Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition @@ -40,17 +40,17 @@ applicable agreement for further details. +-----------------------------------------------------------------------------+ ; Flow Summary ; +---------------------------+-------------------------------------------------+ -; Flow Status ; Flow Failed - Fri Mar 19 02:55:57 2021 ; +; Flow Status ; Flow Failed - Fri Mar 19 06:44:01 2021 ; ; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; ; Revision Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ; ; Family ; MAX II ; ; Device ; EPM240T100C5 ; ; Timing Models ; Final ; -; Total logic elements ; 313 / 240 ( 130 % ) ; -; Total pins ; 73 / 80 ( 91 % ) ; +; Total logic elements ; 250 / 240 ( 104 % ) ; +; Total pins ; 69 / 80 ( 86 % ) ; ; Total virtual pins ; 0 ; -; UFM blocks ; 1 / 1 ( 100 % ) ; +; UFM blocks ; 0 / 1 ( 0 % ) ; +---------------------------+-------------------------------------------------+ @@ -59,7 +59,7 @@ applicable agreement for further details. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 03/19/2021 02:55:46 ; +; Start date & time ; 03/19/2021 06:43:51 ; ; Main task ; Compilation ; ; Revision Name ; GR8RAM ; +-------------------+---------------------+ @@ -70,7 +70,7 @@ applicable agreement for further details. +---------------------------------------+--------------------------------+---------------+-------------+------------+ ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; +---------------------------------------+--------------------------------+---------------+-------------+------------+ -; COMPILER_SIGNATURE_ID ; 44085571633675.161613694503328 ; -- ; -- ; -- ; +; COMPILER_SIGNATURE_ID ; 44085571633675.161615063101880 ; -- ; -- ; -- ; ; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ; ; IP_TOOL_NAME ; ALTUFM_NONE ; -- ; -- ; -- ; ; IP_TOOL_VERSION ; 13.0 ; -- ; -- ; -- ; @@ -88,9 +88,9 @@ applicable agreement for further details. +----------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:06 ; 1.0 ; 301 MB ; 00:00:06 ; -; Fitter ; 00:00:05 ; 1.0 ; 367 MB ; 00:00:05 ; -; Total ; 00:00:11 ; -- ; -- ; 00:00:11 ; +; Analysis & Synthesis ; 00:00:05 ; 1.0 ; 301 MB ; 00:00:05 ; +; Fitter ; 00:00:05 ; 1.0 ; 359 MB ; 00:00:04 ; +; Total ; 00:00:10 ; -- ; -- ; 00:00:09 ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ diff --git a/cpld/output_files/GR8RAM.jdi b/cpld/output_files/GR8RAM.jdi index 80d41b2..2e52d7d 100755 --- a/cpld/output_files/GR8RAM.jdi +++ b/cpld/output_files/GR8RAM.jdi @@ -1,6 +1,6 @@ - + diff --git a/cpld/output_files/GR8RAM.map.rpt b/cpld/output_files/GR8RAM.map.rpt index a3a7383..0574e7b 100755 --- a/cpld/output_files/GR8RAM.map.rpt +++ b/cpld/output_files/GR8RAM.map.rpt @@ -1,5 +1,5 @@ Analysis & Synthesis report for GR8RAM -Fri Mar 19 02:55:50 2021 +Fri Mar 19 06:43:55 2021 Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition @@ -13,14 +13,12 @@ Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit 5. Analysis & Synthesis Source Files Read 6. Analysis & Synthesis Resource Usage Summary 7. Analysis & Synthesis Resource Utilization by Entity - 8. Analysis & Synthesis IP Cores Summary - 9. Registers Removed During Synthesis - 10. General Register Statistics - 11. Inverted Register Statistics - 12. Multiplexer Restructuring Statistics (Restructuring Performed) - 13. Port Connectivity Checks: "UFM:UFM_inst" - 14. Analysis & Synthesis Messages - 15. Analysis & Synthesis Suppressed Messages + 8. Registers Removed During Synthesis + 9. General Register Statistics + 10. Inverted Register Statistics + 11. Multiplexer Restructuring Statistics (Restructuring Performed) + 12. Analysis & Synthesis Messages + 13. Analysis & Synthesis Suppressed Messages @@ -46,15 +44,15 @@ applicable agreement for further details. +-------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +-----------------------------+-------------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Fri Mar 19 02:55:50 2021 ; +; Analysis & Synthesis Status ; Successful - Fri Mar 19 06:43:55 2021 ; ; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; ; Revision Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ; ; Family ; MAX II ; -; Total logic elements ; 343 ; -; Total pins ; 73 ; +; Total logic elements ; 281 ; +; Total pins ; 69 ; ; Total virtual pins ; 0 ; -; UFM blocks ; 1 / 1 ( 100 % ) ; +; UFM blocks ; 0 / 1 ( 0 % ) ; +-----------------------------+-------------------------------------------------+ @@ -153,7 +151,6 @@ applicable agreement for further details. +----------------------------------+-----------------+------------------------------+-------------------------------+---------+ ; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; +----------------------------------+-----------------+------------------------------+-------------------------------+---------+ -; UFM.v ; yes ; User Wizard-Generated File ; Z:/Repos/GR8RAM/cpld/UFM.v ; ; ; gr8ram.v ; yes ; Auto-Found Verilog HDL File ; Z:/Repos/GR8RAM/cpld/gr8ram.v ; ; +----------------------------------+-----------------+------------------------------+-------------------------------+---------+ @@ -163,68 +160,54 @@ applicable agreement for further details. +---------------------------------------------+-------+ ; Resource ; Usage ; +---------------------------------------------+-------+ -; Total logic elements ; 343 ; -; -- Combinational with no register ; 220 ; -; -- Register only ; 30 ; -; -- Combinational with a register ; 93 ; +; Total logic elements ; 281 ; +; -- Combinational with no register ; 182 ; +; -- Register only ; 31 ; +; -- Combinational with a register ; 68 ; ; ; ; ; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 198 ; -; -- 3 input functions ; 43 ; -; -- 2 input functions ; 66 ; -; -- 1 input functions ; 5 ; -; -- 0 input functions ; 1 ; +; -- 4 input functions ; 118 ; +; -- 3 input functions ; 54 ; +; -- 2 input functions ; 70 ; +; -- 1 input functions ; 8 ; +; -- 0 input functions ; 0 ; ; ; ; ; Logic elements by mode ; ; -; -- normal mode ; 306 ; -; -- arithmetic mode ; 37 ; +; -- normal mode ; 233 ; +; -- arithmetic mode ; 48 ; ; -- qfbk mode ; 0 ; ; -- register cascade mode ; 0 ; ; -- synchronous clear/load mode ; 28 ; ; -- asynchronous clear/load mode ; 0 ; ; ; ; -; Total registers ; 123 ; -; Total logic cells in carry chains ; 41 ; -; I/O pins ; 73 ; -; UFM blocks ; 1 ; +; Total registers ; 99 ; +; Total logic cells in carry chains ; 51 ; +; I/O pins ; 69 ; ; Maximum fan-out node ; C25M ; -; Maximum fan-out ; 123 ; -; Total fan-out ; 1357 ; -; Average fan-out ; 3.25 ; +; Maximum fan-out ; 99 ; +; Total fan-out ; 1030 ; +; Average fan-out ; 2.94 ; +---------------------------------------------+-------+ -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Resource Utilization by Entity ; -+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+ -; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ; -+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+ -; |GR8RAM ; 343 (343) ; 123 ; 1 ; 73 ; 0 ; 220 (220) ; 30 (30) ; 93 (93) ; 41 (41) ; 0 (0) ; |GR8RAM ; work ; -; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |GR8RAM|UFM:UFM_inst ; work ; -; |UFM_altufm_none_0ep:UFM_altufm_none_0ep_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |GR8RAM|UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component ; work ; -+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+ ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ; ++----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+ +; |GR8RAM ; 281 (281) ; 99 ; 0 ; 69 ; 0 ; 182 (182) ; 31 (31) ; 68 (68) ; 51 (51) ; 0 (0) ; |GR8RAM ; work ; ++----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. -+-------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis IP Cores Summary ; -+--------+--------------+---------+--------------+--------------+----------------------+----------------------------+ -; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ; -+--------+--------------+---------+--------------+--------------+----------------------+----------------------------+ -; Altera ; ALTUFM_NONE ; 13.0 ; N/A ; N/A ; |GR8RAM|UFM:UFM_inst ; Z:/Repos/GR8RAM/cpld/UFM.v ; -+--------+--------------+---------+--------------+--------------+----------------------+----------------------------+ - - -+--------------------------------------------------------------------------------+ -; Registers Removed During Synthesis ; -+---------------------------------------+----------------------------------------+ -; Register name ; Reason for Removal ; -+---------------------------------------+----------------------------------------+ -; DRDIn ; Stuck at GND due to stuck port data_in ; -; nRESout~reg0 ; Merged with CmdActv ; -; RCKE~reg0 ; Stuck at VCC due to stuck port data_in ; -; Total Number of Removed Registers = 3 ; ; -+---------------------------------------+----------------------------------------+ ++--------------------------------------------------------------+ +; Registers Removed During Synthesis ; ++---------------------------------------+----------------------+ +; Register name ; Reason for Removal ; ++---------------------------------------+----------------------+ +; Addr[21,22] ; Merged with Addr[23] ; +; Total Number of Removed Registers = 2 ; ; ++---------------------------------------+----------------------+ +------------------------------------------------------+ @@ -232,12 +215,12 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +----------------------------------------------+-------+ ; Statistic ; Value ; +----------------------------------------------+-------+ -; Total registers ; 123 ; -; Number of registers using Synchronous Clear ; 24 ; -; Number of registers using Synchronous Load ; 4 ; +; Total registers ; 99 ; +; Number of registers using Synchronous Clear ; 25 ; +; Number of registers using Synchronous Load ; 3 ; ; Number of registers using Asynchronous Clear ; 0 ; ; Number of registers using Asynchronous Load ; 0 ; -; Number of registers using Clock Enable ; 69 ; +; Number of registers using Clock Enable ; 43 ; ; Number of registers using Preset ; 0 ; +----------------------------------------------+-------+ @@ -247,13 +230,12 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +----------------------------------------+---------+ ; Inverted Register ; Fan out ; +----------------------------------------+---------+ -; nRCS~reg0 ; 3 ; -; nRAS~reg0 ; 3 ; -; nCAS~reg0 ; 3 ; -; nSWE~reg0 ; 3 ; -; DQML~reg0 ; 1 ; -; DQMH~reg0 ; 1 ; -; Total number of inverted registers = 6 ; ; +; nRCS~reg0 ; 1 ; +; nRAS~reg0 ; 1 ; +; nCAS~reg0 ; 1 ; +; nSWE~reg0 ; 1 ; +; RCKE~reg0 ; 2 ; +; Total number of inverted registers = 5 ; ; +----------------------------------------+---------+ @@ -262,87 +244,64 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ ; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ -; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |GR8RAM|S[3] ; -; 4:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |GR8RAM|Addr[2] ; -; 5:1 ; 4 bits ; 12 LEs ; 8 LEs ; 4 LEs ; Yes ; |GR8RAM|Addr[18] ; -; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; Yes ; |GR8RAM|IS[1] ; -; 5:1 ; 8 bits ; 24 LEs ; 16 LEs ; 8 LEs ; Yes ; |GR8RAM|Addr[8] ; -; 5:1 ; 3 bits ; 9 LEs ; 6 LEs ; 3 LEs ; Yes ; |GR8RAM|DRShift ; -; 6:1 ; 4 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |GR8RAM|Addr[23] ; -; 13:1 ; 2 bits ; 16 LEs ; 4 LEs ; 12 LEs ; Yes ; |GR8RAM|SA[12]~reg0 ; -; 17:1 ; 5 bits ; 55 LEs ; 30 LEs ; 25 LEs ; Yes ; |GR8RAM|SA[7]~reg0 ; -; 20:1 ; 3 bits ; 39 LEs ; 18 LEs ; 21 LEs ; Yes ; |GR8RAM|SA[2]~reg0 ; -; 20:1 ; 2 bits ; 26 LEs ; 8 LEs ; 18 LEs ; Yes ; |GR8RAM|DQMH~reg0 ; +; 3:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; Yes ; |GR8RAM|PS[0] ; +; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |GR8RAM|Bank[0] ; +; 5:1 ; 8 bits ; 24 LEs ; 16 LEs ; 8 LEs ; Yes ; |GR8RAM|Addr[4] ; +; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; Yes ; |GR8RAM|IS[0] ; +; 7:1 ; 8 bits ; 32 LEs ; 16 LEs ; 16 LEs ; Yes ; |GR8RAM|Addr[14] ; +; 9:1 ; 4 bits ; 24 LEs ; 12 LEs ; 12 LEs ; Yes ; |GR8RAM|Addr[17] ; +; 8:1 ; 2 bits ; 10 LEs ; 6 LEs ; 4 LEs ; No ; |GR8RAM|SA ; +; 8:1 ; 5 bits ; 25 LEs ; 15 LEs ; 10 LEs ; No ; |GR8RAM|SA ; +; 8:1 ; 4 bits ; 20 LEs ; 12 LEs ; 8 LEs ; No ; |GR8RAM|SA ; +; 8:1 ; 2 bits ; 10 LEs ; 6 LEs ; 4 LEs ; No ; |GR8RAM|DQMH ; +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ -+-------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "UFM:UFM_inst" ; -+---------+--------+----------+-------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+---------+--------+----------+-------------------------------------------------------------------------------------+ -; ardin ; Input ; Info ; Stuck at GND ; -; oscena ; Input ; Info ; Stuck at VCC ; -; busy ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; osc ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; rtpbusy ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -+---------+--------+----------+-------------------------------------------------------------------------------------+ - - +-------------------------------+ ; Analysis & Synthesis Messages ; +-------------------------------+ Info: ******************************************************************* Info: Running Quartus II 32-bit Analysis & Synthesis Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - Info: Processing started: Fri Mar 19 02:55:44 2021 + Info: Processing started: Fri Mar 19 06:43:50 2021 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected Info (12021): Found 2 design units, including 2 entities, in source file ufm.v Info (12023): Found entity 1: UFM_altufm_none_0ep Info (12023): Found entity 2: UFM -Warning (10229): Verilog HDL Expression warning at gr8ram.v(545): truncated literal to match 1 bits -Warning (10229): Verilog HDL Expression warning at gr8ram.v(558): truncated literal to match 1 bits Warning (12125): Using design file gr8ram.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info (12023): Found entity 1: GR8RAM -Warning (10236): Verilog HDL Implicit Net warning at gr8ram.v(275): created implicit net for "UFMB" -Warning (10236): Verilog HDL Implicit Net warning at gr8ram.v(278): created implicit net for "RTPB" Info (12127): Elaborating entity "GR8RAM" for the top level hierarchy -Warning (10036): Verilog HDL or VHDL warning at gr8ram.v(112): object "REGEN" assigned a value but never read -Warning (10858): Verilog HDL warning at gr8ram.v(127): object RDout used but never assigned -Warning (10036): Verilog HDL or VHDL warning at gr8ram.v(280): object "UFMBr" assigned a value but never read -Warning (10036): Verilog HDL or VHDL warning at gr8ram.v(282): object "RTPBr" assigned a value but never read -Warning (10230): Verilog HDL assignment warning at gr8ram.v(39): truncated value with size 32 to match size of target (18) -Warning (10230): Verilog HDL assignment warning at gr8ram.v(147): truncated value with size 32 to match size of target (8) -Warning (10230): Verilog HDL assignment warning at gr8ram.v(154): truncated value with size 32 to match size of target (8) -Warning (10230): Verilog HDL assignment warning at gr8ram.v(160): truncated value with size 32 to match size of target (8) -Warning (10230): Verilog HDL assignment warning at gr8ram.v(426): truncated value with size 32 to match size of target (4) -Warning (10230): Verilog HDL assignment warning at gr8ram.v(547): truncated value with size 10 to match size of target (6) -Warning (10230): Verilog HDL assignment warning at gr8ram.v(635): truncated value with size 10 to match size of target (6) -Warning (10030): Net "RDout" at gr8ram.v(127) has no driver or initial value, using a default initial value '0' -Info (12128): Elaborating entity "UFM" for hierarchy "UFM:UFM_inst" -Info (12128): Elaborating entity "UFM_altufm_none_0ep" for hierarchy "UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component" +Warning (10858): Verilog HDL warning at gr8ram.v(110): object RDout used but never assigned +Warning (10858): Verilog HDL warning at gr8ram.v(230): object SetFW used but never assigned +Warning (10036): Verilog HDL or VHDL warning at gr8ram.v(263): object "RefReady" assigned a value but never read +Warning (10230): Verilog HDL assignment warning at gr8ram.v(34): truncated value with size 32 to match size of target (18) +Warning (10230): Verilog HDL assignment warning at gr8ram.v(125): truncated value with size 32 to match size of target (24) +Warning (10230): Verilog HDL assignment warning at gr8ram.v(126): truncated value with size 36 to match size of target (24) +Warning (10230): Verilog HDL assignment warning at gr8ram.v(130): truncated value with size 32 to match size of target (16) +Warning (10230): Verilog HDL assignment warning at gr8ram.v(131): truncated value with size 36 to match size of target (16) +Warning (10230): Verilog HDL assignment warning at gr8ram.v(136): truncated value with size 32 to match size of target (8) +Warning (10230): Verilog HDL assignment warning at gr8ram.v(137): truncated value with size 36 to match size of target (8) +Warning (10230): Verilog HDL assignment warning at gr8ram.v(195): truncated value with size 2 to match size of target (1) +Warning (10230): Verilog HDL assignment warning at gr8ram.v(249): truncated value with size 32 to match size of target (3) +Warning (10030): Net "RDout" at gr8ram.v(110) has no driver or initial value, using a default initial value '0' +Warning (10030): Net "SetFW" at gr8ram.v(230) has no driver or initial value, using a default initial value '0' +Warning (10030): Net "WRD[5..0]" at gr8ram.v(234) has no driver or initial value, using a default initial value '0' Warning (13046): Tri-state node(s) do not directly drive top-level pin(s) - Warning (13047): Converted the fan-out from the tri-state buffer "MOSI" to the node "WRD" into an OR gate + Warning (13047): Converted the fan-out from the tri-state buffer "MOSI" to the node "WRD[6]" into an OR gate Warning (13024): Output pins are stuck at VCC or GND Warning (13410): Pin "RAdir" is stuck at VCC - Warning (13410): Pin "RDdir" is stuck at VCC - Warning (13410): Pin "RCKE" is stuck at VCC -Warning (21074): Design contains 2 input pin(s) that do not drive logic - Warning (15610): No output dependent on input pin "nIOSEL" - Warning (15610): No output dependent on input pin "nIOSTRB" -Info (21057): Implemented 417 device resources after synthesis - the final resource count might be different - Info (21058): Implemented 27 input pins - Info (21059): Implemented 30 output pins +Info (21057): Implemented 350 device resources after synthesis - the final resource count might be different + Info (21058): Implemented 25 input pins + Info (21059): Implemented 28 output pins Info (21060): Implemented 16 bidirectional pins - Info (21061): Implemented 343 logic cells - Info (21070): Implemented 1 User Flash Memory blocks + Info (21061): Implemented 281 logic cells Info (144001): Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg -Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 26 warnings +Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 20 warnings Info: Peak virtual memory: 301 megabytes - Info: Processing ended: Fri Mar 19 02:55:50 2021 - Info: Elapsed time: 00:00:06 - Info: Total CPU time (on all processors): 00:00:06 + Info: Processing ended: Fri Mar 19 06:43:55 2021 + Info: Elapsed time: 00:00:05 + Info: Total CPU time (on all processors): 00:00:05 +------------------------------------------+ diff --git a/cpld/output_files/GR8RAM.map.smsg b/cpld/output_files/GR8RAM.map.smsg index 754d645..63e7356 100755 --- a/cpld/output_files/GR8RAM.map.smsg +++ b/cpld/output_files/GR8RAM.map.smsg @@ -1,4 +1,4 @@ Warning (10463): Verilog HDL Declaration warning at UFM.v(72): "program" is SystemVerilog-2005 keyword Warning (10463): Verilog HDL Declaration warning at UFM.v(188): "program" is SystemVerilog-2005 keyword -Warning (10273): Verilog HDL warning at gr8ram.v(126): extended using "x" or "z" -Warning (10273): Verilog HDL warning at gr8ram.v(410): extended using "x" or "z" +Warning (10273): Verilog HDL warning at gr8ram.v(109): extended using "x" or "z" +Warning (10273): Verilog HDL warning at gr8ram.v(233): extended using "x" or "z" diff --git a/cpld/output_files/GR8RAM.map.summary b/cpld/output_files/GR8RAM.map.summary index b0021ee..d4bb560 100755 --- a/cpld/output_files/GR8RAM.map.summary +++ b/cpld/output_files/GR8RAM.map.summary @@ -1,9 +1,9 @@ -Analysis & Synthesis Status : Successful - Fri Mar 19 02:55:50 2021 +Analysis & Synthesis Status : Successful - Fri Mar 19 06:43:55 2021 Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition Revision Name : GR8RAM Top-level Entity Name : GR8RAM Family : MAX II -Total logic elements : 343 -Total pins : 73 +Total logic elements : 281 +Total pins : 69 Total virtual pins : 0 -UFM blocks : 1 / 1 ( 100 % ) +UFM blocks : 0 / 1 ( 0 % ) diff --git a/cpld/output_files/GR8RAM.pof b/cpld/output_files/GR8RAM.pof index d235b31..8b0bc60 100755 Binary files a/cpld/output_files/GR8RAM.pof and b/cpld/output_files/GR8RAM.pof differ diff --git a/cpld/output_files/GR8RAM.sta.rpt b/cpld/output_files/GR8RAM.sta.rpt index 99c0812..58b5fbf 100755 --- a/cpld/output_files/GR8RAM.sta.rpt +++ b/cpld/output_files/GR8RAM.sta.rpt @@ -1,5 +1,5 @@ TimeQuest Timing Analyzer report for GR8RAM -Thu Mar 18 04:40:58 2021 +Fri Mar 19 05:29:00 2021 Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition @@ -19,8 +19,8 @@ Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit 11. Setup: 'ARCLK' 12. Setup: 'DRCLK' 13. Setup: 'C25M' - 14. Hold: 'DRCLK' - 15. Hold: 'ARCLK' + 14. Hold: 'ARCLK' + 15. Hold: 'DRCLK' 16. Hold: 'C25M' 17. Minimum Pulse Width: 'ARCLK' 18. Minimum Pulse Width: 'DRCLK' @@ -104,15 +104,15 @@ applicable agreement for further details. +------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+ -+--------------------------------------------------+ -; Fmax Summary ; -+------------+-----------------+------------+------+ -; Fmax ; Restricted Fmax ; Clock Name ; Note ; -+------------+-----------------+------------+------+ -; 10.0 MHz ; 10.0 MHz ; ARCLK ; ; -; 10.0 MHz ; 10.0 MHz ; DRCLK ; ; -; 105.85 MHz ; 105.85 MHz ; C25M ; ; -+------------+-----------------+------------+------+ ++-------------------------------------------------+ +; Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 10.0 MHz ; 10.0 MHz ; ARCLK ; ; +; 10.0 MHz ; 10.0 MHz ; DRCLK ; ; +; 94.36 MHz ; 94.36 MHz ; C25M ; ; ++-----------+-----------------+------------+------+ This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. @@ -123,7 +123,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+---------+---------------+ ; ARCLK ; -99.000 ; -99.000 ; ; DRCLK ; -99.000 ; -99.000 ; -; C25M ; -8.447 ; -415.877 ; +; C25M ; -9.598 ; -485.527 ; +-------+---------+---------------+ @@ -132,9 +132,9 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+---------+---------------+ ; Clock ; Slack ; End Point TNS ; +-------+---------+---------------+ -; DRCLK ; -16.286 ; -16.286 ; -; ARCLK ; -16.276 ; -16.276 ; -; C25M ; -1.579 ; -1.579 ; +; ARCLK ; -16.296 ; -16.296 ; +; DRCLK ; -16.276 ; -16.276 ; +; C25M ; -1.031 ; -1.031 ; +-------+---------+---------------+ @@ -167,7 +167,7 @@ No paths to report. ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ; -99.000 ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK ; ARCLK ; 1.000 ; 0.000 ; 80.000 ; -; -22.724 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C25M ; ARCLK ; 1.000 ; -2.195 ; 1.529 ; +; -22.704 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C25M ; ARCLK ; 1.000 ; -2.175 ; 1.529 ; +---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ @@ -177,7 +177,7 @@ No paths to report. ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ; -99.000 ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|wire_maxii_ufm_block1_drdout ; DRCLK ; DRCLK ; 1.000 ; 0.000 ; 80.000 ; -; -22.714 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|wire_maxii_ufm_block1_drdout ; C25M ; DRCLK ; 1.000 ; -2.165 ; 1.549 ; +; -22.724 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|wire_maxii_ufm_block1_drdout ; C25M ; DRCLK ; 1.000 ; -2.195 ; 1.529 ; +---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ @@ -186,234 +186,234 @@ No paths to report. +--------+-----------+--------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+-----------+--------------+--------------+-------------+--------------+------------+------------+ -; -8.447 ; LS[6] ; LS[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.114 ; -; -8.446 ; LS[6] ; LS[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.113 ; -; -8.308 ; LS[8] ; LS[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.975 ; -; -8.237 ; LS[8] ; LS[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.904 ; -; -8.142 ; LS[8] ; LS[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.809 ; -; -8.013 ; LS[8] ; LS[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.680 ; -; -7.999 ; LS[0] ; LS[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.666 ; -; -7.991 ; LS[8] ; LS[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.658 ; -; -7.988 ; LS[6] ; nBODf0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.655 ; -; -7.986 ; LS[8] ; LS[15] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.653 ; -; -7.968 ; LS[12] ; LS[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.635 ; -; -7.952 ; LS[10] ; LS[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.619 ; -; -7.928 ; LS[0] ; LS[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.595 ; -; -7.902 ; LS[5] ; LS[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.569 ; -; -7.901 ; LS[5] ; LS[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.568 ; -; -7.897 ; LS[12] ; LS[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.564 ; -; -7.883 ; LS[3] ; LS[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.550 ; -; -7.881 ; LS[10] ; LS[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.548 ; -; -7.870 ; LS[22] ; InitActv ; C25M ; C25M ; 1.000 ; 0.000 ; 8.537 ; -; -7.847 ; LS[6] ; LS[20] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.514 ; -; -7.846 ; LS[6] ; LS[14] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.513 ; -; -7.846 ; LS[6] ; LS[22] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.513 ; -; -7.844 ; LS[6] ; LS[9] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.511 ; -; -7.842 ; LS[6] ; LS[10] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.509 ; -; -7.841 ; LS[22] ; nRESout~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.508 ; -; -7.838 ; LS[22] ; SDRAMActv ; C25M ; C25M ; 1.000 ; 0.000 ; 8.505 ; -; -7.835 ; LS[4] ; MOSIout ; C25M ; C25M ; 1.000 ; 0.000 ; 8.502 ; -; -7.833 ; LS[0] ; LS[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.500 ; -; -7.832 ; LS[7] ; LS[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.499 ; -; -7.829 ; LS[6] ; LS[11] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.496 ; -; -7.825 ; LS[8] ; LS[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.492 ; -; -7.812 ; LS[3] ; LS[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.479 ; -; -7.786 ; LS[10] ; LS[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.453 ; -; -7.778 ; LS[11] ; LS[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.445 ; -; -7.765 ; LS[6] ; nBODf ; C25M ; C25M ; 1.000 ; 0.000 ; 8.432 ; -; -7.761 ; LS[7] ; LS[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.428 ; -; -7.755 ; LS[10] ; InitActv ; C25M ; C25M ; 1.000 ; 0.000 ; 8.422 ; -; -7.735 ; LS[6] ; LS[4] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.402 ; -; -7.717 ; LS[3] ; LS[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.384 ; -; -7.709 ; LS[0] ; LS[10] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.376 ; -; -7.707 ; LS[11] ; LS[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.374 ; -; -7.704 ; LS[0] ; LS[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.371 ; -; -7.685 ; LS[20] ; InitActv ; C25M ; C25M ; 1.000 ; 0.000 ; 8.352 ; -; -7.682 ; LS[0] ; LS[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.349 ; -; -7.677 ; LS[0] ; LS[15] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.344 ; -; -7.673 ; LS[12] ; LS[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.340 ; -; -7.666 ; LS[7] ; LS[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.333 ; -; -7.657 ; LS[10] ; LS[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.324 ; -; -7.656 ; LS[20] ; nRESout~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.323 ; -; -7.656 ; LS[10] ; nRESout~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.323 ; -; -7.655 ; LS[5] ; LS[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.322 ; -; -7.653 ; LS[20] ; SDRAMActv ; C25M ; C25M ; 1.000 ; 0.000 ; 8.320 ; -; -7.653 ; LS[10] ; SDRAMActv ; C25M ; C25M ; 1.000 ; 0.000 ; 8.320 ; -; -7.651 ; LS[12] ; LS[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.318 ; -; -7.638 ; LS[6] ; LS[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.305 ; -; -7.635 ; LS[10] ; LS[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.302 ; -; -7.630 ; LS[10] ; LS[15] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.297 ; -; -7.620 ; LS[0] ; LS[3] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.287 ; -; -7.611 ; LS[6] ; nFCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.278 ; -; -7.600 ; LS[8] ; LS[14] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.267 ; -; -7.593 ; LS[3] ; LS[10] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.260 ; -; -7.589 ; LS[17] ; InitActv ; C25M ; C25M ; 1.000 ; 0.000 ; 8.256 ; -; -7.588 ; LS[3] ; LS[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.255 ; -; -7.584 ; LS[5] ; LS[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.251 ; -; -7.584 ; LS[8] ; LS[10] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.251 ; -; -7.566 ; LS[3] ; LS[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.233 ; -; -7.565 ; LS[2] ; nRESout~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.232 ; -; -7.562 ; LS[2] ; SDRAMActv ; C25M ; C25M ; 1.000 ; 0.000 ; 8.229 ; -; -7.561 ; LS[3] ; LS[15] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.228 ; -; -7.541 ; LS[2] ; LS[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.208 ; -; -7.540 ; LS[2] ; LS[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.207 ; -; -7.537 ; LS[7] ; LS[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.204 ; -; -7.529 ; LS[19] ; InitActv ; C25M ; C25M ; 1.000 ; 0.000 ; 8.196 ; -; -7.528 ; LS[10] ; nFCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.195 ; -; -7.517 ; LS[0] ; LS[7] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.184 ; -; -7.516 ; LS[0] ; LS[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.183 ; -; -7.515 ; LS[7] ; LS[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.182 ; -; -7.510 ; LS[7] ; LS[15] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.177 ; -; -7.489 ; LS[5] ; LS[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.156 ; -; -7.485 ; LS[12] ; LS[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.152 ; -; -7.483 ; LS[11] ; LS[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.150 ; -; -7.474 ; LS[11] ; InitActv ; C25M ; C25M ; 1.000 ; 0.000 ; 8.141 ; -; -7.469 ; LS[10] ; LS[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.136 ; -; -7.461 ; LS[11] ; LS[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.128 ; -; -7.454 ; LS[13] ; LS[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.121 ; -; -7.451 ; LS[14] ; LS[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.118 ; -; -7.443 ; LS[5] ; nBODf0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.110 ; -; -7.436 ; LS[12] ; LS[15] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.103 ; -; -7.401 ; LS[3] ; LS[7] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.068 ; -; -7.400 ; LS[3] ; LS[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.067 ; -; -7.394 ; LS[17] ; nRESout~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.061 ; -; -7.385 ; LS[11] ; nRESout~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.052 ; -; -7.383 ; LS[13] ; LS[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.050 ; -; -7.382 ; LS[11] ; SDRAMActv ; C25M ; C25M ; 1.000 ; 0.000 ; 8.049 ; -; -7.380 ; LS[14] ; LS[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.047 ; -; -7.367 ; LS[16] ; InitActv ; C25M ; C25M ; 1.000 ; 0.000 ; 8.034 ; -; -7.365 ; LS[5] ; LS[10] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.032 ; -; -7.363 ; LS[16] ; LS[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.030 ; -; -7.360 ; LS[5] ; LS[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.027 ; -; -7.349 ; LS[7] ; LS[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.016 ; +; -9.598 ; RAcur[8] ; nRCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 10.265 ; +; -9.515 ; RAcur[8] ; RCKE~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 10.182 ; +; -9.377 ; RAcur[10] ; nRCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 10.044 ; +; -9.338 ; RAcur[8] ; nRAS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 10.005 ; +; -9.294 ; RAcur[10] ; RCKE~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.961 ; +; -9.232 ; RACr ; nRCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.899 ; +; -9.149 ; RACr ; RCKE~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.816 ; +; -9.117 ; RAcur[10] ; nRAS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.784 ; +; -9.117 ; RAcur[1] ; nRCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.784 ; +; -9.095 ; RAcur[9] ; nRCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.762 ; +; -9.034 ; RAcur[1] ; RCKE~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.701 ; +; -9.012 ; RAcur[9] ; RCKE~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.679 ; +; -8.972 ; RACr ; nRAS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.639 ; +; -8.879 ; LS[10] ; MOSIout ; C25M ; C25M ; 1.000 ; 0.000 ; 9.546 ; +; -8.857 ; RAcur[1] ; nRAS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.524 ; +; -8.835 ; RAcur[9] ; nRAS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.502 ; +; -8.807 ; LS[15] ; MOSIout ; C25M ; C25M ; 1.000 ; 0.000 ; 9.474 ; +; -8.710 ; LS[11] ; MOSIout ; C25M ; C25M ; 1.000 ; 0.000 ; 9.377 ; +; -8.657 ; LS[13] ; MOSIout ; C25M ; C25M ; 1.000 ; 0.000 ; 9.324 ; +; -8.578 ; RAcur[0] ; nRCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.245 ; +; -8.564 ; LS[9] ; MOSIout ; C25M ; C25M ; 1.000 ; 0.000 ; 9.231 ; +; -8.497 ; LS[12] ; MOSIout ; C25M ; C25M ; 1.000 ; 0.000 ; 9.164 ; +; -8.495 ; RAcur[0] ; RCKE~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.162 ; +; -8.486 ; LS[2] ; nRAS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.153 ; +; -8.462 ; LS[3] ; MOSIout ; C25M ; C25M ; 1.000 ; 0.000 ; 9.129 ; +; -8.318 ; RAcur[0] ; nRAS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.985 ; +; -8.310 ; LS[17] ; FCKEN ; C25M ; C25M ; 1.000 ; 0.000 ; 8.977 ; +; -8.276 ; RAcur[8] ; nCAS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.943 ; +; -8.260 ; InitActv ; nRCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.927 ; +; -8.200 ; LS[1] ; nRAS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.867 ; +; -8.195 ; PS[1] ; nRCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.862 ; +; -8.178 ; LS[10] ; IS[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.845 ; +; -8.174 ; LS[10] ; IS[1] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.841 ; +; -8.171 ; RAcur[11] ; nRCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.838 ; +; -8.166 ; LS[10] ; FCKEN ; C25M ; C25M ; 1.000 ; 0.000 ; 8.833 ; +; -8.124 ; LS[14] ; MOSIout ; C25M ; C25M ; 1.000 ; 0.000 ; 8.791 ; +; -8.106 ; LS[15] ; IS[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.773 ; +; -8.102 ; LS[15] ; IS[1] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.769 ; +; -8.088 ; RAcur[11] ; RCKE~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.755 ; +; -8.055 ; RAcur[10] ; nCAS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.722 ; +; -8.054 ; LS[2] ; MOSIout ; C25M ; C25M ; 1.000 ; 0.000 ; 8.721 ; +; -8.027 ; RAcur[7] ; nRCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.694 ; +; -8.009 ; LS[11] ; IS[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.676 ; +; -8.005 ; LS[11] ; IS[1] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.672 ; +; -7.996 ; LS[0] ; FCS ; C25M ; C25M ; 1.000 ; 0.000 ; 8.663 ; +; -7.980 ; LS[0] ; FCKEN ; C25M ; C25M ; 1.000 ; 0.000 ; 8.647 ; +; -7.973 ; LS[16] ; FCKEN ; C25M ; C25M ; 1.000 ; 0.000 ; 8.640 ; +; -7.956 ; LS[13] ; IS[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.623 ; +; -7.952 ; LS[13] ; IS[1] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.619 ; +; -7.950 ; LS[10] ; FCS ; C25M ; C25M ; 1.000 ; 0.000 ; 8.617 ; +; -7.944 ; RAcur[7] ; RCKE~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.611 ; +; -7.942 ; IS[0] ; nRCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.609 ; +; -7.933 ; LS[10] ; ARCLK ; C25M ; C25M ; 1.000 ; 0.000 ; 8.600 ; +; -7.911 ; RAcur[11] ; nRAS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.578 ; +; -7.910 ; RACr ; nCAS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.577 ; +; -7.905 ; LS[15] ; FCKEN ; C25M ; C25M ; 1.000 ; 0.000 ; 8.572 ; +; -7.889 ; RAcur[2] ; nRCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.556 ; +; -7.878 ; LS[15] ; FCS ; C25M ; C25M ; 1.000 ; 0.000 ; 8.545 ; +; -7.863 ; LS[9] ; IS[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.530 ; +; -7.859 ; LS[9] ; IS[1] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.526 ; +; -7.842 ; nWEcur ; RCKE~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.509 ; +; -7.817 ; LS[5] ; FCKEN ; C25M ; C25M ; 1.000 ; 0.000 ; 8.484 ; +; -7.813 ; PS[3] ; RCKE~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.480 ; +; -7.812 ; LS[8] ; MOSIout ; C25M ; C25M ; 1.000 ; 0.000 ; 8.479 ; +; -7.808 ; LS[11] ; FCKEN ; C25M ; C25M ; 1.000 ; 0.000 ; 8.475 ; +; -7.806 ; RAcur[2] ; RCKE~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.473 ; +; -7.800 ; LS[2] ; nRCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.467 ; +; -7.796 ; LS[12] ; IS[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.463 ; +; -7.795 ; LS[17] ; MOSIout ; C25M ; C25M ; 1.000 ; 0.000 ; 8.462 ; +; -7.795 ; RAcur[1] ; nCAS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.462 ; +; -7.792 ; LS[12] ; IS[1] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.459 ; +; -7.786 ; PHI0r2 ; nRCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.453 ; +; -7.781 ; LS[11] ; FCS ; C25M ; C25M ; 1.000 ; 0.000 ; 8.448 ; +; -7.773 ; RAcur[9] ; nCAS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.440 ; +; -7.767 ; RAcur[7] ; nRAS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.434 ; +; -7.765 ; LS[4] ; MOSIout ; C25M ; C25M ; 1.000 ; 0.000 ; 8.432 ; +; -7.764 ; LS[11] ; ARCLK ; C25M ; C25M ; 1.000 ; 0.000 ; 8.431 ; +; -7.755 ; LS[13] ; FCKEN ; C25M ; C25M ; 1.000 ; 0.000 ; 8.422 ; +; -7.736 ; LS[17] ; nRESout~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.403 ; +; -7.728 ; LS[13] ; FCS ; C25M ; C25M ; 1.000 ; 0.000 ; 8.395 ; +; -7.704 ; PS[3] ; IOROMEN ; C25M ; C25M ; 1.000 ; 0.000 ; 8.371 ; +; -7.704 ; LS[9] ; FCKEN ; C25M ; C25M ; 1.000 ; 0.000 ; 8.371 ; +; -7.698 ; PS[3] ; REGEN ; C25M ; C25M ; 1.000 ; 0.000 ; 8.365 ; +; -7.691 ; LS[6] ; MOSIout ; C25M ; C25M ; 1.000 ; 0.000 ; 8.358 ; +; -7.677 ; InitActv ; nRAS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.344 ; +; -7.672 ; LS[2] ; FCS ; C25M ; C25M ; 1.000 ; 0.000 ; 8.339 ; +; -7.662 ; PS[2] ; nRCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.329 ; +; -7.656 ; LS[2] ; FCKEN ; C25M ; C25M ; 1.000 ; 0.000 ; 8.323 ; +; -7.635 ; LS[9] ; FCS ; C25M ; C25M ; 1.000 ; 0.000 ; 8.302 ; +; -7.631 ; LS[10] ; SetFW[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.298 ; +; -7.631 ; LS[10] ; SetFW[1] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.298 ; +; -7.629 ; RAcur[2] ; nRAS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.296 ; +; -7.629 ; PHI0r1 ; nRCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.296 ; +; -7.622 ; LS[0] ; MOSIOE ; C25M ; C25M ; 1.000 ; 0.000 ; 8.289 ; +; -7.618 ; LS[9] ; ARCLK ; C25M ; C25M ; 1.000 ; 0.000 ; 8.285 ; +; -7.612 ; PS[1] ; nRAS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.279 ; +; -7.612 ; LS[10] ; MOSIOE ; C25M ; C25M ; 1.000 ; 0.000 ; 8.279 ; +; -7.608 ; LS[0] ; nBODf ; C25M ; C25M ; 1.000 ; 0.000 ; 8.275 ; +; -7.595 ; LS[12] ; FCKEN ; C25M ; C25M ; 1.000 ; 0.000 ; 8.262 ; +; -7.592 ; LS[10] ; nRESout~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.259 ; +--------+-----------+--------------+--------------+-------------+--------------+------------+------------+ -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Hold: 'DRCLK' ; -+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -; -16.286 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|wire_maxii_ufm_block1_drdout ; C25M ; DRCLK ; 0.000 ; -2.165 ; 1.549 ; -; 60.000 ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|wire_maxii_ufm_block1_drdout ; DRCLK ; DRCLK ; 0.000 ; 0.000 ; 80.000 ; -+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ - - +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Hold: 'ARCLK' ; +---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -; -16.276 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C25M ; ARCLK ; 0.000 ; -2.195 ; 1.529 ; +; -16.296 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C25M ; ARCLK ; 0.000 ; -2.175 ; 1.529 ; ; 60.000 ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK ; ARCLK ; 0.000 ; 0.000 ; 80.000 ; +---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Hold: 'DRCLK' ; ++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; -16.276 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|wire_maxii_ufm_block1_drdout ; C25M ; DRCLK ; 0.000 ; -2.195 ; 1.529 ; +; 60.000 ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|wire_maxii_ufm_block1_drdout ; DRCLK ; DRCLK ; 0.000 ; 0.000 ; 80.000 ; ++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + +------------------------------------------------------------------------------------------------------------+ ; Hold: 'C25M' ; +--------+--------------+--------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+--------------+--------------+--------------+-------------+--------------+------------+------------+ -; -1.579 ; ARCLK ; ARCLK ; ARCLK ; C25M ; 0.000 ; 3.348 ; 2.366 ; -; -1.079 ; ARCLK ; ARCLK ; ARCLK ; C25M ; -0.500 ; 3.348 ; 2.366 ; -; 1.374 ; nBODr0 ; nBODr ; C25M ; C25M ; 0.000 ; 0.000 ; 1.595 ; -; 1.382 ; nRESr0 ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 1.603 ; -; 1.677 ; SDRAMActv ; SDRAMActv ; C25M ; C25M ; 0.000 ; 0.000 ; 1.898 ; -; 1.739 ; S[2] ; S[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.960 ; -; 1.879 ; PHI0r0 ; PHI0r1 ; C25M ; C25M ; -0.500 ; 0.000 ; 1.600 ; -; 1.907 ; UFMD[14] ; UFMD[14] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.128 ; -; 1.908 ; UFMD[13] ; UFMD[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.129 ; -; 2.005 ; S[1] ; S[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.226 ; -; 2.014 ; S[1] ; S[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.235 ; -; 2.127 ; InitIntr ; InitIntr ; C25M ; C25M ; 0.000 ; 0.000 ; 2.348 ; -; 2.160 ; PHI0r2 ; S[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.381 ; -; 2.165 ; PHI0r2 ; S[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.386 ; -; 2.213 ; nFCS~reg0 ; nFCS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.434 ; -; 2.285 ; SetLoaded ; SetLoaded ; C25M ; C25M ; 0.000 ; 0.000 ; 2.506 ; -; 2.288 ; DEVSELr0 ; DEVSELr ; C25M ; C25M ; -0.500 ; 0.000 ; 2.009 ; -; 2.290 ; SetLoaded ; ARShift ; C25M ; C25M ; 0.000 ; 0.000 ; 2.511 ; -; 2.292 ; SetLoaded ; DRShift ; C25M ; C25M ; 0.000 ; 0.000 ; 2.513 ; -; 2.299 ; MOSIOE ; WRD[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.520 ; -; 2.328 ; PHI0r1 ; PHI0r2 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.549 ; -; 2.380 ; S[0] ; S[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.601 ; -; 2.383 ; nWEcur ; SDOE ; C25M ; C25M ; 0.000 ; 0.000 ; 2.604 ; -; 2.383 ; S[0] ; S[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.604 ; -; 2.387 ; S[0] ; S[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.608 ; -; 2.397 ; S[0] ; SDOE ; C25M ; C25M ; 0.000 ; 0.000 ; 2.618 ; -; 2.523 ; DEVSELr ; RAMSEL ; C25M ; C25M ; 0.000 ; 0.000 ; 2.744 ; -; 2.768 ; PHI0r2 ; nWEcur ; C25M ; C25M ; 0.000 ; 0.000 ; 2.989 ; -; 2.770 ; nBODr ; nBODf0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.991 ; -; 2.771 ; InitActv ; WRD[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.992 ; -; 2.771 ; InitActv ; WRD[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.992 ; -; 2.829 ; LS[4] ; DRCLK ; C25M ; C25M ; 0.000 ; 0.000 ; 3.050 ; -; 2.868 ; nRESout~reg0 ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.089 ; -; 2.874 ; LS[2] ; LS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.095 ; -; 2.877 ; nRESout~reg0 ; nFCS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.098 ; -; 2.896 ; LS[1] ; LS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.117 ; -; 2.903 ; InitActv ; SDOE ; C25M ; C25M ; 0.000 ; 0.000 ; 3.124 ; -; 2.966 ; RAMSEL ; SDOE ; C25M ; C25M ; 0.000 ; 0.000 ; 3.187 ; -; 3.035 ; RAcur[11] ; RAMSEL ; C25M ; C25M ; 0.000 ; 0.000 ; 3.256 ; -; 3.084 ; InitActv ; InitActv ; C25M ; C25M ; 0.000 ; 0.000 ; 3.305 ; -; 3.091 ; nBODf ; InitActv ; C25M ; C25M ; 0.000 ; 0.000 ; 3.312 ; -; 3.177 ; MOSIout ; WRD[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.398 ; -; 3.185 ; S[0] ; RAMSEL ; C25M ; C25M ; 0.000 ; 0.000 ; 3.406 ; -; 3.188 ; S[2] ; S[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.409 ; -; 3.264 ; nBODf ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.485 ; -; 3.266 ; S[2] ; S[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.487 ; -; 3.281 ; RAMSEL ; RAMSEL ; C25M ; C25M ; 0.000 ; 0.000 ; 3.502 ; -; 3.284 ; LS[1] ; DRCLK ; C25M ; C25M ; 0.000 ; 0.000 ; 3.505 ; -; 3.285 ; LS[1] ; ARCLK ; C25M ; C25M ; 0.000 ; 0.000 ; 3.506 ; -; 3.301 ; LS[0] ; InitActv ; C25M ; C25M ; 0.000 ; 0.000 ; 3.522 ; -; 3.320 ; RAcur[0] ; RAMSEL ; C25M ; C25M ; 0.000 ; 0.000 ; 3.541 ; -; 3.342 ; LS[4] ; DRShift ; C25M ; C25M ; 0.000 ; 0.000 ; 3.563 ; -; 3.352 ; LS[2] ; SetLoaded ; C25M ; C25M ; 0.000 ; 0.000 ; 3.573 ; -; 3.377 ; LS[22] ; LS[22] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.598 ; -; 3.389 ; InitIntr ; SDRAMActv ; C25M ; C25M ; 0.000 ; 0.000 ; 3.610 ; -; 3.392 ; InitIntr ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.613 ; -; 3.429 ; nBODf ; SDRAMActv ; C25M ; C25M ; 0.000 ; 0.000 ; 3.650 ; -; 3.437 ; nBODf ; InitIntr ; C25M ; C25M ; 0.000 ; 0.000 ; 3.658 ; -; 3.521 ; LS[0] ; InitIntr ; C25M ; C25M ; 0.000 ; 0.000 ; 3.742 ; -; 3.523 ; S[2] ; SDOE ; C25M ; C25M ; 0.000 ; 0.000 ; 3.744 ; -; 3.530 ; LS[21] ; FCK~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.751 ; -; 3.539 ; LS[20] ; LS[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.760 ; -; 3.546 ; RAcur[10] ; RAMSEL ; C25M ; C25M ; 0.000 ; 0.000 ; 3.767 ; -; 3.552 ; S[1] ; S[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.773 ; -; 3.559 ; PHI0r2 ; RACr ; C25M ; C25M ; 0.000 ; 0.000 ; 3.780 ; -; 3.559 ; PHI0r2 ; RAcur[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.780 ; -; 3.559 ; PHI0r2 ; RAcur[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.780 ; -; 3.559 ; PHI0r2 ; RAcur[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.780 ; -; 3.559 ; PHI0r2 ; RAcur[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.780 ; -; 3.559 ; PHI0r2 ; RAcur[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.780 ; -; 3.559 ; PHI0r2 ; RAcur[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.780 ; -; 3.559 ; PHI0r2 ; RAcur[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.780 ; -; 3.559 ; PHI0r2 ; RAcur[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.780 ; -; 3.588 ; SetLoaded ; DRCLK ; C25M ; C25M ; 0.000 ; 0.000 ; 3.809 ; -; 3.597 ; PHI0r1 ; S[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.818 ; -; 3.602 ; PHI0r1 ; S[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.823 ; -; 3.652 ; LS[13] ; LS[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.873 ; -; 3.660 ; S[2] ; RAMSEL ; C25M ; C25M ; 0.000 ; 0.000 ; 3.881 ; -; 3.674 ; S[1] ; RAMSEL ; C25M ; C25M ; 0.000 ; 0.000 ; 3.895 ; -; 3.685 ; LS[6] ; LS[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.906 ; -; 3.701 ; LS[4] ; LS[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.922 ; -; 3.703 ; LS[1] ; LS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.924 ; -; 3.708 ; S[1] ; SDOE ; C25M ; C25M ; 0.000 ; 0.000 ; 3.929 ; -; 3.798 ; nRESout~reg0 ; InitActv ; C25M ; C25M ; 0.000 ; 0.000 ; 4.019 ; -; 3.823 ; LS[4] ; MOSIOE ; C25M ; C25M ; 0.000 ; 0.000 ; 4.044 ; -; 3.825 ; RAcur[8] ; RAMSEL ; C25M ; C25M ; 0.000 ; 0.000 ; 4.046 ; -; 3.874 ; S[2] ; nWEcur ; C25M ; C25M ; 0.000 ; 0.000 ; 4.095 ; -; 3.925 ; LS[2] ; DRShift ; C25M ; C25M ; 0.000 ; 0.000 ; 4.146 ; -; 3.965 ; LS[13] ; LS[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 4.186 ; -; 4.022 ; LS[0] ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 4.243 ; -; 4.093 ; RAcur[9] ; RAMSEL ; C25M ; C25M ; 0.000 ; 0.000 ; 4.314 ; -; 4.116 ; nRESr ; S[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 4.337 ; -; 4.157 ; LS[14] ; MOSIout ; C25M ; C25M ; 0.000 ; 0.000 ; 4.378 ; -; 4.184 ; nRESout~reg0 ; FCK~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 4.405 ; -; 4.184 ; nRESout~reg0 ; MOSIOE ; C25M ; C25M ; 0.000 ; 0.000 ; 4.405 ; -; 4.205 ; PHI0r1 ; nWEcur ; C25M ; C25M ; 0.000 ; 0.000 ; 4.426 ; -; 4.209 ; LS[1] ; WRD[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 4.430 ; -; 4.233 ; RACr ; RAMSEL ; C25M ; C25M ; 0.000 ; 0.000 ; 4.454 ; -; 4.233 ; LS[3] ; InitActv ; C25M ; C25M ; 0.000 ; 0.000 ; 4.454 ; -; 4.238 ; S[1] ; nWEcur ; C25M ; C25M ; 0.000 ; 0.000 ; 4.459 ; +; -1.031 ; ARCLK ; ARCLK ; ARCLK ; C25M ; 0.000 ; 3.348 ; 2.914 ; +; -0.531 ; ARCLK ; ARCLK ; ARCLK ; C25M ; -0.500 ; 3.348 ; 2.914 ; +; 1.646 ; IOSELr ; IOROMEN ; C25M ; C25M ; 0.000 ; 0.000 ; 1.867 ; +; 1.661 ; FCKEN ; FCK~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 1.882 ; +; 1.670 ; LS[17] ; LS[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.891 ; +; 1.687 ; PS[2] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.908 ; +; 1.787 ; PHI0r1 ; PHI0r2 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.008 ; +; 1.877 ; nBODr0 ; nBODr ; C25M ; C25M ; -0.500 ; 0.000 ; 1.598 ; +; 1.886 ; IOSELr0 ; IOSELr ; C25M ; C25M ; -0.500 ; 0.000 ; 1.607 ; +; 1.980 ; PS[0] ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.201 ; +; 2.009 ; SetLoaded ; ARShift ; C25M ; C25M ; 0.000 ; 0.000 ; 2.230 ; +; 2.027 ; SetLoaded ; DRShift ; C25M ; C25M ; 0.000 ; 0.000 ; 2.248 ; +; 2.055 ; IOSELr ; REGEN ; C25M ; C25M ; 0.000 ; 0.000 ; 2.276 ; +; 2.065 ; nBODf0 ; nBODf ; C25M ; C25M ; 0.000 ; 0.000 ; 2.286 ; +; 2.081 ; SDRAMActv ; RefReqd ; C25M ; C25M ; 0.000 ; 0.000 ; 2.302 ; +; 2.108 ; LS[6] ; LS[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.329 ; +; 2.120 ; nBODf ; InitActv ; C25M ; C25M ; 0.000 ; 0.000 ; 2.341 ; +; 2.125 ; LS[9] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.346 ; +; 2.126 ; LS[1] ; LS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ; +; 2.126 ; MOSIOE ; MOSIOE ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ; +; 2.135 ; InitIntr ; InitIntr ; C25M ; C25M ; 0.000 ; 0.000 ; 2.356 ; +; 2.137 ; LS[8] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.358 ; +; 2.137 ; LS[16] ; LS[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.358 ; +; 2.143 ; LS[10] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.364 ; +; 2.145 ; LS[11] ; LS[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.366 ; +; 2.152 ; PS[1] ; PS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.373 ; +; 2.212 ; nRESout~reg0 ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.433 ; +; 2.212 ; FCS ; FCS ; C25M ; C25M ; 0.000 ; 0.000 ; 2.433 ; +; 2.221 ; LS[7] ; LS[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.442 ; +; 2.221 ; LS[2] ; LS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.442 ; +; 2.230 ; LS[12] ; LS[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.451 ; +; 2.230 ; LS[14] ; LS[14] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.451 ; +; 2.230 ; LS[4] ; LS[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.451 ; +; 2.230 ; InitActv ; InitActv ; C25M ; C25M ; 0.000 ; 0.000 ; 2.451 ; +; 2.230 ; RefReqd ; RefReqd ; C25M ; C25M ; 0.000 ; 0.000 ; 2.451 ; +; 2.230 ; SetFW[0] ; SetFW[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.451 ; +; 2.231 ; LS[15] ; LS[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; +; 2.231 ; LS[13] ; LS[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; +; 2.231 ; LS[5] ; LS[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; +; 2.231 ; LS[3] ; LS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; +; 2.232 ; IOROMEN ; IOROMEN ; C25M ; C25M ; 0.000 ; 0.000 ; 2.453 ; +; 2.241 ; IS[1] ; IS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.462 ; +; 2.250 ; nCAS~reg0 ; nCAS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.471 ; +; 2.317 ; PS[0] ; PS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.538 ; +; 2.339 ; SetLoaded ; SetLoaded ; C25M ; C25M ; 0.000 ; 0.000 ; 2.560 ; +; 2.345 ; SetLoaded ; DRCLK ; C25M ; C25M ; 0.000 ; 0.000 ; 2.566 ; +; 2.349 ; SetLoaded ; ARCLK ; C25M ; C25M ; 0.000 ; 0.000 ; 2.570 ; +; 2.357 ; nBODf ; InitIntr ; C25M ; C25M ; 0.000 ; 0.000 ; 2.578 ; +; 2.362 ; nBODf ; SDRAMActv ; C25M ; C25M ; 0.000 ; 0.000 ; 2.583 ; +; 2.380 ; nRESr ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.601 ; +; 2.411 ; LS[0] ; LS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.632 ; +; 2.570 ; nBODf ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.791 ; +; 2.581 ; PS[3] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.802 ; +; 2.659 ; REGEN ; REGEN ; C25M ; C25M ; 0.000 ; 0.000 ; 2.880 ; +; 2.669 ; SDRAMActv ; SDRAMActv ; C25M ; C25M ; 0.000 ; 0.000 ; 2.890 ; +; 2.715 ; InitIntr ; SDRAMActv ; C25M ; C25M ; 0.000 ; 0.000 ; 2.936 ; +; 2.804 ; nBODr ; nBODf0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.025 ; +; 2.932 ; PS[1] ; nCAS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.153 ; +; 2.940 ; LS[6] ; LS[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.161 ; +; 2.957 ; LS[9] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.178 ; +; 2.958 ; LS[1] ; LS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.179 ; +; 2.969 ; LS[16] ; LS[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.190 ; +; 2.973 ; LS[5] ; RefReqd ; C25M ; C25M ; 0.000 ; 0.000 ; 3.194 ; +; 2.975 ; LS[10] ; LS[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.196 ; +; 2.977 ; LS[11] ; LS[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.198 ; +; 2.977 ; InitActv ; SDRAMActv ; C25M ; C25M ; 0.000 ; 0.000 ; 3.198 ; +; 3.012 ; PHI0r0 ; PHI0r1 ; C25M ; C25M ; -0.500 ; 0.000 ; 2.733 ; +; 3.051 ; LS[6] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.272 ; +; 3.057 ; DEVSELr0 ; DEVSELr ; C25M ; C25M ; -0.500 ; 0.000 ; 2.778 ; +; 3.068 ; LS[9] ; LS[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.289 ; +; 3.069 ; LS[1] ; LS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.290 ; +; 3.080 ; PS[2] ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.301 ; +; 3.086 ; LS[10] ; LS[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.307 ; +; 3.088 ; LS[11] ; LS[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.309 ; +; 3.119 ; nRESr ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.340 ; +; 3.126 ; nRESr ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.347 ; +; 3.128 ; nRESr ; PS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.349 ; +; 3.145 ; InitIntr ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.366 ; +; 3.160 ; PS[3] ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.381 ; +; 3.161 ; LS[7] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.382 ; +; 3.161 ; LS[2] ; LS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.382 ; +; 3.167 ; nRAS~reg0 ; nRAS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.388 ; +; 3.170 ; LS[14] ; LS[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.391 ; +; 3.170 ; LS[4] ; LS[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.391 ; +; 3.170 ; LS[12] ; LS[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.391 ; +; 3.171 ; LS[5] ; LS[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.392 ; +; 3.171 ; LS[15] ; LS[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.392 ; +; 3.179 ; LS[9] ; LS[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.400 ; +; 3.197 ; LS[10] ; LS[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.418 ; +; 3.281 ; LS[4] ; LS[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.502 ; +; 3.281 ; LS[14] ; LS[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.502 ; +; 3.282 ; LS[5] ; LS[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.503 ; +; 3.282 ; LS[15] ; LS[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.503 ; +; 3.290 ; LS[9] ; LS[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.511 ; +; 3.316 ; FCKEN ; FCKEN ; C25M ; C25M ; 0.000 ; 0.000 ; 3.537 ; +; 3.361 ; LS[1] ; WRD[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.582 ; +; 3.363 ; PS[2] ; RCKE~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.584 ; +; 3.384 ; LS[0] ; LS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.605 ; +; 3.392 ; LS[4] ; LS[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.613 ; +; 3.392 ; LS[14] ; LS[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.613 ; +--------+--------------+--------------+--------------+-------------+--------------+------------+------------+ @@ -463,8 +463,26 @@ No paths to report. ; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; DRCLK ; ; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; DRShift ; ; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; DRShift ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; FCKEN ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; FCKEN ; ; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; FCK~reg0 ; ; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; FCK~reg0 ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; FCS ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; FCS ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; IOROMEN ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; IOROMEN ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; IOSELr ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; IOSELr ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Fall ; IOSELr0 ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Fall ; IOSELr0 ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; IOSTRBr ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; IOSTRBr ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Fall ; IOSTRBr0 ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Fall ; IOSTRBr0 ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; IS[0] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; IS[0] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; IS[1] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; IS[1] ; ; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; InitActv ; ; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; InitActv ; ; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; InitIntr ; @@ -487,18 +505,8 @@ No paths to report. ; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[16] ; ; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[17] ; ; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[17] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[18] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[18] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[19] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[19] ; ; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[1] ; ; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[1] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[20] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[20] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[21] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[21] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[22] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[22] ; ; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[2] ; ; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[2] ; ; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[3] ; @@ -525,10 +533,16 @@ No paths to report. ; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; PHI0r1 ; ; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; PHI0r2 ; ; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; PHI0r2 ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; PS[0] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; PS[0] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; PS[1] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; PS[1] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; PS[2] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; PS[2] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; PS[3] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; PS[3] ; ; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; RACr ; ; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; RACr ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; RAMSEL ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; RAMSEL ; ; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; RAcur[0] ; ; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; RAcur[0] ; ; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; RAcur[10] ; @@ -536,20 +550,6 @@ No paths to report. ; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; RAcur[11] ; ; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; RAcur[11] ; ; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; RAcur[1] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; RAcur[1] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; RAcur[2] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; RAcur[2] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; RAcur[3] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; RAcur[3] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; RAcur[8] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; RAcur[8] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; RAcur[9] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; RAcur[9] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; SDOE ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; SDOE ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; SDRAMActv ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; SDRAMActv ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; S[0] ; +--------+--------------+----------------+------------------+-------+------------+-----------+ @@ -558,34 +558,40 @@ No paths to report. +-----------+------------+-------+-------+------------+-----------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+-------+-------+------------+-----------------+ -; MISO ; C25M ; 2.942 ; 2.942 ; Rise ; C25M ; -; RA[*] ; C25M ; 3.501 ; 3.501 ; Rise ; C25M ; -; RA[0] ; C25M ; 2.717 ; 2.717 ; Rise ; C25M ; -; RA[1] ; C25M ; 1.838 ; 1.838 ; Rise ; C25M ; -; RA[2] ; C25M ; 1.842 ; 1.842 ; Rise ; C25M ; -; RA[3] ; C25M ; 2.604 ; 2.604 ; Rise ; C25M ; -; RA[8] ; C25M ; 2.435 ; 2.435 ; Rise ; C25M ; -; RA[9] ; C25M ; 2.467 ; 2.467 ; Rise ; C25M ; -; RA[10] ; C25M ; 2.663 ; 2.663 ; Rise ; C25M ; -; RA[11] ; C25M ; 2.353 ; 2.353 ; Rise ; C25M ; -; RA[12] ; C25M ; 3.501 ; 3.501 ; Rise ; C25M ; -; RA[13] ; C25M ; 3.219 ; 3.219 ; Rise ; C25M ; -; RA[14] ; C25M ; 2.101 ; 2.101 ; Rise ; C25M ; -; RA[15] ; C25M ; 3.148 ; 3.148 ; Rise ; C25M ; -; RD[*] ; C25M ; 3.584 ; 3.584 ; Rise ; C25M ; -; RD[0] ; C25M ; 2.094 ; 2.094 ; Rise ; C25M ; -; RD[1] ; C25M ; 1.819 ; 1.819 ; Rise ; C25M ; -; RD[2] ; C25M ; 2.431 ; 2.431 ; Rise ; C25M ; -; RD[3] ; C25M ; 2.028 ; 2.028 ; Rise ; C25M ; -; RD[4] ; C25M ; 1.817 ; 1.817 ; Rise ; C25M ; -; RD[5] ; C25M ; 2.454 ; 2.454 ; Rise ; C25M ; -; RD[6] ; C25M ; 3.584 ; 3.584 ; Rise ; C25M ; -; RD[7] ; C25M ; 3.280 ; 3.280 ; Rise ; C25M ; -; nBOD ; C25M ; 2.712 ; 2.712 ; Rise ; C25M ; -; nRES ; C25M ; 2.707 ; 2.707 ; Rise ; C25M ; -; nWE ; C25M ; 2.649 ; 2.649 ; Rise ; C25M ; -; PHI0 ; C25M ; 2.420 ; 2.420 ; Fall ; C25M ; -; nDEVSEL ; C25M ; 2.916 ; 2.916 ; Fall ; C25M ; +; MISO ; C25M ; 3.547 ; 3.547 ; Rise ; C25M ; +; RA[*] ; C25M ; 3.862 ; 3.862 ; Rise ; C25M ; +; RA[0] ; C25M ; 2.127 ; 2.127 ; Rise ; C25M ; +; RA[1] ; C25M ; 2.953 ; 2.953 ; Rise ; C25M ; +; RA[2] ; C25M ; 2.929 ; 2.929 ; Rise ; C25M ; +; RA[3] ; C25M ; 2.446 ; 2.446 ; Rise ; C25M ; +; RA[4] ; C25M ; 1.926 ; 1.926 ; Rise ; C25M ; +; RA[5] ; C25M ; 1.793 ; 1.793 ; Rise ; C25M ; +; RA[6] ; C25M ; 2.659 ; 2.659 ; Rise ; C25M ; +; RA[7] ; C25M ; 1.849 ; 1.849 ; Rise ; C25M ; +; RA[8] ; C25M ; 2.684 ; 2.684 ; Rise ; C25M ; +; RA[9] ; C25M ; 2.694 ; 2.694 ; Rise ; C25M ; +; RA[10] ; C25M ; 2.926 ; 2.926 ; Rise ; C25M ; +; RA[11] ; C25M ; 2.456 ; 2.456 ; Rise ; C25M ; +; RA[12] ; C25M ; 3.512 ; 3.512 ; Rise ; C25M ; +; RA[13] ; C25M ; 3.862 ; 3.862 ; Rise ; C25M ; +; RA[14] ; C25M ; 2.029 ; 2.029 ; Rise ; C25M ; +; RA[15] ; C25M ; 3.701 ; 3.701 ; Rise ; C25M ; +; RD[*] ; C25M ; 4.042 ; 4.042 ; Rise ; C25M ; +; RD[0] ; C25M ; 2.631 ; 2.631 ; Rise ; C25M ; +; RD[1] ; C25M ; 2.789 ; 2.789 ; Rise ; C25M ; +; RD[2] ; C25M ; 1.817 ; 1.817 ; Rise ; C25M ; +; RD[3] ; C25M ; 2.669 ; 2.669 ; Rise ; C25M ; +; RD[4] ; C25M ; 2.027 ; 2.027 ; Rise ; C25M ; +; RD[5] ; C25M ; 1.833 ; 1.833 ; Rise ; C25M ; +; RD[6] ; C25M ; 4.042 ; 4.042 ; Rise ; C25M ; +; RD[7] ; C25M ; 2.990 ; 2.990 ; Rise ; C25M ; +; nWE ; C25M ; 2.526 ; 2.526 ; Rise ; C25M ; +; PHI0 ; C25M ; 2.666 ; 2.666 ; Fall ; C25M ; +; nBOD ; C25M ; 2.626 ; 2.626 ; Fall ; C25M ; +; nDEVSEL ; C25M ; 2.111 ; 2.111 ; Fall ; C25M ; +; nIOSEL ; C25M ; 2.125 ; 2.125 ; Fall ; C25M ; +; nIOSTRB ; C25M ; 2.393 ; 2.393 ; Fall ; C25M ; +; nRES ; C25M ; 2.421 ; 2.421 ; Fall ; C25M ; +-----------+------------+-------+-------+------------+-----------------+ @@ -594,97 +600,219 @@ No paths to report. +-----------+------------+--------+--------+------------+-----------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+--------+--------+------------+-----------------+ -; MISO ; C25M ; -2.388 ; -2.388 ; Rise ; C25M ; -; RA[*] ; C25M ; -1.284 ; -1.284 ; Rise ; C25M ; -; RA[0] ; C25M ; -2.163 ; -2.163 ; Rise ; C25M ; -; RA[1] ; C25M ; -1.284 ; -1.284 ; Rise ; C25M ; -; RA[2] ; C25M ; -1.288 ; -1.288 ; Rise ; C25M ; -; RA[3] ; C25M ; -2.050 ; -2.050 ; Rise ; C25M ; -; RA[8] ; C25M ; -1.881 ; -1.881 ; Rise ; C25M ; -; RA[9] ; C25M ; -1.913 ; -1.913 ; Rise ; C25M ; -; RA[10] ; C25M ; -2.109 ; -2.109 ; Rise ; C25M ; -; RA[11] ; C25M ; -1.799 ; -1.799 ; Rise ; C25M ; -; RA[12] ; C25M ; -2.947 ; -2.947 ; Rise ; C25M ; -; RA[13] ; C25M ; -2.665 ; -2.665 ; Rise ; C25M ; -; RA[14] ; C25M ; -1.547 ; -1.547 ; Rise ; C25M ; -; RA[15] ; C25M ; -2.594 ; -2.594 ; Rise ; C25M ; +; MISO ; C25M ; -2.993 ; -2.993 ; Rise ; C25M ; +; RA[*] ; C25M ; -1.239 ; -1.239 ; Rise ; C25M ; +; RA[0] ; C25M ; -1.573 ; -1.573 ; Rise ; C25M ; +; RA[1] ; C25M ; -2.399 ; -2.399 ; Rise ; C25M ; +; RA[2] ; C25M ; -2.375 ; -2.375 ; Rise ; C25M ; +; RA[3] ; C25M ; -1.892 ; -1.892 ; Rise ; C25M ; +; RA[4] ; C25M ; -1.372 ; -1.372 ; Rise ; C25M ; +; RA[5] ; C25M ; -1.239 ; -1.239 ; Rise ; C25M ; +; RA[6] ; C25M ; -2.105 ; -2.105 ; Rise ; C25M ; +; RA[7] ; C25M ; -1.295 ; -1.295 ; Rise ; C25M ; +; RA[8] ; C25M ; -2.130 ; -2.130 ; Rise ; C25M ; +; RA[9] ; C25M ; -2.140 ; -2.140 ; Rise ; C25M ; +; RA[10] ; C25M ; -2.372 ; -2.372 ; Rise ; C25M ; +; RA[11] ; C25M ; -1.902 ; -1.902 ; Rise ; C25M ; +; RA[12] ; C25M ; -2.958 ; -2.958 ; Rise ; C25M ; +; RA[13] ; C25M ; -3.308 ; -3.308 ; Rise ; C25M ; +; RA[14] ; C25M ; -1.475 ; -1.475 ; Rise ; C25M ; +; RA[15] ; C25M ; -3.147 ; -3.147 ; Rise ; C25M ; ; RD[*] ; C25M ; -1.263 ; -1.263 ; Rise ; C25M ; -; RD[0] ; C25M ; -1.540 ; -1.540 ; Rise ; C25M ; -; RD[1] ; C25M ; -1.265 ; -1.265 ; Rise ; C25M ; -; RD[2] ; C25M ; -1.877 ; -1.877 ; Rise ; C25M ; -; RD[3] ; C25M ; -1.474 ; -1.474 ; Rise ; C25M ; -; RD[4] ; C25M ; -1.263 ; -1.263 ; Rise ; C25M ; -; RD[5] ; C25M ; -1.900 ; -1.900 ; Rise ; C25M ; -; RD[6] ; C25M ; -3.030 ; -3.030 ; Rise ; C25M ; -; RD[7] ; C25M ; -2.726 ; -2.726 ; Rise ; C25M ; -; nBOD ; C25M ; -2.158 ; -2.158 ; Rise ; C25M ; -; nRES ; C25M ; -2.153 ; -2.153 ; Rise ; C25M ; -; nWE ; C25M ; -2.095 ; -2.095 ; Rise ; C25M ; -; PHI0 ; C25M ; -1.866 ; -1.866 ; Fall ; C25M ; -; nDEVSEL ; C25M ; -2.362 ; -2.362 ; Fall ; C25M ; +; RD[0] ; C25M ; -2.077 ; -2.077 ; Rise ; C25M ; +; RD[1] ; C25M ; -2.235 ; -2.235 ; Rise ; C25M ; +; RD[2] ; C25M ; -1.263 ; -1.263 ; Rise ; C25M ; +; RD[3] ; C25M ; -2.115 ; -2.115 ; Rise ; C25M ; +; RD[4] ; C25M ; -1.473 ; -1.473 ; Rise ; C25M ; +; RD[5] ; C25M ; -1.279 ; -1.279 ; Rise ; C25M ; +; RD[6] ; C25M ; -3.488 ; -3.488 ; Rise ; C25M ; +; RD[7] ; C25M ; -2.436 ; -2.436 ; Rise ; C25M ; +; nWE ; C25M ; -1.972 ; -1.972 ; Rise ; C25M ; +; PHI0 ; C25M ; -2.112 ; -2.112 ; Fall ; C25M ; +; nBOD ; C25M ; -2.072 ; -2.072 ; Fall ; C25M ; +; nDEVSEL ; C25M ; -1.557 ; -1.557 ; Fall ; C25M ; +; nIOSEL ; C25M ; -1.571 ; -1.571 ; Fall ; C25M ; +; nIOSTRB ; C25M ; -1.839 ; -1.839 ; Fall ; C25M ; +; nRES ; C25M ; -1.867 ; -1.867 ; Fall ; C25M ; +-----------+------------+--------+--------+------------+-----------------+ -+-----------------------------------------------------------------------+ -; Clock to Output Times ; -+-----------+------------+-------+-------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-----------+------------+-------+-------+------------+-----------------+ -; FCK ; C25M ; 8.081 ; 8.081 ; Rise ; C25M ; -; MOSI ; C25M ; 8.599 ; 8.599 ; Rise ; C25M ; -; SD[*] ; C25M ; 8.802 ; 8.802 ; Rise ; C25M ; -; SD[0] ; C25M ; 6.853 ; 6.853 ; Rise ; C25M ; -; SD[1] ; C25M ; 6.847 ; 6.847 ; Rise ; C25M ; -; SD[2] ; C25M ; 6.820 ; 6.820 ; Rise ; C25M ; -; SD[3] ; C25M ; 6.867 ; 6.867 ; Rise ; C25M ; -; SD[4] ; C25M ; 6.848 ; 6.848 ; Rise ; C25M ; -; SD[5] ; C25M ; 6.814 ; 6.814 ; Rise ; C25M ; -; SD[6] ; C25M ; 8.802 ; 8.802 ; Rise ; C25M ; -; SD[7] ; C25M ; 8.542 ; 8.542 ; Rise ; C25M ; -; nFCS ; C25M ; 6.854 ; 6.854 ; Rise ; C25M ; -; nRESout ; C25M ; 8.024 ; 8.024 ; Rise ; C25M ; -+-----------+------------+-------+-------+------------+-----------------+ ++-------------------------------------------------------------------------+ +; Clock to Output Times ; ++-----------+------------+--------+--------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+--------+--------+------------+-----------------+ +; FCK ; C25M ; 6.814 ; 6.814 ; Rise ; C25M ; +; MOSI ; C25M ; 9.054 ; 9.054 ; Rise ; C25M ; +; RCKE ; C25M ; 8.111 ; 8.111 ; Rise ; C25M ; +; RD[*] ; C25M ; 14.025 ; 14.025 ; Rise ; C25M ; +; RD[0] ; C25M ; 13.989 ; 13.989 ; Rise ; C25M ; +; RD[1] ; C25M ; 13.989 ; 13.989 ; Rise ; C25M ; +; RD[2] ; C25M ; 14.025 ; 14.025 ; Rise ; C25M ; +; RD[3] ; C25M ; 13.564 ; 13.564 ; Rise ; C25M ; +; RD[4] ; C25M ; 14.025 ; 14.025 ; Rise ; C25M ; +; RD[5] ; C25M ; 14.025 ; 14.025 ; Rise ; C25M ; +; RD[6] ; C25M ; 13.564 ; 13.564 ; Rise ; C25M ; +; RD[7] ; C25M ; 14.005 ; 14.005 ; Rise ; C25M ; +; RDdir ; C25M ; 13.564 ; 13.564 ; Rise ; C25M ; +; SD[*] ; C25M ; 8.201 ; 8.201 ; Rise ; C25M ; +; SD[0] ; C25M ; 8.201 ; 8.201 ; Rise ; C25M ; +; SD[1] ; C25M ; 8.097 ; 8.097 ; Rise ; C25M ; +; SD[2] ; C25M ; 8.090 ; 8.090 ; Rise ; C25M ; +; SD[3] ; C25M ; 8.137 ; 8.137 ; Rise ; C25M ; +; SD[4] ; C25M ; 8.111 ; 8.111 ; Rise ; C25M ; +; SD[5] ; C25M ; 8.101 ; 8.101 ; Rise ; C25M ; +; SD[6] ; C25M ; 6.820 ; 6.820 ; Rise ; C25M ; +; SD[7] ; C25M ; 6.820 ; 6.820 ; Rise ; C25M ; +; nCAS ; C25M ; 8.703 ; 8.703 ; Rise ; C25M ; +; nFCS ; C25M ; 8.534 ; 8.534 ; Rise ; C25M ; +; nRAS ; C25M ; 8.131 ; 8.131 ; Rise ; C25M ; +; nRCS ; C25M ; 6.859 ; 6.859 ; Rise ; C25M ; +; nRESout ; C25M ; 7.478 ; 7.478 ; Rise ; C25M ; +; nSWE ; C25M ; 6.827 ; 6.827 ; Rise ; C25M ; ++-----------+------------+--------+--------+------------+-----------------+ -+-----------------------------------------------------------------------+ -; Minimum Clock to Output Times ; -+-----------+------------+-------+-------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-----------+------------+-------+-------+------------+-----------------+ -; FCK ; C25M ; 8.081 ; 8.081 ; Rise ; C25M ; -; MOSI ; C25M ; 8.599 ; 8.599 ; Rise ; C25M ; -; SD[*] ; C25M ; 6.814 ; 6.814 ; Rise ; C25M ; -; SD[0] ; C25M ; 6.853 ; 6.853 ; Rise ; C25M ; -; SD[1] ; C25M ; 6.847 ; 6.847 ; Rise ; C25M ; -; SD[2] ; C25M ; 6.820 ; 6.820 ; Rise ; C25M ; -; SD[3] ; C25M ; 6.867 ; 6.867 ; Rise ; C25M ; -; SD[4] ; C25M ; 6.848 ; 6.848 ; Rise ; C25M ; -; SD[5] ; C25M ; 6.814 ; 6.814 ; Rise ; C25M ; -; SD[6] ; C25M ; 8.802 ; 8.802 ; Rise ; C25M ; -; SD[7] ; C25M ; 8.542 ; 8.542 ; Rise ; C25M ; -; nFCS ; C25M ; 6.854 ; 6.854 ; Rise ; C25M ; -; nRESout ; C25M ; 8.024 ; 8.024 ; Rise ; C25M ; -+-----------+------------+-------+-------+------------+-----------------+ ++-------------------------------------------------------------------------+ +; Minimum Clock to Output Times ; ++-----------+------------+--------+--------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+--------+--------+------------+-----------------+ +; FCK ; C25M ; 6.814 ; 6.814 ; Rise ; C25M ; +; MOSI ; C25M ; 9.054 ; 9.054 ; Rise ; C25M ; +; RCKE ; C25M ; 8.111 ; 8.111 ; Rise ; C25M ; +; RD[*] ; C25M ; 10.614 ; 10.614 ; Rise ; C25M ; +; RD[0] ; C25M ; 11.039 ; 11.039 ; Rise ; C25M ; +; RD[1] ; C25M ; 11.039 ; 11.039 ; Rise ; C25M ; +; RD[2] ; C25M ; 11.075 ; 11.075 ; Rise ; C25M ; +; RD[3] ; C25M ; 10.614 ; 10.614 ; Rise ; C25M ; +; RD[4] ; C25M ; 11.075 ; 11.075 ; Rise ; C25M ; +; RD[5] ; C25M ; 11.075 ; 11.075 ; Rise ; C25M ; +; RD[6] ; C25M ; 10.614 ; 10.614 ; Rise ; C25M ; +; RD[7] ; C25M ; 11.055 ; 11.055 ; Rise ; C25M ; +; RDdir ; C25M ; 10.614 ; 10.614 ; Rise ; C25M ; +; SD[*] ; C25M ; 6.820 ; 6.820 ; Rise ; C25M ; +; SD[0] ; C25M ; 8.201 ; 8.201 ; Rise ; C25M ; +; SD[1] ; C25M ; 8.097 ; 8.097 ; Rise ; C25M ; +; SD[2] ; C25M ; 8.090 ; 8.090 ; Rise ; C25M ; +; SD[3] ; C25M ; 8.137 ; 8.137 ; Rise ; C25M ; +; SD[4] ; C25M ; 8.111 ; 8.111 ; Rise ; C25M ; +; SD[5] ; C25M ; 8.101 ; 8.101 ; Rise ; C25M ; +; SD[6] ; C25M ; 6.820 ; 6.820 ; Rise ; C25M ; +; SD[7] ; C25M ; 6.820 ; 6.820 ; Rise ; C25M ; +; nCAS ; C25M ; 8.703 ; 8.703 ; Rise ; C25M ; +; nFCS ; C25M ; 8.534 ; 8.534 ; Rise ; C25M ; +; nRAS ; C25M ; 8.131 ; 8.131 ; Rise ; C25M ; +; nRCS ; C25M ; 6.859 ; 6.859 ; Rise ; C25M ; +; nRESout ; C25M ; 7.478 ; 7.478 ; Rise ; C25M ; +; nSWE ; C25M ; 6.827 ; 6.827 ; Rise ; C25M ; ++-----------+------------+--------+--------+------------+-----------------+ -+----------------------------------------------------+ -; Propagation Delay ; -+------------+-------------+-------+----+----+-------+ -; Input Port ; Output Port ; RR ; RF ; FR ; FF ; -+------------+-------------+-------+----+----+-------+ -; DMAin ; DMAout ; 8.003 ; ; ; 8.003 ; -; INTin ; INTout ; 8.012 ; ; ; 8.012 ; -+------------+-------------+-------+----+----+-------+ ++------------------------------------------------------+ +; Propagation Delay ; ++------------+-------------+--------+----+----+--------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+--------+----+----+--------+ +; PHI0 ; RD[0] ; 13.206 ; ; ; 13.206 ; +; PHI0 ; RD[1] ; 13.206 ; ; ; 13.206 ; +; PHI0 ; RD[2] ; 13.242 ; ; ; 13.242 ; +; PHI0 ; RD[3] ; 12.781 ; ; ; 12.781 ; +; PHI0 ; RD[4] ; 13.242 ; ; ; 13.242 ; +; PHI0 ; RD[5] ; 13.242 ; ; ; 13.242 ; +; PHI0 ; RD[6] ; 12.781 ; ; ; 12.781 ; +; PHI0 ; RD[7] ; 13.222 ; ; ; 13.222 ; +; PHI0 ; RDdir ; 12.781 ; ; ; 12.781 ; +; nDEVSEL ; RD[0] ; 11.475 ; ; ; 11.475 ; +; nDEVSEL ; RD[1] ; 11.475 ; ; ; 11.475 ; +; nDEVSEL ; RD[2] ; 11.511 ; ; ; 11.511 ; +; nDEVSEL ; RD[3] ; 11.050 ; ; ; 11.050 ; +; nDEVSEL ; RD[4] ; 11.511 ; ; ; 11.511 ; +; nDEVSEL ; RD[5] ; 11.511 ; ; ; 11.511 ; +; nDEVSEL ; RD[6] ; 11.050 ; ; ; 11.050 ; +; nDEVSEL ; RD[7] ; 11.491 ; ; ; 11.491 ; +; nDEVSEL ; RDdir ; 11.050 ; ; ; 11.050 ; +; nIOSEL ; RD[0] ; 10.201 ; ; ; 10.201 ; +; nIOSEL ; RD[1] ; 10.201 ; ; ; 10.201 ; +; nIOSEL ; RD[2] ; 10.237 ; ; ; 10.237 ; +; nIOSEL ; RD[3] ; 9.776 ; ; ; 9.776 ; +; nIOSEL ; RD[4] ; 10.237 ; ; ; 10.237 ; +; nIOSEL ; RD[5] ; 10.237 ; ; ; 10.237 ; +; nIOSEL ; RD[6] ; 9.776 ; ; ; 9.776 ; +; nIOSEL ; RD[7] ; 10.217 ; ; ; 10.217 ; +; nIOSEL ; RDdir ; 9.776 ; ; ; 9.776 ; +; nIOSTRB ; RD[0] ; 11.644 ; ; ; 11.644 ; +; nIOSTRB ; RD[1] ; 11.644 ; ; ; 11.644 ; +; nIOSTRB ; RD[2] ; 11.680 ; ; ; 11.680 ; +; nIOSTRB ; RD[3] ; 11.219 ; ; ; 11.219 ; +; nIOSTRB ; RD[4] ; 11.680 ; ; ; 11.680 ; +; nIOSTRB ; RD[5] ; 11.680 ; ; ; 11.680 ; +; nIOSTRB ; RD[6] ; 11.219 ; ; ; 11.219 ; +; nIOSTRB ; RD[7] ; 11.660 ; ; ; 11.660 ; +; nIOSTRB ; RDdir ; 11.219 ; ; ; 11.219 ; +; nWE ; RD[0] ; 14.484 ; ; ; 14.484 ; +; nWE ; RD[1] ; 14.484 ; ; ; 14.484 ; +; nWE ; RD[2] ; 14.520 ; ; ; 14.520 ; +; nWE ; RD[3] ; 14.059 ; ; ; 14.059 ; +; nWE ; RD[4] ; 14.520 ; ; ; 14.520 ; +; nWE ; RD[5] ; 14.520 ; ; ; 14.520 ; +; nWE ; RD[6] ; 14.059 ; ; ; 14.059 ; +; nWE ; RD[7] ; 14.500 ; ; ; 14.500 ; +; nWE ; RDdir ; 14.059 ; ; ; 14.059 ; ++------------+-------------+--------+----+----+--------+ -+----------------------------------------------------+ -; Minimum Propagation Delay ; -+------------+-------------+-------+----+----+-------+ -; Input Port ; Output Port ; RR ; RF ; FR ; FF ; -+------------+-------------+-------+----+----+-------+ -; DMAin ; DMAout ; 8.003 ; ; ; 8.003 ; -; INTin ; INTout ; 8.012 ; ; ; 8.012 ; -+------------+-------------+-------+----+----+-------+ ++------------------------------------------------------+ +; Minimum Propagation Delay ; ++------------+-------------+--------+----+----+--------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+--------+----+----+--------+ +; PHI0 ; RD[0] ; 13.206 ; ; ; 13.206 ; +; PHI0 ; RD[1] ; 13.206 ; ; ; 13.206 ; +; PHI0 ; RD[2] ; 13.242 ; ; ; 13.242 ; +; PHI0 ; RD[3] ; 12.781 ; ; ; 12.781 ; +; PHI0 ; RD[4] ; 13.242 ; ; ; 13.242 ; +; PHI0 ; RD[5] ; 13.242 ; ; ; 13.242 ; +; PHI0 ; RD[6] ; 12.781 ; ; ; 12.781 ; +; PHI0 ; RD[7] ; 13.222 ; ; ; 13.222 ; +; PHI0 ; RDdir ; 12.781 ; ; ; 12.781 ; +; nDEVSEL ; RD[0] ; 11.475 ; ; ; 11.475 ; +; nDEVSEL ; RD[1] ; 11.475 ; ; ; 11.475 ; +; nDEVSEL ; RD[2] ; 11.511 ; ; ; 11.511 ; +; nDEVSEL ; RD[3] ; 11.050 ; ; ; 11.050 ; +; nDEVSEL ; RD[4] ; 11.511 ; ; ; 11.511 ; +; nDEVSEL ; RD[5] ; 11.511 ; ; ; 11.511 ; +; nDEVSEL ; RD[6] ; 11.050 ; ; ; 11.050 ; +; nDEVSEL ; RD[7] ; 11.491 ; ; ; 11.491 ; +; nDEVSEL ; RDdir ; 11.050 ; ; ; 11.050 ; +; nIOSEL ; RD[0] ; 10.201 ; ; ; 10.201 ; +; nIOSEL ; RD[1] ; 10.201 ; ; ; 10.201 ; +; nIOSEL ; RD[2] ; 10.237 ; ; ; 10.237 ; +; nIOSEL ; RD[3] ; 9.776 ; ; ; 9.776 ; +; nIOSEL ; RD[4] ; 10.237 ; ; ; 10.237 ; +; nIOSEL ; RD[5] ; 10.237 ; ; ; 10.237 ; +; nIOSEL ; RD[6] ; 9.776 ; ; ; 9.776 ; +; nIOSEL ; RD[7] ; 10.217 ; ; ; 10.217 ; +; nIOSEL ; RDdir ; 9.776 ; ; ; 9.776 ; +; nIOSTRB ; RD[0] ; 11.644 ; ; ; 11.644 ; +; nIOSTRB ; RD[1] ; 11.644 ; ; ; 11.644 ; +; nIOSTRB ; RD[2] ; 11.680 ; ; ; 11.680 ; +; nIOSTRB ; RD[3] ; 11.219 ; ; ; 11.219 ; +; nIOSTRB ; RD[4] ; 11.680 ; ; ; 11.680 ; +; nIOSTRB ; RD[5] ; 11.680 ; ; ; 11.680 ; +; nIOSTRB ; RD[6] ; 11.219 ; ; ; 11.219 ; +; nIOSTRB ; RD[7] ; 11.660 ; ; ; 11.660 ; +; nIOSTRB ; RDdir ; 11.219 ; ; ; 11.219 ; +; nWE ; RD[0] ; 14.484 ; ; ; 14.484 ; +; nWE ; RD[1] ; 14.484 ; ; ; 14.484 ; +; nWE ; RD[2] ; 14.520 ; ; ; 14.520 ; +; nWE ; RD[3] ; 14.059 ; ; ; 14.059 ; +; nWE ; RD[4] ; 14.520 ; ; ; 14.520 ; +; nWE ; RD[5] ; 14.520 ; ; ; 14.520 ; +; nWE ; RD[6] ; 14.059 ; ; ; 14.059 ; +; nWE ; RD[7] ; 14.500 ; ; ; 14.500 ; +; nWE ; RDdir ; 14.059 ; ; ; 14.059 ; ++------------+-------------+--------+----+----+--------+ +----------------------------------------------------------------------+ @@ -692,16 +820,16 @@ No paths to report. +-----------+------------+-------+------+------------+-----------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+-------+------+------------+-----------------+ -; MOSI ; C25M ; 6.350 ; ; Rise ; C25M ; -; SD[*] ; C25M ; 7.768 ; ; Rise ; C25M ; -; SD[0] ; C25M ; 8.282 ; ; Rise ; C25M ; -; SD[1] ; C25M ; 8.282 ; ; Rise ; C25M ; -; SD[2] ; C25M ; 8.282 ; ; Rise ; C25M ; -; SD[3] ; C25M ; 8.282 ; ; Rise ; C25M ; -; SD[4] ; C25M ; 8.282 ; ; Rise ; C25M ; -; SD[5] ; C25M ; 8.282 ; ; Rise ; C25M ; -; SD[6] ; C25M ; 7.768 ; ; Rise ; C25M ; -; SD[7] ; C25M ; 7.768 ; ; Rise ; C25M ; +; MOSI ; C25M ; 8.354 ; ; Rise ; C25M ; +; SD[*] ; C25M ; 6.777 ; ; Rise ; C25M ; +; SD[0] ; C25M ; 7.423 ; ; Rise ; C25M ; +; SD[1] ; C25M ; 6.983 ; ; Rise ; C25M ; +; SD[2] ; C25M ; 6.983 ; ; Rise ; C25M ; +; SD[3] ; C25M ; 7.423 ; ; Rise ; C25M ; +; SD[4] ; C25M ; 6.983 ; ; Rise ; C25M ; +; SD[5] ; C25M ; 6.983 ; ; Rise ; C25M ; +; SD[6] ; C25M ; 6.777 ; ; Rise ; C25M ; +; SD[7] ; C25M ; 6.777 ; ; Rise ; C25M ; +-----------+------------+-------+------+------------+-----------------+ @@ -710,16 +838,16 @@ No paths to report. +-----------+------------+-------+------+------------+-----------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+-------+------+------------+-----------------+ -; MOSI ; C25M ; 6.350 ; ; Rise ; C25M ; -; SD[*] ; C25M ; 7.768 ; ; Rise ; C25M ; -; SD[0] ; C25M ; 8.282 ; ; Rise ; C25M ; -; SD[1] ; C25M ; 8.282 ; ; Rise ; C25M ; -; SD[2] ; C25M ; 8.282 ; ; Rise ; C25M ; -; SD[3] ; C25M ; 8.282 ; ; Rise ; C25M ; -; SD[4] ; C25M ; 8.282 ; ; Rise ; C25M ; -; SD[5] ; C25M ; 8.282 ; ; Rise ; C25M ; -; SD[6] ; C25M ; 7.768 ; ; Rise ; C25M ; -; SD[7] ; C25M ; 7.768 ; ; Rise ; C25M ; +; MOSI ; C25M ; 8.354 ; ; Rise ; C25M ; +; SD[*] ; C25M ; 6.777 ; ; Rise ; C25M ; +; SD[0] ; C25M ; 7.423 ; ; Rise ; C25M ; +; SD[1] ; C25M ; 6.983 ; ; Rise ; C25M ; +; SD[2] ; C25M ; 6.983 ; ; Rise ; C25M ; +; SD[3] ; C25M ; 7.423 ; ; Rise ; C25M ; +; SD[4] ; C25M ; 6.983 ; ; Rise ; C25M ; +; SD[5] ; C25M ; 6.983 ; ; Rise ; C25M ; +; SD[6] ; C25M ; 6.777 ; ; Rise ; C25M ; +; SD[7] ; C25M ; 6.777 ; ; Rise ; C25M ; +-----------+------------+-------+------+------------+-----------------+ @@ -728,16 +856,16 @@ No paths to report. +-----------+------------+-----------+-----------+------------+-----------------+ ; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; +-----------+------------+-----------+-----------+------------+-----------------+ -; MOSI ; C25M ; 6.350 ; ; Rise ; C25M ; -; SD[*] ; C25M ; 7.768 ; ; Rise ; C25M ; -; SD[0] ; C25M ; 8.282 ; ; Rise ; C25M ; -; SD[1] ; C25M ; 8.282 ; ; Rise ; C25M ; -; SD[2] ; C25M ; 8.282 ; ; Rise ; C25M ; -; SD[3] ; C25M ; 8.282 ; ; Rise ; C25M ; -; SD[4] ; C25M ; 8.282 ; ; Rise ; C25M ; -; SD[5] ; C25M ; 8.282 ; ; Rise ; C25M ; -; SD[6] ; C25M ; 7.768 ; ; Rise ; C25M ; -; SD[7] ; C25M ; 7.768 ; ; Rise ; C25M ; +; MOSI ; C25M ; 8.354 ; ; Rise ; C25M ; +; SD[*] ; C25M ; 6.777 ; ; Rise ; C25M ; +; SD[0] ; C25M ; 7.423 ; ; Rise ; C25M ; +; SD[1] ; C25M ; 6.983 ; ; Rise ; C25M ; +; SD[2] ; C25M ; 6.983 ; ; Rise ; C25M ; +; SD[3] ; C25M ; 7.423 ; ; Rise ; C25M ; +; SD[4] ; C25M ; 6.983 ; ; Rise ; C25M ; +; SD[5] ; C25M ; 6.983 ; ; Rise ; C25M ; +; SD[6] ; C25M ; 6.777 ; ; Rise ; C25M ; +; SD[7] ; C25M ; 6.777 ; ; Rise ; C25M ; +-----------+------------+-----------+-----------+------------+-----------------+ @@ -746,16 +874,16 @@ No paths to report. +-----------+------------+-----------+-----------+------------+-----------------+ ; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; +-----------+------------+-----------+-----------+------------+-----------------+ -; MOSI ; C25M ; 6.350 ; ; Rise ; C25M ; -; SD[*] ; C25M ; 7.768 ; ; Rise ; C25M ; -; SD[0] ; C25M ; 8.282 ; ; Rise ; C25M ; -; SD[1] ; C25M ; 8.282 ; ; Rise ; C25M ; -; SD[2] ; C25M ; 8.282 ; ; Rise ; C25M ; -; SD[3] ; C25M ; 8.282 ; ; Rise ; C25M ; -; SD[4] ; C25M ; 8.282 ; ; Rise ; C25M ; -; SD[5] ; C25M ; 8.282 ; ; Rise ; C25M ; -; SD[6] ; C25M ; 7.768 ; ; Rise ; C25M ; -; SD[7] ; C25M ; 7.768 ; ; Rise ; C25M ; +; MOSI ; C25M ; 8.354 ; ; Rise ; C25M ; +; SD[*] ; C25M ; 6.777 ; ; Rise ; C25M ; +; SD[0] ; C25M ; 7.423 ; ; Rise ; C25M ; +; SD[1] ; C25M ; 6.983 ; ; Rise ; C25M ; +; SD[2] ; C25M ; 6.983 ; ; Rise ; C25M ; +; SD[3] ; C25M ; 7.423 ; ; Rise ; C25M ; +; SD[4] ; C25M ; 6.983 ; ; Rise ; C25M ; +; SD[5] ; C25M ; 6.983 ; ; Rise ; C25M ; +; SD[6] ; C25M ; 6.777 ; ; Rise ; C25M ; +; SD[7] ; C25M ; 6.777 ; ; Rise ; C25M ; +-----------+------------+-----------+-----------+------------+-----------------+ @@ -767,7 +895,7 @@ No paths to report. ; ARCLK ; ARCLK ; 1 ; 0 ; 0 ; 0 ; ; C25M ; ARCLK ; 1 ; 0 ; 0 ; 0 ; ; ARCLK ; C25M ; 1 ; 1 ; 0 ; 0 ; -; C25M ; C25M ; 1370 ; 2 ; 0 ; 0 ; +; C25M ; C25M ; 1653 ; 6 ; 0 ; 0 ; ; DRCLK ; C25M ; 3 ; 0 ; 0 ; 0 ; ; C25M ; DRCLK ; 1 ; 0 ; 0 ; 0 ; ; DRCLK ; DRCLK ; 1 ; 0 ; 0 ; 0 ; @@ -783,7 +911,7 @@ Entries labeled "false path" only account for clock-to-clock false paths and not ; ARCLK ; ARCLK ; 1 ; 0 ; 0 ; 0 ; ; C25M ; ARCLK ; 1 ; 0 ; 0 ; 0 ; ; ARCLK ; C25M ; 1 ; 1 ; 0 ; 0 ; -; C25M ; C25M ; 1370 ; 2 ; 0 ; 0 ; +; C25M ; C25M ; 1653 ; 6 ; 0 ; 0 ; ; DRCLK ; C25M ; 3 ; 0 ; 0 ; 0 ; ; C25M ; DRCLK ; 1 ; 0 ; 0 ; 0 ; ; DRCLK ; DRCLK ; 1 ; 0 ; 0 ; 0 ; @@ -810,10 +938,10 @@ No dedicated SERDES Receiver circuitry present in device or used in design +---------------------------------+-------+------+ ; Illegal Clocks ; 0 ; 0 ; ; Unconstrained Clocks ; 0 ; 0 ; -; Unconstrained Input Ports ; 28 ; 28 ; -; Unconstrained Input Port Paths ; 28 ; 28 ; -; Unconstrained Output Ports ; 14 ; 14 ; -; Unconstrained Output Port Paths ; 23 ; 23 ; +; Unconstrained Input Ports ; 32 ; 32 ; +; Unconstrained Input Port Paths ; 77 ; 77 ; +; Unconstrained Output Ports ; 26 ; 26 ; +; Unconstrained Output Port Paths ; 107 ; 107 ; +---------------------------------+-------+------+ @@ -823,7 +951,7 @@ No dedicated SERDES Receiver circuitry present in device or used in design Info: ******************************************************************* Info: Running Quartus II 32-bit TimeQuest Timing Analyzer Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - Info: Processing started: Thu Mar 18 04:40:54 2021 + Info: Processing started: Fri Mar 19 05:28:56 2021 Info: Command: quartus_sta GR8RAM -c GR8RAM Info: qsta_default_script.tcl version: #1 Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected @@ -844,13 +972,13 @@ Info (332146): Worst-case setup slack is -99.000 Info (332119): ========= ============= ===================== Info (332119): -99.000 -99.000 ARCLK Info (332119): -99.000 -99.000 DRCLK - Info (332119): -8.447 -415.877 C25M -Info (332146): Worst-case hold slack is -16.286 + Info (332119): -9.598 -485.527 C25M +Info (332146): Worst-case hold slack is -16.296 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== - Info (332119): -16.286 -16.286 DRCLK - Info (332119): -16.276 -16.276 ARCLK - Info (332119): -1.579 -1.579 C25M + Info (332119): -16.296 -16.296 ARCLK + Info (332119): -16.276 -16.276 DRCLK + Info (332119): -1.031 -1.031 C25M Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332146): Worst-case minimum pulse width slack is -29.500 @@ -863,8 +991,8 @@ Info (332001): The selected device family is not supported by the report_metasta Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings - Info: Peak virtual memory: 286 megabytes - Info: Processing ended: Thu Mar 18 04:40:58 2021 + Info: Peak virtual memory: 275 megabytes + Info: Processing ended: Fri Mar 19 05:29:00 2021 Info: Elapsed time: 00:00:04 Info: Total CPU time (on all processors): 00:00:04 diff --git a/cpld/output_files/GR8RAM.sta.summary b/cpld/output_files/GR8RAM.sta.summary index 1711c4c..1161093 100755 --- a/cpld/output_files/GR8RAM.sta.summary +++ b/cpld/output_files/GR8RAM.sta.summary @@ -11,20 +11,20 @@ Slack : -99.000 TNS : -99.000 Type : Setup 'C25M' -Slack : -8.447 -TNS : -415.877 - -Type : Hold 'DRCLK' -Slack : -16.286 -TNS : -16.286 +Slack : -9.598 +TNS : -485.527 Type : Hold 'ARCLK' +Slack : -16.296 +TNS : -16.296 + +Type : Hold 'DRCLK' Slack : -16.276 TNS : -16.276 Type : Hold 'C25M' -Slack : -1.579 -TNS : -1.579 +Slack : -1.031 +TNS : -1.031 Type : Minimum Pulse Width 'ARCLK' Slack : -29.500