diff --git a/cpld/GR8RAM.dpf b/cpld/GR8RAM.dpf
deleted file mode 100755
index 27594d0..0000000
--- a/cpld/GR8RAM.dpf
+++ /dev/null
@@ -1,20 +0,0 @@
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/cpld/GR8RAM.qsf b/cpld/GR8RAM.qsf
index 7c201ce..40fd6d4 100755
--- a/cpld/GR8RAM.qsf
+++ b/cpld/GR8RAM.qsf
@@ -84,7 +84,6 @@ set_location_assignment PIN_12 -to FCK
set_location_assignment PIN_14 -to RA[10]
set_location_assignment PIN_15 -to MOSI
set_location_assignment PIN_16 -to MISO
-set_location_assignment PIN_17 -to Ddir
set_location_assignment PIN_30 -to nRESout
set_location_assignment PIN_34 -to RA[11]
set_location_assignment PIN_35 -to RA[12]
@@ -142,4 +141,24 @@ set_location_assignment PIN_98 -to RA[1]
set_location_assignment PIN_96 -to SetFW[0]
set_location_assignment PIN_95 -to SetFW[1]
set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 1
-set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 2
\ No newline at end of file
+set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 2
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nFCS
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nFCS
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to FCK
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to FCK
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to MOSI
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to MOSI
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to MISO
+set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to MISO
+set_location_assignment PIN_21 -to nDMAout
+set_location_assignment PIN_19 -to RAdir
+set_location_assignment PIN_20 -to INTout
+set_location_assignment PIN_26 -to nNMIout
+set_location_assignment PIN_27 -to nINHout
+set_location_assignment PIN_28 -to nRDYout
+set_location_assignment PIN_29 -to nIRQout
+set_location_assignment PIN_33 -to RWout
+set_location_assignment PIN_48 -to DMAin
+set_location_assignment PIN_49 -to INTin
+set_location_assignment PIN_17 -to RDdir
+set_location_assignment PIN_18 -to DMAout
\ No newline at end of file
diff --git a/cpld/GR8RAM.v b/cpld/GR8RAM.v
index bc85a37..ca473b4 100644
--- a/cpld/GR8RAM.v
+++ b/cpld/GR8RAM.v
@@ -1,6 +1,7 @@
-module GR8RAM(C25M, PHI0, nRES, nRESout,
+module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
+ RAdir, INTin, INTout, DMAin, DMAout, nDMAout,
+ nNMIout, nIRQout, nRDYout, nINHout, RWout,
nIOSEL, nDEVSEL, nIOSTRB,
- SetFW,
RA, nWE, RD, RDdir,
SBA, SA, nRCS, nRAS, nCAS, nSWE, DQML, DQMH, RCKE, SD,
nFCS, FCK, MISO, MOSI);
@@ -9,7 +10,20 @@ module GR8RAM(C25M, PHI0, nRES, nRESout,
input C25M, PHI0;
reg PHI0r1, PHI0r2;
always @(posedge C25M) begin PHI0r1 <= PHI0; PHI0r2 <= PHI0r1; end
-
+
+ /* Unused Pins */
+ output RAdir = 1;
+ input INTin;
+ output INTout = INTin;
+ input DMAin;
+ output DMAout = DMAin;
+ output nDMAout = 1;
+ output nNMIout = 1;
+ output nINHout = 1;
+ output nRDYout = 1;
+ output nIRQout = 1;
+ output RWout = 1;
+
/* Reset/brown-out detect synchronized inputs */
input nRES;
reg nRESr0, nRESr;
@@ -130,51 +144,54 @@ module GR8RAM(C25M, PHI0, nRES, nRESout,
end
/* SPI flash */
- output nFCS = ~FCS;
+ output nFCS = FCKOE ? ~FCS : 1'bZ;
reg FCS = 0;
- output reg FCK = 0;
+ output FCK = FCKOE ? FCKout : 1'bZ;
+ reg FCKOE = 0;
+ reg FCKout = 0;
inout MOSI = MOSIOE ? MOSIout : 1'bZ;
reg MOSIOE = 0;
- reg MOSIout;
+ reg MOSIout = 0;
input MISO;
always @(posedge C25M) begin
case (PS[3:0])
0: begin // NOP CKE
- FCK <= 1'b1;
+ FCKout <= 1'b1;
end 1: begin // ACT
- FCK <= ~(IS==5 || IS==6);
+ FCKout <= ~(IS==5 || IS==6);
end 2: begin // RD
- FCK <= 1'b1;
+ FCKout <= 1'b1;
end 3: begin // NOP CKE
- FCK <= ~(IS==5 || IS==6);
+ FCKout <= ~(IS==5 || IS==6);
end 4: begin // NOP CKE
- FCK <= 1'b1;
+ FCKout <= 1'b1;
end 5: begin // NOP CKE
- FCK <= ~(IS==5 || IS==6);
+ FCKout <= ~(IS==5 || IS==6);
end 6: begin // NOP CKE
- FCK <= 1'b1;
+ FCKout <= 1'b1;
end 7: begin // NOP CKE
- FCK <= ~(IS==5 || IS==6);
+ FCKout <= ~(IS==5 || IS==6);
end 8: begin // WR AP
- FCK <= 1'b1;
+ FCKout <= 1'b1;
end 9: begin // NOP CKE
- FCK <= ~(IS==5);
+ FCKout <= ~(IS==5);
end 10: begin // PC all
- FCK <= 1'b1;
+ FCKout <= 1'b1;
end 11: begin // AREF
- FCK <= ~(IS==5);
+ FCKout <= ~(IS==5);
end 12: begin // NOP CKE
- FCK <= 1'b1;
+ FCKout <= 1'b1;
end 13: begin // NOP CKE
- FCK <= ~(IS==5);
+ FCKout <= ~(IS==5);
end 14: begin // NOP CKE
- FCK <= 1'b1;
+ FCKout <= 1'b1;
end 15: begin // NOP CKE
- FCK <= ~(IS==5);
+ FCKout <= ~(IS==5);
end
endcase
FCS <= IS==4 || IS==5 || IS==6;
MOSIOE <= IS==5;
+ FCKOE <= IS==1 || IS==2 || IS==3 || IS==4 || IS==5 || IS==6 || IS==7;
end
always @(posedge C25M) begin
@@ -461,7 +478,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout,
end
end 2: begin // RD
if (RAMSpecSELr) begin
- SBA[1:0] <= { 1'b0, Addr[23] && SetRF };
+ SBA[1:0] <= { 1'b0, Addr[23] && SetLim8M && SetRF };
SA[12:0] <= { 4'b0011, Addr[9:1] };
DQML <= Addr[0];
DQMH <= ~Addr[0];
diff --git a/cpld/db/GR8RAM.(0).cnf.cdb b/cpld/db/GR8RAM.(0).cnf.cdb
index 0a718ca..8a01751 100755
Binary files a/cpld/db/GR8RAM.(0).cnf.cdb and b/cpld/db/GR8RAM.(0).cnf.cdb differ
diff --git a/cpld/db/GR8RAM.(0).cnf.hdb b/cpld/db/GR8RAM.(0).cnf.hdb
index f0e8200..b6aa653 100755
Binary files a/cpld/db/GR8RAM.(0).cnf.hdb and b/cpld/db/GR8RAM.(0).cnf.hdb differ
diff --git a/cpld/db/GR8RAM.asm.qmsg b/cpld/db/GR8RAM.asm.qmsg
index 18ac215..86a292a 100755
--- a/cpld/db/GR8RAM.asm.qmsg
+++ b/cpld/db/GR8RAM.asm.qmsg
@@ -1,6 +1,6 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618161759471 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618161759502 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 11 13:22:38 2021 " "Processing started: Sun Apr 11 13:22:38 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618161759502 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1618161759502 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1618161759502 ""}
-{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1618161760940 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1618161760971 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "293 " "Peak virtual memory: 293 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618161761456 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 11 13:22:41 2021 " "Processing ended: Sun Apr 11 13:22:41 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618161761456 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618161761456 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618161761456 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1618161761456 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618731925004 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618731925004 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 18 03:45:24 2021 " "Processing started: Sun Apr 18 03:45:24 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618731925004 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1618731925004 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1618731925004 ""}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1618731925194 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1618731925204 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "381 " "Peak virtual memory: 381 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618731925334 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 18 03:45:25 2021 " "Processing ended: Sun Apr 18 03:45:25 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618731925334 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618731925334 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618731925334 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1618731925334 ""}
diff --git a/cpld/db/GR8RAM.asm.rdb b/cpld/db/GR8RAM.asm.rdb
index 2abb38b..e0520d4 100755
Binary files a/cpld/db/GR8RAM.asm.rdb and b/cpld/db/GR8RAM.asm.rdb differ
diff --git a/cpld/db/GR8RAM.asm_labs.ddb b/cpld/db/GR8RAM.asm_labs.ddb
index bf60bb4..446edbc 100755
Binary files a/cpld/db/GR8RAM.asm_labs.ddb and b/cpld/db/GR8RAM.asm_labs.ddb differ
diff --git a/cpld/db/GR8RAM.cmp.cdb b/cpld/db/GR8RAM.cmp.cdb
index 71781ab..ff3967e 100755
Binary files a/cpld/db/GR8RAM.cmp.cdb and b/cpld/db/GR8RAM.cmp.cdb differ
diff --git a/cpld/db/GR8RAM.cmp.hdb b/cpld/db/GR8RAM.cmp.hdb
index 57e6a85..d5623f7 100755
Binary files a/cpld/db/GR8RAM.cmp.hdb and b/cpld/db/GR8RAM.cmp.hdb differ
diff --git a/cpld/db/GR8RAM.cmp.idb b/cpld/db/GR8RAM.cmp.idb
index 2c31788..1b41e0f 100755
Binary files a/cpld/db/GR8RAM.cmp.idb and b/cpld/db/GR8RAM.cmp.idb differ
diff --git a/cpld/db/GR8RAM.cmp.kpt b/cpld/db/GR8RAM.cmp.kpt
index 9603332..2f27ca1 100755
Binary files a/cpld/db/GR8RAM.cmp.kpt and b/cpld/db/GR8RAM.cmp.kpt differ
diff --git a/cpld/db/GR8RAM.cmp.rdb b/cpld/db/GR8RAM.cmp.rdb
index e0838e0..4ec2617 100755
Binary files a/cpld/db/GR8RAM.cmp.rdb and b/cpld/db/GR8RAM.cmp.rdb differ
diff --git a/cpld/db/GR8RAM.cmp0.ddb b/cpld/db/GR8RAM.cmp0.ddb
index 3cd5192..65b0bfc 100755
Binary files a/cpld/db/GR8RAM.cmp0.ddb and b/cpld/db/GR8RAM.cmp0.ddb differ
diff --git a/cpld/db/GR8RAM.db_info b/cpld/db/GR8RAM.db_info
index 9de02fe..d0885e9 100755
--- a/cpld/db/GR8RAM.db_info
+++ b/cpld/db/GR8RAM.db_info
@@ -1,3 +1,3 @@
Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Version_Index = 302049280
-Creation_Time = Sun Apr 11 00:06:29 2021
+Creation_Time = Sun Apr 18 03:04:53 2021
diff --git a/cpld/db/GR8RAM.fit.qmsg b/cpld/db/GR8RAM.fit.qmsg
index 2b53173..d19197a 100755
--- a/cpld/db/GR8RAM.fit.qmsg
+++ b/cpld/db/GR8RAM.fit.qmsg
@@ -1,44 +1,39 @@
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1618161749377 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1618161749440 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618161749627 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618161749627 ""}
-{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1618161750455 ""}
-{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1618161750486 ""}
-{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618161750955 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618161750955 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618161750955 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618161750955 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618161750955 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1618161750955 ""}
-{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "1 69 " "No exact pin location assignment(s) for 1 pins of 69 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RDdir " "Pin RDdir not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RDdir } } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 82 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RDdir } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 356 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1618161750971 ""} } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1618161750971 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1618161751096 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1618161751096 ""}
-{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1618161751111 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1618161751111 ""}
-{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618161751111 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618161751111 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 C25M " " 1.000 C25M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618161751111 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI0 " " 1.000 PHI0" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618161751111 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1618161751111 ""}
-{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618161751127 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618161751127 ""}
-{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618161751143 ""}
-{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618161751205 ""}
-{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI0 Global clock " "Automatically promoted some destinations of signal \"PHI0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~1 " "Destination \"comb~1\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618161751205 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI0r1 " "Destination \"PHI0r1\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618161751205 ""} } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618161751205 ""}
-{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI0 " "Pin \"PHI0\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI0 } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "PHI0" } } } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 350 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1618161751205 ""}
-{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "nRESr Global clock " "Automatically promoted signal \"nRESr\" to use Global clock" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 15 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618161751205 ""}
-{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618161751205 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1618161751221 ""}
-{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1618161751252 ""}
-{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1618161751377 ""}
-{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1618161751393 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1618161751393 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1618161751393 ""}
-{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "1 unused 3.3V 0 1 0 " "Number of I/O pins in group: 1 (unused VREF, 3.3V VCCIO, 0 input, 1 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "I/O standards used: 3.3-V LVTTL." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1618161751408 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1618161751408 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1618161751408 ""}
-{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.3V 26 12 " "I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 26 total pin(s) used -- 12 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1618161751424 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use 3.3V 42 0 " "I/O bank number 2 does not use VREF pins and has 3.3V VCCIO pins. 42 total pin(s) used -- 0 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1618161751424 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1618161751424 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1618161751424 ""}
-{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "Ddir " "Node \"Ddir\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "Ddir" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1618161751455 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1618161751455 ""}
-{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618161751455 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1618161751674 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618161752080 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1618161752111 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1618161753690 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:02 " "Fitter placement operations ending: elapsed time is 00:00:02" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618161753690 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1618161753752 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "32 " "Router estimated average interconnect usage is 32% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "32 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 32% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 32% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 32% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1618161754096 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1618161754096 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618161754737 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.53 " "Total time spent on timing analysis during the Fitter is 0.53 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1618161754737 ""}
-{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618161754752 ""}
-{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1618161754768 ""}
-{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1618161754768 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1618161754893 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 7 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "382 " "Peak virtual memory: 382 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618161755065 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 11 13:22:35 2021 " "Processing ended: Sun Apr 11 13:22:35 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618161755065 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618161755065 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:09 " "Total CPU time (on all processors): 00:00:09" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618161755065 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1618161755065 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1618731921844 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1618731921844 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618731921884 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618731921884 ""}
+{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1618731921934 ""}
+{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1618731921944 ""}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618731922034 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618731922034 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618731922034 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618731922034 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618731922034 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1618731922034 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1618731922114 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1618731922114 ""}
+{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1618731922114 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1618731922114 ""}
+{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618731922114 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618731922114 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 C25M " " 1.000 C25M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618731922114 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI0 " " 1.000 PHI0" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618731922114 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1618731922114 ""}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618731922124 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618731922124 ""}
+{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618731922124 ""}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618731922134 ""}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI0 Global clock " "Automatically promoted some destinations of signal \"PHI0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~1 " "Destination \"comb~1\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618731922134 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI0r1 " "Destination \"PHI0r1\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 11 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618731922134 ""} } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618731922134 ""}
+{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI0 " "Pin \"PHI0\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { PHI0 } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PHI0" } } } } { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { PHI0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/" { { 0 { 0 ""} 0 369 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1618731922134 ""}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "nRESr Global clock " "Automatically promoted signal \"nRESr\" to use Global clock" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 29 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618731922134 ""}
+{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618731922134 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1618731922134 ""}
+{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1618731922144 ""}
+{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1618731922174 ""}
+{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1618731922174 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1618731922174 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1618731922174 ""}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618731922224 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1618731922294 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618731922514 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1618731922524 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1618731923074 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618731923074 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1618731923104 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "34 " "Router estimated average interconnect usage is 34% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "34 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1618731923314 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1618731923314 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618731924004 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.27 " "Total time spent on timing analysis during the Fitter is 0.27 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1618731924014 ""}
+{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618731924014 ""}
+{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1618731924054 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1618731924104 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "547 " "Peak virtual memory: 547 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618731924124 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 18 03:45:24 2021 " "Processing ended: Sun Apr 18 03:45:24 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618731924124 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618731924124 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618731924124 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1618731924124 ""}
diff --git a/cpld/db/GR8RAM.hier_info b/cpld/db/GR8RAM.hier_info
index 9b744c9..5435e9b 100755
--- a/cpld/db/GR8RAM.hier_info
+++ b/cpld/db/GR8RAM.hier_info
@@ -43,9 +43,10 @@ C25M => WRD[5].CLK
C25M => WRD[6].CLK
C25M => WRD[7].CLK
C25M => MOSIout.CLK
+C25M => FCKOE.CLK
C25M => MOSIOE.CLK
C25M => FCS.CLK
-C25M => FCK~reg0.CLK
+C25M => FCKout.CLK
C25M => Bank.CLK
C25M => AddrIncH.CLK
C25M => AddrIncM.CLK
@@ -95,7 +96,7 @@ C25M => nRESr.CLK
C25M => nRESr0.CLK
C25M => PHI0r2.CLK
C25M => PHI0r1.CLK
-C25M => IS~7.DATAIN
+C25M => IS~9.DATAIN
PHI0 => comb.IN1
PHI0 => nWEr.CLK
PHI0 => RAMSpecSELr.CLK
@@ -103,13 +104,6 @@ PHI0 => ROMSpecSELr.CLK
PHI0 => PHI0r1.DATAIN
nRES => nRESr0.DATAIN
nRESout <= nRESout~reg0.DB_MAX_OUTPUT_PORT_TYPE
-nIOSEL => comb.IN0
-nIOSEL => always5.IN1
-nDEVSEL => comb.IN1
-nDEVSEL => RAMSEL.IN1
-nDEVSEL => comb.IN1
-nIOSTRB => comb.IN1
-nIOSTRB => always5.IN1
SetFW[0] => Mux1.IN10
SetFW[0] => Equal18.IN1
SetFW[0] => Equal19.IN1
@@ -117,33 +111,51 @@ SetFW[1] => MOSIout.DATAB
SetFW[1] => comb.IN1
SetFW[1] => Equal18.IN0
SetFW[1] => Equal19.IN0
+RAdir <=
+INTin => INTout.DATAIN
+INTout <= INTin.DB_MAX_OUTPUT_PORT_TYPE
+DMAin => DMAout.DATAIN
+DMAout <= DMAin.DB_MAX_OUTPUT_PORT_TYPE
+nDMAout <=
+nNMIout <=
+nIRQout <=
+nRDYout <=
+nINHout <=
+RWout <=
+nIOSEL => comb.IN0
+nIOSEL => always5.IN1
+nDEVSEL => comb.IN1
+nDEVSEL => RAMSEL.IN1
+nDEVSEL => comb.IN1
+nIOSTRB => comb.IN1
+nIOSTRB => always5.IN1
RA[0] => DQML.DATAA
RA[0] => Equal6.IN3
-RA[0] => Equal9.IN1
-RA[0] => Equal11.IN3
-RA[0] => Equal12.IN0
+RA[0] => Equal9.IN3
+RA[0] => Equal11.IN2
+RA[0] => Equal12.IN3
RA[0] => Equal13.IN3
RA[0] => Equal14.IN10
RA[0] => DQMH.DATAA
RA[1] => SA.DATAA
RA[1] => Equal6.IN2
-RA[1] => Equal9.IN0
-RA[1] => Equal11.IN0
-RA[1] => Equal12.IN3
+RA[1] => Equal9.IN2
+RA[1] => Equal11.IN3
+RA[1] => Equal12.IN2
RA[1] => Equal13.IN2
RA[1] => Equal14.IN9
RA[2] => SA.DATAA
RA[2] => Equal6.IN1
-RA[2] => Equal9.IN3
-RA[2] => Equal11.IN2
-RA[2] => Equal12.IN2
+RA[2] => Equal9.IN1
+RA[2] => Equal11.IN1
+RA[2] => Equal12.IN1
RA[2] => Equal13.IN1
RA[2] => Equal14.IN8
RA[3] => SA.DATAA
RA[3] => Equal6.IN0
-RA[3] => Equal9.IN2
-RA[3] => Equal11.IN1
-RA[3] => Equal12.IN1
+RA[3] => Equal9.IN0
+RA[3] => Equal11.IN0
+RA[3] => Equal12.IN0
RA[3] => Equal13.IN0
RA[3] => Equal14.IN7
RA[4] => SA.DATAA
@@ -166,10 +178,10 @@ RA[10] => Equal8.IN1
RA[10] => Equal14.IN0
RA[11] => SA.DATAA
RA[11] => Equal8.IN0
-RA[12] => Equal7.IN3
-RA[13] => Equal7.IN2
-RA[14] => Equal7.IN1
-RA[15] => Equal7.IN0
+RA[12] => Equal7.IN1
+RA[13] => Equal7.IN0
+RA[14] => Equal7.IN3
+RA[15] => Equal7.IN2
nWE => comb.IN1
nWE => nWEr.DATAIN
RD[0] <> RD[0]
@@ -211,8 +223,8 @@ SD[4] <> SD[4]
SD[5] <> SD[5]
SD[6] <> SD[6]
SD[7] <> SD[7]
-nFCS <= FCS.DB_MAX_OUTPUT_PORT_TYPE
-FCK <= FCK~reg0.DB_MAX_OUTPUT_PORT_TYPE
+nFCS <= nFCS.DB_MAX_OUTPUT_PORT_TYPE
+FCK <= FCK.DB_MAX_OUTPUT_PORT_TYPE
MISO => WRD.DATAB
MOSI <> MOSI
diff --git a/cpld/db/GR8RAM.hif b/cpld/db/GR8RAM.hif
index bb1c2ba..916cc63 100755
Binary files a/cpld/db/GR8RAM.hif and b/cpld/db/GR8RAM.hif differ
diff --git a/cpld/db/GR8RAM.ipinfo b/cpld/db/GR8RAM.ipinfo
index 6ff9cf3..fa2304d 100755
Binary files a/cpld/db/GR8RAM.ipinfo and b/cpld/db/GR8RAM.ipinfo differ
diff --git a/cpld/db/GR8RAM.lpc.rdb b/cpld/db/GR8RAM.lpc.rdb
index f46ce48..adf8589 100755
Binary files a/cpld/db/GR8RAM.lpc.rdb and b/cpld/db/GR8RAM.lpc.rdb differ
diff --git a/cpld/db/GR8RAM.map.cdb b/cpld/db/GR8RAM.map.cdb
index c2e4bbf..b9e18f1 100755
Binary files a/cpld/db/GR8RAM.map.cdb and b/cpld/db/GR8RAM.map.cdb differ
diff --git a/cpld/db/GR8RAM.map.hdb b/cpld/db/GR8RAM.map.hdb
index d3dead2..de841a8 100755
Binary files a/cpld/db/GR8RAM.map.hdb and b/cpld/db/GR8RAM.map.hdb differ
diff --git a/cpld/db/GR8RAM.map.qmsg b/cpld/db/GR8RAM.map.qmsg
index f411e2a..965736d 100755
--- a/cpld/db/GR8RAM.map.qmsg
+++ b/cpld/db/GR8RAM.map.qmsg
@@ -1,18 +1,19 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618161736158 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618161736158 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 11 13:22:15 2021 " "Processing started: Sun Apr 11 13:22:15 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618161736158 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618161736158 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618161736158 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1618161737908 ""}
-{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(79) " "Verilog HDL warning at GR8RAM.v(79): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 79 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618161738205 ""}
-{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(256) " "Verilog HDL warning at GR8RAM.v(256): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 256 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618161738205 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1618161738205 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1618161738205 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1618161738314 ""}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(20) " "Verilog HDL assignment warning at GR8RAM.v(20): truncated value with size 32 to match size of target (14)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 20 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618161738314 "|GR8RAM"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(103) " "Verilog HDL assignment warning at GR8RAM.v(103): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 103 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618161738314 "|GR8RAM"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(111) " "Verilog HDL assignment warning at GR8RAM.v(111): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 111 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618161738314 "|GR8RAM"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(118) " "Verilog HDL assignment warning at GR8RAM.v(118): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 118 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618161738314 "|GR8RAM"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(307) " "Verilog HDL assignment warning at GR8RAM.v(307): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 307 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618161738330 "|GR8RAM"}
-{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 -1 1618161740127 ""}
-{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1618161740877 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "309 " "Implemented 309 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "26 " "Implemented 26 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1618161740986 ""} { "Info" "ICUT_CUT_TM_OPINS" "26 " "Implemented 26 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1618161740986 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1618161740986 ""} { "Info" "ICUT_CUT_TM_LCELLS" "240 " "Implemented 240 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1618161740986 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1618161740986 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1618161741470 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "301 " "Peak virtual memory: 301 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618161741799 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 11 13:22:21 2021 " "Processing ended: Sun Apr 11 13:22:21 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618161741799 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618161741799 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618161741799 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618161741799 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618731919693 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618731919693 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 18 03:45:19 2021 " "Processing started: Sun Apr 18 03:45:19 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618731919693 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618731919693 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618731919693 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1618731919933 ""}
+{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(93) " "Verilog HDL warning at GR8RAM.v(93): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 93 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618731919973 ""}
+{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(273) " "Verilog HDL warning at GR8RAM.v(273): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 273 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618731919973 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1618731919983 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1618731919983 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1618731920003 ""}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(34) " "Verilog HDL assignment warning at GR8RAM.v(34): truncated value with size 32 to match size of target (14)" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 34 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618731920003 "|GR8RAM"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(117) " "Verilog HDL assignment warning at GR8RAM.v(117): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 117 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618731920003 "|GR8RAM"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(125) " "Verilog HDL assignment warning at GR8RAM.v(125): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 125 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618731920003 "|GR8RAM"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(132) " "Verilog HDL assignment warning at GR8RAM.v(132): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 132 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618731920003 "|GR8RAM"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(324) " "Verilog HDL assignment warning at GR8RAM.v(324): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 324 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618731920013 "|GR8RAM"}
+{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 -1 1618731920343 ""}
+{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 15 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618731920483 "|GR8RAM|RAdir"} { "Warning" "WMLS_MLS_STUCK_PIN" "nDMAout VCC " "Pin \"nDMAout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 20 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618731920483 "|GR8RAM|nDMAout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nNMIout VCC " "Pin \"nNMIout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 21 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618731920483 "|GR8RAM|nNMIout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nIRQout VCC " "Pin \"nIRQout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 24 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618731920483 "|GR8RAM|nIRQout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nRDYout VCC " "Pin \"nRDYout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618731920483 "|GR8RAM|nRDYout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nINHout VCC " "Pin \"nINHout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 22 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618731920483 "|GR8RAM|nINHout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RWout VCC " "Pin \"RWout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618731920483 "|GR8RAM|RWout"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1618731920483 ""}
+{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1618731920733 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "322 " "Implemented 322 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "28 " "Implemented 28 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1618731920743 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1618731920743 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1618731920743 ""} { "Info" "ICUT_CUT_TM_LCELLS" "242 " "Implemented 242 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1618731920743 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1618731920743 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1618731920773 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 14 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 14 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "421 " "Peak virtual memory: 421 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618731920783 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 18 03:45:20 2021 " "Processing ended: Sun Apr 18 03:45:20 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618731920783 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618731920783 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618731920783 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618731920783 ""}
diff --git a/cpld/db/GR8RAM.map.rdb b/cpld/db/GR8RAM.map.rdb
index bc998e6..90b3b8b 100755
Binary files a/cpld/db/GR8RAM.map.rdb and b/cpld/db/GR8RAM.map.rdb differ
diff --git a/cpld/db/GR8RAM.pplq.rdb b/cpld/db/GR8RAM.pplq.rdb
index 6619eee..723fcab 100755
Binary files a/cpld/db/GR8RAM.pplq.rdb and b/cpld/db/GR8RAM.pplq.rdb differ
diff --git a/cpld/db/GR8RAM.pre_map.hdb b/cpld/db/GR8RAM.pre_map.hdb
index ccb0585..ee4aba8 100755
Binary files a/cpld/db/GR8RAM.pre_map.hdb and b/cpld/db/GR8RAM.pre_map.hdb differ
diff --git a/cpld/db/GR8RAM.pti_db_list.ddb b/cpld/db/GR8RAM.pti_db_list.ddb
index 61ca8da..89aa9b4 100755
Binary files a/cpld/db/GR8RAM.pti_db_list.ddb and b/cpld/db/GR8RAM.pti_db_list.ddb differ
diff --git a/cpld/db/GR8RAM.root_partition.map.reg_db.cdb b/cpld/db/GR8RAM.root_partition.map.reg_db.cdb
index 8ea0c5f..5a362d9 100755
Binary files a/cpld/db/GR8RAM.root_partition.map.reg_db.cdb and b/cpld/db/GR8RAM.root_partition.map.reg_db.cdb differ
diff --git a/cpld/db/GR8RAM.routing.rdb b/cpld/db/GR8RAM.routing.rdb
index 66f799f..24be5cf 100755
Binary files a/cpld/db/GR8RAM.routing.rdb and b/cpld/db/GR8RAM.routing.rdb differ
diff --git a/cpld/db/GR8RAM.rtlv.hdb b/cpld/db/GR8RAM.rtlv.hdb
index c4816f4..57571df 100755
Binary files a/cpld/db/GR8RAM.rtlv.hdb and b/cpld/db/GR8RAM.rtlv.hdb differ
diff --git a/cpld/db/GR8RAM.rtlv_sg.cdb b/cpld/db/GR8RAM.rtlv_sg.cdb
index bb29d9b..7795cd5 100755
Binary files a/cpld/db/GR8RAM.rtlv_sg.cdb and b/cpld/db/GR8RAM.rtlv_sg.cdb differ
diff --git a/cpld/db/GR8RAM.rtlv_sg_swap.cdb b/cpld/db/GR8RAM.rtlv_sg_swap.cdb
index e6e4232..bf4c983 100755
Binary files a/cpld/db/GR8RAM.rtlv_sg_swap.cdb and b/cpld/db/GR8RAM.rtlv_sg_swap.cdb differ
diff --git a/cpld/db/GR8RAM.sgdiff.cdb b/cpld/db/GR8RAM.sgdiff.cdb
index e66ca78..aa0263e 100755
Binary files a/cpld/db/GR8RAM.sgdiff.cdb and b/cpld/db/GR8RAM.sgdiff.cdb differ
diff --git a/cpld/db/GR8RAM.sgdiff.hdb b/cpld/db/GR8RAM.sgdiff.hdb
index 9c6c7f2..4370539 100755
Binary files a/cpld/db/GR8RAM.sgdiff.hdb and b/cpld/db/GR8RAM.sgdiff.hdb differ
diff --git a/cpld/db/GR8RAM.sld_design_entry.sci b/cpld/db/GR8RAM.sld_design_entry.sci
index 754b594..1d6d60f 100755
Binary files a/cpld/db/GR8RAM.sld_design_entry.sci and b/cpld/db/GR8RAM.sld_design_entry.sci differ
diff --git a/cpld/db/GR8RAM.sld_design_entry_dsc.sci b/cpld/db/GR8RAM.sld_design_entry_dsc.sci
index 754b594..1d6d60f 100755
Binary files a/cpld/db/GR8RAM.sld_design_entry_dsc.sci and b/cpld/db/GR8RAM.sld_design_entry_dsc.sci differ
diff --git a/cpld/db/GR8RAM.smp_dump.txt b/cpld/db/GR8RAM.smp_dump.txt
index 8062576..365c18b 100755
--- a/cpld/db/GR8RAM.smp_dump.txt
+++ b/cpld/db/GR8RAM.smp_dump.txt
@@ -3,6 +3,8 @@ State Machine - |GR8RAM|IS
Name IS.state_bit_2 IS.state_bit_1 IS.state_bit_0
IS.000 0 0 0
IS.001 0 0 1
+IS.010 1 1 0
+IS.011 1 1 1
IS.100 1 0 0
IS.101 1 0 1
IS.110 0 1 0
diff --git a/cpld/db/GR8RAM.sta.qmsg b/cpld/db/GR8RAM.sta.qmsg
index 8cb6489..4a67a64 100755
--- a/cpld/db/GR8RAM.sta.qmsg
+++ b/cpld/db/GR8RAM.sta.qmsg
@@ -1,23 +1,23 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618161764909 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618161764925 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 11 13:22:43 2021 " "Processing started: Sun Apr 11 13:22:43 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618161764925 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618161764925 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618161764925 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1618161765159 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1618161765987 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618161766175 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618161766175 ""}
-{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1618161766331 ""}
-{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1618161766815 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1618161767003 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1618161767003 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C25M C25M " "create_clock -period 1.000 -name C25M C25M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767018 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI0 PHI0 " "create_clock -period 1.000 -name PHI0 PHI0" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767018 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767018 ""}
-{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1618161767050 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1618161767331 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -9.908 " "Worst-case setup slack is -9.908" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767393 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767393 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.908 -697.920 C25M " " -9.908 -697.920 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767393 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.302 -1.302 PHI0 " " -1.302 -1.302 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767393 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618161767393 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.012 " "Worst-case hold slack is 1.012" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767409 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767409 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.012 0.000 PHI0 " " 1.012 0.000 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767409 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.288 0.000 C25M " " 1.288 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767409 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618161767409 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -4.389 " "Worst-case recovery slack is -4.389" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767425 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767425 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.389 -131.670 C25M " " -4.389 -131.670 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767425 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618161767425 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "removal 4.835 " "Worst-case removal slack is 4.835" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767425 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767425 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.835 0.000 C25M " " 4.835 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767425 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618161767425 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.289 " "Worst-case minimum pulse width slack is -2.289" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767456 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767456 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 C25M " " -2.289 -2.289 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767456 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI0 " " -2.289 -2.289 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767456 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618161767456 ""}
-{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1618161767706 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618161767815 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618161767815 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "278 " "Peak virtual memory: 278 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618161768143 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 11 13:22:48 2021 " "Processing ended: Sun Apr 11 13:22:48 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618161768143 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618161768143 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618161768143 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618161768143 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618731926284 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618731926284 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 18 03:45:26 2021 " "Processing started: Sun Apr 18 03:45:26 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618731926284 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618731926284 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618731926284 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1618731926354 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1618731926464 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618731926504 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618731926504 ""}
+{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1618731926554 ""}
+{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1618731926884 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1618731926924 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1618731926924 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C25M C25M " "create_clock -period 1.000 -name C25M C25M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618731926934 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI0 PHI0 " "create_clock -period 1.000 -name PHI0 PHI0" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618731926934 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618731926934 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1618731926934 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1618731926944 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -9.691 " "Worst-case setup slack is -9.691" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731926944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731926944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.691 -732.295 C25M " " -9.691 -732.295 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731926944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.358 -1.358 PHI0 " " -1.358 -1.358 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731926944 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618731926944 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.092 " "Worst-case hold slack is 1.092" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731926944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731926944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.092 0.000 PHI0 " " 1.092 0.000 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731926944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.418 0.000 C25M " " 1.418 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731926944 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618731926944 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -5.009 " "Worst-case recovery slack is -5.009" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731926944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731926944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.009 -150.270 C25M " " -5.009 -150.270 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731926944 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618731926944 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "removal 5.455 " "Worst-case removal slack is 5.455" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731926954 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731926954 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 5.455 0.000 C25M " " 5.455 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731926954 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618731926954 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.289 " "Worst-case minimum pulse width slack is -2.289" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731926954 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731926954 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 C25M " " -2.289 -2.289 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731926954 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI0 " " -2.289 -2.289 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731926954 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618731926954 ""}
+{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1618731926994 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618731927004 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618731927004 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 3 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "368 " "Peak virtual memory: 368 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618731927044 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 18 03:45:27 2021 " "Processing ended: Sun Apr 18 03:45:27 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618731927044 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618731927044 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618731927044 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618731927044 ""}
diff --git a/cpld/db/GR8RAM.sta.rdb b/cpld/db/GR8RAM.sta.rdb
index 43f530c..852f1d0 100755
Binary files a/cpld/db/GR8RAM.sta.rdb and b/cpld/db/GR8RAM.sta.rdb differ
diff --git a/cpld/db/GR8RAM.sta_cmp.5_slow.tdb b/cpld/db/GR8RAM.sta_cmp.5_slow.tdb
index f3c2c09..66a297d 100755
Binary files a/cpld/db/GR8RAM.sta_cmp.5_slow.tdb and b/cpld/db/GR8RAM.sta_cmp.5_slow.tdb differ
diff --git a/cpld/db/GR8RAM.tis_db_list.ddb b/cpld/db/GR8RAM.tis_db_list.ddb
index 42a925d..91bbe10 100755
Binary files a/cpld/db/GR8RAM.tis_db_list.ddb and b/cpld/db/GR8RAM.tis_db_list.ddb differ
diff --git a/cpld/db/GR8RAM.vpr.ammdb b/cpld/db/GR8RAM.vpr.ammdb
index 6c2f844..8b5e92d 100755
Binary files a/cpld/db/GR8RAM.vpr.ammdb and b/cpld/db/GR8RAM.vpr.ammdb differ
diff --git a/cpld/db/logic_util_heursitic.dat b/cpld/db/logic_util_heursitic.dat
index 2adb0ab..85e389e 100755
Binary files a/cpld/db/logic_util_heursitic.dat and b/cpld/db/logic_util_heursitic.dat differ
diff --git a/cpld/db/prev_cmp_GR8RAM.qmsg b/cpld/db/prev_cmp_GR8RAM.qmsg
index 55e3175..cf8b012 100755
--- a/cpld/db/prev_cmp_GR8RAM.qmsg
+++ b/cpld/db/prev_cmp_GR8RAM.qmsg
@@ -1,99 +1,100 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618116856343 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618116856359 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 11 00:54:16 2021 " "Processing started: Sun Apr 11 00:54:16 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618116856359 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618116856359 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618116856359 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1618116858062 ""}
-{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(79) " "Verilog HDL warning at GR8RAM.v(79): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 79 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618116858250 ""}
-{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(256) " "Verilog HDL warning at GR8RAM.v(256): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 256 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618116858250 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1618116858250 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1618116858250 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1618116858344 ""}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(20) " "Verilog HDL assignment warning at GR8RAM.v(20): truncated value with size 32 to match size of target (14)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 20 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618116858359 "|GR8RAM"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(103) " "Verilog HDL assignment warning at GR8RAM.v(103): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 103 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618116858359 "|GR8RAM"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(111) " "Verilog HDL assignment warning at GR8RAM.v(111): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 111 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618116858359 "|GR8RAM"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(118) " "Verilog HDL assignment warning at GR8RAM.v(118): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 118 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618116858359 "|GR8RAM"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(307) " "Verilog HDL assignment warning at GR8RAM.v(307): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 307 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618116858359 "|GR8RAM"}
-{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 -1 1618116859969 ""}
-{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1618116861047 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "309 " "Implemented 309 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "26 " "Implemented 26 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1618116861078 ""} { "Info" "ICUT_CUT_TM_OPINS" "26 " "Implemented 26 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1618116861078 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1618116861078 ""} { "Info" "ICUT_CUT_TM_LCELLS" "240 " "Implemented 240 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1618116861078 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1618116861078 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1618116861313 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "301 " "Peak virtual memory: 301 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618116861625 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 11 00:54:21 2021 " "Processing ended: Sun Apr 11 00:54:21 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618116861625 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618116861625 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618116861625 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618116861625 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618116865000 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 32-bit " "Running Quartus II 32-bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618116865016 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 11 00:54:23 2021 " "Processing started: Sun Apr 11 00:54:23 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618116865016 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1618116865016 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1618116865016 ""}
-{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1618116865219 ""}
-{ "Info" "0" "" "Project = GR8RAM" { } { } 0 0 "Project = GR8RAM" 0 0 "Fitter" 0 0 1618116865219 ""}
-{ "Info" "0" "" "Revision = GR8RAM" { } { } 0 0 "Revision = GR8RAM" 0 0 "Fitter" 0 0 1618116865219 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1618116865922 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1618116865938 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618116866110 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618116866110 ""}
-{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1618116866391 ""}
-{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1618116866422 ""}
-{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618116866766 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618116866766 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618116866766 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618116866766 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618116866766 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1618116866766 ""}
-{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "1 69 " "No exact pin location assignment(s) for 1 pins of 69 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RDdir " "Pin RDdir not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RDdir } } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 82 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RDdir } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 356 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1618116866766 ""} } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1618116866766 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1618116866938 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1618116866938 ""}
-{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1618116866954 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1618116866954 ""}
-{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618116866954 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618116866954 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 C25M " " 1.000 C25M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618116866954 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI0 " " 1.000 PHI0" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618116866954 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1618116866954 ""}
-{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618116866954 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618116866954 ""}
-{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618116866969 ""}
-{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618116866985 ""}
-{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI0 Global clock " "Automatically promoted some destinations of signal \"PHI0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~1 " "Destination \"comb~1\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618116866985 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI0r1 " "Destination \"PHI0r1\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618116866985 ""} } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618116866985 ""}
-{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI0 " "Pin \"PHI0\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI0 } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "PHI0" } } } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 350 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1618116866985 ""}
-{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "nRESr Global clock " "Automatically promoted signal \"nRESr\" to use Global clock" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 15 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618116866985 ""}
-{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618116866985 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1618116866985 ""}
-{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1618116867032 ""}
-{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1618116867110 ""}
-{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1618116867126 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1618116867126 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1618116867126 ""}
-{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "1 unused 3.3V 0 1 0 " "Number of I/O pins in group: 1 (unused VREF, 3.3V VCCIO, 0 input, 1 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "I/O standards used: 3.3-V LVTTL." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1618116867141 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1618116867141 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1618116867141 ""}
-{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.3V 26 12 " "I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 26 total pin(s) used -- 12 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1618116867141 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use 3.3V 42 0 " "I/O bank number 2 does not use VREF pins and has 3.3V VCCIO pins. 42 total pin(s) used -- 0 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1618116867141 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1618116867141 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1618116867141 ""}
-{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "Ddir " "Node \"Ddir\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "Ddir" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1618116867188 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1618116867188 ""}
-{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618116867188 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1618116867376 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618116867719 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1618116867751 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1618116869157 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618116869157 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1618116869204 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "32 " "Router estimated average interconnect usage is 32% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "32 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 32% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 32% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 32% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1618116869595 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1618116869595 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618116870251 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.53 " "Total time spent on timing analysis during the Fitter is 0.53 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1618116870267 ""}
-{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618116870282 ""}
-{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1618116870329 ""}
-{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1618116870329 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1618116870501 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 7 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "372 " "Peak virtual memory: 372 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618116870720 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 11 00:54:30 2021 " "Processing ended: Sun Apr 11 00:54:30 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618116870720 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618116870720 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618116870720 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1618116870720 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1618116872954 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618116872954 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 11 00:54:32 2021 " "Processing started: Sun Apr 11 00:54:32 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618116872954 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1618116872954 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1618116872954 ""}
-{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1618116874064 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1618116874079 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "293 " "Peak virtual memory: 293 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618116874548 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 11 00:54:34 2021 " "Processing ended: Sun Apr 11 00:54:34 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618116874548 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618116874548 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618116874548 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1618116874548 ""}
-{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1618116875298 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1618116877189 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618116877205 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 11 00:54:36 2021 " "Processing started: Sun Apr 11 00:54:36 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618116877205 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618116877205 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618116877205 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1618116877408 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1618116878158 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618116878314 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618116878314 ""}
-{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1618116878502 ""}
-{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1618116879064 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1618116879220 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1618116879236 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C25M C25M " "create_clock -period 1.000 -name C25M C25M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879236 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI0 PHI0 " "create_clock -period 1.000 -name PHI0 PHI0" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879236 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879236 ""}
-{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1618116879236 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1618116879361 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -9.908 " "Worst-case setup slack is -9.908" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879392 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879392 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.908 -697.920 C25M " " -9.908 -697.920 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879392 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.302 -1.302 PHI0 " " -1.302 -1.302 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879392 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618116879392 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.012 " "Worst-case hold slack is 1.012" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879408 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879408 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.012 0.000 PHI0 " " 1.012 0.000 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879408 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.288 0.000 C25M " " 1.288 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879408 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618116879408 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -4.389 " "Worst-case recovery slack is -4.389" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879424 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879424 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.389 -131.670 C25M " " -4.389 -131.670 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879424 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618116879424 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "removal 4.835 " "Worst-case removal slack is 4.835" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879439 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879439 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.835 0.000 C25M " " 4.835 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879439 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618116879439 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.289 " "Worst-case minimum pulse width slack is -2.289" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879439 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879439 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 C25M " " -2.289 -2.289 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879439 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI0 " " -2.289 -2.289 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618116879439 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618116879439 ""}
-{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1618116879611 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618116879705 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618116879705 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "278 " "Peak virtual memory: 278 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618116879877 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 11 00:54:39 2021 " "Processing ended: Sun Apr 11 00:54:39 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618116879877 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618116879877 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618116879877 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618116879877 ""}
-{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 14 s " "Quartus II Full Compilation was successful. 0 errors, 14 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618116880814 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618731317099 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618731317099 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 18 03:35:16 2021 " "Processing started: Sun Apr 18 03:35:16 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618731317099 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618731317099 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618731317099 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1618731317329 ""}
+{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(93) " "Verilog HDL warning at GR8RAM.v(93): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 93 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618731317379 ""}
+{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(273) " "Verilog HDL warning at GR8RAM.v(273): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 273 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618731317379 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1618731317379 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1618731317379 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1618731317409 ""}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(34) " "Verilog HDL assignment warning at GR8RAM.v(34): truncated value with size 32 to match size of target (14)" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 34 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618731317409 "|GR8RAM"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(117) " "Verilog HDL assignment warning at GR8RAM.v(117): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 117 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618731317409 "|GR8RAM"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(125) " "Verilog HDL assignment warning at GR8RAM.v(125): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 125 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618731317409 "|GR8RAM"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(132) " "Verilog HDL assignment warning at GR8RAM.v(132): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 132 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618731317409 "|GR8RAM"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(324) " "Verilog HDL assignment warning at GR8RAM.v(324): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 324 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618731317409 "|GR8RAM"}
+{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 -1 1618731317749 ""}
+{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 15 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618731317889 "|GR8RAM|RAdir"} { "Warning" "WMLS_MLS_STUCK_PIN" "nDMAout VCC " "Pin \"nDMAout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 20 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618731317889 "|GR8RAM|nDMAout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nNMIout VCC " "Pin \"nNMIout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 21 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618731317889 "|GR8RAM|nNMIout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nIRQout VCC " "Pin \"nIRQout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 24 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618731317889 "|GR8RAM|nIRQout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nRDYout VCC " "Pin \"nRDYout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618731317889 "|GR8RAM|nRDYout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nINHout VCC " "Pin \"nINHout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 22 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618731317889 "|GR8RAM|nINHout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RWout VCC " "Pin \"RWout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618731317889 "|GR8RAM|RWout"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1618731317889 ""}
+{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1618731318139 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "322 " "Implemented 322 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "28 " "Implemented 28 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1618731318149 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1618731318149 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1618731318149 ""} { "Info" "ICUT_CUT_TM_LCELLS" "242 " "Implemented 242 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1618731318149 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1618731318149 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1618731318179 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 14 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 14 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "421 " "Peak virtual memory: 421 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618731318199 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 18 03:35:18 2021 " "Processing ended: Sun Apr 18 03:35:18 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618731318199 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618731318199 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618731318199 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618731318199 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618731319149 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 64-Bit " "Running Quartus II 64-Bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618731319149 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 18 03:35:18 2021 " "Processing started: Sun Apr 18 03:35:18 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618731319149 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1618731319149 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1618731319149 ""}
+{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1618731319209 ""}
+{ "Info" "0" "" "Project = GR8RAM" { } { } 0 0 "Project = GR8RAM" 0 0 "Fitter" 0 0 1618731319209 ""}
+{ "Info" "0" "" "Revision = GR8RAM" { } { } 0 0 "Revision = GR8RAM" 0 0 "Fitter" 0 0 1618731319209 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1618731319249 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1618731319249 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618731319289 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618731319289 ""}
+{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1618731319339 ""}
+{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1618731319349 ""}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618731319439 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618731319439 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618731319439 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618731319439 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618731319439 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1618731319439 ""}
+{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "2 80 " "No exact pin location assignment(s) for 2 pins of 80 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DMAout " "Pin DMAout not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DMAout } } } { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 19 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DMAout } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/" { { 0 { 0 ""} 0 374 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1618731319459 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RDdir " "Pin RDdir not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { RDdir } } } { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 96 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { RDdir } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/" { { 0 { 0 ""} 0 385 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1618731319459 ""} } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1618731319459 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1618731319519 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1618731319519 ""}
+{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1618731319529 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1618731319529 ""}
+{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618731319529 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618731319529 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 C25M " " 1.000 C25M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618731319529 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI0 " " 1.000 PHI0" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618731319529 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1618731319529 ""}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618731319529 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618731319529 ""}
+{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618731319529 ""}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618731319539 ""}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI0 Global clock " "Automatically promoted some destinations of signal \"PHI0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~1 " "Destination \"comb~1\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618731319539 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI0r1 " "Destination \"PHI0r1\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 11 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618731319539 ""} } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618731319539 ""}
+{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI0 " "Pin \"PHI0\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { PHI0 } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PHI0" } } } } { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { PHI0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/" { { 0 { 0 ""} 0 368 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1618731319539 ""}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "nRESr Global clock " "Automatically promoted signal \"nRESr\" to use Global clock" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 29 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618731319539 ""}
+{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618731319539 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1618731319539 ""}
+{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1618731319559 ""}
+{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1618731319579 ""}
+{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1618731319579 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1618731319579 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1618731319579 ""}
+{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "2 unused 3.3V 0 2 0 " "Number of I/O pins in group: 2 (unused VREF, 3.3V VCCIO, 0 input, 2 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "I/O standards used: 3.3-V LVTTL." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1618731319599 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1618731319599 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1618731319599 ""}
+{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.3V 36 2 " "I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 36 total pin(s) used -- 2 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1618731319599 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use 3.3V 42 0 " "I/O bank number 2 does not use VREF pins and has 3.3V VCCIO pins. 42 total pin(s) used -- 0 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1618731319599 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1618731319599 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1618731319599 ""}
+{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "Ddir " "Node \"Ddir\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "Ddir" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1618731319629 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1618731319629 ""}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618731319629 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1618731319699 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618731319919 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1618731319929 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1618731320523 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618731320523 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1618731320553 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "34 " "Router estimated average interconnect usage is 34% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "34 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1618731320763 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1618731320763 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618731321393 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.27 " "Total time spent on timing analysis during the Fitter is 0.27 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1618731321393 ""}
+{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618731321403 ""}
+{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1618731321443 ""}
+{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1618731321443 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1618731321483 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 8 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "545 " "Peak virtual memory: 545 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618731321513 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 18 03:35:21 2021 " "Processing ended: Sun Apr 18 03:35:21 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618731321513 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618731321513 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618731321513 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1618731321513 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1618731322373 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618731322373 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 18 03:35:22 2021 " "Processing started: Sun Apr 18 03:35:22 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618731322373 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1618731322373 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1618731322373 ""}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1618731322563 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1618731322573 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "381 " "Peak virtual memory: 381 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618731322703 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 18 03:35:22 2021 " "Processing ended: Sun Apr 18 03:35:22 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618731322703 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618731322703 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618731322703 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1618731322703 ""}
+{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1618731323273 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1618731323653 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618731323653 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 18 03:35:23 2021 " "Processing started: Sun Apr 18 03:35:23 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618731323653 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618731323653 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618731323653 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1618731323723 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1618731323823 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618731323873 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618731323873 ""}
+{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1618731323923 ""}
+{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1618731324243 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1618731324283 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1618731324283 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C25M C25M " "create_clock -period 1.000 -name C25M C25M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618731324283 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI0 PHI0 " "create_clock -period 1.000 -name PHI0 PHI0" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618731324283 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618731324283 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1618731324283 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1618731324293 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -10.039 " "Worst-case setup slack is -10.039" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731324303 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731324303 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -10.039 -703.074 C25M " " -10.039 -703.074 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731324303 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.227 -1.227 PHI0 " " -1.227 -1.227 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731324303 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618731324303 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.063 " "Worst-case hold slack is 1.063" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731324303 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731324303 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.063 0.000 PHI0 " " 1.063 0.000 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731324303 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.544 0.000 C25M " " 1.544 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731324303 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618731324303 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -4.399 " "Worst-case recovery slack is -4.399" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731324303 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731324303 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.399 -131.970 C25M " " -4.399 -131.970 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731324303 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618731324303 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "removal 4.845 " "Worst-case removal slack is 4.845" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731324303 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731324303 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.845 0.000 C25M " " 4.845 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731324303 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618731324303 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.289 " "Worst-case minimum pulse width slack is -2.289" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731324303 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731324303 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 C25M " " -2.289 -2.289 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731324303 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI0 " " -2.289 -2.289 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731324303 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618731324303 ""}
+{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1618731324353 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618731324363 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618731324363 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 3 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "368 " "Peak virtual memory: 368 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618731324393 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 18 03:35:24 2021 " "Processing ended: Sun Apr 18 03:35:24 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618731324393 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618731324393 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618731324393 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618731324393 ""}
+{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 25 s " "Quartus II Full Compilation was successful. 0 errors, 25 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618731324988 ""}
diff --git a/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt b/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt
index 52f9d5a..0052843 100755
Binary files a/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt and b/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt differ
diff --git a/cpld/output_files/GR8RAM.asm.rpt b/cpld/output_files/GR8RAM.asm.rpt
index c6c0b91..042a03c 100755
--- a/cpld/output_files/GR8RAM.asm.rpt
+++ b/cpld/output_files/GR8RAM.asm.rpt
@@ -1,6 +1,6 @@
Assembler report for GR8RAM
-Sun Apr 11 13:22:41 2021
-Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+Sun Apr 18 03:45:25 2021
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
---------------------
@@ -10,7 +10,7 @@ Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit
2. Assembler Summary
3. Assembler Settings
4. Assembler Generated Files
- 5. Assembler Device Options: Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pof
+ 5. Assembler Device Options: C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.pof
6. Assembler Messages
@@ -37,7 +37,7 @@ applicable agreement for further details.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
-; Assembler Status ; Successful - Sun Apr 11 13:22:41 2021 ;
+; Assembler Status ; Successful - Sun Apr 18 03:45:25 2021 ;
; Revision Name ; GR8RAM ;
; Top-level Entity Name ; GR8RAM ;
; Family ; MAX II ;
@@ -75,40 +75,40 @@ applicable agreement for further details.
+-----------------------------------------------------------------------------+-----------+---------------+
-+----------------------------------------------+
-; Assembler Generated Files ;
-+----------------------------------------------+
-; File Name ;
-+----------------------------------------------+
-; Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pof ;
-+----------------------------------------------+
++-------------------------------------------------------------------+
+; Assembler Generated Files ;
++-------------------------------------------------------------------+
+; File Name ;
++-------------------------------------------------------------------+
+; C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.pof ;
++-------------------------------------------------------------------+
-+------------------------------------------------------------------------+
-; Assembler Device Options: Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pof ;
-+----------------+-------------------------------------------------------+
-; Option ; Setting ;
-+----------------+-------------------------------------------------------+
-; Device ; EPM240T100C5 ;
-; JTAG usercode ; 0x00162982 ;
-; Checksum ; 0x00162E02 ;
-+----------------+-------------------------------------------------------+
++---------------------------------------------------------------------------------------------+
+; Assembler Device Options: C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.pof ;
++----------------+----------------------------------------------------------------------------+
+; Option ; Setting ;
++----------------+----------------------------------------------------------------------------+
+; Device ; EPM240T100C5 ;
+; JTAG usercode ; 0x0015FC20 ;
+; Checksum ; 0x00160180 ;
++----------------+----------------------------------------------------------------------------+
+--------------------+
; Assembler Messages ;
+--------------------+
Info: *******************************************************************
-Info: Running Quartus II 32-bit Assembler
+Info: Running Quartus II 64-Bit Assembler
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
- Info: Processing started: Sun Apr 11 13:22:38 2021
+ Info: Processing started: Sun Apr 18 03:45:24 2021
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM
Info (115031): Writing out detailed assembly data for power analysis
Info (115030): Assembler is generating device programming files
-Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings
- Info: Peak virtual memory: 293 megabytes
- Info: Processing ended: Sun Apr 11 13:22:41 2021
- Info: Elapsed time: 00:00:03
- Info: Total CPU time (on all processors): 00:00:03
+Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
+ Info: Peak virtual memory: 381 megabytes
+ Info: Processing ended: Sun Apr 18 03:45:25 2021
+ Info: Elapsed time: 00:00:01
+ Info: Total CPU time (on all processors): 00:00:00
diff --git a/cpld/output_files/GR8RAM.cdf b/cpld/output_files/GR8RAM.cdf
new file mode 100644
index 0000000..fb7cb58
--- /dev/null
+++ b/cpld/output_files/GR8RAM.cdf
@@ -0,0 +1,13 @@
+/* Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition */
+JedecChain;
+ FileRevision(JESD32A);
+ DefaultMfr(6E);
+
+ P ActionCode(Vfy)
+ Device PartName(EPM240T100) Path("C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/") File("GR8RAM.pof") MfrSpec(OpMask(2) SEC_Device(EPM240T100) Child_OpMask(2 2 2));
+
+ChainEnd;
+
+AlteraBegin;
+ ChainType(JTAG);
+AlteraEnd;
diff --git a/cpld/output_files/GR8RAM.done b/cpld/output_files/GR8RAM.done
index b76e1d7..3bdf1c8 100755
--- a/cpld/output_files/GR8RAM.done
+++ b/cpld/output_files/GR8RAM.done
@@ -1 +1 @@
-Sun Apr 11 13:22:49 2021
+Sun Apr 18 03:45:27 2021
diff --git a/cpld/output_files/GR8RAM.fit.rpt b/cpld/output_files/GR8RAM.fit.rpt
index dffb06e..d075299 100755
--- a/cpld/output_files/GR8RAM.fit.rpt
+++ b/cpld/output_files/GR8RAM.fit.rpt
@@ -1,6 +1,6 @@
Fitter report for GR8RAM
-Sun Apr 11 13:22:34 2021
-Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+Sun Apr 18 03:45:24 2021
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
---------------------
@@ -10,31 +10,30 @@ Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit
2. Fitter Summary
3. Fitter Settings
4. Parallel Compilation
- 5. Ignored Assignments
- 6. Pin-Out File
- 7. Fitter Resource Usage Summary
- 8. Input Pins
- 9. Output Pins
- 10. Bidir Pins
- 11. I/O Bank Usage
- 12. All Package Pins
- 13. Output Pin Default Load For Reported TCO
- 14. Fitter Resource Utilization by Entity
- 15. Delay Chain Summary
- 16. Control Signals
- 17. Global & Other Fast Signals
- 18. Non-Global High Fan-Out Signals
- 19. Other Routing Usage Summary
- 20. LAB Logic Elements
- 21. LAB-wide Signals
- 22. LAB Signals Sourced
- 23. LAB Signals Sourced Out
- 24. LAB Distinct Inputs
- 25. Fitter Device Options
- 26. Estimated Delay Added for Hold Timing Summary
- 27. Estimated Delay Added for Hold Timing Details
- 28. Fitter Messages
- 29. Fitter Suppressed Messages
+ 5. Pin-Out File
+ 6. Fitter Resource Usage Summary
+ 7. Input Pins
+ 8. Output Pins
+ 9. Bidir Pins
+ 10. I/O Bank Usage
+ 11. All Package Pins
+ 12. Output Pin Default Load For Reported TCO
+ 13. Fitter Resource Utilization by Entity
+ 14. Delay Chain Summary
+ 15. Control Signals
+ 16. Global & Other Fast Signals
+ 17. Non-Global High Fan-Out Signals
+ 18. Other Routing Usage Summary
+ 19. LAB Logic Elements
+ 20. LAB-wide Signals
+ 21. LAB Signals Sourced
+ 22. LAB Signals Sourced Out
+ 23. LAB Distinct Inputs
+ 24. Fitter Device Options
+ 25. Estimated Delay Added for Hold Timing Summary
+ 26. Estimated Delay Added for Hold Timing Details
+ 27. Fitter Messages
+ 28. Fitter Suppressed Messages
@@ -60,15 +59,15 @@ applicable agreement for further details.
+-----------------------------------------------------------------------------+
; Fitter Summary ;
+---------------------------+-------------------------------------------------+
-; Fitter Status ; Successful - Sun Apr 11 13:22:34 2021 ;
-; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
+; Fitter Status ; Successful - Sun Apr 18 03:45:24 2021 ;
+; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name ; GR8RAM ;
; Top-level Entity Name ; GR8RAM ;
; Family ; MAX II ;
; Device ; EPM240T100C5 ;
; Timing Models ; Final ;
-; Total logic elements ; 227 / 240 ( 95 % ) ;
-; Total pins ; 69 / 80 ( 86 % ) ;
+; Total logic elements ; 229 / 240 ( 95 % ) ;
+; Total pins ; 80 / 80 ( 100 % ) ;
; Total virtual pins ; 0 ;
; UFM blocks ; 0 / 1 ( 0 % ) ;
+---------------------------+-------------------------------------------------+
@@ -123,36 +122,21 @@ applicable agreement for further details.
+----------------------------------------------------------------------------+--------------------------------+--------------------------------+
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 2 ;
-; Maximum allowed ; 2 ;
-; ; ;
-; Average used ; 1.40 ;
-; Maximum used ; 2 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-; Processor 2 ; 40.0% ;
-+----------------------------+-------------+
-
-
-+----------------------------------------------------------------------------------------+
-; Ignored Assignments ;
-+----------+----------------+--------------+------------+---------------+----------------+
-; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ;
-+----------+----------------+--------------+------------+---------------+----------------+
-; Location ; ; ; Ddir ; PIN_17 ; QSF Assignment ;
-+----------+----------------+--------------+------------+---------------+----------------+
+Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
++-------------------------------------+
+; Parallel Compilation ;
++----------------------------+--------+
+; Processors ; Number ;
++----------------------------+--------+
+; Number detected on machine ; 12 ;
+; Maximum allowed ; 1 ;
++----------------------------+--------+
+--------------+
; Pin-Out File ;
+--------------+
-The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin.
+The pin-out file can be found in C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.pin.
+------------------------------------------------------------------+
@@ -160,43 +144,43 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin.
+---------------------------------------------+--------------------+
; Resource ; Usage ;
+---------------------------------------------+--------------------+
-; Total logic elements ; 227 / 240 ( 95 % ) ;
-; -- Combinational with no register ; 125 ;
+; Total logic elements ; 229 / 240 ( 95 % ) ;
+; -- Combinational with no register ; 126 ;
; -- Register only ; 1 ;
-; -- Combinational with a register ; 101 ;
+; -- Combinational with a register ; 102 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
-; -- 4 input functions ; 130 ;
+; -- 4 input functions ; 135 ;
; -- 3 input functions ; 30 ;
-; -- 2 input functions ; 66 ;
+; -- 2 input functions ; 63 ;
; -- 1 input functions ; 0 ;
; -- 0 input functions ; 0 ;
; ; ;
; Logic elements by mode ; ;
-; -- normal mode ; 194 ;
+; -- normal mode ; 196 ;
; -- arithmetic mode ; 33 ;
; -- qfbk mode ; 4 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 47 ;
; -- asynchronous clear/load mode ; 30 ;
; ; ;
-; Total registers ; 102 / 240 ( 43 % ) ;
+; Total registers ; 103 / 240 ( 43 % ) ;
; Total LABs ; 24 / 24 ( 100 % ) ;
; Logic elements in carry chains ; 37 ;
; Virtual pins ; 0 ;
-; I/O pins ; 69 / 80 ( 86 % ) ;
+; I/O pins ; 80 / 80 ( 100 % ) ;
; -- Clock pins ; 4 / 4 ( 100 % ) ;
; ; ;
; Global signals ; 3 ;
; UFM blocks ; 0 / 1 ( 0 % ) ;
; Global clocks ; 3 / 4 ( 75 % ) ;
; JTAGs ; 0 / 1 ( 0 % ) ;
-; Average interconnect usage (total/H/V) ; 47% / 53% / 40% ;
-; Peak interconnect usage (total/H/V) ; 47% / 53% / 40% ;
-; Maximum fan-out ; 99 ;
-; Highest non-global fan-out ; 42 ;
-; Total fan-out ; 1046 ;
-; Average fan-out ; 3.53 ;
+; Average interconnect usage (total/H/V) ; 51% / 57% / 44% ;
+; Peak interconnect usage (total/H/V) ; 51% / 57% / 44% ;
+; Maximum fan-out ; 100 ;
+; Highest non-global fan-out ; 50 ;
+; Total fan-out ; 1064 ;
+; Average fan-out ; 3.44 ;
+---------------------------------------------+--------------------+
@@ -205,7 +189,9 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin.
+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Location assigned by ;
+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+
-; C25M ; 64 ; 2 ; 8 ; 3 ; 4 ; 99 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; User ;
+; C25M ; 64 ; 2 ; 8 ; 3 ; 4 ; 100 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; User ;
+; DMAin ; 48 ; 1 ; 6 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ;
+; INTin ; 49 ; 1 ; 7 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ;
; MISO ; 16 ; 1 ; 1 ; 2 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ;
; PHI0 ; 41 ; 1 ; 5 ; 0 ; 1 ; 5 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; User ;
; RA[0] ; 100 ; 2 ; 2 ; 5 ; 2 ; 10 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ;
@@ -239,11 +225,15 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin.
+---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ;
+---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
+; DMAout ; 18 ; 1 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; DQMH ; 57 ; 2 ; 8 ; 2 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; DQML ; 85 ; 2 ; 5 ; 5 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
-; FCK ; 12 ; 1 ; 1 ; 3 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
+; FCK ; 12 ; 1 ; 1 ; 3 ; 3 ; no ; no ; no ; no ; yes ; yes ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
+; INTout ; 20 ; 1 ; 1 ; 1 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
+; RAdir ; 19 ; 1 ; 1 ; 1 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; RCKE ; 66 ; 2 ; 8 ; 3 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
-; RDdir ; 17 ; 1 ; 1 ; 2 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ;
+; RDdir ; 17 ; 1 ; 1 ; 2 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
+; RWout ; 33 ; 1 ; 3 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; SA[0] ; 75 ; 2 ; 7 ; 5 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; SA[10] ; 73 ; 2 ; 8 ; 4 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; SA[11] ; 70 ; 2 ; 8 ; 4 ; 4 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
@@ -260,9 +250,14 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin.
; SBA[0] ; 69 ; 2 ; 8 ; 3 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; SBA[1] ; 71 ; 2 ; 8 ; 4 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; nCAS ; 61 ; 2 ; 8 ; 2 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
-; nFCS ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; - ; - ;
+; nDMAout ; 21 ; 1 ; 1 ; 1 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
+; nFCS ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; no ; no ; no ; yes ; no ; On ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
+; nINHout ; 27 ; 1 ; 2 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
+; nIRQout ; 29 ; 1 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
+; nNMIout ; 26 ; 1 ; 2 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; nRAS ; 62 ; 2 ; 8 ; 2 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; nRCS ; 67 ; 2 ; 8 ; 3 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
+; nRDYout ; 28 ; 1 ; 2 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; nRESout ; 30 ; 1 ; 3 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; nSWE ; 58 ; 2 ; 8 ; 2 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
+---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
@@ -273,7 +268,7 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin.
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ;
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
-; MOSI ; 15 ; 1 ; 1 ; 2 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; MOSIOE ; - ;
+; MOSI ; 15 ; 1 ; 1 ; 2 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; MOSIOE ; - ;
; RD[0] ; 86 ; 2 ; 5 ; 5 ; 1 ; 5 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; comb~1 ; - ;
; RD[1] ; 87 ; 2 ; 5 ; 5 ; 2 ; 4 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; comb~1 ; - ;
; RD[2] ; 88 ; 2 ; 5 ; 5 ; 3 ; 4 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; comb~1 ; - ;
@@ -288,7 +283,7 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin.
; SD[3] ; 55 ; 2 ; 8 ; 1 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ;
; SD[4] ; 51 ; 1 ; 7 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ;
; SD[5] ; 52 ; 2 ; 8 ; 1 ; 4 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ;
-; SD[6] ; 53 ; 2 ; 8 ; 1 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ;
+; SD[6] ; 53 ; 2 ; 8 ; 1 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; SDOE ; - ;
; SD[7] ; 54 ; 2 ; 8 ; 1 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ;
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
@@ -298,7 +293,7 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin.
+----------+-------------------+---------------+--------------+
; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
+----------+-------------------+---------------+--------------+
-; 1 ; 27 / 38 ( 71 % ) ; 3.3V ; -- ;
+; 1 ; 38 / 38 ( 100 % ) ; 3.3V ; -- ;
; 2 ; 42 / 42 ( 100 % ) ; 3.3V ; -- ;
+----------+-------------------+---------------+--------------+
@@ -312,35 +307,35 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin.
; 2 ; 0 ; 1 ; RA[5] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 3 ; 1 ; 1 ; RA[6] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 4 ; 2 ; 1 ; RA[3] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; 5 ; 3 ; 1 ; nFCS ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; 5 ; 3 ; 1 ; nFCS ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
; 6 ; 4 ; 1 ; RA[7] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 7 ; 5 ; 1 ; RA[8] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 8 ; 6 ; 1 ; RA[9] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 9 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 10 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;
; 11 ; ; ; GNDINT ; gnd ; ; ; -- ; ; -- ; -- ;
-; 12 ; 7 ; 1 ; FCK ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; 12 ; 7 ; 1 ; FCK ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; yes ; Off ;
; 13 ; ; ; VCCINT ; power ; ; 2.5V/3.3V ; -- ; ; -- ; -- ;
; 14 ; 8 ; 1 ; RA[10] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; 15 ; 9 ; 1 ; MOSI ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; 15 ; 9 ; 1 ; MOSI ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; yes ; Off ;
; 16 ; 10 ; 1 ; MISO ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; 17 ; 11 ; 1 ; RDdir ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
-; 18 ; 12 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 19 ; 13 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 20 ; 14 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 21 ; 15 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 17 ; 11 ; 1 ; RDdir ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; 18 ; 12 ; 1 ; DMAout ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; 19 ; 13 ; 1 ; RAdir ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; 20 ; 14 ; 1 ; INTout ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; 21 ; 15 ; 1 ; nDMAout ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 22 ; 16 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
; 23 ; 17 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
; 24 ; 18 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
; 25 ; 19 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
-; 26 ; 20 ; 1 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 27 ; 21 ; 1 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 28 ; 22 ; 1 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 29 ; 23 ; 1 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 26 ; 20 ; 1 ; nNMIout ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; 27 ; 21 ; 1 ; nINHout ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; 28 ; 22 ; 1 ; nRDYout ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; 29 ; 23 ; 1 ; nIRQout ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 30 ; 24 ; 1 ; nRESout ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 31 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 32 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;
-; 33 ; 25 ; 1 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 33 ; 25 ; 1 ; RWout ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 34 ; 26 ; 1 ; RA[11] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 35 ; 27 ; 1 ; RA[12] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 36 ; 28 ; 1 ; RA[13] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
@@ -355,8 +350,8 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin.
; 45 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 46 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;
; 47 ; 37 ; 1 ; SD[1] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
-; 48 ; 38 ; 1 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 49 ; 39 ; 1 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 48 ; 38 ; 1 ; DMAin ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; 49 ; 39 ; 1 ; INTin ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 50 ; 40 ; 1 ; SD[0] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 51 ; 41 ; 1 ; SD[4] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 52 ; 42 ; 2 ; SD[5] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
@@ -433,7 +428,7 @@ Note: User assignments will override these defaults. The user specified values a
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
-; |GR8RAM ; 227 (227) ; 102 ; 0 ; 69 ; 0 ; 125 (125) ; 1 (1) ; 101 (101) ; 37 (37) ; 12 (12) ; |GR8RAM ; work ;
+; |GR8RAM ; 229 (229) ; 103 ; 0 ; 80 ; 0 ; 126 (126) ; 1 (1) ; 102 (102) ; 37 (37) ; 12 (12) ; |GR8RAM ; work ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
@@ -443,6 +438,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+----------+----------+---------------+
; Name ; Pin Type ; Pad to Core 0 ;
+----------+----------+---------------+
+; INTin ; Input ; (1) ;
+; DMAin ; Input ; (1) ;
; nIOSTRB ; Input ; (1) ;
; nIOSEL ; Input ; (1) ;
; nDEVSEL ; Input ; (1) ;
@@ -470,6 +467,15 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; nRES ; Input ; (1) ;
; MISO ; Input ; (1) ;
; nRESout ; Output ; -- ;
+; RAdir ; Output ; -- ;
+; INTout ; Output ; -- ;
+; DMAout ; Output ; -- ;
+; nDMAout ; Output ; -- ;
+; nNMIout ; Output ; -- ;
+; nIRQout ; Output ; -- ;
+; nRDYout ; Output ; -- ;
+; nINHout ; Output ; -- ;
+; RWout ; Output ; -- ;
; RDdir ; Output ; -- ;
; SBA[0] ; Output ; -- ;
; SBA[1] ; Output ; -- ;
@@ -520,20 +526,21 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+------------+-------------+---------+-------------------------+--------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
+------------+-------------+---------+-------------------------+--------+----------------------+------------------+
-; C25M ; PIN_64 ; 99 ; Clock ; yes ; Global Clock ; GCLK3 ;
-; Decoder1~0 ; LC_X7_Y1_N0 ; 8 ; Clock enable ; no ; -- ; -- ;
-; Equal0~0 ; LC_X4_Y3_N0 ; 19 ; Clock enable ; no ; -- ; -- ;
-; MOSIOE ; LC_X2_Y2_N6 ; 1 ; Output enable ; no ; -- ; -- ;
+; C25M ; PIN_64 ; 100 ; Clock ; yes ; Global Clock ; GCLK3 ;
+; Decoder1~0 ; LC_X6_Y3_N5 ; 8 ; Clock enable ; no ; -- ; -- ;
+; Equal0~0 ; LC_X3_Y4_N6 ; 18 ; Clock enable ; no ; -- ; -- ;
+; FCKOE ; LC_X2_Y1_N9 ; 2 ; Output enable ; no ; -- ; -- ;
+; MOSIOE ; LC_X3_Y1_N7 ; 1 ; Output enable ; no ; -- ; -- ;
; PHI0 ; PIN_41 ; 5 ; Clock ; yes ; Global Clock ; GCLK1 ;
-; PS[0] ; LC_X5_Y3_N8 ; 42 ; Clock enable ; no ; -- ; -- ;
-; PS[2] ; LC_X5_Y3_N1 ; 30 ; Sync. clear, Sync. load ; no ; -- ; -- ;
-; SDOE ; LC_X7_Y1_N9 ; 8 ; Output enable ; no ; -- ; -- ;
-; WRD[0]~0 ; LC_X2_Y1_N5 ; 6 ; Clock enable ; no ; -- ; -- ;
-; always6~4 ; LC_X4_Y4_N9 ; 8 ; Sync. load ; no ; -- ; -- ;
-; always6~5 ; LC_X5_Y4_N4 ; 9 ; Sync. load ; no ; -- ; -- ;
-; always6~6 ; LC_X5_Y4_N0 ; 9 ; Sync. load ; no ; -- ; -- ;
-; comb~1 ; LC_X6_Y2_N9 ; 9 ; Output enable ; no ; -- ; -- ;
-; nRESr ; LC_X2_Y3_N6 ; 30 ; Async. clear ; yes ; Global Clock ; GCLK2 ;
+; PS[0] ; LC_X4_Y1_N2 ; 50 ; Clock enable ; no ; -- ; -- ;
+; PS[2] ; LC_X4_Y1_N0 ; 29 ; Sync. clear, Sync. load ; no ; -- ; -- ;
+; SDOE ; LC_X6_Y1_N7 ; 8 ; Output enable ; no ; -- ; -- ;
+; WRD[0]~0 ; LC_X3_Y1_N6 ; 6 ; Clock enable ; no ; -- ; -- ;
+; always6~4 ; LC_X3_Y4_N7 ; 8 ; Sync. load ; no ; -- ; -- ;
+; always6~5 ; LC_X5_Y1_N8 ; 9 ; Sync. load ; no ; -- ; -- ;
+; always6~6 ; LC_X5_Y2_N9 ; 9 ; Sync. load ; no ; -- ; -- ;
+; comb~1 ; LC_X4_Y1_N4 ; 9 ; Output enable ; no ; -- ; -- ;
+; nRESr ; LC_X2_Y3_N0 ; 30 ; Async. clear ; yes ; Global Clock ; GCLK2 ;
+------------+-------------+---------+-------------------------+--------+----------------------+------------------+
@@ -542,9 +549,9 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+-------+-------------+---------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
+-------+-------------+---------+----------------------+------------------+
-; C25M ; PIN_64 ; 99 ; Global Clock ; GCLK3 ;
+; C25M ; PIN_64 ; 100 ; Global Clock ; GCLK3 ;
; PHI0 ; PIN_41 ; 5 ; Global Clock ; GCLK1 ;
-; nRESr ; LC_X2_Y3_N6 ; 30 ; Global Clock ; GCLK2 ;
+; nRESr ; LC_X2_Y3_N0 ; 30 ; Global Clock ; GCLK2 ;
+-------+-------------+---------+----------------------+------------------+
@@ -553,45 +560,45 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+---------------------+-----------+
; Name ; Fan-Out ;
+---------------------+-----------+
-; PS[0] ; 42 ;
-; PS[1] ; 33 ;
-; PS[2] ; 30 ;
-; PS[3] ; 29 ;
-; IS.state_bit_0 ; 22 ;
-; IS.state_bit_1 ; 20 ;
-; Equal0~0 ; 19 ;
-; LS[0] ; 12 ;
-; RAMSpecSELr ; 12 ;
+; PS[0] ; 50 ;
+; PS[1] ; 34 ;
+; PS[2] ; 29 ;
+; PS[3] ; 28 ;
+; IS.110~0 ; 21 ;
+; Equal0~0 ; 18 ;
+; RAMSpecSELr ; 18 ;
+; IS.state_bit_0 ; 16 ;
+; IS.state_bit_1 ; 13 ;
+; IS.state_bit_2 ; 12 ;
+; LS[0] ; 11 ;
; RA[1] ; 10 ;
; RA[0] ; 10 ;
; always6~6 ; 9 ;
; always6~5 ; 9 ;
; comb~1 ; 9 ;
-; RDD[1]~21 ; 8 ;
+; RDD[2]~21 ; 8 ;
; Decoder1~0 ; 8 ;
-; RDD[1]~2 ; 8 ;
+; RDD[2]~2 ; 8 ;
; SDOE ; 8 ;
; always6~4 ; 8 ;
-; SA[3]~14 ; 8 ;
; LS[1] ; 8 ;
-; IS.110~0 ; 8 ;
; LS[2] ; 7 ;
; Equal15~0 ; 7 ;
; RD[7]~7 ; 6 ;
; SetFW[1] ; 6 ;
; SetFW[0] ; 6 ;
-; SA[3]~19 ; 6 ;
+; SA[8]~16 ; 6 ;
; WRD[0]~0 ; 6 ;
-; IS.state_bit_2 ; 6 ;
-; SA[3]~16 ; 6 ;
-; SA[3]~15 ; 6 ;
+; SA[8]~12 ; 6 ;
+; SA[8]~11 ; 6 ;
; Addr[23] ; 6 ;
; RD[0]~0 ; 5 ;
; always6~3 ; 5 ;
+; LS[13] ; 5 ;
; Addr[0] ; 5 ;
; LS[6]~17 ; 5 ;
+; IS.110~1 ; 5 ;
; LS[1]~3 ; 5 ;
-; Mux14~8 ; 5 ;
; RD[6]~6 ; 4 ;
; RD[5]~5 ; 4 ;
; RD[4]~4 ; 4 ;
@@ -599,11 +606,9 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; RD[2]~2 ; 4 ;
; RD[1]~1 ; 4 ;
; nDEVSEL ; 4 ;
-; RDD[4]~12 ; 4 ;
-; RDD[4]~11 ; 4 ;
-; LS[13] ; 4 ;
-; Equal1~2 ; 4 ;
-; nRCS~2 ; 4 ;
+; RDD[7]~12 ; 4 ;
+; RDD[7]~11 ; 4 ;
+; nRCS~4 ; 4 ;
; Addr[22] ; 4 ;
; Addr[21] ; 4 ;
; Addr[20] ; 4 ;
@@ -619,12 +624,14 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; LS[4] ; 4 ;
; Addr[13] ; 4 ;
; Addr[3] ; 4 ;
+; LS[12] ; 4 ;
; Addr[12] ; 4 ;
; Addr[2] ; 4 ;
; Addr[11] ; 4 ;
-; SA[1]~13 ; 4 ;
+; SA[2]~10 ; 4 ;
; Addr[1] ; 4 ;
; Addr[10] ; 4 ;
+; Mux14~6 ; 4 ;
; Equal18~0 ; 4 ;
; RA[10] ; 3 ;
; RA[9] ; 3 ;
@@ -634,18 +641,17 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; RA[2] ; 3 ;
; nIOSEL ; 3 ;
; always6~8 ; 3 ;
-; SA[1]~18 ; 3 ;
+; nRCS~8 ; 3 ;
; REGEN ; 3 ;
; ROMSpecSEL~0 ; 3 ;
; Equal8~0 ; 3 ;
-; Equal2~0 ; 3 ;
-; Equal3~0 ; 3 ;
+; Equal3~2 ; 3 ;
+; Equal3~1 ; 3 ;
; Equal1~3 ; 3 ;
; Equal15~1 ; 3 ;
; nWEr ; 3 ;
-; nRCS~1 ; 3 ;
-; ROMSpecSELr ; 3 ;
; Addr[20]~41 ; 3 ;
+; SA~14 ; 3 ;
; Equal20~0 ; 3 ;
; Addr[19] ; 3 ;
; LS[9] ; 3 ;
@@ -657,13 +663,12 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; LS[6] ; 3 ;
; Addr[4]~17 ; 3 ;
; LS[3] ; 3 ;
-; LS[12] ; 3 ;
; Addr[12]~11 ; 3 ;
; LS[11] ; 3 ;
-; SA[1]~11 ; 3 ;
+; SA[2]~8 ; 3 ;
+; SA[2]~7 ; 3 ;
; LS[10] ; 3 ;
-; SA[1]~10 ; 3 ;
-; Mux14~5 ; 3 ;
+; SA[2]~6 ; 3 ;
; RA[11] ; 2 ;
; RA[6] ; 2 ;
; RA[5] ; 2 ;
@@ -671,27 +676,31 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; nWE ; 2 ;
; nIOSTRB ; 2 ;
; Mux2~9 ; 2 ;
-; SA~20 ; 2 ;
; Mux2~6 ; 2 ;
; Mux2~4 ; 2 ;
; Mux2~3 ; 2 ;
; AddrIncL ; 2 ;
; AddrIncM ; 2 ;
; always6~2 ; 2 ;
-; IS.state_bit_1~3 ; 2 ;
-; IS.state_bit_1~0 ; 2 ;
-; Equal3~1 ; 2 ;
+; Equal4~1 ; 2 ;
+; Equal2~0 ; 2 ;
+; IS.state_bit_2~0 ; 2 ;
+; Equal4~0 ; 2 ;
+; Equal1~1 ; 2 ;
+; Equal1~0 ; 2 ;
+; FCKOE ; 2 ;
; PS~0 ; 2 ;
; DQMH~0 ; 2 ;
; Mux12~2 ; 2 ;
-; nRCS~4 ; 2 ;
+; nRCS~6 ; 2 ;
; always7~1 ; 2 ;
-; nRCS~0 ; 2 ;
-; Mux19~0 ; 2 ;
+; nRCS~3 ; 2 ;
+; nRCS~2 ; 2 ;
+; ROMSpecSELr ; 2 ;
; Bank ; 2 ;
; LS[11]~5 ; 2 ;
-; SA[1]~12 ; 2 ;
-; Mux14~4 ; 2 ;
+; SA[2]~9 ; 2 ;
+; Mux14~3 ; 2 ;
; always5~2 ; 2 ;
; always7~0 ; 2 ;
; IOROMEN ; 2 ;
@@ -711,8 +720,10 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; RA[12] ; 1 ;
; RA[15] ; 1 ;
; RA[14] ; 1 ;
-; Mux13~2 ; 1 ;
-; Mux14~9 ; 1 ;
+; DMAin ; 1 ;
+; INTin ; 1 ;
+; Mux11~7 ; 1 ;
+; Mux14~7 ; 1 ;
; Mux2~7 ; 1 ;
; Mux2~5 ; 1 ;
; Mux2~2 ; 1 ;
@@ -741,36 +752,33 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; RDD[2] ; 1 ;
; RDD[1] ; 1 ;
; RDD[0] ; 1 ;
-; IS.state_bit_2~1 ; 1 ;
-; IS.state_bit_2~0 ; 1 ;
-; Equal1~4 ; 1 ;
+; MOSIOE ; 1 ;
+; IS.101~0 ; 1 ;
; AddrIncH ; 1 ;
; always7~2 ; 1 ;
; RAMSpecSEL~1 ; 1 ;
; RAMSpecSEL~0 ; 1 ;
-; IS.state_bit_1~2 ; 1 ;
+; IS.state_bit_2~2 ; 1 ;
+; IS.state_bit_2~1 ; 1 ;
; IS.state_bit_1~1 ; 1 ;
-; IS.state_bit_0~5 ; 1 ;
-; IS.state_bit_0~4 ; 1 ;
-; Equal4~0 ; 1 ;
-; Equal1~1 ; 1 ;
-; Equal1~0 ; 1 ;
-; IS.111~0 ; 1 ;
-; MOSIOE ; 1 ;
-; IS.101~0 ; 1 ;
+; IS.state_bit_1~0 ; 1 ;
+; IS.state_bit_0~1 ; 1 ;
+; IS.state_bit_0~0 ; 1 ;
+; Equal3~0 ; 1 ;
+; Equal1~2 ; 1 ;
+; FCKout ; 1 ;
+; FCS ; 1 ;
+; Mux11~5 ; 1 ;
; Mux11~4 ; 1 ;
-; Mux11~3 ; 1 ;
; PHI0r1 ; 1 ;
+; Mux11~3 ; 1 ;
; Mux11~2 ; 1 ;
-; Mux11~1 ; 1 ;
-; Mux11~0 ; 1 ;
; Selector1~0 ; 1 ;
; Selector0~0 ; 1 ;
; Addr[0]~47COUT1_92 ; 1 ;
; Addr[0]~47 ; 1 ;
; Mux12~3 ; 1 ;
; nRCS~5 ; 1 ;
-; nRCS~3 ; 1 ;
; Mux12~1 ; 1 ;
; Mux12~0 ; 1 ;
; Addr[22]~45COUT1_78 ; 1 ;
@@ -779,6 +787,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Addr[21]~43 ; 1 ;
; Mux15~1 ; 1 ;
; Mux15~0 ; 1 ;
+; SA[2]~13 ; 1 ;
; Addr[19]~39COUT1_74 ; 1 ;
; Addr[19]~39 ; 1 ;
; Mux16~2 ; 1 ;
@@ -806,10 +815,12 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Mux18~0 ; 1 ;
; Addr[16]~27COUT1_68 ; 1 ;
; Addr[16]~27 ; 1 ;
+; Mux19~3 ; 1 ;
; Mux19~2 ; 1 ;
-; Mux19~1 ; 1 ;
; Addr[6]~25COUT1_102 ; 1 ;
; Addr[6]~25 ; 1 ;
+; Mux19~1 ; 1 ;
+; Mux19~0 ; 1 ;
; Mux20~2 ; 1 ;
; Addr[5]~21COUT1_100 ; 1 ;
; Addr[5]~21 ; 1 ;
@@ -843,32 +854,32 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; LS[2]~7 ; 1 ;
; Mux23~2 ; 1 ;
; Mux23~1 ; 1 ;
-; WRD[5] ; 1 ;
; Mux23~0 ; 1 ;
; Addr[11]~7COUT1_86 ; 1 ;
; Addr[11]~7 ; 1 ;
-; WRD[4] ; 1 ;
; Addr[1]~5COUT1_94 ; 1 ;
; Addr[1]~5 ; 1 ;
; Mux24~3 ; 1 ;
; Mux24~2 ; 1 ;
; Mux24~1 ; 1 ;
-; WRD[3] ; 1 ;
+; WRD[5] ; 1 ;
; Mux24~0 ; 1 ;
; LS[10]~1COUT1_52 ; 1 ;
; LS[10]~1 ; 1 ;
+; WRD[4] ; 1 ;
; Addr[10]~3COUT1_84 ; 1 ;
; Addr[10]~3 ; 1 ;
+; Mux13~0 ; 1 ;
+; WRD[3] ; 1 ;
; WRD[2] ; 1 ;
+; Mux14~5 ; 1 ;
+; Mux14~4 ; 1 ;
; WRD[1] ; 1 ;
; WRD[0] ; 1 ;
-; Mux14~7 ; 1 ;
-; Mux14~6 ; 1 ;
; nRESr0 ; 1 ;
+; Mux14~2 ; 1 ;
; always5~1 ; 1 ;
; always5~0 ; 1 ;
-; FCK~reg0 ; 1 ;
-; FCS ; 1 ;
; RCKE~reg0 ; 1 ;
; DQMH~reg0 ; 1 ;
; DQML~reg0 ; 1 ;
@@ -901,96 +912,94 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+-----------------------------+--------------------+
; Other Routing Resource Type ; Usage ;
+-----------------------------+--------------------+
-; C4s ; 250 / 784 ( 32 % ) ;
-; Direct links ; 69 / 888 ( 8 % ) ;
+; C4s ; 281 / 784 ( 36 % ) ;
+; Direct links ; 63 / 888 ( 7 % ) ;
; Global clocks ; 3 / 4 ( 75 % ) ;
-; LAB clocks ; 12 / 32 ( 38 % ) ;
-; LUT chains ; 40 / 216 ( 19 % ) ;
-; Local interconnects ; 460 / 888 ( 52 % ) ;
-; R4s ; 312 / 704 ( 44 % ) ;
+; LAB clocks ; 11 / 32 ( 34 % ) ;
+; LUT chains ; 34 / 216 ( 16 % ) ;
+; Local interconnects ; 483 / 888 ( 54 % ) ;
+; R4s ; 341 / 704 ( 48 % ) ;
+-----------------------------+--------------------+
+---------------------------------------------------------------------------+
; LAB Logic Elements ;
+--------------------------------------------+------------------------------+
-; Number of Logic Elements (Average = 9.46) ; Number of LABs (Total = 24) ;
+; Number of Logic Elements (Average = 9.54) ; Number of LABs (Total = 24) ;
+--------------------------------------------+------------------------------+
; 1 ; 0 ;
; 2 ; 0 ;
-; 3 ; 1 ;
+; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
-; 6 ; 0 ;
+; 6 ; 2 ;
; 7 ; 0 ;
-; 8 ; 2 ;
-; 9 ; 2 ;
-; 10 ; 19 ;
+; 8 ; 1 ;
+; 9 ; 1 ;
+; 10 ; 20 ;
+--------------------------------------------+------------------------------+
+-------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+------------------------------+
-; LAB-wide Signals (Average = 1.83) ; Number of LABs (Total = 24) ;
+; LAB-wide Signals (Average = 1.75) ; Number of LABs (Total = 24) ;
+------------------------------------+------------------------------+
-; 1 Async. clear ; 5 ;
-; 1 Clock ; 21 ;
-; 1 Clock enable ; 8 ;
-; 1 Sync. clear ; 4 ;
+; 1 Async. clear ; 6 ;
+; 1 Clock ; 22 ;
+; 1 Clock enable ; 3 ;
+; 1 Sync. clear ; 6 ;
; 1 Sync. load ; 2 ;
; 2 Clock enables ; 1 ;
-; 2 Clocks ; 3 ;
+; 2 Clocks ; 2 ;
+------------------------------------+------------------------------+
+-----------------------------------------------------------------------------+
; LAB Signals Sourced ;
+----------------------------------------------+------------------------------+
-; Number of Signals Sourced (Average = 10.00) ; Number of LABs (Total = 24) ;
+; Number of Signals Sourced (Average = 10.08) ; Number of LABs (Total = 24) ;
+----------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
-; 3 ; 1 ;
+; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
-; 6 ; 0 ;
+; 6 ; 2 ;
; 7 ; 0 ;
-; 8 ; 2 ;
-; 9 ; 2 ;
-; 10 ; 11 ;
-; 11 ; 5 ;
-; 12 ; 2 ;
-; 13 ; 0 ;
-; 14 ; 1 ;
+; 8 ; 0 ;
+; 9 ; 1 ;
+; 10 ; 14 ;
+; 11 ; 3 ;
+; 12 ; 4 ;
+----------------------------------------------+------------------------------+
+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+------------------------------+
-; Number of Signals Sourced Out (Average = 7.04) ; Number of LABs (Total = 24) ;
+; Number of Signals Sourced Out (Average = 6.83) ; Number of LABs (Total = 24) ;
+-------------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 1 ;
-; 3 ; 2 ;
+; 3 ; 3 ;
; 4 ; 2 ;
-; 5 ; 3 ;
-; 6 ; 3 ;
-; 7 ; 0 ;
-; 8 ; 5 ;
-; 9 ; 3 ;
-; 10 ; 2 ;
-; 11 ; 3 ;
+; 5 ; 2 ;
+; 6 ; 4 ;
+; 7 ; 1 ;
+; 8 ; 0 ;
+; 9 ; 7 ;
+; 10 ; 3 ;
+; 11 ; 1 ;
+-------------------------------------------------+------------------------------+
+-----------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+----------------------------------------------+------------------------------+
-; Number of Distinct Inputs (Average = 16.50) ; Number of LABs (Total = 24) ;
+; Number of Distinct Inputs (Average = 17.04) ; Number of LABs (Total = 24) ;
+----------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
@@ -1000,22 +1009,24 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 1 ;
-; 8 ; 1 ;
-; 9 ; 0 ;
-; 10 ; 0 ;
+; 8 ; 0 ;
+; 9 ; 1 ;
+; 10 ; 1 ;
; 11 ; 1 ;
-; 12 ; 0 ;
-; 13 ; 5 ;
-; 14 ; 1 ;
-; 15 ; 0 ;
-; 16 ; 4 ;
+; 12 ; 1 ;
+; 13 ; 1 ;
+; 14 ; 2 ;
+; 15 ; 3 ;
+; 16 ; 1 ;
; 17 ; 1 ;
; 18 ; 0 ;
; 19 ; 1 ;
; 20 ; 3 ;
-; 21 ; 2 ;
-; 22 ; 3 ;
+; 21 ; 1 ;
+; 22 ; 2 ;
; 23 ; 1 ;
+; 24 ; 1 ;
+; 25 ; 2 ;
+----------------------------------------------+------------------------------+
@@ -1048,7 +1059,7 @@ This will disable optimization of problematic paths and expose them for further
+-----------------+----------------------+-------------------+
; Source Register ; Destination Register ; Delay Added in ns ;
+-----------------+----------------------+-------------------+
-; PHI0 ; PHI0r1 ; 0.069 ;
+; PHI0 ; PHI0r1 ; 0.507 ;
+-----------------+----------------------+-------------------+
Note: This table only shows the top 1 path(s) that have the largest delay added for hold.
@@ -1056,7 +1067,7 @@ Note: This table only shows the top 1 path(s) that have the largest delay added
+-----------------+
; Fitter Messages ;
+-----------------+
-Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
+Warning (20028): Parallel compilation is not licensed and has been disabled
Info (119006): Selected device EPM240T100C5 for design "GR8RAM"
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
@@ -1068,8 +1079,6 @@ Info (176444): Device migration not selected. If you intend to use device migrat
Info (176445): Device EPM570T100C5 is compatible
Info (176445): Device EPM570T100I5 is compatible
Info (176445): Device EPM570T100A5 is compatible
-Critical Warning (169085): No exact pin location assignment(s) for 1 pins of 69 total pins
- Info (169086): Pin RDdir not assigned to an exact location on the device
Critical Warning (332012): Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332144): No user constrained base clocks found in the design
Info (332128): Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
@@ -1091,40 +1100,30 @@ Info (176234): Starting register packing
Info (186468): Started processing fast register assignments
Info (186469): Finished processing fast register assignments
Info (176235): Finished register packing
-Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
- Info (176211): Number of I/O pins in group: 1 (unused VREF, 3.3V VCCIO, 0 input, 1 output, 0 bidirectional)
- Info (176212): I/O standards used: 3.3-V LVTTL.
-Info (176215): I/O bank details before I/O pin placement
- Info (176214): Statistics of I/O banks
- Info (176213): I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 26 total pin(s) used -- 12 pins available
- Info (176213): I/O bank number 2 does not use VREF pins and has 3.3V VCCIO pins. 42 total pin(s) used -- 0 pins available
-Warning (15705): Ignored locations or region assignments to the following nodes
- Warning (15706): Node "Ddir" is assigned to location or region, but does not exist in design
-Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
+Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00
Info (170189): Fitter placement preparation operations beginning
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
Info (170191): Fitter placement operations beginning
Info (170137): Fitter placement was successful
-Info (170192): Fitter placement operations ending: elapsed time is 00:00:02
+Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
Info (170193): Fitter routing operations beginning
-Info (170195): Router estimated average interconnect usage is 32% of the available device resources
- Info (170196): Router estimated peak interconnect usage is 32% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
+Info (170195): Router estimated average interconnect usage is 34% of the available device resources
+ Info (170196): Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
-Info (11888): Total time spent on timing analysis during the Fitter is 0.53 seconds.
+Info (11888): Total time spent on timing analysis during the Fitter is 0.27 seconds.
Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
-Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
-Info (144001): Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg
-Info: Quartus II 32-bit Fitter was successful. 0 errors, 7 warnings
- Info: Peak virtual memory: 382 megabytes
- Info: Processing ended: Sun Apr 11 13:22:35 2021
- Info: Elapsed time: 00:00:11
- Info: Total CPU time (on all processors): 00:00:09
+Info (144001): Generated suppressed messages file C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.fit.smsg
+Info: Quartus II 64-Bit Fitter was successful. 0 errors, 4 warnings
+ Info: Peak virtual memory: 547 megabytes
+ Info: Processing ended: Sun Apr 18 03:45:24 2021
+ Info: Elapsed time: 00:00:03
+ Info: Total CPU time (on all processors): 00:00:03
+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
-The suppressed messages can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg.
+The suppressed messages can be found in C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.fit.smsg.
diff --git a/cpld/output_files/GR8RAM.fit.summary b/cpld/output_files/GR8RAM.fit.summary
index f5eba1f..9f627aa 100755
--- a/cpld/output_files/GR8RAM.fit.summary
+++ b/cpld/output_files/GR8RAM.fit.summary
@@ -1,11 +1,11 @@
-Fitter Status : Successful - Sun Apr 11 13:22:34 2021
-Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+Fitter Status : Successful - Sun Apr 18 03:45:24 2021
+Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
Revision Name : GR8RAM
Top-level Entity Name : GR8RAM
Family : MAX II
Device : EPM240T100C5
Timing Models : Final
-Total logic elements : 227 / 240 ( 95 % )
-Total pins : 69 / 80 ( 86 % )
+Total logic elements : 229 / 240 ( 95 % )
+Total pins : 80 / 80 ( 100 % )
Total virtual pins : 0
UFM blocks : 0 / 1 ( 0 % )
diff --git a/cpld/output_files/GR8RAM.flow.rpt b/cpld/output_files/GR8RAM.flow.rpt
index f4bd9d6..6492a6e 100755
--- a/cpld/output_files/GR8RAM.flow.rpt
+++ b/cpld/output_files/GR8RAM.flow.rpt
@@ -1,6 +1,6 @@
Flow report for GR8RAM
-Sun Apr 11 13:22:47 2021
-Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+Sun Apr 18 03:45:27 2021
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
---------------------
@@ -40,15 +40,15 @@ applicable agreement for further details.
+-----------------------------------------------------------------------------+
; Flow Summary ;
+---------------------------+-------------------------------------------------+
-; Flow Status ; Successful - Sun Apr 11 13:22:41 2021 ;
-; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
+; Flow Status ; Successful - Sun Apr 18 03:45:25 2021 ;
+; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name ; GR8RAM ;
; Top-level Entity Name ; GR8RAM ;
; Family ; MAX II ;
; Device ; EPM240T100C5 ;
; Timing Models ; Final ;
-; Total logic elements ; 227 / 240 ( 95 % ) ;
-; Total pins ; 69 / 80 ( 86 % ) ;
+; Total logic elements ; 229 / 240 ( 95 % ) ;
+; Total pins ; 80 / 80 ( 100 % ) ;
; Total virtual pins ; 0 ;
; UFM blocks ; 0 / 1 ( 0 % ) ;
+---------------------------+-------------------------------------------------+
@@ -59,42 +59,42 @@ applicable agreement for further details.
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
-; Start date & time ; 04/11/2021 13:22:17 ;
+; Start date & time ; 04/18/2021 03:45:19 ;
; Main task ; Compilation ;
; Revision Name ; GR8RAM ;
+-------------------+---------------------+
-+-----------------------------------------------------------------------------------------------------------------------------+
-; Flow Non-Default Global Settings ;
-+-------------------------------------------------+--------------------------------+---------------+-------------+------------+
-; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
-+-------------------------------------------------+--------------------------------+---------------+-------------+------------+
-; ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ; On ; Off ; -- ; -- ;
-; ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES ; Always ; Auto ; -- ; -- ;
-; ALM_REGISTER_PACKING_EFFORT ; High ; Medium ; -- ; -- ;
-; AUTO_PACKED_REGISTERS_MAXII ; Minimize Area ; Auto ; -- ; -- ;
-; AUTO_RESOURCE_SHARING ; On ; Off ; -- ; -- ;
-; COMPILER_SIGNATURE_ID ; 44085571633675.161816173700648 ; -- ; -- ; -- ;
-; FINAL_PLACEMENT_OPTIMIZATION ; Always ; Automatically ; -- ; -- ;
-; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ;
-; IOBANK_VCCIO ; 3.3V ; -- ; -- ; 1 ;
-; IOBANK_VCCIO ; 3.3V ; -- ; -- ; 2 ;
-; MAXII_OPTIMIZATION_TECHNIQUE ; Area ; Balanced ; -- ; -- ;
-; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
-; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
-; MUX_RESTRUCTURE ; On ; Auto ; -- ; -- ;
-; PLACEMENT_EFFORT_MULTIPLIER ; 2.0 ; 1.0 ; -- ; -- ;
-; POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR ; 3.3V ; -- ; -- ; -- ;
-; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
-; REMOVE_REDUNDANT_LOGIC_CELLS ; On ; Off ; -- ; -- ;
-; ROUTER_EFFORT_MULTIPLIER ; 2.0 ; 1.0 ; -- ; -- ;
-; ROUTER_REGISTER_DUPLICATION ; Off ; Auto ; -- ; -- ;
-; SEED ; 235 ; 1 ; -- ; -- ;
-; STATE_MACHINE_PROCESSING ; Minimal Bits ; Auto ; -- ; -- ;
-; SYNTHESIS_SEED ; 123 ; 1 ; -- ; -- ;
-; SYNTH_TIMING_DRIVEN_SYNTHESIS ; Off ; -- ; -- ; -- ;
-+-------------------------------------------------+--------------------------------+---------------+-------------+------------+
++---------------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings ;
++-------------------------------------------------+------------------------------+---------------+-------------+------------+
+; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
++-------------------------------------------------+------------------------------+---------------+-------------+------------+
+; ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ; On ; Off ; -- ; -- ;
+; ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES ; Always ; Auto ; -- ; -- ;
+; ALM_REGISTER_PACKING_EFFORT ; High ; Medium ; -- ; -- ;
+; AUTO_PACKED_REGISTERS_MAXII ; Minimize Area ; Auto ; -- ; -- ;
+; AUTO_RESOURCE_SHARING ; On ; Off ; -- ; -- ;
+; COMPILER_SIGNATURE_ID ; 136298148942.161873191903592 ; -- ; -- ; -- ;
+; FINAL_PLACEMENT_OPTIMIZATION ; Always ; Automatically ; -- ; -- ;
+; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ;
+; IOBANK_VCCIO ; 3.3V ; -- ; -- ; 1 ;
+; IOBANK_VCCIO ; 3.3V ; -- ; -- ; 2 ;
+; MAXII_OPTIMIZATION_TECHNIQUE ; Area ; Balanced ; -- ; -- ;
+; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
+; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
+; MUX_RESTRUCTURE ; On ; Auto ; -- ; -- ;
+; PLACEMENT_EFFORT_MULTIPLIER ; 2.0 ; 1.0 ; -- ; -- ;
+; POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR ; 3.3V ; -- ; -- ; -- ;
+; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
+; REMOVE_REDUNDANT_LOGIC_CELLS ; On ; Off ; -- ; -- ;
+; ROUTER_EFFORT_MULTIPLIER ; 2.0 ; 1.0 ; -- ; -- ;
+; ROUTER_REGISTER_DUPLICATION ; Off ; Auto ; -- ; -- ;
+; SEED ; 235 ; 1 ; -- ; -- ;
+; STATE_MACHINE_PROCESSING ; Minimal Bits ; Auto ; -- ; -- ;
+; SYNTHESIS_SEED ; 123 ; 1 ; -- ; -- ;
+; SYNTH_TIMING_DRIVEN_SYNTHESIS ; Off ; -- ; -- ; -- ;
++-------------------------------------------------+------------------------------+---------------+-------------+------------+
+-------------------------------------------------------------------------------------------------------------------------------+
@@ -102,24 +102,24 @@ applicable agreement for further details.
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis ; 00:00:06 ; 1.0 ; 301 MB ; 00:00:06 ;
-; Fitter ; 00:00:10 ; 1.4 ; 382 MB ; 00:00:09 ;
-; Assembler ; 00:00:03 ; 1.0 ; 292 MB ; 00:00:03 ;
-; TimeQuest Timing Analyzer ; 00:00:04 ; 1.0 ; 278 MB ; 00:00:04 ;
-; Total ; 00:00:23 ; -- ; -- ; 00:00:22 ;
+; Analysis & Synthesis ; 00:00:01 ; 1.0 ; 421 MB ; 00:00:01 ;
+; Fitter ; 00:00:03 ; 1.0 ; 547 MB ; 00:00:03 ;
+; Assembler ; 00:00:01 ; 1.0 ; 381 MB ; 00:00:00 ;
+; TimeQuest Timing Analyzer ; 00:00:01 ; 1.0 ; 368 MB ; 00:00:01 ;
+; Total ; 00:00:06 ; -- ; -- ; 00:00:05 ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
-+-----------------------------------------------------------------------------------------+
-; Flow OS Summary ;
-+---------------------------+------------------+------------+------------+----------------+
-; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
-+---------------------------+------------------+------------+------------+----------------+
-; Analysis & Synthesis ; zane-c8bbf8aef2 ; Windows XP ; 5.1 ; i686 ;
-; Fitter ; zane-c8bbf8aef2 ; Windows XP ; 5.1 ; i686 ;
-; Assembler ; zane-c8bbf8aef2 ; Windows XP ; 5.1 ; i686 ;
-; TimeQuest Timing Analyzer ; zane-c8bbf8aef2 ; Windows XP ; 5.1 ; i686 ;
-+---------------------------+------------------+------------+------------+----------------+
++----------------------------------------------------------------------------------------+
+; Flow OS Summary ;
++---------------------------+------------------+-----------+------------+----------------+
+; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
++---------------------------+------------------+-----------+------------+----------------+
+; Analysis & Synthesis ; Dog-PC ; Windows 7 ; 6.1 ; x86_64 ;
+; Fitter ; Dog-PC ; Windows 7 ; 6.1 ; x86_64 ;
+; Assembler ; Dog-PC ; Windows 7 ; 6.1 ; x86_64 ;
+; TimeQuest Timing Analyzer ; Dog-PC ; Windows 7 ; 6.1 ; x86_64 ;
++---------------------------+------------------+-----------+------------+----------------+
------------
diff --git a/cpld/output_files/GR8RAM.jdi b/cpld/output_files/GR8RAM.jdi
index ca0a2c1..3f1d964 100755
--- a/cpld/output_files/GR8RAM.jdi
+++ b/cpld/output_files/GR8RAM.jdi
@@ -1,6 +1,6 @@
-
+
diff --git a/cpld/output_files/GR8RAM.map.rpt b/cpld/output_files/GR8RAM.map.rpt
index 7d7b7e8..8db2d70 100755
--- a/cpld/output_files/GR8RAM.map.rpt
+++ b/cpld/output_files/GR8RAM.map.rpt
@@ -1,6 +1,6 @@
Analysis & Synthesis report for GR8RAM
-Sun Apr 11 13:22:21 2021
-Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+Sun Apr 18 03:45:20 2021
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
---------------------
@@ -45,13 +45,13 @@ applicable agreement for further details.
+-------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+-------------------------------------------------+
-; Analysis & Synthesis Status ; Successful - Sun Apr 11 13:22:21 2021 ;
-; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
+; Analysis & Synthesis Status ; Successful - Sun Apr 18 03:45:20 2021 ;
+; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name ; GR8RAM ;
; Top-level Entity Name ; GR8RAM ;
; Family ; MAX II ;
-; Total logic elements ; 240 ;
-; Total pins ; 69 ;
+; Total logic elements ; 242 ;
+; Total pins ; 80 ;
; Total virtual pins ; 0 ;
; UFM blocks ; 0 / 1 ( 0 % ) ;
+-----------------------------+-------------------------------------------------+
@@ -130,30 +130,24 @@ applicable agreement for further details.
+----------------------------------------------------------------------------+--------------------+--------------------+
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 2 ;
-; Maximum allowed ; 2 ;
-; ; ;
-; Average used ; 1.00 ;
-; Maximum used ; 1 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-; Processor 2 ; 0.0% ;
-+----------------------------+-------------+
+Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
++-------------------------------------+
+; Parallel Compilation ;
++----------------------------+--------+
+; Processors ; Number ;
++----------------------------+--------+
+; Number detected on machine ; 12 ;
+; Maximum allowed ; 1 ;
++----------------------------+--------+
-+-----------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Source Files Read ;
-+----------------------------------+-----------------+------------------------+-------------------------------+---------+
-; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
-+----------------------------------+-----------------+------------------------+-------------------------------+---------+
-; GR8RAM.v ; yes ; User Verilog HDL File ; Z:/Repos/GR8RAM/cpld/GR8RAM.v ; ;
-+----------------------------------+-----------------+------------------------+-------------------------------+---------+
++--------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read ;
++----------------------------------+-----------------+------------------------+----------------------------------------------------+---------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
++----------------------------------+-----------------+------------------------+----------------------------------------------------+---------+
+; GR8RAM.v ; yes ; User Verilog HDL File ; C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v ; ;
++----------------------------------+-----------------+------------------------+----------------------------------------------------+---------+
+-----------------------------------------------------+
@@ -161,33 +155,33 @@ applicable agreement for further details.
+---------------------------------------------+-------+
; Resource ; Usage ;
+---------------------------------------------+-------+
-; Total logic elements ; 240 ;
-; -- Combinational with no register ; 138 ;
+; Total logic elements ; 242 ;
+; -- Combinational with no register ; 139 ;
; -- Register only ; 14 ;
-; -- Combinational with a register ; 88 ;
+; -- Combinational with a register ; 89 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
-; -- 4 input functions ; 130 ;
+; -- 4 input functions ; 135 ;
; -- 3 input functions ; 30 ;
-; -- 2 input functions ; 66 ;
+; -- 2 input functions ; 63 ;
; -- 1 input functions ; 0 ;
; -- 0 input functions ; 0 ;
; ; ;
; Logic elements by mode ; ;
-; -- normal mode ; 207 ;
+; -- normal mode ; 209 ;
; -- arithmetic mode ; 33 ;
; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 35 ;
; -- asynchronous clear/load mode ; 30 ;
; ; ;
-; Total registers ; 102 ;
+; Total registers ; 103 ;
; Total logic cells in carry chains ; 37 ;
-; I/O pins ; 69 ;
+; I/O pins ; 80 ;
; Maximum fan-out node ; C25M ;
-; Maximum fan-out ; 99 ;
-; Total fan-out ; 1036 ;
-; Average fan-out ; 3.35 ;
+; Maximum fan-out ; 100 ;
+; Total fan-out ; 1055 ;
+; Average fan-out ; 3.28 ;
+---------------------------------------------+-------+
@@ -196,7 +190,7 @@ applicable agreement for further details.
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
-; |GR8RAM ; 240 (240) ; 102 ; 0 ; 69 ; 0 ; 138 (138) ; 14 (14) ; 88 (88) ; 37 (37) ; 0 (0) ; |GR8RAM ; work ;
+; |GR8RAM ; 242 (242) ; 103 ; 0 ; 80 ; 0 ; 139 (139) ; 14 (14) ; 89 (89) ; 37 (37) ; 0 (0) ; |GR8RAM ; work ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
@@ -209,6 +203,8 @@ Encoding Type: Minimal Bits
+--------+----------------+----------------+----------------+
; IS.000 ; 0 ; 0 ; 0 ;
; IS.001 ; 0 ; 0 ; 1 ;
+; IS.010 ; 1 ; 1 ; 0 ;
+; IS.011 ; 1 ; 1 ; 1 ;
; IS.100 ; 1 ; 0 ; 0 ;
; IS.101 ; 1 ; 0 ; 1 ;
; IS.110 ; 0 ; 1 ; 0 ;
@@ -221,7 +217,7 @@ Encoding Type: Minimal Bits
+---------------------------------------+--------------------+
; Register name ; Reason for Removal ;
+---------------------------------------+--------------------+
-; IS~10 ; Lost fanout ;
+; IS~12 ; Lost fanout ;
; Total Number of Removed Registers = 1 ; ;
+---------------------------------------+--------------------+
@@ -231,7 +227,7 @@ Encoding Type: Minimal Bits
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
-; Total registers ; 102 ;
+; Total registers ; 103 ;
; Number of registers using Synchronous Clear ; 10 ;
; Number of registers using Synchronous Load ; 25 ;
; Number of registers using Asynchronous Clear ; 30 ;
@@ -262,16 +258,16 @@ Encoding Type: Minimal Bits
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
-; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |GR8RAM|PS[1] ;
-; 5:1 ; 2 bits ; 6 LEs ; 2 LEs ; 4 LEs ; Yes ; |GR8RAM|SA[12]~reg0 ;
-; 20:1 ; 6 bits ; 78 LEs ; 24 LEs ; 54 LEs ; Yes ; |GR8RAM|SA[3]~reg0 ;
-; 20:1 ; 3 bits ; 39 LEs ; 18 LEs ; 21 LEs ; Yes ; |GR8RAM|SA[1]~reg0 ;
+; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |GR8RAM|PS[2] ;
+; 5:1 ; 2 bits ; 6 LEs ; 2 LEs ; 4 LEs ; Yes ; |GR8RAM|SA[11]~reg0 ;
+; 20:1 ; 6 bits ; 78 LEs ; 24 LEs ; 54 LEs ; Yes ; |GR8RAM|SA[8]~reg0 ;
+; 20:1 ; 3 bits ; 39 LEs ; 18 LEs ; 21 LEs ; Yes ; |GR8RAM|SA[2]~reg0 ;
; 3:1 ; 6 bits ; 12 LEs ; 6 LEs ; 6 LEs ; Yes ; |GR8RAM|WRD[0] ;
; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |GR8RAM|WRD[7] ;
-; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |GR8RAM|RDD[1] ;
-; 5:1 ; 4 bits ; 12 LEs ; 8 LEs ; 4 LEs ; Yes ; |GR8RAM|RDD[4] ;
+; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |GR8RAM|RDD[2] ;
+; 5:1 ; 4 bits ; 12 LEs ; 8 LEs ; 4 LEs ; Yes ; |GR8RAM|RDD[7] ;
; 18:1 ; 2 bits ; 24 LEs ; 8 LEs ; 16 LEs ; Yes ; |GR8RAM|DQMH~reg0 ;
-; 8:1 ; 5 bits ; 25 LEs ; 20 LEs ; 5 LEs ; No ; |GR8RAM|IS ;
+; 8:1 ; 7 bits ; 35 LEs ; 28 LEs ; 7 LEs ; No ; |GR8RAM|IS ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
@@ -279,37 +275,45 @@ Encoding Type: Minimal Bits
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
-Info: Running Quartus II 32-bit Analysis & Synthesis
+Info: Running Quartus II 64-Bit Analysis & Synthesis
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
- Info: Processing started: Sun Apr 11 13:22:15 2021
+ Info: Processing started: Sun Apr 18 03:45:19 2021
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM
-Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
+Warning (20028): Parallel compilation is not licensed and has been disabled
Info (12021): Found 1 design units, including 1 entities, in source file gr8ram.v
Info (12023): Found entity 1: GR8RAM
Info (12127): Elaborating entity "GR8RAM" for the top level hierarchy
-Warning (10230): Verilog HDL assignment warning at GR8RAM.v(20): truncated value with size 32 to match size of target (14)
-Warning (10230): Verilog HDL assignment warning at GR8RAM.v(103): truncated value with size 32 to match size of target (8)
-Warning (10230): Verilog HDL assignment warning at GR8RAM.v(111): truncated value with size 32 to match size of target (8)
-Warning (10230): Verilog HDL assignment warning at GR8RAM.v(118): truncated value with size 32 to match size of target (8)
-Warning (10230): Verilog HDL assignment warning at GR8RAM.v(307): truncated value with size 32 to match size of target (4)
+Warning (10230): Verilog HDL assignment warning at GR8RAM.v(34): truncated value with size 32 to match size of target (14)
+Warning (10230): Verilog HDL assignment warning at GR8RAM.v(117): truncated value with size 32 to match size of target (8)
+Warning (10230): Verilog HDL assignment warning at GR8RAM.v(125): truncated value with size 32 to match size of target (8)
+Warning (10230): Verilog HDL assignment warning at GR8RAM.v(132): truncated value with size 32 to match size of target (8)
+Warning (10230): Verilog HDL assignment warning at GR8RAM.v(324): truncated value with size 32 to match size of target (4)
Info (17026): Resynthesizing 0 WYSIWYG logic cells and I/Os using "area" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched
+Warning (13024): Output pins are stuck at VCC or GND
+ Warning (13410): Pin "RAdir" is stuck at VCC
+ Warning (13410): Pin "nDMAout" is stuck at VCC
+ Warning (13410): Pin "nNMIout" is stuck at VCC
+ Warning (13410): Pin "nIRQout" is stuck at VCC
+ Warning (13410): Pin "nRDYout" is stuck at VCC
+ Warning (13410): Pin "nINHout" is stuck at VCC
+ Warning (13410): Pin "RWout" is stuck at VCC
Info (17049): 1 registers lost all their fanouts during netlist optimizations.
-Info (21057): Implemented 309 device resources after synthesis - the final resource count might be different
- Info (21058): Implemented 26 input pins
- Info (21059): Implemented 26 output pins
+Info (21057): Implemented 322 device resources after synthesis - the final resource count might be different
+ Info (21058): Implemented 28 input pins
+ Info (21059): Implemented 35 output pins
Info (21060): Implemented 17 bidirectional pins
- Info (21061): Implemented 240 logic cells
-Info (144001): Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg
-Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 5 warnings
- Info: Peak virtual memory: 301 megabytes
- Info: Processing ended: Sun Apr 11 13:22:21 2021
- Info: Elapsed time: 00:00:06
- Info: Total CPU time (on all processors): 00:00:06
+ Info (21061): Implemented 242 logic cells
+Info (144001): Generated suppressed messages file C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg
+Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 14 warnings
+ Info: Peak virtual memory: 421 megabytes
+ Info: Processing ended: Sun Apr 18 03:45:20 2021
+ Info: Elapsed time: 00:00:01
+ Info: Total CPU time (on all processors): 00:00:01
+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
-The suppressed messages can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg.
+The suppressed messages can be found in C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg.
diff --git a/cpld/output_files/GR8RAM.map.smsg b/cpld/output_files/GR8RAM.map.smsg
index b5fdf9b..35952bc 100755
--- a/cpld/output_files/GR8RAM.map.smsg
+++ b/cpld/output_files/GR8RAM.map.smsg
@@ -1,2 +1,2 @@
-Warning (10273): Verilog HDL warning at GR8RAM.v(79): extended using "x" or "z"
-Warning (10273): Verilog HDL warning at GR8RAM.v(256): extended using "x" or "z"
+Warning (10273): Verilog HDL warning at GR8RAM.v(93): extended using "x" or "z"
+Warning (10273): Verilog HDL warning at GR8RAM.v(273): extended using "x" or "z"
diff --git a/cpld/output_files/GR8RAM.map.summary b/cpld/output_files/GR8RAM.map.summary
index 33c6241..6acbb30 100755
--- a/cpld/output_files/GR8RAM.map.summary
+++ b/cpld/output_files/GR8RAM.map.summary
@@ -1,9 +1,9 @@
-Analysis & Synthesis Status : Successful - Sun Apr 11 13:22:21 2021
-Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+Analysis & Synthesis Status : Successful - Sun Apr 18 03:45:20 2021
+Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
Revision Name : GR8RAM
Top-level Entity Name : GR8RAM
Family : MAX II
-Total logic elements : 240
-Total pins : 69
+Total logic elements : 242
+Total pins : 80
Total virtual pins : 0
UFM blocks : 0 / 1 ( 0 % )
diff --git a/cpld/output_files/GR8RAM.pin b/cpld/output_files/GR8RAM.pin
index 9b0c064..6d11d91 100755
--- a/cpld/output_files/GR8RAM.pin
+++ b/cpld/output_files/GR8RAM.pin
@@ -57,7 +57,7 @@
-- Pin directions (input, output or bidir) are based on device operating in user mode.
---------------------------------------------------------------------------------
-Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
CHIP "GR8RAM" ASSIGNED TO AN: EPM240T100C5
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
@@ -78,23 +78,23 @@ VCCINT : 13 : power : : 2.5V/3.3
RA[10] : 14 : input : 3.3-V LVTTL : : 1 : Y
MOSI : 15 : bidir : 3.3-V LVTTL : : 1 : Y
MISO : 16 : input : 3.3-V LVTTL : : 1 : Y
-RDdir : 17 : output : 3.3-V LVTTL : : 1 : N
-GND* : 18 : : : : 1 :
-GND* : 19 : : : : 1 :
-GND* : 20 : : : : 1 :
-GND* : 21 : : : : 1 :
+RDdir : 17 : output : 3.3-V LVTTL : : 1 : Y
+DMAout : 18 : output : 3.3-V LVTTL : : 1 : Y
+RAdir : 19 : output : 3.3-V LVTTL : : 1 : Y
+INTout : 20 : output : 3.3-V LVTTL : : 1 : Y
+nDMAout : 21 : output : 3.3-V LVTTL : : 1 : Y
TMS : 22 : input : : : 1 :
TDI : 23 : input : : : 1 :
TCK : 24 : input : : : 1 :
TDO : 25 : output : : : 1 :
-GND* : 26 : : : : 1 :
-GND* : 27 : : : : 1 :
-GND* : 28 : : : : 1 :
-GND* : 29 : : : : 1 :
+nNMIout : 26 : output : 3.3-V LVTTL : : 1 : Y
+nINHout : 27 : output : 3.3-V LVTTL : : 1 : Y
+nRDYout : 28 : output : 3.3-V LVTTL : : 1 : Y
+nIRQout : 29 : output : 3.3-V LVTTL : : 1 : Y
nRESout : 30 : output : 3.3-V LVTTL : : 1 : Y
VCCIO1 : 31 : power : : 3.3V : 1 :
GNDIO : 32 : gnd : : : :
-GND* : 33 : : : : 1 :
+RWout : 33 : output : 3.3-V LVTTL : : 1 : Y
RA[11] : 34 : input : 3.3-V LVTTL : : 1 : Y
RA[12] : 35 : input : 3.3-V LVTTL : : 1 : Y
RA[13] : 36 : input : 3.3-V LVTTL : : 1 : Y
@@ -109,8 +109,8 @@ nRES : 44 : input : 3.3-V LVTTL :
VCCIO1 : 45 : power : : 3.3V : 1 :
GNDIO : 46 : gnd : : : :
SD[1] : 47 : bidir : 3.3-V LVTTL : : 1 : Y
-GND* : 48 : : : : 1 :
-GND* : 49 : : : : 1 :
+DMAin : 48 : input : 3.3-V LVTTL : : 1 : Y
+INTin : 49 : input : 3.3-V LVTTL : : 1 : Y
SD[0] : 50 : bidir : 3.3-V LVTTL : : 1 : Y
SD[4] : 51 : bidir : 3.3-V LVTTL : : 1 : Y
SD[5] : 52 : bidir : 3.3-V LVTTL : : 2 : Y
diff --git a/cpld/output_files/GR8RAM.pof b/cpld/output_files/GR8RAM.pof
index dc67a4e..a0b09c8 100755
Binary files a/cpld/output_files/GR8RAM.pof and b/cpld/output_files/GR8RAM.pof differ
diff --git a/cpld/output_files/GR8RAM.sta.rpt b/cpld/output_files/GR8RAM.sta.rpt
index 9139d12..3a8a4a8 100755
--- a/cpld/output_files/GR8RAM.sta.rpt
+++ b/cpld/output_files/GR8RAM.sta.rpt
@@ -1,6 +1,6 @@
TimeQuest Timing Analyzer report for GR8RAM
-Sun Apr 11 13:22:48 2021
-Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+Sun Apr 18 03:45:27 2021
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
---------------------
@@ -77,21 +77,15 @@ applicable agreement for further details.
+--------------------+-------------------------------------------------------------------+
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 2 ;
-; Maximum allowed ; 2 ;
-; ; ;
-; Average used ; 1.00 ;
-; Maximum used ; 2 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-; Processor 2 ; < 0.1% ;
-+----------------------------+-------------+
+Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
++-------------------------------------+
+; Parallel Compilation ;
++----------------------------+--------+
+; Processors ; Number ;
++----------------------------+--------+
+; Number detected on machine ; 12 ;
+; Maximum allowed ; 1 ;
++----------------------------+--------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
@@ -104,13 +98,13 @@ applicable agreement for further details.
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------+
-+--------------------------------------------------+
-; Fmax Summary ;
-+------------+-----------------+------------+------+
-; Fmax ; Restricted Fmax ; Clock Name ; Note ;
-+------------+-----------------+------------+------+
-; 101.47 MHz ; 101.47 MHz ; C25M ; ;
-+------------+-----------------+------------+------+
++-------------------------------------------------+
+; Fmax Summary ;
++-----------+-----------------+------------+------+
+; Fmax ; Restricted Fmax ; Clock Name ; Note ;
++-----------+-----------------+------------+------+
+; 98.64 MHz ; 98.64 MHz ; C25M ; ;
++-----------+-----------------+------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
@@ -119,8 +113,8 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
+-------+--------+---------------+
; Clock ; Slack ; End Point TNS ;
+-------+--------+---------------+
-; C25M ; -9.908 ; -697.920 ;
-; PHI0 ; -1.302 ; -1.302 ;
+; C25M ; -9.691 ; -732.295 ;
+; PHI0 ; -1.358 ; -1.358 ;
+-------+--------+---------------+
@@ -129,8 +123,8 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
+-------+-------+---------------+
; Clock ; Slack ; End Point TNS ;
+-------+-------+---------------+
-; PHI0 ; 1.012 ; 0.000 ;
-; C25M ; 1.288 ; 0.000 ;
+; PHI0 ; 1.092 ; 0.000 ;
+; C25M ; 1.418 ; 0.000 ;
+-------+-------+---------------+
@@ -139,7 +133,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
+-------+--------+---------------+
; Clock ; Slack ; End Point TNS ;
+-------+--------+---------------+
-; C25M ; -4.389 ; -131.670 ;
+; C25M ; -5.009 ; -150.270 ;
+-------+--------+---------------+
@@ -148,7 +142,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
+-------+-------+---------------+
; Clock ; Slack ; End Point TNS ;
+-------+-------+---------------+
-; C25M ; 4.835 ; 0.000 ;
+; C25M ; 5.455 ; 0.000 ;
+-------+-------+---------------+
@@ -167,106 +161,106 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
+--------+----------------+----------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------+----------------+--------------+-------------+--------------+------------+------------+
-; -9.908 ; ROMSpecSELr ; nRCS~reg0 ; PHI0 ; C25M ; 1.000 ; -2.758 ; 7.817 ;
-; -9.870 ; RAMSpecSELr ; SA[5]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.758 ; 7.779 ;
-; -9.836 ; nWEr ; nRCS~reg0 ; PHI0 ; C25M ; 1.000 ; -2.758 ; 7.745 ;
-; -9.662 ; RAMSpecSELr ; nRCS~reg0 ; PHI0 ; C25M ; 1.000 ; -2.758 ; 7.571 ;
-; -9.591 ; ROMSpecSELr ; RCKE~reg0 ; PHI0 ; C25M ; 1.000 ; -2.758 ; 7.500 ;
-; -9.528 ; RAMSpecSELr ; SBA[0]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.758 ; 7.437 ;
-; -9.519 ; nWEr ; RCKE~reg0 ; PHI0 ; C25M ; 1.000 ; -2.758 ; 7.428 ;
-; -9.459 ; RAMSpecSELr ; RCKE~reg0 ; PHI0 ; C25M ; 1.000 ; -2.758 ; 7.368 ;
-; -9.361 ; RAMSpecSELr ; SA[4]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.758 ; 7.270 ;
-; -9.344 ; RAMSpecSELr ; SA[3]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.758 ; 7.253 ;
-; -9.340 ; RAMSpecSELr ; SA[6]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.758 ; 7.249 ;
-; -9.115 ; RAMSpecSELr ; SA[7]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.758 ; 7.024 ;
-; -9.113 ; RAMSpecSELr ; SA[8]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.758 ; 7.022 ;
-; -9.032 ; RAMSpecSELr ; SBA[1]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.758 ; 6.941 ;
-; -8.948 ; RAMSpecSELr ; SA[2]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.758 ; 6.857 ;
-; -8.928 ; RAMSpecSELr ; SA[0]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.758 ; 6.837 ;
-; -8.855 ; PS[1] ; Addr[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.522 ;
-; -8.855 ; PS[1] ; Addr[1] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.522 ;
-; -8.855 ; PS[1] ; Addr[2] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.522 ;
-; -8.855 ; PS[1] ; Addr[3] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.522 ;
-; -8.855 ; PS[1] ; Addr[4] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.522 ;
-; -8.855 ; PS[1] ; Addr[5] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.522 ;
-; -8.855 ; PS[1] ; Addr[6] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.522 ;
-; -8.855 ; PS[1] ; Addr[7] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.522 ;
-; -8.814 ; nWEr ; Addr[0] ; PHI0 ; C25M ; 1.000 ; -2.758 ; 6.723 ;
-; -8.814 ; nWEr ; Addr[1] ; PHI0 ; C25M ; 1.000 ; -2.758 ; 6.723 ;
-; -8.814 ; nWEr ; Addr[2] ; PHI0 ; C25M ; 1.000 ; -2.758 ; 6.723 ;
-; -8.814 ; nWEr ; Addr[3] ; PHI0 ; C25M ; 1.000 ; -2.758 ; 6.723 ;
-; -8.814 ; nWEr ; Addr[4] ; PHI0 ; C25M ; 1.000 ; -2.758 ; 6.723 ;
-; -8.814 ; nWEr ; Addr[5] ; PHI0 ; C25M ; 1.000 ; -2.758 ; 6.723 ;
-; -8.814 ; nWEr ; Addr[6] ; PHI0 ; C25M ; 1.000 ; -2.758 ; 6.723 ;
-; -8.814 ; nWEr ; Addr[7] ; PHI0 ; C25M ; 1.000 ; -2.758 ; 6.723 ;
-; -8.538 ; IS.state_bit_0 ; SA[5]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.205 ;
-; -8.527 ; PS[0] ; RCKE~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.194 ;
-; -8.437 ; PS[1] ; Addr[23] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.104 ;
-; -8.437 ; PS[1] ; Addr[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.104 ;
-; -8.437 ; PS[1] ; Addr[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.104 ;
-; -8.437 ; PS[1] ; Addr[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.104 ;
-; -8.437 ; PS[1] ; Addr[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.104 ;
-; -8.437 ; PS[1] ; Addr[20] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.104 ;
-; -8.437 ; PS[1] ; Addr[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.104 ;
-; -8.437 ; PS[1] ; Addr[22] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.104 ;
-; -8.398 ; PS[0] ; Addr[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.065 ;
-; -8.398 ; PS[0] ; Addr[1] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.065 ;
-; -8.398 ; PS[0] ; Addr[2] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.065 ;
-; -8.398 ; PS[0] ; Addr[3] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.065 ;
-; -8.398 ; PS[0] ; Addr[4] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.065 ;
-; -8.398 ; PS[0] ; Addr[5] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.065 ;
-; -8.398 ; PS[0] ; Addr[6] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.065 ;
-; -8.398 ; PS[0] ; Addr[7] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.065 ;
-; -8.396 ; nWEr ; Addr[23] ; PHI0 ; C25M ; 1.000 ; -2.758 ; 6.305 ;
-; -8.396 ; nWEr ; Addr[16] ; PHI0 ; C25M ; 1.000 ; -2.758 ; 6.305 ;
-; -8.396 ; nWEr ; Addr[17] ; PHI0 ; C25M ; 1.000 ; -2.758 ; 6.305 ;
-; -8.396 ; nWEr ; Addr[18] ; PHI0 ; C25M ; 1.000 ; -2.758 ; 6.305 ;
-; -8.396 ; nWEr ; Addr[19] ; PHI0 ; C25M ; 1.000 ; -2.758 ; 6.305 ;
-; -8.396 ; nWEr ; Addr[20] ; PHI0 ; C25M ; 1.000 ; -2.758 ; 6.305 ;
-; -8.396 ; nWEr ; Addr[21] ; PHI0 ; C25M ; 1.000 ; -2.758 ; 6.305 ;
-; -8.396 ; nWEr ; Addr[22] ; PHI0 ; C25M ; 1.000 ; -2.758 ; 6.305 ;
-; -8.238 ; PS[1] ; IS.state_bit_1 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.905 ;
-; -8.207 ; PS[2] ; Addr[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.874 ;
-; -8.207 ; PS[2] ; Addr[1] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.874 ;
-; -8.207 ; PS[2] ; Addr[2] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.874 ;
-; -8.207 ; PS[2] ; Addr[3] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.874 ;
-; -8.207 ; PS[2] ; Addr[4] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.874 ;
-; -8.207 ; PS[2] ; Addr[5] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.874 ;
-; -8.207 ; PS[2] ; Addr[6] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.874 ;
-; -8.207 ; PS[2] ; Addr[7] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.874 ;
-; -8.193 ; IS.state_bit_0 ; SA[3]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.860 ;
-; -8.182 ; RAMSpecSELr ; SA[1]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.758 ; 6.091 ;
-; -8.150 ; LS[10] ; IS.state_bit_2 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.817 ;
-; -8.111 ; LS[10] ; IS.state_bit_0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.778 ;
-; -8.071 ; PS[0] ; SA[3]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.738 ;
-; -8.036 ; IS.state_bit_0 ; SA[2]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.703 ;
-; -8.029 ; IS.state_bit_0 ; SA[4]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.696 ;
-; -8.025 ; nWEr ; SDOE ; PHI0 ; C25M ; 1.000 ; -2.758 ; 5.934 ;
-; -8.016 ; IS.state_bit_0 ; SA[0]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.683 ;
-; -8.009 ; PS[2] ; RCKE~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.676 ;
-; -8.008 ; IS.state_bit_0 ; SA[6]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.675 ;
-; -8.003 ; LS[8] ; IS.state_bit_2 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.670 ;
-; -7.990 ; IS.state_bit_1 ; SA[5]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.657 ;
-; -7.989 ; PS[3] ; Addr[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.656 ;
-; -7.989 ; PS[3] ; Addr[1] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.656 ;
-; -7.989 ; PS[3] ; Addr[2] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.656 ;
-; -7.989 ; PS[3] ; Addr[3] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.656 ;
-; -7.989 ; PS[3] ; Addr[4] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.656 ;
-; -7.989 ; PS[3] ; Addr[5] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.656 ;
-; -7.989 ; PS[3] ; Addr[6] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.656 ;
-; -7.989 ; PS[3] ; Addr[7] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.656 ;
-; -7.980 ; PS[0] ; Addr[23] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.647 ;
-; -7.980 ; PS[0] ; Addr[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.647 ;
-; -7.980 ; PS[0] ; Addr[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.647 ;
-; -7.980 ; PS[0] ; Addr[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.647 ;
-; -7.980 ; PS[0] ; Addr[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.647 ;
-; -7.980 ; PS[0] ; Addr[20] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.647 ;
-; -7.980 ; PS[0] ; Addr[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.647 ;
-; -7.980 ; PS[0] ; Addr[22] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.647 ;
-; -7.964 ; LS[8] ; IS.state_bit_0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.631 ;
-; -7.957 ; PS[1] ; RCKE~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.624 ;
-; -7.953 ; IS.state_bit_0 ; SA[10]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.620 ;
-; -7.945 ; PS[0] ; WRD[1] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.612 ;
+; -9.691 ; nWEr ; nRCS~reg0 ; PHI0 ; C25M ; 1.000 ; -2.776 ; 7.582 ;
+; -9.602 ; RAMSpecSELr ; RCKE~reg0 ; PHI0 ; C25M ; 1.000 ; -2.776 ; 7.493 ;
+; -9.597 ; ROMSpecSELr ; nRCS~reg0 ; PHI0 ; C25M ; 1.000 ; -2.776 ; 7.488 ;
+; -9.555 ; RAMSpecSELr ; SA[1]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.776 ; 7.446 ;
+; -9.510 ; RAMSpecSELr ; SA[3]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.776 ; 7.401 ;
+; -9.406 ; RAMSpecSELr ; nRCS~reg0 ; PHI0 ; C25M ; 1.000 ; -2.776 ; 7.297 ;
+; -9.356 ; ROMSpecSELr ; RCKE~reg0 ; PHI0 ; C25M ; 1.000 ; -2.776 ; 7.247 ;
+; -9.306 ; nWEr ; RCKE~reg0 ; PHI0 ; C25M ; 1.000 ; -2.776 ; 7.197 ;
+; -9.286 ; RAMSpecSELr ; SA[4]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.776 ; 7.177 ;
+; -9.276 ; RAMSpecSELr ; SA[8]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.776 ; 7.167 ;
+; -9.273 ; RAMSpecSELr ; SA[6]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.776 ; 7.164 ;
+; -9.138 ; IS.state_bit_2 ; SA[1]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.805 ;
+; -9.127 ; RAMSpecSELr ; SA[5]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.776 ; 7.018 ;
+; -9.058 ; RAMSpecSELr ; SA[0]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.776 ; 6.949 ;
+; -9.055 ; RAMSpecSELr ; SA[2]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.776 ; 6.946 ;
+; -9.001 ; IS.state_bit_2 ; RCKE~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.668 ;
+; -8.979 ; REGEN ; RDD[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.646 ;
+; -8.978 ; IS.state_bit_2 ; SA[2]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.645 ;
+; -8.930 ; REGEN ; RDD[2] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.597 ;
+; -8.929 ; IS.state_bit_1 ; SA[1]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.596 ;
+; -8.891 ; IS.state_bit_2 ; SA[0]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.558 ;
+; -8.865 ; RAMSpecSELr ; SA[7]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.776 ; 6.756 ;
+; -8.835 ; LS[10] ; IS.state_bit_2 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.502 ;
+; -8.807 ; nWEr ; Addr[0] ; PHI0 ; C25M ; 1.000 ; -2.776 ; 6.698 ;
+; -8.807 ; nWEr ; Addr[1] ; PHI0 ; C25M ; 1.000 ; -2.776 ; 6.698 ;
+; -8.807 ; nWEr ; Addr[2] ; PHI0 ; C25M ; 1.000 ; -2.776 ; 6.698 ;
+; -8.807 ; nWEr ; Addr[3] ; PHI0 ; C25M ; 1.000 ; -2.776 ; 6.698 ;
+; -8.807 ; nWEr ; Addr[4] ; PHI0 ; C25M ; 1.000 ; -2.776 ; 6.698 ;
+; -8.807 ; nWEr ; Addr[5] ; PHI0 ; C25M ; 1.000 ; -2.776 ; 6.698 ;
+; -8.807 ; nWEr ; Addr[6] ; PHI0 ; C25M ; 1.000 ; -2.776 ; 6.698 ;
+; -8.807 ; nWEr ; Addr[7] ; PHI0 ; C25M ; 1.000 ; -2.776 ; 6.698 ;
+; -8.794 ; nWEr ; Addr[10] ; PHI0 ; C25M ; 1.000 ; -2.776 ; 6.685 ;
+; -8.794 ; nWEr ; Addr[11] ; PHI0 ; C25M ; 1.000 ; -2.776 ; 6.685 ;
+; -8.794 ; nWEr ; Addr[12] ; PHI0 ; C25M ; 1.000 ; -2.776 ; 6.685 ;
+; -8.794 ; nWEr ; Addr[13] ; PHI0 ; C25M ; 1.000 ; -2.776 ; 6.685 ;
+; -8.794 ; nWEr ; Addr[14] ; PHI0 ; C25M ; 1.000 ; -2.776 ; 6.685 ;
+; -8.794 ; nWEr ; Addr[15] ; PHI0 ; C25M ; 1.000 ; -2.776 ; 6.685 ;
+; -8.794 ; nWEr ; Addr[8] ; PHI0 ; C25M ; 1.000 ; -2.776 ; 6.685 ;
+; -8.794 ; nWEr ; Addr[9] ; PHI0 ; C25M ; 1.000 ; -2.776 ; 6.685 ;
+; -8.792 ; IS.state_bit_1 ; RCKE~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.459 ;
+; -8.786 ; nWEr ; SDOE ; PHI0 ; C25M ; 1.000 ; -2.776 ; 6.677 ;
+; -8.769 ; IS.state_bit_1 ; SA[2]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.436 ;
+; -8.682 ; PS[0] ; SA[3]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.349 ;
+; -8.682 ; IS.state_bit_1 ; SA[0]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.349 ;
+; -8.681 ; IS.state_bit_1 ; nRCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.348 ;
+; -8.677 ; LS[8] ; IS.state_bit_2 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.344 ;
+; -8.618 ; PS[3] ; SA[3]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.285 ;
+; -8.593 ; REGEN ; RDD[1] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.260 ;
+; -8.581 ; REGEN ; RDD[3] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.248 ;
+; -8.535 ; IS.state_bit_2 ; nRCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.202 ;
+; -8.497 ; nWEr ; Addr[23] ; PHI0 ; C25M ; 1.000 ; -2.776 ; 6.388 ;
+; -8.497 ; nWEr ; Addr[16] ; PHI0 ; C25M ; 1.000 ; -2.776 ; 6.388 ;
+; -8.497 ; nWEr ; Addr[17] ; PHI0 ; C25M ; 1.000 ; -2.776 ; 6.388 ;
+; -8.497 ; nWEr ; Addr[18] ; PHI0 ; C25M ; 1.000 ; -2.776 ; 6.388 ;
+; -8.497 ; nWEr ; Addr[19] ; PHI0 ; C25M ; 1.000 ; -2.776 ; 6.388 ;
+; -8.497 ; nWEr ; Addr[20] ; PHI0 ; C25M ; 1.000 ; -2.776 ; 6.388 ;
+; -8.497 ; nWEr ; Addr[21] ; PHI0 ; C25M ; 1.000 ; -2.776 ; 6.388 ;
+; -8.497 ; nWEr ; Addr[22] ; PHI0 ; C25M ; 1.000 ; -2.776 ; 6.388 ;
+; -8.487 ; LS[11] ; IS.state_bit_2 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.154 ;
+; -8.458 ; PS[0] ; SA[4]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.125 ;
+; -8.448 ; PS[0] ; SA[8]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.115 ;
+; -8.445 ; PS[0] ; SA[6]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.112 ;
+; -8.417 ; IS.state_bit_0 ; SA[1]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.084 ;
+; -8.405 ; PS[1] ; SA[1]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.072 ;
+; -8.394 ; PS[3] ; SA[4]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.061 ;
+; -8.390 ; LS[7] ; IS.state_bit_2 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.057 ;
+; -8.384 ; PS[3] ; SA[8]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.051 ;
+; -8.381 ; PS[3] ; SA[6]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.048 ;
+; -8.375 ; IS.state_bit_1 ; SA[3]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.042 ;
+; -8.338 ; LS[10] ; IS.state_bit_0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.005 ;
+; -8.321 ; LS[1] ; IS.state_bit_2 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.988 ;
+; -8.316 ; IS.state_bit_2 ; SA[6]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.983 ;
+; -8.299 ; PS[0] ; SA[5]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.966 ;
+; -8.280 ; IS.state_bit_0 ; RCKE~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.947 ;
+; -8.280 ; LS[13] ; IS.state_bit_2 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.947 ;
+; -8.279 ; PS[1] ; RCKE~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.946 ;
+; -8.259 ; PS[1] ; SA[2]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.926 ;
+; -8.257 ; IS.state_bit_0 ; SA[2]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.924 ;
+; -8.254 ; LS[2] ; IS.state_bit_2 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.921 ;
+; -8.244 ; IS.state_bit_2 ; SA[3]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.911 ;
+; -8.235 ; PS[3] ; SA[5]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.902 ;
+; -8.230 ; PS[0] ; SA[0]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.897 ;
+; -8.227 ; PS[0] ; SA[2]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.894 ;
+; -8.204 ; LS[4] ; IS.state_bit_2 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.871 ;
+; -8.197 ; PS[0] ; SA[1]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.864 ;
+; -8.180 ; LS[8] ; IS.state_bit_0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.847 ;
+; -8.172 ; PS[1] ; SA[0]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.839 ;
+; -8.170 ; IS.state_bit_0 ; SA[0]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.837 ;
+; -8.166 ; PS[3] ; SA[0]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.833 ;
+; -8.163 ; PS[3] ; SA[2]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.830 ;
+; -8.156 ; RAMSpecSELr ; SDOE ; PHI0 ; C25M ; 1.000 ; -2.776 ; 6.047 ;
+; -8.151 ; IS.state_bit_1 ; SA[4]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.818 ;
+; -8.146 ; IS.state_bit_2 ; SA[7]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.813 ;
+; -8.146 ; LS[6] ; IS.state_bit_2 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.813 ;
+; -8.145 ; IS.state_bit_2 ; SA[5]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.812 ;
+; -8.145 ; RAMSpecSELr ; SBA[0]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.776 ; 6.036 ;
+; -8.141 ; IS.state_bit_1 ; SA[8]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.808 ;
+; -8.139 ; LS[12] ; IS.state_bit_2 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.806 ;
+; -8.138 ; LS[9] ; IS.state_bit_2 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.805 ;
+; -8.138 ; IS.state_bit_1 ; SA[6]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.805 ;
+--------+----------------+----------------+--------------+-------------+--------------+------------+------------+
@@ -275,11 +269,11 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
+--------+-----------+-------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------+-------------+--------------+-------------+--------------+------------+------------+
-; -1.302 ; Addr[23] ; RAMSpecSELr ; C25M ; PHI0 ; 1.000 ; 2.758 ; 4.727 ;
-; -1.105 ; Addr[21] ; RAMSpecSELr ; C25M ; PHI0 ; 1.000 ; 2.758 ; 4.530 ;
-; -0.987 ; Addr[22] ; RAMSpecSELr ; C25M ; PHI0 ; 1.000 ; 2.758 ; 4.412 ;
-; -0.944 ; REGEN ; RAMSpecSELr ; C25M ; PHI0 ; 1.000 ; 2.758 ; 4.369 ;
-; -0.566 ; Addr[20] ; RAMSpecSELr ; C25M ; PHI0 ; 1.000 ; 2.758 ; 3.991 ;
+; -1.358 ; Addr[22] ; RAMSpecSELr ; C25M ; PHI0 ; 1.000 ; 2.776 ; 4.801 ;
+; -1.201 ; Addr[23] ; RAMSpecSELr ; C25M ; PHI0 ; 1.000 ; 2.776 ; 4.644 ;
+; -1.057 ; Addr[20] ; RAMSpecSELr ; C25M ; PHI0 ; 1.000 ; 2.776 ; 4.500 ;
+; -1.022 ; Addr[21] ; RAMSpecSELr ; C25M ; PHI0 ; 1.000 ; 2.776 ; 4.465 ;
+; -0.977 ; REGEN ; RAMSpecSELr ; C25M ; PHI0 ; 1.000 ; 2.776 ; 4.420 ;
+--------+-----------+-------------+--------------+-------------+--------------+------------+------------+
@@ -288,11 +282,11 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
+-------+-----------+-------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------+-------------+--------------+-------------+--------------+------------+------------+
-; 1.012 ; Addr[20] ; RAMSpecSELr ; C25M ; PHI0 ; 0.000 ; 2.758 ; 3.991 ;
-; 1.242 ; Addr[23] ; RAMSpecSELr ; C25M ; PHI0 ; 0.000 ; 2.758 ; 4.221 ;
-; 1.390 ; REGEN ; RAMSpecSELr ; C25M ; PHI0 ; 0.000 ; 2.758 ; 4.369 ;
-; 1.433 ; Addr[22] ; RAMSpecSELr ; C25M ; PHI0 ; 0.000 ; 2.758 ; 4.412 ;
-; 1.551 ; Addr[21] ; RAMSpecSELr ; C25M ; PHI0 ; 0.000 ; 2.758 ; 4.530 ;
+; 1.092 ; Addr[23] ; RAMSpecSELr ; C25M ; PHI0 ; 0.000 ; 2.776 ; 4.089 ;
+; 1.423 ; REGEN ; RAMSpecSELr ; C25M ; PHI0 ; 0.000 ; 2.776 ; 4.420 ;
+; 1.468 ; Addr[21] ; RAMSpecSELr ; C25M ; PHI0 ; 0.000 ; 2.776 ; 4.465 ;
+; 1.503 ; Addr[20] ; RAMSpecSELr ; C25M ; PHI0 ; 0.000 ; 2.776 ; 4.500 ;
+; 1.804 ; Addr[22] ; RAMSpecSELr ; C25M ; PHI0 ; 0.000 ; 2.776 ; 4.801 ;
+-------+-----------+-------------+--------------+-------------+--------------+------------+------------+
@@ -301,106 +295,106 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
+-------+----------------+----------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------+----------------+--------------+-------------+--------------+------------+------------+
-; 1.288 ; PHI0 ; PHI0r1 ; PHI0 ; C25M ; 0.000 ; 3.458 ; 4.967 ;
-; 1.398 ; nRESr0 ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 1.619 ;
-; 1.650 ; nRESout~reg0 ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 1.871 ;
-; 1.679 ; IS.state_bit_2 ; MOSIOE ; C25M ; C25M ; 0.000 ; 0.000 ; 1.900 ;
-; 1.718 ; PS[2] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.939 ;
-; 1.784 ; PHI0r1 ; PHI0r2 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.005 ;
-; 1.788 ; PHI0 ; PHI0r1 ; PHI0 ; C25M ; -0.500 ; 3.458 ; 4.967 ;
-; 1.935 ; LS[0] ; LS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.156 ;
-; 2.107 ; LS[7] ; LS[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.328 ;
-; 2.108 ; Addr[15] ; Addr[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.329 ;
-; 2.117 ; Addr[1] ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ;
-; 2.117 ; Addr[2] ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ;
+; 1.418 ; PHI0r1 ; PHI0r2 ; C25M ; C25M ; 0.000 ; 0.000 ; 1.639 ;
+; 1.537 ; PHI0 ; PHI0r1 ; PHI0 ; C25M ; 0.000 ; 3.458 ; 5.216 ;
+; 1.899 ; Bank ; Bank ; C25M ; C25M ; 0.000 ; 0.000 ; 2.120 ;
+; 1.929 ; Addr[7] ; AddrIncM ; C25M ; C25M ; 0.000 ; 0.000 ; 2.150 ;
+; 1.939 ; Addr[15] ; AddrIncH ; C25M ; C25M ; 0.000 ; 0.000 ; 2.160 ;
+; 1.946 ; REGEN ; REGEN ; C25M ; C25M ; 0.000 ; 0.000 ; 2.167 ;
+; 1.956 ; PS[2] ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.177 ;
+; 1.986 ; IS.state_bit_2 ; IS.state_bit_0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.207 ;
+; 2.037 ; PHI0 ; PHI0r1 ; PHI0 ; C25M ; -0.500 ; 3.458 ; 5.216 ;
+; 2.048 ; LS[13] ; LS[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.269 ;
+; 2.116 ; LS[7] ; LS[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.337 ;
+; 2.117 ; Addr[10] ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ;
+; 2.117 ; Addr[17] ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ;
+; 2.117 ; Addr[18] ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ;
+; 2.117 ; Addr[9] ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ;
+; 2.124 ; Addr[0] ; Addr[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.345 ;
; 2.125 ; Addr[16] ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.346 ;
-; 2.126 ; Addr[17] ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ;
-; 2.127 ; Addr[23] ; Addr[23] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.348 ;
-; 2.127 ; LS[4] ; LS[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.348 ;
-; 2.127 ; Addr[18] ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.348 ;
-; 2.128 ; LS[6] ; LS[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.349 ;
-; 2.136 ; IS.state_bit_0 ; IS.state_bit_0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.357 ;
-; 2.136 ; Addr[7] ; Addr[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.357 ;
-; 2.137 ; PS[3] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.358 ;
-; 2.137 ; Addr[7] ; AddrIncM ; C25M ; C25M ; 0.000 ; 0.000 ; 2.358 ;
+; 2.127 ; LS[6] ; LS[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.348 ;
+; 2.132 ; Addr[8] ; Addr[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.353 ;
+; 2.134 ; Addr[1] ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.355 ;
+; 2.135 ; Addr[2] ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.356 ;
+; 2.137 ; Addr[7] ; Addr[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.358 ;
; 2.143 ; LS[8] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.364 ;
-; 2.144 ; Addr[10] ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.365 ;
-; 2.144 ; Addr[9] ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.365 ;
+; 2.145 ; Addr[15] ; Addr[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.366 ;
; 2.145 ; LS[9] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.366 ;
-; 2.173 ; PS[2] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.394 ;
-; 2.187 ; PS[2] ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.408 ;
-; 2.222 ; Addr[19] ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.443 ;
-; 2.228 ; AddrIncH ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.449 ;
-; 2.230 ; IOROMEN ; IOROMEN ; C25M ; C25M ; 0.000 ; 0.000 ; 2.451 ;
-; 2.230 ; Addr[21] ; Addr[21] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.451 ;
-; 2.231 ; Bank ; Bank ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ;
+; 2.146 ; LS[0] ; LS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.367 ;
+; 2.151 ; PS[0] ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.372 ;
+; 2.151 ; LS[4] ; LS[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.372 ;
+; 2.159 ; PS[2] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.380 ;
+; 2.180 ; IS.state_bit_0 ; IS.state_bit_0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.401 ;
+; 2.212 ; Addr[19] ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.433 ;
+; 2.222 ; Addr[11] ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.443 ;
+; 2.222 ; Addr[3] ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.443 ;
+; 2.223 ; nRESout~reg0 ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.444 ;
+; 2.229 ; IOROMEN ; IOROMEN ; C25M ; C25M ; 0.000 ; 0.000 ; 2.450 ;
+; 2.229 ; LS[12] ; LS[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.450 ;
+; 2.230 ; Addr[13] ; Addr[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.451 ;
+; 2.230 ; Addr[5] ; Addr[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.451 ;
+; 2.231 ; Addr[12] ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ;
+; 2.231 ; Addr[4] ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ;
+; 2.231 ; Addr[14] ; Addr[14] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ;
+; 2.231 ; Addr[6] ; Addr[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ;
; 2.231 ; Addr[20] ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ;
-; 2.231 ; Addr[22] ; Addr[22] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ;
-; 2.232 ; Addr[3] ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.453 ;
-; 2.232 ; LS[5] ; LS[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.453 ;
-; 2.239 ; LS[2] ; LS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.460 ;
-; 2.240 ; LS[1] ; LS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.461 ;
-; 2.241 ; LS[10] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.462 ;
-; 2.241 ; Addr[11] ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.462 ;
-; 2.247 ; LS[12] ; LS[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.468 ;
-; 2.249 ; Addr[4] ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.470 ;
-; 2.249 ; Addr[14] ; Addr[14] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.470 ;
-; 2.251 ; LS[3] ; LS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.472 ;
-; 2.260 ; LS[11] ; LS[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.481 ;
-; 2.260 ; Addr[13] ; Addr[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.481 ;
-; 2.260 ; Addr[6] ; Addr[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.481 ;
-; 2.260 ; LS[13] ; LS[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.481 ;
-; 2.261 ; Addr[5] ; Addr[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.482 ;
-; 2.262 ; Addr[12] ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.483 ;
-; 2.312 ; PS[0] ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.533 ;
-; 2.313 ; PS[0] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.534 ;
-; 2.319 ; PS[0] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.540 ;
-; 2.380 ; IS.state_bit_1 ; IS.state_bit_0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.601 ;
-; 2.411 ; Addr[22] ; SA[12]~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.632 ;
-; 2.496 ; AddrIncL ; Addr[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.717 ;
-; 2.560 ; Addr[21] ; SA[11]~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.781 ;
-; 2.563 ; PS[3] ; SBA[1]~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.784 ;
-; 2.726 ; IS.state_bit_1 ; WRD[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.947 ;
-; 2.939 ; LS[7] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.160 ;
-; 2.949 ; Addr[1] ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ;
-; 2.949 ; Addr[2] ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ;
+; 2.241 ; LS[11] ; LS[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.462 ;
+; 2.251 ; LS[2] ; LS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.472 ;
+; 2.252 ; LS[1] ; LS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.473 ;
+; 2.253 ; LS[10] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.474 ;
+; 2.259 ; LS[5] ; LS[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.480 ;
+; 2.260 ; PS[3] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.481 ;
+; 2.295 ; PS[0] ; WRD[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.516 ;
+; 2.403 ; PS[0] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.624 ;
+; 2.509 ; PS[0] ; FCKout ; C25M ; C25M ; 0.000 ; 0.000 ; 2.730 ;
+; 2.535 ; LS[0] ; LS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.756 ;
+; 2.536 ; Addr[22] ; Addr[22] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.757 ;
+; 2.549 ; LS[3] ; LS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.770 ;
+; 2.700 ; Addr[21] ; Addr[21] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.921 ;
+; 2.725 ; IS.state_bit_1 ; IS.state_bit_2 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.946 ;
+; 2.730 ; IS.state_bit_1 ; IS.state_bit_0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.951 ;
+; 2.892 ; IS.state_bit_2 ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.113 ;
+; 2.909 ; PS[2] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.130 ;
+; 2.948 ; LS[7] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.169 ;
+; 2.949 ; Addr[9] ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ;
+; 2.949 ; Addr[10] ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ;
+; 2.949 ; Addr[17] ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ;
+; 2.949 ; Addr[18] ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ;
+; 2.956 ; Addr[0] ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.177 ;
; 2.957 ; Addr[16] ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.178 ;
-; 2.958 ; Addr[17] ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.179 ;
-; 2.959 ; LS[4] ; LS[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.180 ;
-; 2.959 ; Addr[18] ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.180 ;
-; 2.965 ; IS.state_bit_1 ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.186 ;
+; 2.958 ; IS.state_bit_2 ; FCKOE ; C25M ; C25M ; 0.000 ; 0.000 ; 3.179 ;
+; 2.963 ; IS.state_bit_2 ; FCS ; C25M ; C25M ; 0.000 ; 0.000 ; 3.184 ;
+; 2.964 ; Addr[8] ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.185 ;
+; 2.966 ; Addr[1] ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.187 ;
+; 2.967 ; Addr[2] ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.188 ;
; 2.975 ; LS[8] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.196 ;
-; 2.976 ; Addr[9] ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.197 ;
-; 2.976 ; Addr[10] ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.197 ;
; 2.977 ; LS[9] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.198 ;
-; 2.990 ; PS[2] ; SA[5]~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.211 ;
-; 3.050 ; LS[7] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.271 ;
-; 3.055 ; Addr[15] ; AddrIncH ; C25M ; C25M ; 0.000 ; 0.000 ; 3.276 ;
-; 3.060 ; Addr[2] ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ;
-; 3.060 ; Addr[1] ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ;
+; 2.978 ; Addr[2] ; RDD[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.199 ;
+; 2.982 ; REGEN ; Bank ; C25M ; C25M ; 0.000 ; 0.000 ; 3.203 ;
+; 2.983 ; LS[4] ; LS[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.204 ;
+; 3.059 ; LS[7] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.280 ;
+; 3.060 ; Addr[10] ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ;
+; 3.060 ; Addr[18] ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ;
+; 3.060 ; Addr[9] ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ;
+; 3.060 ; Addr[17] ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ;
+; 3.067 ; Addr[0] ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.288 ;
+; 3.068 ; PHI0r1 ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.289 ;
; 3.068 ; Addr[16] ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.289 ;
-; 3.069 ; Addr[21] ; RDD[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.290 ;
-; 3.069 ; Addr[17] ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.290 ;
-; 3.070 ; LS[4] ; LS[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.291 ;
-; 3.070 ; Addr[18] ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.291 ;
+; 3.075 ; Addr[8] ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.296 ;
+; 3.077 ; Addr[1] ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.298 ;
+; 3.078 ; Addr[2] ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.299 ;
; 3.086 ; LS[8] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.307 ;
-; 3.087 ; Addr[10] ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.308 ;
-; 3.087 ; Addr[9] ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.308 ;
; 3.088 ; LS[9] ; LS[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.309 ;
-; 3.103 ; Addr[11] ; RDD[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.324 ;
-; 3.119 ; PS[2] ; SA[9]~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.340 ;
-; 3.138 ; Addr[0] ; DQML~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.359 ;
-; 3.161 ; LS[7] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.382 ;
-; 3.162 ; Addr[19] ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.383 ;
-; 3.168 ; AddrIncH ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.389 ;
-; 3.170 ; Addr[21] ; Addr[22] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.391 ;
-; 3.171 ; Addr[22] ; Addr[23] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.392 ;
-; 3.171 ; Addr[1] ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.392 ;
-; 3.172 ; Addr[3] ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.393 ;
-; 3.172 ; LS[5] ; LS[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.393 ;
-; 3.179 ; LS[2] ; LS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.400 ;
-; 3.179 ; Addr[16] ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.400 ;
-; 3.180 ; Addr[17] ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.401 ;
+; 3.089 ; Addr[0] ; DQMH~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.310 ;
+; 3.094 ; LS[4] ; LS[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.315 ;
+; 3.095 ; Addr[0] ; DQML~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.316 ;
+; 3.113 ; Addr[2] ; SA[1]~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.334 ;
+; 3.152 ; Addr[19] ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.373 ;
+; 3.162 ; Addr[11] ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.383 ;
+; 3.162 ; Addr[3] ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.383 ;
+; 3.169 ; LS[12] ; LS[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.390 ;
+; 3.170 ; Addr[13] ; Addr[14] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.391 ;
+; 3.170 ; Addr[5] ; Addr[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.391 ;
+-------+----------------+----------------+--------------+-------------+--------------+------------+------------+
@@ -409,36 +403,36 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
+--------+-----------+----------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------+----------+--------------+-------------+--------------+------------+------------+
-; -4.389 ; nRESr ; IOROMEN ; C25M ; C25M ; 1.000 ; 0.000 ; 5.056 ;
-; -4.389 ; nRESr ; Addr[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.056 ;
-; -4.389 ; nRESr ; Addr[23] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.056 ;
-; -4.389 ; nRESr ; Addr[10] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.056 ;
-; -4.389 ; nRESr ; Addr[1] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.056 ;
-; -4.389 ; nRESr ; Addr[11] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.056 ;
-; -4.389 ; nRESr ; Addr[2] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.056 ;
-; -4.389 ; nRESr ; Addr[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.056 ;
-; -4.389 ; nRESr ; Bank ; C25M ; C25M ; 1.000 ; 0.000 ; 5.056 ;
-; -4.389 ; nRESr ; Addr[3] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.056 ;
-; -4.389 ; nRESr ; Addr[13] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.056 ;
-; -4.389 ; nRESr ; Addr[4] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.056 ;
-; -4.389 ; nRESr ; Addr[14] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.056 ;
-; -4.389 ; nRESr ; Addr[5] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.056 ;
-; -4.389 ; nRESr ; Addr[15] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.056 ;
-; -4.389 ; nRESr ; Addr[6] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.056 ;
-; -4.389 ; nRESr ; Addr[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.056 ;
-; -4.389 ; nRESr ; Addr[7] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.056 ;
-; -4.389 ; nRESr ; Addr[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.056 ;
-; -4.389 ; nRESr ; Addr[8] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.056 ;
-; -4.389 ; nRESr ; Addr[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.056 ;
-; -4.389 ; nRESr ; Addr[9] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.056 ;
-; -4.389 ; nRESr ; Addr[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.056 ;
-; -4.389 ; nRESr ; Addr[20] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.056 ;
-; -4.389 ; nRESr ; Addr[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.056 ;
-; -4.389 ; nRESr ; Addr[22] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.056 ;
-; -4.389 ; nRESr ; REGEN ; C25M ; C25M ; 1.000 ; 0.000 ; 5.056 ;
-; -4.389 ; nRESr ; AddrIncH ; C25M ; C25M ; 1.000 ; 0.000 ; 5.056 ;
-; -4.389 ; nRESr ; AddrIncM ; C25M ; C25M ; 1.000 ; 0.000 ; 5.056 ;
-; -4.389 ; nRESr ; AddrIncL ; C25M ; C25M ; 1.000 ; 0.000 ; 5.056 ;
+; -5.009 ; nRESr ; IOROMEN ; C25M ; C25M ; 1.000 ; 0.000 ; 5.676 ;
+; -5.009 ; nRESr ; Addr[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.676 ;
+; -5.009 ; nRESr ; Addr[23] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.676 ;
+; -5.009 ; nRESr ; Addr[10] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.676 ;
+; -5.009 ; nRESr ; Addr[1] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.676 ;
+; -5.009 ; nRESr ; Addr[11] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.676 ;
+; -5.009 ; nRESr ; Addr[2] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.676 ;
+; -5.009 ; nRESr ; Addr[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.676 ;
+; -5.009 ; nRESr ; Bank ; C25M ; C25M ; 1.000 ; 0.000 ; 5.676 ;
+; -5.009 ; nRESr ; Addr[3] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.676 ;
+; -5.009 ; nRESr ; Addr[13] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.676 ;
+; -5.009 ; nRESr ; Addr[4] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.676 ;
+; -5.009 ; nRESr ; Addr[14] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.676 ;
+; -5.009 ; nRESr ; Addr[5] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.676 ;
+; -5.009 ; nRESr ; Addr[15] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.676 ;
+; -5.009 ; nRESr ; Addr[6] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.676 ;
+; -5.009 ; nRESr ; Addr[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.676 ;
+; -5.009 ; nRESr ; Addr[7] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.676 ;
+; -5.009 ; nRESr ; Addr[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.676 ;
+; -5.009 ; nRESr ; Addr[8] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.676 ;
+; -5.009 ; nRESr ; Addr[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.676 ;
+; -5.009 ; nRESr ; Addr[9] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.676 ;
+; -5.009 ; nRESr ; Addr[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.676 ;
+; -5.009 ; nRESr ; Addr[20] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.676 ;
+; -5.009 ; nRESr ; Addr[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.676 ;
+; -5.009 ; nRESr ; Addr[22] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.676 ;
+; -5.009 ; nRESr ; REGEN ; C25M ; C25M ; 1.000 ; 0.000 ; 5.676 ;
+; -5.009 ; nRESr ; AddrIncH ; C25M ; C25M ; 1.000 ; 0.000 ; 5.676 ;
+; -5.009 ; nRESr ; AddrIncM ; C25M ; C25M ; 1.000 ; 0.000 ; 5.676 ;
+; -5.009 ; nRESr ; AddrIncL ; C25M ; C25M ; 1.000 ; 0.000 ; 5.676 ;
+--------+-----------+----------+--------------+-------------+--------------+------------+------------+
@@ -447,36 +441,36 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
+-------+-----------+----------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------+----------+--------------+-------------+--------------+------------+------------+
-; 4.835 ; nRESr ; IOROMEN ; C25M ; C25M ; 0.000 ; 0.000 ; 5.056 ;
-; 4.835 ; nRESr ; Addr[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.056 ;
-; 4.835 ; nRESr ; Addr[23] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.056 ;
-; 4.835 ; nRESr ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.056 ;
-; 4.835 ; nRESr ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.056 ;
-; 4.835 ; nRESr ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.056 ;
-; 4.835 ; nRESr ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.056 ;
-; 4.835 ; nRESr ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.056 ;
-; 4.835 ; nRESr ; Bank ; C25M ; C25M ; 0.000 ; 0.000 ; 5.056 ;
-; 4.835 ; nRESr ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.056 ;
-; 4.835 ; nRESr ; Addr[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.056 ;
-; 4.835 ; nRESr ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.056 ;
-; 4.835 ; nRESr ; Addr[14] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.056 ;
-; 4.835 ; nRESr ; Addr[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.056 ;
-; 4.835 ; nRESr ; Addr[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.056 ;
-; 4.835 ; nRESr ; Addr[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.056 ;
-; 4.835 ; nRESr ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.056 ;
-; 4.835 ; nRESr ; Addr[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.056 ;
-; 4.835 ; nRESr ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.056 ;
-; 4.835 ; nRESr ; Addr[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.056 ;
-; 4.835 ; nRESr ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.056 ;
-; 4.835 ; nRESr ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.056 ;
-; 4.835 ; nRESr ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.056 ;
-; 4.835 ; nRESr ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.056 ;
-; 4.835 ; nRESr ; Addr[21] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.056 ;
-; 4.835 ; nRESr ; Addr[22] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.056 ;
-; 4.835 ; nRESr ; REGEN ; C25M ; C25M ; 0.000 ; 0.000 ; 5.056 ;
-; 4.835 ; nRESr ; AddrIncH ; C25M ; C25M ; 0.000 ; 0.000 ; 5.056 ;
-; 4.835 ; nRESr ; AddrIncM ; C25M ; C25M ; 0.000 ; 0.000 ; 5.056 ;
-; 4.835 ; nRESr ; AddrIncL ; C25M ; C25M ; 0.000 ; 0.000 ; 5.056 ;
+; 5.455 ; nRESr ; IOROMEN ; C25M ; C25M ; 0.000 ; 0.000 ; 5.676 ;
+; 5.455 ; nRESr ; Addr[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.676 ;
+; 5.455 ; nRESr ; Addr[23] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.676 ;
+; 5.455 ; nRESr ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.676 ;
+; 5.455 ; nRESr ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.676 ;
+; 5.455 ; nRESr ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.676 ;
+; 5.455 ; nRESr ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.676 ;
+; 5.455 ; nRESr ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.676 ;
+; 5.455 ; nRESr ; Bank ; C25M ; C25M ; 0.000 ; 0.000 ; 5.676 ;
+; 5.455 ; nRESr ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.676 ;
+; 5.455 ; nRESr ; Addr[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.676 ;
+; 5.455 ; nRESr ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.676 ;
+; 5.455 ; nRESr ; Addr[14] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.676 ;
+; 5.455 ; nRESr ; Addr[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.676 ;
+; 5.455 ; nRESr ; Addr[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.676 ;
+; 5.455 ; nRESr ; Addr[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.676 ;
+; 5.455 ; nRESr ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.676 ;
+; 5.455 ; nRESr ; Addr[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.676 ;
+; 5.455 ; nRESr ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.676 ;
+; 5.455 ; nRESr ; Addr[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.676 ;
+; 5.455 ; nRESr ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.676 ;
+; 5.455 ; nRESr ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.676 ;
+; 5.455 ; nRESr ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.676 ;
+; 5.455 ; nRESr ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.676 ;
+; 5.455 ; nRESr ; Addr[21] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.676 ;
+; 5.455 ; nRESr ; Addr[22] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.676 ;
+; 5.455 ; nRESr ; REGEN ; C25M ; C25M ; 0.000 ; 0.000 ; 5.676 ;
+; 5.455 ; nRESr ; AddrIncH ; C25M ; C25M ; 0.000 ; 0.000 ; 5.676 ;
+; 5.455 ; nRESr ; AddrIncM ; C25M ; C25M ; 0.000 ; 0.000 ; 5.676 ;
+; 5.455 ; nRESr ; AddrIncL ; C25M ; C25M ; 0.000 ; 0.000 ; 5.676 ;
+-------+-----------+----------+--------------+-------------+--------------+------------+------------+
@@ -546,8 +540,10 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; DQMH~reg0 ;
; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; DQML~reg0 ;
; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; DQML~reg0 ;
-; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; FCK~reg0 ;
-; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; FCK~reg0 ;
+; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; FCKOE ;
+; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; FCKOE ;
+; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; FCKout ;
+; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; FCKout ;
; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; FCS ;
; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; FCS ;
; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; IOROMEN ;
@@ -583,8 +579,6 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[7] ;
; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[7] ;
; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[8] ;
-; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[8] ;
-; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[9] ;
+--------+--------------+----------------+------------------+-------+------------+----------------+
@@ -616,69 +610,69 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
+-----------+------------+--------+--------+------------+-----------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+--------+--------+------------+-----------------+
-; MISO ; C25M ; 3.628 ; 3.628 ; Rise ; C25M ;
-; MOSI ; C25M ; 3.134 ; 3.134 ; Rise ; C25M ;
-; PHI0 ; C25M ; 1.842 ; 1.842 ; Rise ; C25M ;
-; RA[*] ; C25M ; 14.446 ; 14.446 ; Rise ; C25M ;
-; RA[0] ; C25M ; 12.244 ; 12.244 ; Rise ; C25M ;
-; RA[1] ; C25M ; 9.346 ; 9.346 ; Rise ; C25M ;
-; RA[2] ; C25M ; 10.786 ; 10.786 ; Rise ; C25M ;
-; RA[3] ; C25M ; 9.186 ; 9.186 ; Rise ; C25M ;
-; RA[4] ; C25M ; 7.558 ; 7.558 ; Rise ; C25M ;
-; RA[5] ; C25M ; 7.386 ; 7.386 ; Rise ; C25M ;
-; RA[6] ; C25M ; 7.283 ; 7.283 ; Rise ; C25M ;
-; RA[7] ; C25M ; 10.628 ; 10.628 ; Rise ; C25M ;
-; RA[8] ; C25M ; 12.243 ; 12.243 ; Rise ; C25M ;
-; RA[9] ; C25M ; 12.435 ; 12.435 ; Rise ; C25M ;
-; RA[10] ; C25M ; 14.446 ; 14.446 ; Rise ; C25M ;
-; RA[11] ; C25M ; 12.093 ; 12.093 ; Rise ; C25M ;
-; RA[12] ; C25M ; 13.202 ; 13.202 ; Rise ; C25M ;
-; RA[13] ; C25M ; 13.318 ; 13.318 ; Rise ; C25M ;
-; RA[14] ; C25M ; 12.169 ; 12.169 ; Rise ; C25M ;
-; RA[15] ; C25M ; 12.339 ; 12.339 ; Rise ; C25M ;
-; RD[*] ; C25M ; 7.952 ; 7.952 ; Rise ; C25M ;
-; RD[0] ; C25M ; 7.952 ; 7.952 ; Rise ; C25M ;
-; RD[1] ; C25M ; 4.445 ; 4.445 ; Rise ; C25M ;
-; RD[2] ; C25M ; 3.282 ; 3.282 ; Rise ; C25M ;
-; RD[3] ; C25M ; 4.945 ; 4.945 ; Rise ; C25M ;
-; RD[4] ; C25M ; 5.326 ; 5.326 ; Rise ; C25M ;
-; RD[5] ; C25M ; 3.190 ; 3.190 ; Rise ; C25M ;
-; RD[6] ; C25M ; 3.265 ; 3.265 ; Rise ; C25M ;
-; RD[7] ; C25M ; 5.333 ; 5.333 ; Rise ; C25M ;
-; SD[*] ; C25M ; 3.881 ; 3.881 ; Rise ; C25M ;
-; SD[0] ; C25M ; 3.314 ; 3.314 ; Rise ; C25M ;
-; SD[1] ; C25M ; 3.881 ; 3.881 ; Rise ; C25M ;
-; SD[2] ; C25M ; 3.035 ; 3.035 ; Rise ; C25M ;
-; SD[3] ; C25M ; 3.343 ; 3.343 ; Rise ; C25M ;
-; SD[4] ; C25M ; 3.705 ; 3.705 ; Rise ; C25M ;
-; SD[5] ; C25M ; 3.013 ; 3.013 ; Rise ; C25M ;
-; SD[6] ; C25M ; 3.156 ; 3.156 ; Rise ; C25M ;
-; SD[7] ; C25M ; 3.101 ; 3.101 ; Rise ; C25M ;
-; SetFW[*] ; C25M ; 11.106 ; 11.106 ; Rise ; C25M ;
-; SetFW[0] ; C25M ; 9.884 ; 9.884 ; Rise ; C25M ;
-; SetFW[1] ; C25M ; 11.106 ; 11.106 ; Rise ; C25M ;
-; nDEVSEL ; C25M ; 9.577 ; 9.577 ; Rise ; C25M ;
-; nIOSEL ; C25M ; 3.234 ; 3.234 ; Rise ; C25M ;
-; nIOSTRB ; C25M ; 5.830 ; 5.830 ; Rise ; C25M ;
-; nRES ; C25M ; 4.742 ; 4.742 ; Rise ; C25M ;
-; RA[*] ; PHI0 ; 8.035 ; 8.035 ; Rise ; PHI0 ;
-; RA[0] ; PHI0 ; 0.797 ; 0.797 ; Rise ; PHI0 ;
-; RA[1] ; PHI0 ; 0.737 ; 0.737 ; Rise ; PHI0 ;
-; RA[2] ; PHI0 ; 4.375 ; 4.375 ; Rise ; PHI0 ;
-; RA[3] ; PHI0 ; 2.775 ; 2.775 ; Rise ; PHI0 ;
-; RA[7] ; PHI0 ; 4.217 ; 4.217 ; Rise ; PHI0 ;
-; RA[8] ; PHI0 ; 5.832 ; 5.832 ; Rise ; PHI0 ;
-; RA[9] ; PHI0 ; 6.024 ; 6.024 ; Rise ; PHI0 ;
-; RA[10] ; PHI0 ; 8.035 ; 8.035 ; Rise ; PHI0 ;
-; RA[11] ; PHI0 ; 5.682 ; 5.682 ; Rise ; PHI0 ;
-; RA[12] ; PHI0 ; 6.791 ; 6.791 ; Rise ; PHI0 ;
-; RA[13] ; PHI0 ; 6.907 ; 6.907 ; Rise ; PHI0 ;
-; RA[14] ; PHI0 ; 5.758 ; 5.758 ; Rise ; PHI0 ;
-; RA[15] ; PHI0 ; 5.928 ; 5.928 ; Rise ; PHI0 ;
-; SetFW[*] ; PHI0 ; 1.906 ; 1.906 ; Rise ; PHI0 ;
-; SetFW[0] ; PHI0 ; 1.744 ; 1.744 ; Rise ; PHI0 ;
-; SetFW[1] ; PHI0 ; 1.906 ; 1.906 ; Rise ; PHI0 ;
-; nWE ; PHI0 ; 0.488 ; 0.488 ; Rise ; PHI0 ;
+; MISO ; C25M ; 3.207 ; 3.207 ; Rise ; C25M ;
+; MOSI ; C25M ; 4.773 ; 4.773 ; Rise ; C25M ;
+; PHI0 ; C25M ; 2.091 ; 2.091 ; Rise ; C25M ;
+; RA[*] ; C25M ; 15.448 ; 15.448 ; Rise ; C25M ;
+; RA[0] ; C25M ; 8.995 ; 8.995 ; Rise ; C25M ;
+; RA[1] ; C25M ; 9.363 ; 9.363 ; Rise ; C25M ;
+; RA[2] ; C25M ; 10.605 ; 10.605 ; Rise ; C25M ;
+; RA[3] ; C25M ; 12.017 ; 12.017 ; Rise ; C25M ;
+; RA[4] ; C25M ; 9.957 ; 9.957 ; Rise ; C25M ;
+; RA[5] ; C25M ; 7.815 ; 7.815 ; Rise ; C25M ;
+; RA[6] ; C25M ; 8.525 ; 8.525 ; Rise ; C25M ;
+; RA[7] ; C25M ; 12.425 ; 12.425 ; Rise ; C25M ;
+; RA[8] ; C25M ; 15.042 ; 15.042 ; Rise ; C25M ;
+; RA[9] ; C25M ; 14.757 ; 14.757 ; Rise ; C25M ;
+; RA[10] ; C25M ; 13.247 ; 13.247 ; Rise ; C25M ;
+; RA[11] ; C25M ; 14.731 ; 14.731 ; Rise ; C25M ;
+; RA[12] ; C25M ; 15.345 ; 15.345 ; Rise ; C25M ;
+; RA[13] ; C25M ; 14.789 ; 14.789 ; Rise ; C25M ;
+; RA[14] ; C25M ; 15.448 ; 15.448 ; Rise ; C25M ;
+; RA[15] ; C25M ; 14.916 ; 14.916 ; Rise ; C25M ;
+; RD[*] ; C25M ; 4.859 ; 4.859 ; Rise ; C25M ;
+; RD[0] ; C25M ; 3.485 ; 3.485 ; Rise ; C25M ;
+; RD[1] ; C25M ; 3.672 ; 3.672 ; Rise ; C25M ;
+; RD[2] ; C25M ; 4.859 ; 4.859 ; Rise ; C25M ;
+; RD[3] ; C25M ; 3.853 ; 3.853 ; Rise ; C25M ;
+; RD[4] ; C25M ; 4.312 ; 4.312 ; Rise ; C25M ;
+; RD[5] ; C25M ; 3.181 ; 3.181 ; Rise ; C25M ;
+; RD[6] ; C25M ; 4.216 ; 4.216 ; Rise ; C25M ;
+; RD[7] ; C25M ; 4.228 ; 4.228 ; Rise ; C25M ;
+; SD[*] ; C25M ; 6.673 ; 6.673 ; Rise ; C25M ;
+; SD[0] ; C25M ; 3.461 ; 3.461 ; Rise ; C25M ;
+; SD[1] ; C25M ; 3.140 ; 3.140 ; Rise ; C25M ;
+; SD[2] ; C25M ; 6.673 ; 6.673 ; Rise ; C25M ;
+; SD[3] ; C25M ; 4.786 ; 4.786 ; Rise ; C25M ;
+; SD[4] ; C25M ; 3.431 ; 3.431 ; Rise ; C25M ;
+; SD[5] ; C25M ; 3.118 ; 3.118 ; Rise ; C25M ;
+; SD[6] ; C25M ; 3.112 ; 3.112 ; Rise ; C25M ;
+; SD[7] ; C25M ; 3.792 ; 3.792 ; Rise ; C25M ;
+; SetFW[*] ; C25M ; 10.023 ; 10.023 ; Rise ; C25M ;
+; SetFW[0] ; C25M ; 10.023 ; 10.023 ; Rise ; C25M ;
+; SetFW[1] ; C25M ; 9.330 ; 9.330 ; Rise ; C25M ;
+; nDEVSEL ; C25M ; 9.087 ; 9.087 ; Rise ; C25M ;
+; nIOSEL ; C25M ; 3.410 ; 3.410 ; Rise ; C25M ;
+; nIOSTRB ; C25M ; 7.724 ; 7.724 ; Rise ; C25M ;
+; nRES ; C25M ; 3.263 ; 3.263 ; Rise ; C25M ;
+; RA[*] ; PHI0 ; 7.446 ; 7.446 ; Rise ; PHI0 ;
+; RA[0] ; PHI0 ; 0.649 ; 0.649 ; Rise ; PHI0 ;
+; RA[1] ; PHI0 ; 4.217 ; 4.217 ; Rise ; PHI0 ;
+; RA[2] ; PHI0 ; 2.603 ; 2.603 ; Rise ; PHI0 ;
+; RA[3] ; PHI0 ; 4.015 ; 4.015 ; Rise ; PHI0 ;
+; RA[7] ; PHI0 ; 4.423 ; 4.423 ; Rise ; PHI0 ;
+; RA[8] ; PHI0 ; 7.040 ; 7.040 ; Rise ; PHI0 ;
+; RA[9] ; PHI0 ; 6.755 ; 6.755 ; Rise ; PHI0 ;
+; RA[10] ; PHI0 ; 5.245 ; 5.245 ; Rise ; PHI0 ;
+; RA[11] ; PHI0 ; 6.729 ; 6.729 ; Rise ; PHI0 ;
+; RA[12] ; PHI0 ; 7.343 ; 7.343 ; Rise ; PHI0 ;
+; RA[13] ; PHI0 ; 6.787 ; 6.787 ; Rise ; PHI0 ;
+; RA[14] ; PHI0 ; 7.446 ; 7.446 ; Rise ; PHI0 ;
+; RA[15] ; PHI0 ; 6.914 ; 6.914 ; Rise ; PHI0 ;
+; SetFW[*] ; PHI0 ; 4.443 ; 4.443 ; Rise ; PHI0 ;
+; SetFW[0] ; PHI0 ; 1.360 ; 1.360 ; Rise ; PHI0 ;
+; SetFW[1] ; PHI0 ; 4.443 ; 4.443 ; Rise ; PHI0 ;
+; nWE ; PHI0 ; 4.843 ; 4.843 ; Rise ; PHI0 ;
+-----------+------------+--------+--------+------------+-----------------+
@@ -687,69 +681,69 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
+-----------+------------+---------+---------+------------+-----------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+---------+---------+------------+-----------------+
-; MISO ; C25M ; -3.074 ; -3.074 ; Rise ; C25M ;
-; MOSI ; C25M ; -2.580 ; -2.580 ; Rise ; C25M ;
-; PHI0 ; C25M ; -1.288 ; -1.288 ; Rise ; C25M ;
-; RA[*] ; C25M ; -3.928 ; -3.928 ; Rise ; C25M ;
-; RA[0] ; C25M ; -4.918 ; -4.918 ; Rise ; C25M ;
-; RA[1] ; C25M ; -4.935 ; -4.935 ; Rise ; C25M ;
-; RA[2] ; C25M ; -4.605 ; -4.605 ; Rise ; C25M ;
-; RA[3] ; C25M ; -6.231 ; -6.231 ; Rise ; C25M ;
-; RA[4] ; C25M ; -6.105 ; -6.105 ; Rise ; C25M ;
-; RA[5] ; C25M ; -5.742 ; -5.742 ; Rise ; C25M ;
-; RA[6] ; C25M ; -5.229 ; -5.229 ; Rise ; C25M ;
-; RA[7] ; C25M ; -6.491 ; -6.491 ; Rise ; C25M ;
-; RA[8] ; C25M ; -5.819 ; -5.819 ; Rise ; C25M ;
-; RA[9] ; C25M ; -6.243 ; -6.243 ; Rise ; C25M ;
-; RA[10] ; C25M ; -5.745 ; -5.745 ; Rise ; C25M ;
-; RA[11] ; C25M ; -3.928 ; -3.928 ; Rise ; C25M ;
-; RA[12] ; C25M ; -9.999 ; -9.999 ; Rise ; C25M ;
-; RA[13] ; C25M ; -10.115 ; -10.115 ; Rise ; C25M ;
-; RA[14] ; C25M ; -8.966 ; -8.966 ; Rise ; C25M ;
-; RA[15] ; C25M ; -9.136 ; -9.136 ; Rise ; C25M ;
-; RD[*] ; C25M ; -1.915 ; -1.915 ; Rise ; C25M ;
-; RD[0] ; C25M ; -2.139 ; -2.139 ; Rise ; C25M ;
-; RD[1] ; C25M ; -2.095 ; -2.095 ; Rise ; C25M ;
-; RD[2] ; C25M ; -1.915 ; -1.915 ; Rise ; C25M ;
-; RD[3] ; C25M ; -2.074 ; -2.074 ; Rise ; C25M ;
-; RD[4] ; C25M ; -2.111 ; -2.111 ; Rise ; C25M ;
-; RD[5] ; C25M ; -2.050 ; -2.050 ; Rise ; C25M ;
-; RD[6] ; C25M ; -2.646 ; -2.646 ; Rise ; C25M ;
-; RD[7] ; C25M ; -2.403 ; -2.403 ; Rise ; C25M ;
-; SD[*] ; C25M ; -2.459 ; -2.459 ; Rise ; C25M ;
-; SD[0] ; C25M ; -2.760 ; -2.760 ; Rise ; C25M ;
-; SD[1] ; C25M ; -3.327 ; -3.327 ; Rise ; C25M ;
-; SD[2] ; C25M ; -2.481 ; -2.481 ; Rise ; C25M ;
-; SD[3] ; C25M ; -2.789 ; -2.789 ; Rise ; C25M ;
-; SD[4] ; C25M ; -3.151 ; -3.151 ; Rise ; C25M ;
-; SD[5] ; C25M ; -2.459 ; -2.459 ; Rise ; C25M ;
-; SD[6] ; C25M ; -2.602 ; -2.602 ; Rise ; C25M ;
-; SD[7] ; C25M ; -2.547 ; -2.547 ; Rise ; C25M ;
-; SetFW[*] ; C25M ; -2.655 ; -2.655 ; Rise ; C25M ;
-; SetFW[0] ; C25M ; -2.983 ; -2.983 ; Rise ; C25M ;
-; SetFW[1] ; C25M ; -2.655 ; -2.655 ; Rise ; C25M ;
-; nDEVSEL ; C25M ; -2.932 ; -2.932 ; Rise ; C25M ;
-; nIOSEL ; C25M ; -2.343 ; -2.343 ; Rise ; C25M ;
-; nIOSTRB ; C25M ; -4.377 ; -4.377 ; Rise ; C25M ;
-; nRES ; C25M ; -4.188 ; -4.188 ; Rise ; C25M ;
-; RA[*] ; PHI0 ; -0.183 ; -0.183 ; Rise ; PHI0 ;
-; RA[0] ; PHI0 ; -0.243 ; -0.243 ; Rise ; PHI0 ;
-; RA[1] ; PHI0 ; -0.183 ; -0.183 ; Rise ; PHI0 ;
-; RA[2] ; PHI0 ; -3.821 ; -3.821 ; Rise ; PHI0 ;
-; RA[3] ; PHI0 ; -2.221 ; -2.221 ; Rise ; PHI0 ;
-; RA[7] ; PHI0 ; -3.663 ; -3.663 ; Rise ; PHI0 ;
-; RA[8] ; PHI0 ; -2.586 ; -2.586 ; Rise ; PHI0 ;
-; RA[9] ; PHI0 ; -2.778 ; -2.778 ; Rise ; PHI0 ;
-; RA[10] ; PHI0 ; -4.789 ; -4.789 ; Rise ; PHI0 ;
-; RA[11] ; PHI0 ; -2.436 ; -2.436 ; Rise ; PHI0 ;
-; RA[12] ; PHI0 ; -3.708 ; -3.708 ; Rise ; PHI0 ;
-; RA[13] ; PHI0 ; -3.824 ; -3.824 ; Rise ; PHI0 ;
-; RA[14] ; PHI0 ; -2.675 ; -2.675 ; Rise ; PHI0 ;
-; RA[15] ; PHI0 ; -2.845 ; -2.845 ; Rise ; PHI0 ;
-; SetFW[*] ; PHI0 ; -1.190 ; -1.190 ; Rise ; PHI0 ;
-; SetFW[0] ; PHI0 ; -1.190 ; -1.190 ; Rise ; PHI0 ;
-; SetFW[1] ; PHI0 ; -1.352 ; -1.352 ; Rise ; PHI0 ;
-; nWE ; PHI0 ; 0.066 ; 0.066 ; Rise ; PHI0 ;
+; MISO ; C25M ; -2.653 ; -2.653 ; Rise ; C25M ;
+; MOSI ; C25M ; -4.219 ; -4.219 ; Rise ; C25M ;
+; PHI0 ; C25M ; -1.537 ; -1.537 ; Rise ; C25M ;
+; RA[*] ; C25M ; -4.004 ; -4.004 ; Rise ; C25M ;
+; RA[0] ; C25M ; -4.369 ; -4.369 ; Rise ; C25M ;
+; RA[1] ; C25M ; -4.004 ; -4.004 ; Rise ; C25M ;
+; RA[2] ; C25M ; -5.968 ; -5.968 ; Rise ; C25M ;
+; RA[3] ; C25M ; -7.190 ; -7.190 ; Rise ; C25M ;
+; RA[4] ; C25M ; -5.899 ; -5.899 ; Rise ; C25M ;
+; RA[5] ; C25M ; -4.230 ; -4.230 ; Rise ; C25M ;
+; RA[6] ; C25M ; -5.612 ; -5.612 ; Rise ; C25M ;
+; RA[7] ; C25M ; -5.349 ; -5.349 ; Rise ; C25M ;
+; RA[8] ; C25M ; -5.488 ; -5.488 ; Rise ; C25M ;
+; RA[9] ; C25M ; -6.370 ; -6.370 ; Rise ; C25M ;
+; RA[10] ; C25M ; -4.133 ; -4.133 ; Rise ; C25M ;
+; RA[11] ; C25M ; -4.481 ; -4.481 ; Rise ; C25M ;
+; RA[12] ; C25M ; -11.451 ; -11.451 ; Rise ; C25M ;
+; RA[13] ; C25M ; -10.895 ; -10.895 ; Rise ; C25M ;
+; RA[14] ; C25M ; -11.554 ; -11.554 ; Rise ; C25M ;
+; RA[15] ; C25M ; -11.022 ; -11.022 ; Rise ; C25M ;
+; RD[*] ; C25M ; -2.043 ; -2.043 ; Rise ; C25M ;
+; RD[0] ; C25M ; -2.645 ; -2.645 ; Rise ; C25M ;
+; RD[1] ; C25M ; -2.643 ; -2.643 ; Rise ; C25M ;
+; RD[2] ; C25M ; -2.161 ; -2.161 ; Rise ; C25M ;
+; RD[3] ; C25M ; -2.245 ; -2.245 ; Rise ; C25M ;
+; RD[4] ; C25M ; -2.117 ; -2.117 ; Rise ; C25M ;
+; RD[5] ; C25M ; -2.102 ; -2.102 ; Rise ; C25M ;
+; RD[6] ; C25M ; -2.043 ; -2.043 ; Rise ; C25M ;
+; RD[7] ; C25M ; -2.080 ; -2.080 ; Rise ; C25M ;
+; SD[*] ; C25M ; -2.558 ; -2.558 ; Rise ; C25M ;
+; SD[0] ; C25M ; -2.907 ; -2.907 ; Rise ; C25M ;
+; SD[1] ; C25M ; -2.586 ; -2.586 ; Rise ; C25M ;
+; SD[2] ; C25M ; -6.119 ; -6.119 ; Rise ; C25M ;
+; SD[3] ; C25M ; -4.232 ; -4.232 ; Rise ; C25M ;
+; SD[4] ; C25M ; -2.877 ; -2.877 ; Rise ; C25M ;
+; SD[5] ; C25M ; -2.564 ; -2.564 ; Rise ; C25M ;
+; SD[6] ; C25M ; -2.558 ; -2.558 ; Rise ; C25M ;
+; SD[7] ; C25M ; -3.238 ; -3.238 ; Rise ; C25M ;
+; SetFW[*] ; C25M ; -3.532 ; -3.532 ; Rise ; C25M ;
+; SetFW[0] ; C25M ; -3.626 ; -3.626 ; Rise ; C25M ;
+; SetFW[1] ; C25M ; -3.532 ; -3.532 ; Rise ; C25M ;
+; nDEVSEL ; C25M ; -2.650 ; -2.650 ; Rise ; C25M ;
+; nIOSEL ; C25M ; -2.835 ; -2.835 ; Rise ; C25M ;
+; nIOSTRB ; C25M ; -6.727 ; -6.727 ; Rise ; C25M ;
+; nRES ; C25M ; -2.709 ; -2.709 ; Rise ; C25M ;
+; RA[*] ; PHI0 ; -0.095 ; -0.095 ; Rise ; PHI0 ;
+; RA[0] ; PHI0 ; -0.095 ; -0.095 ; Rise ; PHI0 ;
+; RA[1] ; PHI0 ; -3.663 ; -3.663 ; Rise ; PHI0 ;
+; RA[2] ; PHI0 ; -2.049 ; -2.049 ; Rise ; PHI0 ;
+; RA[3] ; PHI0 ; -3.461 ; -3.461 ; Rise ; PHI0 ;
+; RA[7] ; PHI0 ; -3.869 ; -3.869 ; Rise ; PHI0 ;
+; RA[8] ; PHI0 ; -2.719 ; -2.719 ; Rise ; PHI0 ;
+; RA[9] ; PHI0 ; -2.434 ; -2.434 ; Rise ; PHI0 ;
+; RA[10] ; PHI0 ; -0.924 ; -0.924 ; Rise ; PHI0 ;
+; RA[11] ; PHI0 ; -2.408 ; -2.408 ; Rise ; PHI0 ;
+; RA[12] ; PHI0 ; -4.978 ; -4.978 ; Rise ; PHI0 ;
+; RA[13] ; PHI0 ; -4.422 ; -4.422 ; Rise ; PHI0 ;
+; RA[14] ; PHI0 ; -5.081 ; -5.081 ; Rise ; PHI0 ;
+; RA[15] ; PHI0 ; -4.549 ; -4.549 ; Rise ; PHI0 ;
+; SetFW[*] ; PHI0 ; -0.806 ; -0.806 ; Rise ; PHI0 ;
+; SetFW[0] ; PHI0 ; -0.806 ; -0.806 ; Rise ; PHI0 ;
+; SetFW[1] ; PHI0 ; -3.889 ; -3.889 ; Rise ; PHI0 ;
+; nWE ; PHI0 ; -4.289 ; -4.289 ; Rise ; PHI0 ;
+-----------+------------+---------+---------+------------+-----------------+
@@ -758,55 +752,55 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
+-----------+------------+--------+--------+------------+-----------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+--------+--------+------------+-----------------+
-; DQMH ; C25M ; 10.022 ; 10.022 ; Rise ; C25M ;
-; DQML ; C25M ; 9.946 ; 9.946 ; Rise ; C25M ;
-; FCK ; C25M ; 7.598 ; 7.598 ; Rise ; C25M ;
-; MOSI ; C25M ; 8.888 ; 8.888 ; Rise ; C25M ;
-; RCKE ; C25M ; 8.328 ; 8.328 ; Rise ; C25M ;
-; RD[*] ; C25M ; 8.814 ; 8.814 ; Rise ; C25M ;
-; RD[0] ; C25M ; 8.712 ; 8.712 ; Rise ; C25M ;
-; RD[1] ; C25M ; 8.756 ; 8.756 ; Rise ; C25M ;
-; RD[2] ; C25M ; 8.734 ; 8.734 ; Rise ; C25M ;
-; RD[3] ; C25M ; 8.759 ; 8.759 ; Rise ; C25M ;
-; RD[4] ; C25M ; 8.399 ; 8.399 ; Rise ; C25M ;
-; RD[5] ; C25M ; 8.314 ; 8.314 ; Rise ; C25M ;
-; RD[6] ; C25M ; 8.433 ; 8.433 ; Rise ; C25M ;
-; RD[7] ; C25M ; 8.814 ; 8.814 ; Rise ; C25M ;
-; RDdir ; C25M ; 12.952 ; 12.952 ; Rise ; C25M ;
-; SA[*] ; C25M ; 8.981 ; 8.981 ; Rise ; C25M ;
-; SA[0] ; C25M ; 8.671 ; 8.671 ; Rise ; C25M ;
-; SA[1] ; C25M ; 8.812 ; 8.812 ; Rise ; C25M ;
-; SA[2] ; C25M ; 8.981 ; 8.981 ; Rise ; C25M ;
-; SA[3] ; C25M ; 8.095 ; 8.095 ; Rise ; C25M ;
-; SA[4] ; C25M ; 8.105 ; 8.105 ; Rise ; C25M ;
-; SA[5] ; C25M ; 8.250 ; 8.250 ; Rise ; C25M ;
-; SA[6] ; C25M ; 8.122 ; 8.122 ; Rise ; C25M ;
-; SA[7] ; C25M ; 8.125 ; 8.125 ; Rise ; C25M ;
-; SA[8] ; C25M ; 8.264 ; 8.264 ; Rise ; C25M ;
-; SA[9] ; C25M ; 8.746 ; 8.746 ; Rise ; C25M ;
-; SA[10] ; C25M ; 8.454 ; 8.454 ; Rise ; C25M ;
-; SA[11] ; C25M ; 8.204 ; 8.204 ; Rise ; C25M ;
-; SA[12] ; C25M ; 8.825 ; 8.825 ; Rise ; C25M ;
-; SBA[*] ; C25M ; 8.250 ; 8.250 ; Rise ; C25M ;
-; SBA[0] ; C25M ; 7.556 ; 7.556 ; Rise ; C25M ;
-; SBA[1] ; C25M ; 8.250 ; 8.250 ; Rise ; C25M ;
-; SD[*] ; C25M ; 12.597 ; 12.597 ; Rise ; C25M ;
-; SD[0] ; C25M ; 8.735 ; 8.735 ; Rise ; C25M ;
-; SD[1] ; C25M ; 8.691 ; 8.691 ; Rise ; C25M ;
-; SD[2] ; C25M ; 8.215 ; 8.215 ; Rise ; C25M ;
-; SD[3] ; C25M ; 9.967 ; 9.967 ; Rise ; C25M ;
-; SD[4] ; C25M ; 8.709 ; 8.709 ; Rise ; C25M ;
-; SD[5] ; C25M ; 12.597 ; 12.597 ; Rise ; C25M ;
-; SD[6] ; C25M ; 8.580 ; 8.580 ; Rise ; C25M ;
-; SD[7] ; C25M ; 8.801 ; 8.801 ; Rise ; C25M ;
-; nCAS ; C25M ; 8.427 ; 8.427 ; Rise ; C25M ;
-; nFCS ; C25M ; 6.964 ; 6.964 ; Rise ; C25M ;
-; nRAS ; C25M ; 8.315 ; 8.315 ; Rise ; C25M ;
-; nRCS ; C25M ; 8.834 ; 8.834 ; Rise ; C25M ;
-; nRESout ; C25M ; 8.019 ; 8.019 ; Rise ; C25M ;
-; nSWE ; C25M ; 7.580 ; 7.580 ; Rise ; C25M ;
-; RDdir ; PHI0 ; 9.713 ; 9.713 ; Rise ; PHI0 ;
-; RDdir ; PHI0 ; 9.713 ; 9.713 ; Fall ; PHI0 ;
+; DQMH ; C25M ; 8.822 ; 8.822 ; Rise ; C25M ;
+; DQML ; C25M ; 11.807 ; 11.807 ; Rise ; C25M ;
+; FCK ; C25M ; 8.749 ; 8.749 ; Rise ; C25M ;
+; MOSI ; C25M ; 8.378 ; 8.378 ; Rise ; C25M ;
+; RCKE ; C25M ; 9.898 ; 9.898 ; Rise ; C25M ;
+; RD[*] ; C25M ; 10.058 ; 10.058 ; Rise ; C25M ;
+; RD[0] ; C25M ; 10.058 ; 10.058 ; Rise ; C25M ;
+; RD[1] ; C25M ; 8.785 ; 8.785 ; Rise ; C25M ;
+; RD[2] ; C25M ; 9.255 ; 9.255 ; Rise ; C25M ;
+; RD[3] ; C25M ; 9.249 ; 9.249 ; Rise ; C25M ;
+; RD[4] ; C25M ; 8.834 ; 8.834 ; Rise ; C25M ;
+; RD[5] ; C25M ; 9.259 ; 9.259 ; Rise ; C25M ;
+; RD[6] ; C25M ; 8.783 ; 8.783 ; Rise ; C25M ;
+; RD[7] ; C25M ; 8.702 ; 8.702 ; Rise ; C25M ;
+; RDdir ; C25M ; 16.870 ; 16.870 ; Rise ; C25M ;
+; SA[*] ; C25M ; 10.609 ; 10.609 ; Rise ; C25M ;
+; SA[0] ; C25M ; 8.838 ; 8.838 ; Rise ; C25M ;
+; SA[1] ; C25M ; 10.609 ; 10.609 ; Rise ; C25M ;
+; SA[2] ; C25M ; 9.346 ; 9.346 ; Rise ; C25M ;
+; SA[3] ; C25M ; 8.149 ; 8.149 ; Rise ; C25M ;
+; SA[4] ; C25M ; 8.023 ; 8.023 ; Rise ; C25M ;
+; SA[5] ; C25M ; 8.225 ; 8.225 ; Rise ; C25M ;
+; SA[6] ; C25M ; 8.559 ; 8.559 ; Rise ; C25M ;
+; SA[7] ; C25M ; 8.483 ; 8.483 ; Rise ; C25M ;
+; SA[8] ; C25M ; 7.589 ; 7.589 ; Rise ; C25M ;
+; SA[9] ; C25M ; 8.230 ; 8.230 ; Rise ; C25M ;
+; SA[10] ; C25M ; 8.766 ; 8.766 ; Rise ; C25M ;
+; SA[11] ; C25M ; 8.394 ; 8.394 ; Rise ; C25M ;
+; SA[12] ; C25M ; 8.338 ; 8.338 ; Rise ; C25M ;
+; SBA[*] ; C25M ; 8.683 ; 8.683 ; Rise ; C25M ;
+; SBA[0] ; C25M ; 8.683 ; 8.683 ; Rise ; C25M ;
+; SBA[1] ; C25M ; 8.474 ; 8.474 ; Rise ; C25M ;
+; SD[*] ; C25M ; 10.171 ; 10.171 ; Rise ; C25M ;
+; SD[0] ; C25M ; 8.728 ; 8.728 ; Rise ; C25M ;
+; SD[1] ; C25M ; 8.231 ; 8.231 ; Rise ; C25M ;
+; SD[2] ; C25M ; 8.242 ; 8.242 ; Rise ; C25M ;
+; SD[3] ; C25M ; 8.828 ; 8.828 ; Rise ; C25M ;
+; SD[4] ; C25M ; 10.171 ; 10.171 ; Rise ; C25M ;
+; SD[5] ; C25M ; 8.719 ; 8.719 ; Rise ; C25M ;
+; SD[6] ; C25M ; 6.942 ; 6.942 ; Rise ; C25M ;
+; SD[7] ; C25M ; 8.113 ; 8.113 ; Rise ; C25M ;
+; nCAS ; C25M ; 8.009 ; 8.009 ; Rise ; C25M ;
+; nFCS ; C25M ; 9.004 ; 9.004 ; Rise ; C25M ;
+; nRAS ; C25M ; 8.417 ; 8.417 ; Rise ; C25M ;
+; nRCS ; C25M ; 11.091 ; 11.091 ; Rise ; C25M ;
+; nRESout ; C25M ; 9.056 ; 9.056 ; Rise ; C25M ;
+; nSWE ; C25M ; 8.685 ; 8.685 ; Rise ; C25M ;
+; RDdir ; PHI0 ; 12.126 ; 12.126 ; Rise ; PHI0 ;
+; RDdir ; PHI0 ; 12.126 ; 12.126 ; Fall ; PHI0 ;
+-----------+------------+--------+--------+------------+-----------------+
@@ -815,55 +809,55 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
+-----------+------------+--------+--------+------------+-----------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+--------+--------+------------+-----------------+
-; DQMH ; C25M ; 10.022 ; 10.022 ; Rise ; C25M ;
-; DQML ; C25M ; 9.946 ; 9.946 ; Rise ; C25M ;
-; FCK ; C25M ; 7.598 ; 7.598 ; Rise ; C25M ;
-; MOSI ; C25M ; 8.888 ; 8.888 ; Rise ; C25M ;
-; RCKE ; C25M ; 8.328 ; 8.328 ; Rise ; C25M ;
-; RD[*] ; C25M ; 8.314 ; 8.314 ; Rise ; C25M ;
-; RD[0] ; C25M ; 8.712 ; 8.712 ; Rise ; C25M ;
-; RD[1] ; C25M ; 8.756 ; 8.756 ; Rise ; C25M ;
-; RD[2] ; C25M ; 8.734 ; 8.734 ; Rise ; C25M ;
-; RD[3] ; C25M ; 8.759 ; 8.759 ; Rise ; C25M ;
-; RD[4] ; C25M ; 8.399 ; 8.399 ; Rise ; C25M ;
-; RD[5] ; C25M ; 8.314 ; 8.314 ; Rise ; C25M ;
-; RD[6] ; C25M ; 8.433 ; 8.433 ; Rise ; C25M ;
-; RD[7] ; C25M ; 8.814 ; 8.814 ; Rise ; C25M ;
-; RDdir ; C25M ; 9.306 ; 9.306 ; Rise ; C25M ;
-; SA[*] ; C25M ; 8.095 ; 8.095 ; Rise ; C25M ;
-; SA[0] ; C25M ; 8.671 ; 8.671 ; Rise ; C25M ;
-; SA[1] ; C25M ; 8.812 ; 8.812 ; Rise ; C25M ;
-; SA[2] ; C25M ; 8.981 ; 8.981 ; Rise ; C25M ;
-; SA[3] ; C25M ; 8.095 ; 8.095 ; Rise ; C25M ;
-; SA[4] ; C25M ; 8.105 ; 8.105 ; Rise ; C25M ;
-; SA[5] ; C25M ; 8.250 ; 8.250 ; Rise ; C25M ;
-; SA[6] ; C25M ; 8.122 ; 8.122 ; Rise ; C25M ;
-; SA[7] ; C25M ; 8.125 ; 8.125 ; Rise ; C25M ;
-; SA[8] ; C25M ; 8.264 ; 8.264 ; Rise ; C25M ;
-; SA[9] ; C25M ; 8.746 ; 8.746 ; Rise ; C25M ;
-; SA[10] ; C25M ; 8.454 ; 8.454 ; Rise ; C25M ;
-; SA[11] ; C25M ; 8.204 ; 8.204 ; Rise ; C25M ;
-; SA[12] ; C25M ; 8.825 ; 8.825 ; Rise ; C25M ;
-; SBA[*] ; C25M ; 7.556 ; 7.556 ; Rise ; C25M ;
-; SBA[0] ; C25M ; 7.556 ; 7.556 ; Rise ; C25M ;
-; SBA[1] ; C25M ; 8.250 ; 8.250 ; Rise ; C25M ;
-; SD[*] ; C25M ; 8.215 ; 8.215 ; Rise ; C25M ;
-; SD[0] ; C25M ; 8.735 ; 8.735 ; Rise ; C25M ;
-; SD[1] ; C25M ; 8.691 ; 8.691 ; Rise ; C25M ;
-; SD[2] ; C25M ; 8.215 ; 8.215 ; Rise ; C25M ;
-; SD[3] ; C25M ; 9.967 ; 9.967 ; Rise ; C25M ;
-; SD[4] ; C25M ; 8.709 ; 8.709 ; Rise ; C25M ;
-; SD[5] ; C25M ; 12.597 ; 12.597 ; Rise ; C25M ;
-; SD[6] ; C25M ; 8.580 ; 8.580 ; Rise ; C25M ;
-; SD[7] ; C25M ; 8.801 ; 8.801 ; Rise ; C25M ;
-; nCAS ; C25M ; 8.427 ; 8.427 ; Rise ; C25M ;
-; nFCS ; C25M ; 6.964 ; 6.964 ; Rise ; C25M ;
-; nRAS ; C25M ; 8.315 ; 8.315 ; Rise ; C25M ;
-; nRCS ; C25M ; 8.834 ; 8.834 ; Rise ; C25M ;
-; nRESout ; C25M ; 8.019 ; 8.019 ; Rise ; C25M ;
-; nSWE ; C25M ; 7.580 ; 7.580 ; Rise ; C25M ;
-; RDdir ; PHI0 ; 9.713 ; 9.713 ; Rise ; PHI0 ;
-; RDdir ; PHI0 ; 9.713 ; 9.713 ; Fall ; PHI0 ;
+; DQMH ; C25M ; 8.822 ; 8.822 ; Rise ; C25M ;
+; DQML ; C25M ; 11.807 ; 11.807 ; Rise ; C25M ;
+; FCK ; C25M ; 8.749 ; 8.749 ; Rise ; C25M ;
+; MOSI ; C25M ; 8.378 ; 8.378 ; Rise ; C25M ;
+; RCKE ; C25M ; 9.898 ; 9.898 ; Rise ; C25M ;
+; RD[*] ; C25M ; 8.702 ; 8.702 ; Rise ; C25M ;
+; RD[0] ; C25M ; 10.058 ; 10.058 ; Rise ; C25M ;
+; RD[1] ; C25M ; 8.785 ; 8.785 ; Rise ; C25M ;
+; RD[2] ; C25M ; 9.255 ; 9.255 ; Rise ; C25M ;
+; RD[3] ; C25M ; 9.249 ; 9.249 ; Rise ; C25M ;
+; RD[4] ; C25M ; 8.834 ; 8.834 ; Rise ; C25M ;
+; RD[5] ; C25M ; 9.259 ; 9.259 ; Rise ; C25M ;
+; RD[6] ; C25M ; 8.783 ; 8.783 ; Rise ; C25M ;
+; RD[7] ; C25M ; 8.702 ; 8.702 ; Rise ; C25M ;
+; RDdir ; C25M ; 11.471 ; 11.471 ; Rise ; C25M ;
+; SA[*] ; C25M ; 7.589 ; 7.589 ; Rise ; C25M ;
+; SA[0] ; C25M ; 8.838 ; 8.838 ; Rise ; C25M ;
+; SA[1] ; C25M ; 10.609 ; 10.609 ; Rise ; C25M ;
+; SA[2] ; C25M ; 9.346 ; 9.346 ; Rise ; C25M ;
+; SA[3] ; C25M ; 8.149 ; 8.149 ; Rise ; C25M ;
+; SA[4] ; C25M ; 8.023 ; 8.023 ; Rise ; C25M ;
+; SA[5] ; C25M ; 8.225 ; 8.225 ; Rise ; C25M ;
+; SA[6] ; C25M ; 8.559 ; 8.559 ; Rise ; C25M ;
+; SA[7] ; C25M ; 8.483 ; 8.483 ; Rise ; C25M ;
+; SA[8] ; C25M ; 7.589 ; 7.589 ; Rise ; C25M ;
+; SA[9] ; C25M ; 8.230 ; 8.230 ; Rise ; C25M ;
+; SA[10] ; C25M ; 8.766 ; 8.766 ; Rise ; C25M ;
+; SA[11] ; C25M ; 8.394 ; 8.394 ; Rise ; C25M ;
+; SA[12] ; C25M ; 8.338 ; 8.338 ; Rise ; C25M ;
+; SBA[*] ; C25M ; 8.474 ; 8.474 ; Rise ; C25M ;
+; SBA[0] ; C25M ; 8.683 ; 8.683 ; Rise ; C25M ;
+; SBA[1] ; C25M ; 8.474 ; 8.474 ; Rise ; C25M ;
+; SD[*] ; C25M ; 6.942 ; 6.942 ; Rise ; C25M ;
+; SD[0] ; C25M ; 8.728 ; 8.728 ; Rise ; C25M ;
+; SD[1] ; C25M ; 8.231 ; 8.231 ; Rise ; C25M ;
+; SD[2] ; C25M ; 8.242 ; 8.242 ; Rise ; C25M ;
+; SD[3] ; C25M ; 8.828 ; 8.828 ; Rise ; C25M ;
+; SD[4] ; C25M ; 10.171 ; 10.171 ; Rise ; C25M ;
+; SD[5] ; C25M ; 8.719 ; 8.719 ; Rise ; C25M ;
+; SD[6] ; C25M ; 6.942 ; 6.942 ; Rise ; C25M ;
+; SD[7] ; C25M ; 8.113 ; 8.113 ; Rise ; C25M ;
+; nCAS ; C25M ; 8.009 ; 8.009 ; Rise ; C25M ;
+; nFCS ; C25M ; 9.004 ; 9.004 ; Rise ; C25M ;
+; nRAS ; C25M ; 8.417 ; 8.417 ; Rise ; C25M ;
+; nRCS ; C25M ; 11.091 ; 11.091 ; Rise ; C25M ;
+; nRESout ; C25M ; 9.056 ; 9.056 ; Rise ; C25M ;
+; nSWE ; C25M ; 8.685 ; 8.685 ; Rise ; C25M ;
+; RDdir ; PHI0 ; 12.126 ; 12.126 ; Rise ; PHI0 ;
+; RDdir ; PHI0 ; 12.126 ; 12.126 ; Fall ; PHI0 ;
+-----------+------------+--------+--------+------------+-----------------+
@@ -872,42 +866,44 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
+------------+-------------+--------+----+----+--------+
; Input Port ; Output Port ; RR ; RF ; FR ; FF ;
+------------+-------------+--------+----+----+--------+
-; nDEVSEL ; RD[0] ; 13.003 ; ; ; 13.003 ;
-; nDEVSEL ; RD[1] ; 13.003 ; ; ; 13.003 ;
-; nDEVSEL ; RD[2] ; 13.003 ; ; ; 13.003 ;
-; nDEVSEL ; RD[3] ; 15.028 ; ; ; 15.028 ;
-; nDEVSEL ; RD[4] ; 15.028 ; ; ; 15.028 ;
-; nDEVSEL ; RD[5] ; 15.028 ; ; ; 15.028 ;
-; nDEVSEL ; RD[6] ; 15.028 ; ; ; 15.028 ;
-; nDEVSEL ; RD[7] ; 15.572 ; ; ; 15.572 ;
-; nDEVSEL ; RDdir ; 13.983 ; ; ; 13.983 ;
-; nIOSEL ; RD[0] ; 12.278 ; ; ; 12.278 ;
-; nIOSEL ; RD[1] ; 12.278 ; ; ; 12.278 ;
-; nIOSEL ; RD[2] ; 12.278 ; ; ; 12.278 ;
-; nIOSEL ; RD[3] ; 14.303 ; ; ; 14.303 ;
-; nIOSEL ; RD[4] ; 14.303 ; ; ; 14.303 ;
-; nIOSEL ; RD[5] ; 14.303 ; ; ; 14.303 ;
-; nIOSEL ; RD[6] ; 14.303 ; ; ; 14.303 ;
-; nIOSEL ; RD[7] ; 14.847 ; ; ; 14.847 ;
-; nIOSEL ; RDdir ; 13.258 ; ; ; 13.258 ;
-; nIOSTRB ; RD[0] ; 12.821 ; ; ; 12.821 ;
-; nIOSTRB ; RD[1] ; 12.821 ; ; ; 12.821 ;
-; nIOSTRB ; RD[2] ; 12.821 ; ; ; 12.821 ;
-; nIOSTRB ; RD[3] ; 14.846 ; ; ; 14.846 ;
-; nIOSTRB ; RD[4] ; 14.846 ; ; ; 14.846 ;
-; nIOSTRB ; RD[5] ; 14.846 ; ; ; 14.846 ;
-; nIOSTRB ; RD[6] ; 14.846 ; ; ; 14.846 ;
-; nIOSTRB ; RD[7] ; 15.390 ; ; ; 15.390 ;
-; nIOSTRB ; RDdir ; 13.801 ; ; ; 13.801 ;
-; nWE ; RD[0] ; 11.864 ; ; ; 11.864 ;
-; nWE ; RD[1] ; 11.864 ; ; ; 11.864 ;
-; nWE ; RD[2] ; 11.864 ; ; ; 11.864 ;
-; nWE ; RD[3] ; 13.889 ; ; ; 13.889 ;
-; nWE ; RD[4] ; 13.889 ; ; ; 13.889 ;
-; nWE ; RD[5] ; 13.889 ; ; ; 13.889 ;
-; nWE ; RD[6] ; 13.889 ; ; ; 13.889 ;
-; nWE ; RD[7] ; 14.433 ; ; ; 14.433 ;
-; nWE ; RDdir ; 12.844 ; ; ; 12.844 ;
+; DMAin ; DMAout ; 8.209 ; ; ; 8.209 ;
+; INTin ; INTout ; 8.936 ; ; ; 8.936 ;
+; nDEVSEL ; RD[0] ; 12.492 ; ; ; 12.492 ;
+; nDEVSEL ; RD[1] ; 12.492 ; ; ; 12.492 ;
+; nDEVSEL ; RD[2] ; 12.492 ; ; ; 12.492 ;
+; nDEVSEL ; RD[3] ; 12.492 ; ; ; 12.492 ;
+; nDEVSEL ; RD[4] ; 12.492 ; ; ; 12.492 ;
+; nDEVSEL ; RD[5] ; 12.492 ; ; ; 12.492 ;
+; nDEVSEL ; RD[6] ; 12.907 ; ; ; 12.907 ;
+; nDEVSEL ; RD[7] ; 13.680 ; ; ; 13.680 ;
+; nDEVSEL ; RDdir ; 15.627 ; ; ; 15.627 ;
+; nIOSEL ; RD[0] ; 12.748 ; ; ; 12.748 ;
+; nIOSEL ; RD[1] ; 12.748 ; ; ; 12.748 ;
+; nIOSEL ; RD[2] ; 12.748 ; ; ; 12.748 ;
+; nIOSEL ; RD[3] ; 12.748 ; ; ; 12.748 ;
+; nIOSEL ; RD[4] ; 12.748 ; ; ; 12.748 ;
+; nIOSEL ; RD[5] ; 12.748 ; ; ; 12.748 ;
+; nIOSEL ; RD[6] ; 13.163 ; ; ; 13.163 ;
+; nIOSEL ; RD[7] ; 13.936 ; ; ; 13.936 ;
+; nIOSEL ; RDdir ; 15.883 ; ; ; 15.883 ;
+; nIOSTRB ; RD[0] ; 12.388 ; ; ; 12.388 ;
+; nIOSTRB ; RD[1] ; 12.388 ; ; ; 12.388 ;
+; nIOSTRB ; RD[2] ; 12.388 ; ; ; 12.388 ;
+; nIOSTRB ; RD[3] ; 12.388 ; ; ; 12.388 ;
+; nIOSTRB ; RD[4] ; 12.388 ; ; ; 12.388 ;
+; nIOSTRB ; RD[5] ; 12.388 ; ; ; 12.388 ;
+; nIOSTRB ; RD[6] ; 12.803 ; ; ; 12.803 ;
+; nIOSTRB ; RD[7] ; 13.576 ; ; ; 13.576 ;
+; nIOSTRB ; RDdir ; 15.523 ; ; ; 15.523 ;
+; nWE ; RD[0] ; 11.375 ; ; ; 11.375 ;
+; nWE ; RD[1] ; 11.375 ; ; ; 11.375 ;
+; nWE ; RD[2] ; 11.375 ; ; ; 11.375 ;
+; nWE ; RD[3] ; 11.375 ; ; ; 11.375 ;
+; nWE ; RD[4] ; 11.375 ; ; ; 11.375 ;
+; nWE ; RD[5] ; 11.375 ; ; ; 11.375 ;
+; nWE ; RD[6] ; 11.790 ; ; ; 11.790 ;
+; nWE ; RD[7] ; 12.563 ; ; ; 12.563 ;
+; nWE ; RDdir ; 14.510 ; ; ; 14.510 ;
+------------+-------------+--------+----+----+--------+
@@ -916,42 +912,44 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
+------------+-------------+--------+----+----+--------+
; Input Port ; Output Port ; RR ; RF ; FR ; FF ;
+------------+-------------+--------+----+----+--------+
-; nDEVSEL ; RD[0] ; 13.003 ; ; ; 13.003 ;
-; nDEVSEL ; RD[1] ; 13.003 ; ; ; 13.003 ;
-; nDEVSEL ; RD[2] ; 13.003 ; ; ; 13.003 ;
-; nDEVSEL ; RD[3] ; 15.028 ; ; ; 15.028 ;
-; nDEVSEL ; RD[4] ; 15.028 ; ; ; 15.028 ;
-; nDEVSEL ; RD[5] ; 15.028 ; ; ; 15.028 ;
-; nDEVSEL ; RD[6] ; 15.028 ; ; ; 15.028 ;
-; nDEVSEL ; RD[7] ; 15.572 ; ; ; 15.572 ;
-; nDEVSEL ; RDdir ; 13.983 ; ; ; 13.983 ;
-; nIOSEL ; RD[0] ; 12.278 ; ; ; 12.278 ;
-; nIOSEL ; RD[1] ; 12.278 ; ; ; 12.278 ;
-; nIOSEL ; RD[2] ; 12.278 ; ; ; 12.278 ;
-; nIOSEL ; RD[3] ; 14.303 ; ; ; 14.303 ;
-; nIOSEL ; RD[4] ; 14.303 ; ; ; 14.303 ;
-; nIOSEL ; RD[5] ; 14.303 ; ; ; 14.303 ;
-; nIOSEL ; RD[6] ; 14.303 ; ; ; 14.303 ;
-; nIOSEL ; RD[7] ; 14.847 ; ; ; 14.847 ;
-; nIOSEL ; RDdir ; 13.258 ; ; ; 13.258 ;
-; nIOSTRB ; RD[0] ; 12.821 ; ; ; 12.821 ;
-; nIOSTRB ; RD[1] ; 12.821 ; ; ; 12.821 ;
-; nIOSTRB ; RD[2] ; 12.821 ; ; ; 12.821 ;
-; nIOSTRB ; RD[3] ; 14.846 ; ; ; 14.846 ;
-; nIOSTRB ; RD[4] ; 14.846 ; ; ; 14.846 ;
-; nIOSTRB ; RD[5] ; 14.846 ; ; ; 14.846 ;
-; nIOSTRB ; RD[6] ; 14.846 ; ; ; 14.846 ;
-; nIOSTRB ; RD[7] ; 15.390 ; ; ; 15.390 ;
-; nIOSTRB ; RDdir ; 13.801 ; ; ; 13.801 ;
-; nWE ; RD[0] ; 11.864 ; ; ; 11.864 ;
-; nWE ; RD[1] ; 11.864 ; ; ; 11.864 ;
-; nWE ; RD[2] ; 11.864 ; ; ; 11.864 ;
-; nWE ; RD[3] ; 13.889 ; ; ; 13.889 ;
-; nWE ; RD[4] ; 13.889 ; ; ; 13.889 ;
-; nWE ; RD[5] ; 13.889 ; ; ; 13.889 ;
-; nWE ; RD[6] ; 13.889 ; ; ; 13.889 ;
-; nWE ; RD[7] ; 14.433 ; ; ; 14.433 ;
-; nWE ; RDdir ; 12.844 ; ; ; 12.844 ;
+; DMAin ; DMAout ; 8.209 ; ; ; 8.209 ;
+; INTin ; INTout ; 8.936 ; ; ; 8.936 ;
+; nDEVSEL ; RD[0] ; 12.492 ; ; ; 12.492 ;
+; nDEVSEL ; RD[1] ; 12.492 ; ; ; 12.492 ;
+; nDEVSEL ; RD[2] ; 12.492 ; ; ; 12.492 ;
+; nDEVSEL ; RD[3] ; 12.492 ; ; ; 12.492 ;
+; nDEVSEL ; RD[4] ; 12.492 ; ; ; 12.492 ;
+; nDEVSEL ; RD[5] ; 12.492 ; ; ; 12.492 ;
+; nDEVSEL ; RD[6] ; 12.907 ; ; ; 12.907 ;
+; nDEVSEL ; RD[7] ; 13.680 ; ; ; 13.680 ;
+; nDEVSEL ; RDdir ; 15.627 ; ; ; 15.627 ;
+; nIOSEL ; RD[0] ; 12.748 ; ; ; 12.748 ;
+; nIOSEL ; RD[1] ; 12.748 ; ; ; 12.748 ;
+; nIOSEL ; RD[2] ; 12.748 ; ; ; 12.748 ;
+; nIOSEL ; RD[3] ; 12.748 ; ; ; 12.748 ;
+; nIOSEL ; RD[4] ; 12.748 ; ; ; 12.748 ;
+; nIOSEL ; RD[5] ; 12.748 ; ; ; 12.748 ;
+; nIOSEL ; RD[6] ; 13.163 ; ; ; 13.163 ;
+; nIOSEL ; RD[7] ; 13.936 ; ; ; 13.936 ;
+; nIOSEL ; RDdir ; 15.883 ; ; ; 15.883 ;
+; nIOSTRB ; RD[0] ; 12.388 ; ; ; 12.388 ;
+; nIOSTRB ; RD[1] ; 12.388 ; ; ; 12.388 ;
+; nIOSTRB ; RD[2] ; 12.388 ; ; ; 12.388 ;
+; nIOSTRB ; RD[3] ; 12.388 ; ; ; 12.388 ;
+; nIOSTRB ; RD[4] ; 12.388 ; ; ; 12.388 ;
+; nIOSTRB ; RD[5] ; 12.388 ; ; ; 12.388 ;
+; nIOSTRB ; RD[6] ; 12.803 ; ; ; 12.803 ;
+; nIOSTRB ; RD[7] ; 13.576 ; ; ; 13.576 ;
+; nIOSTRB ; RDdir ; 15.523 ; ; ; 15.523 ;
+; nWE ; RD[0] ; 11.375 ; ; ; 11.375 ;
+; nWE ; RD[1] ; 11.375 ; ; ; 11.375 ;
+; nWE ; RD[2] ; 11.375 ; ; ; 11.375 ;
+; nWE ; RD[3] ; 11.375 ; ; ; 11.375 ;
+; nWE ; RD[4] ; 11.375 ; ; ; 11.375 ;
+; nWE ; RD[5] ; 11.375 ; ; ; 11.375 ;
+; nWE ; RD[6] ; 11.790 ; ; ; 11.790 ;
+; nWE ; RD[7] ; 12.563 ; ; ; 12.563 ;
+; nWE ; RDdir ; 14.510 ; ; ; 14.510 ;
+------------+-------------+--------+----+----+--------+
@@ -960,43 +958,45 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
+-----------+------------+--------+------+------------+-----------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+--------+------+------------+-----------------+
-; MOSI ; C25M ; 6.445 ; ; Rise ; C25M ;
-; RD[*] ; C25M ; 11.972 ; ; Rise ; C25M ;
-; RD[0] ; C25M ; 11.972 ; ; Rise ; C25M ;
-; RD[1] ; C25M ; 11.972 ; ; Rise ; C25M ;
-; RD[2] ; C25M ; 11.972 ; ; Rise ; C25M ;
-; RD[3] ; C25M ; 13.997 ; ; Rise ; C25M ;
-; RD[4] ; C25M ; 13.997 ; ; Rise ; C25M ;
-; RD[5] ; C25M ; 13.997 ; ; Rise ; C25M ;
-; RD[6] ; C25M ; 13.997 ; ; Rise ; C25M ;
-; RD[7] ; C25M ; 14.541 ; ; Rise ; C25M ;
-; SD[*] ; C25M ; 6.922 ; ; Rise ; C25M ;
-; SD[0] ; C25M ; 6.922 ; ; Rise ; C25M ;
-; SD[1] ; C25M ; 6.922 ; ; Rise ; C25M ;
-; SD[2] ; C25M ; 7.035 ; ; Rise ; C25M ;
-; SD[3] ; C25M ; 7.035 ; ; Rise ; C25M ;
-; SD[4] ; C25M ; 6.922 ; ; Rise ; C25M ;
-; SD[5] ; C25M ; 7.035 ; ; Rise ; C25M ;
-; SD[6] ; C25M ; 7.035 ; ; Rise ; C25M ;
-; SD[7] ; C25M ; 7.035 ; ; Rise ; C25M ;
-; RD[*] ; PHI0 ; 8.733 ; ; Rise ; PHI0 ;
-; RD[0] ; PHI0 ; 8.733 ; ; Rise ; PHI0 ;
-; RD[1] ; PHI0 ; 8.733 ; ; Rise ; PHI0 ;
-; RD[2] ; PHI0 ; 8.733 ; ; Rise ; PHI0 ;
-; RD[3] ; PHI0 ; 10.758 ; ; Rise ; PHI0 ;
-; RD[4] ; PHI0 ; 10.758 ; ; Rise ; PHI0 ;
-; RD[5] ; PHI0 ; 10.758 ; ; Rise ; PHI0 ;
-; RD[6] ; PHI0 ; 10.758 ; ; Rise ; PHI0 ;
-; RD[7] ; PHI0 ; 11.302 ; ; Rise ; PHI0 ;
-; RD[*] ; PHI0 ; 8.733 ; ; Fall ; PHI0 ;
-; RD[0] ; PHI0 ; 8.733 ; ; Fall ; PHI0 ;
-; RD[1] ; PHI0 ; 8.733 ; ; Fall ; PHI0 ;
-; RD[2] ; PHI0 ; 8.733 ; ; Fall ; PHI0 ;
-; RD[3] ; PHI0 ; 10.758 ; ; Fall ; PHI0 ;
-; RD[4] ; PHI0 ; 10.758 ; ; Fall ; PHI0 ;
-; RD[5] ; PHI0 ; 10.758 ; ; Fall ; PHI0 ;
-; RD[6] ; PHI0 ; 10.758 ; ; Fall ; PHI0 ;
-; RD[7] ; PHI0 ; 11.302 ; ; Fall ; PHI0 ;
+; FCK ; C25M ; 7.883 ; ; Rise ; C25M ;
+; MOSI ; C25M ; 7.607 ; ; Rise ; C25M ;
+; RD[*] ; C25M ; 13.735 ; ; Rise ; C25M ;
+; RD[0] ; C25M ; 13.735 ; ; Rise ; C25M ;
+; RD[1] ; C25M ; 13.735 ; ; Rise ; C25M ;
+; RD[2] ; C25M ; 13.735 ; ; Rise ; C25M ;
+; RD[3] ; C25M ; 13.735 ; ; Rise ; C25M ;
+; RD[4] ; C25M ; 13.735 ; ; Rise ; C25M ;
+; RD[5] ; C25M ; 13.735 ; ; Rise ; C25M ;
+; RD[6] ; C25M ; 14.150 ; ; Rise ; C25M ;
+; RD[7] ; C25M ; 14.923 ; ; Rise ; C25M ;
+; SD[*] ; C25M ; 7.005 ; ; Rise ; C25M ;
+; SD[0] ; C25M ; 7.501 ; ; Rise ; C25M ;
+; SD[1] ; C25M ; 7.005 ; ; Rise ; C25M ;
+; SD[2] ; C25M ; 7.091 ; ; Rise ; C25M ;
+; SD[3] ; C25M ; 7.091 ; ; Rise ; C25M ;
+; SD[4] ; C25M ; 7.501 ; ; Rise ; C25M ;
+; SD[5] ; C25M ; 7.091 ; ; Rise ; C25M ;
+; SD[6] ; C25M ; 7.091 ; ; Rise ; C25M ;
+; SD[7] ; C25M ; 7.091 ; ; Rise ; C25M ;
+; nFCS ; C25M ; 7.901 ; ; Rise ; C25M ;
+; RD[*] ; PHI0 ; 8.991 ; ; Rise ; PHI0 ;
+; RD[0] ; PHI0 ; 8.991 ; ; Rise ; PHI0 ;
+; RD[1] ; PHI0 ; 8.991 ; ; Rise ; PHI0 ;
+; RD[2] ; PHI0 ; 8.991 ; ; Rise ; PHI0 ;
+; RD[3] ; PHI0 ; 8.991 ; ; Rise ; PHI0 ;
+; RD[4] ; PHI0 ; 8.991 ; ; Rise ; PHI0 ;
+; RD[5] ; PHI0 ; 8.991 ; ; Rise ; PHI0 ;
+; RD[6] ; PHI0 ; 9.406 ; ; Rise ; PHI0 ;
+; RD[7] ; PHI0 ; 10.179 ; ; Rise ; PHI0 ;
+; RD[*] ; PHI0 ; 8.991 ; ; Fall ; PHI0 ;
+; RD[0] ; PHI0 ; 8.991 ; ; Fall ; PHI0 ;
+; RD[1] ; PHI0 ; 8.991 ; ; Fall ; PHI0 ;
+; RD[2] ; PHI0 ; 8.991 ; ; Fall ; PHI0 ;
+; RD[3] ; PHI0 ; 8.991 ; ; Fall ; PHI0 ;
+; RD[4] ; PHI0 ; 8.991 ; ; Fall ; PHI0 ;
+; RD[5] ; PHI0 ; 8.991 ; ; Fall ; PHI0 ;
+; RD[6] ; PHI0 ; 9.406 ; ; Fall ; PHI0 ;
+; RD[7] ; PHI0 ; 10.179 ; ; Fall ; PHI0 ;
+-----------+------------+--------+------+------------+-----------------+
@@ -1005,43 +1005,45 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
+-----------+------------+--------+------+------------+-----------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+--------+------+------------+-----------------+
-; MOSI ; C25M ; 6.445 ; ; Rise ; C25M ;
-; RD[*] ; C25M ; 8.326 ; ; Rise ; C25M ;
-; RD[0] ; C25M ; 8.326 ; ; Rise ; C25M ;
-; RD[1] ; C25M ; 8.326 ; ; Rise ; C25M ;
-; RD[2] ; C25M ; 8.326 ; ; Rise ; C25M ;
-; RD[3] ; C25M ; 10.351 ; ; Rise ; C25M ;
-; RD[4] ; C25M ; 10.351 ; ; Rise ; C25M ;
-; RD[5] ; C25M ; 10.351 ; ; Rise ; C25M ;
-; RD[6] ; C25M ; 10.351 ; ; Rise ; C25M ;
-; RD[7] ; C25M ; 10.895 ; ; Rise ; C25M ;
-; SD[*] ; C25M ; 6.922 ; ; Rise ; C25M ;
-; SD[0] ; C25M ; 6.922 ; ; Rise ; C25M ;
-; SD[1] ; C25M ; 6.922 ; ; Rise ; C25M ;
-; SD[2] ; C25M ; 7.035 ; ; Rise ; C25M ;
-; SD[3] ; C25M ; 7.035 ; ; Rise ; C25M ;
-; SD[4] ; C25M ; 6.922 ; ; Rise ; C25M ;
-; SD[5] ; C25M ; 7.035 ; ; Rise ; C25M ;
-; SD[6] ; C25M ; 7.035 ; ; Rise ; C25M ;
-; SD[7] ; C25M ; 7.035 ; ; Rise ; C25M ;
-; RD[*] ; PHI0 ; 8.733 ; ; Rise ; PHI0 ;
-; RD[0] ; PHI0 ; 8.733 ; ; Rise ; PHI0 ;
-; RD[1] ; PHI0 ; 8.733 ; ; Rise ; PHI0 ;
-; RD[2] ; PHI0 ; 8.733 ; ; Rise ; PHI0 ;
-; RD[3] ; PHI0 ; 10.758 ; ; Rise ; PHI0 ;
-; RD[4] ; PHI0 ; 10.758 ; ; Rise ; PHI0 ;
-; RD[5] ; PHI0 ; 10.758 ; ; Rise ; PHI0 ;
-; RD[6] ; PHI0 ; 10.758 ; ; Rise ; PHI0 ;
-; RD[7] ; PHI0 ; 11.302 ; ; Rise ; PHI0 ;
-; RD[*] ; PHI0 ; 8.733 ; ; Fall ; PHI0 ;
-; RD[0] ; PHI0 ; 8.733 ; ; Fall ; PHI0 ;
-; RD[1] ; PHI0 ; 8.733 ; ; Fall ; PHI0 ;
-; RD[2] ; PHI0 ; 8.733 ; ; Fall ; PHI0 ;
-; RD[3] ; PHI0 ; 10.758 ; ; Fall ; PHI0 ;
-; RD[4] ; PHI0 ; 10.758 ; ; Fall ; PHI0 ;
-; RD[5] ; PHI0 ; 10.758 ; ; Fall ; PHI0 ;
-; RD[6] ; PHI0 ; 10.758 ; ; Fall ; PHI0 ;
-; RD[7] ; PHI0 ; 11.302 ; ; Fall ; PHI0 ;
+; FCK ; C25M ; 7.883 ; ; Rise ; C25M ;
+; MOSI ; C25M ; 7.607 ; ; Rise ; C25M ;
+; RD[*] ; C25M ; 8.336 ; ; Rise ; C25M ;
+; RD[0] ; C25M ; 8.336 ; ; Rise ; C25M ;
+; RD[1] ; C25M ; 8.336 ; ; Rise ; C25M ;
+; RD[2] ; C25M ; 8.336 ; ; Rise ; C25M ;
+; RD[3] ; C25M ; 8.336 ; ; Rise ; C25M ;
+; RD[4] ; C25M ; 8.336 ; ; Rise ; C25M ;
+; RD[5] ; C25M ; 8.336 ; ; Rise ; C25M ;
+; RD[6] ; C25M ; 8.751 ; ; Rise ; C25M ;
+; RD[7] ; C25M ; 9.524 ; ; Rise ; C25M ;
+; SD[*] ; C25M ; 7.005 ; ; Rise ; C25M ;
+; SD[0] ; C25M ; 7.501 ; ; Rise ; C25M ;
+; SD[1] ; C25M ; 7.005 ; ; Rise ; C25M ;
+; SD[2] ; C25M ; 7.091 ; ; Rise ; C25M ;
+; SD[3] ; C25M ; 7.091 ; ; Rise ; C25M ;
+; SD[4] ; C25M ; 7.501 ; ; Rise ; C25M ;
+; SD[5] ; C25M ; 7.091 ; ; Rise ; C25M ;
+; SD[6] ; C25M ; 7.091 ; ; Rise ; C25M ;
+; SD[7] ; C25M ; 7.091 ; ; Rise ; C25M ;
+; nFCS ; C25M ; 7.901 ; ; Rise ; C25M ;
+; RD[*] ; PHI0 ; 8.991 ; ; Rise ; PHI0 ;
+; RD[0] ; PHI0 ; 8.991 ; ; Rise ; PHI0 ;
+; RD[1] ; PHI0 ; 8.991 ; ; Rise ; PHI0 ;
+; RD[2] ; PHI0 ; 8.991 ; ; Rise ; PHI0 ;
+; RD[3] ; PHI0 ; 8.991 ; ; Rise ; PHI0 ;
+; RD[4] ; PHI0 ; 8.991 ; ; Rise ; PHI0 ;
+; RD[5] ; PHI0 ; 8.991 ; ; Rise ; PHI0 ;
+; RD[6] ; PHI0 ; 9.406 ; ; Rise ; PHI0 ;
+; RD[7] ; PHI0 ; 10.179 ; ; Rise ; PHI0 ;
+; RD[*] ; PHI0 ; 8.991 ; ; Fall ; PHI0 ;
+; RD[0] ; PHI0 ; 8.991 ; ; Fall ; PHI0 ;
+; RD[1] ; PHI0 ; 8.991 ; ; Fall ; PHI0 ;
+; RD[2] ; PHI0 ; 8.991 ; ; Fall ; PHI0 ;
+; RD[3] ; PHI0 ; 8.991 ; ; Fall ; PHI0 ;
+; RD[4] ; PHI0 ; 8.991 ; ; Fall ; PHI0 ;
+; RD[5] ; PHI0 ; 8.991 ; ; Fall ; PHI0 ;
+; RD[6] ; PHI0 ; 9.406 ; ; Fall ; PHI0 ;
+; RD[7] ; PHI0 ; 10.179 ; ; Fall ; PHI0 ;
+-----------+------------+--------+------+------------+-----------------+
@@ -1050,43 +1052,45 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
+-----------+------------+-----------+-----------+------------+-----------------+
; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ;
+-----------+------------+-----------+-----------+------------+-----------------+
-; MOSI ; C25M ; 6.445 ; ; Rise ; C25M ;
-; RD[*] ; C25M ; 11.972 ; ; Rise ; C25M ;
-; RD[0] ; C25M ; 11.972 ; ; Rise ; C25M ;
-; RD[1] ; C25M ; 11.972 ; ; Rise ; C25M ;
-; RD[2] ; C25M ; 11.972 ; ; Rise ; C25M ;
-; RD[3] ; C25M ; 13.997 ; ; Rise ; C25M ;
-; RD[4] ; C25M ; 13.997 ; ; Rise ; C25M ;
-; RD[5] ; C25M ; 13.997 ; ; Rise ; C25M ;
-; RD[6] ; C25M ; 13.997 ; ; Rise ; C25M ;
-; RD[7] ; C25M ; 14.541 ; ; Rise ; C25M ;
-; SD[*] ; C25M ; 6.922 ; ; Rise ; C25M ;
-; SD[0] ; C25M ; 6.922 ; ; Rise ; C25M ;
-; SD[1] ; C25M ; 6.922 ; ; Rise ; C25M ;
-; SD[2] ; C25M ; 7.035 ; ; Rise ; C25M ;
-; SD[3] ; C25M ; 7.035 ; ; Rise ; C25M ;
-; SD[4] ; C25M ; 6.922 ; ; Rise ; C25M ;
-; SD[5] ; C25M ; 7.035 ; ; Rise ; C25M ;
-; SD[6] ; C25M ; 7.035 ; ; Rise ; C25M ;
-; SD[7] ; C25M ; 7.035 ; ; Rise ; C25M ;
-; RD[*] ; PHI0 ; 8.733 ; ; Rise ; PHI0 ;
-; RD[0] ; PHI0 ; 8.733 ; ; Rise ; PHI0 ;
-; RD[1] ; PHI0 ; 8.733 ; ; Rise ; PHI0 ;
-; RD[2] ; PHI0 ; 8.733 ; ; Rise ; PHI0 ;
-; RD[3] ; PHI0 ; 10.758 ; ; Rise ; PHI0 ;
-; RD[4] ; PHI0 ; 10.758 ; ; Rise ; PHI0 ;
-; RD[5] ; PHI0 ; 10.758 ; ; Rise ; PHI0 ;
-; RD[6] ; PHI0 ; 10.758 ; ; Rise ; PHI0 ;
-; RD[7] ; PHI0 ; 11.302 ; ; Rise ; PHI0 ;
-; RD[*] ; PHI0 ; 8.733 ; ; Fall ; PHI0 ;
-; RD[0] ; PHI0 ; 8.733 ; ; Fall ; PHI0 ;
-; RD[1] ; PHI0 ; 8.733 ; ; Fall ; PHI0 ;
-; RD[2] ; PHI0 ; 8.733 ; ; Fall ; PHI0 ;
-; RD[3] ; PHI0 ; 10.758 ; ; Fall ; PHI0 ;
-; RD[4] ; PHI0 ; 10.758 ; ; Fall ; PHI0 ;
-; RD[5] ; PHI0 ; 10.758 ; ; Fall ; PHI0 ;
-; RD[6] ; PHI0 ; 10.758 ; ; Fall ; PHI0 ;
-; RD[7] ; PHI0 ; 11.302 ; ; Fall ; PHI0 ;
+; FCK ; C25M ; 7.883 ; ; Rise ; C25M ;
+; MOSI ; C25M ; 7.607 ; ; Rise ; C25M ;
+; RD[*] ; C25M ; 13.735 ; ; Rise ; C25M ;
+; RD[0] ; C25M ; 13.735 ; ; Rise ; C25M ;
+; RD[1] ; C25M ; 13.735 ; ; Rise ; C25M ;
+; RD[2] ; C25M ; 13.735 ; ; Rise ; C25M ;
+; RD[3] ; C25M ; 13.735 ; ; Rise ; C25M ;
+; RD[4] ; C25M ; 13.735 ; ; Rise ; C25M ;
+; RD[5] ; C25M ; 13.735 ; ; Rise ; C25M ;
+; RD[6] ; C25M ; 14.150 ; ; Rise ; C25M ;
+; RD[7] ; C25M ; 14.923 ; ; Rise ; C25M ;
+; SD[*] ; C25M ; 7.005 ; ; Rise ; C25M ;
+; SD[0] ; C25M ; 7.501 ; ; Rise ; C25M ;
+; SD[1] ; C25M ; 7.005 ; ; Rise ; C25M ;
+; SD[2] ; C25M ; 7.091 ; ; Rise ; C25M ;
+; SD[3] ; C25M ; 7.091 ; ; Rise ; C25M ;
+; SD[4] ; C25M ; 7.501 ; ; Rise ; C25M ;
+; SD[5] ; C25M ; 7.091 ; ; Rise ; C25M ;
+; SD[6] ; C25M ; 7.091 ; ; Rise ; C25M ;
+; SD[7] ; C25M ; 7.091 ; ; Rise ; C25M ;
+; nFCS ; C25M ; 7.901 ; ; Rise ; C25M ;
+; RD[*] ; PHI0 ; 8.991 ; ; Rise ; PHI0 ;
+; RD[0] ; PHI0 ; 8.991 ; ; Rise ; PHI0 ;
+; RD[1] ; PHI0 ; 8.991 ; ; Rise ; PHI0 ;
+; RD[2] ; PHI0 ; 8.991 ; ; Rise ; PHI0 ;
+; RD[3] ; PHI0 ; 8.991 ; ; Rise ; PHI0 ;
+; RD[4] ; PHI0 ; 8.991 ; ; Rise ; PHI0 ;
+; RD[5] ; PHI0 ; 8.991 ; ; Rise ; PHI0 ;
+; RD[6] ; PHI0 ; 9.406 ; ; Rise ; PHI0 ;
+; RD[7] ; PHI0 ; 10.179 ; ; Rise ; PHI0 ;
+; RD[*] ; PHI0 ; 8.991 ; ; Fall ; PHI0 ;
+; RD[0] ; PHI0 ; 8.991 ; ; Fall ; PHI0 ;
+; RD[1] ; PHI0 ; 8.991 ; ; Fall ; PHI0 ;
+; RD[2] ; PHI0 ; 8.991 ; ; Fall ; PHI0 ;
+; RD[3] ; PHI0 ; 8.991 ; ; Fall ; PHI0 ;
+; RD[4] ; PHI0 ; 8.991 ; ; Fall ; PHI0 ;
+; RD[5] ; PHI0 ; 8.991 ; ; Fall ; PHI0 ;
+; RD[6] ; PHI0 ; 9.406 ; ; Fall ; PHI0 ;
+; RD[7] ; PHI0 ; 10.179 ; ; Fall ; PHI0 ;
+-----------+------------+-----------+-----------+------------+-----------------+
@@ -1095,43 +1099,45 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
+-----------+------------+-----------+-----------+------------+-----------------+
; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ;
+-----------+------------+-----------+-----------+------------+-----------------+
-; MOSI ; C25M ; 6.445 ; ; Rise ; C25M ;
-; RD[*] ; C25M ; 8.326 ; ; Rise ; C25M ;
-; RD[0] ; C25M ; 8.326 ; ; Rise ; C25M ;
-; RD[1] ; C25M ; 8.326 ; ; Rise ; C25M ;
-; RD[2] ; C25M ; 8.326 ; ; Rise ; C25M ;
-; RD[3] ; C25M ; 10.351 ; ; Rise ; C25M ;
-; RD[4] ; C25M ; 10.351 ; ; Rise ; C25M ;
-; RD[5] ; C25M ; 10.351 ; ; Rise ; C25M ;
-; RD[6] ; C25M ; 10.351 ; ; Rise ; C25M ;
-; RD[7] ; C25M ; 10.895 ; ; Rise ; C25M ;
-; SD[*] ; C25M ; 6.922 ; ; Rise ; C25M ;
-; SD[0] ; C25M ; 6.922 ; ; Rise ; C25M ;
-; SD[1] ; C25M ; 6.922 ; ; Rise ; C25M ;
-; SD[2] ; C25M ; 7.035 ; ; Rise ; C25M ;
-; SD[3] ; C25M ; 7.035 ; ; Rise ; C25M ;
-; SD[4] ; C25M ; 6.922 ; ; Rise ; C25M ;
-; SD[5] ; C25M ; 7.035 ; ; Rise ; C25M ;
-; SD[6] ; C25M ; 7.035 ; ; Rise ; C25M ;
-; SD[7] ; C25M ; 7.035 ; ; Rise ; C25M ;
-; RD[*] ; PHI0 ; 8.733 ; ; Rise ; PHI0 ;
-; RD[0] ; PHI0 ; 8.733 ; ; Rise ; PHI0 ;
-; RD[1] ; PHI0 ; 8.733 ; ; Rise ; PHI0 ;
-; RD[2] ; PHI0 ; 8.733 ; ; Rise ; PHI0 ;
-; RD[3] ; PHI0 ; 10.758 ; ; Rise ; PHI0 ;
-; RD[4] ; PHI0 ; 10.758 ; ; Rise ; PHI0 ;
-; RD[5] ; PHI0 ; 10.758 ; ; Rise ; PHI0 ;
-; RD[6] ; PHI0 ; 10.758 ; ; Rise ; PHI0 ;
-; RD[7] ; PHI0 ; 11.302 ; ; Rise ; PHI0 ;
-; RD[*] ; PHI0 ; 8.733 ; ; Fall ; PHI0 ;
-; RD[0] ; PHI0 ; 8.733 ; ; Fall ; PHI0 ;
-; RD[1] ; PHI0 ; 8.733 ; ; Fall ; PHI0 ;
-; RD[2] ; PHI0 ; 8.733 ; ; Fall ; PHI0 ;
-; RD[3] ; PHI0 ; 10.758 ; ; Fall ; PHI0 ;
-; RD[4] ; PHI0 ; 10.758 ; ; Fall ; PHI0 ;
-; RD[5] ; PHI0 ; 10.758 ; ; Fall ; PHI0 ;
-; RD[6] ; PHI0 ; 10.758 ; ; Fall ; PHI0 ;
-; RD[7] ; PHI0 ; 11.302 ; ; Fall ; PHI0 ;
+; FCK ; C25M ; 7.883 ; ; Rise ; C25M ;
+; MOSI ; C25M ; 7.607 ; ; Rise ; C25M ;
+; RD[*] ; C25M ; 8.336 ; ; Rise ; C25M ;
+; RD[0] ; C25M ; 8.336 ; ; Rise ; C25M ;
+; RD[1] ; C25M ; 8.336 ; ; Rise ; C25M ;
+; RD[2] ; C25M ; 8.336 ; ; Rise ; C25M ;
+; RD[3] ; C25M ; 8.336 ; ; Rise ; C25M ;
+; RD[4] ; C25M ; 8.336 ; ; Rise ; C25M ;
+; RD[5] ; C25M ; 8.336 ; ; Rise ; C25M ;
+; RD[6] ; C25M ; 8.751 ; ; Rise ; C25M ;
+; RD[7] ; C25M ; 9.524 ; ; Rise ; C25M ;
+; SD[*] ; C25M ; 7.005 ; ; Rise ; C25M ;
+; SD[0] ; C25M ; 7.501 ; ; Rise ; C25M ;
+; SD[1] ; C25M ; 7.005 ; ; Rise ; C25M ;
+; SD[2] ; C25M ; 7.091 ; ; Rise ; C25M ;
+; SD[3] ; C25M ; 7.091 ; ; Rise ; C25M ;
+; SD[4] ; C25M ; 7.501 ; ; Rise ; C25M ;
+; SD[5] ; C25M ; 7.091 ; ; Rise ; C25M ;
+; SD[6] ; C25M ; 7.091 ; ; Rise ; C25M ;
+; SD[7] ; C25M ; 7.091 ; ; Rise ; C25M ;
+; nFCS ; C25M ; 7.901 ; ; Rise ; C25M ;
+; RD[*] ; PHI0 ; 8.991 ; ; Rise ; PHI0 ;
+; RD[0] ; PHI0 ; 8.991 ; ; Rise ; PHI0 ;
+; RD[1] ; PHI0 ; 8.991 ; ; Rise ; PHI0 ;
+; RD[2] ; PHI0 ; 8.991 ; ; Rise ; PHI0 ;
+; RD[3] ; PHI0 ; 8.991 ; ; Rise ; PHI0 ;
+; RD[4] ; PHI0 ; 8.991 ; ; Rise ; PHI0 ;
+; RD[5] ; PHI0 ; 8.991 ; ; Rise ; PHI0 ;
+; RD[6] ; PHI0 ; 9.406 ; ; Rise ; PHI0 ;
+; RD[7] ; PHI0 ; 10.179 ; ; Rise ; PHI0 ;
+; RD[*] ; PHI0 ; 8.991 ; ; Fall ; PHI0 ;
+; RD[0] ; PHI0 ; 8.991 ; ; Fall ; PHI0 ;
+; RD[1] ; PHI0 ; 8.991 ; ; Fall ; PHI0 ;
+; RD[2] ; PHI0 ; 8.991 ; ; Fall ; PHI0 ;
+; RD[3] ; PHI0 ; 8.991 ; ; Fall ; PHI0 ;
+; RD[4] ; PHI0 ; 8.991 ; ; Fall ; PHI0 ;
+; RD[5] ; PHI0 ; 8.991 ; ; Fall ; PHI0 ;
+; RD[6] ; PHI0 ; 9.406 ; ; Fall ; PHI0 ;
+; RD[7] ; PHI0 ; 10.179 ; ; Fall ; PHI0 ;
+-----------+------------+-----------+-----------+------------+-----------------+
@@ -1140,8 +1146,8 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
+------------+----------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+----------+----------+----------+----------+----------+
-; C25M ; C25M ; 1403 ; 0 ; 0 ; 0 ;
-; PHI0 ; C25M ; 93 ; 1 ; 0 ; 0 ;
+; C25M ; C25M ; 1478 ; 0 ; 0 ; 0 ;
+; PHI0 ; C25M ; 91 ; 1 ; 0 ; 0 ;
; C25M ; PHI0 ; 6 ; 0 ; 0 ; 0 ;
+------------+----------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
@@ -1152,8 +1158,8 @@ Entries labeled "false path" only account for clock-to-clock false paths and not
+------------+----------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+----------+----------+----------+----------+----------+
-; C25M ; C25M ; 1403 ; 0 ; 0 ; 0 ;
-; PHI0 ; C25M ; 93 ; 1 ; 0 ; 0 ;
+; C25M ; C25M ; 1478 ; 0 ; 0 ; 0 ;
+; PHI0 ; C25M ; 91 ; 1 ; 0 ; 0 ;
; C25M ; PHI0 ; 6 ; 0 ; 0 ; 0 ;
+------------+----------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
@@ -1198,10 +1204,10 @@ No dedicated SERDES Receiver circuitry present in device or used in design
+---------------------------------+-------+------+
; Illegal Clocks ; 0 ; 0 ;
; Unconstrained Clocks ; 0 ; 0 ;
-; Unconstrained Input Ports ; 42 ; 42 ;
-; Unconstrained Input Port Paths ; 649 ; 649 ;
-; Unconstrained Output Ports ; 43 ; 43 ;
-; Unconstrained Output Port Paths ; 114 ; 114 ;
+; Unconstrained Input Ports ; 44 ; 44 ;
+; Unconstrained Input Port Paths ; 651 ; 651 ;
+; Unconstrained Output Ports ; 45 ; 45 ;
+; Unconstrained Output Port Paths ; 118 ; 118 ;
+---------------------------------+-------+------+
@@ -1209,12 +1215,12 @@ No dedicated SERDES Receiver circuitry present in device or used in design
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
-Info: Running Quartus II 32-bit TimeQuest Timing Analyzer
+Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
- Info: Processing started: Sun Apr 11 13:22:43 2021
+ Info: Processing started: Sun Apr 18 03:45:26 2021
Info: Command: quartus_sta GR8RAM -c GR8RAM
Info: qsta_default_script.tcl version: #1
-Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
+Warning (20028): Parallel compilation is not licensed and has been disabled
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (306004): Started post-fitting delay annotation
@@ -1226,24 +1232,24 @@ Info (332105): Deriving Clocks
Info (332105): create_clock -period 1.000 -name PHI0 PHI0
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Critical Warning (332148): Timing requirements not met
-Info (332146): Worst-case setup slack is -9.908
+Info (332146): Worst-case setup slack is -9.691
Info (332119): Slack End Point TNS Clock
Info (332119): ========= ============= =====================
- Info (332119): -9.908 -697.920 C25M
- Info (332119): -1.302 -1.302 PHI0
-Info (332146): Worst-case hold slack is 1.012
+ Info (332119): -9.691 -732.295 C25M
+ Info (332119): -1.358 -1.358 PHI0
+Info (332146): Worst-case hold slack is 1.092
Info (332119): Slack End Point TNS Clock
Info (332119): ========= ============= =====================
- Info (332119): 1.012 0.000 PHI0
- Info (332119): 1.288 0.000 C25M
-Info (332146): Worst-case recovery slack is -4.389
+ Info (332119): 1.092 0.000 PHI0
+ Info (332119): 1.418 0.000 C25M
+Info (332146): Worst-case recovery slack is -5.009
Info (332119): Slack End Point TNS Clock
Info (332119): ========= ============= =====================
- Info (332119): -4.389 -131.670 C25M
-Info (332146): Worst-case removal slack is 4.835
+ Info (332119): -5.009 -150.270 C25M
+Info (332146): Worst-case removal slack is 5.455
Info (332119): Slack End Point TNS Clock
Info (332119): ========= ============= =====================
- Info (332119): 4.835 0.000 C25M
+ Info (332119): 5.455 0.000 C25M
Info (332146): Worst-case minimum pulse width slack is -2.289
Info (332119): Slack End Point TNS Clock
Info (332119): ========= ============= =====================
@@ -1252,10 +1258,10 @@ Info (332146): Worst-case minimum pulse width slack is -2.289
Info (332001): The selected device family is not supported by the report_metastability command.
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
-Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings
- Info: Peak virtual memory: 278 megabytes
- Info: Processing ended: Sun Apr 11 13:22:48 2021
- Info: Elapsed time: 00:00:05
- Info: Total CPU time (on all processors): 00:00:05
+Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 3 warnings
+ Info: Peak virtual memory: 368 megabytes
+ Info: Processing ended: Sun Apr 18 03:45:27 2021
+ Info: Elapsed time: 00:00:01
+ Info: Total CPU time (on all processors): 00:00:01
diff --git a/cpld/output_files/GR8RAM.sta.summary b/cpld/output_files/GR8RAM.sta.summary
index 148752c..ed76518 100755
--- a/cpld/output_files/GR8RAM.sta.summary
+++ b/cpld/output_files/GR8RAM.sta.summary
@@ -3,27 +3,27 @@ TimeQuest Timing Analyzer Summary
------------------------------------------------------------
Type : Setup 'C25M'
-Slack : -9.908
-TNS : -697.920
+Slack : -9.691
+TNS : -732.295
Type : Setup 'PHI0'
-Slack : -1.302
-TNS : -1.302
+Slack : -1.358
+TNS : -1.358
Type : Hold 'PHI0'
-Slack : 1.012
+Slack : 1.092
TNS : 0.000
Type : Hold 'C25M'
-Slack : 1.288
+Slack : 1.418
TNS : 0.000
Type : Recovery 'C25M'
-Slack : -4.389
-TNS : -131.670
+Slack : -5.009
+TNS : -150.270
Type : Removal 'C25M'
-Slack : 4.835
+Slack : 5.455
TNS : 0.000
Type : Minimum Pulse Width 'C25M'