diff --git a/cpld/GR8RAM.qsf b/cpld/GR8RAM.qsf index fa2370d..0aa8488 100755 --- a/cpld/GR8RAM.qsf +++ b/cpld/GR8RAM.qsf @@ -69,7 +69,7 @@ set_global_assignment -name MUX_RESTRUCTURE ON set_global_assignment -name STATE_MACHINE_PROCESSING "MINIMAL BITS" set_global_assignment -name SYNTHESIS_SEED 123 set_global_assignment -name SEED 235 -set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII "MINIMIZE AREA" +set_global_assignment -name AUTO_PACKED_REGISTERS_MAX "MINIMIZE AREA" set_global_assignment -name ROUTER_REGISTER_DUPLICATION OFF set_global_assignment -name VERILOG_FILE GR8RAM.v set_location_assignment PIN_1 -to RA[4] diff --git a/cpld/GR8RAM.v b/cpld/GR8RAM.v index 41dd3b5..7618888 100644 --- a/cpld/GR8RAM.v +++ b/cpld/GR8RAM.v @@ -10,27 +10,16 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, reg PHI0r1, PHI0r2; always @(posedge C25M) begin PHI0r1 <= PHI0; PHI0r2 <= PHI0r1; end - /* Reset filter */ + /* Reset input */ input nRES; - reg [3:0] nRESf = 0; reg nRESr = 0; - always @(posedge C25M) begin - nRESf[3:0] <= { nRESf[2:0], nRES }; - nRESr <= nRESf[3] || nRESf[2] || nRESf[1] || nRESf[0]; - end + always @(posedge C25M) if (PS==15) nRESr <= nRES; /* Firmware select */ input [1:0] SetFW; - reg [1:0] SetFWr; - reg SetFWLoaded = 0; - always @(posedge C25M) begin - if (~SetFWLoaded) begin - SetFWLoaded <= 1; - SetFWr[1:0] <= SetFW[1:0]; - end - end - wire [1:0] SetROM = ~SetFWr[1:0]; - wire SetEN16MB = SetROM[1:0]==2'b11; + wire [1:0] SetROM = ~SetFW[1:0]; + wire SetENRestore = SetROM[1:0]==1'b11; + wire SetEN16MB = 0; wire SetEN24bit = SetROM[1]; /* State counter from PHI0 rising edge */ @@ -65,52 +54,52 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, /* Apple address bus */ input [15:0] RA; input nWE; - reg [11:0] RAr; reg nWEr; - reg CXXXr; - always @(posedge PHI0) begin - CXXXr <= RA[15:12]==4'hC; - RAr[11:0] <= RA[11:0]; - nWEr <= nWE; - end + wire CXXX = RA[15:12]==4'hC; /* Apple select signals */ - wire ROMSpecRD = CXXXr && RAr[11:8]!=4'h0 && nWEr && ((RAr[11] && IOROMEN) || (~RAr[11])); - wire REGSpecSEL = CXXXr && RAr[11:8]==4'h0 && RAr[7] && REGEN; - wire BankSpecSEL = REGSpecSEL && RAr[3:0]==4'hF; - wire RAMRegSpecSEL = REGSpecSEL && RAr[3:0]==4'h3; - wire RAMSpecSEL = RAMRegSpecSEL && (~SetEN24bit || SetEN16MB || ~Addr[23]); - wire AddrHSpecSEL = REGSpecSEL && RAr[3:0]==4'h2; - wire AddrMSpecSEL = REGSpecSEL && RAr[3:0]==4'h1; - wire AddrLSpecSEL = REGSpecSEL && RAr[3:0]==4'h0; - wire BankSEL = REGEN && ~nDEVSEL && BankSpecSEL; + wire ROMSpecRD = CXXX && RA[11:8]!=4'h0 && nWE && ((RA[11] && IOROMEN) || (~RA[11])); + wire REGSpecSEL = CXXX && RA[11:8]==4'h0 && RA[7] && REGEN; + wire REGSpecSELAny = RA[11:8]==4'h0; + wire BankSpecSEL = REGSpecSEL && RA[3:0]==4'hF; + wire BankSpecSELAny = REGSpecSELAny && RA[3:0]==4'hF; + wire SPITX1SpecSEL = REGSpecSEL && RA[3:0]==4'hD; + wire SPITX0SpecSEL = REGSpecSEL && RA[3:0]==4'hC; + wire RAMRegSpecSEL = REGSpecSEL && RA[3:0]==4'h3; + wire RAMSpecSEL = RAMRegSpecSEL && (~SetEN24bit || SetEN16MB || ~Addr[23]); + wire RAMSpecSELAny = REGSpecSELAny && (~SetEN24bit || SetEN16MB || ~Addr[23]); + wire AddrHSpecSEL = REGSpecSEL && RA[3:0]==4'h2; + wire AddrHSpecSELAny = REGSpecSELAny && RA[3:0]==4'h2; + wire AddrMSpecSEL = REGSpecSEL && RA[3:0]==4'h1; + wire AddrMSpecSELAny = REGSpecSELAny && RA[3:0]==4'h1; + wire AddrLSpecSEL = REGSpecSEL && RA[3:0]==4'h0; + wire AddrLSpecSELAny = REGSpecSELAny && RA[3:0]==4'h0; + wire BankWR = REGEN && ~nDEVSEL && BankSpecSEL && !nWE; wire RAMRegSEL = ~nDEVSEL && RAMRegSpecSEL; wire RAMSEL = ~nDEVSEL && RAMSpecSEL; - wire RAMWR = RAMSEL && ~nWEr; + wire RAMWR = RAMSEL && ~nWE; wire AddrHSEL = REGEN && ~nDEVSEL && AddrHSpecSEL; wire AddrMSEL = REGEN && ~nDEVSEL && AddrMSpecSEL; wire AddrLSEL = REGEN && ~nDEVSEL && AddrLSpecSEL; - /* IOROMEN and REGEN control */ - reg IOROMEN = 0; + /* REGEN and IOROMEN control */ reg REGEN = 0; - reg nIOSTRBr; - wire IOROMRES = RAr[10:0]==11'h7FF && ~nIOSTRB && ~nIOSTRBr; - always @(posedge C25M, negedge nRESr) begin - if (~nRESr) REGEN <= 0; - else if (PS==8 && ~nIOSEL) REGEN <= 1; - end always @(posedge C25M) begin - nIOSTRBr <= nIOSTRB; - if (~nRESr) IOROMEN <= 0; - else if (PS==8 && IOROMRES) IOROMEN <= 0; - else if (PS==8 && ~nIOSEL) IOROMEN <= 1; + if (!nRESr) REGEN <= 0; + else if (PS==8 && !nIOSEL) REGEN <= 1; + end + reg IOROMEN = 0; + wire IOROMRES = RA[10:0]==11'h7FF && !nIOSTRB; + always @(posedge C25M, posedge IOROMRES) begin + if (IOROMRES) IOROMEN <= 0; + else if (!nRESr) IOROMEN <= 0; + else if (PS==8 && !nIOSEL) IOROMEN <= 1; end /* Apple data bus */ inout [7:0] RD = RDdir ? 8'bZ : RDD[7:0]; reg [7:0] RDD; - output RDdir = ~(PHI0r2 && nWE && PHI0 && - (~nDEVSEL || ~nIOSEL || (~nIOSTRB && IOROMEN && RA[10:0]!=11'h7FF))); + output RDdir = !(PHI0r2 && nWE && PHI0 && + (!nDEVSEL || !nIOSEL || (!nIOSTRB && IOROMEN))); /* Slinky address registers */ reg [23:0] Addr = 0; @@ -127,7 +116,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, if (PS==8 && RAMRegSEL) AddrIncL <= 1; else AddrIncL <= 0; - if (PS==8 && AddrLSEL && ~nWEr) begin + if (PS==8 && AddrLSEL && ~nWE) begin Addr[7:0] <= RD[7:0]; AddrIncM <= Addr[7] && ~RD[7]; end else if (AddrIncL) begin @@ -135,7 +124,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, AddrIncM <= Addr[7:0]==8'hFF; end else AddrIncM <= 0; - if (PS==8 && AddrMSEL && ~nWEr) begin + if (PS==8 && AddrMSEL && ~nWE) begin Addr[15:8] <= RD[7:0]; AddrIncH <= Addr[15] && ~RD[7]; end else if (AddrIncM) begin @@ -143,7 +132,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, AddrIncH <= Addr[15:8]==8'hFF; end else AddrIncH <= 0; - if (PS==8 && AddrHSEL && ~nWEr) begin + if (PS==8 && AddrHSEL && ~nWE) begin Addr[23:16] <= RD[7:0]; end else if (AddrIncH) begin Addr[23:16] <= Addr[23:16]+1; @@ -153,18 +142,21 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, /* ROM bank register */ reg Bank = 0; - always @(posedge C25M, negedge nRESr) begin - if (~nRESr) Bank <= 0; - else if (PS==8 && BankSEL && ~nWEr) begin - Bank <= RD[0]; + reg RestoreDone = 0; + always @(posedge C25M) begin + if (!SetENRestore) RestoreDone <= 1; + else if (PS==8 && BankWR) begin + RestoreDone <= RestoreDone || RD[1:0]==2'b11; end end - + always @(posedge C25M, negedge nRESr) begin + if (!nRESr) Bank <= 0; + else if (PS==8 && BankWR) Bank <= RD[0]; + end + /* SPI flash control signals */ - output nFCS = FCKOE ? ~FCS : 1'bZ; - reg FCS = 0; - output FCK = FCKOE ? FCKout : 1'bZ; - reg FCKOE = 0; + output reg nFCS = 1; + output FCK = FCKout; reg FCKout = 0; inout MOSI = MOSIOE ? MOSIout : 1'bZ; reg MOSIOE = 0; @@ -186,7 +178,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, end 6: begin // NOP CKE FCKout <= 1'b1; end 7: begin // NOP CKE - FCKout <= ~(IS==5 || IS==6); + FCKout <= ~(IS==5 || IS==6 || (!nDEVSEL && !RestoreDone && (SPITX0SpecSEL || SPITX1SpecSEL))); end 8: begin // WR AP FCKout <= 1'b1; end 9: begin // NOP CKE @@ -205,9 +197,9 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, FCKout <= ~(IS==5); end endcase - FCS <= IS==4 || IS==5 || IS==6; - MOSIOE <= IS==5; - FCKOE <= IS==1 || IS==4 || IS==5 || IS==6 || IS==7; + + nFCS <= !(IS==4 || IS==5 || IS==6 || Bank); + MOSIOE <= IS==5 || IS==7; end /* SPI flash MOSI control */ @@ -218,7 +210,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, case (LS[2:0]) 3'h3: MOSIout <= 1'b0; // Command bit 7 3'h4: MOSIout <= 1'b0; // Address bit 23 - 3'h5: MOSIout <= 1'b0; // Address bit 15 + 3'h5: MOSIout <= 1'b1; // Address bit 15 3'h6: MOSIout <= 1'b0; // Address bit 7 default MOSIout <= 1'b0; endcase @@ -239,13 +231,13 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, default MOSIout <= 1'b0; endcase end 7: begin - case (LS[2:0]) - 3'h3: MOSIout <= 1'b1; // Command bit 4 - 3'h4: MOSIout <= 1'b0; // Address bit 20 - 3'h5: MOSIout <= 1'b0; // Address bit 12 - 3'h6: MOSIout <= 1'b0; // Address bit 4 - default MOSIout <= 1'b0; - endcase + if (nRESout) case (LS[2:0]) + 3'h3: MOSIout <= 1'b1; // Command bit 4 + 3'h4: MOSIout <= 1'b0; // Address bit 20 + 3'h5: MOSIout <= 1'b0; // Address bit 12 + 3'h6: MOSIout <= 1'b0; // Address bit 4 + default MOSIout <= 1'b0; + endcase else MOSIout <= RA[0]; end 9: begin case (LS[2:0]) 3'h3: MOSIout <= 1'b1; // Command bit 3 @@ -324,12 +316,13 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, endcase end - /* Apple data bus from SDRAM */ + /* Apple II data bus output */ always @(negedge C25M) begin if (PS==5) begin - if (AddrLSpecSEL) RDD[7:0] <= Addr[7:0]; - else if (AddrMSpecSEL) RDD[7:0] <= Addr[15:8]; - else if (AddrHSpecSEL) RDD[7:0] <= { SetEN24bit ? Addr[23:20] : 4'hF, Addr[19:16] }; + if (AddrLSpecSELAny) RDD[7:0] <= Addr[7:0]; + else if (AddrMSpecSELAny) RDD[7:0] <= Addr[15:8]; + else if (AddrHSpecSELAny) RDD[7:0] <= { SetEN24bit ? Addr[23:20] : 4'hF, Addr[19:16] }; + else if (BankSpecSELAny) RDD[7:0] <= { MISO, SD[6:0] }; else RDD[7:0] <= SD[7:0]; end end @@ -358,14 +351,14 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, nSWE <= 1; SDOE <= 0; end 2: begin // RD CKE / NOP CKD (RD) - RCKE <= IS==7 && nWEr && (ROMSpecRD || RAMSpecSEL); - nRCS <= ~(IS==7 && nWEr && (ROMSpecRD || RAMSpecSEL)); + RCKE <= IS==7 && nWE && (ROMSpecRD || RAMSpecSEL); + nRCS <= ~(IS==7 && nWE && (ROMSpecRD || RAMSpecSEL)); nRAS <= 1; nCAS <= 0; nSWE <= 1; SDOE <= 0; end 3: begin // NOP CKE / CKD - RCKE <= IS==7 && nWEr && (ROMSpecRD || RAMSpecSEL); + RCKE <= IS==7 && nWE && (ROMSpecRD || RAMSpecSEL); nRCS <= 1; nRAS <= 1; nCAS <= 1; @@ -454,27 +447,27 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, DQML <= 1'b1; DQMH <= 1'b1; if (IS==6) begin - SBA[1:0] <= { 2'b10 }; + SBA[1:0] <= 2'b10; SA[12:0] <= { 10'b0011000100, LS[12:10] }; end else if (RAMSpecSEL) begin - SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 }; - SA[12:10] <= SetEN24bit ? Addr[22:20] : 3'b000; + SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[22] : 1'b0 }; + SA[12:10] <= SetEN24bit ? { Addr[23], Addr[21:20] } : 3'b000; SA[9:0] <= Addr[19:10]; end else begin SBA[1:0] <= 2'b10; - SA[12:0] <= { 10'b0011000100, Bank, RAr[11:10] }; + SA[12:0] <= { 10'b0011000100, RestoreDone ? (nIOSEL ? 1'b0 : Bank) : 1'b1, RA[11:10] }; end end 2: begin // RD if (RAMSpecSEL) begin - SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 }; + SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[22] : 1'b0 }; SA[12:0] <= { 4'b0011, Addr[9:1] }; DQML <= Addr[0]; DQMH <= ~Addr[0]; end else begin SBA[1:0] <= 2'b10; - SA[12:0] <= { 4'b0011, RAr[9:1]}; - DQML <= RAr[0]; - DQMH <= ~RAr[0]; + SA[12:0] <= { 4'b0011, RA[9:1]}; + DQML <= RA[0]; + DQMH <= ~RA[0]; end end 3: begin // NOP CKE DQML <= 1'b1; @@ -508,7 +501,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, DQML <= LS[0]; DQMH <= ~LS[0]; end else begin - SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 }; + SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[22] : 1'b0 }; SA[12:0] <= { 4'b0011, Addr[9:1] }; DQML <= Addr[0]; DQMH <= ~Addr[0]; diff --git a/cpld/db/GR8RAM.(0).cnf.cdb b/cpld/db/GR8RAM.(0).cnf.cdb index 6451a87..fa4105b 100644 Binary files a/cpld/db/GR8RAM.(0).cnf.cdb and b/cpld/db/GR8RAM.(0).cnf.cdb differ diff --git a/cpld/db/GR8RAM.(0).cnf.hdb b/cpld/db/GR8RAM.(0).cnf.hdb index f7d56bd..ed60408 100644 Binary files a/cpld/db/GR8RAM.(0).cnf.hdb and b/cpld/db/GR8RAM.(0).cnf.hdb differ diff --git a/cpld/db/GR8RAM.asm.qmsg b/cpld/db/GR8RAM.asm.qmsg index 7337d4d..1faf556 100644 --- a/cpld/db/GR8RAM.asm.qmsg +++ b/cpld/db/GR8RAM.asm.qmsg @@ -1,7 +1,7 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1679994396726 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1679994396726 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 28 05:06:36 2023 " "Processing started: Tue Mar 28 05:06:36 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1679994396726 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1679994396726 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1679994396726 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1679994396991 ""} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1679994397038 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1679994397038 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13057 " "Peak virtual memory: 13057 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679994397272 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 28 05:06:37 2023 " "Processing ended: Tue Mar 28 05:06:37 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679994397272 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679994397272 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679994397272 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1679994397272 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1680020965853 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1680020965867 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 28 12:29:25 2023 " "Processing started: Tue Mar 28 12:29:25 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1680020965867 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1680020965867 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1680020965867 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1680020966133 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1680020966164 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1680020966180 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13059 " "Peak virtual memory: 13059 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1680020966398 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 28 12:29:26 2023 " "Processing ended: Tue Mar 28 12:29:26 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1680020966398 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1680020966398 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1680020966398 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1680020966398 ""} diff --git a/cpld/db/GR8RAM.asm.rdb b/cpld/db/GR8RAM.asm.rdb index 6ee78a0..3693fae 100644 Binary files a/cpld/db/GR8RAM.asm.rdb and b/cpld/db/GR8RAM.asm.rdb differ diff --git a/cpld/db/GR8RAM.asm_labs.ddb b/cpld/db/GR8RAM.asm_labs.ddb index f73294e..b4a65d3 100644 Binary files a/cpld/db/GR8RAM.asm_labs.ddb and b/cpld/db/GR8RAM.asm_labs.ddb differ diff --git a/cpld/db/GR8RAM.cmp.cdb b/cpld/db/GR8RAM.cmp.cdb index b931878..a1f69bd 100644 Binary files a/cpld/db/GR8RAM.cmp.cdb and b/cpld/db/GR8RAM.cmp.cdb differ diff --git a/cpld/db/GR8RAM.cmp.hdb b/cpld/db/GR8RAM.cmp.hdb index 65e8f23..530ea43 100644 Binary files a/cpld/db/GR8RAM.cmp.hdb and b/cpld/db/GR8RAM.cmp.hdb differ diff --git a/cpld/db/GR8RAM.cmp.idb b/cpld/db/GR8RAM.cmp.idb index f8b13a1..f7dfdd7 100644 Binary files a/cpld/db/GR8RAM.cmp.idb and b/cpld/db/GR8RAM.cmp.idb differ diff --git a/cpld/db/GR8RAM.cmp.rdb b/cpld/db/GR8RAM.cmp.rdb index 10d7877..711114e 100644 Binary files a/cpld/db/GR8RAM.cmp.rdb and b/cpld/db/GR8RAM.cmp.rdb differ diff --git a/cpld/db/GR8RAM.cmp0.ddb b/cpld/db/GR8RAM.cmp0.ddb index a72f1d6..f6edc6c 100644 Binary files a/cpld/db/GR8RAM.cmp0.ddb and b/cpld/db/GR8RAM.cmp0.ddb differ diff --git a/cpld/db/GR8RAM.fit.qmsg b/cpld/db/GR8RAM.fit.qmsg index 10b095c..dcefe2a 100644 --- a/cpld/db/GR8RAM.fit.qmsg +++ b/cpld/db/GR8RAM.fit.qmsg @@ -1,40 +1,38 @@ -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1679994392961 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1679994392961 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1679994392961 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1679994393007 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1679994393007 ""} -{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1679994393038 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1679994393054 ""} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679994393132 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679994393132 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679994393132 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679994393132 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679994393132 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1679994393132 ""} -{ "Info" "ISTA_SDC_FOUND" "GR8RAM.sdc " "Reading SDC File: 'GR8RAM.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1679994393225 ""} -{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1679994393241 ""} -{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1679994393241 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1679994393241 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 40.000 C25M " " 40.000 C25M" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1679994393241 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 978.000 PHI0 " " 978.000 PHI0" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1679994393241 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1679994393241 ""} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1679994393257 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1679994393257 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1679994393257 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1679994393272 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI0 Global clock " "Automatically promoted some destinations of signal \"PHI0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~0 " "Destination \"comb~0\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1679994393272 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI0r1 " "Destination \"PHI0r1\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1679994393272 ""} } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1679994393272 ""} -{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI0 " "Pin \"PHI0\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { PHI0 } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PHI0" } } } } { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } { "temporary_test_loc" "" { Generic "Y:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 417 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1679994393272 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nRESr Global clock " "Automatically promoted some destinations of signal \"nRESr\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "IOROMEN " "Destination \"IOROMEN\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 88 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1679994393272 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RestoreDone~0 " "Destination \"RestoreDone~0\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 150 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1679994393272 ""} } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 16 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1679994393272 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1679994393272 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1679994393272 ""} -{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1679994393319 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1679994393366 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1679994393366 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1679994393366 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1679994393366 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1679994393413 ""} -{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1679994393429 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1679994393554 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1679994393804 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1679994393804 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1679994394585 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1679994394585 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1679994394632 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "31 " "Router estimated average interconnect usage is 31% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "31 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 31% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "Y:/Repos/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 31% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 12 { 0 ""} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1679994394866 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1679994394866 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1679994395147 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.31 " "Total time spent on timing analysis during the Fitter is 0.31 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1679994395163 ""} -{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1679994395179 ""} -{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1679994395225 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1679994395272 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13733 " "Peak virtual memory: 13733 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679994395319 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 28 05:06:35 2023 " "Processing ended: Tue Mar 28 05:06:35 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679994395319 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679994395319 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679994395319 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1679994395319 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1680020962117 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1680020962117 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1680020962117 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1680020962164 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1680020962164 ""} +{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1680020962195 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1680020962195 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1680020962289 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1680020962289 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1680020962289 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1680020962289 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1680020962289 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1680020962289 ""} +{ "Info" "ISTA_SDC_FOUND" "GR8RAM.sdc " "Reading SDC File: 'GR8RAM.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1680020962383 ""} +{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1680020962398 ""} +{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1680020962398 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1680020962398 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 40.000 C25M " " 40.000 C25M" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1680020962398 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 978.000 PHI0 " " 978.000 PHI0" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1680020962398 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1680020962398 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1680020962398 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1680020962398 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1680020962414 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1680020962430 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nRESr Global clock " "Automatically promoted some destinations of signal \"nRESr\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "IOROMEN " "Destination \"IOROMEN\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 90 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1680020962430 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "IOROMEN~0 " "Destination \"IOROMEN~0\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 90 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1680020962430 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "REGEN " "Destination \"REGEN\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 85 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1680020962430 ""} } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 15 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1680020962430 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1680020962430 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1680020962430 ""} +{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1680020962461 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1680020962523 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1680020962523 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1680020962523 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1680020962523 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1680020962571 ""} +{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1680020962586 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1680020962711 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1680020962946 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1680020962946 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1680020963633 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1680020963633 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1680020963680 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "33 " "Router estimated average interconnect usage is 33% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "33 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 33% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "Y:/Repos/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 33% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 12 { 0 ""} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1680020963915 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1680020963915 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1680020964320 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.29 " "Total time spent on timing analysis during the Fitter is 0.29 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1680020964336 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1680020964336 ""} +{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1680020964398 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1680020964445 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13734 " "Peak virtual memory: 13734 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1680020964492 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 28 12:29:24 2023 " "Processing ended: Tue Mar 28 12:29:24 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1680020964492 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1680020964492 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1680020964492 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1680020964492 ""} diff --git a/cpld/db/GR8RAM.hier_info b/cpld/db/GR8RAM.hier_info index 1680337..d454bfb 100644 --- a/cpld/db/GR8RAM.hier_info +++ b/cpld/db/GR8RAM.hier_info @@ -34,8 +34,8 @@ C25M => MOSIout.CLK C25M => MOSIOE.CLK C25M => nFCS~reg0.CLK C25M => FCKout.CLK -C25M => RestoreDone.CLK C25M => Bank.CLK +C25M => RestoreDone.CLK C25M => AddrIncH.CLK C25M => AddrIncM.CLK C25M => AddrIncL.CLK @@ -64,7 +64,6 @@ C25M => Addr[21].CLK C25M => Addr[22].CLK C25M => Addr[23].CLK C25M => IOROMEN.CLK -C25M => nIOSTRBr.CLK C25M => REGEN.CLK C25M => nRESout~reg0.CLK C25M => LS[0].CLK @@ -86,10 +85,6 @@ C25M => PS[1].CLK C25M => PS[2].CLK C25M => PS[3].CLK C25M => nRESr.CLK -C25M => nRESf[0].CLK -C25M => nRESf[1].CLK -C25M => nRESf[2].CLK -C25M => nRESf[3].CLK C25M => PHI0r2.CLK C25M => PHI0r1.CLK C25M => IS~7.DATAIN @@ -102,26 +97,22 @@ C25M => RDD[5].CLK C25M => RDD[6].CLK C25M => RDD[7].CLK PHI0 => comb.IN1 -PHI0 => nWEr.CLK -PHI0 => RAr[0].CLK -PHI0 => RAr[1].CLK -PHI0 => RAr[2].CLK -PHI0 => RAr[3].CLK -PHI0 => RAr[4].CLK -PHI0 => RAr[5].CLK -PHI0 => RAr[6].CLK -PHI0 => RAr[7].CLK -PHI0 => RAr[8].CLK -PHI0 => RAr[9].CLK -PHI0 => RAr[10].CLK -PHI0 => RAr[11].CLK -PHI0 => CXXXr.CLK PHI0 => PHI0r1.DATAIN -nRES => MOSIout.OUTPUTSELECT -nRES => nRESf[0].DATAIN +nRES => nRESr.DATAIN nRESout <= nRESout~reg0.DB_MAX_OUTPUT_PORT_TYPE -SetFW[0] => ~NO_FANOUT~ -SetFW[1] => ~NO_FANOUT~ +SetFW[0] => Mux1.IN7 +SetFW[0] => Equal1.IN1 +SetFW[1] => comb.IN1 +SetFW[1] => RDD.OUTPUTSELECT +SetFW[1] => RDD.OUTPUTSELECT +SetFW[1] => RDD.OUTPUTSELECT +SetFW[1] => RDD.OUTPUTSELECT +SetFW[1] => SA.OUTPUTSELECT +SetFW[1] => SA.OUTPUTSELECT +SetFW[1] => SA.OUTPUTSELECT +SetFW[1] => SBA.OUTPUTSELECT +SetFW[1] => MOSIout.DATAB +SetFW[1] => Equal1.IN0 INTin => INTout.DATAIN INTout <= INTin.DB_MAX_OUTPUT_PORT_TYPE DMAin => DMAout.DATAIN @@ -132,35 +123,78 @@ nRDYout <= nINHout <= RWout <= nDMAout <= -RA[0] => RAr[0].DATAIN +RA[0] => MOSIout.DATAA +RA[0] => DQML.DATAA +RA[0] => Equal10.IN3 +RA[0] => Equal11.IN3 +RA[0] => Equal12.IN1 +RA[0] => Equal13.IN3 +RA[0] => Equal14.IN2 +RA[0] => Equal15.IN3 +RA[0] => Equal16.IN3 RA[0] => Equal17.IN10 -RA[1] => RAr[1].DATAIN +RA[0] => DQMH.DATAA +RA[1] => SA.DATAA +RA[1] => Equal10.IN2 +RA[1] => Equal11.IN0 +RA[1] => Equal12.IN0 +RA[1] => Equal13.IN2 +RA[1] => Equal14.IN3 +RA[1] => Equal15.IN2 +RA[1] => Equal16.IN2 RA[1] => Equal17.IN9 -RA[2] => RAr[2].DATAIN +RA[2] => SA.DATAA +RA[2] => Equal10.IN1 +RA[2] => Equal11.IN2 +RA[2] => Equal12.IN3 +RA[2] => Equal13.IN1 +RA[2] => Equal14.IN1 +RA[2] => Equal15.IN1 +RA[2] => Equal16.IN1 RA[2] => Equal17.IN8 -RA[3] => RAr[3].DATAIN +RA[3] => SA.DATAA +RA[3] => Equal10.IN0 +RA[3] => Equal11.IN1 +RA[3] => Equal12.IN2 +RA[3] => Equal13.IN0 +RA[3] => Equal14.IN0 +RA[3] => Equal15.IN0 +RA[3] => Equal16.IN0 RA[3] => Equal17.IN7 -RA[4] => RAr[4].DATAIN +RA[4] => SA.DATAA RA[4] => Equal17.IN6 -RA[5] => RAr[5].DATAIN +RA[5] => SA.DATAA RA[5] => Equal17.IN5 -RA[6] => RAr[6].DATAIN +RA[6] => SA.DATAA RA[6] => Equal17.IN4 -RA[7] => RAr[7].DATAIN +RA[7] => comb.IN1 +RA[7] => SA.DATAA RA[7] => Equal17.IN3 -RA[8] => RAr[8].DATAIN +RA[8] => SA.DATAA +RA[8] => Equal9.IN3 RA[8] => Equal17.IN2 -RA[9] => RAr[9].DATAIN +RA[9] => SA.DATAA +RA[9] => Equal9.IN2 RA[9] => Equal17.IN1 -RA[10] => RAr[10].DATAIN +RA[10] => SA.DATAA +RA[10] => Equal9.IN1 RA[10] => Equal17.IN0 -RA[11] => RAr[11].DATAIN -RA[12] => Equal7.IN1 -RA[13] => Equal7.IN0 -RA[14] => Equal7.IN3 -RA[15] => Equal7.IN2 +RA[11] => comb.IN1 +RA[11] => SA.DATAA +RA[11] => comb.IN1 +RA[11] => Equal9.IN0 +RA[12] => Equal8.IN1 +RA[13] => Equal8.IN0 +RA[14] => Equal8.IN3 +RA[15] => Equal8.IN2 nWE => comb.IN1 -nWE => nWEr.DATAIN +nWE => comb.IN1 +nWE => nRCS.IN0 +nWE => RAMWR.IN1 +nWE => BankWR.IN1 +nWE => always7.IN1 +nWE => always7.IN1 +nWE => always7.IN1 RD[0] <> RD[0] RD[1] <> RD[1] RD[2] <> RD[2] @@ -173,15 +207,14 @@ RAdir <= RDdir <= comb.DB_MAX_OUTPUT_PORT_TYPE nIOSEL => SA.OUTPUTSELECT nIOSEL => comb.IN0 -nIOSEL => always6.IN1 +nIOSEL => always5.IN1 nDEVSEL => comb.IN1 nDEVSEL => RAMSEL.IN1 nDEVSEL => FCKout.IN1 nDEVSEL => comb.IN1 nDEVSEL => RAMRegSEL.IN1 -nIOSTRB => nIOSTRBr.DATAIN -nIOSTRB => comb.IN1 nIOSTRB => comb.IN1 +nIOSTRB => IOROMRES.IN1 SBA[0] <= SBA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE SBA[1] <= SBA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE SA[0] <= SA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE diff --git a/cpld/db/GR8RAM.hif b/cpld/db/GR8RAM.hif index 3eb0cef..a7019e1 100644 Binary files a/cpld/db/GR8RAM.hif and b/cpld/db/GR8RAM.hif differ diff --git a/cpld/db/GR8RAM.map.cdb b/cpld/db/GR8RAM.map.cdb index 4caad7f..87456a7 100644 Binary files a/cpld/db/GR8RAM.map.cdb and b/cpld/db/GR8RAM.map.cdb differ diff --git a/cpld/db/GR8RAM.map.hdb b/cpld/db/GR8RAM.map.hdb index e385e48..aa0f6f5 100644 Binary files a/cpld/db/GR8RAM.map.hdb and b/cpld/db/GR8RAM.map.hdb differ diff --git a/cpld/db/GR8RAM.map.qmsg b/cpld/db/GR8RAM.map.qmsg index d503ea7..d2c0ed9 100644 --- a/cpld/db/GR8RAM.map.qmsg +++ b/cpld/db/GR8RAM.map.qmsg @@ -1,21 +1,22 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1679994373538 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1679994373554 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 28 05:06:13 2023 " "Processing started: Tue Mar 28 05:06:13 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1679994373554 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679994373554 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679994373554 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1679994373897 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1679994373897 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(104) " "Verilog HDL warning at GR8RAM.v(104): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 104 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1679994390038 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(281) " "Verilog HDL warning at GR8RAM.v(281): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 281 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1679994390038 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679994390038 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679994390038 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1679994390069 ""} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(34) " "Verilog HDL assignment warning at GR8RAM.v(34): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 34 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1679994390085 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(39) " "Verilog HDL assignment warning at GR8RAM.v(39): truncated value with size 32 to match size of target (14)" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 39 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1679994390085 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(128) " "Verilog HDL assignment warning at GR8RAM.v(128): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 128 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1679994390085 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(136) " "Verilog HDL assignment warning at GR8RAM.v(136): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 136 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1679994390085 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(143) " "Verilog HDL assignment warning at GR8RAM.v(143): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 143 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1679994390085 "|GR8RAM"} -{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Analysis & Synthesis" 0 -1 1679994390538 ""} -{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "nNMIout VCC " "Pin \"nNMIout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 559 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1679994390757 "|GR8RAM|nNMIout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nIRQout VCC " "Pin \"nIRQout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 562 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1679994390757 "|GR8RAM|nIRQout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nRDYout VCC " "Pin \"nRDYout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 561 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1679994390757 "|GR8RAM|nRDYout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nINHout VCC " "Pin \"nINHout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 560 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1679994390757 "|GR8RAM|nINHout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RWout VCC " "Pin \"RWout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 563 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1679994390757 "|GR8RAM|RWout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nDMAout VCC " "Pin \"nDMAout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 558 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1679994390757 "|GR8RAM|nDMAout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 557 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1679994390757 "|GR8RAM|RAdir"} { "Warning" "WMLS_MLS_STUCK_PIN" "SBA\[0\] GND " "Pin \"SBA\[0\]\" is stuck at GND" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 442 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1679994390757 "|GR8RAM|SBA[0]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1679994390757 ""} -{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1679994391085 ""} -{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SetFW\[0\] " "No output dependent on input pin \"SetFW\[0\]\"" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 23 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1679994391100 "|GR8RAM|SetFW[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SetFW\[1\] " "No output dependent on input pin \"SetFW\[1\]\"" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 23 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1679994391100 "|GR8RAM|SetFW[1]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1679994391100 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "336 " "Implemented 336 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "28 " "Implemented 28 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1679994391100 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1679994391100 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Design Software" 0 -1 1679994391100 ""} { "Info" "ICUT_CUT_TM_LCELLS" "256 " "Implemented 256 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1679994391100 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1679994391100 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679994391147 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 18 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 18 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13094 " "Peak virtual memory: 13094 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679994391179 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 28 05:06:31 2023 " "Processing ended: Tue Mar 28 05:06:31 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679994391179 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:18 " "Elapsed time: 00:00:18" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679994391179 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:39 " "Total CPU time (on all processors): 00:00:39" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679994391179 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1679994391179 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1680020941950 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1680020941966 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 28 12:29:01 2023 " "Processing started: Tue Mar 28 12:29:01 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1680020941966 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1680020941966 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1680020941966 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1680020942309 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1680020942309 ""} +{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "1 GR8RAM.v(21) " "Verilog HDL Expression warning at GR8RAM.v(21): truncated literal to match 1 bits" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 21 0 0 } } } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "Analysis & Synthesis" 0 -1 1680020959164 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(99) " "Verilog HDL warning at GR8RAM.v(99): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 99 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1680020959164 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(278) " "Verilog HDL warning at GR8RAM.v(278): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 278 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1680020959164 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1680020959164 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1680020959164 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1680020959211 ""} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "RAMSpecSELAny GR8RAM.v(69) " "Verilog HDL or VHDL warning at GR8RAM.v(69): object \"RAMSpecSELAny\" assigned a value but never read" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 69 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1680020959211 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(31) " "Verilog HDL assignment warning at GR8RAM.v(31): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 31 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1680020959211 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(36) " "Verilog HDL assignment warning at GR8RAM.v(36): truncated value with size 32 to match size of target (14)" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 36 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1680020959211 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(123) " "Verilog HDL assignment warning at GR8RAM.v(123): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 123 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1680020959211 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(131) " "Verilog HDL assignment warning at GR8RAM.v(131): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 131 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1680020959211 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(138) " "Verilog HDL assignment warning at GR8RAM.v(138): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 138 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1680020959211 "|GR8RAM"} +{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Analysis & Synthesis" 0 -1 1680020959664 ""} +{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "nNMIout VCC " "Pin \"nNMIout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 556 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1680020959930 "|GR8RAM|nNMIout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nIRQout VCC " "Pin \"nIRQout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 559 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1680020959930 "|GR8RAM|nIRQout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nRDYout VCC " "Pin \"nRDYout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 558 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1680020959930 "|GR8RAM|nRDYout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nINHout VCC " "Pin \"nINHout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 557 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1680020959930 "|GR8RAM|nINHout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RWout VCC " "Pin \"RWout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 560 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1680020959930 "|GR8RAM|RWout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nDMAout VCC " "Pin \"nDMAout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 555 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1680020959930 "|GR8RAM|nDMAout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 554 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1680020959930 "|GR8RAM|RAdir"} { "Warning" "WMLS_MLS_STUCK_PIN" "SA\[12\] GND " "Pin \"SA\[12\]\" is stuck at GND" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 439 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1680020959930 "|GR8RAM|SA[12]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1680020959930 ""} +{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1680020960320 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "321 " "Implemented 321 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "28 " "Implemented 28 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1680020960337 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1680020960337 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Design Software" 0 -1 1680020960337 ""} { "Info" "ICUT_CUT_TM_LCELLS" "241 " "Implemented 241 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1680020960337 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1680020960337 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1680020960383 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 17 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 17 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13095 " "Peak virtual memory: 13095 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1680020960414 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 28 12:29:20 2023 " "Processing ended: Tue Mar 28 12:29:20 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1680020960414 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:19 " "Elapsed time: 00:00:19" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1680020960414 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:40 " "Total CPU time (on all processors): 00:00:40" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1680020960414 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1680020960414 ""} diff --git a/cpld/db/GR8RAM.map.rdb b/cpld/db/GR8RAM.map.rdb index 999fd86..7feb4a0 100644 Binary files a/cpld/db/GR8RAM.map.rdb and b/cpld/db/GR8RAM.map.rdb differ diff --git a/cpld/db/GR8RAM.pre_map.hdb b/cpld/db/GR8RAM.pre_map.hdb index 07e0e17..6b4d664 100644 Binary files a/cpld/db/GR8RAM.pre_map.hdb and b/cpld/db/GR8RAM.pre_map.hdb differ diff --git a/cpld/db/GR8RAM.root_partition.map.reg_db.cdb b/cpld/db/GR8RAM.root_partition.map.reg_db.cdb index 142d755..d880104 100644 Binary files a/cpld/db/GR8RAM.root_partition.map.reg_db.cdb and b/cpld/db/GR8RAM.root_partition.map.reg_db.cdb differ diff --git a/cpld/db/GR8RAM.routing.rdb b/cpld/db/GR8RAM.routing.rdb index 02debe0..2194e6a 100644 Binary files a/cpld/db/GR8RAM.routing.rdb and b/cpld/db/GR8RAM.routing.rdb differ diff --git a/cpld/db/GR8RAM.rtlv.hdb b/cpld/db/GR8RAM.rtlv.hdb index 672d736..0ccaa20 100644 Binary files a/cpld/db/GR8RAM.rtlv.hdb and b/cpld/db/GR8RAM.rtlv.hdb differ diff --git a/cpld/db/GR8RAM.rtlv_sg.cdb b/cpld/db/GR8RAM.rtlv_sg.cdb index e3abbbc..2397f7f 100644 Binary files a/cpld/db/GR8RAM.rtlv_sg.cdb and b/cpld/db/GR8RAM.rtlv_sg.cdb differ diff --git a/cpld/db/GR8RAM.sta.qmsg b/cpld/db/GR8RAM.sta.qmsg index 59e52fd..35f7ff8 100644 --- a/cpld/db/GR8RAM.sta.qmsg +++ b/cpld/db/GR8RAM.sta.qmsg @@ -1,22 +1,22 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1679994398756 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1679994398756 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 28 05:06:38 2023 " "Processing started: Tue Mar 28 05:06:38 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1679994398756 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1679994398756 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1679994398756 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1679994398866 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1679994399077 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1679994399077 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679994399112 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679994399112 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1679994399175 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1679994399581 ""} -{ "Info" "ISTA_SDC_FOUND" "GR8RAM.sdc " "Reading SDC File: 'GR8RAM.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Timing Analyzer" 0 -1 1679994399659 ""} -{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1679994399659 ""} -{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1679994399690 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup 12.472 " "Worst-case setup slack is 12.472" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399706 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399706 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 12.472 0.000 C25M " " 12.472 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399706 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679994399706 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.383 " "Worst-case hold slack is 1.383" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399706 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399706 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.383 0.000 C25M " " 1.383 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399706 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679994399706 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 33.331 " "Worst-case recovery slack is 33.331" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399722 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399722 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 33.331 0.000 C25M " " 33.331 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399722 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679994399722 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "removal 6.115 " "Worst-case removal slack is 6.115" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399722 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399722 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 6.115 0.000 C25M " " 6.115 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399722 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679994399722 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 19.734 " "Worst-case minimum pulse width slack is 19.734" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399722 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399722 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.734 0.000 C25M " " 19.734 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399722 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 488.734 0.000 PHI0 " " 488.734 0.000 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399722 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679994399722 ""} -{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Timing Analyzer" 0 -1 1679994399769 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1679994399784 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1679994399784 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1 Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13052 " "Peak virtual memory: 13052 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679994399847 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 28 05:06:39 2023 " "Processing ended: Tue Mar 28 05:06:39 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679994399847 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679994399847 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679994399847 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1679994399847 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1680020967867 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1680020967867 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 28 12:29:27 2023 " "Processing started: Tue Mar 28 12:29:27 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1680020967867 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1680020967867 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1680020967867 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1680020967977 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1680020968133 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1680020968133 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1680020968165 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1680020968165 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1680020968226 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1680020968665 ""} +{ "Info" "ISTA_SDC_FOUND" "GR8RAM.sdc " "Reading SDC File: 'GR8RAM.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Timing Analyzer" 0 -1 1680020968726 ""} +{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1680020968742 ""} +{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1680020968758 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup 14.455 " "Worst-case setup slack is 14.455" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680020968758 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680020968758 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 14.455 0.000 C25M " " 14.455 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680020968758 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1680020968758 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.374 " "Worst-case hold slack is 1.374" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680020968773 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680020968773 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.374 0.000 C25M " " 1.374 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680020968773 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1680020968773 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 34.082 " "Worst-case recovery slack is 34.082" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680020968773 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680020968773 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 34.082 0.000 C25M " " 34.082 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680020968773 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1680020968773 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "removal 5.364 " "Worst-case removal slack is 5.364" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680020968773 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680020968773 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 5.364 0.000 C25M " " 5.364 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680020968773 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1680020968773 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 19.734 " "Worst-case minimum pulse width slack is 19.734" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680020968789 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680020968789 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.734 0.000 C25M " " 19.734 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680020968789 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 974.000 0.000 PHI0 " " 974.000 0.000 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680020968789 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1680020968789 ""} +{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Timing Analyzer" 0 -1 1680020968820 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1680020968836 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1680020968851 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1 Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13053 " "Peak virtual memory: 13053 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1680020968914 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 28 12:29:28 2023 " "Processing ended: Tue Mar 28 12:29:28 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1680020968914 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1680020968914 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1680020968914 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1680020968914 ""} diff --git a/cpld/db/GR8RAM.sta.rdb b/cpld/db/GR8RAM.sta.rdb index 691152f..eb993e5 100644 Binary files a/cpld/db/GR8RAM.sta.rdb and b/cpld/db/GR8RAM.sta.rdb differ diff --git a/cpld/db/GR8RAM.sta_cmp.5_slow.tdb b/cpld/db/GR8RAM.sta_cmp.5_slow.tdb index 1779d3b..bdf25fa 100644 Binary files a/cpld/db/GR8RAM.sta_cmp.5_slow.tdb and b/cpld/db/GR8RAM.sta_cmp.5_slow.tdb differ diff --git a/cpld/db/GR8RAM.vpr.ammdb b/cpld/db/GR8RAM.vpr.ammdb index 4a5bb33..c408771 100644 Binary files a/cpld/db/GR8RAM.vpr.ammdb and b/cpld/db/GR8RAM.vpr.ammdb differ diff --git a/cpld/db/prev_cmp_GR8RAM.qmsg b/cpld/db/prev_cmp_GR8RAM.qmsg index 3ae229c..a772bd0 100644 --- a/cpld/db/prev_cmp_GR8RAM.qmsg +++ b/cpld/db/prev_cmp_GR8RAM.qmsg @@ -1,11 +1,12 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1679994334673 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1679994334673 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 28 05:05:34 2023 " "Processing started: Tue Mar 28 05:05:34 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1679994334673 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679994334673 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679994334673 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1679994335048 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1679994335048 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(103) " "Verilog HDL warning at GR8RAM.v(103): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 103 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1679994351125 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(280) " "Verilog HDL warning at GR8RAM.v(280): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 280 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1679994351125 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679994351125 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679994351125 ""} -{ "Error" "EVRFX_VERI_UNDECLARED_OBJECT" "SetFW GR8RAM.v(1) " "Verilog HDL error at GR8RAM.v(1): object \"SetFW\" is not declared. Verify the object name is correct. If the name is correct, declare the object." { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 1 0 0 } } } 0 10161 "Verilog HDL error at %2!s!: object \"%1!s!\" is not declared. Verify the object name is correct. If the name is correct, declare the object." 0 0 "Analysis & Synthesis" 0 -1 1679994351125 ""} -{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 1 error, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "13076 " "Peak virtual memory: 13076 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679994351157 ""} { "Error" "EQEXE_END_BANNER_TIME" "Tue Mar 28 05:05:51 2023 " "Processing ended: Tue Mar 28 05:05:51 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679994351157 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:17 " "Elapsed time: 00:00:17" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679994351157 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:39 " "Total CPU time (on all processors): 00:00:39" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679994351157 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1679994351157 ""} -{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 3 s 1 " "Quartus Prime Full Compilation was unsuccessful. 3 errors, 1 warning" { } { } 0 293001 "Quartus Prime %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1679994351875 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1680020872985 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1680020873000 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 28 12:27:52 2023 " "Processing started: Tue Mar 28 12:27:52 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1680020873000 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1680020873000 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1680020873000 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1680020873375 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1680020873375 ""} +{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "1 GR8RAM.v(21) " "Verilog HDL Expression warning at GR8RAM.v(21): truncated literal to match 1 bits" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 21 0 0 } } } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "Analysis & Synthesis" 0 -1 1680020890672 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(98) " "Verilog HDL warning at GR8RAM.v(98): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 98 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1680020890672 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(277) " "Verilog HDL warning at GR8RAM.v(277): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 277 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1680020890672 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1680020890672 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1680020890672 ""} +{ "Error" "EVRFX_VERI_UNDECLARED_OBJECT" "BankSpecSELAny GR8RAM.v(324) " "Verilog HDL error at GR8RAM.v(324): object \"BankSpecSELAny\" is not declared. Verify the object name is correct. If the name is correct, declare the object." { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 324 0 0 } } } 0 10161 "Verilog HDL error at %2!s!: object \"%1!s!\" is not declared. Verify the object name is correct. If the name is correct, declare the object." 0 0 "Analysis & Synthesis" 0 -1 1680020890672 ""} +{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1 2 s Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 1 error, 2 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "13078 " "Peak virtual memory: 13078 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1680020890719 ""} { "Error" "EQEXE_END_BANNER_TIME" "Tue Mar 28 12:28:10 2023 " "Processing ended: Tue Mar 28 12:28:10 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1680020890719 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:18 " "Elapsed time: 00:00:18" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1680020890719 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:39 " "Total CPU time (on all processors): 00:00:39" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1680020890719 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1680020890719 ""} +{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 3 s 2 s " "Quartus Prime Full Compilation was unsuccessful. 3 errors, 2 warnings" { } { } 0 293001 "Quartus Prime %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1680020891407 ""} diff --git a/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt b/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt index 7381f89..da5ca3d 100755 Binary files a/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt and b/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt differ diff --git a/cpld/output_files/GR8RAM.asm.rpt b/cpld/output_files/GR8RAM.asm.rpt index f69645f..3a949f9 100644 --- a/cpld/output_files/GR8RAM.asm.rpt +++ b/cpld/output_files/GR8RAM.asm.rpt @@ -1,5 +1,5 @@ Assembler report for GR8RAM -Tue Mar 28 05:06:37 2023 +Tue Mar 28 12:29:26 2023 Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition @@ -38,7 +38,7 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Tue Mar 28 05:06:37 2023 ; +; Assembler Status ; Successful - Tue Mar 28 12:29:26 2023 ; ; Revision Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ; ; Family ; MAX II ; @@ -67,8 +67,8 @@ https://fpgasoftware.intel.com/eula. +----------------+-------------------------------------------------------+ ; Option ; Setting ; +----------------+-------------------------------------------------------+ -; JTAG usercode ; 0x001615F8 ; -; Checksum ; 0x001618F8 ; +; JTAG usercode ; 0x00161718 ; +; Checksum ; 0x00161B18 ; +----------------+-------------------------------------------------------+ @@ -78,14 +78,14 @@ https://fpgasoftware.intel.com/eula. Info: ******************************************************************* Info: Running Quartus Prime Assembler Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition - Info: Processing started: Tue Mar 28 05:06:36 2023 + Info: Processing started: Tue Mar 28 12:29:25 2023 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (115031): Writing out detailed assembly data for power analysis Info (115030): Assembler is generating device programming files Info: Quartus Prime Assembler was successful. 0 errors, 1 warning - Info: Peak virtual memory: 13057 megabytes - Info: Processing ended: Tue Mar 28 05:06:37 2023 + Info: Peak virtual memory: 13059 megabytes + Info: Processing ended: Tue Mar 28 12:29:26 2023 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 diff --git a/cpld/output_files/GR8RAM.done b/cpld/output_files/GR8RAM.done index 582637b..2b87f3c 100755 --- a/cpld/output_files/GR8RAM.done +++ b/cpld/output_files/GR8RAM.done @@ -1 +1 @@ -Tue Mar 28 05:06:40 2023 +Tue Mar 28 12:29:29 2023 diff --git a/cpld/output_files/GR8RAM.fit.rpt b/cpld/output_files/GR8RAM.fit.rpt index 544622d..47211a7 100644 --- a/cpld/output_files/GR8RAM.fit.rpt +++ b/cpld/output_files/GR8RAM.fit.rpt @@ -1,5 +1,5 @@ Fitter report for GR8RAM -Tue Mar 28 05:06:35 2023 +Tue Mar 28 12:29:24 2023 Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition @@ -57,7 +57,7 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------------+ ; Fitter Summary ; +-----------------------+---------------------------------------------+ -; Fitter Status ; Successful - Tue Mar 28 05:06:35 2023 ; +; Fitter Status ; Successful - Tue Mar 28 12:29:24 2023 ; ; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; ; Revision Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ; @@ -129,13 +129,13 @@ https://fpgasoftware.intel.com/eula. ; Number detected on machine ; 4 ; ; Maximum allowed ; 4 ; ; ; ; -; Average used ; 1.04 ; +; Average used ; 1.03 ; ; Maximum used ; 4 ; ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; -; Processor 2 ; 1.6% ; -; Processors 3-4 ; 1.2% ; +; Processor 2 ; 1.3% ; +; Processors 3-4 ; 1.0% ; +----------------------------+-------------+ @@ -151,26 +151,26 @@ The pin-out file can be found in Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin. ; Resource ; Usage ; +---------------------------------------------+-----------------------+ ; Total logic elements ; 236 / 240 ( 98 % ) ; -; -- Combinational with no register ; 119 ; +; -- Combinational with no register ; 138 ; ; -- Register only ; 1 ; -; -- Combinational with a register ; 116 ; +; -- Combinational with a register ; 97 ; ; ; ; ; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 137 ; -; -- 3 input functions ; 35 ; -; -- 2 input functions ; 63 ; -; -- 1 input functions ; 0 ; +; -- 4 input functions ; 136 ; +; -- 3 input functions ; 38 ; +; -- 2 input functions ; 60 ; +; -- 1 input functions ; 1 ; ; -- 0 input functions ; 0 ; ; ; ; ; Logic elements by mode ; ; ; -- normal mode ; 203 ; ; -- arithmetic mode ; 33 ; -; -- qfbk mode ; 15 ; +; -- qfbk mode ; 4 ; ; -- register cascade mode ; 0 ; -; -- synchronous clear/load mode ; 64 ; +; -- synchronous clear/load mode ; 49 ; ; -- asynchronous clear/load mode ; 29 ; ; ; ; -; Total registers ; 117 / 240 ( 49 % ) ; +; Total registers ; 98 / 240 ( 41 % ) ; ; Total LABs ; 24 / 24 ( 100 % ) ; ; Logic elements in carry chains ; 37 ; ; Virtual pins ; 0 ; @@ -182,15 +182,15 @@ The pin-out file can be found in Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin. ; -- Total Fixed Point DSP Blocks ; 0 ; ; -- Total Floating Point DSP Blocks ; 0 ; ; ; ; -; Global signals ; 3 ; -; -- Global clocks ; 3 / 4 ( 75 % ) ; +; Global signals ; 2 ; +; -- Global clocks ; 2 / 4 ( 50 % ) ; ; JTAGs ; 0 / 1 ( 0 % ) ; -; Average interconnect usage (total/H/V) ; 38.7% / 42.5% / 34.6% ; -; Peak interconnect usage (total/H/V) ; 38.7% / 42.5% / 34.6% ; -; Maximum fan-out ; 103 ; -; Highest non-global fan-out ; 53 ; -; Total fan-out ; 1101 ; -; Average fan-out ; 3.48 ; +; Average interconnect usage (total/H/V) ; 43.7% / 46.4% / 40.8% ; +; Peak interconnect usage (total/H/V) ; 43.7% / 46.4% / 40.8% ; +; Maximum fan-out ; 98 ; +; Highest non-global fan-out ; 54 ; +; Total fan-out ; 1081 ; +; Average fan-out ; 3.42 ; +---------------------------------------------+-----------------------+ @@ -199,34 +199,34 @@ The pin-out file can be found in Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin. +----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+----------------------------+----------------------+----------------+ ; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Location assigned by ; Slow Slew Rate ; +----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+----------------------------+----------------------+----------------+ -; C25M ; 64 ; 2 ; 8 ; 3 ; 4 ; 103 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; +; C25M ; 64 ; 2 ; 8 ; 3 ; 4 ; 98 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; ; DMAin ; 48 ; 1 ; 6 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; ; INTin ; 49 ; 1 ; 7 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; ; MISO ; 16 ; 1 ; 1 ; 2 ; 2 ; 2 ; 0 ; no ; no ; yes ; Off ; 3.3-V LVTTL ; User ; no ; -; PHI0 ; 41 ; 1 ; 5 ; 0 ; 1 ; 15 ; 0 ; yes ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; no ; -; RA[0] ; 100 ; 2 ; 2 ; 5 ; 2 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; -; RA[10] ; 14 ; 1 ; 1 ; 2 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; -; RA[11] ; 34 ; 1 ; 3 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; +; PHI0 ; 41 ; 1 ; 5 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; no ; +; RA[0] ; 100 ; 2 ; 2 ; 5 ; 2 ; 11 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; +; RA[10] ; 14 ; 1 ; 1 ; 2 ; 0 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; +; RA[11] ; 34 ; 1 ; 3 ; 0 ; 1 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; ; RA[12] ; 35 ; 1 ; 3 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; ; RA[13] ; 36 ; 1 ; 4 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; ; RA[14] ; 37 ; 1 ; 4 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; ; RA[15] ; 38 ; 1 ; 4 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; -; RA[1] ; 98 ; 2 ; 2 ; 5 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; -; RA[2] ; 97 ; 2 ; 3 ; 5 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; -; RA[3] ; 4 ; 1 ; 1 ; 4 ; 2 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; +; RA[1] ; 98 ; 2 ; 2 ; 5 ; 0 ; 10 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; +; RA[2] ; 97 ; 2 ; 3 ; 5 ; 3 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; +; RA[3] ; 4 ; 1 ; 1 ; 4 ; 2 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; ; RA[4] ; 1 ; 2 ; 2 ; 5 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; ; RA[5] ; 2 ; 1 ; 1 ; 4 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; ; RA[6] ; 3 ; 1 ; 1 ; 4 ; 1 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; -; RA[7] ; 6 ; 1 ; 1 ; 3 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; -; RA[8] ; 7 ; 1 ; 1 ; 3 ; 1 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; -; RA[9] ; 8 ; 1 ; 1 ; 3 ; 2 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; -; SetFW[0] ; 96 ; 2 ; 3 ; 5 ; 2 ; 0 ; 0 ; no ; no ; no ; On ; 3.3V Schmitt Trigger Input ; User ; no ; -; SetFW[1] ; 95 ; 2 ; 3 ; 5 ; 1 ; 0 ; 0 ; no ; no ; no ; On ; 3.3V Schmitt Trigger Input ; User ; no ; +; RA[7] ; 6 ; 1 ; 1 ; 3 ; 0 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; +; RA[8] ; 7 ; 1 ; 1 ; 3 ; 1 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; +; RA[9] ; 8 ; 1 ; 1 ; 3 ; 2 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; +; SetFW[0] ; 96 ; 2 ; 3 ; 5 ; 2 ; 2 ; 0 ; no ; no ; no ; On ; 3.3V Schmitt Trigger Input ; User ; no ; +; SetFW[1] ; 95 ; 2 ; 3 ; 5 ; 1 ; 10 ; 0 ; no ; no ; no ; On ; 3.3V Schmitt Trigger Input ; User ; no ; ; nDEVSEL ; 40 ; 1 ; 5 ; 0 ; 2 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; no ; -; nIOSEL ; 39 ; 1 ; 5 ; 0 ; 3 ; 4 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; no ; -; nIOSTRB ; 42 ; 1 ; 5 ; 0 ; 0 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; no ; +; nIOSEL ; 39 ; 1 ; 5 ; 0 ; 3 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; no ; +; nIOSTRB ; 42 ; 1 ; 5 ; 0 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; no ; ; nRES ; 44 ; 1 ; 6 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; no ; -; nWE ; 43 ; 1 ; 6 ; 0 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; no ; +; nWE ; 43 ; 1 ; 6 ; 0 ; 3 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; no ; +----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+----------------------------+----------------------+----------------+ @@ -252,7 +252,7 @@ The pin-out file can be found in Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin. ; SA[2] ; 82 ; 2 ; 6 ; 5 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; ; SA[3] ; 84 ; 2 ; 6 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; ; SA[4] ; 76 ; 2 ; 7 ; 5 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; -; SA[5] ; 83 ; 2 ; 6 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; yes ; User ; 10 pF ; - ; - ; +; SA[5] ; 83 ; 2 ; 6 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; ; SA[6] ; 77 ; 2 ; 7 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; ; SA[7] ; 78 ; 2 ; 7 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; ; SA[8] ; 74 ; 2 ; 8 ; 4 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; @@ -265,11 +265,11 @@ The pin-out file can be found in Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin. ; nINHout ; 27 ; 1 ; 2 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; ; nIRQout ; 29 ; 1 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; ; nNMIout ; 26 ; 1 ; 2 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; -; nRAS ; 62 ; 2 ; 8 ; 2 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; yes ; User ; 10 pF ; - ; - ; +; nRAS ; 62 ; 2 ; 8 ; 2 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; ; nRCS ; 67 ; 2 ; 8 ; 3 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; ; nRDYout ; 28 ; 1 ; 2 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; -; nRESout ; 30 ; 1 ; 3 ; 0 ; 3 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; yes ; User ; 10 pF ; - ; - ; -; nSWE ; 58 ; 2 ; 8 ; 2 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; +; nRESout ; 30 ; 1 ; 3 ; 0 ; 3 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; +; nSWE ; 58 ; 2 ; 8 ; 2 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; yes ; User ; 10 pF ; - ; - ; +---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ @@ -278,15 +278,15 @@ The pin-out file can be found in Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin. +-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ ; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ; +-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ -; MOSI ; 15 ; 1 ; 1 ; 2 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; MOSIOE ; - ; -; RD[0] ; 86 ; 2 ; 5 ; 5 ; 1 ; 6 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ; -; RD[1] ; 87 ; 2 ; 5 ; 5 ; 2 ; 5 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; yes ; User ; 10 pF ; comb~2 ; - ; -; RD[2] ; 88 ; 2 ; 5 ; 5 ; 3 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ; -; RD[3] ; 89 ; 2 ; 4 ; 5 ; 0 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; yes ; User ; 10 pF ; comb~2 ; - ; -; RD[4] ; 90 ; 2 ; 4 ; 5 ; 1 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ; -; RD[5] ; 91 ; 2 ; 4 ; 5 ; 2 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; yes ; User ; 10 pF ; comb~2 ; - ; -; RD[6] ; 92 ; 2 ; 3 ; 5 ; 0 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ; -; RD[7] ; 99 ; 2 ; 2 ; 5 ; 1 ; 6 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ; +; MOSI ; 15 ; 1 ; 1 ; 2 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; yes ; User ; 10 pF ; MOSIOE ; - ; +; RD[0] ; 86 ; 2 ; 5 ; 5 ; 1 ; 6 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~1 ; - ; +; RD[1] ; 87 ; 2 ; 5 ; 5 ; 2 ; 5 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~1 ; - ; +; RD[2] ; 88 ; 2 ; 5 ; 5 ; 3 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~1 ; - ; +; RD[3] ; 89 ; 2 ; 4 ; 5 ; 0 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~1 ; - ; +; RD[4] ; 90 ; 2 ; 4 ; 5 ; 1 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~1 ; - ; +; RD[5] ; 91 ; 2 ; 4 ; 5 ; 2 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~1 ; - ; +; RD[6] ; 92 ; 2 ; 3 ; 5 ; 0 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~1 ; - ; +; RD[7] ; 99 ; 2 ; 2 ; 5 ; 1 ; 6 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~1 ; - ; ; SD[0] ; 50 ; 1 ; 7 ; 0 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; ; SD[1] ; 47 ; 1 ; 6 ; 0 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; ; SD[2] ; 56 ; 2 ; 8 ; 1 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; @@ -438,7 +438,7 @@ Note: User assignments will override these defaults. The user specified values a +----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+ ; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ; +----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+ -; |GR8RAM ; 236 (236) ; 117 ; 0 ; 80 ; 0 ; 119 (119) ; 1 (1) ; 116 (116) ; 37 (37) ; 20 (20) ; |GR8RAM ; GR8RAM ; work ; +; |GR8RAM ; 236 (236) ; 98 ; 0 ; 80 ; 0 ; 138 (138) ; 1 (1) ; 97 (97) ; 37 (37) ; 5 (5) ; |GR8RAM ; GR8RAM ; work ; +----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. @@ -449,8 +449,6 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; Name ; Pin Type ; Pad to Core 0 ; +----------+----------+---------------+ ; nRESout ; Output ; -- ; -; SetFW[0] ; Input ; (0) ; -; SetFW[1] ; Input ; (0) ; ; INTout ; Output ; -- ; ; DMAout ; Output ; -- ; ; nNMIout ; Output ; -- ; @@ -504,12 +502,16 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; MOSI ; Bidir ; (1) ; ; INTin ; Input ; (1) ; ; DMAin ; Input ; (1) ; -; PHI0 ; Input ; (0) ; +; nIOSTRB ; Input ; (1) ; +; nIOSEL ; Input ; (1) ; +; nDEVSEL ; Input ; (1) ; +; PHI0 ; Input ; (1) ; ; nWE ; Input ; (1) ; -; RA[0] ; Input ; (1) ; -; RA[1] ; Input ; (1) ; +; C25M ; Input ; (0) ; ; RA[2] ; Input ; (1) ; ; RA[3] ; Input ; (1) ; +; RA[0] ; Input ; (1) ; +; RA[1] ; Input ; (1) ; ; RA[4] ; Input ; (1) ; ; RA[5] ; Input ; (1) ; ; RA[6] ; Input ; (1) ; @@ -517,39 +519,38 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; RA[8] ; Input ; (1) ; ; RA[9] ; Input ; (1) ; ; RA[10] ; Input ; (1) ; -; nIOSTRB ; Input ; (1) ; -; nIOSEL ; Input ; (1) ; -; nDEVSEL ; Input ; (1) ; -; C25M ; Input ; (0) ; ; RA[11] ; Input ; (1) ; ; RA[14] ; Input ; (1) ; ; RA[15] ; Input ; (1) ; ; RA[12] ; Input ; (1) ; ; RA[13] ; Input ; (1) ; +; SetFW[1] ; Input ; (1) ; ; nRES ; Input ; (1) ; +; SetFW[0] ; Input ; (1) ; ; MISO ; Input ; (1) ; +----------+----------+---------------+ -+------------------------------------------------------------------------------------------------------------------------------+ -; Control Signals ; -+-----------+-------------+---------+---------------------------------------+--------+----------------------+------------------+ -; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; -+-----------+-------------+---------+---------------------------------------+--------+----------------------+------------------+ -; C25M ; PIN_64 ; 103 ; Clock ; yes ; Global Clock ; GCLK3 ; -; Equal1~0 ; LC_X7_Y3_N5 ; 19 ; Clock enable ; no ; -- ; -- ; -; Equal22~1 ; LC_X6_Y4_N6 ; 8 ; Clock enable ; no ; -- ; -- ; -; MOSIOE ; LC_X4_Y1_N9 ; 1 ; Output enable ; no ; -- ; -- ; -; PHI0 ; PIN_41 ; 15 ; Clock ; yes ; Global Clock ; GCLK2 ; -; PS[0] ; LC_X6_Y4_N5 ; 52 ; Clock enable, Sync. clear, Sync. load ; no ; -- ; -- ; -; PS[2] ; LC_X7_Y3_N1 ; 29 ; Sync. clear, Sync. load ; no ; -- ; -- ; -; SDOE ; LC_X7_Y1_N5 ; 8 ; Output enable ; no ; -- ; -- ; -; always8~2 ; LC_X6_Y2_N5 ; 8 ; Sync. load ; no ; -- ; -- ; -; always8~3 ; LC_X6_Y2_N2 ; 9 ; Sync. load ; no ; -- ; -- ; -; always8~4 ; LC_X5_Y2_N4 ; 9 ; Sync. load ; no ; -- ; -- ; -; comb~2 ; LC_X5_Y2_N1 ; 9 ; Output enable ; no ; -- ; -- ; -; nRESr ; LC_X4_Y2_N9 ; 31 ; Async. clear, Sync. clear ; yes ; Global Clock ; GCLK1 ; -+-----------+-------------+---------+---------------------------------------+--------+----------------------+------------------+ ++-------------------------------------------------------------------------------------------------------------------------------+ +; Control Signals ; ++------------+-------------+---------+---------------------------------------+--------+----------------------+------------------+ +; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; ++------------+-------------+---------+---------------------------------------+--------+----------------------+------------------+ +; C25M ; PIN_64 ; 98 ; Clock ; yes ; Global Clock ; GCLK3 ; +; Equal0~0 ; LC_X3_Y3_N9 ; 20 ; Clock enable ; no ; -- ; -- ; +; Equal22~0 ; LC_X6_Y3_N7 ; 8 ; Clock enable ; no ; -- ; -- ; +; IOROMEN~0 ; LC_X3_Y3_N1 ; 2 ; Clock enable ; no ; -- ; -- ; +; IOROMRES~3 ; LC_X3_Y3_N3 ; 1 ; Async. clear ; no ; -- ; -- ; +; MOSIOE ; LC_X2_Y3_N6 ; 1 ; Output enable ; no ; -- ; -- ; +; PS[0] ; LC_X6_Y3_N1 ; 53 ; Clock enable, Sync. clear, Sync. load ; no ; -- ; -- ; +; PS[2] ; LC_X6_Y3_N0 ; 30 ; Sync. clear, Sync. load ; no ; -- ; -- ; +; SDOE ; LC_X5_Y1_N6 ; 8 ; Output enable ; no ; -- ; -- ; +; always7~3 ; LC_X4_Y4_N9 ; 8 ; Sync. load ; no ; -- ; -- ; +; always7~5 ; LC_X5_Y4_N6 ; 9 ; Sync. load ; no ; -- ; -- ; +; always7~7 ; LC_X5_Y4_N0 ; 9 ; Sync. load ; no ; -- ; -- ; +; comb~1 ; LC_X5_Y4_N5 ; 9 ; Output enable ; no ; -- ; -- ; +; nRESr ; LC_X3_Y3_N1 ; 30 ; Async. clear ; yes ; Global Clock ; GCLK2 ; ++------------+-------------+---------+---------------------------------------+--------+----------------------+------------------+ +-------------------------------------------------------------------------+ @@ -557,9 +558,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +-------+-------------+---------+----------------------+------------------+ ; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; +-------+-------------+---------+----------------------+------------------+ -; C25M ; PIN_64 ; 103 ; Global Clock ; GCLK3 ; -; PHI0 ; PIN_41 ; 15 ; Global Clock ; GCLK2 ; -; nRESr ; LC_X4_Y2_N9 ; 31 ; Global Clock ; GCLK1 ; +; C25M ; PIN_64 ; 98 ; Global Clock ; GCLK3 ; +; nRESr ; LC_X3_Y3_N1 ; 30 ; Global Clock ; GCLK2 ; +-------+-------------+---------+----------------------+------------------+ @@ -568,13 +568,13 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +-----------------------+--------------------+ ; Routing Resource Type ; Usage ; +-----------------------+--------------------+ -; C4s ; 224 / 784 ( 29 % ) ; -; Direct links ; 55 / 888 ( 6 % ) ; -; Global clocks ; 3 / 4 ( 75 % ) ; -; LAB clocks ; 14 / 32 ( 44 % ) ; -; LUT chains ; 32 / 216 ( 15 % ) ; -; Local interconnects ; 418 / 888 ( 47 % ) ; -; R4s ; 228 / 704 ( 32 % ) ; +; C4s ; 237 / 784 ( 30 % ) ; +; Direct links ; 70 / 888 ( 8 % ) ; +; Global clocks ; 2 / 4 ( 50 % ) ; +; LAB clocks ; 11 / 32 ( 34 % ) ; +; LUT chains ; 29 / 216 ( 13 % ) ; +; Local interconnects ; 463 / 888 ( 52 % ) ; +; R4s ; 257 / 704 ( 37 % ) ; +-----------------------+--------------------+ @@ -589,31 +589,30 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; 4 ; 0 ; ; 5 ; 0 ; ; 6 ; 0 ; -; 7 ; 0 ; -; 8 ; 1 ; -; 9 ; 2 ; -; 10 ; 21 ; +; 7 ; 1 ; +; 8 ; 0 ; +; 9 ; 1 ; +; 10 ; 22 ; +--------------------------------------------+------------------------------+ +-------------------------------------------------------------------+ ; LAB-wide Signals ; +------------------------------------+------------------------------+ -; LAB-wide Signals (Average = 1.88) ; Number of LABs (Total = 24) ; +; LAB-wide Signals (Average = 1.96) ; Number of LABs (Total = 24) ; +------------------------------------+------------------------------+ -; 1 Async. clear ; 5 ; -; 1 Clock ; 20 ; -; 1 Clock enable ; 5 ; -; 1 Sync. clear ; 7 ; -; 1 Sync. load ; 4 ; -; 2 Clocks ; 4 ; +; 1 Async. clear ; 6 ; +; 1 Clock ; 23 ; +; 1 Clock enable ; 8 ; +; 1 Sync. clear ; 5 ; +; 1 Sync. load ; 5 ; +------------------------------------+------------------------------+ +-----------------------------------------------------------------------------+ ; LAB Signals Sourced ; +----------------------------------------------+------------------------------+ -; Number of Signals Sourced (Average = 10.63) ; Number of LABs (Total = 24) ; +; Number of Signals Sourced (Average = 10.00) ; Number of LABs (Total = 24) ; +----------------------------------------------+------------------------------+ ; 0 ; 0 ; ; 1 ; 0 ; @@ -622,67 +621,66 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; 4 ; 0 ; ; 5 ; 0 ; ; 6 ; 0 ; -; 7 ; 0 ; -; 8 ; 1 ; -; 9 ; 2 ; -; 10 ; 14 ; +; 7 ; 1 ; +; 8 ; 0 ; +; 9 ; 1 ; +; 10 ; 19 ; ; 11 ; 2 ; -; 12 ; 2 ; -; 13 ; 1 ; -; 14 ; 1 ; -; 15 ; 0 ; -; 16 ; 1 ; +; 12 ; 1 ; +----------------------------------------------+------------------------------+ +--------------------------------------------------------------------------------+ ; LAB Signals Sourced Out ; +-------------------------------------------------+------------------------------+ -; Number of Signals Sourced Out (Average = 7.21) ; Number of LABs (Total = 24) ; +; Number of Signals Sourced Out (Average = 7.13) ; Number of LABs (Total = 24) ; +-------------------------------------------------+------------------------------+ ; 0 ; 0 ; ; 1 ; 0 ; ; 2 ; 0 ; -; 3 ; 2 ; -; 4 ; 1 ; +; 3 ; 1 ; +; 4 ; 3 ; ; 5 ; 3 ; -; 6 ; 2 ; -; 7 ; 3 ; -; 8 ; 5 ; -; 9 ; 5 ; -; 10 ; 3 ; +; 6 ; 4 ; +; 7 ; 1 ; +; 8 ; 3 ; +; 9 ; 4 ; +; 10 ; 5 ; +-------------------------------------------------+------------------------------+ +-----------------------------------------------------------------------------+ ; LAB Distinct Inputs ; +----------------------------------------------+------------------------------+ -; Number of Distinct Inputs (Average = 15.50) ; Number of LABs (Total = 24) ; +; Number of Distinct Inputs (Average = 16.83) ; Number of LABs (Total = 24) ; +----------------------------------------------+------------------------------+ ; 0 ; 0 ; ; 1 ; 0 ; ; 2 ; 0 ; ; 3 ; 0 ; -; 4 ; 1 ; -; 5 ; 0 ; -; 6 ; 0 ; -; 7 ; 1 ; +; 4 ; 0 ; +; 5 ; 1 ; +; 6 ; 1 ; +; 7 ; 0 ; ; 8 ; 0 ; -; 9 ; 0 ; -; 10 ; 1 ; -; 11 ; 1 ; -; 12 ; 0 ; -; 13 ; 4 ; -; 14 ; 4 ; -; 15 ; 0 ; -; 16 ; 2 ; -; 17 ; 2 ; -; 18 ; 0 ; -; 19 ; 2 ; -; 20 ; 2 ; -; 21 ; 1 ; -; 22 ; 2 ; -; 23 ; 1 ; +; 9 ; 1 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 3 ; +; 13 ; 1 ; +; 14 ; 3 ; +; 15 ; 1 ; +; 16 ; 1 ; +; 17 ; 1 ; +; 18 ; 1 ; +; 19 ; 1 ; +; 20 ; 0 ; +; 21 ; 2 ; +; 22 ; 1 ; +; 23 ; 3 ; +; 24 ; 1 ; +; 25 ; 1 ; +; 26 ; 1 ; +----------------------------------------------+------------------------------+ @@ -725,13 +723,10 @@ Info (332111): Found 2 clocks Info (332111): 978.000 PHI0 Info (186079): Completed User Assigned Global Signals Promotion Operation Info (186215): Automatically promoted signal "C25M" to use Global clock in PIN 64 File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 9 -Info (186216): Automatically promoted some destinations of signal "PHI0" to use Global clock File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 9 - Info (186217): Destination "comb~0" may be non-global or may not use global clock - Info (186217): Destination "PHI0r1" may be non-global or may not use global clock File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 10 -Info (186228): Pin "PHI0" drives global clock, but is not placed in a dedicated clock pin position File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 9 -Info (186216): Automatically promoted some destinations of signal "nRESr" to use Global clock File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 16 - Info (186217): Destination "IOROMEN" may be non-global or may not use global clock File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 88 - Info (186217): Destination "RestoreDone~0" may be non-global or may not use global clock File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 150 +Info (186216): Automatically promoted some destinations of signal "nRESr" to use Global clock File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 15 + Info (186217): Destination "IOROMEN" may be non-global or may not use global clock File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 90 + Info (186217): Destination "IOROMEN~0" may be non-global or may not use global clock File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 90 + Info (186217): Destination "REGEN" may be non-global or may not use global clock File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 85 Info (186079): Completed Auto Global Promotion Operation Info (176234): Starting register packing Info (186468): Started processing fast register assignments @@ -745,16 +740,16 @@ Info (170191): Fitter placement operations beginning Info (170137): Fitter placement was successful Info (170192): Fitter placement operations ending: elapsed time is 00:00:01 Info (170193): Fitter routing operations beginning -Info (170195): Router estimated average interconnect usage is 31% of the available device resources - Info (170196): Router estimated peak interconnect usage is 31% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5 -Info (170194): Fitter routing operations ending: elapsed time is 00:00:00 -Info (11888): Total time spent on timing analysis during the Fitter is 0.31 seconds. +Info (170195): Router estimated average interconnect usage is 33% of the available device resources + Info (170196): Router estimated peak interconnect usage is 33% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5 +Info (170194): Fitter routing operations ending: elapsed time is 00:00:01 +Info (11888): Total time spent on timing analysis during the Fitter is 0.29 seconds. Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00 Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'. Info (144001): Generated suppressed messages file Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg Info: Quartus Prime Fitter was successful. 0 errors, 3 warnings - Info: Peak virtual memory: 13733 megabytes - Info: Processing ended: Tue Mar 28 05:06:35 2023 + Info: Peak virtual memory: 13734 megabytes + Info: Processing ended: Tue Mar 28 12:29:24 2023 Info: Elapsed time: 00:00:03 Info: Total CPU time (on all processors): 00:00:04 diff --git a/cpld/output_files/GR8RAM.fit.summary b/cpld/output_files/GR8RAM.fit.summary index ac928d0..df31550 100755 --- a/cpld/output_files/GR8RAM.fit.summary +++ b/cpld/output_files/GR8RAM.fit.summary @@ -1,4 +1,4 @@ -Fitter Status : Successful - Tue Mar 28 05:06:35 2023 +Fitter Status : Successful - Tue Mar 28 12:29:24 2023 Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition Revision Name : GR8RAM Top-level Entity Name : GR8RAM diff --git a/cpld/output_files/GR8RAM.flow.rpt b/cpld/output_files/GR8RAM.flow.rpt index 13b17f9..9ddfa3d 100644 --- a/cpld/output_files/GR8RAM.flow.rpt +++ b/cpld/output_files/GR8RAM.flow.rpt @@ -1,5 +1,5 @@ Flow report for GR8RAM -Tue Mar 28 05:06:39 2023 +Tue Mar 28 12:29:28 2023 Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition @@ -41,7 +41,7 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------------+ ; Flow Summary ; +-----------------------+---------------------------------------------+ -; Flow Status ; Successful - Tue Mar 28 05:06:37 2023 ; +; Flow Status ; Successful - Tue Mar 28 12:29:26 2023 ; ; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; ; Revision Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ; @@ -60,7 +60,7 @@ https://fpgasoftware.intel.com/eula. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 03/28/2023 05:06:13 ; +; Start date & time ; 03/28/2023 12:29:02 ; ; Main task ; Compilation ; ; Revision Name ; GR8RAM ; +-------------------+---------------------+ @@ -76,7 +76,7 @@ https://fpgasoftware.intel.com/eula. ; ALM_REGISTER_PACKING_EFFORT ; High ; Medium ; -- ; -- ; ; AUTO_PACKED_REGISTERS_MAX ; Minimize Area ; Auto ; -- ; -- ; ; AUTO_RESOURCE_SHARING ; On ; Off ; -- ; -- ; -; COMPILER_SIGNATURE_ID ; 121381084694.167999437303928 ; -- ; -- ; -- ; +; COMPILER_SIGNATURE_ID ; 121381084694.168002094211928 ; -- ; -- ; -- ; ; FINAL_PLACEMENT_OPTIMIZATION ; Always ; Automatically ; -- ; -- ; ; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ; ; IOBANK_VCCIO ; -- (Not supported for targeted family) ; -- ; -- ; 1 ; @@ -103,11 +103,11 @@ https://fpgasoftware.intel.com/eula. +----------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:18 ; 1.0 ; 13094 MB ; 00:00:39 ; -; Fitter ; 00:00:03 ; 1.0 ; 13733 MB ; 00:00:04 ; -; Assembler ; 00:00:01 ; 1.0 ; 13053 MB ; 00:00:01 ; -; Timing Analyzer ; 00:00:01 ; 1.0 ; 13052 MB ; 00:00:01 ; -; Total ; 00:00:23 ; -- ; -- ; 00:00:45 ; +; Analysis & Synthesis ; 00:00:19 ; 1.0 ; 13095 MB ; 00:00:40 ; +; Fitter ; 00:00:03 ; 1.0 ; 13734 MB ; 00:00:04 ; +; Assembler ; 00:00:01 ; 1.0 ; 13055 MB ; 00:00:01 ; +; Timing Analyzer ; 00:00:01 ; 1.0 ; 13053 MB ; 00:00:01 ; +; Total ; 00:00:24 ; -- ; -- ; 00:00:46 ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ diff --git a/cpld/output_files/GR8RAM.map.rpt b/cpld/output_files/GR8RAM.map.rpt index b358e9c..dd46cf8 100644 --- a/cpld/output_files/GR8RAM.map.rpt +++ b/cpld/output_files/GR8RAM.map.rpt @@ -1,5 +1,5 @@ Analysis & Synthesis report for GR8RAM -Tue Mar 28 05:06:31 2023 +Tue Mar 28 12:29:20 2023 Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition @@ -46,12 +46,12 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +-----------------------------+---------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Tue Mar 28 05:06:31 2023 ; +; Analysis & Synthesis Status ; Successful - Tue Mar 28 12:29:20 2023 ; ; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; ; Revision Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ; ; Family ; MAX II ; -; Total logic elements ; 256 ; +; Total logic elements ; 241 ; ; Total pins ; 80 ; ; Total virtual pins ; 0 ; ; UFM blocks ; 0 / 1 ( 0 % ) ; @@ -159,33 +159,33 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------+-------+ ; Resource ; Usage ; +---------------------------------------------+-------+ -; Total logic elements ; 256 ; -; -- Combinational with no register ; 139 ; -; -- Register only ; 21 ; -; -- Combinational with a register ; 96 ; +; Total logic elements ; 241 ; +; -- Combinational with no register ; 143 ; +; -- Register only ; 6 ; +; -- Combinational with a register ; 92 ; ; ; ; ; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 137 ; -; -- 3 input functions ; 35 ; -; -- 2 input functions ; 63 ; -; -- 1 input functions ; 0 ; +; -- 4 input functions ; 136 ; +; -- 3 input functions ; 38 ; +; -- 2 input functions ; 60 ; +; -- 1 input functions ; 1 ; ; -- 0 input functions ; 0 ; ; ; ; ; Logic elements by mode ; ; -; -- normal mode ; 223 ; +; -- normal mode ; 208 ; ; -- arithmetic mode ; 33 ; ; -- qfbk mode ; 0 ; ; -- register cascade mode ; 0 ; ; -- synchronous clear/load mode ; 44 ; ; -- asynchronous clear/load mode ; 29 ; ; ; ; -; Total registers ; 117 ; +; Total registers ; 98 ; ; Total logic cells in carry chains ; 37 ; ; I/O pins ; 80 ; ; Maximum fan-out node ; C25M ; -; Maximum fan-out ; 103 ; -; Total fan-out ; 1104 ; -; Average fan-out ; 3.29 ; +; Maximum fan-out ; 98 ; +; Total fan-out ; 1074 ; +; Average fan-out ; 3.35 ; +---------------------------------------------+-------+ @@ -194,7 +194,7 @@ https://fpgasoftware.intel.com/eula. +----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+ ; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ; +----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+ -; |GR8RAM ; 256 (256) ; 117 ; 0 ; 80 ; 0 ; 139 (139) ; 21 (21) ; 96 (96) ; 37 (37) ; 0 (0) ; |GR8RAM ; GR8RAM ; work ; +; |GR8RAM ; 241 (241) ; 98 ; 0 ; 80 ; 0 ; 143 (143) ; 6 (6) ; 92 (92) ; 37 (37) ; 0 (0) ; |GR8RAM ; GR8RAM ; work ; +----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. @@ -219,7 +219,7 @@ Encoding Type: Minimal Bits +---------------------------------------+----------------------------------------+ ; Register name ; Reason for Removal ; +---------------------------------------+----------------------------------------+ -; SBA[0]~reg0 ; Stuck at GND due to stuck port data_in ; +; SA[12]~reg0 ; Stuck at GND due to stuck port data_in ; ; IS~10 ; Lost fanout ; ; Total Number of Removed Registers = 2 ; ; +---------------------------------------+----------------------------------------+ @@ -230,12 +230,12 @@ Encoding Type: Minimal Bits +----------------------------------------------+-------+ ; Statistic ; Value ; +----------------------------------------------+-------+ -; Total registers ; 117 ; +; Total registers ; 98 ; ; Number of registers using Synchronous Clear ; 11 ; ; Number of registers using Synchronous Load ; 33 ; ; Number of registers using Asynchronous Clear ; 29 ; ; Number of registers using Asynchronous Load ; 0 ; -; Number of registers using Clock Enable ; 22 ; +; Number of registers using Clock Enable ; 26 ; ; Number of registers using Preset ; 0 ; +----------------------------------------------+-------+ @@ -262,12 +262,14 @@ Encoding Type: Minimal Bits +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ ; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ -; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |GR8RAM|PS[2] ; -; 4:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |GR8RAM|SA[9]~reg0 ; -; 20:1 ; 6 bits ; 78 LEs ; 24 LEs ; 54 LEs ; Yes ; |GR8RAM|SA[8]~reg0 ; -; 20:1 ; 2 bits ; 26 LEs ; 12 LEs ; 14 LEs ; Yes ; |GR8RAM|SA[1]~reg0 ; +; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |GR8RAM|IOROMEN ; +; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |GR8RAM|PS[0] ; +; 5:1 ; 2 bits ; 6 LEs ; 2 LEs ; 4 LEs ; Yes ; |GR8RAM|SA[12]~reg0 ; +; 20:1 ; 6 bits ; 78 LEs ; 24 LEs ; 54 LEs ; Yes ; |GR8RAM|SA[5]~reg0 ; +; 20:1 ; 2 bits ; 26 LEs ; 12 LEs ; 14 LEs ; Yes ; |GR8RAM|SA[0]~reg0 ; ; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |GR8RAM|WRD[0] ; -; 5:1 ; 7 bits ; 21 LEs ; 14 LEs ; 7 LEs ; Yes ; |GR8RAM|RDD[0] ; +; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |GR8RAM|RDD[0] ; +; 5:1 ; 3 bits ; 9 LEs ; 6 LEs ; 3 LEs ; Yes ; |GR8RAM|RDD[4] ; ; 18:1 ; 2 bits ; 24 LEs ; 8 LEs ; 16 LEs ; Yes ; |GR8RAM|DQMH~reg0 ; ; 7:1 ; 5 bits ; 20 LEs ; 20 LEs ; 0 LEs ; No ; |GR8RAM|IS ; +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ @@ -279,43 +281,42 @@ Encoding Type: Minimal Bits Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition - Info: Processing started: Tue Mar 28 05:06:13 2023 + Info: Processing started: Tue Mar 28 12:29:01 2023 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected +Warning (10229): Verilog HDL Expression warning at GR8RAM.v(21): truncated literal to match 1 bits File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 21 Info (12021): Found 1 design units, including 1 entities, in source file gr8ram.v Info (12023): Found entity 1: GR8RAM File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 1 Info (12127): Elaborating entity "GR8RAM" for the top level hierarchy -Warning (10230): Verilog HDL assignment warning at GR8RAM.v(34): truncated value with size 32 to match size of target (4) File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 34 -Warning (10230): Verilog HDL assignment warning at GR8RAM.v(39): truncated value with size 32 to match size of target (14) File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 39 -Warning (10230): Verilog HDL assignment warning at GR8RAM.v(128): truncated value with size 32 to match size of target (8) File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 128 -Warning (10230): Verilog HDL assignment warning at GR8RAM.v(136): truncated value with size 32 to match size of target (8) File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 136 -Warning (10230): Verilog HDL assignment warning at GR8RAM.v(143): truncated value with size 32 to match size of target (8) File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 143 +Warning (10036): Verilog HDL or VHDL warning at GR8RAM.v(69): object "RAMSpecSELAny" assigned a value but never read File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 69 +Warning (10230): Verilog HDL assignment warning at GR8RAM.v(31): truncated value with size 32 to match size of target (4) File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 31 +Warning (10230): Verilog HDL assignment warning at GR8RAM.v(36): truncated value with size 32 to match size of target (14) File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 36 +Warning (10230): Verilog HDL assignment warning at GR8RAM.v(123): truncated value with size 32 to match size of target (8) File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 123 +Warning (10230): Verilog HDL assignment warning at GR8RAM.v(131): truncated value with size 32 to match size of target (8) File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 131 +Warning (10230): Verilog HDL assignment warning at GR8RAM.v(138): truncated value with size 32 to match size of target (8) File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 138 Info (17026): Resynthesizing 0 WYSIWYG logic cells and I/Os using "area" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched Warning (13024): Output pins are stuck at VCC or GND - Warning (13410): Pin "nNMIout" is stuck at VCC File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 559 - Warning (13410): Pin "nIRQout" is stuck at VCC File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 562 - Warning (13410): Pin "nRDYout" is stuck at VCC File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 561 - Warning (13410): Pin "nINHout" is stuck at VCC File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 560 - Warning (13410): Pin "RWout" is stuck at VCC File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 563 - Warning (13410): Pin "nDMAout" is stuck at VCC File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 558 - Warning (13410): Pin "RAdir" is stuck at VCC File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 557 - Warning (13410): Pin "SBA[0]" is stuck at GND File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 442 + Warning (13410): Pin "nNMIout" is stuck at VCC File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 556 + Warning (13410): Pin "nIRQout" is stuck at VCC File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 559 + Warning (13410): Pin "nRDYout" is stuck at VCC File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 558 + Warning (13410): Pin "nINHout" is stuck at VCC File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 557 + Warning (13410): Pin "RWout" is stuck at VCC File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 560 + Warning (13410): Pin "nDMAout" is stuck at VCC File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 555 + Warning (13410): Pin "RAdir" is stuck at VCC File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 554 + Warning (13410): Pin "SA[12]" is stuck at GND File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 439 Info (17049): 1 registers lost all their fanouts during netlist optimizations. -Warning (21074): Design contains 2 input pin(s) that do not drive logic - Warning (15610): No output dependent on input pin "SetFW[0]" File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 23 - Warning (15610): No output dependent on input pin "SetFW[1]" File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 23 -Info (21057): Implemented 336 device resources after synthesis - the final resource count might be different +Info (21057): Implemented 321 device resources after synthesis - the final resource count might be different Info (21058): Implemented 28 input pins Info (21059): Implemented 35 output pins Info (21060): Implemented 17 bidirectional pins - Info (21061): Implemented 256 logic cells + Info (21061): Implemented 241 logic cells Info (144001): Generated suppressed messages file Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg -Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 18 warnings - Info: Peak virtual memory: 13094 megabytes - Info: Processing ended: Tue Mar 28 05:06:31 2023 - Info: Elapsed time: 00:00:18 - Info: Total CPU time (on all processors): 00:00:39 +Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 17 warnings + Info: Peak virtual memory: 13095 megabytes + Info: Processing ended: Tue Mar 28 12:29:20 2023 + Info: Elapsed time: 00:00:19 + Info: Total CPU time (on all processors): 00:00:40 +------------------------------------------+ diff --git a/cpld/output_files/GR8RAM.map.smsg b/cpld/output_files/GR8RAM.map.smsg index c551f98..1c001f8 100755 --- a/cpld/output_files/GR8RAM.map.smsg +++ b/cpld/output_files/GR8RAM.map.smsg @@ -1,2 +1,2 @@ -Warning (10273): Verilog HDL warning at GR8RAM.v(104): extended using "x" or "z" File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 104 -Warning (10273): Verilog HDL warning at GR8RAM.v(281): extended using "x" or "z" File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 281 +Warning (10273): Verilog HDL warning at GR8RAM.v(99): extended using "x" or "z" File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 99 +Warning (10273): Verilog HDL warning at GR8RAM.v(278): extended using "x" or "z" File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 278 diff --git a/cpld/output_files/GR8RAM.map.summary b/cpld/output_files/GR8RAM.map.summary index 9859dd1..6d84c33 100755 --- a/cpld/output_files/GR8RAM.map.summary +++ b/cpld/output_files/GR8RAM.map.summary @@ -1,9 +1,9 @@ -Analysis & Synthesis Status : Successful - Tue Mar 28 05:06:31 2023 +Analysis & Synthesis Status : Successful - Tue Mar 28 12:29:20 2023 Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition Revision Name : GR8RAM Top-level Entity Name : GR8RAM Family : MAX II -Total logic elements : 256 +Total logic elements : 241 Total pins : 80 Total virtual pins : 0 UFM blocks : 0 / 1 ( 0 % ) diff --git a/cpld/output_files/GR8RAM.pof b/cpld/output_files/GR8RAM.pof index 46b446e..2257115 100755 Binary files a/cpld/output_files/GR8RAM.pof and b/cpld/output_files/GR8RAM.pof differ diff --git a/cpld/output_files/GR8RAM.sta.rpt b/cpld/output_files/GR8RAM.sta.rpt index a0539b9..12798bc 100644 --- a/cpld/output_files/GR8RAM.sta.rpt +++ b/cpld/output_files/GR8RAM.sta.rpt @@ -1,5 +1,5 @@ Timing Analyzer report for GR8RAM -Tue Mar 28 05:06:39 2023 +Tue Mar 28 12:29:28 2023 Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition @@ -80,11 +80,10 @@ https://fpgasoftware.intel.com/eula. ; Maximum allowed ; 4 ; ; ; ; ; Average used ; 1.00 ; -; Maximum used ; 2 ; +; Maximum used ; 1 ; ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; -; Processor 2 ; 0.2% ; +----------------------------+-------------+ @@ -93,7 +92,7 @@ https://fpgasoftware.intel.com/eula. +---------------+--------+--------------------------+ ; SDC File Path ; Status ; Read at ; +---------------+--------+--------------------------+ -; GR8RAM.sdc ; OK ; Tue Mar 28 05:06:39 2023 ; +; GR8RAM.sdc ; OK ; Tue Mar 28 12:29:28 2023 ; +---------------+--------+--------------------------+ @@ -112,7 +111,7 @@ https://fpgasoftware.intel.com/eula. +-----------+-----------------+------------+------+ ; Fmax ; Restricted Fmax ; Clock Name ; Note ; +-----------+-----------------+------------+------+ -; 66.42 MHz ; 66.42 MHz ; C25M ; ; +; 87.68 MHz ; 87.68 MHz ; C25M ; ; +-----------+-----------------+------------+------+ This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. @@ -122,7 +121,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +-------+--------+---------------+ -; C25M ; 12.472 ; 0.000 ; +; C25M ; 14.455 ; 0.000 ; +-------+--------+---------------+ @@ -131,7 +130,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +-------+-------+---------------+ -; C25M ; 1.383 ; 0.000 ; +; C25M ; 1.374 ; 0.000 ; +-------+-------+---------------+ @@ -140,7 +139,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +-------+--------+---------------+ -; C25M ; 33.331 ; 0.000 ; +; C25M ; 34.082 ; 0.000 ; +-------+--------+---------------+ @@ -149,7 +148,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +-------+-------+---------------+ -; C25M ; 6.115 ; 0.000 ; +; C25M ; 5.364 ; 0.000 ; +-------+-------+---------------+ @@ -159,7 +158,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp ; Clock ; Slack ; End Point TNS ; +-------+---------+---------------+ ; C25M ; 19.734 ; 0.000 ; -; PHI0 ; 488.734 ; 0.000 ; +; PHI0 ; 974.000 ; 0.000 ; +-------+---------+---------------+ @@ -168,106 +167,106 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +--------+----------------+----------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+----------------+----------------+--------------+-------------+--------------+------------+------------+ -; 12.472 ; REGEN ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.195 ; -; 12.473 ; REGEN ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.194 ; -; 12.485 ; REGEN ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.182 ; -; 12.571 ; REGEN ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.096 ; -; 12.858 ; REGEN ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.809 ; -; 12.946 ; REGEN ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.721 ; -; 12.947 ; REGEN ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.720 ; -; 13.462 ; PS[3] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.205 ; -; 13.543 ; PS[3] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.124 ; -; 13.543 ; PS[3] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.124 ; -; 13.543 ; PS[3] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.124 ; -; 13.649 ; PS[2] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.018 ; -; 13.668 ; Addr[3] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.999 ; -; 13.730 ; PS[2] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.937 ; -; 13.730 ; PS[2] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.937 ; -; 13.730 ; PS[2] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.937 ; -; 13.825 ; REGEN ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.842 ; -; 13.979 ; PS[1] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.688 ; -; 14.060 ; PS[1] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.607 ; -; 14.060 ; PS[1] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.607 ; -; 14.060 ; PS[1] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.607 ; -; 14.184 ; PS[3] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.483 ; -; 14.184 ; PS[3] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.483 ; -; 14.184 ; PS[3] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.483 ; -; 14.210 ; Addr[0] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.457 ; -; 14.328 ; PS[0] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.339 ; -; 14.366 ; Addr[2] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.301 ; -; 14.371 ; PS[2] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.296 ; -; 14.371 ; PS[2] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.296 ; -; 14.371 ; PS[2] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.296 ; -; 14.390 ; Addr[1] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.277 ; -; 14.409 ; PS[0] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.258 ; -; 14.409 ; PS[0] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.258 ; -; 14.409 ; PS[0] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.258 ; -; 14.445 ; Addr[4] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.222 ; -; 14.496 ; Addr[23] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.171 ; -; 14.622 ; PS[3] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.045 ; -; 14.701 ; PS[1] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.966 ; -; 14.701 ; PS[1] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.966 ; -; 14.701 ; PS[1] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.966 ; -; 14.707 ; Addr[8] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.960 ; -; 14.709 ; Addr[15] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.958 ; -; 14.809 ; PS[2] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.858 ; -; 15.050 ; PS[0] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.617 ; -; 15.050 ; PS[0] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.617 ; -; 15.050 ; PS[0] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.617 ; -; 15.061 ; Addr[5] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.606 ; -; 15.128 ; Addr[6] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.539 ; -; 15.139 ; PS[1] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.528 ; -; 15.199 ; Addr[10] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.468 ; -; 15.284 ; Addr[12] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.383 ; -; 15.322 ; Addr[7] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.345 ; -; 15.488 ; PS[0] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.179 ; -; 15.722 ; Addr[9] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.945 ; -; 16.006 ; Addr[16] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.661 ; -; 16.012 ; Addr[20] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.655 ; -; 16.089 ; Addr[22] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.578 ; -; 16.110 ; Addr[21] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.557 ; -; 16.112 ; Addr[14] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.555 ; -; 16.133 ; Addr[17] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.534 ; -; 16.142 ; Addr[13] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.525 ; -; 16.144 ; Addr[18] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.523 ; -; 16.144 ; Addr[19] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.523 ; -; 16.300 ; Addr[11] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.367 ; -; 27.034 ; IS.state_bit_0 ; SA[3]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 12.633 ; -; 27.416 ; IS.state_bit_0 ; SA[6]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 12.251 ; -; 27.568 ; Addr[23] ; SA[4]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 12.099 ; -; 27.654 ; REGEN ; SA[4]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 12.013 ; -; 27.717 ; Addr[23] ; SA[5]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.950 ; -; 27.803 ; REGEN ; SA[5]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.864 ; -; 27.841 ; IS.state_bit_1 ; SA[3]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.826 ; -; 28.219 ; Addr[23] ; SA[3]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.448 ; -; 28.223 ; IS.state_bit_1 ; SA[6]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.444 ; -; 28.238 ; LS[1] ; IS.state_bit_1 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.429 ; -; 28.251 ; Addr[23] ; SA[7]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.416 ; -; 28.266 ; Addr[23] ; SA[8]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.401 ; -; 28.305 ; REGEN ; SA[3]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.362 ; -; 28.337 ; REGEN ; SA[7]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.330 ; -; 28.352 ; REGEN ; SA[8]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.315 ; -; 28.419 ; IS.state_bit_0 ; SA[8]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.248 ; -; 28.423 ; IS.state_bit_0 ; SA[7]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.244 ; -; 28.431 ; LS[7] ; IS.state_bit_1 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.236 ; -; 28.447 ; LS[10] ; IS.state_bit_1 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.220 ; -; 28.462 ; LS[3] ; IS.state_bit_1 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.205 ; -; 28.464 ; LS[1] ; IS.state_bit_0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.203 ; -; 28.566 ; Addr[23] ; SA[6]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.101 ; -; 28.594 ; LS[9] ; IS.state_bit_1 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.073 ; -; 28.605 ; Addr[23] ; nRCS~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.062 ; -; 28.611 ; Addr[23] ; SA[0]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.056 ; -; 28.652 ; REGEN ; SA[6]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.015 ; -; 28.657 ; LS[7] ; IS.state_bit_0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.010 ; -; 28.673 ; LS[10] ; IS.state_bit_0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.994 ; -; 28.688 ; LS[3] ; IS.state_bit_0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.979 ; -; 28.691 ; REGEN ; nRCS~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.976 ; -; 28.696 ; Addr[23] ; RCKE~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.971 ; -; 28.697 ; REGEN ; SA[0]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.970 ; -; 28.720 ; Addr[23] ; SA[1]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.947 ; -; 28.782 ; REGEN ; RCKE~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.885 ; -; 28.784 ; LS[11] ; IS.state_bit_1 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.883 ; -; 28.806 ; REGEN ; SA[1]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.861 ; +; 14.455 ; PS[1] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.212 ; +; 14.456 ; PS[1] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.211 ; +; 14.456 ; PS[1] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.211 ; +; 14.456 ; PS[1] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.211 ; +; 14.549 ; PS[3] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.118 ; +; 14.550 ; PS[3] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.117 ; +; 14.550 ; PS[3] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.117 ; +; 14.550 ; PS[3] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.117 ; +; 14.596 ; PS[1] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.071 ; +; 14.690 ; PS[3] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.977 ; +; 14.774 ; PS[2] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.893 ; +; 14.775 ; PS[2] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.892 ; +; 14.775 ; PS[2] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.892 ; +; 14.775 ; PS[2] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.892 ; +; 14.915 ; PS[2] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.752 ; +; 15.094 ; Addr[11] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.573 ; +; 15.114 ; Addr[8] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.553 ; +; 15.114 ; PS[0] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.553 ; +; 15.115 ; PS[0] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.552 ; +; 15.115 ; PS[0] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.552 ; +; 15.115 ; PS[0] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.552 ; +; 15.156 ; PS[1] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.511 ; +; 15.156 ; PS[1] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.511 ; +; 15.185 ; Addr[23] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.482 ; +; 15.250 ; PS[3] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.417 ; +; 15.250 ; PS[3] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.417 ; +; 15.255 ; PS[0] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.412 ; +; 15.352 ; Addr[17] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.315 ; +; 15.365 ; Addr[15] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.302 ; +; 15.475 ; PS[2] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.192 ; +; 15.475 ; PS[2] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.192 ; +; 15.494 ; Addr[18] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.173 ; +; 15.532 ; Addr[21] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.135 ; +; 15.569 ; PS[1] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.098 ; +; 15.599 ; Addr[16] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.068 ; +; 15.646 ; Addr[12] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.021 ; +; 15.650 ; Addr[4] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.017 ; +; 15.659 ; Addr[19] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.008 ; +; 15.663 ; PS[3] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.004 ; +; 15.667 ; Addr[5] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.000 ; +; 15.684 ; Addr[2] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.983 ; +; 15.712 ; Addr[10] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.955 ; +; 15.720 ; Addr[3] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.947 ; +; 15.755 ; Addr[22] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.912 ; +; 15.779 ; Addr[20] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.888 ; +; 15.795 ; Addr[9] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.872 ; +; 15.815 ; PS[0] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.852 ; +; 15.815 ; PS[0] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.852 ; +; 15.888 ; PS[2] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.779 ; +; 16.002 ; Addr[6] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.665 ; +; 16.004 ; Addr[1] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.663 ; +; 16.098 ; Addr[0] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.569 ; +; 16.175 ; Addr[7] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.492 ; +; 16.228 ; PS[0] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.439 ; +; 16.304 ; Addr[14] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.363 ; +; 16.850 ; Addr[13] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 2.817 ; +; 28.595 ; IS.state_bit_0 ; SA[7]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.072 ; +; 28.644 ; IS.state_bit_0 ; SA[6]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.023 ; +; 28.780 ; IS.state_bit_0 ; SA[4]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.887 ; +; 28.904 ; IS.state_bit_0 ; SA[3]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.763 ; +; 29.057 ; IS.state_bit_0 ; SA[5]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.610 ; +; 29.188 ; Addr[23] ; SA[7]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.479 ; +; 29.237 ; Addr[23] ; SA[6]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.430 ; +; 29.317 ; IS.state_bit_0 ; SA[8]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.350 ; +; 29.332 ; IS.state_bit_1 ; SA[7]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.335 ; +; 29.373 ; Addr[23] ; SA[4]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.294 ; +; 29.381 ; IS.state_bit_1 ; SA[6]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.286 ; +; 29.492 ; Addr[23] ; SA[1]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.175 ; +; 29.497 ; Addr[23] ; SA[3]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.170 ; +; 29.517 ; IS.state_bit_1 ; SA[4]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.150 ; +; 29.544 ; LS[10] ; IS.state_bit_1 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.123 ; +; 29.640 ; Addr[23] ; RCKE~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.027 ; +; 29.641 ; IS.state_bit_1 ; SA[3]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.026 ; +; 29.650 ; Addr[23] ; SA[5]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.017 ; +; 29.673 ; LS[8] ; IS.state_bit_1 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.994 ; +; 29.740 ; REGEN ; SA[7]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.927 ; +; 29.764 ; LS[10] ; IS.state_bit_0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.903 ; +; 29.789 ; REGEN ; SA[6]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.878 ; +; 29.794 ; IS.state_bit_1 ; SA[5]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.873 ; +; 29.855 ; LS[11] ; IS.state_bit_1 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.812 ; +; 29.893 ; LS[8] ; IS.state_bit_0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.774 ; +; 29.910 ; Addr[23] ; SA[8]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.757 ; +; 29.925 ; REGEN ; SA[4]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.742 ; +; 30.044 ; REGEN ; SA[1]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.623 ; +; 30.049 ; REGEN ; SA[3]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.618 ; +; 30.054 ; IS.state_bit_1 ; SA[8]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.613 ; +; 30.075 ; LS[11] ; IS.state_bit_0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.592 ; +; 30.086 ; Addr[23] ; SA[0]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.581 ; +; 30.096 ; PS[3] ; SA[7]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.571 ; +; 30.145 ; PS[3] ; SA[6]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.522 ; +; 30.177 ; LS[6] ; IS.state_bit_1 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.490 ; +; 30.192 ; REGEN ; RCKE~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.475 ; +; 30.202 ; REGEN ; SA[5]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.465 ; +; 30.212 ; LS[9] ; IS.state_bit_1 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.455 ; +; 30.230 ; IS.state_bit_0 ; SA[1]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.437 ; +; 30.278 ; LS[10] ; IS.state_bit_2 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.389 ; +; 30.281 ; PS[3] ; SA[4]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.386 ; +; 30.336 ; PS[3] ; Addr[10] ; C25M ; C25M ; 40.000 ; 0.000 ; 9.331 ; +; 30.336 ; PS[3] ; Addr[11] ; C25M ; C25M ; 40.000 ; 0.000 ; 9.331 ; +; 30.336 ; PS[3] ; Addr[12] ; C25M ; C25M ; 40.000 ; 0.000 ; 9.331 ; +--------+----------------+----------------+--------------+-------------+--------------+------------+------------+ @@ -276,106 +275,106 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+----------------+----------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +-------+----------------+----------------+--------------+-------------+--------------+------------+------------+ -; 1.383 ; WRD[7] ; WRD[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.604 ; -; 1.384 ; WRD[6] ; WRD[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.605 ; -; 1.396 ; WRD[4] ; WRD[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.617 ; -; 1.412 ; nRESf[1] ; nRESf[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.633 ; -; 1.422 ; nRESf[2] ; nRESf[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.643 ; -; 1.652 ; WRD[1] ; WRD[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.873 ; -; 1.654 ; nRESf[3] ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 1.875 ; -; 1.667 ; nRESout~reg0 ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 1.888 ; -; 1.667 ; REGEN ; REGEN ; C25M ; C25M ; 0.000 ; 0.000 ; 1.888 ; -; 1.779 ; PS[1] ; PS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.000 ; -; 1.780 ; PS[1] ; nCAS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.001 ; -; 1.785 ; PS[1] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.006 ; -; 1.787 ; PS[1] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.008 ; -; 1.825 ; nRESf[0] ; nRESf[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.046 ; -; 1.880 ; WRD[0] ; WRD[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.101 ; -; 1.920 ; Addr[7] ; AddrIncM ; C25M ; C25M ; 0.000 ; 0.000 ; 2.141 ; -; 1.937 ; RestoreDone ; RestoreDone ; C25M ; C25M ; 0.000 ; 0.000 ; 2.158 ; -; 1.942 ; nRESf[1] ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 2.163 ; -; 1.961 ; PS[0] ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.182 ; -; 1.978 ; IS.state_bit_1 ; IS.state_bit_0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.199 ; -; 1.996 ; LS[0] ; LS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.217 ; -; 2.049 ; LS[13] ; LS[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.270 ; -; 2.108 ; Addr[15] ; Addr[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.329 ; -; 2.117 ; Addr[17] ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; -; 2.117 ; Addr[18] ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; -; 2.117 ; WRD[5] ; WRD[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; -; 2.125 ; Addr[16] ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.346 ; -; 2.126 ; Addr[23] ; Addr[23] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ; +; 1.374 ; WRD[6] ; WRD[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.595 ; +; 1.403 ; WRD[4] ; WRD[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.624 ; +; 1.413 ; WRD[2] ; WRD[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.634 ; +; 1.650 ; nRESout~reg0 ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 1.871 ; +; 1.699 ; PS[3] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.920 ; +; 1.854 ; WRD[0] ; WRD[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.075 ; +; 1.964 ; IS.state_bit_0 ; IS.state_bit_0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.185 ; +; 1.970 ; LS[0] ; LS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.191 ; +; 1.986 ; IS.state_bit_1 ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.207 ; +; 2.004 ; IS.state_bit_1 ; MOSIOE ; C25M ; C25M ; 0.000 ; 0.000 ; 2.225 ; +; 2.107 ; LS[6] ; LS[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.328 ; +; 2.108 ; Bank ; Bank ; C25M ; C25M ; 0.000 ; 0.000 ; 2.329 ; +; 2.117 ; Addr[1] ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; +; 2.117 ; Addr[2] ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; +; 2.118 ; WRD[5] ; WRD[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.339 ; +; 2.125 ; Addr[8] ; Addr[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.346 ; ; 2.126 ; Addr[10] ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ; -; 2.126 ; Addr[9] ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ; -; 2.128 ; LS[6] ; LS[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.349 ; -; 2.129 ; Addr[7] ; Addr[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.350 ; +; 2.126 ; Addr[15] ; Addr[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ; +; 2.126 ; Addr[17] ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ; +; 2.127 ; Addr[18] ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.348 ; +; 2.133 ; Addr[16] ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.354 ; ; 2.133 ; LS[7] ; LS[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.354 ; -; 2.133 ; IS.state_bit_2 ; MOSIOE ; C25M ; C25M ; 0.000 ; 0.000 ; 2.354 ; -; 2.134 ; Addr[1] ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.355 ; -; 2.136 ; IS.state_bit_2 ; nFCS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.357 ; -; 2.143 ; LS[9] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.364 ; -; 2.144 ; Addr[2] ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.365 ; +; 2.135 ; Addr[7] ; Addr[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.356 ; +; 2.136 ; Addr[9] ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.357 ; +; 2.142 ; Addr[0] ; Addr[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.363 ; ; 2.144 ; LS[4] ; LS[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.365 ; -; 2.144 ; LS[8] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.365 ; -; 2.148 ; RestoreDone ; Bank ; C25M ; C25M ; 0.000 ; 0.000 ; 2.369 ; -; 2.199 ; IS.state_bit_0 ; IS.state_bit_0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.420 ; -; 2.203 ; PS[2] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.424 ; -; 2.210 ; PS[2] ; MOSIout ; C25M ; C25M ; 0.000 ; 0.000 ; 2.431 ; -; 2.212 ; Addr[11] ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.433 ; -; 2.212 ; Addr[3] ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.433 ; -; 2.212 ; LS[5] ; LS[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.433 ; -; 2.213 ; PS[2] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.434 ; -; 2.214 ; IS.state_bit_0 ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.435 ; -; 2.221 ; Bank ; Bank ; C25M ; C25M ; 0.000 ; 0.000 ; 2.442 ; -; 2.221 ; Addr[13] ; Addr[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.442 ; -; 2.221 ; Addr[5] ; Addr[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.442 ; -; 2.222 ; PS[2] ; nCAS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.443 ; -; 2.222 ; Addr[14] ; Addr[14] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.443 ; -; 2.222 ; Addr[6] ; Addr[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.443 ; -; 2.230 ; LS[12] ; LS[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.451 ; +; 2.145 ; Addr[23] ; Addr[23] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.366 ; +; 2.151 ; LS[8] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.372 ; +; 2.153 ; LS[9] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.374 ; +; 2.172 ; PS[3] ; nRCS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.393 ; +; 2.211 ; IS.state_bit_1 ; nFCS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.432 ; +; 2.213 ; WRD[3] ; WRD[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.434 ; +; 2.221 ; Addr[19] ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.442 ; +; 2.230 ; Addr[13] ; Addr[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.451 ; ; 2.230 ; Addr[21] ; Addr[21] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.451 ; -; 2.231 ; Addr[19] ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; -; 2.231 ; Addr[20] ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; ; 2.231 ; Addr[22] ; Addr[22] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; -; 2.234 ; WRD[4] ; WRD[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.455 ; -; 2.237 ; AddrIncH ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.458 ; -; 2.239 ; LS[2] ; LS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.460 ; -; 2.240 ; LS[1] ; LS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.461 ; -; 2.241 ; LS[10] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.462 ; -; 2.241 ; LS[11] ; LS[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.462 ; -; 2.251 ; LS[3] ; LS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.472 ; -; 2.253 ; nRESf[2] ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 2.474 ; -; 2.262 ; IOROMEN ; IOROMEN ; C25M ; C25M ; 0.000 ; 0.000 ; 2.483 ; -; 2.276 ; PS[3] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.497 ; -; 2.283 ; PS[3] ; nCAS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.504 ; -; 2.290 ; WRD[2] ; WRD[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.511 ; -; 2.291 ; IS.state_bit_1 ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.512 ; -; 2.313 ; WRD[5] ; WRD[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.534 ; -; 2.364 ; PS[1] ; MOSIout ; C25M ; C25M ; 0.000 ; 0.000 ; 2.585 ; -; 2.370 ; WRD[1] ; WRD[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.591 ; -; 2.448 ; WRD[3] ; WRD[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.669 ; -; 2.508 ; Addr[12] ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.729 ; -; 2.542 ; Addr[4] ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.763 ; -; 2.547 ; LS[4] ; SA[3]~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.768 ; -; 2.554 ; WRD[2] ; WRD[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.775 ; -; 2.557 ; nRESf[0] ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 2.778 ; -; 2.582 ; PS[3] ; nRCS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.803 ; -; 2.595 ; Addr[0] ; Addr[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.816 ; -; 2.638 ; PHI0r1 ; PHI0r2 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.859 ; -; 2.652 ; IS.state_bit_0 ; MOSIOE ; C25M ; C25M ; 0.000 ; 0.000 ; 2.873 ; -; 2.655 ; IS.state_bit_0 ; nFCS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.876 ; -; 2.656 ; PHI0r2 ; RCKE~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.877 ; -; 2.676 ; PS[2] ; nRCS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.897 ; -; 2.719 ; LS[7] ; SA[6]~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.940 ; -; 2.720 ; WRD[0] ; WRD[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.941 ; -; 2.838 ; IS.state_bit_1 ; nFCS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.059 ; -; 2.848 ; IS.state_bit_1 ; MOSIOE ; C25M ; C25M ; 0.000 ; 0.000 ; 3.069 ; -; 2.928 ; Addr[14] ; SA[4]~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.149 ; -; 2.949 ; Addr[17] ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; -; 2.949 ; Addr[18] ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; -; 2.957 ; Addr[16] ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.178 ; -; 2.958 ; Addr[9] ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.179 ; +; 2.231 ; Addr[12] ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; +; 2.231 ; Addr[14] ; Addr[14] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; +; 2.231 ; Addr[20] ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; +; 2.232 ; Addr[11] ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.453 ; +; 2.232 ; Addr[3] ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.453 ; +; 2.233 ; LS[10] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.454 ; +; 2.239 ; RestoreDone ; RestoreDone ; C25M ; C25M ; 0.000 ; 0.000 ; 2.460 ; +; 2.248 ; LS[13] ; LS[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.469 ; +; 2.249 ; LS[3] ; LS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.470 ; +; 2.249 ; Addr[4] ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.470 ; +; 2.250 ; LS[1] ; LS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.471 ; +; 2.251 ; LS[5] ; LS[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.472 ; +; 2.256 ; WRD[2] ; WRD[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.477 ; +; 2.259 ; LS[12] ; LS[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.480 ; +; 2.260 ; LS[11] ; LS[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.481 ; +; 2.260 ; Addr[5] ; Addr[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.481 ; +; 2.262 ; Addr[6] ; Addr[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.483 ; +; 2.266 ; PS[1] ; PS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.487 ; +; 2.275 ; PS[1] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.496 ; +; 2.275 ; LS[2] ; LS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.496 ; +; 2.294 ; WRD[5] ; WRD[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.515 ; +; 2.422 ; WRD[7] ; WRD[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.643 ; +; 2.440 ; PS[3] ; RCKE~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.661 ; +; 2.525 ; WRD[1] ; WRD[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.746 ; +; 2.529 ; PHI0r2 ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.750 ; +; 2.581 ; WRD[3] ; WRD[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.802 ; +; 2.591 ; WRD[0] ; WRD[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.812 ; +; 2.616 ; PS[3] ; SA[2]~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.837 ; +; 2.634 ; AddrIncH ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.855 ; +; 2.653 ; AddrIncL ; Addr[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.874 ; +; 2.666 ; nRESr ; IOROMEN ; C25M ; C25M ; 0.000 ; 0.000 ; 2.887 ; +; 2.716 ; PS[0] ; RCKE~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.937 ; +; 2.736 ; PS[1] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.957 ; +; 2.936 ; Addr[7] ; AddrIncM ; C25M ; C25M ; 0.000 ; 0.000 ; 3.157 ; +; 2.949 ; Addr[1] ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; +; 2.949 ; Addr[2] ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; +; 2.957 ; Addr[8] ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.178 ; ; 2.958 ; Addr[10] ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.179 ; +; 2.958 ; Addr[17] ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.179 ; +; 2.959 ; Addr[18] ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.180 ; +; 2.965 ; Addr[16] ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.186 ; ; 2.965 ; LS[7] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.186 ; +; 2.968 ; Addr[9] ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.189 ; +; 2.974 ; Addr[0] ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.195 ; +; 2.976 ; LS[4] ; LS[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.197 ; +; 2.983 ; LS[8] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.204 ; +; 2.985 ; LS[9] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.206 ; +; 3.039 ; Bank ; nFCS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.260 ; +; 3.040 ; PHI0r1 ; PHI0r2 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.261 ; +; 3.041 ; PS[2] ; nCAS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.262 ; +; 3.060 ; Addr[2] ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ; +; 3.060 ; Addr[1] ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ; +; 3.067 ; PS[0] ; SA[2]~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.288 ; +; 3.068 ; Addr[8] ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.289 ; +; 3.069 ; Addr[10] ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.290 ; +; 3.069 ; Addr[17] ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.290 ; +; 3.070 ; Addr[18] ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.291 ; +; 3.076 ; Addr[16] ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.297 ; +; 3.076 ; LS[7] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.297 ; +; 3.079 ; Addr[9] ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.300 ; +; 3.085 ; Addr[0] ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.306 ; +; 3.087 ; LS[4] ; LS[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.308 ; +; 3.094 ; LS[8] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.315 ; +; 3.096 ; LS[9] ; LS[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.317 ; +-------+----------------+----------------+--------------+-------------+--------------+------------+------------+ @@ -384,35 +383,34 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +--------+-----------+----------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+-----------+----------+--------------+-------------+--------------+------------+------------+ -; 33.331 ; nRESr ; Addr[23] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.336 ; -; 33.331 ; nRESr ; Addr[0] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.336 ; -; 33.331 ; nRESr ; REGEN ; C25M ; C25M ; 40.000 ; 0.000 ; 6.336 ; -; 33.331 ; nRESr ; Addr[10] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.336 ; -; 33.331 ; nRESr ; Addr[1] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.336 ; -; 33.331 ; nRESr ; Addr[11] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.336 ; -; 33.331 ; nRESr ; Addr[2] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.336 ; -; 33.331 ; nRESr ; Addr[12] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.336 ; -; 33.331 ; nRESr ; Bank ; C25M ; C25M ; 40.000 ; 0.000 ; 6.336 ; -; 33.331 ; nRESr ; Addr[3] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.336 ; -; 33.331 ; nRESr ; Addr[13] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.336 ; -; 33.331 ; nRESr ; Addr[4] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.336 ; -; 33.331 ; nRESr ; Addr[14] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.336 ; -; 33.331 ; nRESr ; Addr[5] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.336 ; -; 33.331 ; nRESr ; Addr[15] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.336 ; -; 33.331 ; nRESr ; Addr[6] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.336 ; -; 33.331 ; nRESr ; Addr[16] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.336 ; -; 33.331 ; nRESr ; Addr[7] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.336 ; -; 33.331 ; nRESr ; Addr[17] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.336 ; -; 33.331 ; nRESr ; Addr[8] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.336 ; -; 33.331 ; nRESr ; Addr[18] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.336 ; -; 33.331 ; nRESr ; Addr[9] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.336 ; -; 33.331 ; nRESr ; Addr[19] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.336 ; -; 33.331 ; nRESr ; Addr[20] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.336 ; -; 33.331 ; nRESr ; Addr[21] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.336 ; -; 33.331 ; nRESr ; Addr[22] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.336 ; -; 33.331 ; nRESr ; AddrIncH ; C25M ; C25M ; 40.000 ; 0.000 ; 6.336 ; -; 33.331 ; nRESr ; AddrIncM ; C25M ; C25M ; 40.000 ; 0.000 ; 6.336 ; -; 33.331 ; nRESr ; AddrIncL ; C25M ; C25M ; 40.000 ; 0.000 ; 6.336 ; +; 34.082 ; nRESr ; Addr[0] ; C25M ; C25M ; 40.000 ; 0.000 ; 5.585 ; +; 34.082 ; nRESr ; Addr[23] ; C25M ; C25M ; 40.000 ; 0.000 ; 5.585 ; +; 34.082 ; nRESr ; Addr[22] ; C25M ; C25M ; 40.000 ; 0.000 ; 5.585 ; +; 34.082 ; nRESr ; Addr[10] ; C25M ; C25M ; 40.000 ; 0.000 ; 5.585 ; +; 34.082 ; nRESr ; Addr[1] ; C25M ; C25M ; 40.000 ; 0.000 ; 5.585 ; +; 34.082 ; nRESr ; Addr[11] ; C25M ; C25M ; 40.000 ; 0.000 ; 5.585 ; +; 34.082 ; nRESr ; Addr[2] ; C25M ; C25M ; 40.000 ; 0.000 ; 5.585 ; +; 34.082 ; nRESr ; Addr[12] ; C25M ; C25M ; 40.000 ; 0.000 ; 5.585 ; +; 34.082 ; nRESr ; Bank ; C25M ; C25M ; 40.000 ; 0.000 ; 5.585 ; +; 34.082 ; nRESr ; Addr[3] ; C25M ; C25M ; 40.000 ; 0.000 ; 5.585 ; +; 34.082 ; nRESr ; Addr[13] ; C25M ; C25M ; 40.000 ; 0.000 ; 5.585 ; +; 34.082 ; nRESr ; Addr[4] ; C25M ; C25M ; 40.000 ; 0.000 ; 5.585 ; +; 34.082 ; nRESr ; Addr[14] ; C25M ; C25M ; 40.000 ; 0.000 ; 5.585 ; +; 34.082 ; nRESr ; Addr[5] ; C25M ; C25M ; 40.000 ; 0.000 ; 5.585 ; +; 34.082 ; nRESr ; Addr[6] ; C25M ; C25M ; 40.000 ; 0.000 ; 5.585 ; +; 34.082 ; nRESr ; Addr[15] ; C25M ; C25M ; 40.000 ; 0.000 ; 5.585 ; +; 34.082 ; nRESr ; Addr[16] ; C25M ; C25M ; 40.000 ; 0.000 ; 5.585 ; +; 34.082 ; nRESr ; Addr[7] ; C25M ; C25M ; 40.000 ; 0.000 ; 5.585 ; +; 34.082 ; nRESr ; Addr[17] ; C25M ; C25M ; 40.000 ; 0.000 ; 5.585 ; +; 34.082 ; nRESr ; Addr[8] ; C25M ; C25M ; 40.000 ; 0.000 ; 5.585 ; +; 34.082 ; nRESr ; Addr[18] ; C25M ; C25M ; 40.000 ; 0.000 ; 5.585 ; +; 34.082 ; nRESr ; Addr[9] ; C25M ; C25M ; 40.000 ; 0.000 ; 5.585 ; +; 34.082 ; nRESr ; Addr[19] ; C25M ; C25M ; 40.000 ; 0.000 ; 5.585 ; +; 34.082 ; nRESr ; Addr[20] ; C25M ; C25M ; 40.000 ; 0.000 ; 5.585 ; +; 34.082 ; nRESr ; Addr[21] ; C25M ; C25M ; 40.000 ; 0.000 ; 5.585 ; +; 34.082 ; nRESr ; AddrIncH ; C25M ; C25M ; 40.000 ; 0.000 ; 5.585 ; +; 34.082 ; nRESr ; AddrIncM ; C25M ; C25M ; 40.000 ; 0.000 ; 5.585 ; +; 34.082 ; nRESr ; AddrIncL ; C25M ; C25M ; 40.000 ; 0.000 ; 5.585 ; +--------+-----------+----------+--------------+-------------+--------------+------------+------------+ @@ -421,57 +419,56 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+-----------+----------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +-------+-----------+----------+--------------+-------------+--------------+------------+------------+ -; 6.115 ; nRESr ; Addr[23] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.336 ; -; 6.115 ; nRESr ; Addr[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.336 ; -; 6.115 ; nRESr ; REGEN ; C25M ; C25M ; 0.000 ; 0.000 ; 6.336 ; -; 6.115 ; nRESr ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.336 ; -; 6.115 ; nRESr ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.336 ; -; 6.115 ; nRESr ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.336 ; -; 6.115 ; nRESr ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.336 ; -; 6.115 ; nRESr ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.336 ; -; 6.115 ; nRESr ; Bank ; C25M ; C25M ; 0.000 ; 0.000 ; 6.336 ; -; 6.115 ; nRESr ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.336 ; -; 6.115 ; nRESr ; Addr[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.336 ; -; 6.115 ; nRESr ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.336 ; -; 6.115 ; nRESr ; Addr[14] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.336 ; -; 6.115 ; nRESr ; Addr[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.336 ; -; 6.115 ; nRESr ; Addr[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.336 ; -; 6.115 ; nRESr ; Addr[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.336 ; -; 6.115 ; nRESr ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.336 ; -; 6.115 ; nRESr ; Addr[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.336 ; -; 6.115 ; nRESr ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.336 ; -; 6.115 ; nRESr ; Addr[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.336 ; -; 6.115 ; nRESr ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.336 ; -; 6.115 ; nRESr ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.336 ; -; 6.115 ; nRESr ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.336 ; -; 6.115 ; nRESr ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.336 ; -; 6.115 ; nRESr ; Addr[21] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.336 ; -; 6.115 ; nRESr ; Addr[22] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.336 ; -; 6.115 ; nRESr ; AddrIncH ; C25M ; C25M ; 0.000 ; 0.000 ; 6.336 ; -; 6.115 ; nRESr ; AddrIncM ; C25M ; C25M ; 0.000 ; 0.000 ; 6.336 ; -; 6.115 ; nRESr ; AddrIncL ; C25M ; C25M ; 0.000 ; 0.000 ; 6.336 ; +; 5.364 ; nRESr ; Addr[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.585 ; +; 5.364 ; nRESr ; Addr[23] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.585 ; +; 5.364 ; nRESr ; Addr[22] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.585 ; +; 5.364 ; nRESr ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.585 ; +; 5.364 ; nRESr ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.585 ; +; 5.364 ; nRESr ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.585 ; +; 5.364 ; nRESr ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.585 ; +; 5.364 ; nRESr ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.585 ; +; 5.364 ; nRESr ; Bank ; C25M ; C25M ; 0.000 ; 0.000 ; 5.585 ; +; 5.364 ; nRESr ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.585 ; +; 5.364 ; nRESr ; Addr[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.585 ; +; 5.364 ; nRESr ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.585 ; +; 5.364 ; nRESr ; Addr[14] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.585 ; +; 5.364 ; nRESr ; Addr[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.585 ; +; 5.364 ; nRESr ; Addr[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.585 ; +; 5.364 ; nRESr ; Addr[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.585 ; +; 5.364 ; nRESr ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.585 ; +; 5.364 ; nRESr ; Addr[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.585 ; +; 5.364 ; nRESr ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.585 ; +; 5.364 ; nRESr ; Addr[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.585 ; +; 5.364 ; nRESr ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.585 ; +; 5.364 ; nRESr ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.585 ; +; 5.364 ; nRESr ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.585 ; +; 5.364 ; nRESr ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.585 ; +; 5.364 ; nRESr ; Addr[21] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.585 ; +; 5.364 ; nRESr ; AddrIncH ; C25M ; C25M ; 0.000 ; 0.000 ; 5.585 ; +; 5.364 ; nRESr ; AddrIncM ; C25M ; C25M ; 0.000 ; 0.000 ; 5.585 ; +; 5.364 ; nRESr ; AddrIncL ; C25M ; C25M ; 0.000 ; 0.000 ; 5.585 ; +-------+-----------+----------+--------------+-------------+--------------+------------+------------+ -+-------------------------------------------------------------------------+ -; Setup Transfers ; -+------------+----------+------------+------------+------------+----------+ -; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; -+------------+----------+------------+------------+------------+----------+ -; C25M ; C25M ; 1405 ; 0 ; 95 ; 0 ; -; PHI0 ; C25M ; false path ; false path ; false path ; 0 ; -+------------+----------+------------+------------+------------+----------+ ++-----------------------------------------------------------------------+ +; Setup Transfers ; ++------------+----------+------------+------------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++------------+----------+------------+------------+----------+----------+ +; C25M ; C25M ; 1404 ; 0 ; 56 ; 0 ; +; PHI0 ; C25M ; false path ; false path ; 0 ; 0 ; ++------------+----------+------------+------------+----------+----------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. -+-------------------------------------------------------------------------+ -; Hold Transfers ; -+------------+----------+------------+------------+------------+----------+ -; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; -+------------+----------+------------+------------+------------+----------+ -; C25M ; C25M ; 1405 ; 0 ; 95 ; 0 ; -; PHI0 ; C25M ; false path ; false path ; false path ; 0 ; -+------------+----------+------------+------------+------------+----------+ ++-----------------------------------------------------------------------+ +; Hold Transfers ; ++------------+----------+------------+------------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++------------+----------+------------+------------+----------+----------+ +; C25M ; C25M ; 1404 ; 0 ; 56 ; 0 ; +; PHI0 ; C25M ; false path ; false path ; 0 ; 0 ; ++------------+----------+------------+------------+----------+----------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. @@ -480,7 +477,7 @@ Entries labeled "false path" only account for clock-to-clock false paths and not +------------+----------+----------+----------+----------+----------+ ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; +------------+----------+----------+----------+----------+----------+ -; C25M ; C25M ; 29 ; 0 ; 0 ; 0 ; +; C25M ; C25M ; 28 ; 0 ; 0 ; 0 ; +------------+----------+----------+----------+----------+----------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. @@ -490,7 +487,7 @@ Entries labeled "false path" only account for clock-to-clock false paths and not +------------+----------+----------+----------+----------+----------+ ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; +------------+----------+----------+----------+----------+----------+ -; C25M ; C25M ; 29 ; 0 ; 0 ; 0 ; +; C25M ; C25M ; 28 ; 0 ; 0 ; 0 ; +------------+----------+----------+----------+----------+----------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. @@ -514,10 +511,10 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi +---------------------------------+-------+------+ ; Illegal Clocks ; 0 ; 0 ; ; Unconstrained Clocks ; 0 ; 0 ; -; Unconstrained Input Ports ; 42 ; 42 ; -; Unconstrained Input Port Paths ; 251 ; 251 ; +; Unconstrained Input Ports ; 44 ; 44 ; +; Unconstrained Input Port Paths ; 906 ; 906 ; ; Unconstrained Output Ports ; 44 ; 44 ; -; Unconstrained Output Port Paths ; 214 ; 214 ; +; Unconstrained Output Port Paths ; 115 ; 115 ; +---------------------------------+-------+------+ @@ -573,6 +570,8 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi ; SD[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; SD[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; SD[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SetFW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SetFW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; nDEVSEL ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; nIOSEL ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; nIOSTRB ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; @@ -614,7 +613,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi ; SA[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; SA[10] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; SA[11] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; SA[12] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SBA[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; SBA[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; SD[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; SD[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; @@ -675,6 +674,8 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi ; SD[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; SD[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; SD[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SetFW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SetFW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; nDEVSEL ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; nIOSEL ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; nIOSTRB ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; @@ -716,7 +717,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi ; SA[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; SA[10] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; SA[11] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; SA[12] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SBA[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; SBA[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; SD[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; SD[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; @@ -741,7 +742,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi Info: ******************************************************************* Info: Running Quartus Prime Timing Analyzer Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition - Info: Processing started: Tue Mar 28 05:06:38 2023 + Info: Processing started: Tue Mar 28 12:29:27 2023 Info: Command: quartus_sta GR8RAM -c GR8RAM Info: qsta_default_script.tcl version: #1 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. @@ -753,33 +754,33 @@ Info (334004): Delay annotation completed successfully Info (332104): Reading SDC File: 'GR8RAM.sdc' Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON Info: Can't run Report Timing Closure Recommendations. The current device family is not supported. -Info (332146): Worst-case setup slack is 12.472 +Info (332146): Worst-case setup slack is 14.455 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): 12.472 0.000 C25M -Info (332146): Worst-case hold slack is 1.383 + Info (332119): 14.455 0.000 C25M +Info (332146): Worst-case hold slack is 1.374 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): 1.383 0.000 C25M -Info (332146): Worst-case recovery slack is 33.331 + Info (332119): 1.374 0.000 C25M +Info (332146): Worst-case recovery slack is 34.082 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): 33.331 0.000 C25M -Info (332146): Worst-case removal slack is 6.115 + Info (332119): 34.082 0.000 C25M +Info (332146): Worst-case removal slack is 5.364 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): 6.115 0.000 C25M + Info (332119): 5.364 0.000 C25M Info (332146): Worst-case minimum pulse width slack is 19.734 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 19.734 0.000 C25M - Info (332119): 488.734 0.000 PHI0 + Info (332119): 974.000 0.000 PHI0 Info (332001): The selected device family is not supported by the report_metastability command. Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements Info: Quartus Prime Timing Analyzer was successful. 0 errors, 1 warning - Info: Peak virtual memory: 13052 megabytes - Info: Processing ended: Tue Mar 28 05:06:39 2023 + Info: Peak virtual memory: 13053 megabytes + Info: Processing ended: Tue Mar 28 12:29:28 2023 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 diff --git a/cpld/output_files/GR8RAM.sta.summary b/cpld/output_files/GR8RAM.sta.summary index 4d1c4a1..2af454a 100644 --- a/cpld/output_files/GR8RAM.sta.summary +++ b/cpld/output_files/GR8RAM.sta.summary @@ -3,19 +3,19 @@ Timing Analyzer Summary ------------------------------------------------------------ Type : Setup 'C25M' -Slack : 12.472 +Slack : 14.455 TNS : 0.000 Type : Hold 'C25M' -Slack : 1.383 +Slack : 1.374 TNS : 0.000 Type : Recovery 'C25M' -Slack : 33.331 +Slack : 34.082 TNS : 0.000 Type : Removal 'C25M' -Slack : 6.115 +Slack : 5.364 TNS : 0.000 Type : Minimum Pulse Width 'C25M' @@ -23,7 +23,7 @@ Slack : 19.734 TNS : 0.000 Type : Minimum Pulse Width 'PHI0' -Slack : 488.734 +Slack : 974.000 TNS : 0.000 ------------------------------------------------------------