diff --git a/cpld/GR8RAM.qsf b/cpld/GR8RAM.qsf index 40fd6d4..189a496 100755 --- a/cpld/GR8RAM.qsf +++ b/cpld/GR8RAM.qsf @@ -149,7 +149,7 @@ set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to FCK set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to MOSI set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to MOSI set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to MISO -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to MISO +set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to MISO set_location_assignment PIN_21 -to nDMAout set_location_assignment PIN_19 -to RAdir set_location_assignment PIN_20 -to INTout @@ -161,4 +161,112 @@ set_location_assignment PIN_33 -to RWout set_location_assignment PIN_48 -to DMAin set_location_assignment PIN_49 -to INTin set_location_assignment PIN_17 -to RDdir -set_location_assignment PIN_18 -to DMAout \ No newline at end of file +set_location_assignment PIN_18 -to DMAout +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RA +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RA +set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RA +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RD +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RD +set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to RD +set_instance_assignment -name SLOW_SLEW_RATE OFF -to RD +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAdir +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to RAdir +set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RAdir +set_instance_assignment -name SLOW_SLEW_RATE ON -to RAdir +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RAdir +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RDdir +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to RDdir +set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RDdir +set_instance_assignment -name SLOW_SLEW_RATE ON -to RDdir +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RDdir +set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to PHI0 +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to PHI0 +set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to PHI0 +set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to nWE +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nWE +set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nWE +set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to nDEVSEL +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nDEVSEL +set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nDEVSEL +set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to nIOSEL +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nIOSEL +set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nIOSEL +set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to nIOSTRB +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nIOSTRB +set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nIOSTRB +set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to nRES +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nRES +set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nRES +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nRESout +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nRESout +set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nRESout +set_instance_assignment -name SLOW_SLEW_RATE ON -to nRESout +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRESout +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nFCS +set_instance_assignment -name SLOW_SLEW_RATE ON -to nFCS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nFCS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FCK +set_instance_assignment -name SLOW_SLEW_RATE ON -to FCK +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to FCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MOSI +set_instance_assignment -name SLOW_SLEW_RATE ON -to MOSI +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MOSI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MISO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to C25M +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to C25M +set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to C25M +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nRCS +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nRCS +set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nRCS +set_instance_assignment -name SLOW_SLEW_RATE ON -to nRCS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRCS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nRAS +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nRAS +set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nRAS +set_instance_assignment -name SLOW_SLEW_RATE ON -to nRAS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRAS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nCAS +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nCAS +set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nCAS +set_instance_assignment -name SLOW_SLEW_RATE ON -to nCAS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nCAS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nSWE +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nSWE +set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nSWE +set_instance_assignment -name SLOW_SLEW_RATE ON -to nSWE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSWE +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RCKE +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RCKE +set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RCKE +set_instance_assignment -name SLOW_SLEW_RATE ON -to RCKE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RCKE +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SBA +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SBA +set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SBA +set_instance_assignment -name SLOW_SLEW_RATE ON -to SBA +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SBA +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SA +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SA +set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SA +set_instance_assignment -name SLOW_SLEW_RATE ON -to SA +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SA +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQMH +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to DQMH +set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to DQMH +set_instance_assignment -name SLOW_SLEW_RATE ON -to DQMH +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to DQMH +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQML +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to DQML +set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to DQML +set_instance_assignment -name SLOW_SLEW_RATE ON -to DQML +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to DQML +set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to SetFW +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SetFW +set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SetFW +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SD +set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SD +set_instance_assignment -name SLOW_SLEW_RATE ON -to SD +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SD +set_global_assignment -name SDC_FILE GR8RAM.sdc \ No newline at end of file diff --git a/cpld/GR8RAM.qws b/cpld/GR8RAM.qws index 38d1f45..5bd6444 100755 Binary files a/cpld/GR8RAM.qws and b/cpld/GR8RAM.qws differ diff --git a/cpld/GR8RAM.sdc b/cpld/GR8RAM.sdc new file mode 100755 index 0000000..a7c9d8f --- /dev/null +++ b/cpld/GR8RAM.sdc @@ -0,0 +1,3 @@ +create_clock -period 40 [get_ports C25M] +create_clock -period 978 [get_ports PHI0] +set_clock_groups -asynchronous -group C25M -group PHI0 \ No newline at end of file diff --git a/cpld/GR8RAM.v b/cpld/GR8RAM.v index 83b5da3..41dd3b5 100644 --- a/cpld/GR8RAM.v +++ b/cpld/GR8RAM.v @@ -65,40 +65,41 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, /* Apple address bus */ input [15:0] RA; input nWE; + reg [11:0] RAr; reg nWEr; + reg CXXXr; + always @(posedge PHI0) begin + CXXXr <= RA[15:12]==4'hC; + RAr[11:0] <= RA[11:0]; + nWEr <= nWE; + end /* Apple select signals */ - wire ROMSpecRD = RA[15:12]==4'hC && RA[11:8]!=4'h0 && nWE && ((RA[11] && IOROMEN) || (~RA[11])); - wire REGSpecSEL = RA[15:12]==4'hC && RA[11:8]==4'h0 && RA[7] && REGEN; - wire BankSpecSEL = REGSpecSEL && RA[3:0]==4'hF; - wire RAMRegSpecSEL = REGSpecSEL && RA[3:0]==4'h3; + wire ROMSpecRD = CXXXr && RAr[11:8]!=4'h0 && nWEr && ((RAr[11] && IOROMEN) || (~RAr[11])); + wire REGSpecSEL = CXXXr && RAr[11:8]==4'h0 && RAr[7] && REGEN; + wire BankSpecSEL = REGSpecSEL && RAr[3:0]==4'hF; + wire RAMRegSpecSEL = REGSpecSEL && RAr[3:0]==4'h3; wire RAMSpecSEL = RAMRegSpecSEL && (~SetEN24bit || SetEN16MB || ~Addr[23]); - wire AddrHSpecSEL = REGSpecSEL && RA[3:0]==4'h2; - wire AddrMSpecSEL = REGSpecSEL && RA[3:0]==4'h1; - wire AddrLSpecSEL = REGSpecSEL && RA[3:0]==4'h0; - reg ROMSpecRDr, RAMSpecSELr, nWEr; + wire AddrHSpecSEL = REGSpecSEL && RAr[3:0]==4'h2; + wire AddrMSpecSEL = REGSpecSEL && RAr[3:0]==4'h1; + wire AddrLSpecSEL = REGSpecSEL && RAr[3:0]==4'h0; wire BankSEL = REGEN && ~nDEVSEL && BankSpecSEL; - wire RAMSEL = ~nDEVSEL && RAMSpecSELr; wire RAMRegSEL = ~nDEVSEL && RAMRegSpecSEL; + wire RAMSEL = ~nDEVSEL && RAMSpecSEL; wire RAMWR = RAMSEL && ~nWEr; wire AddrHSEL = REGEN && ~nDEVSEL && AddrHSpecSEL; wire AddrMSEL = REGEN && ~nDEVSEL && AddrMSpecSEL; wire AddrLSEL = REGEN && ~nDEVSEL && AddrLSpecSEL; - always @(posedge PHI0) begin - ROMSpecRDr <= ROMSpecRD; - RAMSpecSELr <= RAMSpecSEL; - nWEr <= nWE; - end /* IOROMEN and REGEN control */ reg IOROMEN = 0; reg REGEN = 0; reg nIOSTRBr; - wire IOROMRES = RA[10:0]==11'h7FF && ~nIOSTRB && ~nIOSTRBr; + wire IOROMRES = RAr[10:0]==11'h7FF && ~nIOSTRB && ~nIOSTRBr; always @(posedge C25M, negedge nRESr) begin if (~nRESr) REGEN <= 0; else if (PS==8 && ~nIOSEL) REGEN <= 1; end - always @(posedge C25M, negedge nRESr) begin + always @(posedge C25M) begin nIOSTRBr <= nIOSTRB; if (~nRESr) IOROMEN <= 0; else if (PS==8 && IOROMRES) IOROMEN <= 0; @@ -343,95 +344,95 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, always @(posedge C25M) begin case (PS[3:0]) 0: begin // NOP CKE / NOP CKD - RCKE <= PSStart; - nRCS <= 1'b1; - nRAS <= 1'b1; - nCAS <= 1'b1; - nSWE <= 1'b1; + RCKE <= PSStart && (IS==6 || (IS==7 && (ROMSpecRD || RAMSpecSEL))); + nRCS <= 1; + nRAS <= 1; + nCAS <= 1; + nSWE <= 1; SDOE <= 0; end 1: begin // ACT CKE / NOP CKD (ACT) - RCKE <= IS==6 || (IS==7 && (ROMSpecRDr || RAMSpecSELr)); - nRCS <= ~(IS==6 || (IS==7 && (ROMSpecRDr || RAMSpecSELr))); - nRAS <= 1'b0; - nCAS <= 1'b1; - nSWE <= 1'b1; + RCKE <= IS==6 || (IS==7 && (ROMSpecRD || RAMSpecSEL)); + nRCS <= ~(IS==6 || (IS==7 && (ROMSpecRD || RAMSpecSEL))); + nRAS <= 0; + nCAS <= 1; + nSWE <= 1; SDOE <= 0; end 2: begin // RD CKE / NOP CKD (RD) - RCKE <= IS==7 && nWEr && (ROMSpecRDr || RAMSpecSELr); - nRCS <= ~(IS==7 && nWEr && (ROMSpecRDr || RAMSpecSELr)); - nRAS <= 1'b1; - nCAS <= 1'b0; - nSWE <= 1'b1; + RCKE <= IS==7 && nWEr && (ROMSpecRD || RAMSpecSEL); + nRCS <= ~(IS==7 && nWEr && (ROMSpecRD || RAMSpecSEL)); + nRAS <= 1; + nCAS <= 0; + nSWE <= 1; SDOE <= 0; end 3: begin // NOP CKE / CKD - RCKE <= IS==7 && nWEr && (ROMSpecRDr || RAMSpecSELr); - nRCS <= 1'b1; - nRAS <= 1'b1; - nCAS <= 1'b1; - nSWE <= 1'b1; + RCKE <= IS==7 && nWEr && (ROMSpecRD || RAMSpecSEL); + nRCS <= 1; + nRAS <= 1; + nCAS <= 1; + nSWE <= 1; SDOE <= 0; end 4: begin // NOP CKD - RCKE <= 1'b0; - nRCS <= 1'b1; - nRAS <= 1'b1; - nCAS <= 1'b1; - nSWE <= 1'b1; + RCKE <= 0; + nRCS <= 1; + nRAS <= 1; + nCAS <= 1; + nSWE <= 1; SDOE <= 0; end 5: begin // NOP CKD - RCKE <= 1'b0; - nRCS <= 1'b1; - nRAS <= 1'b1; - nCAS <= 1'b1; - nSWE <= 1'b1; + RCKE <= 0; + nRCS <= 1; + nRAS <= 1; + nCAS <= 1; + nSWE <= 1; SDOE <= 0; end 6: begin // NOP CKD - RCKE <= 1'b0; - nRCS <= 1'b1; - nRAS <= 1'b1; - nCAS <= 1'b1; - nSWE <= 1'b1; + RCKE <= 0; + nRCS <= 1; + nRAS <= 1; + nCAS <= 1; + nSWE <= 1; SDOE <= 0; end 7: begin // NOP CKE / CKD RCKE <= IS==6 || (RAMWR && IS==7); - nRCS <= 1'b1; - nRAS <= 1'b1; - nCAS <= 1'b1; - nSWE <= 1'b1; + nRCS <= 1; + nRAS <= 1; + nCAS <= 1; + nSWE <= 1; SDOE <= 0; end 8: begin // WR AP CKE / NOP CKD (WR AP) RCKE <= IS==6 || (RAMWR && IS==7); nRCS <= ~(IS==6 || (RAMWR && IS==7)); - nRAS <= 1'b1; - nCAS <= 1'b0; - nSWE <= 1'b0; + nRAS <= 1; + nCAS <= 0; + nSWE <= 0; SDOE <= IS==6 || (RAMWR && IS==7); end 9: begin // NOP CKE / NOP CKD - RCKE <= 1'b1; - nRCS <= 1'b1; - nRAS <= 1'b1; - nCAS <= 1'b1; - nSWE <= 1'b1; + RCKE <= 1; + nRCS <= 1; + nRAS <= 1; + nCAS <= 1; + nSWE <= 1; SDOE <= 0; end 10: begin // PC all CKE / PC all CKD RCKE <= IS==1 || IS==4 || IS==5 || IS==6 || (IS==7 && RefReqd); - nRCS <= 1'b0; - nRAS <= 1'b0; - nCAS <= 1'b1; - nSWE <= 1'b0; + nRCS <= 0; + nRAS <= 0; + nCAS <= 1; + nSWE <= 0; SDOE <= 0; end 11: begin // LDM CKE / AREF CKE / NOP CKD RCKE <= IS==1 || IS==4 || IS==5 || IS==6 || (IS==7 && RefReqd); nRCS <= ~(IS==1 || IS==4 || IS==5 || IS==6 || (IS==7 && RefReqd)); - nRAS <= 1'b0; - nCAS <= 1'b0; + nRAS <= 0; + nCAS <= 0; nSWE <= ~(IS==1); SDOE <= 0; end default: begin // NOP CKD - RCKE <= 1'b0; - nRCS <= 1'b1; - nRAS <= 1'b1; - nCAS <= 1'b1; - nSWE <= 1'b1; + RCKE <= 0; + nRCS <= 1; + nRAS <= 1; + nCAS <= 1; + nSWE <= 1; SDOE <= 0; end endcase @@ -455,25 +456,25 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, if (IS==6) begin SBA[1:0] <= { 2'b10 }; SA[12:0] <= { 10'b0011000100, LS[12:10] }; - end else if (RAMSpecSELr) begin + end else if (RAMSpecSEL) begin SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 }; SA[12:10] <= SetEN24bit ? Addr[22:20] : 3'b000; SA[9:0] <= Addr[19:10]; end else begin SBA[1:0] <= 2'b10; - SA[12:0] <= { 10'b0011000100, Bank, RA[11:10] }; + SA[12:0] <= { 10'b0011000100, Bank, RAr[11:10] }; end end 2: begin // RD - if (RAMSpecSELr) begin + if (RAMSpecSEL) begin SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 }; SA[12:0] <= { 4'b0011, Addr[9:1] }; DQML <= Addr[0]; DQMH <= ~Addr[0]; end else begin SBA[1:0] <= 2'b10; - SA[12:0] <= { 4'b0011, RA[9:1]}; - DQML <= RA[0]; - DQMH <= ~RA[0]; + SA[12:0] <= { 4'b0011, RAr[9:1]}; + DQML <= RAr[0]; + DQMH <= ~RAr[0]; end end 3: begin // NOP CKE DQML <= 1'b1; diff --git a/cpld/db/GR8RAM.(0).cnf.cdb b/cpld/db/GR8RAM.(0).cnf.cdb index 2880c4f..df48fdf 100755 Binary files a/cpld/db/GR8RAM.(0).cnf.cdb and b/cpld/db/GR8RAM.(0).cnf.cdb differ diff --git a/cpld/db/GR8RAM.(0).cnf.hdb b/cpld/db/GR8RAM.(0).cnf.hdb index 47938f6..b8143a1 100755 Binary files a/cpld/db/GR8RAM.(0).cnf.hdb and b/cpld/db/GR8RAM.(0).cnf.hdb differ diff --git a/cpld/db/GR8RAM.ace_cmp.cdb b/cpld/db/GR8RAM.ace_cmp.cdb index edfb26a..54f6868 100755 Binary files a/cpld/db/GR8RAM.ace_cmp.cdb and b/cpld/db/GR8RAM.ace_cmp.cdb differ diff --git a/cpld/db/GR8RAM.ace_cmp.hdb b/cpld/db/GR8RAM.ace_cmp.hdb index 291e9e6..28a2850 100755 Binary files a/cpld/db/GR8RAM.ace_cmp.hdb and b/cpld/db/GR8RAM.ace_cmp.hdb differ diff --git a/cpld/db/GR8RAM.acvq.rdb b/cpld/db/GR8RAM.acvq.rdb new file mode 100755 index 0000000..f859694 Binary files /dev/null and b/cpld/db/GR8RAM.acvq.rdb differ diff --git a/cpld/db/GR8RAM.asm.qmsg b/cpld/db/GR8RAM.asm.qmsg index 06f5488..c4a660e 100755 --- a/cpld/db/GR8RAM.asm.qmsg +++ b/cpld/db/GR8RAM.asm.qmsg @@ -1,6 +1,6 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618906796813 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618906796829 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 04:19:56 2021 " "Processing started: Tue Apr 20 04:19:56 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618906796829 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1618906796829 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1618906796829 ""} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1618906798235 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1618906798282 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "293 " "Peak virtual memory: 293 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618906799032 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 04:19:59 2021 " "Processing ended: Tue Apr 20 04:19:59 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618906799032 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618906799032 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618906799032 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1618906799032 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1619049718988 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1619049719004 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 21 20:01:58 2021 " "Processing started: Wed Apr 21 20:01:58 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1619049719004 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1619049719004 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1619049719004 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1619049720098 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1619049720113 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "293 " "Peak virtual memory: 293 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1619049720738 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 21 20:02:00 2021 " "Processing ended: Wed Apr 21 20:02:00 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1619049720738 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1619049720738 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1619049720738 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1619049720738 ""} diff --git a/cpld/db/GR8RAM.asm.rdb b/cpld/db/GR8RAM.asm.rdb index 2dcb4e1..ee2394c 100755 Binary files a/cpld/db/GR8RAM.asm.rdb and b/cpld/db/GR8RAM.asm.rdb differ diff --git a/cpld/db/GR8RAM.asm_labs.ddb b/cpld/db/GR8RAM.asm_labs.ddb index 8480148..c735b7f 100755 Binary files a/cpld/db/GR8RAM.asm_labs.ddb and b/cpld/db/GR8RAM.asm_labs.ddb differ diff --git a/cpld/db/GR8RAM.cmp.cdb b/cpld/db/GR8RAM.cmp.cdb index f41e376..54f6868 100755 Binary files a/cpld/db/GR8RAM.cmp.cdb and b/cpld/db/GR8RAM.cmp.cdb differ diff --git a/cpld/db/GR8RAM.cmp.hdb b/cpld/db/GR8RAM.cmp.hdb index 70fb348..28a2850 100755 Binary files a/cpld/db/GR8RAM.cmp.hdb and b/cpld/db/GR8RAM.cmp.hdb differ diff --git a/cpld/db/GR8RAM.cmp.idb b/cpld/db/GR8RAM.cmp.idb index 0379a24..a8ef6ed 100755 Binary files a/cpld/db/GR8RAM.cmp.idb and b/cpld/db/GR8RAM.cmp.idb differ diff --git a/cpld/db/GR8RAM.cmp.rdb b/cpld/db/GR8RAM.cmp.rdb index 096f455..53ff59e 100755 Binary files a/cpld/db/GR8RAM.cmp.rdb and b/cpld/db/GR8RAM.cmp.rdb differ diff --git a/cpld/db/GR8RAM.cmp0.ddb b/cpld/db/GR8RAM.cmp0.ddb index 443cfd1..b10142e 100755 Binary files a/cpld/db/GR8RAM.cmp0.ddb and b/cpld/db/GR8RAM.cmp0.ddb differ diff --git a/cpld/db/GR8RAM.db_info b/cpld/db/GR8RAM.db_info index 0197121..794f74b 100755 --- a/cpld/db/GR8RAM.db_info +++ b/cpld/db/GR8RAM.db_info @@ -1,3 +1,3 @@ Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition Version_Index = 302049280 -Creation_Time = Mon Apr 19 05:50:25 2021 +Creation_Time = Wed Apr 21 17:47:44 2021 diff --git a/cpld/db/GR8RAM.eco.cdb b/cpld/db/GR8RAM.eco.cdb index bb73074..02ae7ea 100755 Binary files a/cpld/db/GR8RAM.eco.cdb and b/cpld/db/GR8RAM.eco.cdb differ diff --git a/cpld/db/GR8RAM.fit.qmsg b/cpld/db/GR8RAM.fit.qmsg index 5e214cc..19c79e5 100755 --- a/cpld/db/GR8RAM.fit.qmsg +++ b/cpld/db/GR8RAM.fit.qmsg @@ -1,39 +1,38 @@ -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1618906787984 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1618906788015 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618906788219 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618906788219 ""} -{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1618906788531 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1618906788562 ""} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618906788906 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618906788906 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618906788906 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618906788906 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618906788906 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1618906788906 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1618906789062 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1618906789062 ""} -{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1618906789078 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1618906789078 ""} -{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618906789078 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618906789078 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 C25M " " 1.000 C25M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618906789078 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI0 " " 1.000 PHI0" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618906789078 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1618906789078 ""} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618906789094 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618906789094 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618906789094 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618906789125 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI0 Global clock " "Automatically promoted some destinations of signal \"PHI0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~1 " "Destination \"comb~1\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618906789140 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI0r1 " "Destination \"PHI0r1\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618906789140 ""} } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618906789140 ""} -{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI0 " "Pin \"PHI0\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI0 } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "PHI0" } } } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 379 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1618906789140 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "nRESr Global clock " "Automatically promoted signal \"nRESr\" to use Global clock" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 16 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618906789140 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618906789140 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1618906789140 ""} -{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1618906789203 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1618906789265 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1618906789265 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1618906789281 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1618906789281 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618906789328 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1618906789531 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618906790203 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1618906790234 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1618906791859 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:02 " "Fitter placement operations ending: elapsed time is 00:00:02" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618906791859 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1618906791922 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "36 " "Router estimated average interconnect usage is 36% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "36 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 36% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 36% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 36% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1618906792469 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1618906792469 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618906793250 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.56 " "Total time spent on timing analysis during the Fitter is 0.56 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1618906793281 ""} -{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618906793281 ""} -{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1618906793344 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1618906793750 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "382 " "Peak virtual memory: 382 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618906794016 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 04:19:53 2021 " "Processing ended: Tue Apr 20 04:19:53 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618906794016 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618906794016 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618906794016 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1618906794016 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1619049711207 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1619049711222 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1619049711410 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1619049711410 ""} +{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1619049711800 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1619049711847 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1619049712238 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1619049712238 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1619049712238 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1619049712238 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1619049712238 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1619049712238 ""} +{ "Info" "ISTA_SDC_FOUND" "GR8RAM.sdc " "Reading SDC File: 'GR8RAM.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1619049712425 ""} +{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1619049712488 ""} +{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1619049712488 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1619049712488 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 40.000 C25M " " 40.000 C25M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1619049712488 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 978.000 PHI0 " " 978.000 PHI0" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1619049712488 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1619049712488 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1619049712504 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1619049712504 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1619049712519 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1619049712535 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI0 Global clock " "Automatically promoted some destinations of signal \"PHI0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~0 " "Destination \"comb~0\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1619049712535 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI0r1 " "Destination \"PHI0r1\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1619049712535 ""} } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1619049712535 ""} +{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI0 " "Pin \"PHI0\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI0 } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "PHI0" } } } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 418 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1619049712550 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nRESr Global clock " "Automatically promoted some destinations of signal \"nRESr\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "IOROMEN " "Destination \"IOROMEN\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 94 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1619049712550 ""} } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 16 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1619049712550 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1619049712550 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1619049712550 ""} +{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1619049712597 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1619049712691 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1619049712691 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1619049712691 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1619049712691 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619049712738 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1619049712972 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619049713347 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1619049713379 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1619049714550 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619049714566 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1619049714613 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "34 " "Router estimated average interconnect usage is 34% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "34 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1619049714972 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1619049714972 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619049715566 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.36 " "Total time spent on timing analysis during the Fitter is 0.36 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1619049715597 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619049715597 ""} +{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1619049715629 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1619049716238 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "383 " "Peak virtual memory: 383 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1619049716426 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 21 20:01:56 2021 " "Processing ended: Wed Apr 21 20:01:56 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1619049716426 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1619049716426 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1619049716426 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1619049716426 ""} diff --git a/cpld/db/GR8RAM.hier_info b/cpld/db/GR8RAM.hier_info index 053429c..554e4da 100755 --- a/cpld/db/GR8RAM.hier_info +++ b/cpld/db/GR8RAM.hier_info @@ -22,14 +22,6 @@ C25M => nCAS~reg0.CLK C25M => nRAS~reg0.CLK C25M => nRCS~reg0.CLK C25M => RCKE~reg0.CLK -C25M => RDD[0].CLK -C25M => RDD[1].CLK -C25M => RDD[2].CLK -C25M => RDD[3].CLK -C25M => RDD[4].CLK -C25M => RDD[5].CLK -C25M => RDD[6].CLK -C25M => RDD[7].CLK C25M => WRD[0].CLK C25M => WRD[1].CLK C25M => WRD[2].CLK @@ -71,8 +63,9 @@ C25M => Addr[20].CLK C25M => Addr[21].CLK C25M => Addr[22].CLK C25M => Addr[23].CLK -C25M => REGEN.CLK C25M => IOROMEN.CLK +C25M => nIOSTRBr.CLK +C25M => REGEN.CLK C25M => nRESout~reg0.CLK C25M => LS[0].CLK C25M => LS[1].CLK @@ -103,13 +96,31 @@ C25M => nRESf[3].CLK C25M => PHI0r2.CLK C25M => PHI0r1.CLK C25M => IS~7.DATAIN +C25M => RDD[0].CLK +C25M => RDD[1].CLK +C25M => RDD[2].CLK +C25M => RDD[3].CLK +C25M => RDD[4].CLK +C25M => RDD[5].CLK +C25M => RDD[6].CLK +C25M => RDD[7].CLK PHI0 => comb.IN1 PHI0 => nWEr.CLK -PHI0 => RAMSpecSELr.CLK -PHI0 => ROMSpecRDr.CLK +PHI0 => RAr[0].CLK +PHI0 => RAr[1].CLK +PHI0 => RAr[2].CLK +PHI0 => RAr[3].CLK +PHI0 => RAr[4].CLK +PHI0 => RAr[5].CLK +PHI0 => RAr[6].CLK +PHI0 => RAr[7].CLK +PHI0 => RAr[8].CLK +PHI0 => RAr[9].CLK +PHI0 => RAr[10].CLK +PHI0 => RAr[11].CLK +PHI0 => CXXXr.CLK PHI0 => PHI0r1.DATAIN nRES => nRESf[0].DATAIN -nRES => IOROMRES.IN1 nRESout <= nRESout~reg0.DB_MAX_OUTPUT_PORT_TYPE SetFW[0] => SetFWr[0].DATAIN SetFW[1] => SetFWr[1].DATAIN @@ -123,63 +134,34 @@ nRDYout <= nINHout <= RWout <= nDMAout <= -RA[0] => DQML.DATAA -RA[0] => Equal10.IN3 -RA[0] => Equal11.IN3 -RA[0] => Equal12.IN2 -RA[0] => Equal13.IN3 -RA[0] => Equal14.IN3 -RA[0] => Equal15.IN10 -RA[0] => DQMH.DATAA -RA[1] => SA.DATAA -RA[1] => Equal10.IN2 -RA[1] => Equal11.IN2 -RA[1] => Equal12.IN3 -RA[1] => Equal13.IN2 -RA[1] => Equal14.IN2 -RA[1] => Equal15.IN9 -RA[2] => SA.DATAA -RA[2] => Equal10.IN1 -RA[2] => Equal11.IN1 -RA[2] => Equal12.IN1 -RA[2] => Equal13.IN1 -RA[2] => Equal14.IN1 -RA[2] => Equal15.IN8 -RA[3] => SA.DATAA -RA[3] => Equal10.IN0 -RA[3] => Equal11.IN0 -RA[3] => Equal12.IN0 -RA[3] => Equal13.IN0 -RA[3] => Equal14.IN0 -RA[3] => Equal15.IN7 -RA[4] => SA.DATAA -RA[4] => Equal15.IN6 -RA[5] => SA.DATAA -RA[5] => Equal15.IN5 -RA[6] => SA.DATAA -RA[6] => Equal15.IN4 -RA[7] => comb.IN1 -RA[7] => SA.DATAA -RA[7] => Equal15.IN3 -RA[8] => SA.DATAA -RA[8] => Equal9.IN3 -RA[8] => Equal15.IN2 -RA[9] => SA.DATAA -RA[9] => Equal9.IN2 -RA[9] => Equal15.IN1 -RA[10] => SA.DATAA -RA[10] => Equal9.IN1 -RA[10] => Equal15.IN0 -RA[11] => comb.IN1 -RA[11] => SA.DATAA -RA[11] => comb.IN1 -RA[11] => Equal9.IN0 +RA[0] => RAr[0].DATAIN +RA[0] => Equal16.IN10 +RA[1] => RAr[1].DATAIN +RA[1] => Equal16.IN9 +RA[2] => RAr[2].DATAIN +RA[2] => Equal16.IN8 +RA[3] => RAr[3].DATAIN +RA[3] => Equal16.IN7 +RA[4] => RAr[4].DATAIN +RA[4] => Equal16.IN6 +RA[5] => RAr[5].DATAIN +RA[5] => Equal16.IN5 +RA[6] => RAr[6].DATAIN +RA[6] => Equal16.IN4 +RA[7] => RAr[7].DATAIN +RA[7] => Equal16.IN3 +RA[8] => RAr[8].DATAIN +RA[8] => Equal16.IN2 +RA[9] => RAr[9].DATAIN +RA[9] => Equal16.IN1 +RA[10] => RAr[10].DATAIN +RA[10] => Equal16.IN0 +RA[11] => RAr[11].DATAIN RA[12] => Equal8.IN1 RA[13] => Equal8.IN0 RA[14] => Equal8.IN3 RA[15] => Equal8.IN2 nWE => comb.IN1 -nWE => comb.IN1 nWE => nWEr.DATAIN RD[0] <> RD[0] RD[1] <> RD[1] @@ -197,6 +179,7 @@ nDEVSEL => comb.IN1 nDEVSEL => RAMSEL.IN1 nDEVSEL => comb.IN1 nDEVSEL => RAMRegSEL.IN1 +nIOSTRB => nIOSTRBr.DATAIN nIOSTRB => comb.IN1 nIOSTRB => comb.IN1 SBA[0] <= SBA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE diff --git a/cpld/db/GR8RAM.hif b/cpld/db/GR8RAM.hif index 40796d9..fe227ae 100755 Binary files a/cpld/db/GR8RAM.hif and b/cpld/db/GR8RAM.hif differ diff --git a/cpld/db/GR8RAM.map.cdb b/cpld/db/GR8RAM.map.cdb index e81467b..c10742a 100755 Binary files a/cpld/db/GR8RAM.map.cdb and b/cpld/db/GR8RAM.map.cdb differ diff --git a/cpld/db/GR8RAM.map.hdb b/cpld/db/GR8RAM.map.hdb index cbc9472..29410e8 100755 Binary files a/cpld/db/GR8RAM.map.hdb and b/cpld/db/GR8RAM.map.hdb differ diff --git a/cpld/db/GR8RAM.map.qmsg b/cpld/db/GR8RAM.map.qmsg index 3b9d01c..e5c244f 100755 --- a/cpld/db/GR8RAM.map.qmsg +++ b/cpld/db/GR8RAM.map.qmsg @@ -1,19 +1,19 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618906780187 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618906780202 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 04:19:39 2021 " "Processing started: Tue Apr 20 04:19:39 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618906780202 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618906780202 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618906780202 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1618906781718 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(106) " "Verilog HDL warning at GR8RAM.v(106): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 106 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618906781890 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(282) " "Verilog HDL warning at GR8RAM.v(282): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 282 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618906781890 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1618906781905 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1618906781905 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1618906782030 ""} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(42) " "Verilog HDL assignment warning at GR8RAM.v(42): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 42 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618906782062 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(47) " "Verilog HDL assignment warning at GR8RAM.v(47): truncated value with size 32 to match size of target (14)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 47 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618906782062 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(130) " "Verilog HDL assignment warning at GR8RAM.v(130): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 130 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618906782062 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(138) " "Verilog HDL assignment warning at GR8RAM.v(138): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 138 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618906782062 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(145) " "Verilog HDL assignment warning at GR8RAM.v(145): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 145 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618906782062 "|GR8RAM"} -{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 -1 1618906783140 ""} -{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "nNMIout VCC " "Pin \"nNMIout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 553 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618906783406 "|GR8RAM|nNMIout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nIRQout VCC " "Pin \"nIRQout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 556 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618906783406 "|GR8RAM|nIRQout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nRDYout VCC " "Pin \"nRDYout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 555 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618906783406 "|GR8RAM|nRDYout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nINHout VCC " "Pin \"nINHout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 554 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618906783406 "|GR8RAM|nINHout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RWout VCC " "Pin \"RWout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 557 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618906783406 "|GR8RAM|RWout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nDMAout VCC " "Pin \"nDMAout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 552 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618906783406 "|GR8RAM|nDMAout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 551 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618906783406 "|GR8RAM|RAdir"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1618906783406 ""} -{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1618906783906 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "321 " "Implemented 321 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "28 " "Implemented 28 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1618906783968 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1618906783968 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1618906783968 ""} { "Info" "ICUT_CUT_TM_LCELLS" "241 " "Implemented 241 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1618906783968 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1618906783968 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1618906784124 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 13 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 13 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "301 " "Peak virtual memory: 301 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618906784281 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 04:19:44 2021 " "Processing ended: Tue Apr 20 04:19:44 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618906784281 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618906784281 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618906784281 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618906784281 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1619049702769 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1619049702769 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 21 20:01:42 2021 " "Processing started: Wed Apr 21 20:01:42 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1619049702769 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1619049702769 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1619049702769 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1619049704488 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(110) " "Verilog HDL warning at GR8RAM.v(110): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 110 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1619049704706 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(286) " "Verilog HDL warning at GR8RAM.v(286): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 286 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1619049704706 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1619049704722 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1619049704722 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1619049704878 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(42) " "Verilog HDL assignment warning at GR8RAM.v(42): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 42 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1619049704894 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(47) " "Verilog HDL assignment warning at GR8RAM.v(47): truncated value with size 32 to match size of target (14)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 47 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1619049704894 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(134) " "Verilog HDL assignment warning at GR8RAM.v(134): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 134 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1619049704894 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(142) " "Verilog HDL assignment warning at GR8RAM.v(142): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 142 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1619049704894 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(149) " "Verilog HDL assignment warning at GR8RAM.v(149): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 149 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1619049704894 "|GR8RAM"} +{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 -1 1619049706253 ""} +{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "nNMIout VCC " "Pin \"nNMIout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 563 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1619049706628 "|GR8RAM|nNMIout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nIRQout VCC " "Pin \"nIRQout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 566 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1619049706628 "|GR8RAM|nIRQout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nRDYout VCC " "Pin \"nRDYout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 565 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1619049706628 "|GR8RAM|nRDYout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nINHout VCC " "Pin \"nINHout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 564 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1619049706628 "|GR8RAM|nINHout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RWout VCC " "Pin \"RWout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 567 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1619049706628 "|GR8RAM|RWout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nDMAout VCC " "Pin \"nDMAout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 562 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1619049706628 "|GR8RAM|nDMAout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 561 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1619049706628 "|GR8RAM|RAdir"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1619049706628 ""} +{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1619049707050 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "337 " "Implemented 337 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "28 " "Implemented 28 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1619049707081 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1619049707081 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1619049707081 ""} { "Info" "ICUT_CUT_TM_LCELLS" "257 " "Implemented 257 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1619049707081 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1619049707081 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1619049707285 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 13 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 13 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "301 " "Peak virtual memory: 301 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1619049707456 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 21 20:01:47 2021 " "Processing ended: Wed Apr 21 20:01:47 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1619049707456 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1619049707456 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1619049707456 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1619049707456 ""} diff --git a/cpld/db/GR8RAM.map.rdb b/cpld/db/GR8RAM.map.rdb index 470a060..b9f3c94 100755 Binary files a/cpld/db/GR8RAM.map.rdb and b/cpld/db/GR8RAM.map.rdb differ diff --git a/cpld/db/GR8RAM.pplq.rdb b/cpld/db/GR8RAM.pplq.rdb index 723fcab..6619eee 100755 Binary files a/cpld/db/GR8RAM.pplq.rdb and b/cpld/db/GR8RAM.pplq.rdb differ diff --git a/cpld/db/GR8RAM.pre_map.hdb b/cpld/db/GR8RAM.pre_map.hdb index f432588..06c3bda 100755 Binary files a/cpld/db/GR8RAM.pre_map.hdb and b/cpld/db/GR8RAM.pre_map.hdb differ diff --git a/cpld/db/GR8RAM.root_partition.map.reg_db.cdb b/cpld/db/GR8RAM.root_partition.map.reg_db.cdb index 01bfaa7..7a9ca5b 100755 Binary files a/cpld/db/GR8RAM.root_partition.map.reg_db.cdb and b/cpld/db/GR8RAM.root_partition.map.reg_db.cdb differ diff --git a/cpld/db/GR8RAM.routing.rdb b/cpld/db/GR8RAM.routing.rdb index 7b34f68..74003ce 100755 Binary files a/cpld/db/GR8RAM.routing.rdb and b/cpld/db/GR8RAM.routing.rdb differ diff --git a/cpld/db/GR8RAM.rtlv.hdb b/cpld/db/GR8RAM.rtlv.hdb index a6820cf..a31202c 100755 Binary files a/cpld/db/GR8RAM.rtlv.hdb and b/cpld/db/GR8RAM.rtlv.hdb differ diff --git a/cpld/db/GR8RAM.rtlv_sg.cdb b/cpld/db/GR8RAM.rtlv_sg.cdb index 272dde8..4c057ce 100755 Binary files a/cpld/db/GR8RAM.rtlv_sg.cdb and b/cpld/db/GR8RAM.rtlv_sg.cdb differ diff --git a/cpld/db/GR8RAM.sgdiff.cdb b/cpld/db/GR8RAM.sgdiff.cdb index 7d0bd18..b17e2b8 100755 Binary files a/cpld/db/GR8RAM.sgdiff.cdb and b/cpld/db/GR8RAM.sgdiff.cdb differ diff --git a/cpld/db/GR8RAM.sgdiff.hdb b/cpld/db/GR8RAM.sgdiff.hdb index 58f1cf6..34c2115 100755 Binary files a/cpld/db/GR8RAM.sgdiff.hdb and b/cpld/db/GR8RAM.sgdiff.hdb differ diff --git a/cpld/db/GR8RAM.sta.qmsg b/cpld/db/GR8RAM.sta.qmsg index 38a0971..b2e5e88 100755 --- a/cpld/db/GR8RAM.sta.qmsg +++ b/cpld/db/GR8RAM.sta.qmsg @@ -1,23 +1,20 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618906802095 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618906802110 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 04:20:00 2021 " "Processing started: Tue Apr 20 04:20:00 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618906802110 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618906802110 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618906802110 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1618906802314 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1618906803173 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618906803329 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618906803329 ""} -{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1618906803517 ""} -{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1618906804204 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1618906804392 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1618906804407 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C25M C25M " "create_clock -period 1.000 -name C25M C25M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804407 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI0 PHI0 " "create_clock -period 1.000 -name PHI0 PHI0" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804407 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804407 ""} -{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1618906804423 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1618906804595 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -9.005 " "Worst-case setup slack is -9.005" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804611 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804611 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.005 -699.357 C25M " " -9.005 -699.357 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804611 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.425 -0.425 PHI0 " " -0.425 -0.425 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804611 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618906804611 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.248 " "Worst-case hold slack is -0.248" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804642 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804642 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.248 -0.248 PHI0 " " -0.248 -0.248 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804642 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.400 0.000 C25M " " 1.400 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804642 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618906804642 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -4.412 " "Worst-case recovery slack is -4.412" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804657 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804657 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.412 -127.948 C25M " " -4.412 -127.948 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804657 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618906804657 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "removal 4.858 " "Worst-case removal slack is 4.858" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804673 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804673 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.858 0.000 C25M " " 4.858 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804673 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618906804673 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.289 " "Worst-case minimum pulse width slack is -2.289" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804673 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804673 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 C25M " " -2.289 -2.289 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804673 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI0 " " -2.289 -2.289 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804673 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618906804673 ""} -{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1618906804876 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618906804986 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618906804986 ""} -{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "278 " "Peak virtual memory: 278 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618906805220 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 04:20:05 2021 " "Processing ended: Tue Apr 20 04:20:05 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618906805220 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618906805220 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618906805220 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618906805220 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1619049723504 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1619049723520 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 21 20:02:02 2021 " "Processing started: Wed Apr 21 20:02:02 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1619049723520 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1619049723520 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1619049723520 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1619049723692 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1619049724707 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1619049724910 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1619049724910 ""} +{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1619049725098 ""} +{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1619049726082 ""} +{ "Info" "ISTA_SDC_FOUND" "GR8RAM.sdc " "Reading SDC File: 'GR8RAM.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1619049726254 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1619049726348 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup 12.419 " "Worst-case setup slack is 12.419" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049726551 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049726551 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 12.419 0.000 C25M " " 12.419 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049726551 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1619049726551 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.393 " "Worst-case hold slack is 1.393" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049726567 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049726567 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.393 0.000 C25M " " 1.393 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049726567 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1619049726567 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 33.300 " "Worst-case recovery slack is 33.300" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049726567 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049726567 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 33.300 0.000 C25M " " 33.300 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049726567 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1619049726567 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "removal 6.146 " "Worst-case removal slack is 6.146" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049726582 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049726582 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 6.146 0.000 C25M " " 6.146 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049726582 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1619049726582 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 19.734 " "Worst-case minimum pulse width slack is 19.734" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049726582 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049726582 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.734 0.000 C25M " " 19.734 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049726582 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 488.734 0.000 PHI0 " " 488.734 0.000 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049726582 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1619049726582 ""} +{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1619049726739 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1619049726989 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1619049726989 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "278 " "Peak virtual memory: 278 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1619049727395 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 21 20:02:07 2021 " "Processing ended: Wed Apr 21 20:02:07 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1619049727395 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1619049727395 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1619049727395 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1619049727395 ""} diff --git a/cpld/db/GR8RAM.sta.rdb b/cpld/db/GR8RAM.sta.rdb index 3578a35..70a5c98 100755 Binary files a/cpld/db/GR8RAM.sta.rdb and b/cpld/db/GR8RAM.sta.rdb differ diff --git a/cpld/db/GR8RAM.sta_cmp.5_slow.tdb b/cpld/db/GR8RAM.sta_cmp.5_slow.tdb index 905feea..f8378e8 100755 Binary files a/cpld/db/GR8RAM.sta_cmp.5_slow.tdb and b/cpld/db/GR8RAM.sta_cmp.5_slow.tdb differ diff --git a/cpld/db/GR8RAM.tmw_info b/cpld/db/GR8RAM.tmw_info index 51a8f52..6ca838b 100755 --- a/cpld/db/GR8RAM.tmw_info +++ b/cpld/db/GR8RAM.tmw_info @@ -1,6 +1,6 @@ start_full_compilation:s:00:00:28 start_analysis_synthesis:s:00:00:07-start_full_compilation start_analysis_elaboration:s-start_full_compilation -start_fitter:s:00:00:10-start_full_compilation +start_fitter:s:00:00:09-start_full_compilation start_assembler:s:00:00:04-start_full_compilation -start_timing_analyzer:s:00:00:07-start_full_compilation +start_timing_analyzer:s:00:00:08-start_full_compilation diff --git a/cpld/db/GR8RAM.vpr.ammdb b/cpld/db/GR8RAM.vpr.ammdb index c0ccc6d..03a3d4d 100755 Binary files a/cpld/db/GR8RAM.vpr.ammdb and b/cpld/db/GR8RAM.vpr.ammdb differ diff --git a/cpld/db/logic_util_heursitic.dat b/cpld/db/logic_util_heursitic.dat index 8fab785..a673eab 100755 Binary files a/cpld/db/logic_util_heursitic.dat and b/cpld/db/logic_util_heursitic.dat differ diff --git a/cpld/db/prev_cmp_GR8RAM.qmsg b/cpld/db/prev_cmp_GR8RAM.qmsg index 857f1ce..a48d744 100755 --- a/cpld/db/prev_cmp_GR8RAM.qmsg +++ b/cpld/db/prev_cmp_GR8RAM.qmsg @@ -1,95 +1,91 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618906713072 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618906713088 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 04:18:32 2021 " "Processing started: Tue Apr 20 04:18:32 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618906713088 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618906713088 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618906713088 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1618906714666 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(106) " "Verilog HDL warning at GR8RAM.v(106): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 106 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618906714838 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(282) " "Verilog HDL warning at GR8RAM.v(282): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 282 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618906714854 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1618906714854 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1618906714854 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1618906714979 ""} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(42) " "Verilog HDL assignment warning at GR8RAM.v(42): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 42 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618906714979 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(47) " "Verilog HDL assignment warning at GR8RAM.v(47): truncated value with size 32 to match size of target (14)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 47 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618906714979 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(130) " "Verilog HDL assignment warning at GR8RAM.v(130): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 130 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618906714979 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(138) " "Verilog HDL assignment warning at GR8RAM.v(138): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 138 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618906714979 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(145) " "Verilog HDL assignment warning at GR8RAM.v(145): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 145 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618906714994 "|GR8RAM"} -{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 -1 1618906716541 ""} -{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "nNMIout VCC " "Pin \"nNMIout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 553 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618906716822 "|GR8RAM|nNMIout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nIRQout VCC " "Pin \"nIRQout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 556 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618906716822 "|GR8RAM|nIRQout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nRDYout VCC " "Pin \"nRDYout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 555 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618906716822 "|GR8RAM|nRDYout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nINHout VCC " "Pin \"nINHout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 554 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618906716822 "|GR8RAM|nINHout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RWout VCC " "Pin \"RWout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 557 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618906716822 "|GR8RAM|RWout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nDMAout VCC " "Pin \"nDMAout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 552 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618906716822 "|GR8RAM|nDMAout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 551 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618906716822 "|GR8RAM|RAdir"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1618906716822 ""} -{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1618906717276 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "321 " "Implemented 321 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "28 " "Implemented 28 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1618906717307 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1618906717307 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1618906717307 ""} { "Info" "ICUT_CUT_TM_LCELLS" "241 " "Implemented 241 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1618906717307 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1618906717307 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1618906717510 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 13 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 13 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "301 " "Peak virtual memory: 301 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618906717666 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 04:18:37 2021 " "Processing ended: Tue Apr 20 04:18:37 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618906717666 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618906717666 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618906717666 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618906717666 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618906720682 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 32-bit " "Running Quartus II 32-bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618906720698 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 04:18:39 2021 " "Processing started: Tue Apr 20 04:18:39 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618906720698 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1618906720698 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1618906720698 ""} -{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1618906720885 ""} -{ "Info" "0" "" "Project = GR8RAM" { } { } 0 0 "Project = GR8RAM" 0 0 "Fitter" 0 0 1618906720885 ""} -{ "Info" "0" "" "Revision = GR8RAM" { } { } 0 0 "Revision = GR8RAM" 0 0 "Fitter" 0 0 1618906720885 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1618906721651 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1618906721682 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618906721948 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618906721948 ""} -{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1618906722260 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1618906722307 ""} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618906722666 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618906722666 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618906722666 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618906722666 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618906722666 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1618906722666 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1618906722838 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1618906722854 ""} -{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1618906722885 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1618906722885 ""} -{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618906722932 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618906722932 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 C25M " " 1.000 C25M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618906722932 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI0 " " 1.000 PHI0" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618906722932 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1618906722932 ""} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618906722932 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618906722948 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618906722948 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618906722979 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI0 Global clock " "Automatically promoted some destinations of signal \"PHI0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~1 " "Destination \"comb~1\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618906722979 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI0r1 " "Destination \"PHI0r1\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618906722979 ""} } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618906722979 ""} -{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI0 " "Pin \"PHI0\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI0 } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "PHI0" } } } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 380 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1618906722979 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "nRESr Global clock " "Automatically promoted signal \"nRESr\" to use Global clock" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 16 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618906722995 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618906722995 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1618906722995 ""} -{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1618906723026 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1618906723073 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1618906723088 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1618906723088 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1618906723088 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618906723135 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1618906723307 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618906723667 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1618906723682 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1618906725120 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618906725135 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1618906725214 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "36 " "Router estimated average interconnect usage is 36% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "36 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 36% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 36% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 36% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1618906725682 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1618906725682 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618906726260 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.67 " "Total time spent on timing analysis during the Fitter is 0.67 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1618906726276 ""} -{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618906726276 ""} -{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1618906726307 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1618906726589 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "382 " "Peak virtual memory: 382 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618906726823 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 04:18:46 2021 " "Processing ended: Tue Apr 20 04:18:46 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618906726823 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618906726823 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618906726823 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1618906726823 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1618906729714 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618906729714 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 04:18:49 2021 " "Processing started: Tue Apr 20 04:18:49 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618906729714 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1618906729714 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1618906729714 ""} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1618906730948 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1618906730979 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "293 " "Peak virtual memory: 293 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618906731745 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 04:18:51 2021 " "Processing ended: Tue Apr 20 04:18:51 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618906731745 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618906731745 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618906731745 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1618906731745 ""} -{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1618906732667 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1618906734839 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618906734839 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 04:18:53 2021 " "Processing started: Tue Apr 20 04:18:53 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618906734839 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618906734839 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618906734839 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1618906735042 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1618906735948 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618906736105 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618906736105 ""} -{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1618906736308 ""} -{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1618906737074 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1618906737308 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1618906737308 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C25M C25M " "create_clock -period 1.000 -name C25M C25M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737308 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI0 PHI0 " "create_clock -period 1.000 -name PHI0 PHI0" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737308 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737308 ""} -{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1618906737324 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1618906737495 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -9.005 " "Worst-case setup slack is -9.005" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737495 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737495 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.005 -699.357 C25M " " -9.005 -699.357 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737495 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.425 -0.425 PHI0 " " -0.425 -0.425 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737495 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618906737495 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.248 " "Worst-case hold slack is -0.248" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737527 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737527 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.248 -0.248 PHI0 " " -0.248 -0.248 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737527 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.400 0.000 C25M " " 1.400 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737527 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618906737527 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -4.412 " "Worst-case recovery slack is -4.412" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737542 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737542 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.412 -127.948 C25M " " -4.412 -127.948 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737542 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618906737542 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "removal 4.858 " "Worst-case removal slack is 4.858" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737558 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737558 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.858 0.000 C25M " " 4.858 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737558 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618906737558 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.289 " "Worst-case minimum pulse width slack is -2.289" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737589 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737589 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 C25M " " -2.289 -2.289 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737589 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI0 " " -2.289 -2.289 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737589 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618906737589 ""} -{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1618906738136 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618906738246 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618906738246 ""} -{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "278 " "Peak virtual memory: 278 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618906738496 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 04:18:58 2021 " "Processing ended: Tue Apr 20 04:18:58 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618906738496 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618906738496 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618906738496 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618906738496 ""} -{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 18 s " "Quartus II Full Compilation was successful. 0 errors, 18 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618906739949 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1619049425619 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1619049425619 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 21 19:57:05 2021 " "Processing started: Wed Apr 21 19:57:05 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1619049425619 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1619049425619 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1619049425635 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1619049427276 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(110) " "Verilog HDL warning at GR8RAM.v(110): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 110 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1619049427432 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(286) " "Verilog HDL warning at GR8RAM.v(286): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 286 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1619049427432 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1619049427448 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1619049427448 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1619049427557 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(42) " "Verilog HDL assignment warning at GR8RAM.v(42): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 42 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1619049427557 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(47) " "Verilog HDL assignment warning at GR8RAM.v(47): truncated value with size 32 to match size of target (14)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 47 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1619049427557 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(134) " "Verilog HDL assignment warning at GR8RAM.v(134): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 134 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1619049427573 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(142) " "Verilog HDL assignment warning at GR8RAM.v(142): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 142 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1619049427573 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(149) " "Verilog HDL assignment warning at GR8RAM.v(149): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 149 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1619049427589 "|GR8RAM"} +{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 -1 1619049429167 ""} +{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "nNMIout VCC " "Pin \"nNMIout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 563 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1619049429543 "|GR8RAM|nNMIout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nIRQout VCC " "Pin \"nIRQout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 566 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1619049429543 "|GR8RAM|nIRQout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nRDYout VCC " "Pin \"nRDYout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 565 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1619049429543 "|GR8RAM|nRDYout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nINHout VCC " "Pin \"nINHout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 564 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1619049429543 "|GR8RAM|nINHout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RWout VCC " "Pin \"RWout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 567 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1619049429543 "|GR8RAM|RWout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nDMAout VCC " "Pin \"nDMAout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 562 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1619049429543 "|GR8RAM|nDMAout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 561 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1619049429543 "|GR8RAM|RAdir"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1619049429543 ""} +{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1619049430027 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "337 " "Implemented 337 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "28 " "Implemented 28 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1619049430074 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1619049430074 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1619049430074 ""} { "Info" "ICUT_CUT_TM_LCELLS" "257 " "Implemented 257 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1619049430074 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1619049430074 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1619049430324 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 13 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 13 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "301 " "Peak virtual memory: 301 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1619049430496 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 21 19:57:10 2021 " "Processing ended: Wed Apr 21 19:57:10 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1619049430496 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1619049430496 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1619049430496 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1619049430496 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1619049433591 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 32-bit " "Running Quartus II 32-bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1619049433606 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 21 19:57:12 2021 " "Processing started: Wed Apr 21 19:57:12 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1619049433606 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1619049433606 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1619049433606 ""} +{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1619049433810 ""} +{ "Info" "0" "" "Project = GR8RAM" { } { } 0 0 "Project = GR8RAM" 0 0 "Fitter" 0 0 1619049433810 ""} +{ "Info" "0" "" "Revision = GR8RAM" { } { } 0 0 "Revision = GR8RAM" 0 0 "Fitter" 0 0 1619049433810 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1619049434576 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1619049434607 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1619049435513 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1619049435513 ""} +{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1619049435826 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1619049435873 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1619049436217 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1619049436217 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1619049436217 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1619049436217 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1619049436217 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1619049436217 ""} +{ "Info" "ISTA_SDC_FOUND" "GR8RAM.sdc " "Reading SDC File: 'GR8RAM.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1619049436389 ""} +{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1619049436436 ""} +{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1619049436451 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1619049436451 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 40.000 C25M " " 40.000 C25M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1619049436451 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 978.000 PHI0 " " 978.000 PHI0" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1619049436451 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1619049436451 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1619049436451 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1619049436451 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1619049436467 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1619049436514 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI0 Global clock " "Automatically promoted some destinations of signal \"PHI0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~0 " "Destination \"comb~0\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1619049436514 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI0r1 " "Destination \"PHI0r1\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1619049436514 ""} } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1619049436514 ""} +{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI0 " "Pin \"PHI0\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI0 } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "PHI0" } } } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 419 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1619049436514 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nRESr Global clock " "Automatically promoted some destinations of signal \"nRESr\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "IOROMEN " "Destination \"IOROMEN\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 94 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1619049436514 ""} } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 16 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1619049436514 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1619049436514 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1619049436529 ""} +{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1619049436592 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1619049436654 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1619049436670 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1619049436670 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1619049436670 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619049436701 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1619049436967 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619049437342 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1619049437373 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1619049438593 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619049438593 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1619049438686 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "34 " "Router estimated average interconnect usage is 34% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "34 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1619049439186 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1619049439186 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619049439702 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.56 " "Total time spent on timing analysis during the Fitter is 0.56 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1619049439718 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619049439718 ""} +{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1619049439765 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1619049440124 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "383 " "Peak virtual memory: 383 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1619049440312 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 21 19:57:20 2021 " "Processing ended: Wed Apr 21 19:57:20 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1619049440312 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1619049440312 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1619049440312 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1619049440312 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1619049443282 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1619049443297 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 21 19:57:22 2021 " "Processing started: Wed Apr 21 19:57:22 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1619049443297 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1619049443297 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1619049443297 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1619049444797 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1619049444985 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "293 " "Peak virtual memory: 293 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1619049446001 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 21 19:57:26 2021 " "Processing ended: Wed Apr 21 19:57:26 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1619049446001 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1619049446001 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1619049446001 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1619049446001 ""} +{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1619049446923 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1619049449251 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1619049449267 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 21 19:57:27 2021 " "Processing started: Wed Apr 21 19:57:27 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1619049449267 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1619049449267 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1619049449267 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1619049449455 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1619049450502 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1619049450705 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1619049450705 ""} +{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1619049450877 ""} +{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1619049451408 ""} +{ "Info" "ISTA_SDC_FOUND" "GR8RAM.sdc " "Reading SDC File: 'GR8RAM.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1619049451564 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1619049451627 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup 12.419 " "Worst-case setup slack is 12.419" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451721 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451721 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 12.419 0.000 C25M " " 12.419 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451721 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1619049451721 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.393 " "Worst-case hold slack is 1.393" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451721 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451721 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.393 0.000 C25M " " 1.393 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451721 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1619049451721 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 33.300 " "Worst-case recovery slack is 33.300" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451736 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451736 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 33.300 0.000 C25M " " 33.300 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451736 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1619049451736 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "removal 6.146 " "Worst-case removal slack is 6.146" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451736 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451736 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 6.146 0.000 C25M " " 6.146 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451736 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1619049451736 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 19.734 " "Worst-case minimum pulse width slack is 19.734" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451752 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451752 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.734 0.000 C25M " " 19.734 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451752 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 488.734 0.000 PHI0 " " 488.734 0.000 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451752 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1619049451752 ""} +{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1619049451861 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1619049451924 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1619049451939 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "278 " "Peak virtual memory: 278 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1619049452143 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 21 19:57:32 2021 " "Processing ended: Wed Apr 21 19:57:32 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1619049452143 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1619049452143 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1619049452143 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1619049452143 ""} +{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 15 s " "Quartus II Full Compilation was successful. 0 errors, 15 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1619049453283 ""} diff --git a/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt b/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt index 0798033..5d628f7 100755 Binary files a/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt and b/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt differ diff --git a/cpld/output_files/GR8RAM.asm.rpt b/cpld/output_files/GR8RAM.asm.rpt index 609cd3a..02ce44c 100755 --- a/cpld/output_files/GR8RAM.asm.rpt +++ b/cpld/output_files/GR8RAM.asm.rpt @@ -1,5 +1,5 @@ Assembler report for GR8RAM -Tue Apr 20 04:19:58 2021 +Wed Apr 21 20:02:00 2021 Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition @@ -37,7 +37,7 @@ applicable agreement for further details. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Tue Apr 20 04:19:58 2021 ; +; Assembler Status ; Successful - Wed Apr 21 20:02:00 2021 ; ; Revision Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ; ; Family ; MAX II ; @@ -90,8 +90,8 @@ applicable agreement for further details. ; Option ; Setting ; +----------------+-------------------------------------------------------+ ; Device ; EPM240T100C5 ; -; JTAG usercode ; 0x001644CE ; -; Checksum ; 0x0016484E ; +; JTAG usercode ; 0x00161CF0 ; +; Checksum ; 0x001620E8 ; +----------------+-------------------------------------------------------+ @@ -101,14 +101,14 @@ applicable agreement for further details. Info: ******************************************************************* Info: Running Quartus II 32-bit Assembler Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - Info: Processing started: Tue Apr 20 04:19:56 2021 + Info: Processing started: Wed Apr 21 20:01:58 2021 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM Info (115031): Writing out detailed assembly data for power analysis Info (115030): Assembler is generating device programming files Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings Info: Peak virtual memory: 293 megabytes - Info: Processing ended: Tue Apr 20 04:19:59 2021 - Info: Elapsed time: 00:00:03 + Info: Processing ended: Wed Apr 21 20:02:00 2021 + Info: Elapsed time: 00:00:02 Info: Total CPU time (on all processors): 00:00:02 diff --git a/cpld/output_files/GR8RAM.done b/cpld/output_files/GR8RAM.done index 7c4faa1..6e7ef41 100755 --- a/cpld/output_files/GR8RAM.done +++ b/cpld/output_files/GR8RAM.done @@ -1 +1 @@ -Tue Apr 20 04:20:06 2021 +Wed Apr 21 20:02:09 2021 diff --git a/cpld/output_files/GR8RAM.fit.rpt b/cpld/output_files/GR8RAM.fit.rpt index b4be352..a738d24 100755 --- a/cpld/output_files/GR8RAM.fit.rpt +++ b/cpld/output_files/GR8RAM.fit.rpt @@ -1,5 +1,5 @@ Fitter report for GR8RAM -Tue Apr 20 04:19:53 2021 +Wed Apr 21 20:01:56 2021 Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition @@ -57,14 +57,14 @@ applicable agreement for further details. +-----------------------------------------------------------------------------+ ; Fitter Summary ; +---------------------------+-------------------------------------------------+ -; Fitter Status ; Successful - Tue Apr 20 04:19:53 2021 ; +; Fitter Status ; Successful - Wed Apr 21 20:01:56 2021 ; ; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; ; Revision Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ; ; Family ; MAX II ; ; Device ; EPM240T100C5 ; ; Timing Models ; Final ; -; Total logic elements ; 230 / 240 ( 96 % ) ; +; Total logic elements ; 234 / 240 ( 98 % ) ; ; Total pins ; 80 / 80 ( 100 % ) ; ; Total virtual pins ; 0 ; ; UFM blocks ; 0 / 1 ( 0 % ) ; @@ -128,12 +128,12 @@ applicable agreement for further details. ; Number detected on machine ; 2 ; ; Maximum allowed ; 2 ; ; ; ; -; Average used ; 1.20 ; +; Average used ; 1.40 ; ; Maximum used ; 2 ; ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; -; Processor 2 ; 20.0% ; +; Processor 2 ; 40.0% ; +----------------------------+-------------+ @@ -148,27 +148,27 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin. +---------------------------------------------+--------------------+ ; Resource ; Usage ; +---------------------------------------------+--------------------+ -; Total logic elements ; 230 / 240 ( 96 % ) ; -; -- Combinational with no register ; 121 ; +; Total logic elements ; 234 / 240 ( 98 % ) ; +; -- Combinational with no register ; 113 ; ; -- Register only ; 1 ; -; -- Combinational with a register ; 108 ; +; -- Combinational with a register ; 120 ; ; ; ; ; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 119 ; -; -- 3 input functions ; 38 ; -; -- 2 input functions ; 69 ; +; -- 4 input functions ; 126 ; +; -- 3 input functions ; 41 ; +; -- 2 input functions ; 65 ; ; -- 1 input functions ; 0 ; -; -- 0 input functions ; 3 ; +; -- 0 input functions ; 1 ; ; ; ; ; Logic elements by mode ; ; -; -- normal mode ; 197 ; +; -- normal mode ; 201 ; ; -- arithmetic mode ; 33 ; -; -- qfbk mode ; 6 ; +; -- qfbk mode ; 18 ; ; -- register cascade mode ; 0 ; -; -- synchronous clear/load mode ; 54 ; -; -- asynchronous clear/load mode ; 30 ; +; -- synchronous clear/load mode ; 67 ; +; -- asynchronous clear/load mode ; 29 ; ; ; ; -; Total registers ; 109 / 240 ( 45 % ) ; +; Total registers ; 121 / 240 ( 50 % ) ; ; Total LABs ; 24 / 24 ( 100 % ) ; ; Logic elements in carry chains ; 37 ; ; Virtual pins ; 0 ; @@ -179,49 +179,49 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin. ; UFM blocks ; 0 / 1 ( 0 % ) ; ; Global clocks ; 3 / 4 ( 75 % ) ; ; JTAGs ; 0 / 1 ( 0 % ) ; -; Average interconnect usage (total/H/V) ; 44% / 49% / 38% ; -; Peak interconnect usage (total/H/V) ; 44% / 49% / 38% ; -; Maximum fan-out ; 106 ; -; Highest non-global fan-out ; 45 ; -; Total fan-out ; 1050 ; -; Average fan-out ; 3.39 ; +; Average interconnect usage (total/H/V) ; 40% / 44% / 37% ; +; Peak interconnect usage (total/H/V) ; 40% / 44% / 37% ; +; Maximum fan-out ; 107 ; +; Highest non-global fan-out ; 47 ; +; Total fan-out ; 1091 ; +; Average fan-out ; 3.47 ; +---------------------------------------------+--------------------+ -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Input Pins ; -+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+ -; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Location assigned by ; -+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+ -; C25M ; 64 ; 2 ; 8 ; 3 ; 4 ; 106 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; DMAin ; 48 ; 1 ; 6 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; INTin ; 49 ; 1 ; 7 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; MISO ; 16 ; 1 ; 1 ; 2 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; PHI0 ; 41 ; 1 ; 5 ; 0 ; 1 ; 5 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; RA[0] ; 100 ; 2 ; 2 ; 5 ; 2 ; 9 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; RA[10] ; 14 ; 1 ; 1 ; 2 ; 0 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; RA[11] ; 34 ; 1 ; 3 ; 0 ; 1 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; RA[12] ; 35 ; 1 ; 3 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; RA[13] ; 36 ; 1 ; 4 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; RA[14] ; 37 ; 1 ; 4 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; RA[15] ; 38 ; 1 ; 4 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; RA[1] ; 98 ; 2 ; 2 ; 5 ; 0 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; RA[2] ; 97 ; 2 ; 3 ; 5 ; 3 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; RA[3] ; 4 ; 1 ; 1 ; 4 ; 2 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; RA[4] ; 1 ; 2 ; 2 ; 5 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; RA[5] ; 2 ; 1 ; 1 ; 4 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; RA[6] ; 3 ; 1 ; 1 ; 4 ; 1 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; RA[7] ; 6 ; 1 ; 1 ; 3 ; 0 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; RA[8] ; 7 ; 1 ; 1 ; 3 ; 1 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; RA[9] ; 8 ; 1 ; 1 ; 3 ; 2 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; SetFW[0] ; 96 ; 2 ; 3 ; 5 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; SetFW[1] ; 95 ; 2 ; 3 ; 5 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; nDEVSEL ; 40 ; 1 ; 5 ; 0 ; 2 ; 4 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; nIOSEL ; 39 ; 1 ; 5 ; 0 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; nIOSTRB ; 42 ; 1 ; 5 ; 0 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; nRES ; 44 ; 1 ; 6 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; nWE ; 43 ; 1 ; 6 ; 0 ; 3 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+ ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+----------------------------+----------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Location assigned by ; ++----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+----------------------------+----------------------+ +; C25M ; 64 ; 2 ; 8 ; 3 ; 4 ; 107 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; User ; +; DMAin ; 48 ; 1 ; 6 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; +; INTin ; 49 ; 1 ; 7 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; +; MISO ; 16 ; 1 ; 1 ; 2 ; 2 ; 1 ; 0 ; no ; no ; yes ; Off ; 3.3-V LVTTL ; User ; +; PHI0 ; 41 ; 1 ; 5 ; 0 ; 1 ; 16 ; 0 ; yes ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; +; RA[0] ; 100 ; 2 ; 2 ; 5 ; 2 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; +; RA[10] ; 14 ; 1 ; 1 ; 2 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; +; RA[11] ; 34 ; 1 ; 3 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; +; RA[12] ; 35 ; 1 ; 3 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; +; RA[13] ; 36 ; 1 ; 4 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; +; RA[14] ; 37 ; 1 ; 4 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; +; RA[15] ; 38 ; 1 ; 4 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; +; RA[1] ; 98 ; 2 ; 2 ; 5 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; +; RA[2] ; 97 ; 2 ; 3 ; 5 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; +; RA[3] ; 4 ; 1 ; 1 ; 4 ; 2 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; +; RA[4] ; 1 ; 2 ; 2 ; 5 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; +; RA[5] ; 2 ; 1 ; 1 ; 4 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; +; RA[6] ; 3 ; 1 ; 1 ; 4 ; 1 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; +; RA[7] ; 6 ; 1 ; 1 ; 3 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; +; RA[8] ; 7 ; 1 ; 1 ; 3 ; 1 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; +; RA[9] ; 8 ; 1 ; 1 ; 3 ; 2 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; +; SetFW[0] ; 96 ; 2 ; 3 ; 5 ; 2 ; 1 ; 0 ; no ; no ; no ; On ; 3.3V Schmitt Trigger Input ; User ; +; SetFW[1] ; 95 ; 2 ; 3 ; 5 ; 1 ; 1 ; 0 ; no ; no ; no ; On ; 3.3V Schmitt Trigger Input ; User ; +; nDEVSEL ; 40 ; 1 ; 5 ; 0 ; 2 ; 4 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; +; nIOSEL ; 39 ; 1 ; 5 ; 0 ; 3 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; +; nIOSTRB ; 42 ; 1 ; 5 ; 0 ; 0 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; +; nRES ; 44 ; 1 ; 6 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; +; nWE ; 43 ; 1 ; 6 ; 0 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; ++----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+----------------------------+----------------------+ +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ @@ -230,40 +230,40 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin. ; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ; +---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ ; DMAout ; 18 ; 1 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; -; DQMH ; 57 ; 2 ; 8 ; 2 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; -; DQML ; 85 ; 2 ; 5 ; 5 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; -; FCK ; 12 ; 1 ; 1 ; 3 ; 3 ; no ; no ; no ; no ; yes ; yes ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; +; DQMH ; 57 ; 2 ; 8 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; +; DQML ; 85 ; 2 ; 5 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; +; FCK ; 12 ; 1 ; 1 ; 3 ; 3 ; no ; yes ; no ; no ; yes ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; ; INTout ; 20 ; 1 ; 1 ; 1 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; -; RAdir ; 19 ; 1 ; 1 ; 1 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; -; RCKE ; 66 ; 2 ; 8 ; 3 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; -; RDdir ; 17 ; 1 ; 1 ; 2 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; +; RAdir ; 19 ; 1 ; 1 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; +; RCKE ; 66 ; 2 ; 8 ; 3 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; +; RDdir ; 17 ; 1 ; 1 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; ; RWout ; 33 ; 1 ; 3 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; -; SA[0] ; 75 ; 2 ; 7 ; 5 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; -; SA[10] ; 73 ; 2 ; 8 ; 4 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; - ; - ; -; SA[11] ; 70 ; 2 ; 8 ; 4 ; 4 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; -; SA[12] ; 68 ; 2 ; 8 ; 3 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; -; SA[1] ; 81 ; 2 ; 6 ; 5 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; -; SA[2] ; 82 ; 2 ; 6 ; 5 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; -; SA[3] ; 84 ; 2 ; 6 ; 5 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; -; SA[4] ; 76 ; 2 ; 7 ; 5 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; -; SA[5] ; 83 ; 2 ; 6 ; 5 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; -; SA[6] ; 77 ; 2 ; 7 ; 5 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; -; SA[7] ; 78 ; 2 ; 7 ; 5 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; -; SA[8] ; 74 ; 2 ; 8 ; 4 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; -; SA[9] ; 72 ; 2 ; 8 ; 4 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; -; SBA[0] ; 69 ; 2 ; 8 ; 3 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; -; SBA[1] ; 71 ; 2 ; 8 ; 4 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; - ; - ; -; nCAS ; 61 ; 2 ; 8 ; 2 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; +; SA[0] ; 75 ; 2 ; 7 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; yes ; User ; 10 pF ; - ; - ; +; SA[10] ; 73 ; 2 ; 8 ; 4 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; +; SA[11] ; 70 ; 2 ; 8 ; 4 ; 4 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; +; SA[12] ; 68 ; 2 ; 8 ; 3 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; +; SA[1] ; 81 ; 2 ; 6 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; +; SA[2] ; 82 ; 2 ; 6 ; 5 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; +; SA[3] ; 84 ; 2 ; 6 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; +; SA[4] ; 76 ; 2 ; 7 ; 5 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; +; SA[5] ; 83 ; 2 ; 6 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; +; SA[6] ; 77 ; 2 ; 7 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; +; SA[7] ; 78 ; 2 ; 7 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; +; SA[8] ; 74 ; 2 ; 8 ; 4 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; +; SA[9] ; 72 ; 2 ; 8 ; 4 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; +; SBA[0] ; 69 ; 2 ; 8 ; 3 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; +; SBA[1] ; 71 ; 2 ; 8 ; 4 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; +; nCAS ; 61 ; 2 ; 8 ; 2 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; ; nDMAout ; 21 ; 1 ; 1 ; 1 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; -; nFCS ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; no ; no ; no ; yes ; no ; On ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; +; nFCS ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; yes ; no ; no ; yes ; no ; On ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; ; nINHout ; 27 ; 1 ; 2 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; ; nIRQout ; 29 ; 1 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; ; nNMIout ; 26 ; 1 ; 2 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; -; nRAS ; 62 ; 2 ; 8 ; 2 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; -; nRCS ; 67 ; 2 ; 8 ; 3 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; +; nRAS ; 62 ; 2 ; 8 ; 2 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; yes ; User ; 10 pF ; - ; - ; +; nRCS ; 67 ; 2 ; 8 ; 3 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; ; nRDYout ; 28 ; 1 ; 2 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; -; nRESout ; 30 ; 1 ; 3 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; -; nSWE ; 58 ; 2 ; 8 ; 2 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; +; nRESout ; 30 ; 1 ; 3 ; 0 ; 3 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; +; nSWE ; 58 ; 2 ; 8 ; 2 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; +---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ @@ -272,23 +272,23 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin. +-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ ; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ; +-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ -; MOSI ; 15 ; 1 ; 1 ; 2 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; MOSIOE ; - ; -; RD[0] ; 86 ; 2 ; 5 ; 5 ; 1 ; 5 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; comb~1 ; - ; -; RD[1] ; 87 ; 2 ; 5 ; 5 ; 2 ; 4 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; comb~1 ; - ; -; RD[2] ; 88 ; 2 ; 5 ; 5 ; 3 ; 4 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; comb~1 ; - ; -; RD[3] ; 89 ; 2 ; 4 ; 5 ; 0 ; 4 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; comb~1 ; - ; -; RD[4] ; 90 ; 2 ; 4 ; 5 ; 1 ; 4 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; comb~1 ; - ; -; RD[5] ; 91 ; 2 ; 4 ; 5 ; 2 ; 4 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; comb~1 ; - ; -; RD[6] ; 92 ; 2 ; 3 ; 5 ; 0 ; 4 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; comb~1 ; - ; -; RD[7] ; 99 ; 2 ; 2 ; 5 ; 1 ; 6 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; comb~1 ; - ; -; SD[0] ; 50 ; 1 ; 7 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; SDOE ; - ; -; SD[1] ; 47 ; 1 ; 6 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; -; SD[2] ; 56 ; 2 ; 8 ; 1 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; -; SD[3] ; 55 ; 2 ; 8 ; 1 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; -; SD[4] ; 51 ; 1 ; 7 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; -; SD[5] ; 52 ; 2 ; 8 ; 1 ; 4 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; SDOE ; - ; -; SD[6] ; 53 ; 2 ; 8 ; 1 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; -; SD[7] ; 54 ; 2 ; 8 ; 1 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; +; MOSI ; 15 ; 1 ; 1 ; 2 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; MOSIOE ; - ; +; RD[0] ; 86 ; 2 ; 5 ; 5 ; 1 ; 5 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ; +; RD[1] ; 87 ; 2 ; 5 ; 5 ; 2 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ; +; RD[2] ; 88 ; 2 ; 5 ; 5 ; 3 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ; +; RD[3] ; 89 ; 2 ; 4 ; 5 ; 0 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ; +; RD[4] ; 90 ; 2 ; 4 ; 5 ; 1 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ; +; RD[5] ; 91 ; 2 ; 4 ; 5 ; 2 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ; +; RD[6] ; 92 ; 2 ; 3 ; 5 ; 0 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ; +; RD[7] ; 99 ; 2 ; 2 ; 5 ; 1 ; 6 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ; +; SD[0] ; 50 ; 1 ; 7 ; 0 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; +; SD[1] ; 47 ; 1 ; 6 ; 0 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; +; SD[2] ; 56 ; 2 ; 8 ; 1 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; +; SD[3] ; 55 ; 2 ; 8 ; 1 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; +; SD[4] ; 51 ; 1 ; 7 ; 0 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; +; SD[5] ; 52 ; 2 ; 8 ; 1 ; 4 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; +; SD[6] ; 53 ; 2 ; 8 ; 1 ; 3 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; +; SD[7] ; 54 ; 2 ; 8 ; 1 ; 2 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; +-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ @@ -302,112 +302,112 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin. +----------+-------------------+---------------+--------------+ -+------------------------------------------------------------------------------------------------------------------------------------------------+ -; All Package Pins ; -+----------+------------+----------+----------------+--------+--------------+-----------+------------+-----------------+----------+--------------+ -; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; -+----------+------------+----------+----------------+--------+--------------+-----------+------------+-----------------+----------+--------------+ -; 1 ; 83 ; 2 ; RA[4] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 2 ; 0 ; 1 ; RA[5] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 3 ; 1 ; 1 ; RA[6] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 4 ; 2 ; 1 ; RA[3] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 5 ; 3 ; 1 ; nFCS ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ; -; 6 ; 4 ; 1 ; RA[7] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 7 ; 5 ; 1 ; RA[8] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 8 ; 6 ; 1 ; RA[9] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 9 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 10 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; -; 11 ; ; ; GNDINT ; gnd ; ; ; -- ; ; -- ; -- ; -; 12 ; 7 ; 1 ; FCK ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; yes ; Off ; -; 13 ; ; ; VCCINT ; power ; ; 2.5V/3.3V ; -- ; ; -- ; -- ; -; 14 ; 8 ; 1 ; RA[10] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 15 ; 9 ; 1 ; MOSI ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; yes ; Off ; -; 16 ; 10 ; 1 ; MISO ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 17 ; 11 ; 1 ; RDdir ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 18 ; 12 ; 1 ; DMAout ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 19 ; 13 ; 1 ; RAdir ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 20 ; 14 ; 1 ; INTout ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 21 ; 15 ; 1 ; nDMAout ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 22 ; 16 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ; -; 23 ; 17 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ; -; 24 ; 18 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ; -; 25 ; 19 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ; -; 26 ; 20 ; 1 ; nNMIout ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 27 ; 21 ; 1 ; nINHout ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 28 ; 22 ; 1 ; nRDYout ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 29 ; 23 ; 1 ; nIRQout ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 30 ; 24 ; 1 ; nRESout ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 31 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 32 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; -; 33 ; 25 ; 1 ; RWout ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 34 ; 26 ; 1 ; RA[11] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 35 ; 27 ; 1 ; RA[12] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 36 ; 28 ; 1 ; RA[13] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 37 ; 29 ; 1 ; RA[14] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 38 ; 30 ; 1 ; RA[15] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 39 ; 31 ; 1 ; nIOSEL ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 40 ; 32 ; 1 ; nDEVSEL ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 41 ; 33 ; 1 ; PHI0 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 42 ; 34 ; 1 ; nIOSTRB ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 43 ; 35 ; 1 ; nWE ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 44 ; 36 ; 1 ; nRES ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 45 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 46 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; -; 47 ; 37 ; 1 ; SD[1] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 48 ; 38 ; 1 ; DMAin ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 49 ; 39 ; 1 ; INTin ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 50 ; 40 ; 1 ; SD[0] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 51 ; 41 ; 1 ; SD[4] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 52 ; 42 ; 2 ; SD[5] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 53 ; 43 ; 2 ; SD[6] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 54 ; 44 ; 2 ; SD[7] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 55 ; 45 ; 2 ; SD[3] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 56 ; 46 ; 2 ; SD[2] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 57 ; 47 ; 2 ; DQMH ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 58 ; 48 ; 2 ; nSWE ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 59 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 60 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; -; 61 ; 49 ; 2 ; nCAS ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 62 ; 50 ; 2 ; nRAS ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 63 ; ; ; VCCINT ; power ; ; 2.5V/3.3V ; -- ; ; -- ; -- ; -; 64 ; 51 ; 2 ; C25M ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 65 ; ; ; GNDINT ; gnd ; ; ; -- ; ; -- ; -- ; -; 66 ; 52 ; 2 ; RCKE ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 67 ; 53 ; 2 ; nRCS ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 68 ; 54 ; 2 ; SA[12] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 69 ; 55 ; 2 ; SBA[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 70 ; 56 ; 2 ; SA[11] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 71 ; 57 ; 2 ; SBA[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 72 ; 58 ; 2 ; SA[9] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 73 ; 59 ; 2 ; SA[10] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 74 ; 60 ; 2 ; SA[8] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 75 ; 61 ; 2 ; SA[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 76 ; 62 ; 2 ; SA[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 77 ; 63 ; 2 ; SA[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 78 ; 64 ; 2 ; SA[7] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 79 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; -; 80 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 81 ; 65 ; 2 ; SA[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 82 ; 66 ; 2 ; SA[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 83 ; 67 ; 2 ; SA[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 84 ; 68 ; 2 ; SA[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 85 ; 69 ; 2 ; DQML ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 86 ; 70 ; 2 ; RD[0] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 87 ; 71 ; 2 ; RD[1] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 88 ; 72 ; 2 ; RD[2] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 89 ; 73 ; 2 ; RD[3] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 90 ; 74 ; 2 ; RD[4] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 91 ; 75 ; 2 ; RD[5] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 92 ; 76 ; 2 ; RD[6] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 93 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; -; 94 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 95 ; 77 ; 2 ; SetFW[1] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 96 ; 78 ; 2 ; SetFW[0] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 97 ; 79 ; 2 ; RA[2] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 98 ; 80 ; 2 ; RA[1] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 99 ; 81 ; 2 ; RD[7] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 100 ; 82 ; 2 ; RA[0] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -+----------+------------+----------+----------------+--------+--------------+-----------+------------+-----------------+----------+--------------+ ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------+----------------+--------+----------------------------+-----------+------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------+----------------+--------+----------------------------+-----------+------------+-----------------+----------+--------------+ +; 1 ; 83 ; 2 ; RA[4] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 2 ; 0 ; 1 ; RA[5] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 3 ; 1 ; 1 ; RA[6] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 4 ; 2 ; 1 ; RA[3] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 5 ; 3 ; 1 ; nFCS ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ; +; 6 ; 4 ; 1 ; RA[7] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 7 ; 5 ; 1 ; RA[8] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 8 ; 6 ; 1 ; RA[9] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 9 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 10 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; +; 11 ; ; ; GNDINT ; gnd ; ; ; -- ; ; -- ; -- ; +; 12 ; 7 ; 1 ; FCK ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; yes ; Off ; +; 13 ; ; ; VCCINT ; power ; ; 2.5V/3.3V ; -- ; ; -- ; -- ; +; 14 ; 8 ; 1 ; RA[10] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 15 ; 9 ; 1 ; MOSI ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; yes ; Off ; +; 16 ; 10 ; 1 ; MISO ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; yes ; Off ; +; 17 ; 11 ; 1 ; RDdir ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ; +; 18 ; 12 ; 1 ; DMAout ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 19 ; 13 ; 1 ; RAdir ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ; +; 20 ; 14 ; 1 ; INTout ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 21 ; 15 ; 1 ; nDMAout ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 22 ; 16 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ; +; 23 ; 17 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ; +; 24 ; 18 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ; +; 25 ; 19 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ; +; 26 ; 20 ; 1 ; nNMIout ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 27 ; 21 ; 1 ; nINHout ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 28 ; 22 ; 1 ; nRDYout ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 29 ; 23 ; 1 ; nIRQout ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 30 ; 24 ; 1 ; nRESout ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ; +; 31 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 32 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; +; 33 ; 25 ; 1 ; RWout ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 34 ; 26 ; 1 ; RA[11] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 35 ; 27 ; 1 ; RA[12] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 36 ; 28 ; 1 ; RA[13] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 37 ; 29 ; 1 ; RA[14] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 38 ; 30 ; 1 ; RA[15] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 39 ; 31 ; 1 ; nIOSEL ; input ; 3.3V Schmitt Trigger Input ; ; Column I/O ; Y ; no ; Off ; +; 40 ; 32 ; 1 ; nDEVSEL ; input ; 3.3V Schmitt Trigger Input ; ; Column I/O ; Y ; no ; Off ; +; 41 ; 33 ; 1 ; PHI0 ; input ; 3.3V Schmitt Trigger Input ; ; Column I/O ; Y ; no ; Off ; +; 42 ; 34 ; 1 ; nIOSTRB ; input ; 3.3V Schmitt Trigger Input ; ; Column I/O ; Y ; no ; Off ; +; 43 ; 35 ; 1 ; nWE ; input ; 3.3V Schmitt Trigger Input ; ; Column I/O ; Y ; no ; Off ; +; 44 ; 36 ; 1 ; nRES ; input ; 3.3V Schmitt Trigger Input ; ; Column I/O ; Y ; no ; Off ; +; 45 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 46 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; +; 47 ; 37 ; 1 ; SD[1] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 48 ; 38 ; 1 ; DMAin ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 49 ; 39 ; 1 ; INTin ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 50 ; 40 ; 1 ; SD[0] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 51 ; 41 ; 1 ; SD[4] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 52 ; 42 ; 2 ; SD[5] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 53 ; 43 ; 2 ; SD[6] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 54 ; 44 ; 2 ; SD[7] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 55 ; 45 ; 2 ; SD[3] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 56 ; 46 ; 2 ; SD[2] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 57 ; 47 ; 2 ; DQMH ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 58 ; 48 ; 2 ; nSWE ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 59 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 60 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; +; 61 ; 49 ; 2 ; nCAS ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 62 ; 50 ; 2 ; nRAS ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 63 ; ; ; VCCINT ; power ; ; 2.5V/3.3V ; -- ; ; -- ; -- ; +; 64 ; 51 ; 2 ; C25M ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 65 ; ; ; GNDINT ; gnd ; ; ; -- ; ; -- ; -- ; +; 66 ; 52 ; 2 ; RCKE ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 67 ; 53 ; 2 ; nRCS ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 68 ; 54 ; 2 ; SA[12] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 69 ; 55 ; 2 ; SBA[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 70 ; 56 ; 2 ; SA[11] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 71 ; 57 ; 2 ; SBA[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 72 ; 58 ; 2 ; SA[9] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 73 ; 59 ; 2 ; SA[10] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 74 ; 60 ; 2 ; SA[8] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 75 ; 61 ; 2 ; SA[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 76 ; 62 ; 2 ; SA[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 77 ; 63 ; 2 ; SA[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 78 ; 64 ; 2 ; SA[7] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 79 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; +; 80 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 81 ; 65 ; 2 ; SA[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 82 ; 66 ; 2 ; SA[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 83 ; 67 ; 2 ; SA[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 84 ; 68 ; 2 ; SA[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 85 ; 69 ; 2 ; DQML ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 86 ; 70 ; 2 ; RD[0] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; yes ; Off ; +; 87 ; 71 ; 2 ; RD[1] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; yes ; Off ; +; 88 ; 72 ; 2 ; RD[2] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; yes ; Off ; +; 89 ; 73 ; 2 ; RD[3] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; yes ; Off ; +; 90 ; 74 ; 2 ; RD[4] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; yes ; Off ; +; 91 ; 75 ; 2 ; RD[5] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; yes ; Off ; +; 92 ; 76 ; 2 ; RD[6] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; yes ; Off ; +; 93 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; +; 94 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 95 ; 77 ; 2 ; SetFW[1] ; input ; 3.3V Schmitt Trigger Input ; ; Column I/O ; Y ; no ; On ; +; 96 ; 78 ; 2 ; SetFW[0] ; input ; 3.3V Schmitt Trigger Input ; ; Column I/O ; Y ; no ; On ; +; 97 ; 79 ; 2 ; RA[2] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 98 ; 80 ; 2 ; RA[1] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 99 ; 81 ; 2 ; RD[7] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; yes ; Off ; +; 100 ; 82 ; 2 ; RA[0] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; ++----------+------------+----------+----------------+--------+----------------------------+-----------+------------+-----------------+----------+--------------+ Note: Pin directions (input, output or bidir) are based on device operating in user mode. @@ -432,7 +432,7 @@ Note: User assignments will override these defaults. The user specified values a +----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+ ; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ; +----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+ -; |GR8RAM ; 230 (230) ; 109 ; 0 ; 80 ; 0 ; 121 (121) ; 1 (1) ; 108 (108) ; 37 (37) ; 10 (10) ; |GR8RAM ; work ; +; |GR8RAM ; 234 (234) ; 121 ; 0 ; 80 ; 0 ; 113 (113) ; 1 (1) ; 120 (120) ; 37 (37) ; 22 (22) ; |GR8RAM ; work ; +----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. @@ -444,12 +444,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +----------+----------+---------------+ ; INTin ; Input ; (1) ; ; DMAin ; Input ; (1) ; -; nIOSTRB ; Input ; (1) ; -; nIOSEL ; Input ; (1) ; -; nDEVSEL ; Input ; (1) ; ; PHI0 ; Input ; (0) ; ; nWE ; Input ; (1) ; -; C25M ; Input ; (0) ; ; RA[0] ; Input ; (1) ; ; RA[1] ; Input ; (1) ; ; RA[2] ; Input ; (1) ; @@ -461,7 +457,10 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; RA[8] ; Input ; (1) ; ; RA[9] ; Input ; (1) ; ; RA[10] ; Input ; (1) ; -; nRES ; Input ; (1) ; +; nIOSTRB ; Input ; (1) ; +; nIOSEL ; Input ; (1) ; +; nDEVSEL ; Input ; (1) ; +; C25M ; Input ; (0) ; ; RA[11] ; Input ; (1) ; ; RA[14] ; Input ; (1) ; ; RA[15] ; Input ; (1) ; @@ -469,6 +468,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; RA[13] ; Input ; (1) ; ; SetFW[1] ; Input ; (1) ; ; SetFW[0] ; Input ; (1) ; +; nRES ; Input ; (1) ; ; MISO ; Input ; (1) ; ; nRESout ; Output ; -- ; ; INTout ; Output ; -- ; @@ -530,23 +530,21 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +-------------+-------------+---------+---------------------------------------+--------+----------------------+------------------+ ; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; +-------------+-------------+---------+---------------------------------------+--------+----------------------+------------------+ -; C25M ; PIN_64 ; 106 ; Clock ; yes ; Global Clock ; GCLK3 ; -; Decoder1~0 ; LC_X4_Y2_N5 ; 8 ; Clock enable ; no ; -- ; -- ; -; Equal2~0 ; LC_X3_Y2_N8 ; 19 ; Clock enable ; no ; -- ; -- ; -; FCKOE ; LC_X6_Y4_N4 ; 2 ; Output enable ; no ; -- ; -- ; -; IOROMRES ; LC_X2_Y3_N8 ; 1 ; Async. clear ; no ; -- ; -- ; -; MOSIOE ; LC_X6_Y4_N0 ; 1 ; Output enable ; no ; -- ; -- ; -; PHI0 ; PIN_41 ; 5 ; Clock ; yes ; Global Clock ; GCLK1 ; -; PS[0] ; LC_X4_Y2_N2 ; 44 ; Clock enable, Sync. clear, Sync. load ; no ; -- ; -- ; -; PS[2] ; LC_X4_Y2_N7 ; 26 ; Sync. clear, Sync. load ; no ; -- ; -- ; -; SDOE ; LC_X4_Y1_N6 ; 8 ; Output enable ; no ; -- ; -- ; -; SetFWLoaded ; LC_X4_Y2_N6 ; 2 ; Clock enable ; no ; -- ; -- ; -; always7~1 ; LC_X2_Y3_N1 ; 2 ; Clock enable ; no ; -- ; -- ; -; always9~2 ; LC_X2_Y2_N9 ; 8 ; Sync. load ; no ; -- ; -- ; -; always9~3 ; LC_X2_Y1_N8 ; 9 ; Sync. load ; no ; -- ; -- ; -; always9~4 ; LC_X7_Y2_N8 ; 9 ; Sync. load ; no ; -- ; -- ; -; comb~1 ; LC_X5_Y1_N6 ; 9 ; Output enable ; no ; -- ; -- ; -; nRESr ; LC_X2_Y3_N4 ; 29 ; Async. clear ; yes ; Global Clock ; GCLK2 ; +; C25M ; PIN_64 ; 107 ; Clock ; yes ; Global Clock ; GCLK3 ; +; Equal20~0 ; LC_X7_Y2_N8 ; 8 ; Clock enable ; no ; -- ; -- ; +; Equal2~1 ; LC_X3_Y2_N5 ; 19 ; Clock enable ; no ; -- ; -- ; +; FCKOE ; LC_X2_Y2_N8 ; 2 ; Output enable ; no ; -- ; -- ; +; MOSIOE ; LC_X2_Y2_N4 ; 1 ; Output enable ; no ; -- ; -- ; +; PHI0 ; PIN_41 ; 16 ; Clock ; yes ; Global Clock ; GCLK2 ; +; PS[0] ; LC_X3_Y2_N8 ; 46 ; Clock enable, Sync. clear, Sync. load ; no ; -- ; -- ; +; PS[2] ; LC_X3_Y2_N9 ; 27 ; Sync. clear, Sync. load ; no ; -- ; -- ; +; SDOE ; LC_X4_Y2_N1 ; 8 ; Output enable ; no ; -- ; -- ; +; SetFWLoaded ; LC_X7_Y3_N6 ; 2 ; Clock enable ; no ; -- ; -- ; +; always9~2 ; LC_X4_Y4_N9 ; 8 ; Sync. load ; no ; -- ; -- ; +; always9~3 ; LC_X4_Y4_N8 ; 9 ; Sync. load ; no ; -- ; -- ; +; always9~4 ; LC_X5_Y4_N8 ; 9 ; Sync. load ; no ; -- ; -- ; +; comb~2 ; LC_X3_Y3_N9 ; 9 ; Output enable ; no ; -- ; -- ; +; nRESr ; LC_X7_Y3_N2 ; 30 ; Async. clear, Sync. clear ; yes ; Global Clock ; GCLK1 ; +-------------+-------------+---------+---------------------------------------+--------+----------------------+------------------+ @@ -555,9 +553,9 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +-------+-------------+---------+----------------------+------------------+ ; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; +-------+-------------+---------+----------------------+------------------+ -; C25M ; PIN_64 ; 106 ; Global Clock ; GCLK3 ; -; PHI0 ; PIN_41 ; 5 ; Global Clock ; GCLK1 ; -; nRESr ; LC_X2_Y3_N4 ; 29 ; Global Clock ; GCLK2 ; +; C25M ; PIN_64 ; 107 ; Global Clock ; GCLK3 ; +; PHI0 ; PIN_41 ; 16 ; Global Clock ; GCLK2 ; +; nRESr ; LC_X7_Y3_N2 ; 30 ; Global Clock ; GCLK1 ; +-------+-------------+---------+----------------------+------------------+ @@ -566,46 +564,46 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +---------------------+-----------+ ; Name ; Fan-Out ; +---------------------+-----------+ -; PS[0] ; 45 ; -; PS[1] ; 30 ; -; PS[3] ; 28 ; -; PS[2] ; 26 ; -; Equal2~0 ; 19 ; -; IS.state_bit_0 ; 19 ; -; IS.110~0 ; 17 ; -; RAMSpecSELr ; 16 ; -; IS.state_bit_1 ; 16 ; +; PS[0] ; 47 ; +; PS[1] ; 33 ; +; PS[3] ; 29 ; +; PS[2] ; 27 ; +; IS.state_bit_0 ; 20 ; +; Equal2~1 ; 19 ; +; IS.state_bit_1 ; 17 ; +; IS.110~0 ; 16 ; +; RAMSpecSEL~0 ; 16 ; ; LS[0] ; 13 ; -; RA[0] ; 9 ; ; RDD[1]~23 ; 9 ; ; always9~4 ; 9 ; ; always9~3 ; 9 ; -; comb~1 ; 9 ; -; RA[1] ; 8 ; +; comb~2 ; 9 ; ; RDD[1]~22 ; 8 ; -; Decoder1~0 ; 8 ; +; Equal20~0 ; 8 ; ; SDOE ; 8 ; ; always9~2 ; 8 ; ; IS.state_bit_2 ; 8 ; ; LS[2] ; 8 ; +; RAr[0] ; 8 ; +; SA[1]~6 ; 7 ; ; SetFWr[1] ; 7 ; -; SA[0]~8 ; 7 ; +; RAr[1] ; 7 ; ; RD[7]~7 ; 6 ; -; SA[3]~17 ; 6 ; -; SA[3]~10 ; 6 ; ; SA[3]~9 ; 6 ; +; SA[3]~8 ; 6 ; +; SA[3]~7 ; 6 ; ; LS[1] ; 6 ; +; Equal19~0 ; 6 ; ; RD[0]~0 ; 5 ; -; RA[3] ; 5 ; -; RA[2] ; 5 ; ; RDD[4]~12 ; 5 ; -; RAMRegSpecSEL~0 ; 5 ; -; REGSpecSEL~1 ; 5 ; ; Addr[0] ; 5 ; ; LS[6]~17 ; 5 ; +; SA[1]~5 ; 5 ; ; LS[1]~3 ; 5 ; -; Mux14~3 ; 5 ; +; Mux14~2 ; 5 ; ; Addr[23] ; 5 ; +; always9~0 ; 5 ; +; RAMRegSpecSEL~0 ; 5 ; ; RD[6]~6 ; 4 ; ; RD[5]~5 ; 4 ; ; RD[4]~4 ; 4 ; @@ -613,10 +611,11 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; RD[2]~2 ; 4 ; ; RD[1]~1 ; 4 ; ; nDEVSEL ; 4 ; -; always9~6 ; 4 ; ; RDD[4]~13 ; 4 ; +; always9~1 ; 4 ; ; LS[13] ; 4 ; ; Equal3~2 ; 4 ; +; nRCS~1 ; 4 ; ; Addr[9] ; 4 ; ; Addr[8] ; 4 ; ; Addr[7] ; 4 ; @@ -629,20 +628,16 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; LS[4] ; 4 ; ; Addr[13] ; 4 ; ; Addr[3] ; 4 ; +; RAr[3] ; 4 ; ; Addr[12] ; 4 ; ; Addr[2] ; 4 ; ; Addr[11] ; 4 ; -; SA[0]~7 ; 4 ; ; Addr[1] ; 4 ; ; Addr[10] ; 4 ; -; always7~0 ; 4 ; -; RA[11] ; 3 ; -; RA[10] ; 3 ; -; RA[9] ; 3 ; -; RA[8] ; 3 ; -; RA[7] ; 3 ; -; nWE ; 3 ; -; SA[0]~16 ; 3 ; +; RAr[2] ; 4 ; +; nIOSEL ; 3 ; +; nIOSTRB ; 3 ; +; SA[1]~15 ; 3 ; ; WRD[5] ; 3 ; ; WRD[4] ; 3 ; ; WRD[3] ; 3 ; @@ -652,12 +647,13 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; Equal4~0 ; 3 ; ; Equal5~0 ; 3 ; ; Equal3~3 ; 3 ; -; nRCS~1 ; 3 ; +; IS.111~0 ; 3 ; +; nWEr ; 3 ; ; Addr[22] ; 3 ; ; Addr[21] ; 3 ; ; Addr[20]~41 ; 3 ; ; Addr[20] ; 3 ; -; SA~11 ; 3 ; +; SA~10 ; 3 ; ; Equal1~0 ; 3 ; ; Addr[19] ; 3 ; ; LS[9] ; 3 ; @@ -672,47 +668,54 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; LS[12] ; 3 ; ; Addr[12]~11 ; 3 ; ; LS[11] ; 3 ; -; SA[0]~5 ; 3 ; +; SA[1]~3 ; 3 ; ; LS[10] ; 3 ; -; SA[0]~4 ; 3 ; +; SA[1]~2 ; 3 ; +; IOROMEN ; 3 ; +; RA[10] ; 2 ; +; RA[9] ; 2 ; +; RA[8] ; 2 ; +; RA[7] ; 2 ; ; RA[6] ; 2 ; ; RA[5] ; 2 ; ; RA[4] ; 2 ; -; nIOSEL ; 2 ; -; nIOSTRB ; 2 ; -; PHI0r1 ; 2 ; +; RA[3] ; 2 ; +; RA[2] ; 2 ; +; RA[1] ; 2 ; +; RA[0] ; 2 ; +; nWE ; 2 ; ; WRD[7] ; 2 ; ; WRD[6] ; 2 ; ; AddrIncL ; 2 ; ; AddrIncM ; 2 ; ; SetFWLoaded ; 2 ; -; RAMRegSpecSEL ; 2 ; -; Equal9~0 ; 2 ; -; REGSpecSEL~0 ; 2 ; ; IS.state_bit_1~3 ; 2 ; ; IS.state_bit_1~0 ; 2 ; ; Equal5~1 ; 2 ; ; FCKOE ; 2 ; -; PHI0r2 ; 2 ; +; PS~0 ; 2 ; ; Equal1~1 ; 2 ; ; DQMH~0 ; 2 ; -; Mux12~2 ; 2 ; -; IS.111~0 ; 2 ; +; Mux12~1 ; 2 ; +; nRCS~5 ; 2 ; ; nRCS~4 ; 2 ; -; ROMSpecRDr ; 2 ; -; nRCS~3 ; 2 ; -; nWEr ; 2 ; +; nRCS~2 ; 2 ; +; RAr[9] ; 2 ; ; Bank ; 2 ; +; RAr[11] ; 2 ; ; LS[11]~5 ; 2 ; -; SA[0]~6 ; 2 ; +; SA[1]~4 ; 2 ; +; RAr[10] ; 2 ; ; nRESf[2] ; 2 ; -; Mux14~1 ; 2 ; -; Mux14~0 ; 2 ; ; nRESf[1] ; 2 ; -; always7~1 ; 2 ; ; nRESf[0] ; 2 ; -; comb~2 ; 2 ; -; IOROMEN ; 2 ; +; RAMRegSpecSEL ; 2 ; +; CXXXr ; 2 ; +; REGEN ; 2 ; +; RAr[8] ; 2 ; +; Equal9~0 ; 2 ; +; RAr[7] ; 2 ; +; always8~0 ; 2 ; ; nRESout~reg0 ; 2 ; ; MOSI~0 ; 1 ; ; SD[7]~7 ; 1 ; @@ -724,23 +727,22 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; SD[1]~1 ; 1 ; ; SD[0]~0 ; 1 ; ; MISO ; 1 ; +; nRES ; 1 ; ; SetFW[0] ; 1 ; ; SetFW[1] ; 1 ; ; RA[13] ; 1 ; ; RA[12] ; 1 ; ; RA[15] ; 1 ; ; RA[14] ; 1 ; -; nRES ; 1 ; +; RA[11] ; 1 ; ; DMAin ; 1 ; ; INTin ; 1 ; -; Mux11~6 ; 1 ; -; Mux13~2 ; 1 ; ; Mux2~3 ; 1 ; ; SetFWr[0] ; 1 ; ; Mux2~2 ; 1 ; ; Mux2~1 ; 1 ; ; Mux2~0 ; 1 ; -; SA[0]~15 ; 1 ; +; SA[1]~14 ; 1 ; ; RDD~20 ; 1 ; ; RDD~18 ; 1 ; ; RDD~16 ; 1 ; @@ -766,12 +768,10 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; RDD[0] ; 1 ; ; MOSIOE ; 1 ; ; IS.101~0 ; 1 ; -; ROMSpecRD~0 ; 1 ; ; IS.state_bit_2~1 ; 1 ; ; IS.state_bit_2~0 ; 1 ; ; Equal3~4 ; 1 ; ; AddrIncH ; 1 ; -; REGEN ; 1 ; ; IS.state_bit_1~2 ; 1 ; ; IS.state_bit_1~1 ; 1 ; ; IS.state_bit_0~5 ; 1 ; @@ -781,19 +781,21 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; Equal3~0 ; 1 ; ; FCKout ; 1 ; ; FCS ; 1 ; -; Mux11~4 ; 1 ; +; Equal2~0 ; 1 ; ; Mux11~3 ; 1 ; ; Mux11~2 ; 1 ; -; PS~0 ; 1 ; +; Mux11~1 ; 1 ; +; PHI0r1 ; 1 ; +; Mux11~0 ; 1 ; ; Selector2~0 ; 1 ; ; Selector1~0 ; 1 ; ; Addr[0]~47COUT1_92 ; 1 ; ; Addr[0]~47 ; 1 ; ; Selector0~0 ; 1 ; -; Mux12~3 ; 1 ; -; Mux12~1 ; 1 ; +; Mux12~2 ; 1 ; +; nRCS~3 ; 1 ; ; Mux12~0 ; 1 ; -; nRCS~2 ; 1 ; +; IS.000~0 ; 1 ; ; nRCS~0 ; 1 ; ; Addr[22]~45COUT1_78 ; 1 ; ; Addr[22]~45 ; 1 ; @@ -832,6 +834,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; Mux19~2 ; 1 ; ; Addr[6]~25COUT1_102 ; 1 ; ; Addr[6]~25 ; 1 ; +; RAr[6] ; 1 ; ; Mux19~1 ; 1 ; ; Mux19~0 ; 1 ; ; Mux20~2 ; 1 ; @@ -846,6 +849,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; Mux21~2 ; 1 ; ; LS[4]~13COUT1_42 ; 1 ; ; LS[4]~13 ; 1 ; +; RAr[4] ; 1 ; ; Mux21~1 ; 1 ; ; Mux21~0 ; 1 ; ; Addr[13]~15COUT1_88 ; 1 ; @@ -867,6 +871,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; LS[2]~7 ; 1 ; ; Mux23~2 ; 1 ; ; Mux23~1 ; 1 ; +; nRESf[3] ; 1 ; ; Mux23~0 ; 1 ; ; Addr[11]~7COUT1_86 ; 1 ; ; Addr[11]~7 ; 1 ; @@ -880,12 +885,15 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; LS[10]~1 ; 1 ; ; Addr[10]~3COUT1_84 ; 1 ; ; Addr[10]~3 ; 1 ; -; Mux14~4 ; 1 ; -; nRESf[3] ; 1 ; -; Mux14~2 ; 1 ; -; IOROMRES ; 1 ; -; comb~4 ; 1 ; -; comb~3 ; 1 ; +; Mux13~0 ; 1 ; +; Mux14~3 ; 1 ; +; Mux14~1 ; 1 ; +; Mux14~0 ; 1 ; +; always8~4 ; 1 ; +; RAr[5] ; 1 ; +; always8~3 ; 1 ; +; always8~2 ; 1 ; +; always8~1 ; 1 ; ; RCKE~reg0 ; 1 ; ; DQMH~reg0 ; 1 ; ; DQML~reg0 ; 1 ; @@ -908,6 +916,11 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; SA[0]~reg0 ; 1 ; ; SBA[1]~reg0 ; 1 ; ; SBA[0]~reg0 ; 1 ; +; comb~1 ; 1 ; +; Equal16~2 ; 1 ; +; Equal16~1 ; 1 ; +; Equal16~0 ; 1 ; +; PHI0r2 ; 1 ; ; comb~0 ; 1 ; +---------------------+-----------+ @@ -917,20 +930,20 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +-----------------------------+--------------------+ ; Other Routing Resource Type ; Usage ; +-----------------------------+--------------------+ -; C4s ; 234 / 784 ( 30 % ) ; -; Direct links ; 69 / 888 ( 8 % ) ; +; C4s ; 226 / 784 ( 29 % ) ; +; Direct links ; 67 / 888 ( 8 % ) ; ; Global clocks ; 3 / 4 ( 75 % ) ; -; LAB clocks ; 12 / 32 ( 38 % ) ; -; LUT chains ; 39 / 216 ( 18 % ) ; -; Local interconnects ; 436 / 888 ( 49 % ) ; -; R4s ; 282 / 704 ( 40 % ) ; +; LAB clocks ; 14 / 32 ( 44 % ) ; +; LUT chains ; 24 / 216 ( 11 % ) ; +; Local interconnects ; 434 / 888 ( 49 % ) ; +; R4s ; 255 / 704 ( 36 % ) ; +-----------------------------+--------------------+ +---------------------------------------------------------------------------+ ; LAB Logic Elements ; +--------------------------------------------+------------------------------+ -; Number of Logic Elements (Average = 9.58) ; Number of LABs (Total = 24) ; +; Number of Logic Elements (Average = 9.75) ; Number of LABs (Total = 24) ; +--------------------------------------------+------------------------------+ ; 1 ; 0 ; ; 2 ; 0 ; @@ -938,32 +951,31 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; 4 ; 0 ; ; 5 ; 0 ; ; 6 ; 0 ; -; 7 ; 0 ; -; 8 ; 3 ; -; 9 ; 4 ; -; 10 ; 17 ; +; 7 ; 1 ; +; 8 ; 1 ; +; 9 ; 1 ; +; 10 ; 21 ; +--------------------------------------------+------------------------------+ +-------------------------------------------------------------------+ ; LAB-wide Signals ; +------------------------------------+------------------------------+ -; LAB-wide Signals (Average = 1.83) ; Number of LABs (Total = 24) ; +; LAB-wide Signals (Average = 1.71) ; Number of LABs (Total = 24) ; +------------------------------------+------------------------------+ -; 1 Async. clear ; 7 ; -; 1 Clock ; 22 ; -; 1 Clock enable ; 6 ; -; 1 Sync. clear ; 4 ; -; 1 Sync. load ; 2 ; -; 2 Clock enables ; 1 ; -; 2 Clocks ; 2 ; +; 1 Async. clear ; 3 ; +; 1 Clock ; 19 ; +; 1 Clock enable ; 5 ; +; 1 Sync. clear ; 6 ; +; 1 Sync. load ; 3 ; +; 2 Clocks ; 5 ; +------------------------------------+------------------------------+ +-----------------------------------------------------------------------------+ ; LAB Signals Sourced ; +----------------------------------------------+------------------------------+ -; Number of Signals Sourced (Average = 10.04) ; Number of LABs (Total = 24) ; +; Number of Signals Sourced (Average = 10.67) ; Number of LABs (Total = 24) ; +----------------------------------------------+------------------------------+ ; 0 ; 0 ; ; 1 ; 0 ; @@ -972,34 +984,35 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; 4 ; 0 ; ; 5 ; 0 ; ; 6 ; 0 ; -; 7 ; 0 ; -; 8 ; 3 ; -; 9 ; 4 ; -; 10 ; 12 ; +; 7 ; 1 ; +; 8 ; 0 ; +; 9 ; 1 ; +; 10 ; 16 ; ; 11 ; 2 ; -; 12 ; 2 ; -; 13 ; 0 ; -; 14 ; 0 ; +; 12 ; 0 ; +; 13 ; 1 ; +; 14 ; 1 ; ; 15 ; 1 ; +; 16 ; 1 ; +----------------------------------------------+------------------------------+ +--------------------------------------------------------------------------------+ ; LAB Signals Sourced Out ; +-------------------------------------------------+------------------------------+ -; Number of Signals Sourced Out (Average = 6.92) ; Number of LABs (Total = 24) ; +; Number of Signals Sourced Out (Average = 7.54) ; Number of LABs (Total = 24) ; +-------------------------------------------------+------------------------------+ ; 0 ; 0 ; ; 1 ; 0 ; -; 2 ; 0 ; -; 3 ; 3 ; -; 4 ; 4 ; -; 5 ; 2 ; +; 2 ; 1 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 4 ; ; 6 ; 2 ; -; 7 ; 1 ; -; 8 ; 3 ; -; 9 ; 3 ; -; 10 ; 5 ; +; 7 ; 4 ; +; 8 ; 4 ; +; 9 ; 4 ; +; 10 ; 4 ; ; 11 ; 1 ; +-------------------------------------------------+------------------------------+ @@ -1007,30 +1020,35 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +-----------------------------------------------------------------------------+ ; LAB Distinct Inputs ; +----------------------------------------------+------------------------------+ -; Number of Distinct Inputs (Average = 15.54) ; Number of LABs (Total = 24) ; +; Number of Distinct Inputs (Average = 16.08) ; Number of LABs (Total = 24) ; +----------------------------------------------+------------------------------+ ; 0 ; 0 ; ; 1 ; 0 ; ; 2 ; 0 ; ; 3 ; 0 ; -; 4 ; 1 ; +; 4 ; 0 ; ; 5 ; 0 ; -; 6 ; 0 ; +; 6 ; 1 ; ; 7 ; 0 ; ; 8 ; 1 ; -; 9 ; 0 ; -; 10 ; 0 ; +; 9 ; 1 ; +; 10 ; 3 ; ; 11 ; 0 ; -; 12 ; 3 ; +; 12 ; 1 ; ; 13 ; 2 ; -; 14 ; 2 ; +; 14 ; 0 ; ; 15 ; 3 ; -; 16 ; 2 ; -; 17 ; 2 ; -; 18 ; 1 ; -; 19 ; 2 ; -; 20 ; 1 ; -; 21 ; 4 ; +; 16 ; 1 ; +; 17 ; 1 ; +; 18 ; 2 ; +; 19 ; 1 ; +; 20 ; 2 ; +; 21 ; 0 ; +; 22 ; 2 ; +; 23 ; 0 ; +; 24 ; 0 ; +; 25 ; 0 ; +; 26 ; 3 ; +----------------------------------------------+------------------------------+ @@ -1064,46 +1082,45 @@ Info (176444): Device migration not selected. If you intend to use device migrat Info (176445): Device EPM570T100C5 is compatible Info (176445): Device EPM570T100I5 is compatible Info (176445): Device EPM570T100A5 is compatible -Critical Warning (332012): Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. -Info (332144): No user constrained base clocks found in the design -Info (332128): Timing requirements not specified -- optimizing circuit to achieve the following default global requirements - Info (332127): Assuming a default timing requirement +Info (332104): Reading SDC File: 'GR8RAM.sdc' +Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements Info (332111): Found 2 clocks Info (332111): Period Clock Name Info (332111): ======== ============ - Info (332111): 1.000 C25M - Info (332111): 1.000 PHI0 + Info (332111): 40.000 C25M + Info (332111): 978.000 PHI0 Info (186079): Completed User Assigned Global Signals Promotion Operation Info (186215): Automatically promoted signal "C25M" to use Global clock in PIN 64 Info (186216): Automatically promoted some destinations of signal "PHI0" to use Global clock - Info (186217): Destination "comb~1" may be non-global or may not use global clock + Info (186217): Destination "comb~0" may be non-global or may not use global clock Info (186217): Destination "PHI0r1" may be non-global or may not use global clock Info (186228): Pin "PHI0" drives global clock, but is not placed in a dedicated clock pin position -Info (186215): Automatically promoted signal "nRESr" to use Global clock +Info (186216): Automatically promoted some destinations of signal "nRESr" to use Global clock + Info (186217): Destination "IOROMEN" may be non-global or may not use global clock Info (186079): Completed Auto Global Promotion Operation Info (176234): Starting register packing Info (186468): Started processing fast register assignments Info (186469): Finished processing fast register assignments Info (176235): Finished register packing -Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01 +Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00 Info (170189): Fitter placement preparation operations beginning -Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01 +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 Info (170191): Fitter placement operations beginning Info (170137): Fitter placement was successful -Info (170192): Fitter placement operations ending: elapsed time is 00:00:02 +Info (170192): Fitter placement operations ending: elapsed time is 00:00:01 Info (170193): Fitter routing operations beginning -Info (170195): Router estimated average interconnect usage is 36% of the available device resources - Info (170196): Router estimated peak interconnect usage is 36% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5 +Info (170195): Router estimated average interconnect usage is 34% of the available device resources + Info (170196): Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5 Info (170194): Fitter routing operations ending: elapsed time is 00:00:01 -Info (11888): Total time spent on timing analysis during the Fitter is 0.56 seconds. +Info (11888): Total time spent on timing analysis during the Fitter is 0.36 seconds. Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00 Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'. Info (144001): Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg -Info: Quartus II 32-bit Fitter was successful. 0 errors, 3 warnings - Info: Peak virtual memory: 382 megabytes - Info: Processing ended: Tue Apr 20 04:19:53 2021 - Info: Elapsed time: 00:00:08 - Info: Total CPU time (on all processors): 00:00:08 +Info: Quartus II 32-bit Fitter was successful. 0 errors, 2 warnings + Info: Peak virtual memory: 383 megabytes + Info: Processing ended: Wed Apr 21 20:01:56 2021 + Info: Elapsed time: 00:00:07 + Info: Total CPU time (on all processors): 00:00:07 +----------------------------+ diff --git a/cpld/output_files/GR8RAM.fit.summary b/cpld/output_files/GR8RAM.fit.summary index 18cf322..9fb4782 100755 --- a/cpld/output_files/GR8RAM.fit.summary +++ b/cpld/output_files/GR8RAM.fit.summary @@ -1,11 +1,11 @@ -Fitter Status : Successful - Tue Apr 20 04:19:53 2021 +Fitter Status : Successful - Wed Apr 21 20:01:56 2021 Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition Revision Name : GR8RAM Top-level Entity Name : GR8RAM Family : MAX II Device : EPM240T100C5 Timing Models : Final -Total logic elements : 230 / 240 ( 96 % ) +Total logic elements : 234 / 240 ( 98 % ) Total pins : 80 / 80 ( 100 % ) Total virtual pins : 0 UFM blocks : 0 / 1 ( 0 % ) diff --git a/cpld/output_files/GR8RAM.flow.rpt b/cpld/output_files/GR8RAM.flow.rpt index c322ed2..53c1394 100755 --- a/cpld/output_files/GR8RAM.flow.rpt +++ b/cpld/output_files/GR8RAM.flow.rpt @@ -1,5 +1,5 @@ Flow report for GR8RAM -Tue Apr 20 04:20:05 2021 +Wed Apr 21 20:02:07 2021 Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition @@ -40,14 +40,14 @@ applicable agreement for further details. +-----------------------------------------------------------------------------+ ; Flow Summary ; +---------------------------+-------------------------------------------------+ -; Flow Status ; Successful - Tue Apr 20 04:19:58 2021 ; +; Flow Status ; Successful - Wed Apr 21 20:02:00 2021 ; ; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; ; Revision Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ; ; Family ; MAX II ; ; Device ; EPM240T100C5 ; ; Timing Models ; Final ; -; Total logic elements ; 230 / 240 ( 96 % ) ; +; Total logic elements ; 234 / 240 ( 98 % ) ; ; Total pins ; 80 / 80 ( 100 % ) ; ; Total virtual pins ; 0 ; ; UFM blocks ; 0 / 1 ( 0 % ) ; @@ -59,7 +59,7 @@ applicable agreement for further details. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 04/20/2021 04:19:41 ; +; Start date & time ; 04/21/2021 20:01:44 ; ; Main task ; Compilation ; ; Revision Name ; GR8RAM ; +-------------------+---------------------+ @@ -75,7 +75,7 @@ applicable agreement for further details. ; ALM_REGISTER_PACKING_EFFORT ; High ; Medium ; -- ; -- ; ; AUTO_PACKED_REGISTERS_MAXII ; Minimize Area ; Auto ; -- ; -- ; ; AUTO_RESOURCE_SHARING ; On ; Off ; -- ; -- ; -; COMPILER_SIGNATURE_ID ; 44085571633675.161890678100176 ; -- ; -- ; -- ; +; COMPILER_SIGNATURE_ID ; 44085571633675.161904970303144 ; -- ; -- ; -- ; ; FINAL_PLACEMENT_OPTIMIZATION ; Always ; Automatically ; -- ; -- ; ; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ; ; IOBANK_VCCIO ; 3.3V ; -- ; -- ; 1 ; @@ -102,11 +102,11 @@ applicable agreement for further details. +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:05 ; 1.0 ; 301 MB ; 00:00:04 ; -; Fitter ; 00:00:08 ; 1.2 ; 382 MB ; 00:00:07 ; +; Analysis & Synthesis ; 00:00:05 ; 1.0 ; 301 MB ; 00:00:05 ; +; Fitter ; 00:00:07 ; 1.4 ; 383 MB ; 00:00:07 ; ; Assembler ; 00:00:02 ; 1.0 ; 292 MB ; 00:00:02 ; ; TimeQuest Timing Analyzer ; 00:00:05 ; 1.0 ; 278 MB ; 00:00:04 ; -; Total ; 00:00:20 ; -- ; -- ; 00:00:17 ; +; Total ; 00:00:19 ; -- ; -- ; 00:00:18 ; +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ diff --git a/cpld/output_files/GR8RAM.jdi b/cpld/output_files/GR8RAM.jdi index 5414390..f1d936f 100755 --- a/cpld/output_files/GR8RAM.jdi +++ b/cpld/output_files/GR8RAM.jdi @@ -1,6 +1,6 @@ - + diff --git a/cpld/output_files/GR8RAM.map.rpt b/cpld/output_files/GR8RAM.map.rpt index 008860b..82599fe 100755 --- a/cpld/output_files/GR8RAM.map.rpt +++ b/cpld/output_files/GR8RAM.map.rpt @@ -1,5 +1,5 @@ Analysis & Synthesis report for GR8RAM -Tue Apr 20 04:19:44 2021 +Wed Apr 21 20:01:47 2021 Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition @@ -45,12 +45,12 @@ applicable agreement for further details. +-------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +-----------------------------+-------------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Tue Apr 20 04:19:44 2021 ; +; Analysis & Synthesis Status ; Successful - Wed Apr 21 20:01:47 2021 ; ; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; ; Revision Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ; ; Family ; MAX II ; -; Total logic elements ; 241 ; +; Total logic elements ; 257 ; ; Total pins ; 80 ; ; Total virtual pins ; 0 ; ; UFM blocks ; 0 / 1 ( 0 % ) ; @@ -161,32 +161,32 @@ applicable agreement for further details. +---------------------------------------------+-------+ ; Resource ; Usage ; +---------------------------------------------+-------+ -; Total logic elements ; 241 ; -; -- Combinational with no register ; 132 ; -; -- Register only ; 12 ; +; Total logic elements ; 257 ; +; -- Combinational with no register ; 136 ; +; -- Register only ; 24 ; ; -- Combinational with a register ; 97 ; ; ; ; ; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 119 ; -; -- 3 input functions ; 38 ; -; -- 2 input functions ; 69 ; +; -- 4 input functions ; 126 ; +; -- 3 input functions ; 41 ; +; -- 2 input functions ; 65 ; ; -- 1 input functions ; 0 ; -; -- 0 input functions ; 3 ; +; -- 0 input functions ; 1 ; ; ; ; ; Logic elements by mode ; ; -; -- normal mode ; 208 ; +; -- normal mode ; 224 ; ; -- arithmetic mode ; 33 ; ; -- qfbk mode ; 0 ; ; -- register cascade mode ; 0 ; -; -- synchronous clear/load mode ; 44 ; -; -- asynchronous clear/load mode ; 30 ; +; -- synchronous clear/load mode ; 45 ; +; -- asynchronous clear/load mode ; 29 ; ; ; ; -; Total registers ; 109 ; +; Total registers ; 121 ; ; Total logic cells in carry chains ; 37 ; ; I/O pins ; 80 ; ; Maximum fan-out node ; C25M ; -; Maximum fan-out ; 106 ; -; Total fan-out ; 1044 ; +; Maximum fan-out ; 107 ; +; Total fan-out ; 1095 ; ; Average fan-out ; 3.25 ; +---------------------------------------------+-------+ @@ -196,7 +196,7 @@ applicable agreement for further details. +----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+ ; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ; +----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+ -; |GR8RAM ; 241 (241) ; 109 ; 0 ; 80 ; 0 ; 132 (132) ; 12 (12) ; 97 (97) ; 37 (37) ; 0 (0) ; |GR8RAM ; work ; +; |GR8RAM ; 257 (257) ; 121 ; 0 ; 80 ; 0 ; 136 (136) ; 24 (24) ; 97 (97) ; 37 (37) ; 0 (0) ; |GR8RAM ; work ; +----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. @@ -231,12 +231,12 @@ Encoding Type: Minimal Bits +----------------------------------------------+-------+ ; Statistic ; Value ; +----------------------------------------------+-------+ -; Total registers ; 109 ; -; Number of registers using Synchronous Clear ; 11 ; +; Total registers ; 121 ; +; Number of registers using Synchronous Clear ; 12 ; ; Number of registers using Synchronous Load ; 33 ; -; Number of registers using Asynchronous Clear ; 30 ; +; Number of registers using Asynchronous Clear ; 29 ; ; Number of registers using Asynchronous Load ; 0 ; -; Number of registers using Clock Enable ; 26 ; +; Number of registers using Clock Enable ; 24 ; ; Number of registers using Preset ; 0 ; +----------------------------------------------+-------+ @@ -265,7 +265,7 @@ Encoding Type: Minimal Bits ; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |GR8RAM|PS[2] ; ; 5:1 ; 2 bits ; 6 LEs ; 2 LEs ; 4 LEs ; Yes ; |GR8RAM|SA[11]~reg0 ; ; 20:1 ; 6 bits ; 78 LEs ; 24 LEs ; 54 LEs ; Yes ; |GR8RAM|SA[3]~reg0 ; -; 20:1 ; 3 bits ; 39 LEs ; 18 LEs ; 21 LEs ; Yes ; |GR8RAM|SA[0]~reg0 ; +; 20:1 ; 3 bits ; 39 LEs ; 18 LEs ; 21 LEs ; Yes ; |GR8RAM|SA[1]~reg0 ; ; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |GR8RAM|WRD[7] ; ; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |GR8RAM|RDD[1] ; ; 5:1 ; 4 bits ; 12 LEs ; 8 LEs ; 4 LEs ; Yes ; |GR8RAM|RDD[4] ; @@ -280,7 +280,7 @@ Encoding Type: Minimal Bits Info: ******************************************************************* Info: Running Quartus II 32-bit Analysis & Synthesis Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - Info: Processing started: Tue Apr 20 04:19:39 2021 + Info: Processing started: Wed Apr 21 20:01:42 2021 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected Info (12021): Found 1 design units, including 1 entities, in source file gr8ram.v @@ -288,9 +288,9 @@ Info (12021): Found 1 design units, including 1 entities, in source file gr8ram. Info (12127): Elaborating entity "GR8RAM" for the top level hierarchy Warning (10230): Verilog HDL assignment warning at GR8RAM.v(42): truncated value with size 32 to match size of target (4) Warning (10230): Verilog HDL assignment warning at GR8RAM.v(47): truncated value with size 32 to match size of target (14) -Warning (10230): Verilog HDL assignment warning at GR8RAM.v(130): truncated value with size 32 to match size of target (8) -Warning (10230): Verilog HDL assignment warning at GR8RAM.v(138): truncated value with size 32 to match size of target (8) -Warning (10230): Verilog HDL assignment warning at GR8RAM.v(145): truncated value with size 32 to match size of target (8) +Warning (10230): Verilog HDL assignment warning at GR8RAM.v(134): truncated value with size 32 to match size of target (8) +Warning (10230): Verilog HDL assignment warning at GR8RAM.v(142): truncated value with size 32 to match size of target (8) +Warning (10230): Verilog HDL assignment warning at GR8RAM.v(149): truncated value with size 32 to match size of target (8) Info (17026): Resynthesizing 0 WYSIWYG logic cells and I/Os using "area" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched Warning (13024): Output pins are stuck at VCC or GND Warning (13410): Pin "nNMIout" is stuck at VCC @@ -301,17 +301,17 @@ Warning (13024): Output pins are stuck at VCC or GND Warning (13410): Pin "nDMAout" is stuck at VCC Warning (13410): Pin "RAdir" is stuck at VCC Info (17049): 1 registers lost all their fanouts during netlist optimizations. -Info (21057): Implemented 321 device resources after synthesis - the final resource count might be different +Info (21057): Implemented 337 device resources after synthesis - the final resource count might be different Info (21058): Implemented 28 input pins Info (21059): Implemented 35 output pins Info (21060): Implemented 17 bidirectional pins - Info (21061): Implemented 241 logic cells + Info (21061): Implemented 257 logic cells Info (144001): Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 13 warnings Info: Peak virtual memory: 301 megabytes - Info: Processing ended: Tue Apr 20 04:19:44 2021 + Info: Processing ended: Wed Apr 21 20:01:47 2021 Info: Elapsed time: 00:00:05 - Info: Total CPU time (on all processors): 00:00:04 + Info: Total CPU time (on all processors): 00:00:05 +------------------------------------------+ diff --git a/cpld/output_files/GR8RAM.map.smsg b/cpld/output_files/GR8RAM.map.smsg index ffbb919..91314af 100755 --- a/cpld/output_files/GR8RAM.map.smsg +++ b/cpld/output_files/GR8RAM.map.smsg @@ -1,2 +1,2 @@ -Warning (10273): Verilog HDL warning at GR8RAM.v(106): extended using "x" or "z" -Warning (10273): Verilog HDL warning at GR8RAM.v(282): extended using "x" or "z" +Warning (10273): Verilog HDL warning at GR8RAM.v(110): extended using "x" or "z" +Warning (10273): Verilog HDL warning at GR8RAM.v(286): extended using "x" or "z" diff --git a/cpld/output_files/GR8RAM.map.summary b/cpld/output_files/GR8RAM.map.summary index 8eeb674..15d05bc 100755 --- a/cpld/output_files/GR8RAM.map.summary +++ b/cpld/output_files/GR8RAM.map.summary @@ -1,9 +1,9 @@ -Analysis & Synthesis Status : Successful - Tue Apr 20 04:19:44 2021 +Analysis & Synthesis Status : Successful - Wed Apr 21 20:01:47 2021 Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition Revision Name : GR8RAM Top-level Entity Name : GR8RAM Family : MAX II -Total logic elements : 241 +Total logic elements : 257 Total pins : 80 Total virtual pins : 0 UFM blocks : 0 / 1 ( 0 % ) diff --git a/cpld/output_files/GR8RAM.pin b/cpld/output_files/GR8RAM.pin index 54ede08..1a08c4e 100755 --- a/cpld/output_files/GR8RAM.pin +++ b/cpld/output_files/GR8RAM.pin @@ -100,12 +100,12 @@ RA[12] : 35 : input : 3.3-V LVTTL : RA[13] : 36 : input : 3.3-V LVTTL : : 1 : Y RA[14] : 37 : input : 3.3-V LVTTL : : 1 : Y RA[15] : 38 : input : 3.3-V LVTTL : : 1 : Y -nIOSEL : 39 : input : 3.3-V LVTTL : : 1 : Y -nDEVSEL : 40 : input : 3.3-V LVTTL : : 1 : Y -PHI0 : 41 : input : 3.3-V LVTTL : : 1 : Y -nIOSTRB : 42 : input : 3.3-V LVTTL : : 1 : Y -nWE : 43 : input : 3.3-V LVTTL : : 1 : Y -nRES : 44 : input : 3.3-V LVTTL : : 1 : Y +nIOSEL : 39 : input : 3.3V Schmitt Trigger Input : : 1 : Y +nDEVSEL : 40 : input : 3.3V Schmitt Trigger Input : : 1 : Y +PHI0 : 41 : input : 3.3V Schmitt Trigger Input : : 1 : Y +nIOSTRB : 42 : input : 3.3V Schmitt Trigger Input : : 1 : Y +nWE : 43 : input : 3.3V Schmitt Trigger Input : : 1 : Y +nRES : 44 : input : 3.3V Schmitt Trigger Input : : 1 : Y VCCIO1 : 45 : power : : 3.3V : 1 : GNDIO : 46 : gnd : : : : SD[1] : 47 : bidir : 3.3-V LVTTL : : 1 : Y @@ -156,8 +156,8 @@ RD[5] : 91 : bidir : 3.3-V LVTTL : RD[6] : 92 : bidir : 3.3-V LVTTL : : 2 : Y GNDIO : 93 : gnd : : : : VCCIO2 : 94 : power : : 3.3V : 2 : -SetFW[1] : 95 : input : 3.3-V LVTTL : : 2 : Y -SetFW[0] : 96 : input : 3.3-V LVTTL : : 2 : Y +SetFW[1] : 95 : input : 3.3V Schmitt Trigger Input : : 2 : Y +SetFW[0] : 96 : input : 3.3V Schmitt Trigger Input : : 2 : Y RA[2] : 97 : input : 3.3-V LVTTL : : 2 : Y RA[1] : 98 : input : 3.3-V LVTTL : : 2 : Y RD[7] : 99 : bidir : 3.3-V LVTTL : : 2 : Y diff --git a/cpld/output_files/GR8RAM.pof b/cpld/output_files/GR8RAM.pof index 7723661..1f453df 100755 Binary files a/cpld/output_files/GR8RAM.pof and b/cpld/output_files/GR8RAM.pof differ diff --git a/cpld/output_files/GR8RAM.sta.rpt b/cpld/output_files/GR8RAM.sta.rpt index 2aa7fff..96e596b 100755 --- a/cpld/output_files/GR8RAM.sta.rpt +++ b/cpld/output_files/GR8RAM.sta.rpt @@ -1,5 +1,5 @@ TimeQuest Timing Analyzer report for GR8RAM -Tue Apr 20 04:20:05 2021 +Wed Apr 21 20:02:07 2021 Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition @@ -9,39 +9,38 @@ Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit 1. Legal Notice 2. TimeQuest Timing Analyzer Summary 3. Parallel Compilation - 4. Clocks - 5. Fmax Summary - 6. Setup Summary - 7. Hold Summary - 8. Recovery Summary - 9. Removal Summary - 10. Minimum Pulse Width Summary - 11. Setup: 'C25M' - 12. Setup: 'PHI0' - 13. Hold: 'PHI0' - 14. Hold: 'C25M' - 15. Recovery: 'C25M' - 16. Removal: 'C25M' - 17. Minimum Pulse Width: 'C25M' - 18. Minimum Pulse Width: 'PHI0' - 19. Setup Times - 20. Hold Times - 21. Clock to Output Times - 22. Minimum Clock to Output Times - 23. Propagation Delay - 24. Minimum Propagation Delay - 25. Output Enable Times - 26. Minimum Output Enable Times - 27. Output Disable Times - 28. Minimum Output Disable Times - 29. Setup Transfers - 30. Hold Transfers - 31. Recovery Transfers - 32. Removal Transfers - 33. Report TCCS - 34. Report RSKM - 35. Unconstrained Paths - 36. TimeQuest Timing Analyzer Messages + 4. SDC File List + 5. Clocks + 6. Fmax Summary + 7. Setup Summary + 8. Hold Summary + 9. Recovery Summary + 10. Removal Summary + 11. Minimum Pulse Width Summary + 12. Setup: 'C25M' + 13. Hold: 'C25M' + 14. Recovery: 'C25M' + 15. Removal: 'C25M' + 16. Minimum Pulse Width: 'C25M' + 17. Minimum Pulse Width: 'PHI0' + 18. Setup Times + 19. Hold Times + 20. Clock to Output Times + 21. Minimum Clock to Output Times + 22. Propagation Delay + 23. Minimum Propagation Delay + 24. Output Enable Times + 25. Minimum Output Enable Times + 26. Output Disable Times + 27. Minimum Output Disable Times + 28. Setup Transfers + 29. Hold Transfers + 30. Recovery Transfers + 31. Removal Transfers + 32. Report TCCS + 33. Report RSKM + 34. Unconstrained Paths + 35. TimeQuest Timing Analyzer Messages @@ -94,23 +93,32 @@ applicable agreement for further details. +----------------------------+-------------+ -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Clocks ; -+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------+ -; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; -+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------+ -; C25M ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { C25M } ; -; PHI0 ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { PHI0 } ; -+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------+ ++---------------------------------------------------+ +; SDC File List ; ++---------------+--------+--------------------------+ +; SDC File Path ; Status ; Read at ; ++---------------+--------+--------------------------+ +; GR8RAM.sdc ; OK ; Wed Apr 21 20:02:06 2021 ; ++---------------+--------+--------------------------+ -+--------------------------------------------------+ -; Fmax Summary ; -+------------+-----------------+------------+------+ -; Fmax ; Restricted Fmax ; Clock Name ; Note ; -+------------+-----------------+------------+------+ -; 103.27 MHz ; 103.27 MHz ; C25M ; ; -+------------+-----------------+------------+------+ ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clocks ; ++------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------+ +; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; ++------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------+ +; C25M ; Base ; 40.000 ; 25.0 MHz ; 0.000 ; 20.000 ; ; ; ; ; ; ; ; ; ; ; { C25M } ; +; PHI0 ; Base ; 978.000 ; 1.02 MHz ; 0.000 ; 489.000 ; ; ; ; ; ; ; ; ; ; ; { PHI0 } ; ++------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------+ + + ++-------------------------------------------------+ +; Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 65.95 MHz ; 65.95 MHz ; C25M ; ; ++-----------+-----------------+------------+------+ This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. @@ -119,19 +127,17 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +-------+--------+---------------+ -; C25M ; -9.005 ; -699.357 ; -; PHI0 ; -0.425 ; -0.425 ; +; C25M ; 12.419 ; 0.000 ; +-------+--------+---------------+ -+--------------------------------+ -; Hold Summary ; -+-------+--------+---------------+ -; Clock ; Slack ; End Point TNS ; -+-------+--------+---------------+ -; PHI0 ; -0.248 ; -0.248 ; -; C25M ; 1.400 ; 0.000 ; -+-------+--------+---------------+ ++-------------------------------+ +; Hold Summary ; ++-------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-------+-------+---------------+ +; C25M ; 1.393 ; 0.000 ; ++-------+-------+---------------+ +--------------------------------+ @@ -139,7 +145,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +-------+--------+---------------+ -; C25M ; -4.412 ; -127.948 ; +; C25M ; 33.300 ; 0.000 ; +-------+--------+---------------+ @@ -148,18 +154,18 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +-------+-------+---------------+ -; C25M ; 4.858 ; 0.000 ; +; C25M ; 6.146 ; 0.000 ; +-------+-------+---------------+ -+--------------------------------+ -; Minimum Pulse Width Summary ; -+-------+--------+---------------+ -; Clock ; Slack ; End Point TNS ; -+-------+--------+---------------+ -; C25M ; -2.289 ; -2.289 ; -; PHI0 ; -2.289 ; -2.289 ; -+-------+--------+---------------+ ++---------------------------------+ +; Minimum Pulse Width Summary ; ++-------+---------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-------+---------+---------------+ +; C25M ; 19.734 ; 0.000 ; +; PHI0 ; 488.734 ; 0.000 ; ++-------+---------+---------------+ +----------------------------------------------------------------------------------------------------------------+ @@ -167,240 +173,214 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +--------+----------------+----------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+----------------+----------------+--------------+-------------+--------------+------------+------------+ -; -9.005 ; RAMSpecSELr ; SA[8]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.894 ; -; -8.961 ; RAMSpecSELr ; SA[6]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.850 ; -; -8.953 ; RAMSpecSELr ; SA[7]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.842 ; -; -8.919 ; nWEr ; RCKE~reg0 ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.808 ; -; -8.916 ; ROMSpecRDr ; RCKE~reg0 ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.805 ; -; -8.897 ; RAMSpecSELr ; SA[2]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.786 ; -; -8.683 ; IS.state_bit_1 ; SA[8]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.350 ; -; -8.631 ; IS.state_bit_1 ; SA[7]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.298 ; -; -8.625 ; IS.state_bit_1 ; SA[6]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.292 ; -; -8.571 ; RAMSpecSELr ; RCKE~reg0 ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.460 ; -; -8.495 ; RAMSpecSELr ; SA[1]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.384 ; -; -8.451 ; LS[10] ; IS.state_bit_0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.118 ; -; -8.428 ; RAMSpecSELr ; SA[5]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.317 ; -; -8.422 ; nWEr ; Addr[0] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.311 ; -; -8.422 ; nWEr ; Addr[1] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.311 ; -; -8.422 ; nWEr ; Addr[2] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.311 ; -; -8.422 ; nWEr ; Addr[3] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.311 ; -; -8.422 ; nWEr ; Addr[4] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.311 ; -; -8.422 ; nWEr ; Addr[5] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.311 ; -; -8.422 ; nWEr ; Addr[6] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.311 ; -; -8.422 ; nWEr ; Addr[7] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.311 ; -; -8.419 ; nWEr ; Addr[10] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.308 ; -; -8.419 ; nWEr ; Addr[11] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.308 ; -; -8.419 ; nWEr ; Addr[12] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.308 ; -; -8.419 ; nWEr ; Addr[13] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.308 ; -; -8.419 ; nWEr ; Addr[14] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.308 ; -; -8.419 ; nWEr ; Addr[15] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.308 ; -; -8.419 ; nWEr ; Addr[8] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.308 ; -; -8.419 ; nWEr ; Addr[9] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.308 ; -; -8.387 ; nWEr ; AddrIncH ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.276 ; -; -8.301 ; LS[11] ; IS.state_bit_0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.968 ; -; -8.289 ; IS.state_bit_0 ; SA[8]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.956 ; -; -8.284 ; nWEr ; nRCS~reg0 ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.173 ; -; -8.265 ; RAMSpecSELr ; SA[0]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.154 ; -; -8.261 ; nWEr ; Addr[23] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.150 ; -; -8.261 ; nWEr ; Addr[16] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.150 ; -; -8.261 ; nWEr ; Addr[17] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.150 ; -; -8.261 ; nWEr ; Addr[18] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.150 ; -; -8.261 ; nWEr ; Addr[19] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.150 ; -; -8.261 ; nWEr ; Addr[20] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.150 ; -; -8.261 ; nWEr ; Addr[21] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.150 ; -; -8.261 ; nWEr ; Addr[22] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.150 ; -; -8.245 ; ROMSpecRDr ; nRCS~reg0 ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.134 ; -; -8.237 ; IS.state_bit_0 ; SA[7]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.904 ; -; -8.231 ; IS.state_bit_0 ; SA[6]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.898 ; -; -8.226 ; RAMSpecSELr ; SA[9]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.115 ; -; -8.222 ; RAMSpecSELr ; SA[11]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.111 ; -; -8.222 ; RAMSpecSELr ; SA[12]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.111 ; -; -8.177 ; IS.state_bit_1 ; SA[2]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.844 ; -; -8.116 ; LS[9] ; IS.state_bit_0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.783 ; -; -8.115 ; PS[0] ; SA[2]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.782 ; -; -8.106 ; RAMSpecSELr ; SA[4]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.778 ; 5.995 ; -; -8.104 ; RAMSpecSELr ; SA[3]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.778 ; 5.993 ; -; -7.954 ; PS[0] ; SA[0]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.621 ; -; -7.928 ; IS.state_bit_1 ; SA[5]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.595 ; -; -7.900 ; RAMSpecSELr ; nRCS~reg0 ; PHI0 ; C25M ; 1.000 ; -2.778 ; 5.789 ; -; -7.896 ; PS[1] ; IS.state_bit_1 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.563 ; -; -7.878 ; PS[1] ; IOROMEN ; C25M ; C25M ; 1.000 ; 0.000 ; 8.545 ; -; -7.844 ; LS[1] ; nRCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.511 ; -; -7.817 ; IS.state_bit_1 ; RCKE~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.484 ; -; -7.817 ; PS[1] ; RCKE~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.484 ; -; -7.804 ; REGEN ; Addr[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.471 ; -; -7.804 ; REGEN ; Addr[1] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.471 ; -; -7.804 ; REGEN ; Addr[2] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.471 ; -; -7.804 ; REGEN ; Addr[3] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.471 ; -; -7.804 ; REGEN ; Addr[4] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.471 ; -; -7.804 ; REGEN ; Addr[5] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.471 ; -; -7.804 ; REGEN ; Addr[6] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.471 ; -; -7.804 ; REGEN ; Addr[7] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.471 ; -; -7.801 ; REGEN ; Addr[10] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.468 ; -; -7.801 ; REGEN ; Addr[11] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.468 ; -; -7.801 ; REGEN ; Addr[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.468 ; -; -7.801 ; REGEN ; Addr[13] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.468 ; -; -7.801 ; REGEN ; Addr[14] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.468 ; -; -7.801 ; REGEN ; Addr[15] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.468 ; -; -7.801 ; REGEN ; Addr[8] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.468 ; -; -7.801 ; REGEN ; Addr[9] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.468 ; -; -7.785 ; LS[10] ; IS.state_bit_2 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.452 ; -; -7.783 ; IS.state_bit_0 ; SA[2]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.450 ; -; -7.775 ; IS.state_bit_1 ; SA[1]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.442 ; -; -7.769 ; REGEN ; AddrIncH ; C25M ; C25M ; 1.000 ; 0.000 ; 8.436 ; -; -7.762 ; IS.state_bit_1 ; SA[4]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.429 ; -; -7.760 ; IS.state_bit_1 ; SA[3]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.427 ; -; -7.741 ; LS[8] ; IS.state_bit_0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.408 ; -; -7.706 ; PS[3] ; SA[8]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.373 ; -; -7.704 ; LS[7] ; IS.state_bit_0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.371 ; -; -7.680 ; IS.state_bit_1 ; SA[0]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.347 ; -; -7.668 ; PS[0] ; SA[1]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.335 ; -; -7.662 ; PS[3] ; SA[6]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.329 ; -; -7.654 ; PS[3] ; SA[7]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.321 ; -; -7.645 ; PS[1] ; REGEN ; C25M ; C25M ; 1.000 ; 0.000 ; 8.312 ; -; -7.643 ; REGEN ; Addr[23] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.310 ; -; -7.643 ; REGEN ; Addr[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.310 ; -; -7.643 ; REGEN ; Addr[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.310 ; -; -7.643 ; REGEN ; Addr[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.310 ; -; -7.643 ; REGEN ; Addr[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.310 ; -; -7.643 ; REGEN ; Addr[20] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.310 ; -; -7.643 ; REGEN ; Addr[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.310 ; -; -7.643 ; REGEN ; Addr[22] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.310 ; -; -7.642 ; LS[1] ; IS.state_bit_0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.309 ; +; 12.419 ; REGEN ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.248 ; +; 12.825 ; REGEN ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.842 ; +; 12.826 ; REGEN ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.841 ; +; 12.830 ; REGEN ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.837 ; +; 12.861 ; REGEN ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.806 ; +; 12.948 ; Addr[7] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.719 ; +; 13.317 ; REGEN ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.350 ; +; 13.332 ; PS[2] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.335 ; +; 13.332 ; PS[2] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.335 ; +; 13.485 ; REGEN ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.182 ; +; 13.494 ; REGEN ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.173 ; +; 13.610 ; PS[1] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.057 ; +; 13.610 ; PS[1] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.057 ; +; 13.611 ; PS[3] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.056 ; +; 13.611 ; PS[3] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.056 ; +; 13.692 ; Addr[14] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.975 ; +; 13.794 ; Addr[15] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.873 ; +; 13.950 ; Addr[10] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.717 ; +; 13.955 ; PS[2] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.712 ; +; 13.958 ; Addr[12] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.709 ; +; 13.965 ; Addr[4] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.702 ; +; 14.046 ; PS[0] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.621 ; +; 14.046 ; PS[0] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.621 ; +; 14.233 ; PS[1] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.434 ; +; 14.234 ; PS[3] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.433 ; +; 14.257 ; Addr[13] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.410 ; +; 14.387 ; PS[2] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.280 ; +; 14.387 ; PS[2] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.280 ; +; 14.387 ; PS[2] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.280 ; +; 14.387 ; PS[2] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.280 ; +; 14.387 ; PS[2] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.280 ; +; 14.407 ; Addr[11] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.260 ; +; 14.442 ; Addr[6] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.225 ; +; 14.448 ; Addr[5] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.219 ; +; 14.638 ; Addr[19] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.029 ; +; 14.650 ; Addr[3] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.017 ; +; 14.665 ; PS[1] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.002 ; +; 14.665 ; PS[1] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.002 ; +; 14.665 ; PS[1] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.002 ; +; 14.665 ; PS[1] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.002 ; +; 14.665 ; PS[1] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.002 ; +; 14.666 ; PS[3] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.001 ; +; 14.666 ; PS[3] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.001 ; +; 14.666 ; PS[3] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.001 ; +; 14.666 ; PS[3] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.001 ; +; 14.666 ; PS[3] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.001 ; +; 14.669 ; PS[0] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.998 ; +; 14.690 ; Addr[22] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.977 ; +; 14.700 ; Addr[16] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.967 ; +; 14.800 ; SetFWr[1] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.867 ; +; 14.801 ; SetFWr[1] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.866 ; +; 14.805 ; SetFWr[1] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.862 ; +; 14.871 ; Addr[9] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.796 ; +; 14.878 ; Addr[8] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.789 ; +; 15.101 ; PS[0] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.566 ; +; 15.101 ; PS[0] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.566 ; +; 15.101 ; PS[0] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.566 ; +; 15.101 ; PS[0] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.566 ; +; 15.101 ; PS[0] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.566 ; +; 15.384 ; Addr[21] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.283 ; +; 15.456 ; Addr[2] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.211 ; +; 15.469 ; Addr[20] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.198 ; +; 15.505 ; Addr[23] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.162 ; +; 15.510 ; SetFWr[1] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.157 ; +; 15.817 ; Addr[18] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.850 ; +; 15.897 ; Addr[17] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.770 ; +; 16.230 ; Addr[1] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.437 ; +; 16.377 ; Addr[0] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.290 ; +; 25.936 ; REGEN ; SA[1]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 13.731 ; +; 26.182 ; REGEN ; SA[0]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 13.485 ; +; 26.524 ; REGEN ; SA[2]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 13.143 ; +; 26.906 ; Addr[23] ; SA[1]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 12.761 ; +; 27.133 ; REGEN ; RCKE~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 12.534 ; +; 27.152 ; Addr[23] ; SA[0]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 12.515 ; +; 27.487 ; REGEN ; SA[8]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 12.180 ; +; 27.494 ; Addr[23] ; SA[2]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 12.173 ; +; 27.513 ; IS.state_bit_1 ; SA[1]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 12.154 ; +; 27.759 ; IS.state_bit_1 ; SA[0]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.908 ; +; 27.761 ; REGEN ; SA[5]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.906 ; +; 27.882 ; IS.state_bit_0 ; SA[1]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.785 ; +; 27.915 ; REGEN ; SA[4]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.752 ; +; 28.015 ; IS.state_bit_1 ; RCKE~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.652 ; +; 28.101 ; IS.state_bit_1 ; SA[2]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.566 ; +; 28.103 ; Addr[23] ; RCKE~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.564 ; +; 28.107 ; PS[1] ; SA[1]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.560 ; +; 28.128 ; IS.state_bit_0 ; SA[0]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.539 ; +; 28.154 ; REGEN ; SA[6]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.513 ; +; 28.192 ; IS.state_bit_0 ; RCKE~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.475 ; +; 28.245 ; PS[1] ; SA[2]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.422 ; +; 28.350 ; REGEN ; nRCS~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.317 ; +; 28.456 ; PS[0] ; SA[1]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.211 ; +; 28.457 ; Addr[23] ; SA[8]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.210 ; +; 28.470 ; IS.state_bit_0 ; SA[2]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.197 ; +; 28.515 ; REGEN ; SA[3]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.152 ; +; 28.594 ; PS[0] ; SA[2]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.073 ; +; 28.638 ; SetFWr[0] ; SA[1]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.029 ; +; 28.731 ; Addr[23] ; SA[5]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.936 ; +; 28.806 ; LS[10] ; IS.state_bit_0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.861 ; +; 28.812 ; REGEN ; SA[7]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.855 ; +; 28.884 ; SetFWr[0] ; SA[0]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.783 ; +--------+----------------+----------------+--------------+-------------+--------------+------------+------------+ -+--------------------------------------------------------------------------------------------------------+ -; Setup: 'PHI0' ; -+--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ -; -0.425 ; Addr[23] ; RAMSpecSELr ; C25M ; PHI0 ; 1.000 ; 2.778 ; 3.870 ; -; -0.265 ; REGEN ; RAMSpecSELr ; C25M ; PHI0 ; 1.000 ; 2.778 ; 3.710 ; -; 0.296 ; IOROMEN ; ROMSpecRDr ; C25M ; PHI0 ; 1.000 ; 2.778 ; 3.149 ; -; 0.609 ; SetFWr[0] ; RAMSpecSELr ; C25M ; PHI0 ; 1.000 ; 2.778 ; 2.836 ; -; 0.694 ; SetFWr[1] ; RAMSpecSELr ; C25M ; PHI0 ; 1.000 ; 2.778 ; 2.751 ; -+--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ - - -+--------------------------------------------------------------------------------------------------------+ -; Hold: 'PHI0' ; -+--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ -; -0.248 ; SetFWr[1] ; RAMSpecSELr ; C25M ; PHI0 ; 0.000 ; 2.778 ; 2.751 ; -; -0.163 ; SetFWr[0] ; RAMSpecSELr ; C25M ; PHI0 ; 0.000 ; 2.778 ; 2.836 ; -; 0.150 ; IOROMEN ; ROMSpecRDr ; C25M ; PHI0 ; 0.000 ; 2.778 ; 3.149 ; -; 0.711 ; REGEN ; RAMSpecSELr ; C25M ; PHI0 ; 0.000 ; 2.778 ; 3.710 ; -; 0.871 ; Addr[23] ; RAMSpecSELr ; C25M ; PHI0 ; 0.000 ; 2.778 ; 3.870 ; -+--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ - - +---------------------------------------------------------------------------------------------------------------+ ; Hold: 'C25M' ; +-------+----------------+----------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +-------+----------------+----------------+--------------+-------------+--------------+------------+------------+ -; 1.400 ; WRD[7] ; WRD[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.621 ; -; 1.411 ; WRD[4] ; WRD[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.632 ; -; 1.412 ; WRD[6] ; WRD[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.633 ; -; 1.414 ; nRESf[2] ; nRESf[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.635 ; -; 1.420 ; WRD[0] ; WRD[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.641 ; -; 1.420 ; WRD[3] ; WRD[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.641 ; -; 1.640 ; nRESout~reg0 ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 1.861 ; -; 1.782 ; WRD[2] ; WRD[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.003 ; -; 1.822 ; nRESf[1] ; nRESf[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.043 ; -; 1.930 ; Addr[7] ; AddrIncM ; C25M ; C25M ; 0.000 ; 0.000 ; 2.151 ; -; 1.933 ; nRESf[2] ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 2.154 ; +; 1.393 ; WRD[0] ; WRD[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.614 ; +; 1.400 ; PHI0r1 ; PHI0r2 ; C25M ; C25M ; 0.000 ; 0.000 ; 1.621 ; +; 1.411 ; WRD[7] ; WRD[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.632 ; +; 1.413 ; nRESf[1] ; nRESf[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.634 ; +; 1.418 ; WRD[4] ; WRD[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.639 ; +; 1.418 ; WRD[5] ; WRD[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.639 ; +; 1.420 ; WRD[1] ; WRD[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.641 ; +; 1.421 ; WRD[2] ; WRD[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.642 ; +; 1.645 ; WRD[3] ; WRD[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.866 ; +; 1.649 ; nRESout~reg0 ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 1.870 ; +; 1.661 ; REGEN ; REGEN ; C25M ; C25M ; 0.000 ; 0.000 ; 1.882 ; +; 1.695 ; PS[2] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.916 ; +; 1.734 ; PS[0] ; PS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.955 ; +; 1.778 ; WRD[3] ; WRD[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.999 ; +; 1.840 ; nRESf[2] ; nRESf[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.061 ; +; 1.930 ; Addr[15] ; AddrIncH ; C25M ; C25M ; 0.000 ; 0.000 ; 2.151 ; +; 1.939 ; Addr[7] ; AddrIncM ; C25M ; C25M ; 0.000 ; 0.000 ; 2.160 ; +; 1.944 ; nRESf[1] ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 2.165 ; +; 1.958 ; PS[3] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.179 ; +; 1.994 ; PS[1] ; PS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.215 ; +; 2.003 ; PS[1] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.224 ; ; 2.063 ; LS[13] ; LS[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.284 ; -; 2.075 ; nRESf[3] ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 2.296 ; -; 2.107 ; LS[7] ; LS[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.328 ; ; 2.117 ; Addr[10] ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; ; 2.117 ; Addr[1] ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; ; 2.117 ; Addr[2] ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; -; 2.117 ; Bank ; Bank ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; -; 2.117 ; Addr[15] ; Addr[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; -; 2.117 ; LS[8] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; -; 2.117 ; LS[9] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; ; 2.117 ; Addr[9] ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; -; 2.120 ; WRD[1] ; WRD[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.341 ; -; 2.123 ; WRD[2] ; WRD[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.344 ; -; 2.124 ; Addr[16] ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.345 ; -; 2.125 ; Addr[0] ; Addr[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.346 ; -; 2.126 ; LS[4] ; LS[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ; -; 2.126 ; LS[6] ; LS[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ; +; 2.125 ; Addr[16] ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.346 ; +; 2.125 ; Addr[8] ; Addr[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.346 ; +; 2.126 ; Addr[23] ; Addr[23] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ; ; 2.126 ; Addr[17] ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ; -; 2.127 ; Addr[23] ; Addr[23] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.348 ; +; 2.127 ; LS[6] ; LS[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.348 ; ; 2.127 ; Addr[18] ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.348 ; -; 2.137 ; Addr[7] ; Addr[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.358 ; -; 2.151 ; WRD[4] ; WRD[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.372 ; -; 2.155 ; nRESf[1] ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 2.376 ; -; 2.162 ; PS[2] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.383 ; -; 2.164 ; PS[3] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.385 ; -; 2.175 ; PS[3] ; nRAS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.396 ; -; 2.215 ; nRESf[0] ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 2.436 ; +; 2.133 ; Addr[0] ; Addr[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.354 ; +; 2.133 ; LS[7] ; LS[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.354 ; +; 2.135 ; LS[0] ; LS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.356 ; +; 2.137 ; Addr[15] ; Addr[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.358 ; +; 2.138 ; LS[0] ; LS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.359 ; +; 2.145 ; IOROMEN ; IOROMEN ; C25M ; C25M ; 0.000 ; 0.000 ; 2.366 ; +; 2.145 ; Addr[7] ; Addr[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.366 ; +; 2.151 ; LS[8] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.372 ; +; 2.153 ; LS[9] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.374 ; +; 2.160 ; LS[4] ; LS[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.381 ; +; 2.160 ; WRD[5] ; WRD[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.381 ; +; 2.161 ; WRD[4] ; WRD[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.382 ; +; 2.166 ; PS[2] ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.387 ; +; 2.169 ; PS[2] ; MOSIout ; C25M ; C25M ; 0.000 ; 0.000 ; 2.390 ; ; 2.222 ; Addr[19] ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.443 ; -; 2.226 ; PHI0 ; PHI0r1 ; PHI0 ; C25M ; 0.000 ; 3.458 ; 5.905 ; -; 2.228 ; AddrIncH ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.449 ; ; 2.230 ; Addr[5] ; Addr[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.451 ; ; 2.230 ; Addr[21] ; Addr[21] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.451 ; +; 2.230 ; PS[0] ; FCKout ; C25M ; C25M ; 0.000 ; 0.000 ; 2.451 ; ; 2.231 ; Addr[3] ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; ; 2.231 ; Addr[4] ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; ; 2.231 ; Addr[6] ; Addr[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; ; 2.231 ; Addr[20] ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; ; 2.231 ; Addr[22] ; Addr[22] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; -; 2.232 ; LS[10] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.453 ; +; 2.232 ; Addr[11] ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.453 ; +; 2.240 ; LS[1] ; LS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.461 ; ; 2.240 ; LS[3] ; LS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.461 ; -; 2.241 ; Addr[11] ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.462 ; +; 2.242 ; LS[10] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.463 ; ; 2.248 ; LS[12] ; LS[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.469 ; ; 2.249 ; Addr[12] ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.470 ; -; 2.249 ; LS[5] ; LS[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.470 ; ; 2.250 ; LS[11] ; LS[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.471 ; -; 2.251 ; LS[2] ; LS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.472 ; -; 2.251 ; LS[0] ; LS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.472 ; -; 2.252 ; LS[0] ; LS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.473 ; +; 2.251 ; LS[5] ; LS[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.472 ; +; 2.252 ; LS[2] ; LS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.473 ; ; 2.260 ; Addr[13] ; Addr[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.481 ; +; 2.261 ; WRD[2] ; WRD[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.482 ; ; 2.262 ; Addr[14] ; Addr[14] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.483 ; -; 2.263 ; WRD[3] ; WRD[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.484 ; -; 2.267 ; WRD[0] ; WRD[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.488 ; -; 2.285 ; WRD[5] ; WRD[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.506 ; -; 2.297 ; IS.state_bit_0 ; IS.state_bit_0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.518 ; -; 2.421 ; nRESf[0] ; nRESf[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.642 ; -; 2.423 ; WRD[1] ; WRD[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.644 ; -; 2.532 ; PS[0] ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.753 ; -; 2.534 ; PS[0] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.755 ; -; 2.537 ; PS[0] ; nRAS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.758 ; -; 2.538 ; PHI0r1 ; PHI0r2 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.759 ; -; 2.545 ; PS[0] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.766 ; -; 2.559 ; Addr[2] ; RDD[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.780 ; -; 2.606 ; AddrIncL ; Addr[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.827 ; -; 2.680 ; Addr[1] ; RDD[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.901 ; -; 2.699 ; PS[2] ; nRAS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.920 ; -; 2.702 ; PS[2] ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.923 ; -; 2.703 ; PS[2] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.924 ; -; 2.726 ; PHI0 ; PHI0r1 ; PHI0 ; C25M ; -0.500 ; 3.458 ; 5.905 ; -; 2.826 ; PHI0r1 ; RCKE~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.047 ; -; 2.860 ; Addr[3] ; RDD[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.081 ; -; 2.905 ; IS.state_bit_0 ; FCS ; C25M ; C25M ; 0.000 ; 0.000 ; 3.126 ; -; 2.939 ; LS[7] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.160 ; +; 2.264 ; WRD[1] ; WRD[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.485 ; +; 2.310 ; PS[0] ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.531 ; +; 2.312 ; PS[0] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.533 ; +; 2.317 ; Bank ; Bank ; C25M ; C25M ; 0.000 ; 0.000 ; 2.538 ; +; 2.319 ; IS.state_bit_0 ; IS.state_bit_0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.540 ; +; 2.333 ; IS.state_bit_0 ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.554 ; +; 2.345 ; PS[0] ; MOSIout ; C25M ; C25M ; 0.000 ; 0.000 ; 2.566 ; +; 2.448 ; WRD[6] ; WRD[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.669 ; +; 2.521 ; nRESf[3] ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 2.742 ; +; 2.531 ; IS.state_bit_1 ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.752 ; +; 2.660 ; PS[1] ; nCAS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.881 ; +; 2.673 ; nRESf[2] ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 2.894 ; +; 2.708 ; PS[2] ; nCAS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.929 ; +; 2.709 ; PS[0] ; nSWE~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.930 ; +; 2.753 ; IS.state_bit_1 ; IS.state_bit_0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.974 ; +; 2.782 ; PS[0] ; nCAS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.003 ; +; 2.829 ; PS[0] ; nRAS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.050 ; ; 2.949 ; Addr[9] ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; -; 2.949 ; LS[9] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; ; 2.949 ; Addr[10] ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; ; 2.949 ; Addr[1] ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; ; 2.949 ; Addr[2] ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; -; 2.949 ; LS[8] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; -; 2.956 ; Addr[16] ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.177 ; -; 2.957 ; Addr[0] ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.178 ; -; 2.958 ; LS[4] ; LS[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.179 ; +; 2.957 ; Addr[16] ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.178 ; +; 2.957 ; Addr[8] ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.178 ; ; 2.958 ; Addr[17] ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.179 ; ; 2.959 ; Addr[18] ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.180 ; -; 3.011 ; IS.state_bit_0 ; FCKOE ; C25M ; C25M ; 0.000 ; 0.000 ; 3.232 ; -; 3.014 ; IS.state_bit_0 ; MOSIOE ; C25M ; C25M ; 0.000 ; 0.000 ; 3.235 ; -; 3.050 ; LS[7] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.271 ; -; 3.060 ; LS[9] ; LS[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ; +; 2.965 ; Addr[0] ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.186 ; +; 2.965 ; LS[7] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.186 ; +; 2.983 ; LS[8] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.204 ; +; 2.985 ; LS[9] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.206 ; +; 2.992 ; LS[4] ; LS[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.213 ; +; 3.034 ; Addr[0] ; DQMH~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.255 ; ; 3.060 ; Addr[10] ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ; ; 3.060 ; Addr[2] ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ; -; 3.060 ; LS[8] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ; +-------+----------------+----------------+--------------+-------------+--------------+------------+------------+ @@ -409,35 +389,35 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +--------+-----------+----------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+-----------+----------+--------------+-------------+--------------+------------+------------+ -; -4.412 ; nRESr ; Addr[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; -; -4.412 ; nRESr ; Addr[23] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; -; -4.412 ; nRESr ; Addr[10] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; -; -4.412 ; nRESr ; Addr[1] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; -; -4.412 ; nRESr ; Addr[11] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; -; -4.412 ; nRESr ; Addr[2] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; -; -4.412 ; nRESr ; Addr[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; -; -4.412 ; nRESr ; Bank ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; -; -4.412 ; nRESr ; Addr[3] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; -; -4.412 ; nRESr ; Addr[13] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; -; -4.412 ; nRESr ; Addr[4] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; -; -4.412 ; nRESr ; Addr[14] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; -; -4.412 ; nRESr ; Addr[5] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; -; -4.412 ; nRESr ; Addr[15] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; -; -4.412 ; nRESr ; Addr[6] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; -; -4.412 ; nRESr ; Addr[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; -; -4.412 ; nRESr ; Addr[7] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; -; -4.412 ; nRESr ; Addr[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; -; -4.412 ; nRESr ; Addr[8] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; -; -4.412 ; nRESr ; Addr[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; -; -4.412 ; nRESr ; Addr[9] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; -; -4.412 ; nRESr ; Addr[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; -; -4.412 ; nRESr ; Addr[20] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; -; -4.412 ; nRESr ; Addr[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; -; -4.412 ; nRESr ; Addr[22] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; -; -4.412 ; nRESr ; REGEN ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; -; -4.412 ; nRESr ; AddrIncH ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; -; -4.412 ; nRESr ; AddrIncM ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; -; -4.412 ; nRESr ; AddrIncL ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; +; 33.300 ; nRESr ; Addr[0] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.367 ; +; 33.300 ; nRESr ; REGEN ; C25M ; C25M ; 40.000 ; 0.000 ; 6.367 ; +; 33.300 ; nRESr ; Addr[23] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.367 ; +; 33.300 ; nRESr ; Addr[10] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.367 ; +; 33.300 ; nRESr ; Addr[1] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.367 ; +; 33.300 ; nRESr ; Addr[11] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.367 ; +; 33.300 ; nRESr ; Addr[2] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.367 ; +; 33.300 ; nRESr ; Addr[12] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.367 ; +; 33.300 ; nRESr ; Bank ; C25M ; C25M ; 40.000 ; 0.000 ; 6.367 ; +; 33.300 ; nRESr ; Addr[3] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.367 ; +; 33.300 ; nRESr ; Addr[13] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.367 ; +; 33.300 ; nRESr ; Addr[4] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.367 ; +; 33.300 ; nRESr ; Addr[14] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.367 ; +; 33.300 ; nRESr ; Addr[5] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.367 ; +; 33.300 ; nRESr ; Addr[15] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.367 ; +; 33.300 ; nRESr ; Addr[6] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.367 ; +; 33.300 ; nRESr ; Addr[16] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.367 ; +; 33.300 ; nRESr ; Addr[7] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.367 ; +; 33.300 ; nRESr ; Addr[17] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.367 ; +; 33.300 ; nRESr ; Addr[8] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.367 ; +; 33.300 ; nRESr ; Addr[18] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.367 ; +; 33.300 ; nRESr ; Addr[9] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.367 ; +; 33.300 ; nRESr ; Addr[19] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.367 ; +; 33.300 ; nRESr ; Addr[20] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.367 ; +; 33.300 ; nRESr ; Addr[21] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.367 ; +; 33.300 ; nRESr ; Addr[22] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.367 ; +; 33.300 ; nRESr ; AddrIncH ; C25M ; C25M ; 40.000 ; 0.000 ; 6.367 ; +; 33.300 ; nRESr ; AddrIncM ; C25M ; C25M ; 40.000 ; 0.000 ; 6.367 ; +; 33.300 ; nRESr ; AddrIncL ; C25M ; C25M ; 40.000 ; 0.000 ; 6.367 ; +--------+-----------+----------+--------------+-------------+--------------+------------+------------+ @@ -446,35 +426,35 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+-----------+----------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +-------+-----------+----------+--------------+-------------+--------------+------------+------------+ -; 4.858 ; nRESr ; Addr[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; -; 4.858 ; nRESr ; Addr[23] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; -; 4.858 ; nRESr ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; -; 4.858 ; nRESr ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; -; 4.858 ; nRESr ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; -; 4.858 ; nRESr ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; -; 4.858 ; nRESr ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; -; 4.858 ; nRESr ; Bank ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; -; 4.858 ; nRESr ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; -; 4.858 ; nRESr ; Addr[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; -; 4.858 ; nRESr ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; -; 4.858 ; nRESr ; Addr[14] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; -; 4.858 ; nRESr ; Addr[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; -; 4.858 ; nRESr ; Addr[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; -; 4.858 ; nRESr ; Addr[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; -; 4.858 ; nRESr ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; -; 4.858 ; nRESr ; Addr[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; -; 4.858 ; nRESr ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; -; 4.858 ; nRESr ; Addr[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; -; 4.858 ; nRESr ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; -; 4.858 ; nRESr ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; -; 4.858 ; nRESr ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; -; 4.858 ; nRESr ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; -; 4.858 ; nRESr ; Addr[21] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; -; 4.858 ; nRESr ; Addr[22] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; -; 4.858 ; nRESr ; REGEN ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; -; 4.858 ; nRESr ; AddrIncH ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; -; 4.858 ; nRESr ; AddrIncM ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; -; 4.858 ; nRESr ; AddrIncL ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; +; 6.146 ; nRESr ; Addr[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.367 ; +; 6.146 ; nRESr ; REGEN ; C25M ; C25M ; 0.000 ; 0.000 ; 6.367 ; +; 6.146 ; nRESr ; Addr[23] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.367 ; +; 6.146 ; nRESr ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.367 ; +; 6.146 ; nRESr ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.367 ; +; 6.146 ; nRESr ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.367 ; +; 6.146 ; nRESr ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.367 ; +; 6.146 ; nRESr ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.367 ; +; 6.146 ; nRESr ; Bank ; C25M ; C25M ; 0.000 ; 0.000 ; 6.367 ; +; 6.146 ; nRESr ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.367 ; +; 6.146 ; nRESr ; Addr[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.367 ; +; 6.146 ; nRESr ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.367 ; +; 6.146 ; nRESr ; Addr[14] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.367 ; +; 6.146 ; nRESr ; Addr[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.367 ; +; 6.146 ; nRESr ; Addr[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.367 ; +; 6.146 ; nRESr ; Addr[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.367 ; +; 6.146 ; nRESr ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.367 ; +; 6.146 ; nRESr ; Addr[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.367 ; +; 6.146 ; nRESr ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.367 ; +; 6.146 ; nRESr ; Addr[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.367 ; +; 6.146 ; nRESr ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.367 ; +; 6.146 ; nRESr ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.367 ; +; 6.146 ; nRESr ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.367 ; +; 6.146 ; nRESr ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.367 ; +; 6.146 ; nRESr ; Addr[21] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.367 ; +; 6.146 ; nRESr ; Addr[22] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.367 ; +; 6.146 ; nRESr ; AddrIncH ; C25M ; C25M ; 0.000 ; 0.000 ; 6.367 ; +; 6.146 ; nRESr ; AddrIncM ; C25M ; C25M ; 0.000 ; 0.000 ; 6.367 ; +; 6.146 ; nRESr ; AddrIncL ; C25M ; C25M ; 0.000 ; 0.000 ; 6.367 ; +-------+-----------+----------+--------------+-------------+--------------+------------+------------+ @@ -483,130 +463,174 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +--------+--------------+----------------+------------------+-------+------------+----------------+ ; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; +--------+--------------+----------------+------------------+-------+------------+----------------+ -; -2.289 ; 1.000 ; 3.289 ; Port Rate ; C25M ; Rise ; C25M ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; AddrIncH ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; AddrIncH ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; AddrIncL ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; AddrIncL ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; AddrIncM ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; AddrIncM ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[0] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[0] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[10] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[10] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[11] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[11] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[12] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[12] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[13] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[13] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[14] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[14] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[15] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[15] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[16] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[16] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[17] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[17] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[18] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[18] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[19] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[19] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[1] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[1] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[20] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[20] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[21] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[21] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[22] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[22] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[23] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[23] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[2] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[2] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[3] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[3] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[4] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[4] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[5] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[5] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[6] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[6] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[7] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[7] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[8] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[8] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[9] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[9] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Bank ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Bank ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; DQMH~reg0 ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; DQMH~reg0 ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; DQML~reg0 ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; DQML~reg0 ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; FCKOE ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; FCKOE ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; FCKout ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; FCKout ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; FCS ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; FCS ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; IOROMEN ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; IOROMEN ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; IS.state_bit_0 ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; IS.state_bit_0 ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; IS.state_bit_1 ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; IS.state_bit_1 ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; IS.state_bit_2 ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; IS.state_bit_2 ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[0] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[0] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[10] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[10] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[11] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[11] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[12] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[12] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[13] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[13] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[1] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[1] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[2] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[2] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[3] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[3] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[4] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[4] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[5] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[5] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[6] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[6] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[7] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[7] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[8] ; +; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; AddrIncH ; +; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; AddrIncH ; +; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; AddrIncL ; +; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; AddrIncL ; +; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; AddrIncM ; +; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; AddrIncM ; +; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[0] ; +; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[0] ; +; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[10] ; +; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[10] ; +; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[11] ; +; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[11] ; +; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[12] ; +; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[12] ; +; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[13] ; +; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[13] ; +; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[14] ; +; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[14] ; +; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[15] ; +; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[15] ; +; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[16] ; +; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[16] ; +; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[17] ; +; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[17] ; +; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[18] ; +; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[18] ; +; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[19] ; +; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[19] ; +; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[1] ; +; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[1] ; +; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[20] ; +; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[20] ; +; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[21] ; +; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[21] ; +; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[22] ; +; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[22] ; +; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[23] ; +; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[23] ; +; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[2] ; +; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[2] ; +; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[3] ; +; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[3] ; +; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[4] ; +; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[4] ; +; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[5] ; +; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[5] ; +; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[6] ; +; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[6] ; +; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[7] ; +; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[7] ; +; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[8] ; +; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[8] ; +; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[9] ; +; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[9] ; +; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Bank ; +; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Bank ; +; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; DQMH~reg0 ; +; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; DQMH~reg0 ; +; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; DQML~reg0 ; +; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; DQML~reg0 ; +; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; FCKOE ; +; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; FCKOE ; +; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; FCKout ; +; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; FCKout ; +; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; FCS ; +; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; FCS ; +; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; IOROMEN ; +; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; IOROMEN ; +; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; IS.state_bit_0 ; +; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; IS.state_bit_0 ; +; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; IS.state_bit_1 ; +; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; IS.state_bit_1 ; +; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; IS.state_bit_2 ; +; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; IS.state_bit_2 ; +; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[0] ; +; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[0] ; +; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[10] ; +; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[10] ; +; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[11] ; +; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[11] ; +; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[12] ; +; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[12] ; +; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[13] ; +; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[13] ; +; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[1] ; +; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[1] ; +; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[2] ; +; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[2] ; +; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[3] ; +; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[3] ; +; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[4] ; +; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[4] ; +; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[5] ; +; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[5] ; +; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[6] ; +; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[6] ; +; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[7] ; +; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[7] ; +; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[8] ; +; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[8] ; +--------+--------------+----------------+------------------+-------+------------+----------------+ -+--------------------------------------------------------------------------------------------------+ -; Minimum Pulse Width: 'PHI0' ; -+--------+--------------+----------------+------------------+-------+------------+-----------------+ -; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; -+--------+--------------+----------------+------------------+-------+------------+-----------------+ -; -2.289 ; 1.000 ; 3.289 ; Port Rate ; PHI0 ; Rise ; PHI0 ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI0 ; Rise ; RAMSpecSELr ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI0 ; Rise ; RAMSpecSELr ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI0 ; Rise ; ROMSpecRDr ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI0 ; Rise ; ROMSpecRDr ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI0 ; Rise ; nWEr ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI0 ; Rise ; nWEr ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI0 ; Rise ; PHI0|combout ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI0 ; Rise ; PHI0|combout ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI0 ; Rise ; RAMSpecSELr|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI0 ; Rise ; RAMSpecSELr|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI0 ; Rise ; ROMSpecRDr|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI0 ; Rise ; ROMSpecRDr|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI0 ; Rise ; nWEr|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI0 ; Rise ; nWEr|clk ; -+--------+--------------+----------------+------------------+-------+------------+-----------------+ ++------------------------------------------------------------------------------------------------+ +; Minimum Pulse Width: 'PHI0' ; ++---------+--------------+----------------+------------------+-------+------------+--------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++---------+--------------+----------------+------------------+-------+------------+--------------+ +; 488.734 ; 489.000 ; 0.266 ; High Pulse Width ; PHI0 ; Rise ; CXXXr ; +; 488.734 ; 489.000 ; 0.266 ; Low Pulse Width ; PHI0 ; Rise ; CXXXr ; +; 488.734 ; 489.000 ; 0.266 ; High Pulse Width ; PHI0 ; Rise ; RAr[0] ; +; 488.734 ; 489.000 ; 0.266 ; Low Pulse Width ; PHI0 ; Rise ; RAr[0] ; +; 488.734 ; 489.000 ; 0.266 ; High Pulse Width ; PHI0 ; Rise ; RAr[10] ; +; 488.734 ; 489.000 ; 0.266 ; Low Pulse Width ; PHI0 ; Rise ; RAr[10] ; +; 488.734 ; 489.000 ; 0.266 ; High Pulse Width ; PHI0 ; Rise ; RAr[11] ; +; 488.734 ; 489.000 ; 0.266 ; Low Pulse Width ; PHI0 ; Rise ; RAr[11] ; +; 488.734 ; 489.000 ; 0.266 ; High Pulse Width ; PHI0 ; Rise ; RAr[1] ; +; 488.734 ; 489.000 ; 0.266 ; Low Pulse Width ; PHI0 ; Rise ; RAr[1] ; +; 488.734 ; 489.000 ; 0.266 ; High Pulse Width ; PHI0 ; Rise ; RAr[2] ; +; 488.734 ; 489.000 ; 0.266 ; Low Pulse Width ; PHI0 ; Rise ; RAr[2] ; +; 488.734 ; 489.000 ; 0.266 ; High Pulse Width ; PHI0 ; Rise ; RAr[3] ; +; 488.734 ; 489.000 ; 0.266 ; Low Pulse Width ; PHI0 ; Rise ; RAr[3] ; +; 488.734 ; 489.000 ; 0.266 ; High Pulse Width ; PHI0 ; Rise ; RAr[4] ; +; 488.734 ; 489.000 ; 0.266 ; Low Pulse Width ; PHI0 ; Rise ; RAr[4] ; +; 488.734 ; 489.000 ; 0.266 ; High Pulse Width ; PHI0 ; Rise ; RAr[5] ; +; 488.734 ; 489.000 ; 0.266 ; Low Pulse Width ; PHI0 ; Rise ; RAr[5] ; +; 488.734 ; 489.000 ; 0.266 ; High Pulse Width ; PHI0 ; Rise ; RAr[6] ; +; 488.734 ; 489.000 ; 0.266 ; Low Pulse Width ; PHI0 ; Rise ; RAr[6] ; +; 488.734 ; 489.000 ; 0.266 ; High Pulse Width ; PHI0 ; Rise ; RAr[7] ; +; 488.734 ; 489.000 ; 0.266 ; Low Pulse Width ; PHI0 ; Rise ; RAr[7] ; +; 488.734 ; 489.000 ; 0.266 ; High Pulse Width ; PHI0 ; Rise ; RAr[8] ; +; 488.734 ; 489.000 ; 0.266 ; Low Pulse Width ; PHI0 ; Rise ; RAr[8] ; +; 488.734 ; 489.000 ; 0.266 ; High Pulse Width ; PHI0 ; Rise ; RAr[9] ; +; 488.734 ; 489.000 ; 0.266 ; Low Pulse Width ; PHI0 ; Rise ; RAr[9] ; +; 488.734 ; 489.000 ; 0.266 ; High Pulse Width ; PHI0 ; Rise ; nWEr ; +; 488.734 ; 489.000 ; 0.266 ; Low Pulse Width ; PHI0 ; Rise ; nWEr ; +; 489.000 ; 489.000 ; 0.000 ; High Pulse Width ; PHI0 ; Rise ; CXXXr|clk ; +; 489.000 ; 489.000 ; 0.000 ; Low Pulse Width ; PHI0 ; Rise ; CXXXr|clk ; +; 489.000 ; 489.000 ; 0.000 ; High Pulse Width ; PHI0 ; Rise ; PHI0|combout ; +; 489.000 ; 489.000 ; 0.000 ; Low Pulse Width ; PHI0 ; Rise ; PHI0|combout ; +; 489.000 ; 489.000 ; 0.000 ; High Pulse Width ; PHI0 ; Rise ; RAr[0]|clk ; +; 489.000 ; 489.000 ; 0.000 ; Low Pulse Width ; PHI0 ; Rise ; RAr[0]|clk ; +; 489.000 ; 489.000 ; 0.000 ; High Pulse Width ; PHI0 ; Rise ; RAr[10]|clk ; +; 489.000 ; 489.000 ; 0.000 ; Low Pulse Width ; PHI0 ; Rise ; RAr[10]|clk ; +; 489.000 ; 489.000 ; 0.000 ; High Pulse Width ; PHI0 ; Rise ; RAr[11]|clk ; +; 489.000 ; 489.000 ; 0.000 ; Low Pulse Width ; PHI0 ; Rise ; RAr[11]|clk ; +; 489.000 ; 489.000 ; 0.000 ; High Pulse Width ; PHI0 ; Rise ; RAr[1]|clk ; +; 489.000 ; 489.000 ; 0.000 ; Low Pulse Width ; PHI0 ; Rise ; RAr[1]|clk ; +; 489.000 ; 489.000 ; 0.000 ; High Pulse Width ; PHI0 ; Rise ; RAr[2]|clk ; +; 489.000 ; 489.000 ; 0.000 ; Low Pulse Width ; PHI0 ; Rise ; RAr[2]|clk ; +; 489.000 ; 489.000 ; 0.000 ; High Pulse Width ; PHI0 ; Rise ; RAr[3]|clk ; +; 489.000 ; 489.000 ; 0.000 ; Low Pulse Width ; PHI0 ; Rise ; RAr[3]|clk ; +; 489.000 ; 489.000 ; 0.000 ; High Pulse Width ; PHI0 ; Rise ; RAr[4]|clk ; +; 489.000 ; 489.000 ; 0.000 ; Low Pulse Width ; PHI0 ; Rise ; RAr[4]|clk ; +; 489.000 ; 489.000 ; 0.000 ; High Pulse Width ; PHI0 ; Rise ; RAr[5]|clk ; +; 489.000 ; 489.000 ; 0.000 ; Low Pulse Width ; PHI0 ; Rise ; RAr[5]|clk ; +; 489.000 ; 489.000 ; 0.000 ; High Pulse Width ; PHI0 ; Rise ; RAr[6]|clk ; +; 489.000 ; 489.000 ; 0.000 ; Low Pulse Width ; PHI0 ; Rise ; RAr[6]|clk ; +; 489.000 ; 489.000 ; 0.000 ; High Pulse Width ; PHI0 ; Rise ; RAr[7]|clk ; +; 489.000 ; 489.000 ; 0.000 ; Low Pulse Width ; PHI0 ; Rise ; RAr[7]|clk ; +; 489.000 ; 489.000 ; 0.000 ; High Pulse Width ; PHI0 ; Rise ; RAr[8]|clk ; +; 489.000 ; 489.000 ; 0.000 ; Low Pulse Width ; PHI0 ; Rise ; RAr[8]|clk ; +; 489.000 ; 489.000 ; 0.000 ; High Pulse Width ; PHI0 ; Rise ; RAr[9]|clk ; +; 489.000 ; 489.000 ; 0.000 ; Low Pulse Width ; PHI0 ; Rise ; RAr[9]|clk ; +; 489.000 ; 489.000 ; 0.000 ; High Pulse Width ; PHI0 ; Rise ; nWEr|clk ; +; 489.000 ; 489.000 ; 0.000 ; Low Pulse Width ; PHI0 ; Rise ; nWEr|clk ; +; 974.000 ; 978.000 ; 4.000 ; Port Rate ; PHI0 ; Rise ; PHI0 ; ++---------+--------------+----------------+------------------+-------+------------+--------------+ +-------------------------------------------------------------------------+ @@ -614,65 +638,51 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-----------+------------+--------+--------+------------+-----------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+--------+--------+------------+-----------------+ -; MISO ; C25M ; 4.236 ; 4.236 ; Rise ; C25M ; -; MOSI ; C25M ; 4.174 ; 4.174 ; Rise ; C25M ; -; PHI0 ; C25M ; 2.780 ; 2.780 ; Rise ; C25M ; -; RA[*] ; C25M ; 13.704 ; 13.704 ; Rise ; C25M ; -; RA[0] ; C25M ; 9.040 ; 9.040 ; Rise ; C25M ; -; RA[1] ; C25M ; 10.111 ; 10.111 ; Rise ; C25M ; -; RA[2] ; C25M ; 11.221 ; 11.221 ; Rise ; C25M ; -; RA[3] ; C25M ; 11.322 ; 11.322 ; Rise ; C25M ; -; RA[4] ; C25M ; 6.069 ; 6.069 ; Rise ; C25M ; -; RA[5] ; C25M ; 5.790 ; 5.790 ; Rise ; C25M ; -; RA[6] ; C25M ; 7.139 ; 7.139 ; Rise ; C25M ; -; RA[7] ; C25M ; 10.088 ; 10.088 ; Rise ; C25M ; -; RA[8] ; C25M ; 13.349 ; 13.349 ; Rise ; C25M ; -; RA[9] ; C25M ; 13.704 ; 13.704 ; Rise ; C25M ; -; RA[10] ; C25M ; 12.357 ; 12.357 ; Rise ; C25M ; -; RA[11] ; C25M ; 12.145 ; 12.145 ; Rise ; C25M ; -; RA[12] ; C25M ; 12.246 ; 12.246 ; Rise ; C25M ; -; RA[13] ; C25M ; 11.874 ; 11.874 ; Rise ; C25M ; -; RA[14] ; C25M ; 12.544 ; 12.544 ; Rise ; C25M ; -; RA[15] ; C25M ; 11.995 ; 11.995 ; Rise ; C25M ; -; RD[*] ; C25M ; 6.903 ; 6.903 ; Rise ; C25M ; -; RD[0] ; C25M ; 4.401 ; 4.401 ; Rise ; C25M ; -; RD[1] ; C25M ; 4.653 ; 4.653 ; Rise ; C25M ; -; RD[2] ; C25M ; 3.968 ; 3.968 ; Rise ; C25M ; -; RD[3] ; C25M ; 4.146 ; 4.146 ; Rise ; C25M ; -; RD[4] ; C25M ; 4.101 ; 4.101 ; Rise ; C25M ; -; RD[5] ; C25M ; 4.868 ; 4.868 ; Rise ; C25M ; -; RD[6] ; C25M ; 4.516 ; 4.516 ; Rise ; C25M ; -; RD[7] ; C25M ; 6.903 ; 6.903 ; Rise ; C25M ; -; SD[*] ; C25M ; 5.643 ; 5.643 ; Rise ; C25M ; -; SD[0] ; C25M ; 4.467 ; 4.467 ; Rise ; C25M ; -; SD[1] ; C25M ; 5.643 ; 5.643 ; Rise ; C25M ; -; SD[2] ; C25M ; 3.772 ; 3.772 ; Rise ; C25M ; -; SD[3] ; C25M ; 3.824 ; 3.824 ; Rise ; C25M ; -; SD[4] ; C25M ; 4.593 ; 4.593 ; Rise ; C25M ; -; SD[5] ; C25M ; 4.266 ; 4.266 ; Rise ; C25M ; -; SD[6] ; C25M ; 3.851 ; 3.851 ; Rise ; C25M ; -; SD[7] ; C25M ; 3.789 ; 3.789 ; Rise ; C25M ; -; SetFW[*] ; C25M ; 3.175 ; 3.175 ; Rise ; C25M ; -; SetFW[0] ; C25M ; 2.614 ; 2.614 ; Rise ; C25M ; -; SetFW[1] ; C25M ; 3.175 ; 3.175 ; Rise ; C25M ; -; nDEVSEL ; C25M ; 8.361 ; 8.361 ; Rise ; C25M ; -; nIOSEL ; C25M ; 6.803 ; 6.803 ; Rise ; C25M ; -; nRES ; C25M ; 3.239 ; 3.239 ; Rise ; C25M ; -; RA[*] ; PHI0 ; 6.165 ; 6.165 ; Rise ; PHI0 ; -; RA[0] ; PHI0 ; 3.454 ; 3.454 ; Rise ; PHI0 ; -; RA[1] ; PHI0 ; 2.966 ; 2.966 ; Rise ; PHI0 ; -; RA[2] ; PHI0 ; 4.328 ; 4.328 ; Rise ; PHI0 ; -; RA[3] ; PHI0 ; 4.429 ; 4.429 ; Rise ; PHI0 ; -; RA[7] ; PHI0 ; 2.549 ; 2.549 ; Rise ; PHI0 ; -; RA[8] ; PHI0 ; 5.810 ; 5.810 ; Rise ; PHI0 ; -; RA[9] ; PHI0 ; 6.165 ; 6.165 ; Rise ; PHI0 ; -; RA[10] ; PHI0 ; 4.818 ; 4.818 ; Rise ; PHI0 ; -; RA[11] ; PHI0 ; 4.606 ; 4.606 ; Rise ; PHI0 ; -; RA[12] ; PHI0 ; 4.707 ; 4.707 ; Rise ; PHI0 ; -; RA[13] ; PHI0 ; 4.335 ; 4.335 ; Rise ; PHI0 ; -; RA[14] ; PHI0 ; 5.005 ; 5.005 ; Rise ; PHI0 ; -; RA[15] ; PHI0 ; 4.456 ; 4.456 ; Rise ; PHI0 ; -; nWE ; PHI0 ; 1.098 ; 1.098 ; Rise ; PHI0 ; +; MISO ; C25M ; 4.863 ; 4.863 ; Rise ; C25M ; +; MOSI ; C25M ; 3.316 ; 3.316 ; Rise ; C25M ; +; RD[*] ; C25M ; 6.278 ; 6.278 ; Rise ; C25M ; +; RD[0] ; C25M ; 4.055 ; 4.055 ; Rise ; C25M ; +; RD[1] ; C25M ; 3.822 ; 3.822 ; Rise ; C25M ; +; RD[2] ; C25M ; 3.312 ; 3.312 ; Rise ; C25M ; +; RD[3] ; C25M ; 3.974 ; 3.974 ; Rise ; C25M ; +; RD[4] ; C25M ; 3.441 ; 3.441 ; Rise ; C25M ; +; RD[5] ; C25M ; 3.969 ; 3.969 ; Rise ; C25M ; +; RD[6] ; C25M ; 6.278 ; 6.278 ; Rise ; C25M ; +; RD[7] ; C25M ; 4.093 ; 4.093 ; Rise ; C25M ; +; SetFW[*] ; C25M ; 4.149 ; 4.149 ; Rise ; C25M ; +; SetFW[0] ; C25M ; 4.149 ; 4.149 ; Rise ; C25M ; +; SetFW[1] ; C25M ; 3.738 ; 3.738 ; Rise ; C25M ; +; nDEVSEL ; C25M ; 9.957 ; 9.957 ; Rise ; C25M ; +; nIOSEL ; C25M ; 4.637 ; 4.637 ; Rise ; C25M ; +; nIOSTRB ; C25M ; 5.052 ; 5.052 ; Rise ; C25M ; +; nRES ; C25M ; 3.763 ; 3.763 ; Rise ; C25M ; +; SD[*] ; C25M ; 5.269 ; 5.269 ; Fall ; C25M ; +; SD[0] ; C25M ; 4.676 ; 4.676 ; Fall ; C25M ; +; SD[1] ; C25M ; 4.064 ; 4.064 ; Fall ; C25M ; +; SD[2] ; C25M ; 3.916 ; 3.916 ; Fall ; C25M ; +; SD[3] ; C25M ; 5.158 ; 5.158 ; Fall ; C25M ; +; SD[4] ; C25M ; 3.719 ; 3.719 ; Fall ; C25M ; +; SD[5] ; C25M ; 3.149 ; 3.149 ; Fall ; C25M ; +; SD[6] ; C25M ; 3.295 ; 3.295 ; Fall ; C25M ; +; SD[7] ; C25M ; 5.269 ; 5.269 ; Fall ; C25M ; +; RA[*] ; PHI0 ; 0.892 ; 0.892 ; Rise ; PHI0 ; +; RA[0] ; PHI0 ; 0.414 ; 0.414 ; Rise ; PHI0 ; +; RA[1] ; PHI0 ; 0.713 ; 0.713 ; Rise ; PHI0 ; +; RA[2] ; PHI0 ; 0.008 ; 0.008 ; Rise ; PHI0 ; +; RA[3] ; PHI0 ; 0.464 ; 0.464 ; Rise ; PHI0 ; +; RA[4] ; PHI0 ; -0.520 ; -0.520 ; Rise ; PHI0 ; +; RA[5] ; PHI0 ; 0.727 ; 0.727 ; Rise ; PHI0 ; +; RA[6] ; PHI0 ; -0.603 ; -0.603 ; Rise ; PHI0 ; +; RA[7] ; PHI0 ; -0.772 ; -0.772 ; Rise ; PHI0 ; +; RA[8] ; PHI0 ; -1.522 ; -1.522 ; Rise ; PHI0 ; +; RA[9] ; PHI0 ; -1.478 ; -1.478 ; Rise ; PHI0 ; +; RA[10] ; PHI0 ; 0.892 ; 0.892 ; Rise ; PHI0 ; +; RA[11] ; PHI0 ; -0.105 ; -0.105 ; Rise ; PHI0 ; +; RA[12] ; PHI0 ; -0.073 ; -0.073 ; Rise ; PHI0 ; +; RA[13] ; PHI0 ; -0.133 ; -0.133 ; Rise ; PHI0 ; +; RA[14] ; PHI0 ; -0.434 ; -0.434 ; Rise ; PHI0 ; +; RA[15] ; PHI0 ; 0.054 ; 0.054 ; Rise ; PHI0 ; +; nWE ; PHI0 ; 1.076 ; 1.076 ; Rise ; PHI0 ; +-----------+------------+--------+--------+------------+-----------------+ @@ -681,65 +691,51 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-----------+------------+--------+--------+------------+-----------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+--------+--------+------------+-----------------+ -; MISO ; C25M ; -3.682 ; -3.682 ; Rise ; C25M ; -; MOSI ; C25M ; -3.620 ; -3.620 ; Rise ; C25M ; -; PHI0 ; C25M ; -2.226 ; -2.226 ; Rise ; C25M ; -; RA[*] ; C25M ; -3.852 ; -3.852 ; Rise ; C25M ; -; RA[0] ; C25M ; -4.647 ; -4.647 ; Rise ; C25M ; -; RA[1] ; C25M ; -4.783 ; -4.783 ; Rise ; C25M ; -; RA[2] ; C25M ; -4.332 ; -4.332 ; Rise ; C25M ; -; RA[3] ; C25M ; -3.852 ; -3.852 ; Rise ; C25M ; -; RA[4] ; C25M ; -5.515 ; -5.515 ; Rise ; C25M ; -; RA[5] ; C25M ; -5.236 ; -5.236 ; Rise ; C25M ; -; RA[6] ; C25M ; -6.585 ; -6.585 ; Rise ; C25M ; -; RA[7] ; C25M ; -4.632 ; -4.632 ; Rise ; C25M ; -; RA[8] ; C25M ; -4.901 ; -4.901 ; Rise ; C25M ; -; RA[9] ; C25M ; -5.857 ; -5.857 ; Rise ; C25M ; -; RA[10] ; C25M ; -5.398 ; -5.398 ; Rise ; C25M ; -; RA[11] ; C25M ; -4.066 ; -4.066 ; Rise ; C25M ; -; RA[12] ; C25M ; -9.038 ; -9.038 ; Rise ; C25M ; -; RA[13] ; C25M ; -8.666 ; -8.666 ; Rise ; C25M ; -; RA[14] ; C25M ; -9.336 ; -9.336 ; Rise ; C25M ; -; RA[15] ; C25M ; -8.787 ; -8.787 ; Rise ; C25M ; -; RD[*] ; C25M ; -2.106 ; -2.106 ; Rise ; C25M ; -; RD[0] ; C25M ; -2.689 ; -2.689 ; Rise ; C25M ; -; RD[1] ; C25M ; -2.558 ; -2.558 ; Rise ; C25M ; -; RD[2] ; C25M ; -2.686 ; -2.686 ; Rise ; C25M ; -; RD[3] ; C25M ; -2.620 ; -2.620 ; Rise ; C25M ; -; RD[4] ; C25M ; -2.645 ; -2.645 ; Rise ; C25M ; -; RD[5] ; C25M ; -2.677 ; -2.677 ; Rise ; C25M ; -; RD[6] ; C25M ; -2.106 ; -2.106 ; Rise ; C25M ; -; RD[7] ; C25M ; -2.154 ; -2.154 ; Rise ; C25M ; -; SD[*] ; C25M ; -3.218 ; -3.218 ; Rise ; C25M ; -; SD[0] ; C25M ; -3.913 ; -3.913 ; Rise ; C25M ; -; SD[1] ; C25M ; -5.089 ; -5.089 ; Rise ; C25M ; -; SD[2] ; C25M ; -3.218 ; -3.218 ; Rise ; C25M ; -; SD[3] ; C25M ; -3.270 ; -3.270 ; Rise ; C25M ; -; SD[4] ; C25M ; -4.039 ; -4.039 ; Rise ; C25M ; -; SD[5] ; C25M ; -3.712 ; -3.712 ; Rise ; C25M ; -; SD[6] ; C25M ; -3.297 ; -3.297 ; Rise ; C25M ; -; SD[7] ; C25M ; -3.235 ; -3.235 ; Rise ; C25M ; -; SetFW[*] ; C25M ; -2.060 ; -2.060 ; Rise ; C25M ; -; SetFW[0] ; C25M ; -2.060 ; -2.060 ; Rise ; C25M ; -; SetFW[1] ; C25M ; -2.621 ; -2.621 ; Rise ; C25M ; -; nDEVSEL ; C25M ; -2.931 ; -2.931 ; Rise ; C25M ; -; nIOSEL ; C25M ; -6.016 ; -6.016 ; Rise ; C25M ; -; nRES ; C25M ; -2.685 ; -2.685 ; Rise ; C25M ; -; RA[*] ; PHI0 ; -0.955 ; -0.955 ; Rise ; PHI0 ; -; RA[0] ; PHI0 ; -2.900 ; -2.900 ; Rise ; PHI0 ; -; RA[1] ; PHI0 ; -2.412 ; -2.412 ; Rise ; PHI0 ; -; RA[2] ; PHI0 ; -3.774 ; -3.774 ; Rise ; PHI0 ; -; RA[3] ; PHI0 ; -3.875 ; -3.875 ; Rise ; PHI0 ; -; RA[7] ; PHI0 ; -1.995 ; -1.995 ; Rise ; PHI0 ; -; RA[8] ; PHI0 ; -2.159 ; -2.159 ; Rise ; PHI0 ; -; RA[9] ; PHI0 ; -2.514 ; -2.514 ; Rise ; PHI0 ; -; RA[10] ; PHI0 ; -1.167 ; -1.167 ; Rise ; PHI0 ; -; RA[11] ; PHI0 ; -0.955 ; -0.955 ; Rise ; PHI0 ; -; RA[12] ; PHI0 ; -3.055 ; -3.055 ; Rise ; PHI0 ; -; RA[13] ; PHI0 ; -2.683 ; -2.683 ; Rise ; PHI0 ; -; RA[14] ; PHI0 ; -3.353 ; -3.353 ; Rise ; PHI0 ; -; RA[15] ; PHI0 ; -2.804 ; -2.804 ; Rise ; PHI0 ; -; nWE ; PHI0 ; -0.009 ; -0.009 ; Rise ; PHI0 ; +; MISO ; C25M ; -4.309 ; -4.309 ; Rise ; C25M ; +; MOSI ; C25M ; -2.762 ; -2.762 ; Rise ; C25M ; +; RD[*] ; C25M ; -1.878 ; -1.878 ; Rise ; C25M ; +; RD[0] ; C25M ; -2.106 ; -2.106 ; Rise ; C25M ; +; RD[1] ; C25M ; -2.899 ; -2.899 ; Rise ; C25M ; +; RD[2] ; C25M ; -1.911 ; -1.911 ; Rise ; C25M ; +; RD[3] ; C25M ; -2.031 ; -2.031 ; Rise ; C25M ; +; RD[4] ; C25M ; -2.065 ; -2.065 ; Rise ; C25M ; +; RD[5] ; C25M ; -1.878 ; -1.878 ; Rise ; C25M ; +; RD[6] ; C25M ; -2.052 ; -2.052 ; Rise ; C25M ; +; RD[7] ; C25M ; -1.899 ; -1.899 ; Rise ; C25M ; +; SetFW[*] ; C25M ; -3.184 ; -3.184 ; Rise ; C25M ; +; SetFW[0] ; C25M ; -3.595 ; -3.595 ; Rise ; C25M ; +; SetFW[1] ; C25M ; -3.184 ; -3.184 ; Rise ; C25M ; +; nDEVSEL ; C25M ; -4.698 ; -4.698 ; Rise ; C25M ; +; nIOSEL ; C25M ; -4.076 ; -4.076 ; Rise ; C25M ; +; nIOSTRB ; C25M ; -3.232 ; -3.232 ; Rise ; C25M ; +; nRES ; C25M ; -3.209 ; -3.209 ; Rise ; C25M ; +; SD[*] ; C25M ; -2.595 ; -2.595 ; Fall ; C25M ; +; SD[0] ; C25M ; -4.122 ; -4.122 ; Fall ; C25M ; +; SD[1] ; C25M ; -3.510 ; -3.510 ; Fall ; C25M ; +; SD[2] ; C25M ; -3.362 ; -3.362 ; Fall ; C25M ; +; SD[3] ; C25M ; -4.604 ; -4.604 ; Fall ; C25M ; +; SD[4] ; C25M ; -3.165 ; -3.165 ; Fall ; C25M ; +; SD[5] ; C25M ; -2.595 ; -2.595 ; Fall ; C25M ; +; SD[6] ; C25M ; -2.741 ; -2.741 ; Fall ; C25M ; +; SD[7] ; C25M ; -4.715 ; -4.715 ; Fall ; C25M ; +; RA[*] ; PHI0 ; 2.076 ; 2.076 ; Rise ; PHI0 ; +; RA[0] ; PHI0 ; 0.140 ; 0.140 ; Rise ; PHI0 ; +; RA[1] ; PHI0 ; -0.159 ; -0.159 ; Rise ; PHI0 ; +; RA[2] ; PHI0 ; 0.546 ; 0.546 ; Rise ; PHI0 ; +; RA[3] ; PHI0 ; 0.090 ; 0.090 ; Rise ; PHI0 ; +; RA[4] ; PHI0 ; 1.074 ; 1.074 ; Rise ; PHI0 ; +; RA[5] ; PHI0 ; -0.173 ; -0.173 ; Rise ; PHI0 ; +; RA[6] ; PHI0 ; 1.157 ; 1.157 ; Rise ; PHI0 ; +; RA[7] ; PHI0 ; 1.326 ; 1.326 ; Rise ; PHI0 ; +; RA[8] ; PHI0 ; 2.076 ; 2.076 ; Rise ; PHI0 ; +; RA[9] ; PHI0 ; 2.032 ; 2.032 ; Rise ; PHI0 ; +; RA[10] ; PHI0 ; -0.338 ; -0.338 ; Rise ; PHI0 ; +; RA[11] ; PHI0 ; 0.659 ; 0.659 ; Rise ; PHI0 ; +; RA[12] ; PHI0 ; 0.627 ; 0.627 ; Rise ; PHI0 ; +; RA[13] ; PHI0 ; 0.687 ; 0.687 ; Rise ; PHI0 ; +; RA[14] ; PHI0 ; 0.988 ; 0.988 ; Rise ; PHI0 ; +; RA[15] ; PHI0 ; 0.500 ; 0.500 ; Rise ; PHI0 ; +; nWE ; PHI0 ; -0.522 ; -0.522 ; Rise ; PHI0 ; +-----------+------------+--------+--------+------------+-----------------+ @@ -748,55 +744,55 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-----------+------------+--------+--------+------------+-----------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+--------+--------+------------+-----------------+ -; DQMH ; C25M ; 9.305 ; 9.305 ; Rise ; C25M ; -; DQML ; C25M ; 9.483 ; 9.483 ; Rise ; C25M ; -; FCK ; C25M ; 9.008 ; 9.008 ; Rise ; C25M ; -; MOSI ; C25M ; 8.844 ; 8.844 ; Rise ; C25M ; -; RCKE ; C25M ; 9.013 ; 9.013 ; Rise ; C25M ; -; RD[*] ; C25M ; 9.287 ; 9.287 ; Rise ; C25M ; -; RD[0] ; C25M ; 8.456 ; 8.456 ; Rise ; C25M ; -; RD[1] ; C25M ; 8.246 ; 8.246 ; Rise ; C25M ; -; RD[2] ; C25M ; 8.212 ; 8.212 ; Rise ; C25M ; -; RD[3] ; C25M ; 8.920 ; 8.920 ; Rise ; C25M ; -; RD[4] ; C25M ; 8.200 ; 8.200 ; Rise ; C25M ; -; RD[5] ; C25M ; 8.222 ; 8.222 ; Rise ; C25M ; -; RD[6] ; C25M ; 8.841 ; 8.841 ; Rise ; C25M ; -; RD[7] ; C25M ; 9.287 ; 9.287 ; Rise ; C25M ; -; RDdir ; C25M ; 13.847 ; 13.847 ; Rise ; C25M ; -; SA[*] ; C25M ; 9.270 ; 9.270 ; Rise ; C25M ; -; SA[0] ; C25M ; 8.917 ; 8.917 ; Rise ; C25M ; -; SA[1] ; C25M ; 8.665 ; 8.665 ; Rise ; C25M ; -; SA[2] ; C25M ; 9.270 ; 9.270 ; Rise ; C25M ; -; SA[3] ; C25M ; 8.223 ; 8.223 ; Rise ; C25M ; -; SA[4] ; C25M ; 8.244 ; 8.244 ; Rise ; C25M ; -; SA[5] ; C25M ; 8.115 ; 8.115 ; Rise ; C25M ; -; SA[6] ; C25M ; 8.104 ; 8.104 ; Rise ; C25M ; -; SA[7] ; C25M ; 8.114 ; 8.114 ; Rise ; C25M ; -; SA[8] ; C25M ; 8.229 ; 8.229 ; Rise ; C25M ; -; SA[9] ; C25M ; 8.975 ; 8.975 ; Rise ; C25M ; -; SA[10] ; C25M ; 6.951 ; 6.951 ; Rise ; C25M ; -; SA[11] ; C25M ; 8.922 ; 8.922 ; Rise ; C25M ; -; SA[12] ; C25M ; 8.773 ; 8.773 ; Rise ; C25M ; -; SBA[*] ; C25M ; 8.182 ; 8.182 ; Rise ; C25M ; -; SBA[0] ; C25M ; 8.182 ; 8.182 ; Rise ; C25M ; -; SBA[1] ; C25M ; 6.923 ; 6.923 ; Rise ; C25M ; -; SD[*] ; C25M ; 9.179 ; 9.179 ; Rise ; C25M ; -; SD[0] ; C25M ; 6.937 ; 6.937 ; Rise ; C25M ; -; SD[1] ; C25M ; 9.179 ; 9.179 ; Rise ; C25M ; -; SD[2] ; C25M ; 7.562 ; 7.562 ; Rise ; C25M ; -; SD[3] ; C25M ; 7.576 ; 7.576 ; Rise ; C25M ; -; SD[4] ; C25M ; 8.135 ; 8.135 ; Rise ; C25M ; -; SD[5] ; C25M ; 6.944 ; 6.944 ; Rise ; C25M ; -; SD[6] ; C25M ; 7.570 ; 7.570 ; Rise ; C25M ; -; SD[7] ; C25M ; 7.556 ; 7.556 ; Rise ; C25M ; -; nCAS ; C25M ; 8.431 ; 8.431 ; Rise ; C25M ; -; nFCS ; C25M ; 8.772 ; 8.772 ; Rise ; C25M ; -; nRAS ; C25M ; 8.114 ; 8.114 ; Rise ; C25M ; -; nRCS ; C25M ; 9.195 ; 9.195 ; Rise ; C25M ; -; nRESout ; C25M ; 8.037 ; 8.037 ; Rise ; C25M ; -; nSWE ; C25M ; 8.335 ; 8.335 ; Rise ; C25M ; -; RDdir ; PHI0 ; 11.354 ; 11.354 ; Rise ; PHI0 ; -; RDdir ; PHI0 ; 11.354 ; 11.354 ; Fall ; PHI0 ; +; DQMH ; C25M ; 17.381 ; 17.381 ; Rise ; C25M ; +; DQML ; C25M ; 17.650 ; 17.650 ; Rise ; C25M ; +; FCK ; C25M ; 17.362 ; 17.362 ; Rise ; C25M ; +; MOSI ; C25M ; 17.251 ; 17.251 ; Rise ; C25M ; +; RCKE ; C25M ; 17.169 ; 17.169 ; Rise ; C25M ; +; RDdir ; C25M ; 23.995 ; 23.995 ; Rise ; C25M ; +; SA[*] ; C25M ; 18.571 ; 18.571 ; Rise ; C25M ; +; SA[0] ; C25M ; 15.989 ; 15.989 ; Rise ; C25M ; +; SA[1] ; C25M ; 17.051 ; 17.051 ; Rise ; C25M ; +; SA[2] ; C25M ; 17.460 ; 17.460 ; Rise ; C25M ; +; SA[3] ; C25M ; 18.571 ; 18.571 ; Rise ; C25M ; +; SA[4] ; C25M ; 17.861 ; 17.861 ; Rise ; C25M ; +; SA[5] ; C25M ; 17.846 ; 17.846 ; Rise ; C25M ; +; SA[6] ; C25M ; 17.924 ; 17.924 ; Rise ; C25M ; +; SA[7] ; C25M ; 17.771 ; 17.771 ; Rise ; C25M ; +; SA[8] ; C25M ; 17.826 ; 17.826 ; Rise ; C25M ; +; SA[9] ; C25M ; 17.029 ; 17.029 ; Rise ; C25M ; +; SA[10] ; C25M ; 17.820 ; 17.820 ; Rise ; C25M ; +; SA[11] ; C25M ; 17.097 ; 17.097 ; Rise ; C25M ; +; SA[12] ; C25M ; 18.520 ; 18.520 ; Rise ; C25M ; +; SBA[*] ; C25M ; 18.530 ; 18.530 ; Rise ; C25M ; +; SBA[0] ; C25M ; 17.892 ; 17.892 ; Rise ; C25M ; +; SBA[1] ; C25M ; 18.530 ; 18.530 ; Rise ; C25M ; +; SD[*] ; C25M ; 17.061 ; 17.061 ; Rise ; C25M ; +; SD[0] ; C25M ; 17.061 ; 17.061 ; Rise ; C25M ; +; SD[1] ; C25M ; 15.918 ; 15.918 ; Rise ; C25M ; +; SD[2] ; C25M ; 16.402 ; 16.402 ; Rise ; C25M ; +; SD[3] ; C25M ; 16.297 ; 16.297 ; Rise ; C25M ; +; SD[4] ; C25M ; 15.834 ; 15.834 ; Rise ; C25M ; +; SD[5] ; C25M ; 16.821 ; 16.821 ; Rise ; C25M ; +; SD[6] ; C25M ; 16.477 ; 16.477 ; Rise ; C25M ; +; SD[7] ; C25M ; 16.328 ; 16.328 ; Rise ; C25M ; +; nCAS ; C25M ; 17.133 ; 17.133 ; Rise ; C25M ; +; nFCS ; C25M ; 17.510 ; 17.510 ; Rise ; C25M ; +; nRAS ; C25M ; 15.968 ; 15.968 ; Rise ; C25M ; +; nRCS ; C25M ; 17.139 ; 17.139 ; Rise ; C25M ; +; nRESout ; C25M ; 17.067 ; 17.067 ; Rise ; C25M ; +; nSWE ; C25M ; 17.830 ; 17.830 ; Rise ; C25M ; +; RD[*] ; C25M ; 10.221 ; 10.221 ; Fall ; C25M ; +; RD[0] ; C25M ; 8.885 ; 8.885 ; Fall ; C25M ; +; RD[1] ; C25M ; 9.048 ; 9.048 ; Fall ; C25M ; +; RD[2] ; C25M ; 9.448 ; 9.448 ; Fall ; C25M ; +; RD[3] ; C25M ; 9.926 ; 9.926 ; Fall ; C25M ; +; RD[4] ; C25M ; 9.443 ; 9.443 ; Fall ; C25M ; +; RD[5] ; C25M ; 10.114 ; 10.114 ; Fall ; C25M ; +; RD[6] ; C25M ; 9.651 ; 9.651 ; Fall ; C25M ; +; RD[7] ; C25M ; 10.221 ; 10.221 ; Fall ; C25M ; +; RDdir ; PHI0 ; 21.935 ; 21.935 ; Rise ; PHI0 ; +; RDdir ; PHI0 ; 21.935 ; 21.935 ; Fall ; PHI0 ; +-----------+------------+--------+--------+------------+-----------------+ @@ -805,55 +801,55 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-----------+------------+--------+--------+------------+-----------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+--------+--------+------------+-----------------+ -; DQMH ; C25M ; 9.305 ; 9.305 ; Rise ; C25M ; -; DQML ; C25M ; 9.483 ; 9.483 ; Rise ; C25M ; -; FCK ; C25M ; 9.008 ; 9.008 ; Rise ; C25M ; -; MOSI ; C25M ; 8.844 ; 8.844 ; Rise ; C25M ; -; RCKE ; C25M ; 9.013 ; 9.013 ; Rise ; C25M ; -; RD[*] ; C25M ; 8.200 ; 8.200 ; Rise ; C25M ; -; RD[0] ; C25M ; 8.456 ; 8.456 ; Rise ; C25M ; -; RD[1] ; C25M ; 8.246 ; 8.246 ; Rise ; C25M ; -; RD[2] ; C25M ; 8.212 ; 8.212 ; Rise ; C25M ; -; RD[3] ; C25M ; 8.920 ; 8.920 ; Rise ; C25M ; -; RD[4] ; C25M ; 8.200 ; 8.200 ; Rise ; C25M ; -; RD[5] ; C25M ; 8.222 ; 8.222 ; Rise ; C25M ; -; RD[6] ; C25M ; 8.841 ; 8.841 ; Rise ; C25M ; -; RD[7] ; C25M ; 9.287 ; 9.287 ; Rise ; C25M ; -; RDdir ; C25M ; 11.009 ; 11.009 ; Rise ; C25M ; -; SA[*] ; C25M ; 6.951 ; 6.951 ; Rise ; C25M ; -; SA[0] ; C25M ; 8.917 ; 8.917 ; Rise ; C25M ; -; SA[1] ; C25M ; 8.665 ; 8.665 ; Rise ; C25M ; -; SA[2] ; C25M ; 9.270 ; 9.270 ; Rise ; C25M ; -; SA[3] ; C25M ; 8.223 ; 8.223 ; Rise ; C25M ; -; SA[4] ; C25M ; 8.244 ; 8.244 ; Rise ; C25M ; -; SA[5] ; C25M ; 8.115 ; 8.115 ; Rise ; C25M ; -; SA[6] ; C25M ; 8.104 ; 8.104 ; Rise ; C25M ; -; SA[7] ; C25M ; 8.114 ; 8.114 ; Rise ; C25M ; -; SA[8] ; C25M ; 8.229 ; 8.229 ; Rise ; C25M ; -; SA[9] ; C25M ; 8.975 ; 8.975 ; Rise ; C25M ; -; SA[10] ; C25M ; 6.951 ; 6.951 ; Rise ; C25M ; -; SA[11] ; C25M ; 8.922 ; 8.922 ; Rise ; C25M ; -; SA[12] ; C25M ; 8.773 ; 8.773 ; Rise ; C25M ; -; SBA[*] ; C25M ; 6.923 ; 6.923 ; Rise ; C25M ; -; SBA[0] ; C25M ; 8.182 ; 8.182 ; Rise ; C25M ; -; SBA[1] ; C25M ; 6.923 ; 6.923 ; Rise ; C25M ; -; SD[*] ; C25M ; 6.937 ; 6.937 ; Rise ; C25M ; -; SD[0] ; C25M ; 6.937 ; 6.937 ; Rise ; C25M ; -; SD[1] ; C25M ; 9.179 ; 9.179 ; Rise ; C25M ; -; SD[2] ; C25M ; 7.562 ; 7.562 ; Rise ; C25M ; -; SD[3] ; C25M ; 7.576 ; 7.576 ; Rise ; C25M ; -; SD[4] ; C25M ; 8.135 ; 8.135 ; Rise ; C25M ; -; SD[5] ; C25M ; 6.944 ; 6.944 ; Rise ; C25M ; -; SD[6] ; C25M ; 7.570 ; 7.570 ; Rise ; C25M ; -; SD[7] ; C25M ; 7.556 ; 7.556 ; Rise ; C25M ; -; nCAS ; C25M ; 8.431 ; 8.431 ; Rise ; C25M ; -; nFCS ; C25M ; 8.772 ; 8.772 ; Rise ; C25M ; -; nRAS ; C25M ; 8.114 ; 8.114 ; Rise ; C25M ; -; nRCS ; C25M ; 9.195 ; 9.195 ; Rise ; C25M ; -; nRESout ; C25M ; 8.037 ; 8.037 ; Rise ; C25M ; -; nSWE ; C25M ; 8.335 ; 8.335 ; Rise ; C25M ; -; RDdir ; PHI0 ; 11.354 ; 11.354 ; Rise ; PHI0 ; -; RDdir ; PHI0 ; 11.354 ; 11.354 ; Fall ; PHI0 ; +; DQMH ; C25M ; 17.381 ; 17.381 ; Rise ; C25M ; +; DQML ; C25M ; 17.650 ; 17.650 ; Rise ; C25M ; +; FCK ; C25M ; 17.362 ; 17.362 ; Rise ; C25M ; +; MOSI ; C25M ; 17.251 ; 17.251 ; Rise ; C25M ; +; RCKE ; C25M ; 17.169 ; 17.169 ; Rise ; C25M ; +; RDdir ; C25M ; 20.487 ; 20.487 ; Rise ; C25M ; +; SA[*] ; C25M ; 15.989 ; 15.989 ; Rise ; C25M ; +; SA[0] ; C25M ; 15.989 ; 15.989 ; Rise ; C25M ; +; SA[1] ; C25M ; 17.051 ; 17.051 ; Rise ; C25M ; +; SA[2] ; C25M ; 17.460 ; 17.460 ; Rise ; C25M ; +; SA[3] ; C25M ; 18.571 ; 18.571 ; Rise ; C25M ; +; SA[4] ; C25M ; 17.861 ; 17.861 ; Rise ; C25M ; +; SA[5] ; C25M ; 17.846 ; 17.846 ; Rise ; C25M ; +; SA[6] ; C25M ; 17.924 ; 17.924 ; Rise ; C25M ; +; SA[7] ; C25M ; 17.771 ; 17.771 ; Rise ; C25M ; +; SA[8] ; C25M ; 17.826 ; 17.826 ; Rise ; C25M ; +; SA[9] ; C25M ; 17.029 ; 17.029 ; Rise ; C25M ; +; SA[10] ; C25M ; 17.820 ; 17.820 ; Rise ; C25M ; +; SA[11] ; C25M ; 17.097 ; 17.097 ; Rise ; C25M ; +; SA[12] ; C25M ; 18.520 ; 18.520 ; Rise ; C25M ; +; SBA[*] ; C25M ; 17.892 ; 17.892 ; Rise ; C25M ; +; SBA[0] ; C25M ; 17.892 ; 17.892 ; Rise ; C25M ; +; SBA[1] ; C25M ; 18.530 ; 18.530 ; Rise ; C25M ; +; SD[*] ; C25M ; 15.834 ; 15.834 ; Rise ; C25M ; +; SD[0] ; C25M ; 17.061 ; 17.061 ; Rise ; C25M ; +; SD[1] ; C25M ; 15.918 ; 15.918 ; Rise ; C25M ; +; SD[2] ; C25M ; 16.402 ; 16.402 ; Rise ; C25M ; +; SD[3] ; C25M ; 16.297 ; 16.297 ; Rise ; C25M ; +; SD[4] ; C25M ; 15.834 ; 15.834 ; Rise ; C25M ; +; SD[5] ; C25M ; 16.821 ; 16.821 ; Rise ; C25M ; +; SD[6] ; C25M ; 16.477 ; 16.477 ; Rise ; C25M ; +; SD[7] ; C25M ; 16.328 ; 16.328 ; Rise ; C25M ; +; nCAS ; C25M ; 17.133 ; 17.133 ; Rise ; C25M ; +; nFCS ; C25M ; 17.510 ; 17.510 ; Rise ; C25M ; +; nRAS ; C25M ; 15.968 ; 15.968 ; Rise ; C25M ; +; nRCS ; C25M ; 17.139 ; 17.139 ; Rise ; C25M ; +; nRESout ; C25M ; 17.067 ; 17.067 ; Rise ; C25M ; +; nSWE ; C25M ; 17.830 ; 17.830 ; Rise ; C25M ; +; RD[*] ; C25M ; 8.885 ; 8.885 ; Fall ; C25M ; +; RD[0] ; C25M ; 8.885 ; 8.885 ; Fall ; C25M ; +; RD[1] ; C25M ; 9.048 ; 9.048 ; Fall ; C25M ; +; RD[2] ; C25M ; 9.448 ; 9.448 ; Fall ; C25M ; +; RD[3] ; C25M ; 9.926 ; 9.926 ; Fall ; C25M ; +; RD[4] ; C25M ; 9.443 ; 9.443 ; Fall ; C25M ; +; RD[5] ; C25M ; 10.114 ; 10.114 ; Fall ; C25M ; +; RD[6] ; C25M ; 9.651 ; 9.651 ; Fall ; C25M ; +; RD[7] ; C25M ; 10.221 ; 10.221 ; Fall ; C25M ; +; RDdir ; PHI0 ; 21.935 ; 21.935 ; Rise ; PHI0 ; +; RDdir ; PHI0 ; 21.935 ; 21.935 ; Fall ; PHI0 ; +-----------+------------+--------+--------+------------+-----------------+ @@ -862,44 +858,143 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +------------+-------------+--------+----+----+--------+ ; Input Port ; Output Port ; RR ; RF ; FR ; FF ; +------------+-------------+--------+----+----+--------+ -; DMAin ; DMAout ; 8.420 ; ; ; 8.420 ; -; INTin ; INTout ; 8.852 ; ; ; 8.852 ; -; nDEVSEL ; RD[0] ; 13.908 ; ; ; 13.908 ; -; nDEVSEL ; RD[1] ; 13.908 ; ; ; 13.908 ; -; nDEVSEL ; RD[2] ; 13.908 ; ; ; 13.908 ; -; nDEVSEL ; RD[3] ; 13.908 ; ; ; 13.908 ; -; nDEVSEL ; RD[4] ; 13.908 ; ; ; 13.908 ; -; nDEVSEL ; RD[5] ; 13.908 ; ; ; 13.908 ; -; nDEVSEL ; RD[6] ; 13.954 ; ; ; 13.954 ; -; nDEVSEL ; RD[7] ; 13.954 ; ; ; 13.954 ; -; nDEVSEL ; RDdir ; 15.512 ; ; ; 15.512 ; -; nIOSEL ; RD[0] ; 13.721 ; ; ; 13.721 ; -; nIOSEL ; RD[1] ; 13.721 ; ; ; 13.721 ; -; nIOSEL ; RD[2] ; 13.721 ; ; ; 13.721 ; -; nIOSEL ; RD[3] ; 13.721 ; ; ; 13.721 ; -; nIOSEL ; RD[4] ; 13.721 ; ; ; 13.721 ; -; nIOSEL ; RD[5] ; 13.721 ; ; ; 13.721 ; -; nIOSEL ; RD[6] ; 13.767 ; ; ; 13.767 ; -; nIOSEL ; RD[7] ; 13.767 ; ; ; 13.767 ; -; nIOSEL ; RDdir ; 15.325 ; ; ; 15.325 ; -; nIOSTRB ; RD[0] ; 13.574 ; ; ; 13.574 ; -; nIOSTRB ; RD[1] ; 13.574 ; ; ; 13.574 ; -; nIOSTRB ; RD[2] ; 13.574 ; ; ; 13.574 ; -; nIOSTRB ; RD[3] ; 13.574 ; ; ; 13.574 ; -; nIOSTRB ; RD[4] ; 13.574 ; ; ; 13.574 ; -; nIOSTRB ; RD[5] ; 13.574 ; ; ; 13.574 ; -; nIOSTRB ; RD[6] ; 13.620 ; ; ; 13.620 ; -; nIOSTRB ; RD[7] ; 13.620 ; ; ; 13.620 ; -; nIOSTRB ; RDdir ; 15.178 ; ; ; 15.178 ; -; nWE ; RD[0] ; 10.209 ; ; ; 10.209 ; -; nWE ; RD[1] ; 10.209 ; ; ; 10.209 ; -; nWE ; RD[2] ; 10.209 ; ; ; 10.209 ; -; nWE ; RD[3] ; 10.209 ; ; ; 10.209 ; -; nWE ; RD[4] ; 10.209 ; ; ; 10.209 ; -; nWE ; RD[5] ; 10.209 ; ; ; 10.209 ; -; nWE ; RD[6] ; 10.255 ; ; ; 10.255 ; -; nWE ; RD[7] ; 10.255 ; ; ; 10.255 ; -; nWE ; RDdir ; 11.813 ; ; ; 11.813 ; +; DMAin ; DMAout ; 8.665 ; ; ; 8.665 ; +; INTin ; INTout ; 8.862 ; ; ; 8.862 ; +; RA[0] ; RD[0] ; 13.610 ; ; ; 13.610 ; +; RA[0] ; RD[1] ; 13.610 ; ; ; 13.610 ; +; RA[0] ; RD[2] ; 13.610 ; ; ; 13.610 ; +; RA[0] ; RD[3] ; 13.610 ; ; ; 13.610 ; +; RA[0] ; RD[4] ; 13.610 ; ; ; 13.610 ; +; RA[0] ; RD[5] ; 13.610 ; ; ; 13.610 ; +; RA[0] ; RD[6] ; 13.565 ; ; ; 13.565 ; +; RA[0] ; RD[7] ; 13.565 ; ; ; 13.565 ; +; RA[0] ; RDdir ; 23.870 ; ; ; 23.870 ; +; RA[1] ; RD[0] ; 12.760 ; ; ; 12.760 ; +; RA[1] ; RD[1] ; 12.760 ; ; ; 12.760 ; +; RA[1] ; RD[2] ; 12.760 ; ; ; 12.760 ; +; RA[1] ; RD[3] ; 12.760 ; ; ; 12.760 ; +; RA[1] ; RD[4] ; 12.760 ; ; ; 12.760 ; +; RA[1] ; RD[5] ; 12.760 ; ; ; 12.760 ; +; RA[1] ; RD[6] ; 12.715 ; ; ; 12.715 ; +; RA[1] ; RD[7] ; 12.715 ; ; ; 12.715 ; +; RA[1] ; RDdir ; 23.020 ; ; ; 23.020 ; +; RA[2] ; RD[0] ; 13.252 ; ; ; 13.252 ; +; RA[2] ; RD[1] ; 13.252 ; ; ; 13.252 ; +; RA[2] ; RD[2] ; 13.252 ; ; ; 13.252 ; +; RA[2] ; RD[3] ; 13.252 ; ; ; 13.252 ; +; RA[2] ; RD[4] ; 13.252 ; ; ; 13.252 ; +; RA[2] ; RD[5] ; 13.252 ; ; ; 13.252 ; +; RA[2] ; RD[6] ; 13.207 ; ; ; 13.207 ; +; RA[2] ; RD[7] ; 13.207 ; ; ; 13.207 ; +; RA[2] ; RDdir ; 23.512 ; ; ; 23.512 ; +; RA[3] ; RD[0] ; 13.532 ; ; ; 13.532 ; +; RA[3] ; RD[1] ; 13.532 ; ; ; 13.532 ; +; RA[3] ; RD[2] ; 13.532 ; ; ; 13.532 ; +; RA[3] ; RD[3] ; 13.532 ; ; ; 13.532 ; +; RA[3] ; RD[4] ; 13.532 ; ; ; 13.532 ; +; RA[3] ; RD[5] ; 13.532 ; ; ; 13.532 ; +; RA[3] ; RD[6] ; 13.487 ; ; ; 13.487 ; +; RA[3] ; RD[7] ; 13.487 ; ; ; 13.487 ; +; RA[3] ; RDdir ; 23.792 ; ; ; 23.792 ; +; RA[4] ; RD[0] ; 13.442 ; ; ; 13.442 ; +; RA[4] ; RD[1] ; 13.442 ; ; ; 13.442 ; +; RA[4] ; RD[2] ; 13.442 ; ; ; 13.442 ; +; RA[4] ; RD[3] ; 13.442 ; ; ; 13.442 ; +; RA[4] ; RD[4] ; 13.442 ; ; ; 13.442 ; +; RA[4] ; RD[5] ; 13.442 ; ; ; 13.442 ; +; RA[4] ; RD[6] ; 13.397 ; ; ; 13.397 ; +; RA[4] ; RD[7] ; 13.397 ; ; ; 13.397 ; +; RA[4] ; RDdir ; 23.702 ; ; ; 23.702 ; +; RA[5] ; RD[0] ; 13.393 ; ; ; 13.393 ; +; RA[5] ; RD[1] ; 13.393 ; ; ; 13.393 ; +; RA[5] ; RD[2] ; 13.393 ; ; ; 13.393 ; +; RA[5] ; RD[3] ; 13.393 ; ; ; 13.393 ; +; RA[5] ; RD[4] ; 13.393 ; ; ; 13.393 ; +; RA[5] ; RD[5] ; 13.393 ; ; ; 13.393 ; +; RA[5] ; RD[6] ; 13.348 ; ; ; 13.348 ; +; RA[5] ; RD[7] ; 13.348 ; ; ; 13.348 ; +; RA[5] ; RDdir ; 23.653 ; ; ; 23.653 ; +; RA[6] ; RD[0] ; 13.690 ; ; ; 13.690 ; +; RA[6] ; RD[1] ; 13.690 ; ; ; 13.690 ; +; RA[6] ; RD[2] ; 13.690 ; ; ; 13.690 ; +; RA[6] ; RD[3] ; 13.690 ; ; ; 13.690 ; +; RA[6] ; RD[4] ; 13.690 ; ; ; 13.690 ; +; RA[6] ; RD[5] ; 13.690 ; ; ; 13.690 ; +; RA[6] ; RD[6] ; 13.645 ; ; ; 13.645 ; +; RA[6] ; RD[7] ; 13.645 ; ; ; 13.645 ; +; RA[6] ; RDdir ; 23.950 ; ; ; 23.950 ; +; RA[7] ; RD[0] ; 12.122 ; ; ; 12.122 ; +; RA[7] ; RD[1] ; 12.122 ; ; ; 12.122 ; +; RA[7] ; RD[2] ; 12.122 ; ; ; 12.122 ; +; RA[7] ; RD[3] ; 12.122 ; ; ; 12.122 ; +; RA[7] ; RD[4] ; 12.122 ; ; ; 12.122 ; +; RA[7] ; RD[5] ; 12.122 ; ; ; 12.122 ; +; RA[7] ; RD[6] ; 12.077 ; ; ; 12.077 ; +; RA[7] ; RD[7] ; 12.077 ; ; ; 12.077 ; +; RA[7] ; RDdir ; 22.382 ; ; ; 22.382 ; +; RA[8] ; RD[0] ; 11.505 ; ; ; 11.505 ; +; RA[8] ; RD[1] ; 11.505 ; ; ; 11.505 ; +; RA[8] ; RD[2] ; 11.505 ; ; ; 11.505 ; +; RA[8] ; RD[3] ; 11.505 ; ; ; 11.505 ; +; RA[8] ; RD[4] ; 11.505 ; ; ; 11.505 ; +; RA[8] ; RD[5] ; 11.505 ; ; ; 11.505 ; +; RA[8] ; RD[6] ; 11.460 ; ; ; 11.460 ; +; RA[8] ; RD[7] ; 11.460 ; ; ; 11.460 ; +; RA[8] ; RDdir ; 21.765 ; ; ; 21.765 ; +; RA[9] ; RD[0] ; 11.899 ; ; ; 11.899 ; +; RA[9] ; RD[1] ; 11.899 ; ; ; 11.899 ; +; RA[9] ; RD[2] ; 11.899 ; ; ; 11.899 ; +; RA[9] ; RD[3] ; 11.899 ; ; ; 11.899 ; +; RA[9] ; RD[4] ; 11.899 ; ; ; 11.899 ; +; RA[9] ; RD[5] ; 11.899 ; ; ; 11.899 ; +; RA[9] ; RD[6] ; 11.854 ; ; ; 11.854 ; +; RA[9] ; RD[7] ; 11.854 ; ; ; 11.854 ; +; RA[9] ; RDdir ; 22.159 ; ; ; 22.159 ; +; RA[10] ; RD[0] ; 13.038 ; ; ; 13.038 ; +; RA[10] ; RD[1] ; 13.038 ; ; ; 13.038 ; +; RA[10] ; RD[2] ; 13.038 ; ; ; 13.038 ; +; RA[10] ; RD[3] ; 13.038 ; ; ; 13.038 ; +; RA[10] ; RD[4] ; 13.038 ; ; ; 13.038 ; +; RA[10] ; RD[5] ; 13.038 ; ; ; 13.038 ; +; RA[10] ; RD[6] ; 12.993 ; ; ; 12.993 ; +; RA[10] ; RD[7] ; 12.993 ; ; ; 12.993 ; +; RA[10] ; RDdir ; 23.298 ; ; ; 23.298 ; +; nDEVSEL ; RD[0] ; 11.136 ; ; ; 11.136 ; +; nDEVSEL ; RD[1] ; 11.136 ; ; ; 11.136 ; +; nDEVSEL ; RD[2] ; 11.136 ; ; ; 11.136 ; +; nDEVSEL ; RD[3] ; 11.136 ; ; ; 11.136 ; +; nDEVSEL ; RD[4] ; 11.136 ; ; ; 11.136 ; +; nDEVSEL ; RD[5] ; 11.136 ; ; ; 11.136 ; +; nDEVSEL ; RD[6] ; 11.091 ; ; ; 11.091 ; +; nDEVSEL ; RD[7] ; 11.091 ; ; ; 11.091 ; +; nDEVSEL ; RDdir ; 21.396 ; ; ; 21.396 ; +; nIOSEL ; RD[0] ; 11.071 ; ; ; 11.071 ; +; nIOSEL ; RD[1] ; 11.071 ; ; ; 11.071 ; +; nIOSEL ; RD[2] ; 11.071 ; ; ; 11.071 ; +; nIOSEL ; RD[3] ; 11.071 ; ; ; 11.071 ; +; nIOSEL ; RD[4] ; 11.071 ; ; ; 11.071 ; +; nIOSEL ; RD[5] ; 11.071 ; ; ; 11.071 ; +; nIOSEL ; RD[6] ; 11.026 ; ; ; 11.026 ; +; nIOSEL ; RD[7] ; 11.026 ; ; ; 11.026 ; +; nIOSEL ; RDdir ; 21.331 ; ; ; 21.331 ; +; nIOSTRB ; RD[0] ; 12.415 ; ; ; 12.415 ; +; nIOSTRB ; RD[1] ; 12.415 ; ; ; 12.415 ; +; nIOSTRB ; RD[2] ; 12.415 ; ; ; 12.415 ; +; nIOSTRB ; RD[3] ; 12.415 ; ; ; 12.415 ; +; nIOSTRB ; RD[4] ; 12.415 ; ; ; 12.415 ; +; nIOSTRB ; RD[5] ; 12.415 ; ; ; 12.415 ; +; nIOSTRB ; RD[6] ; 12.370 ; ; ; 12.370 ; +; nIOSTRB ; RD[7] ; 12.370 ; ; ; 12.370 ; +; nIOSTRB ; RDdir ; 22.675 ; ; ; 22.675 ; +; nWE ; RD[0] ; 13.158 ; ; ; 13.158 ; +; nWE ; RD[1] ; 13.158 ; ; ; 13.158 ; +; nWE ; RD[2] ; 13.158 ; ; ; 13.158 ; +; nWE ; RD[3] ; 13.158 ; ; ; 13.158 ; +; nWE ; RD[4] ; 13.158 ; ; ; 13.158 ; +; nWE ; RD[5] ; 13.158 ; ; ; 13.158 ; +; nWE ; RD[6] ; 13.113 ; ; ; 13.113 ; +; nWE ; RD[7] ; 13.113 ; ; ; 13.113 ; +; nWE ; RDdir ; 23.418 ; ; ; 23.418 ; +------------+-------------+--------+----+----+--------+ @@ -908,44 +1003,143 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +------------+-------------+--------+----+----+--------+ ; Input Port ; Output Port ; RR ; RF ; FR ; FF ; +------------+-------------+--------+----+----+--------+ -; DMAin ; DMAout ; 8.420 ; ; ; 8.420 ; -; INTin ; INTout ; 8.852 ; ; ; 8.852 ; -; nDEVSEL ; RD[0] ; 13.908 ; ; ; 13.908 ; -; nDEVSEL ; RD[1] ; 13.908 ; ; ; 13.908 ; -; nDEVSEL ; RD[2] ; 13.908 ; ; ; 13.908 ; -; nDEVSEL ; RD[3] ; 13.908 ; ; ; 13.908 ; -; nDEVSEL ; RD[4] ; 13.908 ; ; ; 13.908 ; -; nDEVSEL ; RD[5] ; 13.908 ; ; ; 13.908 ; -; nDEVSEL ; RD[6] ; 13.954 ; ; ; 13.954 ; -; nDEVSEL ; RD[7] ; 13.954 ; ; ; 13.954 ; -; nDEVSEL ; RDdir ; 15.512 ; ; ; 15.512 ; -; nIOSEL ; RD[0] ; 13.721 ; ; ; 13.721 ; -; nIOSEL ; RD[1] ; 13.721 ; ; ; 13.721 ; -; nIOSEL ; RD[2] ; 13.721 ; ; ; 13.721 ; -; nIOSEL ; RD[3] ; 13.721 ; ; ; 13.721 ; -; nIOSEL ; RD[4] ; 13.721 ; ; ; 13.721 ; -; nIOSEL ; RD[5] ; 13.721 ; ; ; 13.721 ; -; nIOSEL ; RD[6] ; 13.767 ; ; ; 13.767 ; -; nIOSEL ; RD[7] ; 13.767 ; ; ; 13.767 ; -; nIOSEL ; RDdir ; 15.325 ; ; ; 15.325 ; -; nIOSTRB ; RD[0] ; 13.574 ; ; ; 13.574 ; -; nIOSTRB ; RD[1] ; 13.574 ; ; ; 13.574 ; -; nIOSTRB ; RD[2] ; 13.574 ; ; ; 13.574 ; -; nIOSTRB ; RD[3] ; 13.574 ; ; ; 13.574 ; -; nIOSTRB ; RD[4] ; 13.574 ; ; ; 13.574 ; -; nIOSTRB ; RD[5] ; 13.574 ; ; ; 13.574 ; -; nIOSTRB ; RD[6] ; 13.620 ; ; ; 13.620 ; -; nIOSTRB ; RD[7] ; 13.620 ; ; ; 13.620 ; -; nIOSTRB ; RDdir ; 15.178 ; ; ; 15.178 ; -; nWE ; RD[0] ; 10.209 ; ; ; 10.209 ; -; nWE ; RD[1] ; 10.209 ; ; ; 10.209 ; -; nWE ; RD[2] ; 10.209 ; ; ; 10.209 ; -; nWE ; RD[3] ; 10.209 ; ; ; 10.209 ; -; nWE ; RD[4] ; 10.209 ; ; ; 10.209 ; -; nWE ; RD[5] ; 10.209 ; ; ; 10.209 ; -; nWE ; RD[6] ; 10.255 ; ; ; 10.255 ; -; nWE ; RD[7] ; 10.255 ; ; ; 10.255 ; -; nWE ; RDdir ; 11.813 ; ; ; 11.813 ; +; DMAin ; DMAout ; 8.665 ; ; ; 8.665 ; +; INTin ; INTout ; 8.862 ; ; ; 8.862 ; +; RA[0] ; RD[0] ; 13.610 ; ; ; 13.610 ; +; RA[0] ; RD[1] ; 13.610 ; ; ; 13.610 ; +; RA[0] ; RD[2] ; 13.610 ; ; ; 13.610 ; +; RA[0] ; RD[3] ; 13.610 ; ; ; 13.610 ; +; RA[0] ; RD[4] ; 13.610 ; ; ; 13.610 ; +; RA[0] ; RD[5] ; 13.610 ; ; ; 13.610 ; +; RA[0] ; RD[6] ; 13.565 ; ; ; 13.565 ; +; RA[0] ; RD[7] ; 13.565 ; ; ; 13.565 ; +; RA[0] ; RDdir ; 23.870 ; ; ; 23.870 ; +; RA[1] ; RD[0] ; 12.760 ; ; ; 12.760 ; +; RA[1] ; RD[1] ; 12.760 ; ; ; 12.760 ; +; RA[1] ; RD[2] ; 12.760 ; ; ; 12.760 ; +; RA[1] ; RD[3] ; 12.760 ; ; ; 12.760 ; +; RA[1] ; RD[4] ; 12.760 ; ; ; 12.760 ; +; RA[1] ; RD[5] ; 12.760 ; ; ; 12.760 ; +; RA[1] ; RD[6] ; 12.715 ; ; ; 12.715 ; +; RA[1] ; RD[7] ; 12.715 ; ; ; 12.715 ; +; RA[1] ; RDdir ; 23.020 ; ; ; 23.020 ; +; RA[2] ; RD[0] ; 13.252 ; ; ; 13.252 ; +; RA[2] ; RD[1] ; 13.252 ; ; ; 13.252 ; +; RA[2] ; RD[2] ; 13.252 ; ; ; 13.252 ; +; RA[2] ; RD[3] ; 13.252 ; ; ; 13.252 ; +; RA[2] ; RD[4] ; 13.252 ; ; ; 13.252 ; +; RA[2] ; RD[5] ; 13.252 ; ; ; 13.252 ; +; RA[2] ; RD[6] ; 13.207 ; ; ; 13.207 ; +; RA[2] ; RD[7] ; 13.207 ; ; ; 13.207 ; +; RA[2] ; RDdir ; 23.512 ; ; ; 23.512 ; +; RA[3] ; RD[0] ; 13.532 ; ; ; 13.532 ; +; RA[3] ; RD[1] ; 13.532 ; ; ; 13.532 ; +; RA[3] ; RD[2] ; 13.532 ; ; ; 13.532 ; +; RA[3] ; RD[3] ; 13.532 ; ; ; 13.532 ; +; RA[3] ; RD[4] ; 13.532 ; ; ; 13.532 ; +; RA[3] ; RD[5] ; 13.532 ; ; ; 13.532 ; +; RA[3] ; RD[6] ; 13.487 ; ; ; 13.487 ; +; RA[3] ; RD[7] ; 13.487 ; ; ; 13.487 ; +; RA[3] ; RDdir ; 23.792 ; ; ; 23.792 ; +; RA[4] ; RD[0] ; 13.442 ; ; ; 13.442 ; +; RA[4] ; RD[1] ; 13.442 ; ; ; 13.442 ; +; RA[4] ; RD[2] ; 13.442 ; ; ; 13.442 ; +; RA[4] ; RD[3] ; 13.442 ; ; ; 13.442 ; +; RA[4] ; RD[4] ; 13.442 ; ; ; 13.442 ; +; RA[4] ; RD[5] ; 13.442 ; ; ; 13.442 ; +; RA[4] ; RD[6] ; 13.397 ; ; ; 13.397 ; +; RA[4] ; RD[7] ; 13.397 ; ; ; 13.397 ; +; RA[4] ; RDdir ; 23.702 ; ; ; 23.702 ; +; RA[5] ; RD[0] ; 13.393 ; ; ; 13.393 ; +; RA[5] ; RD[1] ; 13.393 ; ; ; 13.393 ; +; RA[5] ; RD[2] ; 13.393 ; ; ; 13.393 ; +; RA[5] ; RD[3] ; 13.393 ; ; ; 13.393 ; +; RA[5] ; RD[4] ; 13.393 ; ; ; 13.393 ; +; RA[5] ; RD[5] ; 13.393 ; ; ; 13.393 ; +; RA[5] ; RD[6] ; 13.348 ; ; ; 13.348 ; +; RA[5] ; RD[7] ; 13.348 ; ; ; 13.348 ; +; RA[5] ; RDdir ; 23.653 ; ; ; 23.653 ; +; RA[6] ; RD[0] ; 13.690 ; ; ; 13.690 ; +; RA[6] ; RD[1] ; 13.690 ; ; ; 13.690 ; +; RA[6] ; RD[2] ; 13.690 ; ; ; 13.690 ; +; RA[6] ; RD[3] ; 13.690 ; ; ; 13.690 ; +; RA[6] ; RD[4] ; 13.690 ; ; ; 13.690 ; +; RA[6] ; RD[5] ; 13.690 ; ; ; 13.690 ; +; RA[6] ; RD[6] ; 13.645 ; ; ; 13.645 ; +; RA[6] ; RD[7] ; 13.645 ; ; ; 13.645 ; +; RA[6] ; RDdir ; 23.950 ; ; ; 23.950 ; +; RA[7] ; RD[0] ; 12.122 ; ; ; 12.122 ; +; RA[7] ; RD[1] ; 12.122 ; ; ; 12.122 ; +; RA[7] ; RD[2] ; 12.122 ; ; ; 12.122 ; +; RA[7] ; RD[3] ; 12.122 ; ; ; 12.122 ; +; RA[7] ; RD[4] ; 12.122 ; ; ; 12.122 ; +; RA[7] ; RD[5] ; 12.122 ; ; ; 12.122 ; +; RA[7] ; RD[6] ; 12.077 ; ; ; 12.077 ; +; RA[7] ; RD[7] ; 12.077 ; ; ; 12.077 ; +; RA[7] ; RDdir ; 22.382 ; ; ; 22.382 ; +; RA[8] ; RD[0] ; 11.505 ; ; ; 11.505 ; +; RA[8] ; RD[1] ; 11.505 ; ; ; 11.505 ; +; RA[8] ; RD[2] ; 11.505 ; ; ; 11.505 ; +; RA[8] ; RD[3] ; 11.505 ; ; ; 11.505 ; +; RA[8] ; RD[4] ; 11.505 ; ; ; 11.505 ; +; RA[8] ; RD[5] ; 11.505 ; ; ; 11.505 ; +; RA[8] ; RD[6] ; 11.460 ; ; ; 11.460 ; +; RA[8] ; RD[7] ; 11.460 ; ; ; 11.460 ; +; RA[8] ; RDdir ; 21.765 ; ; ; 21.765 ; +; RA[9] ; RD[0] ; 11.899 ; ; ; 11.899 ; +; RA[9] ; RD[1] ; 11.899 ; ; ; 11.899 ; +; RA[9] ; RD[2] ; 11.899 ; ; ; 11.899 ; +; RA[9] ; RD[3] ; 11.899 ; ; ; 11.899 ; +; RA[9] ; RD[4] ; 11.899 ; ; ; 11.899 ; +; RA[9] ; RD[5] ; 11.899 ; ; ; 11.899 ; +; RA[9] ; RD[6] ; 11.854 ; ; ; 11.854 ; +; RA[9] ; RD[7] ; 11.854 ; ; ; 11.854 ; +; RA[9] ; RDdir ; 22.159 ; ; ; 22.159 ; +; RA[10] ; RD[0] ; 13.038 ; ; ; 13.038 ; +; RA[10] ; RD[1] ; 13.038 ; ; ; 13.038 ; +; RA[10] ; RD[2] ; 13.038 ; ; ; 13.038 ; +; RA[10] ; RD[3] ; 13.038 ; ; ; 13.038 ; +; RA[10] ; RD[4] ; 13.038 ; ; ; 13.038 ; +; RA[10] ; RD[5] ; 13.038 ; ; ; 13.038 ; +; RA[10] ; RD[6] ; 12.993 ; ; ; 12.993 ; +; RA[10] ; RD[7] ; 12.993 ; ; ; 12.993 ; +; RA[10] ; RDdir ; 23.298 ; ; ; 23.298 ; +; nDEVSEL ; RD[0] ; 11.136 ; ; ; 11.136 ; +; nDEVSEL ; RD[1] ; 11.136 ; ; ; 11.136 ; +; nDEVSEL ; RD[2] ; 11.136 ; ; ; 11.136 ; +; nDEVSEL ; RD[3] ; 11.136 ; ; ; 11.136 ; +; nDEVSEL ; RD[4] ; 11.136 ; ; ; 11.136 ; +; nDEVSEL ; RD[5] ; 11.136 ; ; ; 11.136 ; +; nDEVSEL ; RD[6] ; 11.091 ; ; ; 11.091 ; +; nDEVSEL ; RD[7] ; 11.091 ; ; ; 11.091 ; +; nDEVSEL ; RDdir ; 21.396 ; ; ; 21.396 ; +; nIOSEL ; RD[0] ; 11.071 ; ; ; 11.071 ; +; nIOSEL ; RD[1] ; 11.071 ; ; ; 11.071 ; +; nIOSEL ; RD[2] ; 11.071 ; ; ; 11.071 ; +; nIOSEL ; RD[3] ; 11.071 ; ; ; 11.071 ; +; nIOSEL ; RD[4] ; 11.071 ; ; ; 11.071 ; +; nIOSEL ; RD[5] ; 11.071 ; ; ; 11.071 ; +; nIOSEL ; RD[6] ; 11.026 ; ; ; 11.026 ; +; nIOSEL ; RD[7] ; 11.026 ; ; ; 11.026 ; +; nIOSEL ; RDdir ; 21.331 ; ; ; 21.331 ; +; nIOSTRB ; RD[0] ; 12.415 ; ; ; 12.415 ; +; nIOSTRB ; RD[1] ; 12.415 ; ; ; 12.415 ; +; nIOSTRB ; RD[2] ; 12.415 ; ; ; 12.415 ; +; nIOSTRB ; RD[3] ; 12.415 ; ; ; 12.415 ; +; nIOSTRB ; RD[4] ; 12.415 ; ; ; 12.415 ; +; nIOSTRB ; RD[5] ; 12.415 ; ; ; 12.415 ; +; nIOSTRB ; RD[6] ; 12.370 ; ; ; 12.370 ; +; nIOSTRB ; RD[7] ; 12.370 ; ; ; 12.370 ; +; nIOSTRB ; RDdir ; 22.675 ; ; ; 22.675 ; +; nWE ; RD[0] ; 13.158 ; ; ; 13.158 ; +; nWE ; RD[1] ; 13.158 ; ; ; 13.158 ; +; nWE ; RD[2] ; 13.158 ; ; ; 13.158 ; +; nWE ; RD[3] ; 13.158 ; ; ; 13.158 ; +; nWE ; RD[4] ; 13.158 ; ; ; 13.158 ; +; nWE ; RD[5] ; 13.158 ; ; ; 13.158 ; +; nWE ; RD[6] ; 13.113 ; ; ; 13.113 ; +; nWE ; RD[7] ; 13.113 ; ; ; 13.113 ; +; nWE ; RDdir ; 23.418 ; ; ; 23.418 ; +------------+-------------+--------+----+----+--------+ @@ -954,93 +1148,93 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-----------+------------+--------+------+------------+-----------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+--------+------+------------+-----------------+ -; FCK ; C25M ; 7.909 ; ; Rise ; C25M ; -; MOSI ; C25M ; 8.455 ; ; Rise ; C25M ; -; RD[*] ; C25M ; 12.243 ; ; Rise ; C25M ; -; RD[0] ; C25M ; 12.243 ; ; Rise ; C25M ; -; RD[1] ; C25M ; 12.243 ; ; Rise ; C25M ; -; RD[2] ; C25M ; 12.243 ; ; Rise ; C25M ; -; RD[3] ; C25M ; 12.243 ; ; Rise ; C25M ; -; RD[4] ; C25M ; 12.243 ; ; Rise ; C25M ; -; RD[5] ; C25M ; 12.243 ; ; Rise ; C25M ; -; RD[6] ; C25M ; 12.289 ; ; Rise ; C25M ; -; RD[7] ; C25M ; 12.289 ; ; Rise ; C25M ; -; SD[*] ; C25M ; 7.014 ; ; Rise ; C25M ; -; SD[0] ; C25M ; 7.446 ; ; Rise ; C25M ; -; SD[1] ; C25M ; 7.446 ; ; Rise ; C25M ; -; SD[2] ; C25M ; 7.014 ; ; Rise ; C25M ; -; SD[3] ; C25M ; 7.014 ; ; Rise ; C25M ; -; SD[4] ; C25M ; 7.446 ; ; Rise ; C25M ; -; SD[5] ; C25M ; 7.014 ; ; Rise ; C25M ; -; SD[6] ; C25M ; 7.014 ; ; Rise ; C25M ; -; SD[7] ; C25M ; 7.014 ; ; Rise ; C25M ; -; nFCS ; C25M ; 7.116 ; ; Rise ; C25M ; -; RD[*] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; -; RD[0] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; -; RD[1] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; -; RD[2] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; -; RD[3] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; -; RD[4] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; -; RD[5] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; -; RD[6] ; PHI0 ; 9.796 ; ; Rise ; PHI0 ; -; RD[7] ; PHI0 ; 9.796 ; ; Rise ; PHI0 ; -; RD[*] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; -; RD[0] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; -; RD[1] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; -; RD[2] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; -; RD[3] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; -; RD[4] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; -; RD[5] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; -; RD[6] ; PHI0 ; 9.796 ; ; Fall ; PHI0 ; -; RD[7] ; PHI0 ; 9.796 ; ; Fall ; PHI0 ; +; FCK ; C25M ; 15.951 ; ; Rise ; C25M ; +; MOSI ; C25M ; 15.242 ; ; Rise ; C25M ; +; RD[*] ; C25M ; 13.690 ; ; Rise ; C25M ; +; RD[0] ; C25M ; 13.735 ; ; Rise ; C25M ; +; RD[1] ; C25M ; 13.735 ; ; Rise ; C25M ; +; RD[2] ; C25M ; 13.735 ; ; Rise ; C25M ; +; RD[3] ; C25M ; 13.735 ; ; Rise ; C25M ; +; RD[4] ; C25M ; 13.735 ; ; Rise ; C25M ; +; RD[5] ; C25M ; 13.735 ; ; Rise ; C25M ; +; RD[6] ; C25M ; 13.690 ; ; Rise ; C25M ; +; RD[7] ; C25M ; 13.690 ; ; Rise ; C25M ; +; SD[*] ; C25M ; 13.373 ; ; Rise ; C25M ; +; SD[0] ; C25M ; 13.829 ; ; Rise ; C25M ; +; SD[1] ; C25M ; 13.829 ; ; Rise ; C25M ; +; SD[2] ; C25M ; 13.373 ; ; Rise ; C25M ; +; SD[3] ; C25M ; 13.373 ; ; Rise ; C25M ; +; SD[4] ; C25M ; 13.829 ; ; Rise ; C25M ; +; SD[5] ; C25M ; 13.373 ; ; Rise ; C25M ; +; SD[6] ; C25M ; 13.373 ; ; Rise ; C25M ; +; SD[7] ; C25M ; 13.373 ; ; Rise ; C25M ; +; nFCS ; C25M ; 15.969 ; ; Rise ; C25M ; +; RD[*] ; PHI0 ; 11.630 ; ; Rise ; PHI0 ; +; RD[0] ; PHI0 ; 11.675 ; ; Rise ; PHI0 ; +; RD[1] ; PHI0 ; 11.675 ; ; Rise ; PHI0 ; +; RD[2] ; PHI0 ; 11.675 ; ; Rise ; PHI0 ; +; RD[3] ; PHI0 ; 11.675 ; ; Rise ; PHI0 ; +; RD[4] ; PHI0 ; 11.675 ; ; Rise ; PHI0 ; +; RD[5] ; PHI0 ; 11.675 ; ; Rise ; PHI0 ; +; RD[6] ; PHI0 ; 11.630 ; ; Rise ; PHI0 ; +; RD[7] ; PHI0 ; 11.630 ; ; Rise ; PHI0 ; +; RD[*] ; PHI0 ; 11.630 ; ; Fall ; PHI0 ; +; RD[0] ; PHI0 ; 11.675 ; ; Fall ; PHI0 ; +; RD[1] ; PHI0 ; 11.675 ; ; Fall ; PHI0 ; +; RD[2] ; PHI0 ; 11.675 ; ; Fall ; PHI0 ; +; RD[3] ; PHI0 ; 11.675 ; ; Fall ; PHI0 ; +; RD[4] ; PHI0 ; 11.675 ; ; Fall ; PHI0 ; +; RD[5] ; PHI0 ; 11.675 ; ; Fall ; PHI0 ; +; RD[6] ; PHI0 ; 11.630 ; ; Fall ; PHI0 ; +; RD[7] ; PHI0 ; 11.630 ; ; Fall ; PHI0 ; +-----------+------------+--------+------+------------+-----------------+ -+----------------------------------------------------------------------+ -; Minimum Output Enable Times ; -+-----------+------------+-------+------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-----------+------------+-------+------+------------+-----------------+ -; FCK ; C25M ; 7.909 ; ; Rise ; C25M ; -; MOSI ; C25M ; 8.455 ; ; Rise ; C25M ; -; RD[*] ; C25M ; 9.405 ; ; Rise ; C25M ; -; RD[0] ; C25M ; 9.405 ; ; Rise ; C25M ; -; RD[1] ; C25M ; 9.405 ; ; Rise ; C25M ; -; RD[2] ; C25M ; 9.405 ; ; Rise ; C25M ; -; RD[3] ; C25M ; 9.405 ; ; Rise ; C25M ; -; RD[4] ; C25M ; 9.405 ; ; Rise ; C25M ; -; RD[5] ; C25M ; 9.405 ; ; Rise ; C25M ; -; RD[6] ; C25M ; 9.451 ; ; Rise ; C25M ; -; RD[7] ; C25M ; 9.451 ; ; Rise ; C25M ; -; SD[*] ; C25M ; 7.014 ; ; Rise ; C25M ; -; SD[0] ; C25M ; 7.446 ; ; Rise ; C25M ; -; SD[1] ; C25M ; 7.446 ; ; Rise ; C25M ; -; SD[2] ; C25M ; 7.014 ; ; Rise ; C25M ; -; SD[3] ; C25M ; 7.014 ; ; Rise ; C25M ; -; SD[4] ; C25M ; 7.446 ; ; Rise ; C25M ; -; SD[5] ; C25M ; 7.014 ; ; Rise ; C25M ; -; SD[6] ; C25M ; 7.014 ; ; Rise ; C25M ; -; SD[7] ; C25M ; 7.014 ; ; Rise ; C25M ; -; nFCS ; C25M ; 7.116 ; ; Rise ; C25M ; -; RD[*] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; -; RD[0] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; -; RD[1] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; -; RD[2] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; -; RD[3] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; -; RD[4] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; -; RD[5] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; -; RD[6] ; PHI0 ; 9.796 ; ; Rise ; PHI0 ; -; RD[7] ; PHI0 ; 9.796 ; ; Rise ; PHI0 ; -; RD[*] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; -; RD[0] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; -; RD[1] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; -; RD[2] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; -; RD[3] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; -; RD[4] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; -; RD[5] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; -; RD[6] ; PHI0 ; 9.796 ; ; Fall ; PHI0 ; -; RD[7] ; PHI0 ; 9.796 ; ; Fall ; PHI0 ; -+-----------+------------+-------+------+------------+-----------------+ ++-----------------------------------------------------------------------+ +; Minimum Output Enable Times ; ++-----------+------------+--------+------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+--------+------+------------+-----------------+ +; FCK ; C25M ; 15.951 ; ; Rise ; C25M ; +; MOSI ; C25M ; 15.242 ; ; Rise ; C25M ; +; RD[*] ; C25M ; 10.182 ; ; Rise ; C25M ; +; RD[0] ; C25M ; 10.227 ; ; Rise ; C25M ; +; RD[1] ; C25M ; 10.227 ; ; Rise ; C25M ; +; RD[2] ; C25M ; 10.227 ; ; Rise ; C25M ; +; RD[3] ; C25M ; 10.227 ; ; Rise ; C25M ; +; RD[4] ; C25M ; 10.227 ; ; Rise ; C25M ; +; RD[5] ; C25M ; 10.227 ; ; Rise ; C25M ; +; RD[6] ; C25M ; 10.182 ; ; Rise ; C25M ; +; RD[7] ; C25M ; 10.182 ; ; Rise ; C25M ; +; SD[*] ; C25M ; 13.373 ; ; Rise ; C25M ; +; SD[0] ; C25M ; 13.829 ; ; Rise ; C25M ; +; SD[1] ; C25M ; 13.829 ; ; Rise ; C25M ; +; SD[2] ; C25M ; 13.373 ; ; Rise ; C25M ; +; SD[3] ; C25M ; 13.373 ; ; Rise ; C25M ; +; SD[4] ; C25M ; 13.829 ; ; Rise ; C25M ; +; SD[5] ; C25M ; 13.373 ; ; Rise ; C25M ; +; SD[6] ; C25M ; 13.373 ; ; Rise ; C25M ; +; SD[7] ; C25M ; 13.373 ; ; Rise ; C25M ; +; nFCS ; C25M ; 15.969 ; ; Rise ; C25M ; +; RD[*] ; PHI0 ; 11.630 ; ; Rise ; PHI0 ; +; RD[0] ; PHI0 ; 11.675 ; ; Rise ; PHI0 ; +; RD[1] ; PHI0 ; 11.675 ; ; Rise ; PHI0 ; +; RD[2] ; PHI0 ; 11.675 ; ; Rise ; PHI0 ; +; RD[3] ; PHI0 ; 11.675 ; ; Rise ; PHI0 ; +; RD[4] ; PHI0 ; 11.675 ; ; Rise ; PHI0 ; +; RD[5] ; PHI0 ; 11.675 ; ; Rise ; PHI0 ; +; RD[6] ; PHI0 ; 11.630 ; ; Rise ; PHI0 ; +; RD[7] ; PHI0 ; 11.630 ; ; Rise ; PHI0 ; +; RD[*] ; PHI0 ; 11.630 ; ; Fall ; PHI0 ; +; RD[0] ; PHI0 ; 11.675 ; ; Fall ; PHI0 ; +; RD[1] ; PHI0 ; 11.675 ; ; Fall ; PHI0 ; +; RD[2] ; PHI0 ; 11.675 ; ; Fall ; PHI0 ; +; RD[3] ; PHI0 ; 11.675 ; ; Fall ; PHI0 ; +; RD[4] ; PHI0 ; 11.675 ; ; Fall ; PHI0 ; +; RD[5] ; PHI0 ; 11.675 ; ; Fall ; PHI0 ; +; RD[6] ; PHI0 ; 11.630 ; ; Fall ; PHI0 ; +; RD[7] ; PHI0 ; 11.630 ; ; Fall ; PHI0 ; ++-----------+------------+--------+------+------------+-----------------+ +-------------------------------------------------------------------------------+ @@ -1048,45 +1242,45 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-----------+------------+-----------+-----------+------------+-----------------+ ; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; +-----------+------------+-----------+-----------+------------+-----------------+ -; FCK ; C25M ; 7.909 ; ; Rise ; C25M ; -; MOSI ; C25M ; 8.455 ; ; Rise ; C25M ; -; RD[*] ; C25M ; 12.243 ; ; Rise ; C25M ; -; RD[0] ; C25M ; 12.243 ; ; Rise ; C25M ; -; RD[1] ; C25M ; 12.243 ; ; Rise ; C25M ; -; RD[2] ; C25M ; 12.243 ; ; Rise ; C25M ; -; RD[3] ; C25M ; 12.243 ; ; Rise ; C25M ; -; RD[4] ; C25M ; 12.243 ; ; Rise ; C25M ; -; RD[5] ; C25M ; 12.243 ; ; Rise ; C25M ; -; RD[6] ; C25M ; 12.289 ; ; Rise ; C25M ; -; RD[7] ; C25M ; 12.289 ; ; Rise ; C25M ; -; SD[*] ; C25M ; 7.014 ; ; Rise ; C25M ; -; SD[0] ; C25M ; 7.446 ; ; Rise ; C25M ; -; SD[1] ; C25M ; 7.446 ; ; Rise ; C25M ; -; SD[2] ; C25M ; 7.014 ; ; Rise ; C25M ; -; SD[3] ; C25M ; 7.014 ; ; Rise ; C25M ; -; SD[4] ; C25M ; 7.446 ; ; Rise ; C25M ; -; SD[5] ; C25M ; 7.014 ; ; Rise ; C25M ; -; SD[6] ; C25M ; 7.014 ; ; Rise ; C25M ; -; SD[7] ; C25M ; 7.014 ; ; Rise ; C25M ; -; nFCS ; C25M ; 7.116 ; ; Rise ; C25M ; -; RD[*] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; -; RD[0] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; -; RD[1] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; -; RD[2] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; -; RD[3] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; -; RD[4] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; -; RD[5] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; -; RD[6] ; PHI0 ; 9.796 ; ; Rise ; PHI0 ; -; RD[7] ; PHI0 ; 9.796 ; ; Rise ; PHI0 ; -; RD[*] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; -; RD[0] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; -; RD[1] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; -; RD[2] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; -; RD[3] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; -; RD[4] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; -; RD[5] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; -; RD[6] ; PHI0 ; 9.796 ; ; Fall ; PHI0 ; -; RD[7] ; PHI0 ; 9.796 ; ; Fall ; PHI0 ; +; FCK ; C25M ; 15.951 ; ; Rise ; C25M ; +; MOSI ; C25M ; 15.242 ; ; Rise ; C25M ; +; RD[*] ; C25M ; 13.690 ; ; Rise ; C25M ; +; RD[0] ; C25M ; 13.735 ; ; Rise ; C25M ; +; RD[1] ; C25M ; 13.735 ; ; Rise ; C25M ; +; RD[2] ; C25M ; 13.735 ; ; Rise ; C25M ; +; RD[3] ; C25M ; 13.735 ; ; Rise ; C25M ; +; RD[4] ; C25M ; 13.735 ; ; Rise ; C25M ; +; RD[5] ; C25M ; 13.735 ; ; Rise ; C25M ; +; RD[6] ; C25M ; 13.690 ; ; Rise ; C25M ; +; RD[7] ; C25M ; 13.690 ; ; Rise ; C25M ; +; SD[*] ; C25M ; 13.373 ; ; Rise ; C25M ; +; SD[0] ; C25M ; 13.829 ; ; Rise ; C25M ; +; SD[1] ; C25M ; 13.829 ; ; Rise ; C25M ; +; SD[2] ; C25M ; 13.373 ; ; Rise ; C25M ; +; SD[3] ; C25M ; 13.373 ; ; Rise ; C25M ; +; SD[4] ; C25M ; 13.829 ; ; Rise ; C25M ; +; SD[5] ; C25M ; 13.373 ; ; Rise ; C25M ; +; SD[6] ; C25M ; 13.373 ; ; Rise ; C25M ; +; SD[7] ; C25M ; 13.373 ; ; Rise ; C25M ; +; nFCS ; C25M ; 15.969 ; ; Rise ; C25M ; +; RD[*] ; PHI0 ; 11.630 ; ; Rise ; PHI0 ; +; RD[0] ; PHI0 ; 11.675 ; ; Rise ; PHI0 ; +; RD[1] ; PHI0 ; 11.675 ; ; Rise ; PHI0 ; +; RD[2] ; PHI0 ; 11.675 ; ; Rise ; PHI0 ; +; RD[3] ; PHI0 ; 11.675 ; ; Rise ; PHI0 ; +; RD[4] ; PHI0 ; 11.675 ; ; Rise ; PHI0 ; +; RD[5] ; PHI0 ; 11.675 ; ; Rise ; PHI0 ; +; RD[6] ; PHI0 ; 11.630 ; ; Rise ; PHI0 ; +; RD[7] ; PHI0 ; 11.630 ; ; Rise ; PHI0 ; +; RD[*] ; PHI0 ; 11.630 ; ; Fall ; PHI0 ; +; RD[0] ; PHI0 ; 11.675 ; ; Fall ; PHI0 ; +; RD[1] ; PHI0 ; 11.675 ; ; Fall ; PHI0 ; +; RD[2] ; PHI0 ; 11.675 ; ; Fall ; PHI0 ; +; RD[3] ; PHI0 ; 11.675 ; ; Fall ; PHI0 ; +; RD[4] ; PHI0 ; 11.675 ; ; Fall ; PHI0 ; +; RD[5] ; PHI0 ; 11.675 ; ; Fall ; PHI0 ; +; RD[6] ; PHI0 ; 11.630 ; ; Fall ; PHI0 ; +; RD[7] ; PHI0 ; 11.630 ; ; Fall ; PHI0 ; +-----------+------------+-----------+-----------+------------+-----------------+ @@ -1095,69 +1289,67 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-----------+------------+-----------+-----------+------------+-----------------+ ; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; +-----------+------------+-----------+-----------+------------+-----------------+ -; FCK ; C25M ; 7.909 ; ; Rise ; C25M ; -; MOSI ; C25M ; 8.455 ; ; Rise ; C25M ; -; RD[*] ; C25M ; 9.405 ; ; Rise ; C25M ; -; RD[0] ; C25M ; 9.405 ; ; Rise ; C25M ; -; RD[1] ; C25M ; 9.405 ; ; Rise ; C25M ; -; RD[2] ; C25M ; 9.405 ; ; Rise ; C25M ; -; RD[3] ; C25M ; 9.405 ; ; Rise ; C25M ; -; RD[4] ; C25M ; 9.405 ; ; Rise ; C25M ; -; RD[5] ; C25M ; 9.405 ; ; Rise ; C25M ; -; RD[6] ; C25M ; 9.451 ; ; Rise ; C25M ; -; RD[7] ; C25M ; 9.451 ; ; Rise ; C25M ; -; SD[*] ; C25M ; 7.014 ; ; Rise ; C25M ; -; SD[0] ; C25M ; 7.446 ; ; Rise ; C25M ; -; SD[1] ; C25M ; 7.446 ; ; Rise ; C25M ; -; SD[2] ; C25M ; 7.014 ; ; Rise ; C25M ; -; SD[3] ; C25M ; 7.014 ; ; Rise ; C25M ; -; SD[4] ; C25M ; 7.446 ; ; Rise ; C25M ; -; SD[5] ; C25M ; 7.014 ; ; Rise ; C25M ; -; SD[6] ; C25M ; 7.014 ; ; Rise ; C25M ; -; SD[7] ; C25M ; 7.014 ; ; Rise ; C25M ; -; nFCS ; C25M ; 7.116 ; ; Rise ; C25M ; -; RD[*] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; -; RD[0] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; -; RD[1] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; -; RD[2] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; -; RD[3] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; -; RD[4] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; -; RD[5] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; -; RD[6] ; PHI0 ; 9.796 ; ; Rise ; PHI0 ; -; RD[7] ; PHI0 ; 9.796 ; ; Rise ; PHI0 ; -; RD[*] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; -; RD[0] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; -; RD[1] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; -; RD[2] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; -; RD[3] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; -; RD[4] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; -; RD[5] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; -; RD[6] ; PHI0 ; 9.796 ; ; Fall ; PHI0 ; -; RD[7] ; PHI0 ; 9.796 ; ; Fall ; PHI0 ; +; FCK ; C25M ; 15.951 ; ; Rise ; C25M ; +; MOSI ; C25M ; 15.242 ; ; Rise ; C25M ; +; RD[*] ; C25M ; 10.182 ; ; Rise ; C25M ; +; RD[0] ; C25M ; 10.227 ; ; Rise ; C25M ; +; RD[1] ; C25M ; 10.227 ; ; Rise ; C25M ; +; RD[2] ; C25M ; 10.227 ; ; Rise ; C25M ; +; RD[3] ; C25M ; 10.227 ; ; Rise ; C25M ; +; RD[4] ; C25M ; 10.227 ; ; Rise ; C25M ; +; RD[5] ; C25M ; 10.227 ; ; Rise ; C25M ; +; RD[6] ; C25M ; 10.182 ; ; Rise ; C25M ; +; RD[7] ; C25M ; 10.182 ; ; Rise ; C25M ; +; SD[*] ; C25M ; 13.373 ; ; Rise ; C25M ; +; SD[0] ; C25M ; 13.829 ; ; Rise ; C25M ; +; SD[1] ; C25M ; 13.829 ; ; Rise ; C25M ; +; SD[2] ; C25M ; 13.373 ; ; Rise ; C25M ; +; SD[3] ; C25M ; 13.373 ; ; Rise ; C25M ; +; SD[4] ; C25M ; 13.829 ; ; Rise ; C25M ; +; SD[5] ; C25M ; 13.373 ; ; Rise ; C25M ; +; SD[6] ; C25M ; 13.373 ; ; Rise ; C25M ; +; SD[7] ; C25M ; 13.373 ; ; Rise ; C25M ; +; nFCS ; C25M ; 15.969 ; ; Rise ; C25M ; +; RD[*] ; PHI0 ; 11.630 ; ; Rise ; PHI0 ; +; RD[0] ; PHI0 ; 11.675 ; ; Rise ; PHI0 ; +; RD[1] ; PHI0 ; 11.675 ; ; Rise ; PHI0 ; +; RD[2] ; PHI0 ; 11.675 ; ; Rise ; PHI0 ; +; RD[3] ; PHI0 ; 11.675 ; ; Rise ; PHI0 ; +; RD[4] ; PHI0 ; 11.675 ; ; Rise ; PHI0 ; +; RD[5] ; PHI0 ; 11.675 ; ; Rise ; PHI0 ; +; RD[6] ; PHI0 ; 11.630 ; ; Rise ; PHI0 ; +; RD[7] ; PHI0 ; 11.630 ; ; Rise ; PHI0 ; +; RD[*] ; PHI0 ; 11.630 ; ; Fall ; PHI0 ; +; RD[0] ; PHI0 ; 11.675 ; ; Fall ; PHI0 ; +; RD[1] ; PHI0 ; 11.675 ; ; Fall ; PHI0 ; +; RD[2] ; PHI0 ; 11.675 ; ; Fall ; PHI0 ; +; RD[3] ; PHI0 ; 11.675 ; ; Fall ; PHI0 ; +; RD[4] ; PHI0 ; 11.675 ; ; Fall ; PHI0 ; +; RD[5] ; PHI0 ; 11.675 ; ; Fall ; PHI0 ; +; RD[6] ; PHI0 ; 11.630 ; ; Fall ; PHI0 ; +; RD[7] ; PHI0 ; 11.630 ; ; Fall ; PHI0 ; +-----------+------------+-----------+-----------+------------+-----------------+ -+-------------------------------------------------------------------+ -; Setup Transfers ; -+------------+----------+----------+----------+----------+----------+ -; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; -+------------+----------+----------+----------+----------+----------+ -; C25M ; C25M ; 1374 ; 0 ; 0 ; 0 ; -; PHI0 ; C25M ; 82 ; 1 ; 0 ; 0 ; -; C25M ; PHI0 ; 5 ; 0 ; 0 ; 0 ; -+------------+----------+----------+----------+----------+----------+ ++-------------------------------------------------------------------------+ +; Setup Transfers ; ++------------+----------+------------+------------+------------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++------------+----------+------------+------------+------------+----------+ +; C25M ; C25M ; 1526 ; 0 ; 88 ; 0 ; +; PHI0 ; C25M ; false path ; false path ; false path ; 0 ; ++------------+----------+------------+------------+------------+----------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. -+-------------------------------------------------------------------+ -; Hold Transfers ; -+------------+----------+----------+----------+----------+----------+ -; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; -+------------+----------+----------+----------+----------+----------+ -; C25M ; C25M ; 1374 ; 0 ; 0 ; 0 ; -; PHI0 ; C25M ; 82 ; 1 ; 0 ; 0 ; -; C25M ; PHI0 ; 5 ; 0 ; 0 ; 0 ; -+------------+----------+----------+----------+----------+----------+ ++-------------------------------------------------------------------------+ +; Hold Transfers ; ++------------+----------+------------+------------+------------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++------------+----------+------------+------------+------------+----------+ +; C25M ; C25M ; 1526 ; 0 ; 88 ; 0 ; +; PHI0 ; C25M ; false path ; false path ; false path ; 0 ; ++------------+----------+------------+------------+------------+----------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. @@ -1201,9 +1393,9 @@ No dedicated SERDES Receiver circuitry present in device or used in design ; Illegal Clocks ; 0 ; 0 ; ; Unconstrained Clocks ; 0 ; 0 ; ; Unconstrained Input Ports ; 44 ; 44 ; -; Unconstrained Input Port Paths ; 645 ; 645 ; +; Unconstrained Input Port Paths ; 246 ; 246 ; ; Unconstrained Output Ports ; 45 ; 45 ; -; Unconstrained Output Port Paths ; 118 ; 118 ; +; Unconstrained Output Port Paths ; 217 ; 217 ; +---------------------------------+-------+------+ @@ -1213,7 +1405,7 @@ No dedicated SERDES Receiver circuitry present in device or used in design Info: ******************************************************************* Info: Running Quartus II 32-bit TimeQuest Timing Analyzer Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - Info: Processing started: Tue Apr 20 04:20:00 2021 + Info: Processing started: Wed Apr 21 20:02:02 2021 Info: Command: quartus_sta GR8RAM -c GR8RAM Info: qsta_default_script.tcl version: #1 Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected @@ -1221,43 +1413,36 @@ Info (21077): Low junction temperature is 0 degrees C Info (21077): High junction temperature is 85 degrees C Info (306004): Started post-fitting delay annotation Info (306005): Delay annotation completed successfully -Critical Warning (332012): Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. -Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" -Info (332105): Deriving Clocks - Info (332105): create_clock -period 1.000 -name C25M C25M - Info (332105): create_clock -period 1.000 -name PHI0 PHI0 +Info (332104): Reading SDC File: 'GR8RAM.sdc' Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON -Critical Warning (332148): Timing requirements not met -Info (332146): Worst-case setup slack is -9.005 +Info (332146): Worst-case setup slack is 12.419 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== - Info (332119): -9.005 -699.357 C25M - Info (332119): -0.425 -0.425 PHI0 -Info (332146): Worst-case hold slack is -0.248 + Info (332119): 12.419 0.000 C25M +Info (332146): Worst-case hold slack is 1.393 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== - Info (332119): -0.248 -0.248 PHI0 - Info (332119): 1.400 0.000 C25M -Info (332146): Worst-case recovery slack is -4.412 + Info (332119): 1.393 0.000 C25M +Info (332146): Worst-case recovery slack is 33.300 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== - Info (332119): -4.412 -127.948 C25M -Info (332146): Worst-case removal slack is 4.858 + Info (332119): 33.300 0.000 C25M +Info (332146): Worst-case removal slack is 6.146 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== - Info (332119): 4.858 0.000 C25M -Info (332146): Worst-case minimum pulse width slack is -2.289 + Info (332119): 6.146 0.000 C25M +Info (332146): Worst-case minimum pulse width slack is 19.734 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== - Info (332119): -2.289 -2.289 C25M - Info (332119): -2.289 -2.289 PHI0 + Info (332119): 19.734 0.000 C25M + Info (332119): 488.734 0.000 PHI0 Info (332001): The selected device family is not supported by the report_metastability command. Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements -Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings +Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 0 warnings Info: Peak virtual memory: 278 megabytes - Info: Processing ended: Tue Apr 20 04:20:05 2021 + Info: Processing ended: Wed Apr 21 20:02:07 2021 Info: Elapsed time: 00:00:05 - Info: Total CPU time (on all processors): 00:00:04 + Info: Total CPU time (on all processors): 00:00:05 diff --git a/cpld/output_files/GR8RAM.sta.summary b/cpld/output_files/GR8RAM.sta.summary index c650a04..d814531 100755 --- a/cpld/output_files/GR8RAM.sta.summary +++ b/cpld/output_files/GR8RAM.sta.summary @@ -3,35 +3,27 @@ TimeQuest Timing Analyzer Summary ------------------------------------------------------------ Type : Setup 'C25M' -Slack : -9.005 -TNS : -699.357 - -Type : Setup 'PHI0' -Slack : -0.425 -TNS : -0.425 - -Type : Hold 'PHI0' -Slack : -0.248 -TNS : -0.248 +Slack : 12.419 +TNS : 0.000 Type : Hold 'C25M' -Slack : 1.400 +Slack : 1.393 TNS : 0.000 Type : Recovery 'C25M' -Slack : -4.412 -TNS : -127.948 +Slack : 33.300 +TNS : 0.000 Type : Removal 'C25M' -Slack : 4.858 +Slack : 6.146 TNS : 0.000 Type : Minimum Pulse Width 'C25M' -Slack : -2.289 -TNS : -2.289 +Slack : 19.734 +TNS : 0.000 Type : Minimum Pulse Width 'PHI0' -Slack : -2.289 -TNS : -2.289 +Slack : 488.734 +TNS : 0.000 ------------------------------------------------------------