diff --git a/cpld/GR8RAM.qsf b/cpld/GR8RAM.qsf index 19d06a3..92bdf28 100755 --- a/cpld/GR8RAM.qsf +++ b/cpld/GR8RAM.qsf @@ -114,9 +114,9 @@ set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF set_global_assignment -name FITTER_EFFORT "STANDARD FIT" set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING "PACK ALL IO REGISTERS" set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF -set_global_assignment -name AUTO_LCELL_INSERTION ON -set_global_assignment -name AUTO_PARALLEL_EXPANDERS ON -set_global_assignment -name AUTO_RESOURCE_SHARING ON +set_global_assignment -name AUTO_LCELL_INSERTION OFF +set_global_assignment -name AUTO_PARALLEL_EXPANDERS OFF +set_global_assignment -name AUTO_RESOURCE_SHARING OFF set_global_assignment -name SYNTH_MESSAGE_LEVEL HIGH set_global_assignment -name SLOW_SLEW_RATE ON set_global_assignment -name ALM_REGISTER_PACKING_EFFORT HIGH @@ -141,18 +141,201 @@ set_location_assignment LC16 -to Addr[15] set_global_assignment -name PARALLEL_SYNTHESIS OFF set_global_assignment -name STATE_MACHINE_PROCESSING "USER-ENCODED" set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS OFF -set_location_assignment LC128 -to Addr[22] -set_location_assignment LC122 -to Addr[19] -set_location_assignment LC124 -to Addr[20] -set_location_assignment LC120 -to Addr[17] -set_location_assignment LC118 -to Addr[16] -set_location_assignment LC126 -to Addr[21] set_location_assignment PIN_76 -to A[1] set_location_assignment PIN_8 -to PHI0in set_location_assignment PIN_2 -to PHI1in -set_location_assignment LC127 -to PHI1b7_MC -set_location_assignment LC125 -to PHI1b6_MC -set_location_assignment LC123 -to PHI1b5_MC -set_location_assignment LC121 -to PHI1b4_MC set_location_assignment PIN_31 -to C7Mout -set_location_assignment PIN_30 -to PHI1out \ No newline at end of file +set_location_assignment PIN_30 -to PHI1out +set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES OFF +set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES OFF +set_global_assignment -name PRE_MAPPING_RESYNTHESIS ON +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to ASel +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to A[0] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to A[1] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to A[2] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to A[3] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to A[4] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to A[5] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to A[6] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to A[7] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to A[8] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to A[9] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to A[10] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to A[11] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to A[12] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to A[13] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to A[14] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to A[15] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Add0 +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Add1 +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Add2 +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Add3 +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Addr +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to AddrHWR_MC +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to AddrLWR_MC +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to AddrMWR_MC +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Addr[0] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Addr[1] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Addr[2] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Addr[3] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Addr[4] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Addr[5] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Addr[6] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Addr[7] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Addr[8] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Addr[9] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Addr[10] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Addr[11] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Addr[12] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Addr[13] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Addr[14] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Addr[15] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Addr[16] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Addr[17] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Addr[18] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Addr[19] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Addr[20] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Addr[21] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Addr[22] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Bank +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to BankWR_MC +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Bank[0] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Bank[1] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Bank[2] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Bank[3] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Bank[4] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Bank[5] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Bank[6] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Bank[7] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to C7M +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to C7M_2 +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to C7Mout +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to CASf +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to CASr +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to CSDBEN +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to D +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to DOE +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to D[0] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to D[0]~direct +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to D[1] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to D[1]~direct +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to D[2] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to D[2]~direct +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to D[3] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to D[3]~direct +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to D[4] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to D[4]~direct +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to D[5] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to D[5]~direct +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to D[6] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to D[6]~direct +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to D[7] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to D[7]~direct +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Dout +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Dout[0] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Dout[1] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Dout[2] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Dout[3] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Dout[4] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Dout[5] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Dout[6] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Dout[7] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Equal0 +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Equal1 +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Equal2 +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Equal3 +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Equal4 +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Equal5 +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Equal6 +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Equal7 +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Equal8 +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Equal9 +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Equal10 +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Equal11 +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Equal12 +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Equal13 +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Equal14 +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Equal15 +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Equal16 +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Equal17 +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to IOBank0 +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to IOROMEN +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to MODE +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to PHI0in +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to PHI0seen +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to PHI1b +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to PHI1b0_MC +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to PHI1b1_MC +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to PHI1b2_MC +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to PHI1b3_MC +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to PHI1b4_MC +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to PHI1b5_MC +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to PHI1b6_MC +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to PHI1b7_MC +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to PHI1b8_MC +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to PHI1b9_MC +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to PHI1in +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to PHI1out +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to PHI1reg +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Q3 +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RA +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RAMSEL_MC +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RAMSELreg +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RASf +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RASr +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RA[0] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RA[1] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RA[2] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RA[3] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RA[4] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RA[5] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RA[6] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RA[7] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RA[8] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RA[9] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RA[10] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RD +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RDOE +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RD[0] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RD[0]~direct +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RD[1] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RD[1]~direct +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RD[2] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RD[2]~direct +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RD[3] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RD[3]~direct +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RD[4] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RD[4]~direct +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RD[5] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RD[5]~direct +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RD[6] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RD[6]~direct +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RD[7] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to RD[7]~direct +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to REGEN +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Ref +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Ref[0] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Ref[1] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Ref[2] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to Ref[3] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to S +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to S[0] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to S[1] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to S[2] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to SetWR +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to always0 +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to always2 +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to comb +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to nCAS0 +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to nCAS1 +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to nDEVSEL +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to nINH +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to nIOSEL +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to nIOSTRB +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to nRAS +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to nRCS +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to nRES +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to nROE +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to nRWE +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to nWE +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to A \ No newline at end of file diff --git a/cpld/GR8RAM.qws b/cpld/GR8RAM.qws index 50b8f9f..10d80a6 100755 Binary files a/cpld/GR8RAM.qws and b/cpld/GR8RAM.qws differ diff --git a/cpld/GR8RAM.v b/cpld/GR8RAM.v index 05a41db..0ff5ebd 100755 --- a/cpld/GR8RAM.v +++ b/cpld/GR8RAM.v @@ -9,7 +9,7 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, MODE, input nRES, MODE; // Reset, mode /* PHI1 Delay */ - wire [6:0] PHI1b; + wire [8:0] PHI1b; wire PHI1; LCELL PHI1b0_MC (.in(PHI1in), .out(PHI1b[0])); LCELL PHI1b1_MC (.in(PHI1b[0]), .out(PHI1b[1])); @@ -18,7 +18,9 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, MODE, LCELL PHI1b4_MC (.in(PHI1b[3]), .out(PHI1b[4])); LCELL PHI1b5_MC (.in(PHI1b[4]), .out(PHI1b[5])); LCELL PHI1b6_MC (.in(PHI1b[5]), .out(PHI1b[6])); - LCELL PHI1b7_MC (.in(PHI1b[6] & PHI1in), .out(PHI1)); + LCELL PHI1b7_MC (.in(PHI1b[6]), .out(PHI1b[7])); + LCELL PHI1b8_MC (.in(PHI1b[7]), .out(PHI1b[8])); + LCELL PHI1b9_MC (.in(PHI1b[8] & PHI1in), .out(PHI1)); output C7Mout = C7M_2; output PHI1out = PHI1; @@ -28,37 +30,40 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, MODE, input nWE; // 6502 R/W output [10:0] RA; // DRAM/ROM address assign RA[10:8] = ASel ? Addr[10:8] : Addr[21:19]; - assign RA[7:1] = ~nDEVSEL ? (ASel ? Addr[7:1] : Addr[18:12]) : Bank[6:0]; - assign RA[0] = ~nDEVSEL ? (ASel ? Addr[0] : Addr[11]) : A[11]; + assign RA[7:0] = + (~nIOSTRB & nIOSEL & ~IOBank0) ? Bank+1 : + (ASel & nIOSEL & nIOSTRB) ? Addr[7:0] : + (~ASel & nIOSEL & nIOSTRB) ? Addr[18:11] : 8'h00; /* Data Bus Routing */ // DRAM/ROM data bus - wire RDOE = nRES | (CSDBEN & (~nWE | (nDEVSEL & nIOSEL & nIOSTRB))); + wire RDOE = CSDBEN & ~nWE; inout [7:0] RD = RDOE ? D[7:0] : 8'bZ; // Apple II data bus - wire DOE = nRES & CSDBEN & nWE & + wire DOE = CSDBEN & nWE & ((~nDEVSEL & REGEN) | ~nIOSEL | (~nIOSTRB & IOROMEN)); wire [7:0] Dout = (nDEVSEL | RAMSELA) ? RD[7:0] : - AddrHSELA ? {1'b1, Addr[22:16]} : + AddrHSELA ? {4'b1111, Addr[19:16]} : AddrMSELA ? Addr[15:8] : AddrLSELA ? Addr[7:0] : 8'h00; inout [7:0] D = DOE ? Dout : 8'bZ; /* Inhibit output */ - wire AROMSEL; + /*wire AROMSEL; LCELL AROMSEL_MC (.in((A[15:12]==4'hD | A[15:12]==4'hE | A[15:12]==4'hF) & nWE & ~MODE), .out(AROMSEL)); - output nINH = AROMSEL ? 1'b0 : 1'bZ; + output nINH = AROMSEL ? 1'b0 : 1'bZ;*/ + output nINH = 1'bZ; /* DRAM and ROM Control Signals */ output nRCS = ~((~nIOSEL | (~nIOSTRB & IOROMEN)) & CSDBEN); // ROM chip select output nROE = ~nWE; // need this for flash ROM - output nRWE = ~(~nWE & (~nDEVSEL | ~nIOSEL | ~nIOSTRB)); // for ROM & DRAM + output nRWE = nWE | (nDEVSEL & nIOSEL & nIOSTRB); // for ROM & DRAM output nRAS = ~(RASr | RASf); output nCAS0 = ~(CASr | (CASf & ~nDEVSEL & ~Addr[22])); // DRAM CAS bank 0 output nCAS1 = ~(CASr | (CASf & ~nDEVSEL & Addr[22])); // DRAM CAS bank 1 /* 6502-accessible Registers */ - reg [6:0] Bank = 7'h00; // Bank register for ROM access + reg [7:0] Bank = 8'h00; // Bank register for ROM access reg [22:0] Addr = 23'h00000; // RAM address register /* CAS rising/falling edge components */ @@ -77,22 +82,24 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, MODE, /* Select Signals */ reg RAMSELreg = 1'b0; // RAMSEL registered at end of S4 wire BankSELA = A[3:0]==4'hF; + wire SetSELA = A[3:0]==4'hE; wire RAMSELA = A[3:0]==4'h3; wire AddrHSELA = A[3:0]==4'h2; wire AddrMSELA = A[3:0]==4'h1; wire AddrLSELA = A[3:0]==4'h0; - LCELL BankWR_MC (.in(BankSELA & ~nWE & ~nDEVSEL & REGEN), .out(BankWR)); - wire BankWR; // Bank reg. at Cn0F - wire RAMSEL = RAMSELA & ~nDEVSEL & REGEN; // RAM data reg. at Cn03 - wire AddrHWR = AddrHSELA & ~nWE & ~nDEVSEL & REGEN; // Addr. hi reg. at Cn02 - wire AddrMWR = AddrMSELA & ~nWE & ~nDEVSEL & REGEN; // Addr. mid reg. at Cn01 - wire AddrLWR = AddrLSELA & ~nWE & ~nDEVSEL & REGEN; // Addr. lo reg. at Cn00 + LCELL BankWR_MC (.in(BankSELA & ~nWE & ~nDEVSEL & REGEN), .out(BankWR)); wire BankWR; + wire SetWR = SetSELA & ~nWE & ~nDEVSEL & REGEN; + LCELL RAMSEL_MC (.in(RAMSELA & ~nDEVSEL & REGEN), .out(RAMSEL)); wire RAMSEL; + LCELL AddrHWR_MC (.in(AddrHSELA & ~nWE & ~nDEVSEL & REGEN), .out(AddrHWR)); wire AddrHWR; + LCELL AddrMWR_MC (.in(AddrMSELA & ~nWE & ~nDEVSEL & REGEN), .out(AddrMWR)); wire AddrMWR; + LCELL AddrLWR_MC (.in(AddrLSELA & ~nWE & ~nDEVSEL & REGEN), .out(AddrLWR)); wire AddrLWR; /* Misc. */ reg REGEN = 0; // Register enable reg IOROMEN = 0; // IOSTRB ROM enable reg CSDBEN = 0; // ROM CS, data bus driver gating reg ASel = 0; // DRAM address multiplexer select + reg IOBank0 = 0; // Apple II Bus Compatibiltiy Rules: // Synchronize to PHI0 or PHI1. (PHI1 here) @@ -115,7 +122,8 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, MODE, IOROMEN <= 1'b0; CSDBEN <= 1'b0; Addr <= 23'h000000; - Bank <= 7'h00; + Bank <= 8'h00; + IOBank0 <= 1'b0; RAMSELreg <= 1'b0; end else begin // Synchronize state counter to S1 when just entering PHI1 @@ -134,8 +142,8 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, MODE, // Registers enabled at end of S4 by any IOSEL access (Cn00-CnFF). if (S==4 & ~nIOSEL) REGEN <= 1; - // Enable IOSTRB ROM when accessing 0xCn00 in IOSEL ROM. - if (S==4 & ~nIOSEL /* & A[7:0]==8'h00 */) IOROMEN <= 1'b1; + // Enable IOSTRB ROM when accessing CnXX in IOSEL ROM. + if (S==4 & ~nIOSEL) IOROMEN <= 1'b1; // Register RAM "register" selected at end of S4. if (S==4) RAMSELreg <= RAMSEL; @@ -150,12 +158,17 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, MODE, // Increment address register after RAM access, // otherwise set register during S6 if accessed. - if (S==1 & RAMSELreg) Addr <= Addr+1; // RAMSELreg refers to prev. - else if (S==6) begin - if (AddrHWR) Addr[22:16] <= D[6:0]; // Addr hi + if (S==2 & RAMSELreg) begin + Addr <= Addr+1; // RAMSELreg refers to prev. + RAMSELreg <= 1'b0; + end + + if (S==6) begin + if (BankWR) Bank[7:0] <= D[7:0]; // Bank + if (SetWR) IOBank0 <= D[7:0] == 8'hE5; + if (AddrHWR) Addr[19:16] <= D[3:0]; // Addr hi if (AddrMWR) Addr[15:8] <= D[7:0]; // Addr mid if (AddrLWR) Addr[7:0] <= D[7:0]; // Addr lo - if (BankWR) Bank[6:0] <= D[6:0]; // Bank end end end diff --git a/cpld/db/GR8RAM.(0).cnf.cdb b/cpld/db/GR8RAM.(0).cnf.cdb index 3ab6a18..f5ff821 100755 Binary files a/cpld/db/GR8RAM.(0).cnf.cdb and b/cpld/db/GR8RAM.(0).cnf.cdb differ diff --git a/cpld/db/GR8RAM.(0).cnf.hdb b/cpld/db/GR8RAM.(0).cnf.hdb index 9d28688..6752489 100755 Binary files a/cpld/db/GR8RAM.(0).cnf.hdb and b/cpld/db/GR8RAM.(0).cnf.hdb differ diff --git a/cpld/db/GR8RAM.(1).cnf.cdb b/cpld/db/GR8RAM.(1).cnf.cdb index a5f13c1..de85ff3 100755 Binary files a/cpld/db/GR8RAM.(1).cnf.cdb and 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a/cpld/db/GR8RAM.(9).cnf.cdb and b/cpld/db/GR8RAM.(9).cnf.cdb differ diff --git a/cpld/db/GR8RAM.(9).cnf.hdb b/cpld/db/GR8RAM.(9).cnf.hdb index aedc650..6a799fc 100755 Binary files a/cpld/db/GR8RAM.(9).cnf.hdb and b/cpld/db/GR8RAM.(9).cnf.hdb differ diff --git a/cpld/db/GR8RAM.ace_cmp.cdb b/cpld/db/GR8RAM.ace_cmp.cdb index d7774c6..cdc66bb 100755 Binary files a/cpld/db/GR8RAM.ace_cmp.cdb and b/cpld/db/GR8RAM.ace_cmp.cdb differ diff --git a/cpld/db/GR8RAM.ace_cmp.hdb b/cpld/db/GR8RAM.ace_cmp.hdb index becfb9a..6fdf4c1 100755 Binary files a/cpld/db/GR8RAM.ace_cmp.hdb and b/cpld/db/GR8RAM.ace_cmp.hdb differ diff --git a/cpld/db/GR8RAM.asm.qmsg b/cpld/db/GR8RAM.asm.qmsg index 3231818..7272185 100755 --- a/cpld/db/GR8RAM.asm.qmsg +++ b/cpld/db/GR8RAM.asm.qmsg @@ -1,5 +1,5 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567306420769 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567306420769 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Aug 31 22:53:40 2019 " "Processing started: Sat Aug 31 22:53:40 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567306420769 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1567306420769 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1567306420769 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1567306422534 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "277 " "Peak virtual memory: 277 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567306423003 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 31 22:53:43 2019 " "Processing ended: Sat Aug 31 22:53:43 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567306423003 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567306423003 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567306423003 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1567306423003 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567385056202 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567385056202 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Sep 01 20:44:16 2019 " "Processing started: Sun Sep 01 20:44:16 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567385056202 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1567385056202 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1567385056202 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1567385056310 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4520 " "Peak virtual memory: 4520 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567385056470 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Sep 01 20:44:16 2019 " "Processing ended: Sun Sep 01 20:44:16 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567385056470 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567385056470 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567385056470 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1567385056470 ""} diff --git a/cpld/db/GR8RAM.asm.rdb b/cpld/db/GR8RAM.asm.rdb index 96b496c..e5975f4 100755 Binary files a/cpld/db/GR8RAM.asm.rdb and b/cpld/db/GR8RAM.asm.rdb differ diff --git a/cpld/db/GR8RAM.cmp.cdb b/cpld/db/GR8RAM.cmp.cdb index c55969f..6f73150 100755 Binary files a/cpld/db/GR8RAM.cmp.cdb and b/cpld/db/GR8RAM.cmp.cdb differ diff --git a/cpld/db/GR8RAM.cmp.hdb b/cpld/db/GR8RAM.cmp.hdb index a325b36..3ae1f94 100755 Binary files a/cpld/db/GR8RAM.cmp.hdb and b/cpld/db/GR8RAM.cmp.hdb differ diff --git a/cpld/db/GR8RAM.cmp.rdb b/cpld/db/GR8RAM.cmp.rdb index 10e571a..834cece 100755 Binary files a/cpld/db/GR8RAM.cmp.rdb and b/cpld/db/GR8RAM.cmp.rdb differ diff --git a/cpld/db/GR8RAM.cmp0.ddb b/cpld/db/GR8RAM.cmp0.ddb index c103558..f0e0e13 100755 Binary files a/cpld/db/GR8RAM.cmp0.ddb and b/cpld/db/GR8RAM.cmp0.ddb differ diff --git a/cpld/db/GR8RAM.db_info b/cpld/db/GR8RAM.db_info index f748a16..c2244d3 100755 --- a/cpld/db/GR8RAM.db_info +++ b/cpld/db/GR8RAM.db_info @@ -1,3 +1,3 @@ Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition Version_Index = 302049280 -Creation_Time = Sat Aug 31 21:50:24 2019 +Creation_Time = Sat Aug 31 22:55:28 2019 diff --git a/cpld/db/GR8RAM.eco.cdb b/cpld/db/GR8RAM.eco.cdb index 4b820b1..41a35fa 100755 Binary files a/cpld/db/GR8RAM.eco.cdb and b/cpld/db/GR8RAM.eco.cdb differ diff --git a/cpld/db/GR8RAM.fit.qmsg b/cpld/db/GR8RAM.fit.qmsg index 92ef7b7..6558ca6 100755 --- a/cpld/db/GR8RAM.fit.qmsg +++ b/cpld/db/GR8RAM.fit.qmsg @@ -1,4 +1,3 @@ -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1567306416644 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1567306416878 ""} -{ "Warning" "WF7K_INCONSISTENT_MC_PIN_LOCATION" "PHI1b7_MC LC127 PHI1out PIN_30 " "Can't place macrocell \"PHI1b7_MC\" assigned to LC127 and node \"PHI1out\" assigned to PIN_30 -- ignoring macrocell assignment" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 23 -1 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 21 0 0 } } } 0 163058 "Can't place macrocell \"%1!s!\" assigned to %2!s! and node \"%3!s!\" assigned to %4!s! -- ignoring macrocell assignment" 0 0 "Fitter" 0 -1 1567306417144 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "287 " "Peak virtual memory: 287 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567306418425 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 31 22:53:38 2019 " "Processing ended: Sat Aug 31 22:53:38 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567306418425 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567306418425 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567306418425 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1567306418425 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1567385055172 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1567385055174 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4708 " "Peak virtual memory: 4708 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567385055356 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Sep 01 20:44:15 2019 " "Processing ended: Sun Sep 01 20:44:15 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567385055356 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567385055356 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567385055356 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1567385055356 ""} diff --git a/cpld/db/GR8RAM.hier_info b/cpld/db/GR8RAM.hier_info index cdee1b8..0c0820c 100755 --- a/cpld/db/GR8RAM.hier_info +++ b/cpld/db/GR8RAM.hier_info @@ -3,6 +3,7 @@ C7M => CASr.CLK C7M => RASr.CLK C7M => ASel.CLK C7M => RAMSELreg.CLK +C7M => IOBank0.CLK C7M => Bank[0].CLK C7M => Bank[1].CLK C7M => Bank[2].CLK @@ -10,6 +11,7 @@ C7M => Bank[3].CLK C7M => Bank[4].CLK C7M => Bank[5].CLK C7M => Bank[6].CLK +C7M => Bank[7].CLK C7M => Addr[0].CLK C7M => Addr[1].CLK C7M => Addr[2].CLK @@ -51,54 +53,48 @@ Q3 => ~NO_FANOUT~ PHI0in => ~NO_FANOUT~ PHI1in => comb.IN0 PHI1in => PHI1b0_MC.DATAIN -nRES => RDOE.IN1 -nRES => comb.IN0 nRES => always0.IN0 -MODE => comb.IN0 +MODE => ~NO_FANOUT~ +A[0] => Equal0.IN7 +A[0] => Equal1.IN7 +A[0] => Equal2.IN7 A[0] => Equal3.IN7 A[0] => Equal4.IN7 A[0] => Equal5.IN7 -A[0] => Equal6.IN7 -A[0] => Equal7.IN7 -A[0] => Equal12.IN21 +A[0] => Equal10.IN21 +A[1] => Equal0.IN6 +A[1] => Equal1.IN6 +A[1] => Equal2.IN6 A[1] => Equal3.IN6 A[1] => Equal4.IN6 A[1] => Equal5.IN6 -A[1] => Equal6.IN6 -A[1] => Equal7.IN6 -A[1] => Equal12.IN20 +A[1] => Equal10.IN20 +A[2] => Equal0.IN5 +A[2] => Equal1.IN5 +A[2] => Equal2.IN5 A[2] => Equal3.IN5 A[2] => Equal4.IN5 A[2] => Equal5.IN5 -A[2] => Equal6.IN5 -A[2] => Equal7.IN5 -A[2] => Equal12.IN19 +A[2] => Equal10.IN19 +A[3] => Equal0.IN4 +A[3] => Equal1.IN4 +A[3] => Equal2.IN4 A[3] => Equal3.IN4 A[3] => Equal4.IN4 A[3] => Equal5.IN4 -A[3] => Equal6.IN4 -A[3] => Equal7.IN4 -A[3] => Equal12.IN18 -A[4] => Equal12.IN17 -A[5] => Equal12.IN16 -A[6] => Equal12.IN15 -A[7] => Equal12.IN14 -A[8] => Equal12.IN13 -A[9] => Equal12.IN12 -A[10] => Equal12.IN11 -A[11] => RA.DATAA -A[12] => Equal0.IN7 -A[12] => Equal1.IN7 -A[12] => Equal2.IN7 -A[13] => Equal0.IN6 -A[13] => Equal1.IN6 -A[13] => Equal2.IN6 -A[14] => Equal0.IN5 -A[14] => Equal1.IN5 -A[14] => Equal2.IN5 -A[15] => Equal0.IN4 -A[15] => Equal1.IN4 -A[15] => Equal2.IN4 +A[3] => Equal10.IN18 +A[4] => Equal10.IN17 +A[5] => Equal10.IN16 +A[6] => Equal10.IN15 +A[7] => Equal10.IN14 +A[8] => Equal10.IN13 +A[9] => Equal10.IN12 +A[10] => Equal10.IN11 +A[11] => ~NO_FANOUT~ +A[12] => ~NO_FANOUT~ +A[13] => ~NO_FANOUT~ +A[14] => ~NO_FANOUT~ +A[15] => ~NO_FANOUT~ RA[0] <= RA.DB_MAX_OUTPUT_PORT_TYPE RA[1] <= RA.DB_MAX_OUTPUT_PORT_TYPE RA[2] <= RA.DB_MAX_OUTPUT_PORT_TYPE @@ -111,8 +107,11 @@ RA[8] <= RA.DB_MAX_OUTPUT_PORT_TYPE RA[9] <= RA.DB_MAX_OUTPUT_PORT_TYPE RA[10] <= RA.DB_MAX_OUTPUT_PORT_TYPE nWE => comb.IN0 +nWE => comb.IN0 nWE => comb.IN1 -nWE => comb.IN1 +nWE => comb.IN0 +nWE => comb.IN0 +nWE => comb.IN0 nWE => comb.IN0 nWE => CASf.IN1 D[0] <> D[0] @@ -132,14 +131,23 @@ RD[5] <> RD[5] RD[6] <> RD[6] RD[7] <> RD[7] nINH <= nINH.DB_MAX_OUTPUT_PORT_TYPE -nDEVSEL => RA.IN0 nDEVSEL => comb.IN0 nDEVSEL => comb.IN0 nDEVSEL => comb.IN0 -nIOSEL => comb.IN1 +nDEVSEL => comb.IN0 +nDEVSEL => comb.IN0 +nDEVSEL => comb.IN0 +nDEVSEL => comb.IN0 +nDEVSEL => comb.IN0 +nIOSEL => RA.IN1 +nIOSEL => RA.IN0 +nIOSEL => RA.IN1 nIOSEL => comb.IN0 +nIOSEL => comb.IN1 +nIOSTRB => RA.IN0 +nIOSTRB => RA.IN1 +nIOSTRB => RA.IN1 nIOSTRB => comb.IN1 -nIOSTRB => comb.IN0 nRAS <= comb.DB_MAX_OUTPUT_PORT_TYPE nCAS0 <= comb.DB_MAX_OUTPUT_PORT_TYPE nCAS1 <= comb.DB_MAX_OUTPUT_PORT_TYPE @@ -147,6 +155,6 @@ nRCS <= comb.DB_MAX_OUTPUT_PORT_TYPE nROE <= comb.DB_MAX_OUTPUT_PORT_TYPE nRWE <= comb.DB_MAX_OUTPUT_PORT_TYPE C7Mout <= C7M_2.DB_MAX_OUTPUT_PORT_TYPE -PHI1out <= PHI1b7_MC.DB_MAX_OUTPUT_PORT_TYPE +PHI1out <= PHI1b9_MC.DB_MAX_OUTPUT_PORT_TYPE diff --git a/cpld/db/GR8RAM.hif b/cpld/db/GR8RAM.hif index dad855a..94c46c0 100755 Binary files a/cpld/db/GR8RAM.hif and b/cpld/db/GR8RAM.hif differ diff --git a/cpld/db/GR8RAM.ipinfo b/cpld/db/GR8RAM.ipinfo index 6ff9cf3..fa2304d 100755 Binary files a/cpld/db/GR8RAM.ipinfo and b/cpld/db/GR8RAM.ipinfo differ diff --git a/cpld/db/GR8RAM.lpc.rdb b/cpld/db/GR8RAM.lpc.rdb index f46ce48..adf8589 100755 Binary files a/cpld/db/GR8RAM.lpc.rdb and b/cpld/db/GR8RAM.lpc.rdb differ diff --git a/cpld/db/GR8RAM.map.cdb b/cpld/db/GR8RAM.map.cdb index 793c2ef..a702a7b 100755 Binary files a/cpld/db/GR8RAM.map.cdb and b/cpld/db/GR8RAM.map.cdb differ diff --git a/cpld/db/GR8RAM.map.hdb b/cpld/db/GR8RAM.map.hdb index f997ee2..f73aba6 100755 Binary files a/cpld/db/GR8RAM.map.hdb and b/cpld/db/GR8RAM.map.hdb differ diff --git a/cpld/db/GR8RAM.map.qmsg b/cpld/db/GR8RAM.map.qmsg index 5a8f19f..55f5765 100755 --- a/cpld/db/GR8RAM.map.qmsg +++ b/cpld/db/GR8RAM.map.qmsg @@ -1,32 +1,36 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567306399346 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567306399346 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Aug 31 22:53:19 2019 " "Processing started: Sat Aug 31 22:53:19 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567306399346 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1567306399346 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1567306399346 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1567306403300 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(37) " "Verilog HDL warning at GR8RAM.v(37): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 37 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1567306403518 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(45) " "Verilog HDL warning at GR8RAM.v(45): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 45 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1567306403534 ""} -{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "GR8RAM.v(164) " "Verilog HDL information at GR8RAM.v(164): always construct contains both blocking and non-blocking assignments" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 164 0 0 } } } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Quartus II" 0 -1 1567306403534 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1567306403534 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1567306403534 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1567306404003 ""} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 GR8RAM.v(124) " "Verilog HDL assignment warning at GR8RAM.v(124): truncated value with size 32 to match size of target (3)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 124 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567306404003 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(129) " "Verilog HDL assignment warning at GR8RAM.v(129): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 129 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567306404003 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 23 GR8RAM.v(153) " "Verilog HDL assignment warning at GR8RAM.v(153): truncated value with size 32 to match size of target (23)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 153 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567306404003 "|GR8RAM"} -{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "Ref_rtl_0 4 " "Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"Ref_rtl_0\"" { } { } 0 19001 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567306404362 ""} } { } 0 19000 "Inferred %1!d! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1567306404362 ""} -{ "Info" "ILPMS_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add2 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add2\"" { } { { "GR8RAM.v" "Add2" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 153 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567306404362 ""} } { } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1567306404362 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter:Ref_rtl_0 " "Elaborated megafunction instantiation \"lpm_counter:Ref_rtl_0\"" { } { } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567306404956 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_counter:Ref_rtl_0 " "Instantiated megafunction \"lpm_counter:Ref_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 4 " "Parameter \"LPM_WIDTH\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567306404956 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION UP " "Parameter \"LPM_DIRECTION\" = \"UP\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567306404956 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_COUNTER " "Parameter \"LPM_TYPE\" = \"LPM_COUNTER\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567306404956 ""} } { } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567306404956 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add2 " "Elaborated megafunction instantiation \"lpm_add_sub:Add2\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 153 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567306405222 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add2 " "Instantiated megafunction \"lpm_add_sub:Add2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 23 " "Parameter \"LPM_WIDTH\" = \"23\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567306405222 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Parameter \"LPM_DIRECTION\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567306405222 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567306405222 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567306405222 ""} } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 153 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567306405222 ""} -{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add2\|addcore:adder\[2\] lpm_add_sub:Add2 " "Elaborated megafunction instantiation \"lpm_add_sub:Add2\|addcore:adder\[2\]\", which is child of megafunction instantiation \"lpm_add_sub:Add2\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 260 9 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 153 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567306405487 ""} -{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add2\|addcore:adder\[2\]\|a_csnbuffer:oflow_node lpm_add_sub:Add2 " "Elaborated megafunction instantiation \"lpm_add_sub:Add2\|addcore:adder\[2\]\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:Add2\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 86 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 153 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567306405690 ""} -{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add2\|addcore:adder\[2\]\|a_csnbuffer:result_node lpm_add_sub:Add2 " "Elaborated megafunction instantiation \"lpm_add_sub:Add2\|addcore:adder\[2\]\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:Add2\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 178 5 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 153 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567306405706 ""} -{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add2\|addcore:adder\[1\] lpm_add_sub:Add2 " "Elaborated megafunction instantiation \"lpm_add_sub:Add2\|addcore:adder\[1\]\", which is child of megafunction instantiation \"lpm_add_sub:Add2\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 260 9 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 153 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567306405722 ""} -{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add2\|look_add:look_ahead_unit lpm_add_sub:Add2 " "Elaborated megafunction instantiation \"lpm_add_sub:Add2\|look_add:look_ahead_unit\", which is child of megafunction instantiation \"lpm_add_sub:Add2\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 263 4 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 153 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567306406065 ""} -{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add2\|altshift:result_ext_latency_ffs lpm_add_sub:Add2 " "Elaborated megafunction instantiation \"lpm_add_sub:Add2\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add2\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 153 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567306406315 ""} -{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add2\|altshift:carry_ext_latency_ffs lpm_add_sub:Add2 " "Elaborated megafunction instantiation \"lpm_add_sub:Add2\|altshift:carry_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add2\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 270 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 153 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567306406331 ""} -{ "Info" "IMLS_MLS_IGNORED_SUMMARY" "23 " "Ignored 23 buffer(s)" { { "Info" "IMLS_MLS_IGNORED_SOFT" "23 " "Ignored 23 SOFT buffer(s)" { } { } 0 13019 "Ignored %1!d! SOFT buffer(s)" 0 0 "Quartus II" 0 -1 1567306406815 ""} } { } 0 13014 "Ignored %1!d! buffer(s)" 0 0 "Quartus II" 0 -1 1567306406815 ""} -{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "C7M " "Promoted clock signal driven by pin \"C7M\" to global clock signal" { } { } 0 280014 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0 "Quartus II" 0 -1 1567306407050 ""} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "nRES " "Promoted clear signal driven by pin \"nRES\" to global clear signal" { } { } 0 280015 "Promoted clear signal driven by pin \"%1!s!\" to global clear signal" 0 0 "Quartus II" 0 -1 1567306407050 ""} } { } 0 280013 "Promoted pin-driven signal(s) to global signal" 0 0 "Quartus II" 0 -1 1567306407050 ""} -{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "C7M " "Promoted clock signal driven by pin \"C7M\" to global clock signal" { } { } 0 280014 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0 "Quartus II" 0 -1 1567306408190 ""} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "nRES " "Promoted clear signal driven by pin \"nRES\" to global clear signal" { } { } 0 280015 "Promoted clear signal driven by pin \"%1!s!\" to global clear signal" 0 0 "Quartus II" 0 -1 1567306408190 ""} } { } 0 280013 "Promoted pin-driven signal(s) to global signal" 0 0 "Quartus II" 0 -1 1567306408190 ""} -{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "Q3 " "No output dependent on input pin \"Q3\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 8 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567306409065 "|GR8RAM|Q3"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "PHI0in " "No output dependent on input pin \"PHI0in\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 8 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567306409065 "|GR8RAM|PHI0in"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1567306409065 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "169 " "Implemented 169 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "27 " "Implemented 27 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1567306409112 ""} { "Info" "ICUT_CUT_TM_OPINS" "20 " "Implemented 20 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1567306409112 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Implemented 16 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1567306409112 ""} { "Info" "ICUT_CUT_TM_MCELLS" "96 " "Implemented 96 macrocells" { } { } 0 21063 "Implemented %1!d! macrocells" 0 0 "Quartus II" 0 -1 1567306409112 ""} { "Info" "ICUT_CUT_TM_SEXPS" "10 " "Implemented 10 shareable expanders" { } { } 0 21073 "Implemented %1!d! shareable expanders" 0 0 "Quartus II" 0 -1 1567306409112 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1567306409112 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1567306409518 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 7 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "308 " "Peak virtual memory: 308 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567306409659 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 31 22:53:29 2019 " "Processing ended: Sat Aug 31 22:53:29 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567306409659 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567306409659 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:10 " "Total CPU time (on all processors): 00:00:10" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567306409659 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567306409659 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567385053238 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567385053238 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Sep 01 20:44:13 2019 " "Processing started: Sun Sep 01 20:44:13 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567385053238 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1567385053238 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1567385053238 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1567385053456 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(41) " "Verilog HDL warning at GR8RAM.v(41): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 41 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1567385053481 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(49) " "Verilog HDL warning at GR8RAM.v(49): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 49 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1567385053481 ""} +{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "GR8RAM.v(177) " "Verilog HDL information at GR8RAM.v(177): always construct contains both blocking and non-blocking assignments" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 177 0 0 } } } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Quartus II" 0 -1 1567385053481 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1567385053482 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1567385053482 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1567385053522 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(33) " "Verilog HDL assignment warning at GR8RAM.v(33): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 33 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567385053523 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 GR8RAM.v(132) " "Verilog HDL assignment warning at GR8RAM.v(132): truncated value with size 32 to match size of target (3)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 132 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567385053523 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(137) " "Verilog HDL assignment warning at GR8RAM.v(137): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 137 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567385053524 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 23 GR8RAM.v(162) " "Verilog HDL assignment warning at GR8RAM.v(162): truncated value with size 32 to match size of target (23)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 162 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567385053524 "|GR8RAM"} +{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "Ref_rtl_0 4 " "Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"Ref_rtl_0\"" { } { } 0 19001 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567385053598 ""} } { } 0 19000 "Inferred %1!d! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1567385053598 ""} +{ "Info" "ILPMS_INFERENCING_SUMMARY" "2 " "Inferred 2 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add0 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add0\"" { } { { "GR8RAM.v" "Add0" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 34 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567385053599 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add3 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add3\"" { } { { "GR8RAM.v" "Add3" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 162 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567385053599 ""} } { } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1567385053599 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter:Ref_rtl_0 " "Elaborated megafunction instantiation \"lpm_counter:Ref_rtl_0\"" { } { } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567385053623 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_counter:Ref_rtl_0 " "Instantiated megafunction \"lpm_counter:Ref_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 4 " "Parameter \"LPM_WIDTH\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567385053624 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION UP " "Parameter \"LPM_DIRECTION\" = \"UP\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567385053624 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_COUNTER " "Parameter \"LPM_TYPE\" = \"LPM_COUNTER\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567385053624 ""} } { } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567385053624 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 34 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567385053641 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add0 " "Instantiated megafunction \"lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 8 " "Parameter \"LPM_WIDTH\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567385053641 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Parameter \"LPM_DIRECTION\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567385053641 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567385053641 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567385053641 ""} } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 34 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567385053641 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\] lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 260 9 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 34 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567385053656 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 86 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 34 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567385053665 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 178 5 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 34 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567385053667 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|look_add:look_ahead_unit lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|look_add:look_ahead_unit\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 263 4 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 34 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567385053679 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:result_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 34 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567385053688 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 270 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 34 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567385053689 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add3 " "Elaborated megafunction instantiation \"lpm_add_sub:Add3\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 162 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567385053692 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add3 " "Instantiated megafunction \"lpm_add_sub:Add3\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 23 " "Parameter \"LPM_WIDTH\" = \"23\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567385053692 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Parameter \"LPM_DIRECTION\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567385053692 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567385053692 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567385053692 ""} } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 162 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567385053692 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add3\|addcore:adder\[2\] lpm_add_sub:Add3 " "Elaborated megafunction instantiation \"lpm_add_sub:Add3\|addcore:adder\[2\]\", which is child of megafunction instantiation \"lpm_add_sub:Add3\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 260 9 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 162 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567385053694 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add3\|look_add:look_ahead_unit lpm_add_sub:Add3 " "Elaborated megafunction instantiation \"lpm_add_sub:Add3\|look_add:look_ahead_unit\", which is child of megafunction instantiation \"lpm_add_sub:Add3\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 263 4 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 162 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567385053700 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add3\|altshift:result_ext_latency_ffs lpm_add_sub:Add3 " "Elaborated megafunction instantiation \"lpm_add_sub:Add3\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add3\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 162 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567385053701 ""} +{ "Info" "IMLS_MLS_IGNORED_SUMMARY" "31 " "Ignored 31 buffer(s)" { { "Info" "IMLS_MLS_IGNORED_SOFT" "31 " "Ignored 31 SOFT buffer(s)" { } { } 0 13019 "Ignored %1!d! SOFT buffer(s)" 0 0 "Quartus II" 0 -1 1567385053756 ""} } { } 0 13014 "Ignored %1!d! buffer(s)" 0 0 "Quartus II" 0 -1 1567385053756 ""} +{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "C7M " "Promoted clock signal driven by pin \"C7M\" to global clock signal" { } { } 0 280014 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0 "Quartus II" 0 -1 1567385053836 ""} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "nRES " "Promoted clear signal driven by pin \"nRES\" to global clear signal" { } { } 0 280015 "Promoted clear signal driven by pin \"%1!s!\" to global clear signal" 0 0 "Quartus II" 0 -1 1567385053836 ""} } { } 0 280013 "Promoted pin-driven signal(s) to global signal" 0 0 "Quartus II" 0 -1 1567385053836 ""} +{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "8 " "Design contains 8 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "Q3 " "No output dependent on input pin \"Q3\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 8 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567385054051 "|GR8RAM|Q3"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "PHI0in " "No output dependent on input pin \"PHI0in\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 8 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567385054051 "|GR8RAM|PHI0in"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "MODE " "No output dependent on input pin \"MODE\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567385054051 "|GR8RAM|MODE"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[11\] " "No output dependent on input pin \"A\[11\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 29 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567385054051 "|GR8RAM|A[11]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[12\] " "No output dependent on input pin \"A\[12\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 29 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567385054051 "|GR8RAM|A[12]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[13\] " "No output dependent on input pin \"A\[13\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 29 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567385054051 "|GR8RAM|A[13]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[14\] " "No output dependent on input pin \"A\[14\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 29 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567385054051 "|GR8RAM|A[14]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[15\] " "No output dependent on input pin \"A\[15\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 29 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567385054051 "|GR8RAM|A[15]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1567385054051 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "170 " "Implemented 170 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "27 " "Implemented 27 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1567385054052 ""} { "Info" "ICUT_CUT_TM_OPINS" "20 " "Implemented 20 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1567385054052 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Implemented 16 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1567385054052 ""} { "Info" "ICUT_CUT_TM_MCELLS" "102 " "Implemented 102 macrocells" { } { } 0 21063 "Implemented %1!d! macrocells" 0 0 "Quartus II" 0 -1 1567385054052 ""} { "Info" "ICUT_CUT_TM_SEXPS" "5 " "Implemented 5 shareable expanders" { } { } 0 21073 "Implemented %1!d! shareable expanders" 0 0 "Quartus II" 0 -1 1567385054052 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1567385054052 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1567385054089 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 14 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 14 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4587 " "Peak virtual memory: 4587 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567385054124 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Sep 01 20:44:14 2019 " "Processing ended: Sun Sep 01 20:44:14 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567385054124 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567385054124 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567385054124 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567385054124 ""} diff --git a/cpld/db/GR8RAM.map.rdb b/cpld/db/GR8RAM.map.rdb index 9c5d47f..142bd0c 100755 Binary files a/cpld/db/GR8RAM.map.rdb and b/cpld/db/GR8RAM.map.rdb differ diff --git a/cpld/db/GR8RAM.pplq.rdb b/cpld/db/GR8RAM.pplq.rdb index 6619eee..723fcab 100755 Binary files a/cpld/db/GR8RAM.pplq.rdb and b/cpld/db/GR8RAM.pplq.rdb differ diff --git a/cpld/db/GR8RAM.pre_map.hdb b/cpld/db/GR8RAM.pre_map.hdb index a7344bf..7f8b4cf 100755 Binary files a/cpld/db/GR8RAM.pre_map.hdb and b/cpld/db/GR8RAM.pre_map.hdb differ diff --git a/cpld/db/GR8RAM.pti_db_list.ddb b/cpld/db/GR8RAM.pti_db_list.ddb index 61ca8da..89aa9b4 100755 Binary files a/cpld/db/GR8RAM.pti_db_list.ddb and b/cpld/db/GR8RAM.pti_db_list.ddb differ diff --git a/cpld/db/GR8RAM.root_partition.map.reg_db.cdb b/cpld/db/GR8RAM.root_partition.map.reg_db.cdb index 1414cf3..ecea7f4 100755 Binary files a/cpld/db/GR8RAM.root_partition.map.reg_db.cdb and b/cpld/db/GR8RAM.root_partition.map.reg_db.cdb differ diff --git a/cpld/db/GR8RAM.rtlv.hdb b/cpld/db/GR8RAM.rtlv.hdb index 7e74d25..b860ce6 100755 Binary files a/cpld/db/GR8RAM.rtlv.hdb and b/cpld/db/GR8RAM.rtlv.hdb differ diff --git a/cpld/db/GR8RAM.rtlv_sg.cdb b/cpld/db/GR8RAM.rtlv_sg.cdb index 5bd50f6..71cec57 100755 Binary files a/cpld/db/GR8RAM.rtlv_sg.cdb and b/cpld/db/GR8RAM.rtlv_sg.cdb differ diff --git a/cpld/db/GR8RAM.rtlv_sg_swap.cdb b/cpld/db/GR8RAM.rtlv_sg_swap.cdb index e6e4232..bf4c983 100755 Binary files a/cpld/db/GR8RAM.rtlv_sg_swap.cdb and b/cpld/db/GR8RAM.rtlv_sg_swap.cdb differ diff --git a/cpld/db/GR8RAM.sgdiff.cdb b/cpld/db/GR8RAM.sgdiff.cdb index 85ecf12..64574be 100755 Binary files a/cpld/db/GR8RAM.sgdiff.cdb and b/cpld/db/GR8RAM.sgdiff.cdb differ diff --git a/cpld/db/GR8RAM.sgdiff.hdb b/cpld/db/GR8RAM.sgdiff.hdb index 88ca078..02ad015 100755 Binary files a/cpld/db/GR8RAM.sgdiff.hdb and b/cpld/db/GR8RAM.sgdiff.hdb differ diff --git a/cpld/db/GR8RAM.sld_design_entry.sci b/cpld/db/GR8RAM.sld_design_entry.sci index 754b594..1d6d60f 100755 Binary files a/cpld/db/GR8RAM.sld_design_entry.sci and b/cpld/db/GR8RAM.sld_design_entry.sci differ diff --git a/cpld/db/GR8RAM.sld_design_entry_dsc.sci b/cpld/db/GR8RAM.sld_design_entry_dsc.sci index 754b594..1d6d60f 100755 Binary files a/cpld/db/GR8RAM.sld_design_entry_dsc.sci and b/cpld/db/GR8RAM.sld_design_entry_dsc.sci differ diff --git a/cpld/db/GR8RAM.sta.qmsg b/cpld/db/GR8RAM.sta.qmsg index de57a35..41b8f32 100755 --- a/cpld/db/GR8RAM.sta.qmsg +++ b/cpld/db/GR8RAM.sta.qmsg @@ -1,22 +1,22 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567306426612 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567306426628 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Aug 31 22:53:44 2019 " "Processing started: Sat Aug 31 22:53:44 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567306426628 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1567306426628 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1567306426628 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1567306426847 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1567306429191 ""} -{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1567306429253 ""} -{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1567306429253 ""} -{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." { } { } 0 335095 "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." 0 0 "Quartus II" 0 -1 1567306429425 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1567306429612 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1567306429612 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M C7M " "create_clock -period 1.000 -name C7M C7M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567306429612 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M_2 C7M_2 " "create_clock -period 1.000 -name C7M_2 C7M_2" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567306429612 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567306429612 ""} -{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1567306429628 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1567306429816 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -29.000 " "Worst-case setup slack is -29.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567306429831 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567306429831 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.000 -821.000 C7M " " -29.000 -821.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567306429831 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.500 -11.000 C7M_2 " " -5.500 -11.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567306429831 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567306429831 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold -1.500 " "Worst-case hold slack is -1.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567306429847 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567306429847 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.500 -3.000 C7M_2 " " -1.500 -3.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567306429847 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 5.000 0.000 C7M " " 5.000 0.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567306429847 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567306429847 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567306430034 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567306430066 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -5.500 " "Worst-case minimum pulse width slack is -5.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567306430128 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567306430128 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.500 -22.000 C7M_2 " " -5.500 -22.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567306430128 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.500 -414.000 C7M " " -4.500 -414.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567306430128 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567306430128 ""} -{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1567306430378 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1567306430519 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1567306430519 ""} -{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "260 " "Peak virtual memory: 260 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567306430847 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 31 22:53:50 2019 " "Processing ended: Sat Aug 31 22:53:50 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567306430847 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567306430847 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567306430847 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567306430847 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567385057408 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567385057409 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Sep 01 20:44:17 2019 " "Processing started: Sun Sep 01 20:44:17 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567385057409 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1567385057409 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1567385057409 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1567385057466 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1567385057560 ""} +{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1567385057568 ""} +{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1567385057571 ""} +{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." { } { } 0 335095 "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." 0 0 "Quartus II" 0 -1 1567385057616 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1567385057629 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1567385057630 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M C7M " "create_clock -period 1.000 -name C7M C7M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567385057630 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M_2 C7M_2 " "create_clock -period 1.000 -name C7M_2 C7M_2" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567385057630 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567385057630 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1567385057632 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1567385057644 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -47.000 " "Worst-case setup slack is -47.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567385057649 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567385057649 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -47.000 -1802.000 C7M " " -47.000 -1802.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567385057649 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -27.500 -33.000 C7M_2 " " -27.500 -33.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567385057649 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567385057649 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold -1.500 " "Worst-case hold slack is -1.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567385057658 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567385057658 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.500 -3.000 C7M_2 " " -1.500 -3.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567385057658 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 5.000 0.000 C7M " " 5.000 0.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567385057658 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567385057658 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567385057664 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567385057669 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -5.500 " "Worst-case minimum pulse width slack is -5.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567385057674 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567385057674 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.500 -22.000 C7M_2 " " -5.500 -22.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567385057674 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.500 -432.000 C7M " " -4.500 -432.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567385057674 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567385057674 ""} +{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1567385057736 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1567385057757 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1567385057758 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4530 " "Peak virtual memory: 4530 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567385057823 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Sep 01 20:44:17 2019 " "Processing ended: Sun Sep 01 20:44:17 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567385057823 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567385057823 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567385057823 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567385057823 ""} diff --git a/cpld/db/GR8RAM.sta.rdb b/cpld/db/GR8RAM.sta.rdb index c11307a..3bbd688 100755 Binary files a/cpld/db/GR8RAM.sta.rdb and b/cpld/db/GR8RAM.sta.rdb differ diff --git a/cpld/db/GR8RAM.sta_cmp.15_slow.tdb b/cpld/db/GR8RAM.sta_cmp.15_slow.tdb index d52de17..2459af9 100755 Binary files a/cpld/db/GR8RAM.sta_cmp.15_slow.tdb and b/cpld/db/GR8RAM.sta_cmp.15_slow.tdb differ diff --git a/cpld/db/GR8RAM.tis_db_list.ddb b/cpld/db/GR8RAM.tis_db_list.ddb index 42a925d..91bbe10 100755 Binary files a/cpld/db/GR8RAM.tis_db_list.ddb and b/cpld/db/GR8RAM.tis_db_list.ddb differ diff --git a/cpld/db/GR8RAM.tmw_info b/cpld/db/GR8RAM.tmw_info index f7a5714..c91c206 100755 --- a/cpld/db/GR8RAM.tmw_info +++ b/cpld/db/GR8RAM.tmw_info @@ -1,6 +1,6 @@ -start_full_compilation:s:00:00:35 -start_analysis_synthesis:s:00:00:13-start_full_compilation +start_full_compilation:s:00:00:06 +start_analysis_synthesis:s:00:00:02-start_full_compilation start_analysis_elaboration:s-start_full_compilation -start_fitter:s:00:00:09-start_full_compilation -start_assembler:s:00:00:04-start_full_compilation -start_timing_analyzer:s:00:00:09-start_full_compilation +start_fitter:s:00:00:01-start_full_compilation +start_assembler:s:00:00:02-start_full_compilation +start_timing_analyzer:s:00:00:01-start_full_compilation diff --git a/cpld/db/add_sub_8ph.tdf b/cpld/db/add_sub_8ph.tdf index 4d85006..7cfaee1 100755 --- a/cpld/db/add_sub_8ph.tdf +++ b/cpld/db/add_sub_8ph.tdf @@ -1,5 +1,5 @@ --lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="MAX7000S" LPM_DIRECTION="ADD" LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=23 ONE_INPUT_IS_CONSTANT="YES" cin dataa datab result ---VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:40:SJ cbx_lpm_add_sub 2013:06:12:18:03:40:SJ cbx_mgl 2013:06:12:18:04:42:SJ cbx_stratix 2013:06:12:18:03:40:SJ cbx_stratixii 2013:06:12:18:03:40:SJ VERSION_END +--VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ VERSION_END -- Copyright (C) 1991-2013 Altera Corporation diff --git a/cpld/db/add_sub_rnh.tdf b/cpld/db/add_sub_rnh.tdf new file mode 100644 index 0000000..9106a37 --- /dev/null +++ b/cpld/db/add_sub_rnh.tdf @@ -0,0 +1,46 @@ +--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="MAX7000S" LPM_DIRECTION="ADD" LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=8 ONE_INPUT_IS_CONSTANT="YES" cin dataa datab result +--VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ VERSION_END + + +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION carry_sum (cin, sin) +RETURNS ( cout, sout); + +--synthesis_resources = lut 9 +SUBDESIGN add_sub_rnh +( + cin : input; + dataa[7..0] : input; + datab[7..0] : input; + result[7..0] : output; +) +VARIABLE + add_sub_cella[7..0] : carry_sum; + external_cin_cell : carry_sum; + datab_node[7..0] : WIRE; + main_cin_wire : WIRE; + +BEGIN + add_sub_cella[].cin = ( ((dataa[7..7] & datab_node[7..7]) # ((dataa[7..7] # datab_node[7..7]) & add_sub_cella[6].cout)), ((dataa[6..6] & datab_node[6..6]) # ((dataa[6..6] # datab_node[6..6]) & add_sub_cella[5].cout)), ((dataa[5..5] & datab_node[5..5]) # ((dataa[5..5] # datab_node[5..5]) & add_sub_cella[4].cout)), ((dataa[4..4] & datab_node[4..4]) # ((dataa[4..4] # datab_node[4..4]) & add_sub_cella[3].cout)), ((dataa[3..3] & datab_node[3..3]) # ((dataa[3..3] # datab_node[3..3]) & add_sub_cella[2].cout)), ((dataa[2..2] & datab_node[2..2]) # ((dataa[2..2] # datab_node[2..2]) & add_sub_cella[1].cout)), ((dataa[1..1] & datab_node[1..1]) # ((dataa[1..1] # datab_node[1..1]) & add_sub_cella[0].cout)), ((dataa[0..0] & datab_node[0..0]) # ((dataa[0..0] # datab_node[0..0]) & main_cin_wire))); + add_sub_cella[].sin = ( ((dataa[7..7] $ datab_node[7..7]) $ add_sub_cella[6].cout), ((dataa[6..6] $ datab_node[6..6]) $ add_sub_cella[5].cout), ((dataa[5..5] $ datab_node[5..5]) $ add_sub_cella[4].cout), ((dataa[4..4] $ datab_node[4..4]) $ add_sub_cella[3].cout), ((dataa[3..3] $ datab_node[3..3]) $ add_sub_cella[2].cout), ((dataa[2..2] $ datab_node[2..2]) $ add_sub_cella[1].cout), ((dataa[1..1] $ datab_node[1..1]) $ add_sub_cella[0].cout), ((dataa[0..0] $ datab_node[0..0]) $ main_cin_wire)); + external_cin_cell.cin = cin; + external_cin_cell.sin = B"0"; + datab_node[] = datab[]; + main_cin_wire = external_cin_cell.cout; + result[] = add_sub_cella[].sout; +END; +--VALID FILE diff --git a/cpld/db/prev_cmp_GR8RAM.qmsg b/cpld/db/prev_cmp_GR8RAM.qmsg index 3cf3c54..0cc81c1 100755 --- a/cpld/db/prev_cmp_GR8RAM.qmsg +++ b/cpld/db/prev_cmp_GR8RAM.qmsg @@ -1,71 +1,74 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567304478688 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567304478704 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Aug 31 22:21:18 2019 " "Processing started: Sat Aug 31 22:21:18 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567304478704 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1567304478704 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1567304478704 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1567304484735 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(37) " "Verilog HDL warning at GR8RAM.v(37): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 37 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1567304484907 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(45) " "Verilog HDL warning at GR8RAM.v(45): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 45 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1567304484907 ""} -{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "GR8RAM.v(164) " "Verilog HDL information at GR8RAM.v(164): always construct contains both blocking and non-blocking assignments" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 164 0 0 } } } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Quartus II" 0 -1 1567304484907 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1567304484922 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1567304484922 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1567304485282 ""} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 GR8RAM.v(124) " "Verilog HDL assignment warning at GR8RAM.v(124): truncated value with size 32 to match size of target (3)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 124 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567304485282 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(129) " "Verilog HDL assignment warning at GR8RAM.v(129): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 129 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567304485282 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 23 GR8RAM.v(153) " "Verilog HDL assignment warning at GR8RAM.v(153): truncated value with size 32 to match size of target (23)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 153 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567304485282 "|GR8RAM"} -{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "Ref_rtl_0 4 " "Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"Ref_rtl_0\"" { } { } 0 19001 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567304485579 ""} } { } 0 19000 "Inferred %1!d! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1567304485579 ""} -{ "Info" "ILPMS_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add2 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add2\"" { } { { "GR8RAM.v" "Add2" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 153 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567304485579 ""} } { } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1567304485579 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter:Ref_rtl_0 " "Elaborated megafunction instantiation \"lpm_counter:Ref_rtl_0\"" { } { } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567304485985 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_counter:Ref_rtl_0 " "Instantiated megafunction \"lpm_counter:Ref_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 4 " "Parameter \"LPM_WIDTH\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567304486032 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION UP " "Parameter \"LPM_DIRECTION\" = \"UP\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567304486032 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_COUNTER " "Parameter \"LPM_TYPE\" = \"LPM_COUNTER\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567304486032 ""} } { } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567304486032 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add2 " "Elaborated megafunction instantiation \"lpm_add_sub:Add2\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 153 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567304486360 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add2 " "Instantiated megafunction \"lpm_add_sub:Add2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 23 " "Parameter \"LPM_WIDTH\" = \"23\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567304486360 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Parameter \"LPM_DIRECTION\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567304486360 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567304486360 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567304486360 ""} } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 153 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567304486360 ""} -{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add2\|addcore:adder\[2\] lpm_add_sub:Add2 " "Elaborated megafunction instantiation \"lpm_add_sub:Add2\|addcore:adder\[2\]\", which is child of megafunction instantiation \"lpm_add_sub:Add2\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 260 9 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 153 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567304486719 ""} -{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add2\|addcore:adder\[2\]\|a_csnbuffer:oflow_node lpm_add_sub:Add2 " "Elaborated megafunction instantiation \"lpm_add_sub:Add2\|addcore:adder\[2\]\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:Add2\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 86 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 153 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567304487000 ""} -{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add2\|addcore:adder\[2\]\|a_csnbuffer:result_node lpm_add_sub:Add2 " "Elaborated megafunction instantiation \"lpm_add_sub:Add2\|addcore:adder\[2\]\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:Add2\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 178 5 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 153 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567304487032 ""} -{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add2\|addcore:adder\[1\] lpm_add_sub:Add2 " "Elaborated megafunction instantiation \"lpm_add_sub:Add2\|addcore:adder\[1\]\", which is child of megafunction instantiation \"lpm_add_sub:Add2\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 260 9 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 153 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567304487063 ""} -{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add2\|look_add:look_ahead_unit lpm_add_sub:Add2 " "Elaborated megafunction instantiation \"lpm_add_sub:Add2\|look_add:look_ahead_unit\", which is child of megafunction instantiation \"lpm_add_sub:Add2\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 263 4 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 153 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567304487610 ""} -{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add2\|altshift:result_ext_latency_ffs lpm_add_sub:Add2 " "Elaborated megafunction instantiation \"lpm_add_sub:Add2\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add2\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 153 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567304487844 ""} -{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add2\|altshift:carry_ext_latency_ffs lpm_add_sub:Add2 " "Elaborated megafunction instantiation \"lpm_add_sub:Add2\|altshift:carry_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add2\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 270 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 153 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567304487860 ""} -{ "Info" "IMLS_MLS_IGNORED_SUMMARY" "23 " "Ignored 23 buffer(s)" { { "Info" "IMLS_MLS_IGNORED_SOFT" "23 " "Ignored 23 SOFT buffer(s)" { } { } 0 13019 "Ignored %1!d! SOFT buffer(s)" 0 0 "Quartus II" 0 -1 1567304488282 ""} } { } 0 13014 "Ignored %1!d! buffer(s)" 0 0 "Quartus II" 0 -1 1567304488282 ""} -{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "C7M " "Promoted clock signal driven by pin \"C7M\" to global clock signal" { } { } 0 280014 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0 "Quartus II" 0 -1 1567304488547 ""} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "nRES " "Promoted clear signal driven by pin \"nRES\" to global clear signal" { } { } 0 280015 "Promoted clear signal driven by pin \"%1!s!\" to global clear signal" 0 0 "Quartus II" 0 -1 1567304488547 ""} } { } 0 280013 "Promoted pin-driven signal(s) to global signal" 0 0 "Quartus II" 0 -1 1567304488547 ""} -{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "C7M " "Promoted clock signal driven by pin \"C7M\" to global clock signal" { } { } 0 280014 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0 "Quartus II" 0 -1 1567304489469 ""} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "nRES " "Promoted clear signal driven by pin \"nRES\" to global clear signal" { } { } 0 280015 "Promoted clear signal driven by pin \"%1!s!\" to global clear signal" 0 0 "Quartus II" 0 -1 1567304489469 ""} } { } 0 280013 "Promoted pin-driven signal(s) to global signal" 0 0 "Quartus II" 0 -1 1567304489469 ""} -{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "Q3 " "No output dependent on input pin \"Q3\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 8 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567304490157 "|GR8RAM|Q3"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "PHI0in " "No output dependent on input pin \"PHI0in\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 8 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567304490157 "|GR8RAM|PHI0in"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1567304490157 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "169 " "Implemented 169 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "27 " "Implemented 27 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1567304490157 ""} { "Info" "ICUT_CUT_TM_OPINS" "20 " "Implemented 20 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1567304490157 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Implemented 16 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1567304490157 ""} { "Info" "ICUT_CUT_TM_MCELLS" "96 " "Implemented 96 macrocells" { } { } 0 21063 "Implemented %1!d! macrocells" 0 0 "Quartus II" 0 -1 1567304490157 ""} { "Info" "ICUT_CUT_TM_SEXPS" "10 " "Implemented 10 shareable expanders" { } { } 0 21073 "Implemented %1!d! shareable expanders" 0 0 "Quartus II" 0 -1 1567304490157 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1567304490157 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1567304490469 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 7 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "308 " "Peak virtual memory: 308 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567304490610 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 31 22:21:30 2019 " "Processing ended: Sat Aug 31 22:21:30 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567304490610 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Elapsed time: 00:00:12" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567304490610 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:10 " "Total CPU time (on all processors): 00:00:10" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567304490610 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567304490610 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567304496719 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 32-bit " "Running Quartus II 32-bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567304496751 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Aug 31 22:21:32 2019 " "Processing started: Sat Aug 31 22:21:32 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567304496751 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1567304496751 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1567304496751 ""} -{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1567304497079 ""} -{ "Info" "0" "" "Project = GR8RAM" { } { } 0 0 "Project = GR8RAM" 0 0 "Fitter" 0 0 1567304497079 ""} -{ "Info" "0" "" "Revision = GR8RAM" { } { } 0 0 "Revision = GR8RAM" 0 0 "Fitter" 0 0 1567304497079 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1567304500032 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1567304500157 ""} -{ "Warning" "WF7K_INCONSISTENT_MC_PIN_LOCATION" "PHI1b7_MC LC127 PHI1out PIN_30 " "Can't place macrocell \"PHI1b7_MC\" assigned to LC127 and node \"PHI1out\" assigned to PIN_30 -- ignoring macrocell assignment" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 23 -1 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 21 0 0 } } } 0 163058 "Can't place macrocell \"%1!s!\" assigned to %2!s! and node \"%3!s!\" assigned to %4!s! -- ignoring macrocell assignment" 0 0 "Fitter" 0 -1 1567304500767 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "287 " "Peak virtual memory: 287 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567304502767 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 31 22:21:42 2019 " "Processing ended: Sat Aug 31 22:21:42 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567304502767 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567304502767 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567304502767 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1567304502767 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1567304505314 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567304505314 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Aug 31 22:21:45 2019 " "Processing started: Sat Aug 31 22:21:45 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567304505314 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1567304505314 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1567304505314 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1567304507767 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "277 " "Peak virtual memory: 277 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567304508361 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 31 22:21:48 2019 " "Processing ended: Sat Aug 31 22:21:48 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567304508361 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567304508361 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567304508361 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1567304508361 ""} -{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1567304509111 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1567304511845 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567304511861 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Aug 31 22:21:49 2019 " "Processing started: Sat Aug 31 22:21:49 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567304511861 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1567304511861 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1567304511861 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1567304512048 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1567304513799 ""} -{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1567304513830 ""} -{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1567304513830 ""} -{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." { } { } 0 335095 "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." 0 0 "Quartus II" 0 -1 1567304513955 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1567304514049 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1567304514049 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M C7M " "create_clock -period 1.000 -name C7M C7M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567304514064 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M_2 C7M_2 " "create_clock -period 1.000 -name C7M_2 C7M_2" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567304514064 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567304514064 ""} -{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1567304514080 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1567304514220 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -29.000 " "Worst-case setup slack is -29.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567304514236 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567304514236 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.000 -821.000 C7M " " -29.000 -821.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567304514236 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.500 -11.000 C7M_2 " " -5.500 -11.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567304514236 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567304514236 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold -1.500 " "Worst-case hold slack is -1.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567304514252 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567304514252 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.500 -3.000 C7M_2 " " -1.500 -3.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567304514252 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 5.000 0.000 C7M " " 5.000 0.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567304514252 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567304514252 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567304514267 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567304514267 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -5.500 " "Worst-case minimum pulse width slack is -5.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567304514283 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567304514283 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.500 -22.000 C7M_2 " " -5.500 -22.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567304514283 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.500 -414.000 C7M " " -4.500 -414.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567304514283 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567304514283 ""} -{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1567304514439 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1567304514486 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1567304514486 ""} -{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "260 " "Peak virtual memory: 260 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567304514658 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 31 22:21:54 2019 " "Processing ended: Sat Aug 31 22:21:54 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567304514658 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567304514658 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567304514658 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567304514658 ""} -{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 13 s " "Quartus II Full Compilation was successful. 0 errors, 13 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567304515533 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567384350839 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567384350840 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Sep 01 20:32:30 2019 " "Processing started: Sun Sep 01 20:32:30 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567384350840 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1567384350840 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1567384350840 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1567384351069 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(41) " "Verilog HDL warning at GR8RAM.v(41): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 41 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1567384351095 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(49) " "Verilog HDL warning at GR8RAM.v(49): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 49 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1567384351095 ""} +{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "GR8RAM.v(177) " "Verilog HDL information at GR8RAM.v(177): always construct contains both blocking and non-blocking assignments" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 177 0 0 } } } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Quartus II" 0 -1 1567384351095 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1567384351098 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1567384351098 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1567384351146 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(33) " "Verilog HDL assignment warning at GR8RAM.v(33): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 33 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567384351148 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 GR8RAM.v(132) " "Verilog HDL assignment warning at GR8RAM.v(132): truncated value with size 32 to match size of target (3)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 132 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567384351149 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(137) " "Verilog HDL assignment warning at GR8RAM.v(137): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 137 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567384351149 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 23 GR8RAM.v(162) " "Verilog HDL assignment warning at GR8RAM.v(162): truncated value with size 32 to match size of target (23)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 162 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567384351149 "|GR8RAM"} +{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "Ref_rtl_0 4 " "Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"Ref_rtl_0\"" { } { } 0 19001 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567384351230 ""} } { } 0 19000 "Inferred %1!d! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1567384351230 ""} +{ "Info" "ILPMS_INFERENCING_SUMMARY" "2 " "Inferred 2 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add0 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add0\"" { } { { "GR8RAM.v" "Add0" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 34 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567384351230 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add3 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add3\"" { } { { "GR8RAM.v" "Add3" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 162 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567384351230 ""} } { } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1567384351230 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter:Ref_rtl_0 " "Elaborated megafunction instantiation \"lpm_counter:Ref_rtl_0\"" { } { } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567384351258 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_counter:Ref_rtl_0 " "Instantiated megafunction \"lpm_counter:Ref_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 4 " "Parameter \"LPM_WIDTH\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567384351258 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION UP " "Parameter \"LPM_DIRECTION\" = \"UP\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567384351258 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_COUNTER " "Parameter \"LPM_TYPE\" = \"LPM_COUNTER\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567384351258 ""} } { } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567384351258 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 34 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567384351275 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add0 " "Instantiated megafunction \"lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 8 " "Parameter \"LPM_WIDTH\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567384351275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Parameter \"LPM_DIRECTION\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567384351275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567384351275 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567384351275 ""} } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 34 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567384351275 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\] lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 260 9 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 34 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567384351288 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 86 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 34 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567384351298 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 178 5 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 34 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567384351300 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|look_add:look_ahead_unit lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|look_add:look_ahead_unit\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 263 4 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 34 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567384351312 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:result_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 34 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567384351324 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 270 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 34 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567384351325 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add3 " "Elaborated megafunction instantiation \"lpm_add_sub:Add3\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 162 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567384351330 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add3 " "Instantiated megafunction \"lpm_add_sub:Add3\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 23 " "Parameter \"LPM_WIDTH\" = \"23\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567384351330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Parameter \"LPM_DIRECTION\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567384351330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567384351330 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567384351330 ""} } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 162 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567384351330 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add3\|addcore:adder\[2\] lpm_add_sub:Add3 " "Elaborated megafunction instantiation \"lpm_add_sub:Add3\|addcore:adder\[2\]\", which is child of megafunction instantiation \"lpm_add_sub:Add3\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 260 9 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 162 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567384351332 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add3\|look_add:look_ahead_unit lpm_add_sub:Add3 " "Elaborated megafunction instantiation \"lpm_add_sub:Add3\|look_add:look_ahead_unit\", which is child of megafunction instantiation \"lpm_add_sub:Add3\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 263 4 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 162 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567384351338 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add3\|altshift:result_ext_latency_ffs lpm_add_sub:Add3 " "Elaborated megafunction instantiation \"lpm_add_sub:Add3\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add3\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 162 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567384351339 ""} +{ "Info" "IMLS_MLS_IGNORED_SUMMARY" "31 " "Ignored 31 buffer(s)" { { "Info" "IMLS_MLS_IGNORED_SOFT" "31 " "Ignored 31 SOFT buffer(s)" { } { } 0 13019 "Ignored %1!d! SOFT buffer(s)" 0 0 "Quartus II" 0 -1 1567384351400 ""} } { } 0 13014 "Ignored %1!d! buffer(s)" 0 0 "Quartus II" 0 -1 1567384351400 ""} +{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "C7M " "Promoted clock signal driven by pin \"C7M\" to global clock signal" { } { } 0 280014 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0 "Quartus II" 0 -1 1567384351481 ""} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "nRES " "Promoted clear signal driven by pin \"nRES\" to global clear signal" { } { } 0 280015 "Promoted clear signal driven by pin \"%1!s!\" to global clear signal" 0 0 "Quartus II" 0 -1 1567384351481 ""} } { } 0 280013 "Promoted pin-driven signal(s) to global signal" 0 0 "Quartus II" 0 -1 1567384351481 ""} +{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "8 " "Design contains 8 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "Q3 " "No output dependent on input pin \"Q3\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 8 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567384351716 "|GR8RAM|Q3"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "PHI0in " "No output dependent on input pin \"PHI0in\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 8 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567384351716 "|GR8RAM|PHI0in"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "MODE " "No output dependent on input pin \"MODE\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567384351716 "|GR8RAM|MODE"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[11\] " "No output dependent on input pin \"A\[11\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 29 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567384351716 "|GR8RAM|A[11]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[12\] " "No output dependent on input pin \"A\[12\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 29 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567384351716 "|GR8RAM|A[12]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[13\] " "No output dependent on input pin \"A\[13\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 29 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567384351716 "|GR8RAM|A[13]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[14\] " "No output dependent on input pin \"A\[14\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 29 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567384351716 "|GR8RAM|A[14]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[15\] " "No output dependent on input pin \"A\[15\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 29 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567384351716 "|GR8RAM|A[15]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1567384351716 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "170 " "Implemented 170 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "27 " "Implemented 27 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1567384351716 ""} { "Info" "ICUT_CUT_TM_OPINS" "20 " "Implemented 20 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1567384351716 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Implemented 16 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1567384351716 ""} { "Info" "ICUT_CUT_TM_MCELLS" "102 " "Implemented 102 macrocells" { } { } 0 21063 "Implemented %1!d! macrocells" 0 0 "Quartus II" 0 -1 1567384351716 ""} { "Info" "ICUT_CUT_TM_SEXPS" "5 " "Implemented 5 shareable expanders" { } { } 0 21073 "Implemented %1!d! shareable expanders" 0 0 "Quartus II" 0 -1 1567384351716 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1567384351716 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1567384351755 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 14 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 14 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4587 " "Peak virtual memory: 4587 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567384351797 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Sep 01 20:32:31 2019 " "Processing ended: Sun Sep 01 20:32:31 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567384351797 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567384351797 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567384351797 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567384351797 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567384352736 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 64-Bit " "Running Quartus II 64-Bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567384352736 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Sep 01 20:32:32 2019 " "Processing started: Sun Sep 01 20:32:32 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567384352736 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1567384352736 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1567384352736 ""} +{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1567384352791 ""} +{ "Info" "0" "" "Project = GR8RAM" { } { } 0 0 "Project = GR8RAM" 0 0 "Fitter" 0 0 1567384352792 ""} +{ "Info" "0" "" "Revision = GR8RAM" { } { } 0 0 "Revision = GR8RAM" 0 0 "Fitter" 0 0 1567384352792 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1567384352842 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1567384352844 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4708 " "Peak virtual memory: 4708 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567384353046 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Sep 01 20:32:33 2019 " "Processing ended: Sun Sep 01 20:32:33 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567384353046 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567384353046 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567384353046 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1567384353046 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1567384353861 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567384353861 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Sep 01 20:32:33 2019 " "Processing started: Sun Sep 01 20:32:33 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567384353861 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1567384353861 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1567384353861 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1567384353992 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4520 " "Peak virtual memory: 4520 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567384354129 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Sep 01 20:32:34 2019 " "Processing ended: Sun Sep 01 20:32:34 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567384354129 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567384354129 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567384354129 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1567384354129 ""} +{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1567384354733 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1567384355080 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567384355080 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Sep 01 20:32:34 2019 " "Processing started: Sun Sep 01 20:32:34 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567384355080 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1567384355080 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1567384355080 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1567384355139 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1567384355239 ""} +{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1567384355247 ""} +{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1567384355250 ""} +{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." { } { } 0 335095 "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." 0 0 "Quartus II" 0 -1 1567384355277 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1567384355297 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1567384355297 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M C7M " "create_clock -period 1.000 -name C7M C7M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567384355298 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M_2 C7M_2 " "create_clock -period 1.000 -name C7M_2 C7M_2" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567384355298 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567384355298 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1567384355301 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1567384355316 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -21.000 " "Worst-case setup slack is -21.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567384355319 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567384355319 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -21.000 -840.000 C7M " " -21.000 -840.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567384355319 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -14.500 -20.000 C7M_2 " " -14.500 -20.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567384355319 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567384355319 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold -1.500 " "Worst-case hold slack is -1.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567384355326 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567384355326 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.500 -3.000 C7M_2 " " -1.500 -3.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567384355326 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 5.000 0.000 C7M " " 5.000 0.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567384355326 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567384355326 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567384355329 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567384355332 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -5.500 " "Worst-case minimum pulse width slack is -5.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567384355335 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567384355335 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.500 -22.000 C7M_2 " " -5.500 -22.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567384355335 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.500 -432.000 C7M " " -4.500 -432.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567384355335 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567384355335 ""} +{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1567384355402 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1567384355438 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1567384355438 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4530 " "Peak virtual memory: 4530 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567384355509 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Sep 01 20:32:35 2019 " "Processing ended: Sun Sep 01 20:32:35 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567384355509 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567384355509 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567384355509 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567384355509 ""} +{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 19 s " "Quartus II Full Compilation was successful. 0 errors, 19 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567384356160 ""} diff --git a/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt b/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt index 3982b9f..87e67ad 100755 Binary files a/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt and b/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt differ diff --git a/cpld/output_files/GR8RAM.asm.rpt b/cpld/output_files/GR8RAM.asm.rpt index ac3ea9d..5a62e13 100755 --- a/cpld/output_files/GR8RAM.asm.rpt +++ b/cpld/output_files/GR8RAM.asm.rpt @@ -1,6 +1,6 @@ Assembler report for GR8RAM -Sat Aug 31 22:53:42 2019 -Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +Sun Sep 01 20:44:16 2019 +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition --------------------- @@ -10,7 +10,7 @@ Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit 2. Assembler Summary 3. Assembler Settings 4. Assembler Generated Files - 5. Assembler Device Options: Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pof + 5. Assembler Device Options: C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.pof 6. Assembler Messages @@ -37,7 +37,7 @@ applicable agreement for further details. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Sat Aug 31 22:53:42 2019 ; +; Assembler Status ; Successful - Sun Sep 01 20:44:16 2019 ; ; Revision Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ; ; Family ; MAX7000S ; @@ -73,39 +73,39 @@ applicable agreement for further details. +-----------------------------------------------------------------------------+----------+---------------+ -+----------------------------------------------+ -; Assembler Generated Files ; -+----------------------------------------------+ -; File Name ; -+----------------------------------------------+ -; Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pof ; -+----------------------------------------------+ ++--------------------------------------------------------------------+ +; Assembler Generated Files ; ++--------------------------------------------------------------------+ +; File Name ; ++--------------------------------------------------------------------+ +; C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.pof ; ++--------------------------------------------------------------------+ -+------------------------------------------------------------------------+ -; Assembler Device Options: Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pof ; -+----------------+-------------------------------------------------------+ -; Option ; Setting ; -+----------------+-------------------------------------------------------+ -; Device ; EPM7128SLC84-15 ; -; JTAG usercode ; 0x00000000 ; -; Checksum ; 0x001862DC ; -+----------------+-------------------------------------------------------+ ++----------------------------------------------------------------------------------------------+ +; Assembler Device Options: C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.pof ; ++----------------+-----------------------------------------------------------------------------+ +; Option ; Setting ; ++----------------+-----------------------------------------------------------------------------+ +; Device ; EPM7128SLC84-15 ; +; JTAG usercode ; 0x00000000 ; +; Checksum ; 0x0017B91B ; ++----------------+-----------------------------------------------------------------------------+ +--------------------+ ; Assembler Messages ; +--------------------+ Info: ******************************************************************* -Info: Running Quartus II 32-bit Assembler +Info: Running Quartus II 64-Bit Assembler Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - Info: Processing started: Sat Aug 31 22:53:40 2019 + Info: Processing started: Sun Sep 01 20:44:16 2019 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM Info (115030): Assembler is generating device programming files -Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 277 megabytes - Info: Processing ended: Sat Aug 31 22:53:43 2019 - Info: Elapsed time: 00:00:03 - Info: Total CPU time (on all processors): 00:00:02 +Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 4520 megabytes + Info: Processing ended: Sun Sep 01 20:44:16 2019 + Info: Elapsed time: 00:00:00 + Info: Total CPU time (on all processors): 00:00:00 diff --git a/cpld/output_files/GR8RAM.cdf b/cpld/output_files/GR8RAM.cdf new file mode 100644 index 0000000..f371835 --- /dev/null +++ b/cpld/output_files/GR8RAM.cdf @@ -0,0 +1,13 @@ +/* Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition */ +JedecChain; + FileRevision(JESD32A); + DefaultMfr(6E); + + P ActionCode(Cfg) + Device PartName(EPM7128SL84) Path("C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/") File("GR8RAM.pof") MfrSpec(OpMask(3)); + +ChainEnd; + +AlteraBegin; + ChainType(JTAG); +AlteraEnd; diff --git a/cpld/output_files/GR8RAM.done b/cpld/output_files/GR8RAM.done index 5a51568..a116b4b 100755 --- a/cpld/output_files/GR8RAM.done +++ b/cpld/output_files/GR8RAM.done @@ -1 +1 @@ -Sat Aug 31 22:53:52 2019 +Sun Sep 01 20:44:18 2019 diff --git a/cpld/output_files/GR8RAM.fit.rpt b/cpld/output_files/GR8RAM.fit.rpt index 4f13624..de8542e 100755 --- a/cpld/output_files/GR8RAM.fit.rpt +++ b/cpld/output_files/GR8RAM.fit.rpt @@ -1,6 +1,6 @@ Fitter report for GR8RAM -Sat Aug 31 22:53:38 2019 -Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +Sun Sep 01 20:44:15 2019 +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition --------------------- @@ -9,26 +9,27 @@ Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit 1. Legal Notice 2. Fitter Summary 3. Fitter Settings - 4. Pin-Out File - 5. Fitter Resource Usage Summary - 6. Input Pins - 7. Output Pins - 8. Bidir Pins - 9. All Package Pins - 10. I/O Standard - 11. Dedicated Inputs I/O - 12. Output Pin Default Load For Reported TCO - 13. Fitter Resource Utilization by Entity - 14. Control Signals - 15. Global & Other Fast Signals - 16. Non-Global High Fan-Out Signals - 17. Other Routing Usage Summary - 18. LAB External Interconnect - 19. LAB Macrocells - 20. Shareable Expander - 21. Logic Cell Interconnection - 22. Fitter Device Options - 23. Fitter Messages + 4. Parallel Compilation + 5. Pin-Out File + 6. Fitter Resource Usage Summary + 7. Input Pins + 8. Output Pins + 9. Bidir Pins + 10. All Package Pins + 11. I/O Standard + 12. Dedicated Inputs I/O + 13. Output Pin Default Load For Reported TCO + 14. Fitter Resource Utilization by Entity + 15. Control Signals + 16. Global & Other Fast Signals + 17. Non-Global High Fan-Out Signals + 18. Other Routing Usage Summary + 19. LAB External Interconnect + 20. LAB Macrocells + 21. Shareable Expander + 22. Logic Cell Interconnection + 23. Fitter Device Options + 24. Fitter Messages @@ -54,14 +55,14 @@ applicable agreement for further details. +-----------------------------------------------------------------------------+ ; Fitter Summary ; +---------------------------+-------------------------------------------------+ -; Fitter Status ; Successful - Sat Aug 31 22:53:38 2019 ; -; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; +; Fitter Status ; Successful - Sun Sep 01 20:44:15 2019 ; +; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; ; Revision Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ; ; Family ; MAX7000S ; ; Device ; EPM7128SLC84-15 ; ; Timing Models ; Final ; -; Total macrocells ; 96 / 128 ( 75 % ) ; +; Total macrocells ; 102 / 128 ( 80 % ) ; ; Total pins ; 67 / 68 ( 99 % ) ; +---------------------------+-------------------------------------------------+ @@ -86,33 +87,44 @@ applicable agreement for further details. +----------------------------------------------------------------------------+-----------------------+---------------+ +Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. ++-------------------------------------+ +; Parallel Compilation ; ++----------------------------+--------+ +; Processors ; Number ; ++----------------------------+--------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 1 ; ++----------------------------+--------+ + + +--------------+ ; Pin-Out File ; +--------------+ -The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin. +The pin-out file can be found in C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.pin. -+--------------------------------------------------+ -; Fitter Resource Usage Summary ; -+------------------------------+-------------------+ -; Resource ; Usage ; -+------------------------------+-------------------+ -; Logic cells ; 96 / 128 ( 75 % ) ; -; Registers ; 48 / 128 ( 38 % ) ; -; Number of pterms used ; 255 ; -; I/O pins ; 67 / 68 ( 99 % ) ; -; -- Clock pins ; 2 / 2 ( 100 % ) ; -; -- Dedicated input pins ; 2 / 2 ( 100 % ) ; -; ; ; -; Global signals ; 2 ; -; Shareable expanders ; 10 / 128 ( 8 % ) ; -; Parallel expanders ; 0 / 120 ( 0 % ) ; -; Cells using turbo bit ; 96 / 128 ( 75 % ) ; -; Maximum fan-out ; 50 ; -; Highest non-global fan-out ; 45 ; -; Total fan-out ; 1124 ; -; Average fan-out ; 6.50 ; -+------------------------------+-------------------+ ++---------------------------------------------------+ +; Fitter Resource Usage Summary ; ++------------------------------+--------------------+ +; Resource ; Usage ; ++------------------------------+--------------------+ +; Logic cells ; 102 / 128 ( 80 % ) ; +; Registers ; 50 / 128 ( 39 % ) ; +; Number of pterms used ; 250 ; +; I/O pins ; 67 / 68 ( 99 % ) ; +; -- Clock pins ; 2 / 2 ( 100 % ) ; +; -- Dedicated input pins ; 2 / 2 ( 100 % ) ; +; ; ; +; Global signals ; 2 ; +; Shareable expanders ; 5 / 128 ( 4 % ) ; +; Parallel expanders ; 0 / 120 ( 0 % ) ; +; Cells using turbo bit ; 41 / 128 ( 32 % ) ; +; Maximum fan-out ; 50 ; +; Highest non-global fan-out ; 48 ; +; Total fan-out ; 993 ; +; Average fan-out ; 5.71 ; ++------------------------------+--------------------+ +-----------------------------------------------------------------------------------------------------------------------------------------------+ @@ -120,33 +132,33 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin. +---------+-------+----------+-----+-----------------------+--------------------+--------+----------------+--------------+----------------------+ ; Name ; Pin # ; I/O Bank ; LAB ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; I/O Standard ; Location assigned by ; +---------+-------+----------+-----+-----------------------+--------------------+--------+----------------+--------------+----------------------+ -; A[0] ; 75 ; -- ; 8 ; 33 ; 0 ; no ; no ; TTL ; User ; +; A[0] ; 75 ; -- ; 8 ; 15 ; 0 ; no ; no ; TTL ; User ; ; A[10] ; 11 ; -- ; 1 ; 1 ; 0 ; no ; no ; TTL ; User ; -; A[11] ; 12 ; -- ; 1 ; 1 ; 0 ; no ; no ; TTL ; User ; -; A[12] ; 15 ; -- ; 2 ; 1 ; 0 ; no ; no ; TTL ; User ; -; A[13] ; 16 ; -- ; 2 ; 1 ; 0 ; no ; no ; TTL ; User ; -; A[14] ; 17 ; -- ; 2 ; 1 ; 0 ; no ; no ; TTL ; User ; -; A[15] ; 18 ; -- ; 2 ; 1 ; 0 ; no ; no ; TTL ; User ; -; A[1] ; 76 ; -- ; 8 ; 33 ; 0 ; no ; no ; TTL ; User ; -; A[2] ; 77 ; -- ; 8 ; 33 ; 0 ; no ; no ; TTL ; User ; -; A[3] ; 79 ; -- ; 8 ; 33 ; 0 ; no ; no ; TTL ; User ; +; A[11] ; 12 ; -- ; 1 ; 0 ; 0 ; no ; no ; TTL ; User ; +; A[12] ; 15 ; -- ; 2 ; 0 ; 0 ; no ; no ; TTL ; User ; +; A[13] ; 16 ; -- ; 2 ; 0 ; 0 ; no ; no ; TTL ; User ; +; A[14] ; 17 ; -- ; 2 ; 0 ; 0 ; no ; no ; TTL ; User ; +; A[15] ; 18 ; -- ; 2 ; 0 ; 0 ; no ; no ; TTL ; User ; +; A[1] ; 76 ; -- ; 8 ; 15 ; 0 ; no ; no ; TTL ; User ; +; A[2] ; 77 ; -- ; 8 ; 15 ; 0 ; no ; no ; TTL ; User ; +; A[3] ; 79 ; -- ; 8 ; 15 ; 0 ; no ; no ; TTL ; User ; ; A[4] ; 80 ; -- ; 8 ; 1 ; 0 ; no ; no ; TTL ; User ; ; A[5] ; 81 ; -- ; 8 ; 1 ; 0 ; no ; no ; TTL ; User ; ; A[6] ; 4 ; -- ; 1 ; 1 ; 0 ; no ; no ; TTL ; User ; ; A[7] ; 5 ; -- ; 1 ; 1 ; 0 ; no ; no ; TTL ; User ; ; A[8] ; 9 ; -- ; 1 ; 1 ; 0 ; no ; no ; TTL ; User ; ; A[9] ; 10 ; -- ; 1 ; 1 ; 0 ; no ; no ; TTL ; User ; -; C7M ; 83 ; -- ; -- ; 46 ; 0 ; yes ; no ; TTL ; User ; +; C7M ; 83 ; -- ; -- ; 48 ; 0 ; yes ; no ; TTL ; User ; ; C7M_2 ; 84 ; -- ; -- ; 3 ; 0 ; no ; no ; TTL ; User ; -; MODE ; 44 ; -- ; 5 ; 1 ; 0 ; no ; no ; TTL ; User ; +; MODE ; 44 ; -- ; 5 ; 0 ; 0 ; no ; no ; TTL ; User ; ; PHI0in ; 8 ; -- ; 1 ; 0 ; 0 ; no ; no ; TTL ; User ; ; PHI1in ; 2 ; -- ; -- ; 2 ; 0 ; no ; no ; TTL ; User ; ; Q3 ; 6 ; -- ; 1 ; 0 ; 0 ; no ; no ; TTL ; User ; -; nDEVSEL ; 21 ; -- ; 2 ; 45 ; 0 ; no ; no ; TTL ; User ; -; nIOSEL ; 74 ; -- ; 8 ; 6 ; 0 ; no ; no ; TTL ; User ; -; nIOSTRB ; 24 ; -- ; 3 ; 5 ; 0 ; no ; no ; TTL ; User ; +; nDEVSEL ; 21 ; -- ; 2 ; 18 ; 0 ; no ; no ; TTL ; User ; +; nIOSEL ; 74 ; -- ; 8 ; 13 ; 0 ; no ; no ; TTL ; User ; +; nIOSTRB ; 24 ; -- ; 3 ; 12 ; 0 ; no ; no ; TTL ; User ; ; nRES ; 1 ; -- ; -- ; 50 ; 0 ; yes ; no ; TTL ; User ; -; nWE ; 20 ; -- ; 2 ; 26 ; 0 ; no ; no ; TTL ; User ; +; nWE ; 20 ; -- ; 2 ; 11 ; 0 ; no ; no ; TTL ; User ; +---------+-------+----------+-----+-----------------------+--------------------+--------+----------------+--------------+----------------------+ @@ -183,22 +195,22 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin. +-------+-------+----------+-----+-----------------------+--------------------+--------+----------------+-----------------+----------------+------------+--------------+----------------------+-------+----------------------+---------------------+ ; Name ; Pin # ; I/O Bank ; LAB ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Output Register ; Slow Slew Rate ; Open Drain ; I/O Standard ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ; +-------+-------+----------+-----+-----------------------+--------------------+--------+----------------+-----------------+----------------+------------+--------------+----------------------+-------+----------------------+---------------------+ -; D[0] ; 36 ; -- ; 4 ; 5 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; DOE~11 ; - ; -; D[1] ; 35 ; -- ; 4 ; 5 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; DOE~11 ; - ; -; D[2] ; 34 ; -- ; 4 ; 5 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; DOE~11 ; - ; -; D[3] ; 33 ; -- ; 4 ; 5 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; DOE~11 ; - ; -; D[4] ; 29 ; -- ; 3 ; 5 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; DOE~11 ; - ; -; D[5] ; 28 ; -- ; 3 ; 5 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; DOE~11 ; - ; -; D[6] ; 27 ; -- ; 3 ; 5 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; DOE~11 ; - ; -; D[7] ; 25 ; -- ; 3 ; 3 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; DOE~11 ; - ; -; RD[0] ; 73 ; -- ; 8 ; 1 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; RDOE~11 ; - ; -; RD[1] ; 70 ; -- ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; RDOE~11 ; - ; -; RD[2] ; 69 ; -- ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; RDOE~11 ; - ; -; RD[3] ; 68 ; -- ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; RDOE~11 ; - ; -; RD[4] ; 65 ; -- ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; RDOE~11 ; - ; -; RD[5] ; 63 ; -- ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; RDOE~11 ; - ; -; RD[6] ; 64 ; -- ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; RDOE~11 ; - ; -; RD[7] ; 61 ; -- ; 6 ; 1 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; RDOE~11 ; - ; +; D[0] ; 36 ; -- ; 4 ; 6 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; DOE~5 ; - ; +; D[1] ; 35 ; -- ; 4 ; 6 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; DOE~5 ; - ; +; D[2] ; 34 ; -- ; 4 ; 6 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; DOE~5 ; - ; +; D[3] ; 33 ; -- ; 4 ; 6 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; DOE~5 ; - ; +; D[4] ; 29 ; -- ; 3 ; 5 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; DOE~5 ; - ; +; D[5] ; 28 ; -- ; 3 ; 5 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; DOE~5 ; - ; +; D[6] ; 27 ; -- ; 3 ; 5 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; DOE~5 ; - ; +; D[7] ; 25 ; -- ; 3 ; 5 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; DOE~5 ; - ; +; RD[0] ; 73 ; -- ; 8 ; 1 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; RDOE~1 ; - ; +; RD[1] ; 70 ; -- ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; RDOE~1 ; - ; +; RD[2] ; 69 ; -- ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; RDOE~1 ; - ; +; RD[3] ; 68 ; -- ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; RDOE~1 ; - ; +; RD[4] ; 65 ; -- ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; RDOE~1 ; - ; +; RD[5] ; 63 ; -- ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; RDOE~1 ; - ; +; RD[6] ; 64 ; -- ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; RDOE~1 ; - ; +; RD[7] ; 61 ; -- ; 6 ; 1 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; RDOE~1 ; - ; +-------+-------+----------+-----+-----------------------+--------------------+--------+----------------+-----------------+----------------+------------+--------------+----------------------+-------+----------------------+---------------------+ @@ -333,7 +345,7 @@ Note: User assignments will override these defaults. The user specified values a +----------------------------+------------+------+-------------------------------+--------------+ ; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ; Library Name ; +----------------------------+------------+------+-------------------------------+--------------+ -; |GR8RAM ; 96 ; 67 ; |GR8RAM ; work ; +; |GR8RAM ; 102 ; 67 ; |GR8RAM ; work ; ; |lpm_counter:Ref_rtl_0| ; 4 ; 0 ; |GR8RAM|lpm_counter:Ref_rtl_0 ; work ; +----------------------------+------------+------+-------------------------------+--------------+ @@ -343,16 +355,23 @@ Note: User assignments will override these defaults. The user specified values a +-----------+----------+---------+--------------+--------+----------------------+------------------+ ; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; +-----------+----------+---------+--------------+--------+----------------------+------------------+ -; Addr~481 ; SEXP115 ; 4 ; Clock enable ; no ; -- ; -- ; -; BankWR_MC ; LC55 ; 7 ; Clock enable ; no ; -- ; -- ; -; C7M ; PIN_83 ; 46 ; Clock ; yes ; On ; -- ; +; A[0] ; PIN_75 ; 15 ; Clock enable ; no ; -- ; -- ; +; A[1] ; PIN_76 ; 15 ; Clock enable ; no ; -- ; -- ; +; A[2] ; PIN_77 ; 15 ; Clock enable ; no ; -- ; -- ; +; A[3] ; PIN_79 ; 15 ; Clock enable ; no ; -- ; -- ; +; BankWR_MC ; LC111 ; 8 ; Clock enable ; no ; -- ; -- ; +; C7M ; PIN_83 ; 48 ; Clock ; yes ; On ; -- ; ; C7M_2 ; PIN_84 ; 3 ; Clock ; no ; -- ; -- ; -; PHI1b7_MC ; LC37 ; 6 ; Clock enable ; no ; -- ; -- ; -; S[0] ; LC18 ; 40 ; Clock enable ; no ; -- ; -- ; -; S[1] ; LC27 ; 41 ; Clock enable ; no ; -- ; -- ; -; S[2] ; LC24 ; 42 ; Clock enable ; no ; -- ; -- ; -; nIOSEL ; PIN_74 ; 6 ; Clock enable ; no ; -- ; -- ; +; PHI1b9_MC ; LC37 ; 6 ; Clock enable ; no ; -- ; -- ; +; RAMSELreg ; LC34 ; 24 ; Clock enable ; no ; -- ; -- ; +; REGEN ; LC41 ; 7 ; Clock enable ; no ; -- ; -- ; +; S[0] ; LC113 ; 46 ; Clock enable ; no ; -- ; -- ; +; S[1] ; LC117 ; 47 ; Clock enable ; no ; -- ; -- ; +; S[2] ; LC122 ; 48 ; Clock enable ; no ; -- ; -- ; +; nDEVSEL ; PIN_21 ; 18 ; Clock enable ; no ; -- ; -- ; +; nIOSEL ; PIN_74 ; 13 ; Clock enable ; no ; -- ; -- ; ; nRES ; PIN_1 ; 50 ; Async. clear ; yes ; On ; -- ; +; nWE ; PIN_20 ; 11 ; Clock enable ; no ; -- ; -- ; +-----------+----------+---------+--------------+--------+----------------------+------------------+ @@ -361,7 +380,7 @@ Note: User assignments will override these defaults. The user specified values a +------+----------+---------+----------------------+------------------+ ; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; +------+----------+---------+----------------------+------------------+ -; C7M ; PIN_83 ; 46 ; On ; -- ; +; C7M ; PIN_83 ; 48 ; On ; -- ; ; nRES ; PIN_1 ; 50 ; On ; -- ; +------+----------+---------+----------------------+------------------+ @@ -371,64 +390,72 @@ Note: User assignments will override these defaults. The user specified values a +-------------------------------+---------+ ; Name ; Fan-Out ; +-------------------------------+---------+ -; nDEVSEL ; 45 ; -; S[2] ; 42 ; -; S[1] ; 41 ; -; S[0] ; 40 ; -; A[3] ; 33 ; -; A[2] ; 33 ; -; A[0] ; 33 ; -; A[1] ; 33 ; -; Addr[0] ; 33 ; -; Addr[1] ; 32 ; -; Addr[2] ; 31 ; -; Addr[3] ; 30 ; -; Addr[4] ; 29 ; -; Addr[5] ; 28 ; -; Addr[6] ; 27 ; -; nWE ; 26 ; -; Addr[7] ; 26 ; -; REGEN ; 25 ; -; Addr[8] ; 24 ; -; always0~15 ; 23 ; -; Addr[9] ; 22 ; -; Addr[10] ; 20 ; -; Addr[11] ; 18 ; -; Addr[12] ; 16 ; -; Addr[13] ; 14 ; -; Addr[14] ; 12 ; +; S[2] ; 48 ; +; S[1] ; 47 ; +; S[0] ; 46 ; +; Addr[0] ; 25 ; +; Addr[1] ; 24 ; +; RAMSELreg ; 24 ; +; Addr[2] ; 23 ; +; Addr[3] ; 22 ; +; Addr[4] ; 21 ; +; Addr[5] ; 20 ; +; Addr[6] ; 19 ; +; nDEVSEL ; 18 ; +; Addr[7] ; 18 ; +; Addr[8] ; 17 ; +; Addr[9] ; 16 ; +; A[3] ; 15 ; +; A[2] ; 15 ; +; A[1] ; 15 ; +; A[0] ; 15 ; +; Addr[10] ; 15 ; +; Addr[11] ; 14 ; +; nIOSEL ; 13 ; +; Addr[12] ; 13 ; +; Bank[0] ; 13 ; +; nIOSTRB ; 12 ; +; Addr[13] ; 12 ; +; Bank[1] ; 12 ; +; nWE ; 11 ; +; Addr[14] ; 11 ; +; Bank[2] ; 11 ; ; ASel ; 11 ; ; Addr[15] ; 10 ; -; RAMSELreg ; 10 ; +; Bank[3] ; 9 ; ; Addr[16] ; 9 ; +; IOBank0 ; 8 ; ; Addr[17] ; 8 ; -; Addr~430 ; 8 ; -; RDOE~11 ; 8 ; -; DOE~11 ; 8 ; +; BankWR_MC ; 8 ; +; AddrLWR_MC ; 8 ; +; AddrMWR_MC ; 8 ; +; RDOE~1 ; 8 ; +; DOE~5 ; 8 ; +; Bank[4] ; 7 ; ; Addr[18] ; 7 ; -; BankWR_MC ; 7 ; -; nIOSEL ; 6 ; +; REGEN ; 7 ; +; D[3]~3 ; 6 ; +; D[2]~2 ; 6 ; +; D[1]~1 ; 6 ; +; D[0]~0 ; 6 ; ; Addr[19] ; 6 ; ; lpm_counter:Ref_rtl_0|dffs[3] ; 6 ; ; lpm_counter:Ref_rtl_0|dffs[2] ; 6 ; ; lpm_counter:Ref_rtl_0|dffs[0] ; 6 ; -; PHI1b7_MC ; 6 ; +; PHI1b9_MC ; 6 ; +; D[7]~7 ; 5 ; ; D[6]~6 ; 5 ; ; D[5]~5 ; 5 ; ; D[4]~4 ; 5 ; -; D[3]~3 ; 5 ; -; D[2]~2 ; 5 ; -; D[1]~1 ; 5 ; -; D[0]~0 ; 5 ; -; nIOSTRB ; 5 ; -; Addr[20] ; 5 ; +; Bank[5] ; 5 ; +; RAMSEL_MC ; 5 ; ; lpm_counter:Ref_rtl_0|dffs[1] ; 5 ; -; Addr[22] ; 4 ; -; Addr[21] ; 4 ; -; Addr~481 ; 4 ; -; Addr~464 ; 4 ; -; D[7]~7 ; 3 ; +; Addr[20] ; 4 ; +; AddrHWR_MC ; 4 ; ; C7M_2 ; 3 ; +; Bank[6] ; 3 ; +; Addr[22] ; 3 ; +; Addr[21] ; 3 ; ; IOROMEN ; 3 ; ; CSDBEN ; 3 ; ; PHI0seen ; 3 ; @@ -444,11 +471,6 @@ Note: User assignments will override these defaults. The user specified values a ; RD[2]~2 ; 1 ; ; RD[1]~1 ; 1 ; ; RD[0]~0 ; 1 ; -; A[13] ; 1 ; -; A[12] ; 1 ; -; A[15] ; 1 ; -; A[14] ; 1 ; -; MODE ; 1 ; ; A[10] ; 1 ; ; A[9] ; 1 ; ; A[8] ; 1 ; @@ -456,66 +478,58 @@ Note: User assignments will override these defaults. The user specified values a ; A[6] ; 1 ; ; A[5] ; 1 ; ; A[4] ; 1 ; -; A[11] ; 1 ; -; RA~138 ; 1 ; -; RA~134 ; 1 ; -; Bank[0] ; 1 ; -; RA~130 ; 1 ; -; RA~126 ; 1 ; -; RA~122 ; 1 ; -; Bank[6] ; 1 ; -; comb~63 ; 1 ; -; comb~59 ; 1 ; -; RA~118 ; 1 ; -; RA~114 ; 1 ; -; Addr~532 ; 1 ; -; Bank[5] ; 1 ; +; ~VCC~0 ; 1 ; ; RA~111 ; 1 ; -; Addr~525 ; 1 ; -; RA~107 ; 1 ; -; Addr~518 ; 1 ; -; Addr~511 ; 1 ; -; Bank[4] ; 1 ; -; RA~103 ; 1 ; -; Bank[3] ; 1 ; +; RA~106 ; 1 ; +; RA~105 ; 1 ; ; RA~100 ; 1 ; -; Bank[2] ; 1 ; -; Addr~456 ; 1 ; -; Bank[1] ; 1 ; -; Addr~449 ; 1 ; -; comb~56 ; 1 ; +; RA~99 ; 1 ; +; RA~94 ; 1 ; +; RA~93 ; 1 ; +; RA~88 ; 1 ; +; RA~87 ; 1 ; +; RA~82 ; 1 ; +; RA~81 ; 1 ; +; RA~75 ; 1 ; +; RA~70 ; 1 ; +; Bank[7] ; 1 ; +; comb~55 ; 1 ; +; comb~51 ; 1 ; +; RA~66 ; 1 ; +; RA~63 ; 1 ; +; RA~60 ; 1 ; +; comb~48 ; 1 ; ; RASf ; 1 ; -; Addr~443 ; 1 ; -; Addr~431 ; 1 ; -; comb~54 ; 1 ; ; RASr ; 1 ; +; comb~46 ; 1 ; +; PHI1b8_MC ; 1 ; +; PHI1b7_MC ; 1 ; ; PHI1b6_MC ; 1 ; ; PHI1b5_MC ; 1 ; ; PHI1b4_MC ; 1 ; ; PHI1b3_MC ; 1 ; -; AROMSEL_MC ; 1 ; ; PHI1b2_MC ; 1 ; -; comb~50 ; 1 ; +; comb~42 ; 1 ; ; PHI1b1_MC ; 1 ; -; C7M_2~4 ; 1 ; -; nWE~4 ; 1 ; +; C7M_2~1 ; 1 ; +; nWE~1 ; 1 ; ; PHI1b0_MC ; 1 ; -; D[7]~83 ; 1 ; -; D[6]~81 ; 1 ; -; D[5]~79 ; 1 ; -; D[4]~77 ; 1 ; -; D[3]~75 ; 1 ; -; D[2]~73 ; 1 ; -; D[1]~71 ; 1 ; -; D[0]~69 ; 1 ; -; Dout[7]~161 ; 1 ; -; Dout[6]~155 ; 1 ; -; Dout[5]~149 ; 1 ; -; Dout[4]~143 ; 1 ; -; Dout[3]~137 ; 1 ; -; Dout[2]~131 ; 1 ; -; Dout[1]~125 ; 1 ; -; Dout[0]~119 ; 1 ; +; D[7]~38 ; 1 ; +; D[6]~36 ; 1 ; +; D[5]~34 ; 1 ; +; D[4]~32 ; 1 ; +; D[3]~30 ; 1 ; +; D[2]~28 ; 1 ; +; D[1]~26 ; 1 ; +; D[0]~24 ; 1 ; +; Dout[7]~95 ; 1 ; +; Dout[6]~89 ; 1 ; +; Dout[5]~83 ; 1 ; +; Dout[4]~77 ; 1 ; +; Dout[3]~71 ; 1 ; +; Dout[2]~65 ; 1 ; +; Dout[1]~59 ; 1 ; +; Dout[0]~53 ; 1 ; +-------------------------------+---------+ @@ -525,33 +539,35 @@ Note: User assignments will override these defaults. The user specified values a ; Other Routing Resource Type ; Usage ; +-----------------------------+--------------------+ ; Output enables ; 2 / 6 ( 33 % ) ; -; PIA buffers ; 210 / 288 ( 73 % ) ; -; PIAs ; 254 / 288 ( 88 % ) ; +; PIA buffers ; 198 / 288 ( 69 % ) ; +; PIAs ; 228 / 288 ( 79 % ) ; +-----------------------------+--------------------+ +-----------------------------------------------------------------------------+ ; LAB External Interconnect ; +-----------------------------------------------+-----------------------------+ -; LAB External Interconnects (Average = 31.75) ; Number of LABs (Total = 8) ; +; LAB External Interconnects (Average = 28.50) ; Number of LABs (Total = 8) ; +-----------------------------------------------+-----------------------------+ -; 0 - 3 ; 0 ; -; 4 - 7 ; 0 ; -; 8 - 11 ; 0 ; -; 12 - 15 ; 0 ; -; 16 - 19 ; 0 ; -; 20 - 23 ; 0 ; -; 24 - 27 ; 1 ; -; 28 - 31 ; 2 ; -; 32 - 35 ; 4 ; -; 36 - 39 ; 1 ; +; 0 - 2 ; 0 ; +; 3 - 5 ; 0 ; +; 6 - 8 ; 0 ; +; 9 - 11 ; 0 ; +; 12 - 14 ; 0 ; +; 15 - 17 ; 0 ; +; 18 - 20 ; 1 ; +; 21 - 23 ; 0 ; +; 24 - 26 ; 0 ; +; 27 - 29 ; 3 ; +; 30 - 32 ; 3 ; +; 33 - 35 ; 1 ; +-----------------------------------------------+-----------------------------+ +-----------------------------------------------------------------------+ ; LAB Macrocells ; +-----------------------------------------+-----------------------------+ -; Number of Macrocells (Average = 12.00) ; Number of LABs (Total = 8) ; +; Number of Macrocells (Average = 12.75) ; Number of LABs (Total = 8) ; +-----------------------------------------+-----------------------------+ ; 0 ; 0 ; ; 1 ; 0 ; @@ -560,14 +576,14 @@ Note: User assignments will override these defaults. The user specified values a ; 4 ; 0 ; ; 5 ; 0 ; ; 6 ; 0 ; -; 7 ; 1 ; -; 8 ; 1 ; +; 7 ; 0 ; +; 8 ; 2 ; ; 9 ; 0 ; -; 10 ; 2 ; -; 11 ; 0 ; +; 10 ; 0 ; +; 11 ; 1 ; ; 12 ; 0 ; ; 13 ; 1 ; -; 14 ; 0 ; +; 14 ; 1 ; ; 15 ; 0 ; ; 16 ; 3 ; +-----------------------------------------+-----------------------------+ @@ -576,123 +592,123 @@ Note: User assignments will override these defaults. The user specified values a +-------------------------------------------------------------------------------+ ; Shareable Expander ; +-------------------------------------------------+-----------------------------+ -; Number of shareable expanders (Average = 1.25) ; Number of LABs (Total = 2) ; +; Number of shareable expanders (Average = 0.63) ; Number of LABs (Total = 2) ; +-------------------------------------------------+-----------------------------+ ; 0 ; 6 ; -; 1 ; 1 ; -; 2 ; 0 ; -; 3 ; 0 ; -; 4 ; 0 ; -; 5 ; 0 ; -; 6 ; 0 ; -; 7 ; 0 ; -; 8 ; 0 ; -; 9 ; 1 ; +; 1 ; 0 ; +; 2 ; 1 ; +; 3 ; 1 ; +-------------------------------------------------+-----------------------------+ -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Logic Cell Interconnection ; -+-----+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; LAB ; Logic Cell ; Input ; Output ; -+-----+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; A ; LC13 ; C7M, nRES, Addr[11], Addr[10], Addr[9], Addr[8], Addr[2], Addr[3], Addr[6], Addr[7], Addr[0], Addr[1], Addr[4], Addr[5], always0~15, Addr[12], D[4], S[0], S[2], S[1], nWE, nDEVSEL, REGEN, A[1], A[0], A[2], A[3], Addr~511, Addr~430, RAMSELreg ; Dout[4]~143, Addr[17], Addr[18], Addr[19], Addr[20], Addr[12], Addr~518, Addr[13], Addr~525, Addr[14], Addr~532, Addr[15], Addr[21], Addr[22], Addr[16], RA~134 ; -; A ; LC1 ; C7M, nRES, S[0], S[1], S[2], A[1], A[0], A[2], A[3], nWE, nDEVSEL, REGEN, D[0], Addr[0], RAMSELreg ; Dout[0]~119, Addr~431, Addr[8], Addr[1], Addr~443, Addr[9], Addr~449, Addr[10], Addr~456, Addr[11], Addr[17], Addr[18], Addr[19], Addr[20], Addr[2], Addr[3], Addr[4], Addr[5], Addr~511, Addr[12], Addr~518, Addr[13], Addr~525, Addr[14], Addr~532, Addr[15], Addr[21], Addr[22], Addr[6], Addr[7], Addr[16], Addr[0], RA~138 ; -; A ; LC10 ; C7M, nRES, Addr[8], Addr[2], Addr[3], Addr[6], Addr[7], Addr[0], Addr[1], Addr[4], Addr[5], always0~15, Addr[9], D[1], S[0], S[2], S[1], nWE, nDEVSEL, REGEN, A[1], A[0], A[2], A[3], Addr~430, Addr~443, RAMSELreg ; Dout[1]~125, Addr[9], Addr~449, Addr[10], Addr~456, Addr[11], Addr[17], Addr[18], Addr[19], Addr[20], RA~103, Addr~511, Addr[12], Addr~518, Addr[13], Addr~525, Addr[14], Addr~532, Addr[15], Addr[21], Addr[22], Addr[16] ; -; A ; LC8 ; C7M, nRES, D[7], always0~15, Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[0], Addr[1], A[1], A[0], A[2], A[3], S[0], S[2], S[1], nWE, nDEVSEL, REGEN ; Dout[7]~161, Addr~431, Addr[8], Addr~443, Addr[9], Addr~449, Addr[10], Addr~456, Addr[11], Addr[17], Addr[18], Addr[19], Addr[20], Addr~511, Addr[12], Addr~518, Addr[13], Addr~525, Addr[14], Addr~532, Addr[15], Addr[21], Addr[22], Addr[7], RA~126, Addr[16] ; -; A ; LC7 ; C7M, nRES, D[6], always0~15, Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[0], Addr[1], A[1], A[0], A[2], A[3], S[0], S[2], S[1], nWE, nDEVSEL, REGEN ; Dout[6]~155, Addr~431, Addr[8], Addr~443, Addr[9], Addr~449, Addr[10], Addr~456, Addr[11], Addr[17], Addr[18], Addr[19], Addr[20], Addr~511, Addr[12], Addr~518, Addr[13], Addr~525, Addr[14], Addr~532, Addr[15], Addr[21], Addr[22], Addr[6], RA~122, Addr[7], Addr[16] ; -; A ; LC3 ; C7M, nRES, D[2], A[1], A[0], A[2], A[3], S[0], S[2], S[1], nWE, nDEVSEL, REGEN, always0~15, Addr[2], Addr[0], Addr[1] ; Dout[2]~131, Addr~431, Addr[8], Addr~443, Addr[9], Addr~449, Addr[10], Addr~456, Addr[11], Addr[17], Addr[18], Addr[19], Addr[20], Addr[2], Addr[3], Addr[4], Addr[5], Addr~511, Addr[12], Addr~518, Addr[13], RA~107, Addr~525, Addr[14], Addr~532, Addr[15], Addr[21], Addr[22], Addr[6], Addr[7], Addr[16] ; -; A ; LC4 ; C7M, nRES, D[3], always0~15, Addr[3], Addr[2], Addr[0], Addr[1], A[1], A[0], A[2], A[3], S[0], S[2], S[1], nWE, nDEVSEL, REGEN ; Dout[3]~137, Addr~431, Addr[8], Addr~443, Addr[9], Addr~449, Addr[10], Addr~456, Addr[11], Addr[17], Addr[18], Addr[19], Addr[20], Addr[3], Addr[4], Addr[5], Addr~511, Addr[12], Addr~518, Addr[13], Addr~525, Addr[14], RA~111, Addr~532, Addr[15], Addr[21], Addr[22], Addr[6], Addr[7], Addr[16] ; -; A ; LC5 ; C7M, nRES, D[4], always0~15, Addr[4], Addr[3], Addr[2], Addr[0], Addr[1], A[1], A[0], A[2], A[3], S[0], S[2], S[1], nWE, nDEVSEL, REGEN ; Dout[4]~143, Addr~431, Addr[8], Addr~443, Addr[9], Addr~449, Addr[10], Addr~456, Addr[11], Addr[17], Addr[18], Addr[19], Addr[20], Addr[4], Addr[5], Addr~511, Addr[12], Addr~518, Addr[13], Addr~525, Addr[14], Addr~532, Addr[15], Addr[21], RA~118, Addr[22], Addr[6], Addr[7], Addr[16] ; -; A ; LC6 ; C7M, nRES, D[5], always0~15, Addr[5], Addr[4], Addr[3], Addr[2], Addr[0], Addr[1], A[1], A[0], A[2], A[3], S[0], S[2], S[1], nWE, nDEVSEL, REGEN ; Dout[5]~149, Addr~431, Addr[8], Addr~443, Addr[9], Addr~449, Addr[10], Addr~456, Addr[11], Addr[17], Addr[18], Addr[19], Addr[20], Addr[5], Addr~511, Addr[12], Addr~518, Addr[13], Addr~525, Addr[14], Addr~532, Addr[15], Addr[21], Addr[22], Addr[6], Addr[7], Addr[16], RA~130 ; -; A ; LC2 ; C7M, nRES, D[1], A[1], A[0], A[2], A[3], S[0], S[2], S[1], nWE, nDEVSEL, REGEN, Addr[1], always0~15, Addr[0] ; Dout[1]~125, Addr~431, Addr[8], Addr[1], Addr~443, Addr[9], Addr~449, Addr[10], Addr~456, Addr[11], Addr[17], Addr[18], Addr[19], Addr[20], Addr[2], Addr[3], Addr[4], Addr[5], Addr~511, Addr[12], Addr~518, Addr[13], Addr~525, Addr[14], Addr~532, Addr[15], Addr[21], Addr[22], Addr[6], Addr[7], Addr[16], RA~134 ; -; A ; LC16 ; C7M, nRES, Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], Addr[2], Addr[3], Addr[6], Addr[7], Addr[0], Addr[1], Addr[4], Addr[5], always0~15, Addr[15], D[7], S[0], S[2], S[1], nWE, nDEVSEL, REGEN, A[1], A[0], A[2], A[3], Addr~532, Addr~430, RAMSELreg ; Dout[7]~161, Addr[17], Addr[18], Addr[19], Addr[20], Addr[15], Addr[21], RA~118, Addr[22], Addr[16] ; -; A ; LC15 ; C7M, nRES, Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], Addr[2], Addr[3], Addr[6], Addr[7], Addr[0], Addr[1], Addr[4], Addr[5], always0~15, Addr[14], D[6], S[0], S[2], S[1], nWE, nDEVSEL, REGEN, A[1], A[0], A[2], A[3], Addr~525, Addr~430, RAMSELreg ; Dout[6]~155, Addr[17], Addr[18], Addr[19], Addr[20], Addr[14], RA~111, Addr~532, Addr[15], Addr[21], Addr[22], Addr[16] ; -; A ; LC14 ; C7M, nRES, Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], Addr[2], Addr[3], Addr[6], Addr[7], Addr[0], Addr[1], Addr[4], Addr[5], always0~15, Addr[13], D[5], S[0], S[2], S[1], nWE, nDEVSEL, REGEN, A[1], A[0], A[2], A[3], Addr~518, Addr~430, RAMSELreg ; Dout[5]~149, Addr[17], Addr[18], Addr[19], Addr[20], Addr[13], RA~107, Addr~525, Addr[14], Addr~532, Addr[15], Addr[21], Addr[22], Addr[16] ; -; A ; LC12 ; C7M, nRES, Addr[10], Addr[9], Addr[8], Addr[2], Addr[3], Addr[6], Addr[7], Addr[0], Addr[1], Addr[4], Addr[5], always0~15, Addr[11], D[3], S[0], S[2], S[1], nWE, nDEVSEL, REGEN, A[1], A[0], A[2], A[3], Addr~456, Addr~430, RAMSELreg ; Dout[3]~137, Addr[11], Addr[17], Addr[18], Addr[19], Addr[20], Addr~511, Addr[12], Addr~518, Addr[13], Addr~525, Addr[14], Addr~532, Addr[15], Addr[21], Addr[22], Addr[16], RA~138 ; -; A ; LC11 ; C7M, nRES, Addr[9], Addr[8], Addr[2], Addr[3], Addr[6], Addr[7], Addr[0], Addr[1], Addr[4], Addr[5], always0~15, Addr[10], D[2], S[0], S[2], S[1], nWE, nDEVSEL, REGEN, A[1], A[0], A[2], A[3], Addr~449, Addr~430, RAMSELreg ; Dout[2]~131, Addr[10], Addr~456, Addr[11], Addr[17], Addr[18], Addr[19], Addr[20], Addr~511, Addr[12], Addr~518, Addr[13], Addr~525, Addr[14], Addr~532, Addr[15], Addr[21], RA~114, Addr[22], Addr[16] ; -; A ; LC9 ; C7M, nRES, Addr[2], Addr[3], Addr[6], Addr[7], Addr[0], Addr[1], Addr[4], Addr[5], always0~15, Addr[8], D[0], S[0], S[2], S[1], nWE, nDEVSEL, REGEN, A[1], A[0], A[2], A[3], Addr~430, Addr~431, RAMSELreg ; Dout[0]~119, Addr[8], Addr~443, Addr[9], Addr~449, Addr[10], Addr~456, Addr[11], Addr[17], Addr[18], Addr[19], RA~100, Addr[20], Addr~511, Addr[12], Addr~518, Addr[13], Addr~525, Addr[14], Addr~532, Addr[15], Addr[21], Addr[22], Addr[16] ; -; B ; LC21 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], CASr, RASf ; -; B ; LC25 ; C7M, nRES, S[1], S[2], nDEVSEL, REGEN, A[1], A[0], A[2], A[3] ; RA~100, RA~103, RA~107, RA~111, RA~114, RA~118, RA~122, RA~126, RA~130, RA~134, RA~138 ; -; B ; LC30 ; C7M, nRES, nIOSEL, S[2], S[1], S[0] ; DOE~11, RAMSELreg, RASr, BankWR_MC, ASel, Addr~430, Addr[8], Addr[1], Addr[9], CASr, RASf, Addr[10], Addr[11], Addr~464, Addr[2], Addr[12], Addr[13], Addr[14], Addr[15], Addr[0], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7] ; -; B ; LC17 ; A[15], MODE, A[14], nWE, A[12], A[13] ; nINH ; -; B ; LC28 ; PHI1b1_MC ; PHI1b3_MC ; -; B ; LC31 ; PHI1b2_MC ; PHI1b4_MC ; -; B ; LC32 ; nIOSEL, nWE, nRES, CSDBEN, IOROMEN, nIOSTRB, nDEVSEL, REGEN ; D[0], D[1], D[2], D[3], D[4], D[5], D[6], D[7] ; -; B ; LC23 ; C7M, nRES, PHI1b7_MC ; S[0], S[2], S[1] ; -; B ; LC20 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[0], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], CASr, RASf ; -; B ; LC18 ; C7M, nRES, PHI1b7_MC, PHI0seen, PHI1reg, S[0], S[2], S[1] ; S[0], S[2], lpm_counter:Ref_rtl_0|dffs[0], REGEN, S[1], lpm_counter:Ref_rtl_0|dffs[1], IOROMEN, RAMSELreg, RASr, CASf, lpm_counter:Ref_rtl_0|dffs[2], Addr~430, always0~15, Addr[8], Addr[1], lpm_counter:Ref_rtl_0|dffs[3], Addr[9], CASr, RASf, Addr[10], Bank[1], Addr[11], Addr~464, Bank[2], Addr[2], Bank[3], Bank[4], Addr[12], Addr[13], Addr[14], Bank[5], Addr[15], Bank[6], Bank[0], Addr[0], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7] ; -; B ; LC24 ; C7M, nRES, PHI1b7_MC, PHI0seen, PHI1reg, S[1], S[2], S[0] ; S[0], S[2], CSDBEN, lpm_counter:Ref_rtl_0|dffs[0], REGEN, S[1], lpm_counter:Ref_rtl_0|dffs[1], IOROMEN, RAMSELreg, RASr, CASf, ASel, lpm_counter:Ref_rtl_0|dffs[2], Addr~430, always0~15, Addr[8], Addr[1], lpm_counter:Ref_rtl_0|dffs[3], Addr[9], CASr, RASf, Addr[10], Bank[1], Addr[11], Addr~464, Bank[2], Addr[2], Bank[3], Bank[4], Addr[12], Addr[13], Addr[14], Bank[5], Addr[15], Bank[6], Bank[0], Addr[0], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7] ; -; B ; LC29 ; S[1], S[0], RAMSELreg, S[2] ; Addr[8], Addr[1], Addr[9], Addr[10], Addr[11], Addr[17], Addr[18], Addr[19], Addr~481, Addr[20], Addr[2], Addr[3], Addr[4], Addr[5], Addr[12], Addr[13], Addr[14], Addr[15], Addr[21], Addr[22], Addr[6], Addr[7], Addr[16] ; -; B ; LC26 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[0], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], CASr, RASf ; -; B ; LC19 ; C7M, nRES, nDEVSEL, REGEN, A[1], A[0], A[2], A[3], S[2], S[1], S[0] ; comb~56 ; -; B ; LC27 ; C7M, nRES, PHI1b7_MC, PHI0seen, PHI1reg, S[1], S[0], S[2] ; S[0], S[2], lpm_counter:Ref_rtl_0|dffs[0], REGEN, S[1], lpm_counter:Ref_rtl_0|dffs[1], IOROMEN, RAMSELreg, RASr, CASf, ASel, lpm_counter:Ref_rtl_0|dffs[2], Addr~430, always0~15, Addr[8], Addr[1], lpm_counter:Ref_rtl_0|dffs[3], Addr[9], CASr, RASf, Addr[10], Bank[1], Addr[11], Addr~464, Bank[2], Addr[2], Bank[3], Bank[4], Addr[12], Addr[13], Addr[14], Bank[5], Addr[15], Bank[6], Bank[0], Addr[0], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7] ; -; B ; LC22 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], CASr, RASf ; -; C ; LC33 ; PHI1b0_MC ; PHI1b2_MC ; -; C ; LC40 ; RD[5], nDEVSEL, A[0], A[1], A[2], A[3], Addr[13], Addr[21], Addr[5] ; D[5] ; -; C ; LC38 ; RD[4], nDEVSEL, A[0], A[1], A[2], A[3], Addr[12], Addr[20], Addr[4] ; D[4] ; -; C ; LC45 ; RD[7], nDEVSEL, A[1], A[2], A[3], A[0], Addr[15], Addr[7] ; D[7] ; -; C ; LC37 ; PHI1in, PHI1b6_MC ; PHI1out, PHI1reg, PHI0seen, S[0], S[2], S[1] ; -; C ; LC35 ; C7M_2 ; C7Mout ; -; C ; LC43 ; RD[6], nDEVSEL, A[0], A[1], A[2], A[3], Addr[14], Addr[22], Addr[6] ; D[6] ; -; D ; LC59 ; RD[1], nDEVSEL, A[0], A[1], A[2], A[3], Addr[9], Addr[17], Addr[1] ; D[1] ; -; D ; LC61 ; RD[2], nDEVSEL, A[0], A[1], A[2], A[3], Addr[10], Addr[18], Addr[2] ; D[2] ; -; D ; LC64 ; RD[3], nDEVSEL, A[0], A[1], A[2], A[3], Addr[11], Addr[19], Addr[3] ; D[3] ; -; D ; LC53 ; Addr[22], nDEVSEL, CASf, CASr ; nCAS0 ; -; D ; LC56 ; nWE, CSDBEN, nDEVSEL, nIOSTRB, nIOSEL, nRES ; RD[0], RD[1], RD[2], RD[3], RD[4], RD[5], RD[6], RD[7] ; -; D ; LC51 ; Addr[22], nDEVSEL, CASf, CASr ; nCAS1 ; -; D ; LC63 ; C7M, nRES, S[2] ; DOE~11, RDOE~11, comb~54 ; -; D ; LC55 ; nWE, nDEVSEL, REGEN, A[2], A[1], A[3], A[0] ; Bank[1], Bank[2], Bank[3], Bank[4], Bank[5], Bank[6], Bank[0] ; -; D ; LC49 ; CSDBEN, nIOSEL, IOROMEN, nIOSTRB ; nRCS ; -; D ; LC57 ; RD[0], nDEVSEL, A[0], A[1], A[2], A[3], Addr[8], Addr[16], Addr[0] ; D[0] ; -; E ; LC75 ; Bank[1], nDEVSEL, Addr[2], ASel, Addr[13] ; RA[2] ; -; E ; LC67 ; nWE ; nROE ; -; E ; LC69 ; ASel, Addr[9], Addr[20] ; RA[9] ; -; E ; LC72 ; ASel, Addr[10], Addr[21] ; RA[10] ; -; E ; LC68 ; C7M, nRES, D[2], Addr~464, always0~15, Addr[18], Addr[17], Addr[16], Addr[2], Addr[3], Addr[6], Addr[7], Addr[0], Addr[1], Addr[4], Addr[5], Addr[12], Addr[13], Addr[8], Addr[9], Addr[11], Addr[10], Addr[14], Addr[15] ; Dout[2]~131, Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], RA~126 ; -; E ; LC73 ; Bank[2], nDEVSEL, Addr[3], ASel, Addr[14] ; RA[3] ; -; E ; LC80 ; A[11], nDEVSEL, Addr[0], ASel, Addr[11] ; RA[0] ; -; E ; LC77 ; Bank[4], nDEVSEL, Addr[5], ASel, Addr[16] ; RA[5] ; -; F ; LC93 ; RASr, RASf ; nRAS ; -; F ; LC94 ; D[7] ; RD[7] ; -; F ; LC82 ; nRES, S[2], S[1], nWE, S[0], C7M_2 ; comb~59, comb~63 ; -; F ; LC89 ; nRES, nDEVSEL, REGEN, A[1], A[0], A[2], A[3], nWE, S[2], S[1], S[0], lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[2], C7M_2 ; comb~56 ; -; F ; LC90 ; C7M, nRES, PHI1b7_MC ; S[0], S[2], S[1] ; -; F ; LC85 ; Bank[3], nDEVSEL, Addr[4], ASel, Addr[15] ; RA[4] ; -; F ; LC84 ; S[0], S[2], S[1], nWE, nDEVSEL, REGEN, A[1], A[0], A[2], A[3] ; Addr[17], Addr[18], Addr~481, Addr[16] ; -; F ; LC92 ; PHI1in ; PHI1b1_MC ; -; F ; LC91 ; ASel, Addr[8], Addr[19] ; RA[8] ; -; F ; LC96 ; C7M, nRES, nDEVSEL, REGEN, A[1], A[0], A[2], A[3], S[2], S[1], S[0] ; always0~15, Addr[0], Addr[8], Addr[9], Addr[10], Addr[11], Addr[12], Addr[13], Addr[14], Addr[15] ; -; F ; LC88 ; Bank[5], nDEVSEL, Addr[6], ASel, Addr[17] ; RA[6] ; -; F ; LC86 ; Bank[6], nDEVSEL, Addr[7], ASel, Addr[18] ; RA[7] ; -; F ; LC83 ; Bank[0], nDEVSEL, Addr[1], ASel, Addr[12] ; RA[1] ; -; G ; LC107 ; D[2] ; RD[2] ; -; G ; LC104 ; nDEVSEL, nWE, nIOSTRB, nIOSEL ; nRWE ; -; G ; LC106 ; C7M, nRES, D[4], S[0], S[2], S[1], BankWR_MC ; RA~130 ; -; G ; LC111 ; C7M, nRES, D[5], S[0], S[2], S[1], BankWR_MC ; RA~122 ; -; G ; LC99 ; D[6] ; RD[6] ; -; G ; LC109 ; D[1] ; RD[1] ; -; G ; LC110 ; C7M, nRES, nIOSEL, S[2], S[1], S[0], IOROMEN, A[9], A[5], A[6], A[10], A[2], A[1], A[3], A[0], nIOSTRB, A[8], A[7], A[4] ; DOE~11, IOROMEN, comb~54 ; -; G ; LC100 ; C7M, nRES, D[6], S[0], S[2], S[1], BankWR_MC ; RA~126 ; -; G ; LC97 ; D[5] ; RD[5] ; -; G ; LC98 ; C7M, nRES, S[1], S[0], S[2], nDEVSEL, REGEN, A[1], A[0], A[2], A[3], lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[2] ; comb~59, comb~63 ; -; G ; LC101 ; D[4] ; RD[4] ; -; G ; LC102 ; C7M, nRES, D[1], S[0], S[2], S[1], BankWR_MC ; RA~107 ; -; G ; LC103 ; C7M, nRES, D[2], S[0], S[2], S[1], BankWR_MC ; RA~111 ; -; G ; LC108 ; C7M, nRES, D[0], S[0], S[2], S[1], BankWR_MC ; RA~134 ; -; G ; LC112 ; C7M, nRES, D[3], S[0], S[2], S[1], BankWR_MC ; RA~118 ; -; G ; LC105 ; D[3] ; RD[3] ; -; H ; LC123 ; PHI1b4_MC ; PHI1b6_MC ; -; H ; LC126 ; C7M, nRES, D[5], always0~15, Addr[21], Addr[20], Addr[19], Addr[18], Addr[17], Addr[16], Addr[2], Addr[3], Addr[6], Addr[7], Addr[0], Addr[1], Addr[4], Addr[5], Addr[12], Addr[13], Addr[8], Addr[9], Addr[11], Addr[10], Addr[14], Addr[15], Addr~481 ; Dout[5]~149, Addr[21], RA~114, Addr[22] ; -; H ; LC120 ; C7M, nRES, D[1], Addr~464, always0~15, Addr[17], Addr[16], Addr[2], Addr[3], Addr[6], Addr[7], Addr[0], Addr[1], Addr[4], Addr[5], Addr[12], Addr[13], Addr[8], Addr[9], Addr[11], Addr[10], Addr[14], Addr[15] ; Dout[1]~125, Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], RA~122 ; -; H ; LC125 ; PHI1b5_MC ; PHI1b7_MC ; -; H ; LC115 ; D[0] ; RD[0] ; -; H ; LC128 ; C7M, nRES, D[6], always0~15, Addr[22], Addr[21], Addr[20], Addr[19], Addr[18], Addr[17], Addr[16], Addr[2], Addr[3], Addr[6], Addr[7], Addr[0], Addr[1], Addr[4], Addr[5], Addr[12], Addr[13], Addr[8], Addr[9], Addr[11], Addr[10], Addr[14], Addr[15], Addr~481 ; Dout[6]~155, Addr[22], comb~59, comb~63 ; -; H ; LC124 ; C7M, nRES, D[4], always0~15, Addr[20], Addr[19], Addr[18], Addr[17], Addr[16], Addr[2], Addr[3], Addr[6], Addr[7], Addr[0], Addr[1], Addr[4], Addr[5], Addr[12], Addr[13], Addr[8], Addr[9], Addr[11], Addr[10], Addr[14], Addr[15], Addr~481 ; Dout[4]~143, Addr[20], RA~103, Addr[21], Addr[22] ; -; H ; LC122 ; C7M, nRES, D[3], always0~15, Addr[19], Addr[18], Addr[17], Addr[16], Addr[2], Addr[3], Addr[6], Addr[7], Addr[0], Addr[1], Addr[4], Addr[5], Addr[12], Addr[13], Addr[8], Addr[9], Addr[11], Addr[10], Addr[14], Addr[15], Addr~481 ; Dout[3]~137, Addr[19], RA~100, Addr[20], Addr[21], Addr[22] ; -; H ; LC121 ; PHI1b3_MC ; PHI1b5_MC ; -; H ; LC118 ; C7M, nRES, D[0], Addr~464, always0~15, Addr[16], Addr[2], Addr[3], Addr[6], Addr[7], Addr[0], Addr[1], Addr[4], Addr[5], Addr[12], Addr[13], Addr[8], Addr[9], Addr[11], Addr[10], Addr[14], Addr[15] ; Dout[0]~119, Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[16], RA~130 ; -+-----+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Logic Cell Interconnection ; ++-----+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; LAB ; Logic Cell ; Input ; Output ; ++-----+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; A ; LC8 ; C7M, nRES, D[7], AddrLWR_MC, S[2], S[1], S[0], Addr[7], Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], RAMSELreg ; Dout[7]~95, Addr[11], Addr[7], Addr[8], Addr[16], Addr[17], Addr[9], Addr[10], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[12], Addr[13], Addr[14], Addr[15], RA~111 ; +; A ; LC12 ; C7M, nRES, D[3], AddrMWR_MC, S[2], S[1], S[0], Addr[11], Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], Addr[8], Addr[9], Addr[10], RAMSELreg ; Dout[3]~71, Addr[11], Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[12], Addr[13], Addr[14], Addr[15], RA~70 ; +; A ; LC1 ; C7M, nRES, D[0], AddrLWR_MC, S[1], S[2], S[0], Addr[0], RAMSELreg ; Dout[0]~53, Addr[0], Addr[11], Addr[7], Addr[1], Addr[2], Addr[8], Addr[16], Addr[17], Addr[9], Addr[10], Addr[18], Addr[19], Addr[20], Addr[3], Addr[21], Addr[22], Addr[4], Addr[12], Addr[13], Addr[5], Addr[6], Addr[14], Addr[15], RA~70 ; +; A ; LC11 ; C7M, nRES, D[2], AddrMWR_MC, S[2], S[1], S[0], Addr[10], Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], Addr[8], Addr[9], RAMSELreg ; Dout[2]~65, Addr[11], Addr[16], Addr[17], Addr[10], Addr[18], Addr[19], Addr[20], Addr[21], RA~66, Addr[22], Addr[12], Addr[13], Addr[14], Addr[15] ; +; A ; LC10 ; C7M, nRES, D[1], AddrMWR_MC, S[2], S[1], S[0], Addr[9], Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], Addr[8], RAMSELreg ; Dout[1]~59, Addr[11], Addr[16], Addr[17], Addr[9], Addr[10], Addr[18], Addr[19], Addr[20], RA~63, Addr[21], Addr[22], Addr[12], Addr[13], Addr[14], Addr[15] ; +; A ; LC9 ; C7M, nRES, D[0], AddrMWR_MC, S[2], S[1], S[0], Addr[8], Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], RAMSELreg ; Dout[0]~53, Addr[11], Addr[8], Addr[16], Addr[17], Addr[9], Addr[10], Addr[18], Addr[19], RA~60, Addr[20], Addr[21], Addr[22], Addr[12], Addr[13], Addr[14], Addr[15] ; +; A ; LC16 ; C7M, nRES, D[7], AddrMWR_MC, S[2], S[1], S[0], Addr[15], Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], Addr[8], Addr[9], Addr[10], Addr[11], Addr[12], Addr[13], Addr[14], RAMSELreg ; Dout[7]~95, Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[15], RA~93 ; +; A ; LC7 ; C7M, nRES, D[6], AddrLWR_MC, S[2], S[1], S[0], Addr[6], Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], RAMSELreg ; Dout[6]~89, Addr[11], Addr[7], Addr[8], Addr[16], Addr[17], Addr[9], Addr[10], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[12], Addr[13], Addr[6], Addr[14], Addr[15], RA~105 ; +; A ; LC3 ; C7M, nRES, D[2], AddrLWR_MC, S[2], S[1], S[0], Addr[2], Addr[0], Addr[1], RAMSELreg ; Dout[2]~65, Addr[11], Addr[7], Addr[2], Addr[8], Addr[16], Addr[17], Addr[9], Addr[10], Addr[18], Addr[19], Addr[20], Addr[3], Addr[21], Addr[22], Addr[4], Addr[12], Addr[13], Addr[5], Addr[6], Addr[14], Addr[15], RA~81 ; +; A ; LC6 ; C7M, nRES, D[5], AddrLWR_MC, S[2], S[1], S[0], Addr[5], Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], RAMSELreg ; Dout[5]~83, Addr[11], Addr[7], Addr[8], Addr[16], Addr[17], Addr[9], Addr[10], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[12], Addr[13], Addr[5], Addr[6], Addr[14], Addr[15], RA~99 ; +; A ; LC2 ; C7M, nRES, D[1], AddrLWR_MC, S[2], S[1], S[0], Addr[1], Addr[0], RAMSELreg ; Dout[1]~59, Addr[11], Addr[7], Addr[1], Addr[2], Addr[8], Addr[16], Addr[17], Addr[9], Addr[10], Addr[18], Addr[19], Addr[20], Addr[3], Addr[21], Addr[22], Addr[4], Addr[12], Addr[13], Addr[5], Addr[6], Addr[14], Addr[15], RA~75 ; +; A ; LC14 ; C7M, nRES, D[5], AddrMWR_MC, S[2], S[1], S[0], Addr[13], Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], Addr[8], Addr[9], Addr[10], Addr[11], Addr[12], RAMSELreg ; Dout[5]~83, Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[13], Addr[14], Addr[15], RA~81 ; +; A ; LC13 ; C7M, nRES, D[4], AddrMWR_MC, S[2], S[1], S[0], Addr[12], Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], Addr[8], Addr[9], Addr[10], Addr[11], RAMSELreg ; Dout[4]~77, Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[12], Addr[13], Addr[14], Addr[15], RA~75 ; +; A ; LC5 ; C7M, nRES, D[4], AddrLWR_MC, S[2], S[1], S[0], Addr[4], Addr[0], Addr[1], Addr[2], Addr[3], RAMSELreg ; Dout[4]~77, Addr[11], Addr[7], Addr[8], Addr[16], Addr[17], Addr[9], Addr[10], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[4], Addr[12], Addr[13], Addr[5], Addr[6], Addr[14], Addr[15], RA~93 ; +; A ; LC15 ; C7M, nRES, D[6], AddrMWR_MC, S[2], S[1], S[0], Addr[14], Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], Addr[8], Addr[9], Addr[10], Addr[11], Addr[12], Addr[13], RAMSELreg ; Dout[6]~89, Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[14], Addr[15], RA~87 ; +; A ; LC4 ; C7M, nRES, D[3], AddrLWR_MC, S[2], S[1], S[0], Addr[3], Addr[0], Addr[1], Addr[2], RAMSELreg ; Dout[3]~71, Addr[11], Addr[7], Addr[8], Addr[16], Addr[17], Addr[9], Addr[10], Addr[18], Addr[19], Addr[20], Addr[3], Addr[21], Addr[22], Addr[4], Addr[12], Addr[13], Addr[5], Addr[6], Addr[14], Addr[15], RA~87 ; +; B ; LC29 ; C7M, nRES, D[3], AddrHWR_MC, S[2], S[1], S[0], Addr[19], Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], Addr[8], Addr[9], Addr[10], Addr[11], Addr[12], Addr[13], Addr[14], Addr[15], Addr[16], Addr[17], Addr[18], RAMSELreg ; Dout[3]~71, Addr[19], RA~60, Addr[20], Addr[21], Addr[22] ; +; B ; LC31 ; C7M, nRES, D[2], AddrHWR_MC, S[2], S[1], S[0], Addr[18], Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], Addr[8], Addr[9], Addr[10], Addr[11], Addr[12], Addr[13], Addr[14], Addr[15], Addr[16], Addr[17], RAMSELreg ; Dout[2]~65, Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], RA~111 ; +; B ; LC19 ; C7M, nRES, D[2], BankWR_MC, S[0], S[2], S[1] ; RA~81, RA~82, RA~87, RA~88, RA~93, RA~94, RA~99, RA~100, RA~105, RA~106, RA~111 ; +; B ; LC30 ; C7M, nRES, S[2] ; DOE~5, RDOE~1, comb~46 ; +; B ; LC21 ; C7M, nRES, D[0], AddrHWR_MC, S[2], S[1], S[0], Addr[16], Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], Addr[8], Addr[9], Addr[10], Addr[11], Addr[12], Addr[13], Addr[14], Addr[15], RAMSELreg ; Dout[0]~53, Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], RA~99 ; +; B ; LC32 ; CSDBEN, nWE ; RD[0], RD[1], RD[2], RD[3], RD[4], RD[5], RD[6], RD[7] ; +; B ; LC27 ; C7M, nRES, D[1], BankWR_MC, S[0], S[2], S[1] ; RA~75, RA~81, RA~82, RA~87, RA~88, RA~93, RA~94, RA~99, RA~100, RA~105, RA~106, RA~111 ; +; B ; LC17 ; ; nINH ; +; B ; LC22 ; C7M, nRES, D[1], AddrHWR_MC, S[2], S[1], S[0], Addr[17], Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], Addr[8], Addr[9], Addr[10], Addr[11], Addr[12], Addr[13], Addr[14], Addr[15], Addr[16], RAMSELreg ; Dout[1]~59, Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], RA~105 ; +; B ; LC20 ; C7M, nRES, D[0], BankWR_MC, S[0], S[2], S[1] ; RA~70, RA~75, RA~81, RA~82, RA~87, RA~88, RA~93, RA~94, RA~99, RA~100, RA~105, RA~106, RA~111 ; +; B ; LC26 ; C7M, nRES, Addr[21], Addr[20], Addr[19], Addr[18], Addr[17], Addr[16], Addr[15], Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], Addr[22], S[1], RAMSELreg, S[2], S[0] ; Addr[22], comb~51, comb~55 ; +; B ; LC25 ; C7M, nRES, Addr[20], Addr[19], Addr[18], Addr[17], Addr[16], Addr[15], Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], Addr[21], S[1], RAMSELreg, S[2], S[0] ; Addr[21], RA~66, Addr[22] ; +; B ; LC28 ; C7M, nRES, D[3], BankWR_MC, S[0], S[2], S[1] ; RA~87, RA~88, RA~93, RA~94, RA~99, RA~100, RA~105, RA~106, RA~111 ; +; B ; LC23 ; C7M, nRES, Addr[19], Addr[18], Addr[17], Addr[16], Addr[15], Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], Addr[20], S[1], RAMSELreg, S[2], S[0] ; Addr[20], RA~63, Addr[21], Addr[22] ; +; C ; LC34 ; C7M, nRES, RAMSEL_MC, S[2], S[0], S[1], RAMSELreg ; RAMSELreg, Addr[0], Addr[11], Addr[7], Addr[1], Addr[2], Addr[8], Addr[16], Addr[17], Addr[9], Addr[10], Addr[18], Addr[19], Addr[20], Addr[3], Addr[21], Addr[22], Addr[4], Addr[12], Addr[13], Addr[5], Addr[6], Addr[14], Addr[15] ; +; C ; LC46 ; PHI1in ; PHI1b1_MC ; +; C ; LC35 ; C7M_2 ; C7Mout ; +; C ; LC37 ; PHI1in, PHI1b8_MC ; PHI1reg, PHI0seen, PHI1out, S[0], S[1], S[2] ; +; C ; LC33 ; C7M, nRES, PHI1b9_MC ; S[0], S[1], S[2] ; +; C ; LC38 ; RD[4], nDEVSEL, A[1], A[2], A[3], A[0], Addr[12], Addr[4] ; D[4] ; +; C ; LC40 ; RD[5], nDEVSEL, A[1], A[2], A[3], A[0], Addr[13], Addr[5] ; D[5] ; +; C ; LC43 ; RD[6], nDEVSEL, A[1], A[2], A[3], A[0], Addr[14], Addr[6] ; D[6] ; +; C ; LC45 ; RD[7], nDEVSEL, A[1], A[2], A[3], A[0], Addr[15], Addr[7] ; D[7] ; +; C ; LC36 ; C7M, nRES, PHI1b9_MC ; S[0], S[1], S[2] ; +; C ; LC39 ; C7M, nRES, RAMSEL_MC, S[2], S[1] ; RA~60, RA~63, RA~66, RA~70, RA~75, RA~81, RA~87, RA~93, RA~99, RA~105, RA~111 ; +; C ; LC42 ; C7M, nRES, RAMSEL_MC, S[0], S[2], S[1] ; comb~48 ; +; C ; LC41 ; C7M, nRES, nIOSEL, S[0], S[2], S[1] ; DOE~5, RAMSEL_MC, AddrHWR_MC, AddrMWR_MC, AddrLWR_MC, BankWR_MC, IOBank0 ; +; D ; LC57 ; RD[0], nDEVSEL, A[0], A[1], A[2], A[3], Addr[8], Addr[16], Addr[0] ; D[0] ; +; D ; LC56 ; REGEN, nDEVSEL, CSDBEN, nWE, nIOSEL, IOROMEN, nIOSTRB ; D[0], D[1], D[2], D[3], D[4], D[5], D[6], D[7] ; +; D ; LC59 ; RD[1], nDEVSEL, A[0], A[1], A[2], A[3], Addr[9], Addr[17], Addr[1] ; D[1] ; +; D ; LC61 ; RD[2], nDEVSEL, A[0], A[1], A[2], A[3], Addr[10], Addr[18], Addr[2] ; D[2] ; +; D ; LC64 ; RD[3], nDEVSEL, A[0], A[1], A[2], A[3], Addr[11], Addr[19], Addr[3] ; D[3] ; +; D ; LC53 ; Addr[22], CASf, nDEVSEL, CASr ; nCAS0 ; +; D ; LC51 ; Addr[22], CASf, nDEVSEL, CASr ; nCAS1 ; +; D ; LC49 ; CSDBEN, nIOSEL, IOROMEN, nIOSTRB ; nRCS ; +; E ; LC80 ; IOBank0, Bank[0], nIOSEL, nIOSTRB, Addr[0], ASel, Addr[11] ; RA[0] ; +; E ; LC72 ; Addr[10], ASel, Addr[21] ; RA[10] ; +; E ; LC68 ; PHI1b7_MC ; PHI1b9_MC ; +; E ; LC67 ; nWE ; nROE ; +; E ; LC70 ; PHI1b4_MC ; PHI1b6_MC ; +; E ; LC65 ; PHI1b5_MC ; PHI1b7_MC ; +; E ; LC69 ; Addr[9], ASel, Addr[20] ; RA[9] ; +; E ; LC66 ; PHI1b6_MC ; PHI1b8_MC ; +; E ; LC77 ; IOBank0, Bank[5], Bank[4], Bank[3], Bank[2], Bank[1], Bank[0], nIOSEL, nIOSTRB, Addr[5], ASel, Addr[16], RA~94 ; RA[5] ; +; E ; LC73 ; IOBank0, Bank[3], Bank[2], Bank[1], Bank[0], nIOSEL, nIOSTRB, Addr[3], ASel, Addr[14], RA~82 ; RA[3] ; +; E ; LC75 ; IOBank0, Bank[2], Bank[1], nIOSEL, nIOSTRB, Bank[0], Addr[2], ASel, Addr[13] ; RA[2] ; +; F ; LC93 ; RASr, RASf ; nRAS ; +; F ; LC91 ; Addr[8], ASel, Addr[19] ; RA[8] ; +; F ; LC94 ; D[7] ; RD[7] ; +; F ; LC82 ; C7M, nRES, D[5], BankWR_MC, S[0], S[2], S[1] ; RA~99, RA~100, RA~105, RA~106, RA~111 ; +; F ; LC85 ; IOBank0, Bank[4], Bank[3], Bank[2], Bank[1], Bank[0], nIOSEL, nIOSTRB, Addr[4], ASel, Addr[15], RA~88 ; RA[4] ; +; F ; LC88 ; IOBank0, Bank[6], Bank[5], Bank[4], Bank[3], Bank[2], Bank[1], Bank[0], nIOSEL, nIOSTRB, Addr[6], ASel, Addr[17], RA~100 ; RA[6] ; +; F ; LC86 ; IOBank0, Bank[7], Bank[6], Bank[5], Bank[4], Bank[3], Bank[2], Bank[1], Bank[0], nIOSEL, nIOSTRB, Addr[7], ASel, Addr[18], RA~106 ; RA[7] ; +; F ; LC83 ; IOBank0, Bank[1], Bank[0], nIOSEL, nIOSTRB, Addr[1], ASel, Addr[12] ; RA[1] ; +; G ; LC109 ; D[1] ; RD[1] ; +; G ; LC101 ; D[4] ; RD[4] ; +; G ; LC97 ; D[5] ; RD[5] ; +; G ; LC111 ; A[0], nWE, REGEN, nDEVSEL, A[1], A[2], A[3] ; Bank[0], Bank[1], Bank[2], Bank[3], Bank[4], Bank[5], Bank[6], Bank[7] ; +; G ; LC102 ; C7M, nRES, nIOSEL, S[2], S[1], S[0], IOROMEN, A[0], A[4], A[5], A[6], A[7], A[8], A[9], A[10], nIOSTRB, A[1], A[2], A[3] ; DOE~5, IOROMEN, comb~46 ; +; G ; LC104 ; nDEVSEL, nIOSEL, nIOSTRB, nWE ; nRWE ; +; G ; LC108 ; C7M, nRES, D[6], BankWR_MC, S[0], S[2], S[1] ; RA~105, RA~106, RA~111 ; +; G ; LC107 ; D[2] ; RD[2] ; +; G ; LC99 ; D[6] ; RD[6] ; +; G ; LC112 ; C7M, nRES, D[7], BankWR_MC, S[0], S[2], S[1] ; RA~111 ; +; G ; LC103 ; C7M, nRES, D[7], D[6], D[5], D[4], D[3], D[2], D[1], D[0], A[0], S[0], S[2], S[1], nWE, REGEN, nDEVSEL, A[1], A[2], A[3] ; RA~70, RA~75, RA~81, RA~87, RA~93, RA~99, RA~105, RA~111 ; +; G ; LC98 ; REGEN, nDEVSEL, A[1], A[0], A[2], A[3] ; ASel, RASr, RAMSELreg, CASr, RASf ; +; G ; LC105 ; D[3] ; RD[3] ; +; G ; LC110 ; A[1], A[0], A[2], A[3], nWE, REGEN, nDEVSEL ; Addr[16], Addr[17], Addr[18], Addr[19] ; +; G ; LC106 ; A[1], A[0], A[2], A[3], nWE, REGEN, nDEVSEL ; Addr[11], Addr[8], Addr[9], Addr[10], Addr[12], Addr[13], Addr[14], Addr[15] ; +; G ; LC100 ; A[1], A[0], A[2], A[3], nWE, REGEN, nDEVSEL ; Addr[0], Addr[7], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6] ; +; H ; LC115 ; D[0] ; RD[0] ; +; H ; LC126 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], CASr, RASf ; +; H ; LC128 ; C7M, nRES, S[1], S[0], S[2], lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], RAMSEL_MC ; comb~51, comb~55 ; +; H ; LC119 ; nRES, S[0], S[2], S[1], lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], nWE, RAMSEL_MC, C7M_2 ; comb~48 ; +; H ; LC123 ; PHI1b2_MC ; PHI1b4_MC ; +; H ; LC124 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[0], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], CASr, RASf ; +; H ; LC121 ; PHI1b1_MC ; PHI1b3_MC ; +; H ; LC114 ; C7M, nRES, D[4], BankWR_MC, S[0], S[2], S[1] ; RA~93, RA~94, RA~99, RA~100, RA~105, RA~106, RA~111 ; +; H ; LC118 ; PHI1b0_MC ; PHI1b2_MC ; +; H ; LC113 ; C7M, nRES, PHI1reg, PHI0seen, PHI1b9_MC, S[0], S[1], S[2] ; S[0], S[1], S[2], CASf, lpm_counter:Ref_rtl_0|dffs[0], REGEN, IOROMEN, lpm_counter:Ref_rtl_0|dffs[1], RASr, lpm_counter:Ref_rtl_0|dffs[2], RAMSELreg, lpm_counter:Ref_rtl_0|dffs[3], Addr[0], Addr[11], Addr[7], CASr, RASf, Addr[1], Addr[2], Addr[8], Bank[0], Addr[16], Addr[17], Bank[1], Addr[9], Addr[10], Bank[2], Addr[18], Addr[19], Addr[20], Bank[3], Addr[3], Addr[21], Addr[22], Addr[4], Bank[4], Addr[12], Addr[13], Bank[5], Addr[5], Addr[6], Bank[6], Addr[14], Addr[15], Bank[7], IOBank0 ; +; H ; LC120 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], CASr, RASf ; +; H ; LC125 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], CASr, RASf ; +; H ; LC117 ; C7M, nRES, PHI1reg, PHI0seen, PHI1b9_MC, S[0], S[1], S[2] ; S[0], S[1], S[2], CASf, lpm_counter:Ref_rtl_0|dffs[0], REGEN, IOROMEN, lpm_counter:Ref_rtl_0|dffs[1], ASel, RASr, lpm_counter:Ref_rtl_0|dffs[2], RAMSELreg, lpm_counter:Ref_rtl_0|dffs[3], Addr[0], Addr[11], Addr[7], CASr, RASf, Addr[1], Addr[2], Addr[8], Bank[0], Addr[16], Addr[17], Bank[1], Addr[9], Addr[10], Bank[2], Addr[18], Addr[19], Addr[20], Bank[3], Addr[3], Addr[21], Addr[22], Addr[4], Bank[4], Addr[12], Addr[13], Bank[5], Addr[5], Addr[6], Bank[6], Addr[14], Addr[15], Bank[7], IOBank0 ; +; H ; LC122 ; C7M, nRES, PHI1reg, PHI0seen, PHI1b9_MC, S[1], S[2], S[0] ; S[0], S[1], S[2], CSDBEN, CASf, lpm_counter:Ref_rtl_0|dffs[0], REGEN, IOROMEN, lpm_counter:Ref_rtl_0|dffs[1], ASel, RASr, lpm_counter:Ref_rtl_0|dffs[2], RAMSELreg, lpm_counter:Ref_rtl_0|dffs[3], Addr[0], Addr[11], Addr[7], CASr, RASf, Addr[1], Addr[2], Addr[8], Bank[0], Addr[16], Addr[17], Bank[1], Addr[9], Addr[10], Bank[2], Addr[18], Addr[19], Addr[20], Bank[3], Addr[3], Addr[21], Addr[22], Addr[4], Bank[4], Addr[12], Addr[13], Bank[5], Addr[5], Addr[6], Bank[6], Addr[14], Addr[15], Bank[7], IOBank0 ; +; H ; LC127 ; nRES, S[2], S[1], S[0], nWE, C7M_2 ; comb~51, comb~55 ; +; H ; LC116 ; PHI1b3_MC ; PHI1b5_MC ; ++-----+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +---------------------------------------------------------------+ @@ -715,11 +731,10 @@ Note: User assignments will override these defaults. The user specified values a +-----------------+ Warning (20028): Parallel compilation is not licensed and has been disabled Info (119006): Selected device EPM7128SLC84-15 for design "GR8RAM" -Warning (163058): Can't place macrocell "PHI1b7_MC" assigned to LC127 and node "PHI1out" assigned to PIN_30 -- ignoring macrocell assignment -Info: Quartus II 32-bit Fitter was successful. 0 errors, 2 warnings - Info: Peak virtual memory: 287 megabytes - Info: Processing ended: Sat Aug 31 22:53:38 2019 - Info: Elapsed time: 00:00:07 - Info: Total CPU time (on all processors): 00:00:06 +Info: Quartus II 64-Bit Fitter was successful. 0 errors, 1 warning + Info: Peak virtual memory: 4708 megabytes + Info: Processing ended: Sun Sep 01 20:44:15 2019 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:01 diff --git a/cpld/output_files/GR8RAM.fit.summary b/cpld/output_files/GR8RAM.fit.summary index 7085db9..5b4ff03 100755 --- a/cpld/output_files/GR8RAM.fit.summary +++ b/cpld/output_files/GR8RAM.fit.summary @@ -1,9 +1,9 @@ -Fitter Status : Successful - Sat Aug 31 22:53:38 2019 -Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition +Fitter Status : Successful - Sun Sep 01 20:44:15 2019 +Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition Revision Name : GR8RAM Top-level Entity Name : GR8RAM Family : MAX7000S Device : EPM7128SLC84-15 Timing Models : Final -Total macrocells : 96 / 128 ( 75 % ) +Total macrocells : 102 / 128 ( 80 % ) Total pins : 67 / 68 ( 99 % ) diff --git a/cpld/output_files/GR8RAM.flow.rpt b/cpld/output_files/GR8RAM.flow.rpt index e3171a2..7de0d88 100755 --- a/cpld/output_files/GR8RAM.flow.rpt +++ b/cpld/output_files/GR8RAM.flow.rpt @@ -1,6 +1,6 @@ Flow report for GR8RAM -Sat Aug 31 22:53:50 2019 -Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +Sun Sep 01 20:44:17 2019 +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition --------------------- @@ -40,14 +40,14 @@ applicable agreement for further details. +-----------------------------------------------------------------------------+ ; Flow Summary ; +---------------------------+-------------------------------------------------+ -; Flow Status ; Successful - Sat Aug 31 22:53:42 2019 ; -; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; +; Flow Status ; Successful - Sun Sep 01 20:44:16 2019 ; +; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; ; Revision Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ; ; Family ; MAX7000S ; ; Device ; EPM7128SLC84-15 ; ; Timing Models ; Final ; -; Total macrocells ; 96 / 128 ( 75 % ) ; +; Total macrocells ; 102 / 128 ( 80 % ) ; ; Total pins ; 67 / 68 ( 99 % ) ; +---------------------------+-------------------------------------------------+ @@ -57,35 +57,39 @@ applicable agreement for further details. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 08/31/2019 22:53:23 ; +; Start date & time ; 09/01/2019 20:44:13 ; ; Main task ; Compilation ; ; Revision Name ; GR8RAM ; +-------------------+---------------------+ -+---------------------------------------------------------------------------------------------------------------------+ -; Flow Non-Default Global Settings ; -+--------------------------------------------+-----------------------------+---------------+-------------+------------+ -; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; -+--------------------------------------------+-----------------------------+---------------+-------------+------------+ -; ALM_REGISTER_PACKING_EFFORT ; High ; Medium ; -- ; -- ; -; AUTO_RESOURCE_SHARING ; On ; Off ; -- ; -- ; -; COMPILER_SIGNATURE_ID ; 52238299365.156730640303584 ; -- ; -- ; -- ; -; ECO_OPTIMIZE_TIMING ; On ; Off ; -- ; -- ; -; ECO_REGENERATE_REPORT ; On ; Off ; -- ; -- ; -; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ; -; MAX7000_IGNORE_LCELL_BUFFERS ; Off ; Auto ; -- ; -- ; -; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; -; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; -; OPTIMIZE_HOLD_TIMING ; Off ; -- ; -- ; -- ; -; OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING ; Pack All IO Registers ; Normal ; -- ; -- ; -; PARALLEL_SYNTHESIS ; Off ; On ; -- ; -- ; -; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; -; SLOW_SLEW_RATE ; On ; Off ; -- ; -- ; -; STATE_MACHINE_PROCESSING ; User-Encoded ; Auto ; -- ; -- ; -; SYNTH_MESSAGE_LEVEL ; High ; Medium ; -- ; -- ; -; SYNTH_TIMING_DRIVEN_SYNTHESIS ; Off ; -- ; -- ; -- ; -+--------------------------------------------+-----------------------------+---------------+-------------+------------+ ++-------------------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++--------------------------------------------+---------------------------------+---------------+-------------+------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++--------------------------------------------+---------------------------------+---------------+-------------+------------+ +; ALM_REGISTER_PACKING_EFFORT ; High ; Medium ; -- ; -- ; +; AUTO_LCELL_INSERTION ; Off ; On ; -- ; -- ; +; AUTO_PARALLEL_EXPANDERS ; Off ; On ; -- ; -- ; +; COMPILER_SIGNATURE_ID ; 207120313862967.156738505316020 ; -- ; -- ; -- ; +; ECO_OPTIMIZE_TIMING ; On ; Off ; -- ; -- ; +; ECO_REGENERATE_REPORT ; On ; Off ; -- ; -- ; +; EXTRACT_VERILOG_STATE_MACHINES ; Off ; On ; -- ; -- ; +; EXTRACT_VHDL_STATE_MACHINES ; Off ; On ; -- ; -- ; +; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ; +; MAX7000_IGNORE_LCELL_BUFFERS ; Off ; Auto ; -- ; -- ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; OPTIMIZE_HOLD_TIMING ; Off ; -- ; -- ; -- ; +; OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING ; Pack All IO Registers ; Normal ; -- ; -- ; +; PARALLEL_SYNTHESIS ; Off ; On ; -- ; -- ; +; PRE_MAPPING_RESYNTHESIS ; On ; Off ; -- ; -- ; +; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; +; SLOW_SLEW_RATE ; On ; Off ; -- ; -- ; +; STATE_MACHINE_PROCESSING ; User-Encoded ; Auto ; -- ; -- ; +; SYNTH_MESSAGE_LEVEL ; High ; Medium ; -- ; -- ; +; SYNTH_TIMING_DRIVEN_SYNTHESIS ; Off ; -- ; -- ; -- ; ++--------------------------------------------+---------------------------------+---------------+-------------+------------+ +-------------------------------------------------------------------------------------------------------------------------------+ @@ -93,24 +97,24 @@ applicable agreement for further details. +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:10 ; 1.0 ; 308 MB ; 00:00:09 ; -; Fitter ; 00:00:07 ; 1.0 ; 287 MB ; 00:00:05 ; -; Assembler ; 00:00:02 ; 1.0 ; 275 MB ; 00:00:02 ; -; TimeQuest Timing Analyzer ; 00:00:06 ; 1.0 ; 260 MB ; 00:00:05 ; -; Total ; 00:00:25 ; -- ; -- ; 00:00:21 ; +; Analysis & Synthesis ; 00:00:01 ; 1.0 ; 4587 MB ; 00:00:01 ; +; Fitter ; 00:00:01 ; 1.0 ; 4708 MB ; 00:00:00 ; +; Assembler ; 00:00:00 ; 1.0 ; 4520 MB ; 00:00:00 ; +; TimeQuest Timing Analyzer ; 00:00:00 ; 1.0 ; 4530 MB ; 00:00:00 ; +; Total ; 00:00:02 ; -- ; -- ; 00:00:01 ; +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ -+-----------------------------------------------------------------------------------------+ -; Flow OS Summary ; -+---------------------------+------------------+------------+------------+----------------+ -; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; -+---------------------------+------------------+------------+------------+----------------+ -; Analysis & Synthesis ; zane-f8c4ec68a5 ; Windows XP ; 5.1 ; i686 ; -; Fitter ; zane-f8c4ec68a5 ; Windows XP ; 5.1 ; i686 ; -; Assembler ; zane-f8c4ec68a5 ; Windows XP ; 5.1 ; i686 ; -; TimeQuest Timing Analyzer ; zane-f8c4ec68a5 ; Windows XP ; 5.1 ; i686 ; -+---------------------------+------------------+------------+------------+----------------+ ++----------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++---------------------------+------------------+-----------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++---------------------------+------------------+-----------+------------+----------------+ +; Analysis & Synthesis ; DESKTOP-G62HNQS ; Windows 7 ; 6.2 ; x86_64 ; +; Fitter ; DESKTOP-G62HNQS ; Windows 7 ; 6.2 ; x86_64 ; +; Assembler ; DESKTOP-G62HNQS ; Windows 7 ; 6.2 ; x86_64 ; +; TimeQuest Timing Analyzer ; DESKTOP-G62HNQS ; Windows 7 ; 6.2 ; x86_64 ; ++---------------------------+------------------+-----------+------------+----------------+ ------------ diff --git a/cpld/output_files/GR8RAM.jdi b/cpld/output_files/GR8RAM.jdi index 8feebb4..5b4d4c5 100755 --- a/cpld/output_files/GR8RAM.jdi +++ b/cpld/output_files/GR8RAM.jdi @@ -1,6 +1,6 @@ - + diff --git a/cpld/output_files/GR8RAM.map.rpt b/cpld/output_files/GR8RAM.map.rpt index 97fa0f2..260e580 100755 --- a/cpld/output_files/GR8RAM.map.rpt +++ b/cpld/output_files/GR8RAM.map.rpt @@ -1,6 +1,6 @@ Analysis & Synthesis report for GR8RAM -Sat Aug 31 22:53:29 2019 -Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +Sun Sep 01 20:44:14 2019 +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition --------------------- @@ -9,13 +9,15 @@ Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit 1. Legal Notice 2. Analysis & Synthesis Summary 3. Analysis & Synthesis Settings - 4. Analysis & Synthesis Source Files Read - 5. Analysis & Synthesis Resource Usage Summary - 6. Analysis & Synthesis Resource Utilization by Entity - 7. Parameter Settings for Inferred Entity Instance: lpm_counter:Ref_rtl_0 - 8. Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add2 - 9. Analysis & Synthesis Messages - 10. Analysis & Synthesis Suppressed Messages + 4. Parallel Compilation + 5. Analysis & Synthesis Source Files Read + 6. Analysis & Synthesis Resource Usage Summary + 7. Analysis & Synthesis Resource Utilization by Entity + 8. Parameter Settings for Inferred Entity Instance: lpm_counter:Ref_rtl_0 + 9. Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add0 + 10. Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add3 + 11. Analysis & Synthesis Messages + 12. Analysis & Synthesis Suppressed Messages @@ -41,12 +43,12 @@ applicable agreement for further details. +-------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +-----------------------------+-------------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Sat Aug 31 22:53:29 2019 ; -; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; +; Analysis & Synthesis Status ; Successful - Sun Sep 01 20:44:14 2019 ; +; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; ; Revision Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ; ; Family ; MAX7000S ; -; Total macrocells ; 96 ; +; Total macrocells ; 102 ; ; Total pins ; 63 ; +-----------------------------+-------------------------------------------------+ @@ -60,9 +62,13 @@ applicable agreement for further details. ; Top-level entity name ; GR8RAM ; GR8RAM ; ; Family name ; MAX7000S ; Cyclone IV GX ; ; State Machine Processing ; User-Encoded ; Auto ; +; Extract Verilog State Machines ; Off ; On ; +; Extract VHDL State Machines ; Off ; On ; ; Parallel Synthesis ; Off ; On ; ; Ignore LCELL Buffers ; Off ; Auto ; -; Auto Resource Sharing ; On ; Off ; +; Auto Logic Cell Insertion ; Off ; On ; +; Auto Parallel Expanders ; Off ; On ; +; Pre-Mapping Resynthesis Optimization ; On ; Off ; ; Analysis & Synthesis Message Level ; High ; Medium ; ; Use smart compilation ; Off ; Off ; ; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; @@ -73,8 +79,6 @@ applicable agreement for further details. ; Verilog Version ; Verilog_2001 ; Verilog_2001 ; ; VHDL Version ; VHDL_1993 ; VHDL_1993 ; ; Safe State Machine ; Off ; Off ; -; Extract Verilog State Machines ; On ; On ; -; Extract VHDL State Machines ; On ; On ; ; Ignore Verilog initial constructs ; Off ; Off ; ; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; ; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; @@ -91,10 +95,9 @@ applicable agreement for further details. ; Limit AHDL Integers to 32 Bits ; Off ; Off ; ; Optimization Technique ; Speed ; Speed ; ; Allow XOR Gate Usage ; On ; On ; -; Auto Logic Cell Insertion ; On ; On ; ; Parallel Expander Chain Length ; 4 ; 4 ; -; Auto Parallel Expanders ; On ; On ; ; Auto Open-Drain Pins ; On ; On ; +; Auto Resource Sharing ; Off ; Off ; ; Maximum Fan-in Per Macrocell ; 100 ; 100 ; ; Use LogicLock Constraints during Resource Balancing ; On ; On ; ; Ignore translate_off and synthesis_off directives ; Off ; Off ; @@ -109,18 +112,28 @@ applicable agreement for further details. ; Block Design Naming ; Auto ; Auto ; ; Synthesis Effort ; Auto ; Auto ; ; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; -; Pre-Mapping Resynthesis Optimization ; Off ; Off ; ; Disable Register Merging Across Hierarchies ; Auto ; Auto ; ; Synthesis Seed ; 1 ; 1 ; +----------------------------------------------------------------------------+-----------------+---------------+ +Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. ++-------------------------------------+ +; Parallel Compilation ; ++----------------------------+--------+ +; Processors ; Number ; ++----------------------------+--------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 1 ; ++----------------------------+--------+ + + +-------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Source Files Read ; +----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------+---------+ ; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; +----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------+---------+ -; GR8RAM.v ; yes ; User Verilog HDL File ; Z:/Repos/GR8RAM/cpld/GR8RAM.v ; ; +; GR8RAM.v ; yes ; User Verilog HDL File ; C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v ; ; ; lpm_counter.tdf ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_counter.tdf ; ; ; lpm_constant.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_constant.inc ; ; ; lpm_decode.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_decode.inc ; ; @@ -150,14 +163,14 @@ applicable agreement for further details. +----------------------+----------------------+ ; Resource ; Usage ; +----------------------+----------------------+ -; Logic cells ; 96 ; -; Total registers ; 48 ; +; Logic cells ; 102 ; +; Total registers ; 50 ; ; I/O pins ; 63 ; -; Shareable expanders ; 10 ; +; Shareable expanders ; 5 ; ; Maximum fan-out node ; nRES ; ; Maximum fan-out ; 50 ; -; Total fan-out ; 1124 ; -; Average fan-out ; 6.65 ; +; Total fan-out ; 993 ; +; Average fan-out ; 5.84 ; +----------------------+----------------------+ @@ -166,7 +179,7 @@ applicable agreement for further details. +----------------------------+------------+------+-------------------------------+--------------+ ; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ; Library Name ; +----------------------------+------------+------+-------------------------------+--------------+ -; |GR8RAM ; 96 ; 63 ; |GR8RAM ; work ; +; |GR8RAM ; 102 ; 63 ; |GR8RAM ; work ; ; |lpm_counter:Ref_rtl_0| ; 4 ; 0 ; |GR8RAM|lpm_counter:Ref_rtl_0 ; work ; +----------------------------+------------+------+-------------------------------+--------------+ @@ -199,7 +212,35 @@ Note: In order to hide this table in the UI and the text report file, please set +-------------------------------------------------------------------+ -; Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add2 ; +; Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add0 ; ++------------------------+-------------+----------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+----------------------------+ +; LPM_WIDTH ; 8 ; Untyped ; +; LPM_REPRESENTATION ; UNSIGNED ; Untyped ; +; LPM_DIRECTION ; ADD ; Untyped ; +; ONE_INPUT_IS_CONSTANT ; YES ; Untyped ; +; LPM_PIPELINE ; 0 ; Untyped ; +; MAXIMIZE_SPEED ; 5 ; Untyped ; +; REGISTERED_AT_END ; 0 ; Untyped ; +; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ; +; USE_CS_BUFFERS ; 1 ; Untyped ; +; CARRY_CHAIN ; MANUAL ; Untyped ; +; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ; +; DEVICE_FAMILY ; MAX7000S ; Untyped ; +; USE_WYS ; OFF ; Untyped ; +; STYLE ; FAST ; Untyped ; +; CBXI_PARAMETER ; add_sub_rnh ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+----------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------+ +; Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add3 ; +------------------------+-------------+----------------------------+ ; Parameter Name ; Value ; Type ; +------------------------+-------------+----------------------------+ @@ -230,67 +271,80 @@ Note: In order to hide this table in the UI and the text report file, please set ; Analysis & Synthesis Messages ; +-------------------------------+ Info: ******************************************************************* -Info: Running Quartus II 32-bit Analysis & Synthesis +Info: Running Quartus II 64-Bit Analysis & Synthesis Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - Info: Processing started: Sat Aug 31 22:53:19 2019 + Info: Processing started: Sun Sep 01 20:44:13 2019 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM Warning (20028): Parallel compilation is not licensed and has been disabled Info (12021): Found 1 design units, including 1 entities, in source file gr8ram.v Info (12023): Found entity 1: GR8RAM Info (12127): Elaborating entity "GR8RAM" for the top level hierarchy -Warning (10230): Verilog HDL assignment warning at GR8RAM.v(124): truncated value with size 32 to match size of target (3) -Warning (10230): Verilog HDL assignment warning at GR8RAM.v(129): truncated value with size 32 to match size of target (4) -Warning (10230): Verilog HDL assignment warning at GR8RAM.v(153): truncated value with size 32 to match size of target (23) +Warning (10230): Verilog HDL assignment warning at GR8RAM.v(33): truncated value with size 32 to match size of target (8) +Warning (10230): Verilog HDL assignment warning at GR8RAM.v(132): truncated value with size 32 to match size of target (3) +Warning (10230): Verilog HDL assignment warning at GR8RAM.v(137): truncated value with size 32 to match size of target (4) +Warning (10230): Verilog HDL assignment warning at GR8RAM.v(162): truncated value with size 32 to match size of target (23) Info (19000): Inferred 1 megafunctions from design logic Info (19001): Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "Ref_rtl_0" -Info (278001): Inferred 1 megafunctions from design logic - Info (278002): Inferred adder/subtractor megafunction ("lpm_add_sub") from the following logic: "Add2" +Info (278001): Inferred 2 megafunctions from design logic + Info (278002): Inferred adder/subtractor megafunction ("lpm_add_sub") from the following logic: "Add0" + Info (278002): Inferred adder/subtractor megafunction ("lpm_add_sub") from the following logic: "Add3" Info (12130): Elaborated megafunction instantiation "lpm_counter:Ref_rtl_0" Info (12133): Instantiated megafunction "lpm_counter:Ref_rtl_0" with the following parameter: Info (12134): Parameter "LPM_WIDTH" = "4" Info (12134): Parameter "LPM_DIRECTION" = "UP" Info (12134): Parameter "LPM_TYPE" = "LPM_COUNTER" -Info (12130): Elaborated megafunction instantiation "lpm_add_sub:Add2" -Info (12133): Instantiated megafunction "lpm_add_sub:Add2" with the following parameter: +Info (12130): Elaborated megafunction instantiation "lpm_add_sub:Add0" +Info (12133): Instantiated megafunction "lpm_add_sub:Add0" with the following parameter: + Info (12134): Parameter "LPM_WIDTH" = "8" + Info (12134): Parameter "LPM_DIRECTION" = "ADD" + Info (12134): Parameter "LPM_REPRESENTATION" = "UNSIGNED" + Info (12134): Parameter "ONE_INPUT_IS_CONSTANT" = "YES" +Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add0|addcore:adder[0]", which is child of megafunction instantiation "lpm_add_sub:Add0" +Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add0|addcore:adder[0]|a_csnbuffer:oflow_node", which is child of megafunction instantiation "lpm_add_sub:Add0" +Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add0|addcore:adder[0]|a_csnbuffer:result_node", which is child of megafunction instantiation "lpm_add_sub:Add0" +Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add0|look_add:look_ahead_unit", which is child of megafunction instantiation "lpm_add_sub:Add0" +Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add0|altshift:result_ext_latency_ffs", which is child of megafunction instantiation "lpm_add_sub:Add0" +Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add0|altshift:carry_ext_latency_ffs", which is child of megafunction instantiation "lpm_add_sub:Add0" +Info (12130): Elaborated megafunction instantiation "lpm_add_sub:Add3" +Info (12133): Instantiated megafunction "lpm_add_sub:Add3" with the following parameter: Info (12134): Parameter "LPM_WIDTH" = "23" Info (12134): Parameter "LPM_DIRECTION" = "ADD" Info (12134): Parameter "LPM_REPRESENTATION" = "UNSIGNED" Info (12134): Parameter "ONE_INPUT_IS_CONSTANT" = "YES" -Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add2|addcore:adder[2]", which is child of megafunction instantiation "lpm_add_sub:Add2" -Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add2|addcore:adder[2]|a_csnbuffer:oflow_node", which is child of megafunction instantiation "lpm_add_sub:Add2" -Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add2|addcore:adder[2]|a_csnbuffer:result_node", which is child of megafunction instantiation "lpm_add_sub:Add2" -Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add2|addcore:adder[1]", which is child of megafunction instantiation "lpm_add_sub:Add2" -Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add2|look_add:look_ahead_unit", which is child of megafunction instantiation "lpm_add_sub:Add2" -Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add2|altshift:result_ext_latency_ffs", which is child of megafunction instantiation "lpm_add_sub:Add2" -Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add2|altshift:carry_ext_latency_ffs", which is child of megafunction instantiation "lpm_add_sub:Add2" -Info (13014): Ignored 23 buffer(s) - Info (13019): Ignored 23 SOFT buffer(s) +Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add3|addcore:adder[2]", which is child of megafunction instantiation "lpm_add_sub:Add3" +Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add3|look_add:look_ahead_unit", which is child of megafunction instantiation "lpm_add_sub:Add3" +Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add3|altshift:result_ext_latency_ffs", which is child of megafunction instantiation "lpm_add_sub:Add3" +Info (13014): Ignored 31 buffer(s) + Info (13019): Ignored 31 SOFT buffer(s) Info (280013): Promoted pin-driven signal(s) to global signal Info (280014): Promoted clock signal driven by pin "C7M" to global clock signal Info (280015): Promoted clear signal driven by pin "nRES" to global clear signal -Info (280013): Promoted pin-driven signal(s) to global signal - Info (280014): Promoted clock signal driven by pin "C7M" to global clock signal - Info (280015): Promoted clear signal driven by pin "nRES" to global clear signal -Warning (21074): Design contains 2 input pin(s) that do not drive logic +Warning (21074): Design contains 8 input pin(s) that do not drive logic Warning (15610): No output dependent on input pin "Q3" Warning (15610): No output dependent on input pin "PHI0in" -Info (21057): Implemented 169 device resources after synthesis - the final resource count might be different + Warning (15610): No output dependent on input pin "MODE" + Warning (15610): No output dependent on input pin "A[11]" + Warning (15610): No output dependent on input pin "A[12]" + Warning (15610): No output dependent on input pin "A[13]" + Warning (15610): No output dependent on input pin "A[14]" + Warning (15610): No output dependent on input pin "A[15]" +Info (21057): Implemented 170 device resources after synthesis - the final resource count might be different Info (21058): Implemented 27 input pins Info (21059): Implemented 20 output pins Info (21060): Implemented 16 bidirectional pins - Info (21063): Implemented 96 macrocells - Info (21073): Implemented 10 shareable expanders -Info (144001): Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg -Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 7 warnings - Info: Peak virtual memory: 308 megabytes - Info: Processing ended: Sat Aug 31 22:53:29 2019 - Info: Elapsed time: 00:00:10 - Info: Total CPU time (on all processors): 00:00:10 + Info (21063): Implemented 102 macrocells + Info (21073): Implemented 5 shareable expanders +Info (144001): Generated suppressed messages file C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg +Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 14 warnings + Info: Peak virtual memory: 4587 megabytes + Info: Processing ended: Sun Sep 01 20:44:14 2019 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:01 +------------------------------------------+ ; Analysis & Synthesis Suppressed Messages ; +------------------------------------------+ -The suppressed messages can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg. +The suppressed messages can be found in C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg. diff --git a/cpld/output_files/GR8RAM.map.smsg b/cpld/output_files/GR8RAM.map.smsg index 0842ca3..1e30372 100755 --- a/cpld/output_files/GR8RAM.map.smsg +++ b/cpld/output_files/GR8RAM.map.smsg @@ -1,3 +1,3 @@ -Warning (10273): Verilog HDL warning at GR8RAM.v(37): extended using "x" or "z" -Warning (10273): Verilog HDL warning at GR8RAM.v(45): extended using "x" or "z" -Warning (10268): Verilog HDL information at GR8RAM.v(164): always construct contains both blocking and non-blocking assignments +Warning (10273): Verilog HDL warning at GR8RAM.v(41): extended using "x" or "z" +Warning (10273): Verilog HDL warning at GR8RAM.v(49): extended using "x" or "z" +Warning (10268): Verilog HDL information at GR8RAM.v(177): always construct contains both blocking and non-blocking assignments diff --git a/cpld/output_files/GR8RAM.map.summary b/cpld/output_files/GR8RAM.map.summary index f195efc..f1ed85e 100755 --- a/cpld/output_files/GR8RAM.map.summary +++ b/cpld/output_files/GR8RAM.map.summary @@ -1,7 +1,7 @@ -Analysis & Synthesis Status : Successful - Sat Aug 31 22:53:29 2019 -Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition +Analysis & Synthesis Status : Successful - Sun Sep 01 20:44:14 2019 +Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition Revision Name : GR8RAM Top-level Entity Name : GR8RAM Family : MAX7000S -Total macrocells : 96 +Total macrocells : 102 Total pins : 63 diff --git a/cpld/output_files/GR8RAM.pin b/cpld/output_files/GR8RAM.pin index b81bcfc..f046df9 100755 --- a/cpld/output_files/GR8RAM.pin +++ b/cpld/output_files/GR8RAM.pin @@ -56,7 +56,7 @@ -- Pin directions (input, output or bidir) are based on device operating in user mode. --------------------------------------------------------------------------------- -Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition CHIP "GR8RAM" ASSIGNED TO AN: EPM7128SLC84-15 Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment diff --git a/cpld/output_files/GR8RAM.pof b/cpld/output_files/GR8RAM.pof index 72ea449..0df6d92 100755 Binary files a/cpld/output_files/GR8RAM.pof and b/cpld/output_files/GR8RAM.pof differ diff --git a/cpld/output_files/GR8RAM.sta.rpt b/cpld/output_files/GR8RAM.sta.rpt index 4f43da8..8915e81 100755 --- a/cpld/output_files/GR8RAM.sta.rpt +++ b/cpld/output_files/GR8RAM.sta.rpt @@ -1,6 +1,6 @@ TimeQuest Timing Analyzer report for GR8RAM -Sat Aug 31 22:53:51 2019 -Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +Sun Sep 01 20:44:17 2019 +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition --------------------- @@ -8,35 +8,36 @@ Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit --------------------- 1. Legal Notice 2. TimeQuest Timing Analyzer Summary - 3. Clocks - 4. Fmax Summary - 5. Setup Summary - 6. Hold Summary - 7. Recovery Summary - 8. Removal Summary - 9. Minimum Pulse Width Summary - 10. Setup: 'C7M' - 11. Setup: 'C7M_2' - 12. Hold: 'C7M_2' - 13. Hold: 'C7M' - 14. Minimum Pulse Width: 'C7M_2' - 15. Minimum Pulse Width: 'C7M' - 16. Setup Times - 17. Hold Times - 18. Clock to Output Times - 19. Minimum Clock to Output Times - 20. Propagation Delay - 21. Minimum Propagation Delay - 22. Output Enable Times - 23. Minimum Output Enable Times - 24. Output Disable Times - 25. Minimum Output Disable Times - 26. Setup Transfers - 27. Hold Transfers - 28. Report TCCS - 29. Report RSKM - 30. Unconstrained Paths - 31. TimeQuest Timing Analyzer Messages + 3. Parallel Compilation + 4. Clocks + 5. Fmax Summary + 6. Setup Summary + 7. Hold Summary + 8. Recovery Summary + 9. Removal Summary + 10. Minimum Pulse Width Summary + 11. Setup: 'C7M' + 12. Setup: 'C7M_2' + 13. Hold: 'C7M_2' + 14. Hold: 'C7M' + 15. Minimum Pulse Width: 'C7M_2' + 16. Minimum Pulse Width: 'C7M' + 17. Setup Times + 18. Hold Times + 19. Clock to Output Times + 20. Minimum Clock to Output Times + 21. Propagation Delay + 22. Minimum Propagation Delay + 23. Output Enable Times + 24. Minimum Output Enable Times + 25. Output Disable Times + 26. Minimum Output Disable Times + 27. Setup Transfers + 28. Hold Transfers + 29. Report TCCS + 30. Report RSKM + 31. Unconstrained Paths + 32. TimeQuest Timing Analyzer Messages @@ -72,6 +73,17 @@ applicable agreement for further details. +--------------------+-------------------------------------------------------------------+ +Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. ++-------------------------------------+ +; Parallel Compilation ; ++----------------------------+--------+ +; Processors ; Number ; ++----------------------------+--------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 1 ; ++----------------------------+--------+ + + +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Clocks ; +------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+ @@ -87,7 +99,7 @@ applicable agreement for further details. +-----------+-----------------+------------+------+ ; Fmax ; Restricted Fmax ; Clock Name ; Note ; +-----------+-----------------+------------+------+ -; 33.33 MHz ; 33.33 MHz ; C7M ; ; +; 20.83 MHz ; 20.83 MHz ; C7M ; ; +-----------+-----------------+------------+------+ This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. @@ -97,8 +109,8 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+---------+---------------+ ; Clock ; Slack ; End Point TNS ; +-------+---------+---------------+ -; C7M ; -29.000 ; -821.000 ; -; C7M_2 ; -5.500 ; -11.000 ; +; C7M ; -47.000 ; -1802.000 ; +; C7M_2 ; -27.500 ; -33.000 ; +-------+---------+---------------+ @@ -130,135 +142,135 @@ No paths to report. ; Clock ; Slack ; End Point TNS ; +-------+--------+---------------+ ; C7M_2 ; -5.500 ; -22.000 ; -; C7M ; -4.500 ; -414.000 ; +; C7M ; -4.500 ; -432.000 ; +-------+--------+---------------+ -+------------------------------------------------------------------------------------------------------+ -; Setup: 'C7M' ; -+---------+-----------+----------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+---------+-----------+----------+--------------+-------------+--------------+------------+------------+ -; -29.000 ; S[1] ; Addr[21] ; C7M ; C7M ; 1.000 ; 0.000 ; 26.000 ; -; -29.000 ; S[1] ; Addr[19] ; C7M ; C7M ; 1.000 ; 0.000 ; 26.000 ; -; -29.000 ; S[1] ; Addr[20] ; C7M ; C7M ; 1.000 ; 0.000 ; 26.000 ; -; -29.000 ; S[1] ; Addr[22] ; C7M ; C7M ; 1.000 ; 0.000 ; 26.000 ; -; -29.000 ; S[0] ; Addr[21] ; C7M ; C7M ; 1.000 ; 0.000 ; 26.000 ; -; -29.000 ; RAMSELreg ; Addr[21] ; C7M ; C7M ; 1.000 ; 0.000 ; 26.000 ; -; -29.000 ; S[2] ; Addr[21] ; C7M ; C7M ; 1.000 ; 0.000 ; 26.000 ; -; -29.000 ; S[0] ; Addr[19] ; C7M ; C7M ; 1.000 ; 0.000 ; 26.000 ; -; -29.000 ; RAMSELreg ; Addr[19] ; C7M ; C7M ; 1.000 ; 0.000 ; 26.000 ; -; -29.000 ; S[2] ; Addr[19] ; C7M ; C7M ; 1.000 ; 0.000 ; 26.000 ; -; -29.000 ; S[0] ; Addr[20] ; C7M ; C7M ; 1.000 ; 0.000 ; 26.000 ; -; -29.000 ; RAMSELreg ; Addr[20] ; C7M ; C7M ; 1.000 ; 0.000 ; 26.000 ; -; -29.000 ; S[2] ; Addr[20] ; C7M ; C7M ; 1.000 ; 0.000 ; 26.000 ; -; -29.000 ; S[0] ; Addr[22] ; C7M ; C7M ; 1.000 ; 0.000 ; 26.000 ; -; -29.000 ; RAMSELreg ; Addr[22] ; C7M ; C7M ; 1.000 ; 0.000 ; 26.000 ; -; -29.000 ; S[2] ; Addr[22] ; C7M ; C7M ; 1.000 ; 0.000 ; 26.000 ; -; -29.000 ; REGEN ; Addr[21] ; C7M ; C7M ; 1.000 ; 0.000 ; 26.000 ; -; -29.000 ; REGEN ; Addr[19] ; C7M ; C7M ; 1.000 ; 0.000 ; 26.000 ; -; -29.000 ; REGEN ; Addr[20] ; C7M ; C7M ; 1.000 ; 0.000 ; 26.000 ; -; -29.000 ; REGEN ; Addr[22] ; C7M ; C7M ; 1.000 ; 0.000 ; 26.000 ; -; -21.000 ; S[1] ; Addr[5] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; S[0] ; Addr[18] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; S[1] ; Addr[18] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; S[1] ; Addr[4] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; S[0] ; Addr[16] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; S[1] ; Addr[16] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; S[0] ; Addr[17] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; S[1] ; Addr[17] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; S[1] ; Addr[1] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; S[1] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; S[1] ; Addr[7] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; S[1] ; Addr[12] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; S[1] ; Addr[13] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; S[1] ; Addr[14] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; S[1] ; Addr[6] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; S[1] ; Addr[11] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; S[1] ; Addr[3] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; S[1] ; Addr[9] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; S[1] ; Addr[10] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; S[1] ; Addr[2] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; S[1] ; Addr[8] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; REGEN ; Bank[1] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; REGEN ; Bank[2] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; REGEN ; Bank[3] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; REGEN ; Bank[4] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; REGEN ; Bank[5] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; REGEN ; Bank[6] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; REGEN ; Bank[0] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; S[0] ; Addr[5] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; RAMSELreg ; Addr[5] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; S[2] ; Addr[5] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; S[2] ; Addr[18] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; REGEN ; Addr[18] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; RAMSELreg ; Addr[18] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; S[0] ; Addr[4] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; RAMSELreg ; Addr[4] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; S[2] ; Addr[4] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; S[2] ; Addr[16] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; REGEN ; Addr[16] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; RAMSELreg ; Addr[16] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; S[2] ; Addr[17] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; REGEN ; Addr[17] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; RAMSELreg ; Addr[17] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; S[0] ; Addr[1] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; RAMSELreg ; Addr[1] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; S[2] ; Addr[1] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; S[0] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; RAMSELreg ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; S[2] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; S[0] ; Addr[7] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; RAMSELreg ; Addr[7] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; S[2] ; Addr[7] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; S[0] ; Addr[12] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; RAMSELreg ; Addr[12] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; S[2] ; Addr[12] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; S[0] ; Addr[13] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; RAMSELreg ; Addr[13] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; S[2] ; Addr[13] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; S[0] ; Addr[14] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; RAMSELreg ; Addr[14] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; S[2] ; Addr[14] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; S[0] ; Addr[6] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; RAMSELreg ; Addr[6] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; S[2] ; Addr[6] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; S[0] ; Addr[11] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; RAMSELreg ; Addr[11] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; S[2] ; Addr[11] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; S[0] ; Addr[3] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; RAMSELreg ; Addr[3] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; S[2] ; Addr[3] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; S[0] ; Addr[9] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; RAMSELreg ; Addr[9] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; S[2] ; Addr[9] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; S[0] ; Addr[10] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; RAMSELreg ; Addr[10] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; S[2] ; Addr[10] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; S[0] ; Addr[2] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; RAMSELreg ; Addr[2] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; S[2] ; Addr[2] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -; -21.000 ; S[0] ; Addr[8] ; C7M ; C7M ; 1.000 ; 0.000 ; 18.000 ; -+---------+-----------+----------+--------------+-------------+--------------+------------+------------+ ++-------------------------------------------------------------------------------------------------------+ +; Setup: 'C7M' ; ++---------+-----------+-----------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++---------+-----------+-----------+--------------+-------------+--------------+------------+------------+ +; -47.000 ; REGEN ; RAMSELreg ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; +; -47.000 ; REGEN ; Addr[0] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; +; -47.000 ; REGEN ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; +; -47.000 ; REGEN ; Addr[7] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; +; -47.000 ; REGEN ; Addr[14] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; +; -47.000 ; REGEN ; Addr[6] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; +; -47.000 ; REGEN ; Addr[13] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; +; -47.000 ; REGEN ; Addr[5] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; +; -47.000 ; REGEN ; Addr[12] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; +; -47.000 ; REGEN ; Addr[4] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; +; -47.000 ; REGEN ; Addr[11] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; +; -47.000 ; REGEN ; Addr[16] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; +; -47.000 ; REGEN ; Addr[17] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; +; -47.000 ; REGEN ; Addr[18] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; +; -47.000 ; REGEN ; Addr[19] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; +; -47.000 ; REGEN ; Addr[3] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; +; -47.000 ; REGEN ; Addr[10] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; +; -47.000 ; REGEN ; Addr[2] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; +; -47.000 ; REGEN ; Addr[9] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; +; -47.000 ; REGEN ; Addr[1] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; +; -47.000 ; REGEN ; Addr[8] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; +; -47.000 ; REGEN ; ASel ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; +; -47.000 ; REGEN ; RASr ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; +; -47.000 ; REGEN ; CASr ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; +; -47.000 ; REGEN ; Bank[0] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; +; -47.000 ; REGEN ; Bank[1] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; +; -47.000 ; REGEN ; Bank[2] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; +; -47.000 ; REGEN ; Bank[3] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; +; -47.000 ; REGEN ; Bank[4] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; +; -47.000 ; REGEN ; Bank[5] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; +; -47.000 ; REGEN ; Bank[6] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; +; -47.000 ; REGEN ; Bank[7] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ; +; -25.000 ; PHI1reg ; S[2] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; PHI0seen ; S[2] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; S[1] ; S[2] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; S[2] ; S[2] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; S[0] ; S[2] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; PHI1reg ; S[1] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; PHI0seen ; S[1] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; S[0] ; S[1] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; S[1] ; S[1] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; S[2] ; S[1] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; PHI1reg ; S[0] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; PHI0seen ; S[0] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; S[0] ; S[0] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; S[1] ; S[0] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; S[2] ; S[0] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; S[0] ; REGEN ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; S[2] ; REGEN ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; S[1] ; REGEN ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; S[2] ; CSDBEN ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; S[2] ; IOROMEN ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; S[1] ; IOROMEN ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; S[0] ; IOROMEN ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; IOROMEN ; IOROMEN ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; S[2] ; RAMSELreg ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; S[0] ; RAMSELreg ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; S[1] ; RAMSELreg ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; RAMSELreg ; RAMSELreg ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; S[1] ; Addr[0] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; S[2] ; Addr[0] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; S[0] ; Addr[0] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; Addr[0] ; Addr[0] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; RAMSELreg ; Addr[0] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; S[2] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; S[1] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; S[0] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; Addr[15] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; Addr[0] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; Addr[1] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; Addr[2] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; Addr[3] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; Addr[4] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; Addr[5] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; Addr[6] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; Addr[7] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; Addr[8] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; Addr[9] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; Addr[10] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; Addr[11] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; Addr[12] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; Addr[13] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; Addr[14] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; RAMSELreg ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; S[2] ; Addr[7] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; S[1] ; Addr[7] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; S[0] ; Addr[7] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; Addr[7] ; Addr[7] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; Addr[0] ; Addr[7] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; Addr[1] ; Addr[7] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; Addr[2] ; Addr[7] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; Addr[3] ; Addr[7] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; Addr[4] ; Addr[7] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; Addr[5] ; Addr[7] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; Addr[6] ; Addr[7] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; RAMSELreg ; Addr[7] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; S[2] ; Addr[14] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; S[1] ; Addr[14] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; S[0] ; Addr[14] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; +; -25.000 ; Addr[14] ; Addr[14] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ; ++---------+-----------+-----------+--------------+-------------+--------------+------------+------------+ -+------------------------------------------------------------------------------------------------------------------------+ -; Setup: 'C7M_2' ; -+--------+-------------------------------+---------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+--------+-------------------------------+---------+--------------+-------------+--------------+------------+------------+ -; -5.500 ; S[2] ; CASf ; C7M ; C7M_2 ; 0.500 ; 7.000 ; 9.000 ; -; -5.500 ; S[1] ; CASf ; C7M ; C7M_2 ; 0.500 ; 7.000 ; 9.000 ; -; -5.500 ; S[0] ; CASf ; C7M ; C7M_2 ; 0.500 ; 7.000 ; 9.000 ; -; -5.500 ; REGEN ; RASf ; C7M ; C7M_2 ; 0.500 ; 7.000 ; 9.000 ; -; -5.500 ; S[2] ; RASf ; C7M ; C7M_2 ; 0.500 ; 7.000 ; 9.000 ; -; -5.500 ; S[1] ; RASf ; C7M ; C7M_2 ; 0.500 ; 7.000 ; 9.000 ; -; -5.500 ; S[0] ; RASf ; C7M ; C7M_2 ; 0.500 ; 7.000 ; 9.000 ; -; -5.500 ; lpm_counter:Ref_rtl_0|dffs[3] ; RASf ; C7M ; C7M_2 ; 0.500 ; 7.000 ; 9.000 ; -; -5.500 ; lpm_counter:Ref_rtl_0|dffs[1] ; RASf ; C7M ; C7M_2 ; 0.500 ; 7.000 ; 9.000 ; -; -5.500 ; lpm_counter:Ref_rtl_0|dffs[0] ; RASf ; C7M ; C7M_2 ; 0.500 ; 7.000 ; 9.000 ; -; -5.500 ; lpm_counter:Ref_rtl_0|dffs[2] ; RASf ; C7M ; C7M_2 ; 0.500 ; 7.000 ; 9.000 ; -+--------+-------------------------------+---------+--------------+-------------+--------------+------------+------------+ ++-------------------------------------------------------------------------------------------------------------------------+ +; Setup: 'C7M_2' ; ++---------+-------------------------------+---------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++---------+-------------------------------+---------+--------------+-------------+--------------+------------+------------+ +; -27.500 ; REGEN ; RASf ; C7M ; C7M_2 ; 0.500 ; 20.000 ; 44.000 ; +; -5.500 ; S[2] ; CASf ; C7M ; C7M_2 ; 0.500 ; 20.000 ; 22.000 ; +; -5.500 ; S[1] ; CASf ; C7M ; C7M_2 ; 0.500 ; 20.000 ; 22.000 ; +; -5.500 ; S[0] ; CASf ; C7M ; C7M_2 ; 0.500 ; 20.000 ; 22.000 ; +; -5.500 ; S[0] ; RASf ; C7M ; C7M_2 ; 0.500 ; 20.000 ; 22.000 ; +; -5.500 ; S[2] ; RASf ; C7M ; C7M_2 ; 0.500 ; 20.000 ; 22.000 ; +; -5.500 ; S[1] ; RASf ; C7M ; C7M_2 ; 0.500 ; 20.000 ; 22.000 ; +; -5.500 ; lpm_counter:Ref_rtl_0|dffs[3] ; RASf ; C7M ; C7M_2 ; 0.500 ; 20.000 ; 22.000 ; +; -5.500 ; lpm_counter:Ref_rtl_0|dffs[2] ; RASf ; C7M ; C7M_2 ; 0.500 ; 20.000 ; 22.000 ; +; -5.500 ; lpm_counter:Ref_rtl_0|dffs[1] ; RASf ; C7M ; C7M_2 ; 0.500 ; 20.000 ; 22.000 ; +; -5.500 ; lpm_counter:Ref_rtl_0|dffs[0] ; RASf ; C7M ; C7M_2 ; 0.500 ; 20.000 ; 22.000 ; ++---------+-------------------------------+---------+--------------+-------------+--------------+------------+------------+ +------------------------------------------------------------------------------------------------------------------------+ @@ -266,126 +278,126 @@ No paths to report. +--------+-------------------------------+---------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+-------------------------------+---------+--------------+-------------+--------------+------------+------------+ -; -1.500 ; S[2] ; CASf ; C7M ; C7M_2 ; -0.500 ; 7.000 ; 9.000 ; -; -1.500 ; S[1] ; CASf ; C7M ; C7M_2 ; -0.500 ; 7.000 ; 9.000 ; -; -1.500 ; S[0] ; CASf ; C7M ; C7M_2 ; -0.500 ; 7.000 ; 9.000 ; -; -1.500 ; REGEN ; RASf ; C7M ; C7M_2 ; -0.500 ; 7.000 ; 9.000 ; -; -1.500 ; S[2] ; RASf ; C7M ; C7M_2 ; -0.500 ; 7.000 ; 9.000 ; -; -1.500 ; S[1] ; RASf ; C7M ; C7M_2 ; -0.500 ; 7.000 ; 9.000 ; -; -1.500 ; S[0] ; RASf ; C7M ; C7M_2 ; -0.500 ; 7.000 ; 9.000 ; -; -1.500 ; lpm_counter:Ref_rtl_0|dffs[3] ; RASf ; C7M ; C7M_2 ; -0.500 ; 7.000 ; 9.000 ; -; -1.500 ; lpm_counter:Ref_rtl_0|dffs[1] ; RASf ; C7M ; C7M_2 ; -0.500 ; 7.000 ; 9.000 ; -; -1.500 ; lpm_counter:Ref_rtl_0|dffs[0] ; RASf ; C7M ; C7M_2 ; -0.500 ; 7.000 ; 9.000 ; -; -1.500 ; lpm_counter:Ref_rtl_0|dffs[2] ; RASf ; C7M ; C7M_2 ; -0.500 ; 7.000 ; 9.000 ; +; -1.500 ; S[2] ; CASf ; C7M ; C7M_2 ; -0.500 ; 20.000 ; 22.000 ; +; -1.500 ; S[1] ; CASf ; C7M ; C7M_2 ; -0.500 ; 20.000 ; 22.000 ; +; -1.500 ; S[0] ; CASf ; C7M ; C7M_2 ; -0.500 ; 20.000 ; 22.000 ; +; -1.500 ; S[0] ; RASf ; C7M ; C7M_2 ; -0.500 ; 20.000 ; 22.000 ; +; -1.500 ; S[2] ; RASf ; C7M ; C7M_2 ; -0.500 ; 20.000 ; 22.000 ; +; -1.500 ; S[1] ; RASf ; C7M ; C7M_2 ; -0.500 ; 20.000 ; 22.000 ; +; -1.500 ; lpm_counter:Ref_rtl_0|dffs[3] ; RASf ; C7M ; C7M_2 ; -0.500 ; 20.000 ; 22.000 ; +; -1.500 ; lpm_counter:Ref_rtl_0|dffs[2] ; RASf ; C7M ; C7M_2 ; -0.500 ; 20.000 ; 22.000 ; +; -1.500 ; lpm_counter:Ref_rtl_0|dffs[1] ; RASf ; C7M ; C7M_2 ; -0.500 ; 20.000 ; 22.000 ; +; -1.500 ; lpm_counter:Ref_rtl_0|dffs[0] ; RASf ; C7M ; C7M_2 ; -0.500 ; 20.000 ; 22.000 ; +; 20.500 ; REGEN ; RASf ; C7M ; C7M_2 ; -0.500 ; 20.000 ; 44.000 ; +--------+-------------------------------+---------+--------------+-------------+--------------+------------+------------+ -+-----------------------------------------------------------------------------------------------------+ -; Hold: 'C7M' ; -+-------+-----------+-----------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+-------+-----------+-----------+--------------+-------------+--------------+------------+------------+ -; 5.000 ; PHI0seen ; S[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; PHI1reg ; S[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; S[1] ; S[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; S[0] ; S[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; S[2] ; S[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; PHI0seen ; S[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; PHI1reg ; S[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; S[1] ; S[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; S[2] ; S[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; S[0] ; S[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; PHI0seen ; S[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; PHI1reg ; S[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; S[0] ; S[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; S[2] ; S[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; S[1] ; S[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; S[2] ; REGEN ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; S[1] ; REGEN ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; S[0] ; REGEN ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; S[2] ; CSDBEN ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; IOROMEN ; IOROMEN ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; S[2] ; IOROMEN ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; S[1] ; IOROMEN ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; S[0] ; IOROMEN ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; REGEN ; RAMSELreg ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; S[2] ; RAMSELreg ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; S[1] ; RAMSELreg ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; S[0] ; RAMSELreg ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[0] ; Addr[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; S[0] ; Addr[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; S[1] ; Addr[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; S[2] ; Addr[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; REGEN ; Addr[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; RAMSELreg ; Addr[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[21] ; Addr[21] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[20] ; Addr[21] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[19] ; Addr[21] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[18] ; Addr[21] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[17] ; Addr[21] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[16] ; Addr[21] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[2] ; Addr[21] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[3] ; Addr[21] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[6] ; Addr[21] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[7] ; Addr[21] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[0] ; Addr[21] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[1] ; Addr[21] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[4] ; Addr[21] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[5] ; Addr[21] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[12] ; Addr[21] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[13] ; Addr[21] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[8] ; Addr[21] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[9] ; Addr[21] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[11] ; Addr[21] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[10] ; Addr[21] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[14] ; Addr[21] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[15] ; Addr[21] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[5] ; Addr[5] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; S[0] ; Addr[5] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; S[2] ; Addr[5] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; S[1] ; Addr[5] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; REGEN ; Addr[5] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[4] ; Addr[5] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[3] ; Addr[5] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[2] ; Addr[5] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[0] ; Addr[5] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[1] ; Addr[5] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[18] ; Addr[18] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[17] ; Addr[18] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[16] ; Addr[18] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[2] ; Addr[18] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[3] ; Addr[18] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[6] ; Addr[18] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[7] ; Addr[18] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[0] ; Addr[18] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[1] ; Addr[18] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[4] ; Addr[18] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[5] ; Addr[18] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[12] ; Addr[18] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[13] ; Addr[18] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[8] ; Addr[18] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[9] ; Addr[18] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[11] ; Addr[18] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[10] ; Addr[18] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[14] ; Addr[18] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[15] ; Addr[18] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[19] ; Addr[19] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[18] ; Addr[19] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[17] ; Addr[19] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[16] ; Addr[19] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[2] ; Addr[19] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[3] ; Addr[19] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[6] ; Addr[19] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[7] ; Addr[19] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[0] ; Addr[19] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[1] ; Addr[19] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[4] ; Addr[19] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[5] ; Addr[19] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[12] ; Addr[19] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[13] ; Addr[19] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[8] ; Addr[19] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[9] ; Addr[19] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -+-------+-----------+-----------+--------------+-------------+--------------+------------+------------+ ++----------------------------------------------------------------------------------------------------------------------------------------------+ +; Hold: 'C7M' ; ++--------+-------------------------------+-------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+-------------------------------+-------------------------------+--------------+-------------+--------------+------------+------------+ +; 5.000 ; IOROMEN ; IOROMEN ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; +; 5.000 ; RAMSELreg ; RAMSELreg ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; +; 5.000 ; Addr[0] ; Addr[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; +; 5.000 ; Addr[15] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; +; 5.000 ; Addr[7] ; Addr[7] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; +; 5.000 ; Addr[14] ; Addr[14] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; +; 5.000 ; Addr[6] ; Addr[6] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; +; 5.000 ; Addr[13] ; Addr[13] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; +; 5.000 ; Addr[5] ; Addr[5] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; +; 5.000 ; Addr[12] ; Addr[12] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; +; 5.000 ; Addr[4] ; Addr[4] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; +; 5.000 ; Addr[11] ; Addr[11] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; +; 5.000 ; Addr[16] ; Addr[16] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; +; 5.000 ; Addr[17] ; Addr[17] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; +; 5.000 ; Addr[18] ; Addr[18] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; +; 5.000 ; Addr[19] ; Addr[19] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; +; 5.000 ; Addr[3] ; Addr[3] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; +; 5.000 ; Addr[10] ; Addr[10] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; +; 5.000 ; Addr[2] ; Addr[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; +; 5.000 ; Addr[9] ; Addr[9] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; +; 5.000 ; Addr[1] ; Addr[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; +; 5.000 ; Addr[8] ; Addr[8] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; +; 5.000 ; lpm_counter:Ref_rtl_0|dffs[2] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; +; 5.000 ; lpm_counter:Ref_rtl_0|dffs[3] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; +; 5.000 ; lpm_counter:Ref_rtl_0|dffs[1] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; +; 5.000 ; lpm_counter:Ref_rtl_0|dffs[0] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; +; 5.000 ; S[2] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; +; 5.000 ; S[1] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; +; 5.000 ; S[0] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; +; 5.000 ; lpm_counter:Ref_rtl_0|dffs[1] ; lpm_counter:Ref_rtl_0|dffs[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; +; 5.000 ; lpm_counter:Ref_rtl_0|dffs[3] ; lpm_counter:Ref_rtl_0|dffs[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; +; 5.000 ; lpm_counter:Ref_rtl_0|dffs[0] ; lpm_counter:Ref_rtl_0|dffs[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; +; 5.000 ; lpm_counter:Ref_rtl_0|dffs[2] ; lpm_counter:Ref_rtl_0|dffs[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; +; 5.000 ; S[2] ; lpm_counter:Ref_rtl_0|dffs[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; +; 5.000 ; S[1] ; lpm_counter:Ref_rtl_0|dffs[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; +; 5.000 ; S[0] ; lpm_counter:Ref_rtl_0|dffs[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; +; 5.000 ; lpm_counter:Ref_rtl_0|dffs[1] ; lpm_counter:Ref_rtl_0|dffs[3] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; +; 5.000 ; lpm_counter:Ref_rtl_0|dffs[0] ; lpm_counter:Ref_rtl_0|dffs[3] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; +; 5.000 ; lpm_counter:Ref_rtl_0|dffs[2] ; lpm_counter:Ref_rtl_0|dffs[3] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; +; 5.000 ; lpm_counter:Ref_rtl_0|dffs[3] ; lpm_counter:Ref_rtl_0|dffs[3] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; +; 5.000 ; S[2] ; lpm_counter:Ref_rtl_0|dffs[3] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; +; 5.000 ; S[1] ; lpm_counter:Ref_rtl_0|dffs[3] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; +; 5.000 ; S[0] ; lpm_counter:Ref_rtl_0|dffs[3] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; +; 5.000 ; lpm_counter:Ref_rtl_0|dffs[0] ; lpm_counter:Ref_rtl_0|dffs[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; +; 5.000 ; lpm_counter:Ref_rtl_0|dffs[3] ; lpm_counter:Ref_rtl_0|dffs[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; +; 5.000 ; lpm_counter:Ref_rtl_0|dffs[2] ; lpm_counter:Ref_rtl_0|dffs[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; +; 5.000 ; S[2] ; lpm_counter:Ref_rtl_0|dffs[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; +; 5.000 ; S[1] ; lpm_counter:Ref_rtl_0|dffs[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; +; 5.000 ; S[0] ; lpm_counter:Ref_rtl_0|dffs[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; +; 18.000 ; PHI1reg ; S[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; PHI0seen ; S[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; S[1] ; S[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; S[2] ; S[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; S[0] ; S[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; PHI1reg ; S[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; PHI0seen ; S[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; S[0] ; S[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; S[1] ; S[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; S[2] ; S[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; PHI1reg ; S[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; PHI0seen ; S[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; S[0] ; S[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; S[1] ; S[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; S[2] ; S[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; S[0] ; REGEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; S[2] ; REGEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; S[1] ; REGEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; S[2] ; CSDBEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; S[2] ; IOROMEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; S[1] ; IOROMEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; S[0] ; IOROMEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; S[2] ; RAMSELreg ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; S[0] ; RAMSELreg ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; S[1] ; RAMSELreg ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; S[1] ; Addr[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; S[2] ; Addr[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; S[0] ; Addr[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; RAMSELreg ; Addr[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; S[2] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; S[1] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; S[0] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; Addr[0] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; Addr[1] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; Addr[2] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; Addr[3] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; Addr[4] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; Addr[5] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; Addr[6] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; Addr[7] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; Addr[8] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; Addr[9] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; Addr[10] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; Addr[11] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; Addr[12] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; Addr[13] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; Addr[14] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; RAMSELreg ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; S[2] ; Addr[7] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; S[1] ; Addr[7] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; +; 18.000 ; S[0] ; Addr[7] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; ++--------+-------------------------------+-------------------------------+--------------+-------------+--------------+------------+------------+ +------------------------------------------------------------------------------------------------+ @@ -401,8 +413,8 @@ No paths to report. ; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; C7M_2 ; Rise ; C7M_2|dataout ; ; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; C7M_2 ; Rise ; CASf|[4] ; ; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; C7M_2 ; Rise ; CASf|[4] ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; C7M_2 ; Rise ; RASf|[14] ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; C7M_2 ; Rise ; RASf|[14] ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; C7M_2 ; Rise ; RASf|[9] ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; C7M_2 ; Rise ; RASf|[9] ; +--------+--------------+----------------+------------------+-------+------------+---------------+ @@ -473,10 +485,14 @@ No paths to report. ; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Bank[5] ; ; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Bank[6] ; ; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Bank[6] ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Bank[7] ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Bank[7] ; ; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; CASr ; ; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; CASr ; ; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; CSDBEN ; ; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; CSDBEN ; +; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; IOBank0 ; +; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; IOBank0 ; ; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; IOROMEN ; ; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; IOROMEN ; ; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; PHI0seen ; @@ -507,52 +523,48 @@ No paths to report. ; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; C7M ; Rise ; ASel|clk ; ; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; C7M ; Rise ; Addr[0]|clk ; ; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; C7M ; Rise ; Addr[0]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; C7M ; Rise ; Addr[10]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; C7M ; Rise ; Addr[10]|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; C7M ; Rise ; Addr[11]|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; C7M ; Rise ; Addr[11]|clk ; +--------+--------------+----------------+------------------+-------+------------+-------------------------------+ -+-------------------------------------------------------------------------+ -; Setup Times ; -+-----------+------------+--------+--------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-----------+------------+--------+--------+------------+-----------------+ -; A[*] ; C7M ; 28.000 ; 28.000 ; Rise ; C7M ; -; A[0] ; C7M ; 28.000 ; 28.000 ; Rise ; C7M ; -; A[1] ; C7M ; 28.000 ; 28.000 ; Rise ; C7M ; -; A[2] ; C7M ; 28.000 ; 28.000 ; Rise ; C7M ; -; A[3] ; C7M ; 28.000 ; 28.000 ; Rise ; C7M ; -; A[4] ; C7M ; 11.000 ; 11.000 ; Rise ; C7M ; -; A[5] ; C7M ; 11.000 ; 11.000 ; Rise ; C7M ; -; A[6] ; C7M ; 11.000 ; 11.000 ; Rise ; C7M ; -; A[7] ; C7M ; 11.000 ; 11.000 ; Rise ; C7M ; -; A[8] ; C7M ; 11.000 ; 11.000 ; Rise ; C7M ; -; A[9] ; C7M ; 11.000 ; 11.000 ; Rise ; C7M ; -; A[10] ; C7M ; 11.000 ; 11.000 ; Rise ; C7M ; -; D[*] ; C7M ; 11.000 ; 11.000 ; Rise ; C7M ; -; D[0] ; C7M ; 11.000 ; 11.000 ; Rise ; C7M ; -; D[1] ; C7M ; 11.000 ; 11.000 ; Rise ; C7M ; -; D[2] ; C7M ; 11.000 ; 11.000 ; Rise ; C7M ; -; D[3] ; C7M ; 11.000 ; 11.000 ; Rise ; C7M ; -; D[4] ; C7M ; 11.000 ; 11.000 ; Rise ; C7M ; -; D[5] ; C7M ; 11.000 ; 11.000 ; Rise ; C7M ; -; D[6] ; C7M ; 11.000 ; 11.000 ; Rise ; C7M ; -; D[7] ; C7M ; 11.000 ; 11.000 ; Rise ; C7M ; -; PHI1in ; C7M ; 83.000 ; 83.000 ; Rise ; C7M ; -; nDEVSEL ; C7M ; 28.000 ; 28.000 ; Rise ; C7M ; -; nIOSEL ; C7M ; 11.000 ; 11.000 ; Rise ; C7M ; -; nIOSTRB ; C7M ; 11.000 ; 11.000 ; Rise ; C7M ; -; nWE ; C7M ; 28.000 ; 28.000 ; Rise ; C7M ; -; A[*] ; C7M_2 ; 4.000 ; 4.000 ; Fall ; C7M_2 ; -; A[0] ; C7M_2 ; 4.000 ; 4.000 ; Fall ; C7M_2 ; -; A[1] ; C7M_2 ; 4.000 ; 4.000 ; Fall ; C7M_2 ; -; A[2] ; C7M_2 ; 4.000 ; 4.000 ; Fall ; C7M_2 ; -; A[3] ; C7M_2 ; 4.000 ; 4.000 ; Fall ; C7M_2 ; -; nDEVSEL ; C7M_2 ; 4.000 ; 4.000 ; Fall ; C7M_2 ; -; nWE ; C7M_2 ; 4.000 ; 4.000 ; Fall ; C7M_2 ; -+-----------+------------+--------+--------+------------+-----------------+ ++---------------------------------------------------------------------------+ +; Setup Times ; ++-----------+------------+---------+---------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+---------+---------+------------+-----------------+ +; A[*] ; C7M ; 46.000 ; 46.000 ; Rise ; C7M ; +; A[0] ; C7M ; 46.000 ; 46.000 ; Rise ; C7M ; +; A[1] ; C7M ; 46.000 ; 46.000 ; Rise ; C7M ; +; A[2] ; C7M ; 46.000 ; 46.000 ; Rise ; C7M ; +; A[3] ; C7M ; 46.000 ; 46.000 ; Rise ; C7M ; +; A[4] ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ; +; A[5] ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ; +; A[6] ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ; +; A[7] ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ; +; A[8] ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ; +; A[9] ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ; +; A[10] ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ; +; D[*] ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ; +; D[0] ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ; +; D[1] ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ; +; D[2] ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ; +; D[3] ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ; +; D[4] ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ; +; D[5] ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ; +; D[6] ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ; +; D[7] ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ; +; PHI1in ; C7M ; 244.000 ; 244.000 ; Rise ; C7M ; +; nDEVSEL ; C7M ; 46.000 ; 46.000 ; Rise ; C7M ; +; nIOSEL ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ; +; nIOSTRB ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ; +; nWE ; C7M ; 46.000 ; 46.000 ; Rise ; C7M ; +; A[*] ; C7M_2 ; 26.000 ; 26.000 ; Fall ; C7M_2 ; +; A[0] ; C7M_2 ; 26.000 ; 26.000 ; Fall ; C7M_2 ; +; A[1] ; C7M_2 ; 26.000 ; 26.000 ; Fall ; C7M_2 ; +; A[2] ; C7M_2 ; 26.000 ; 26.000 ; Fall ; C7M_2 ; +; A[3] ; C7M_2 ; 26.000 ; 26.000 ; Fall ; C7M_2 ; +; nDEVSEL ; C7M_2 ; 26.000 ; 26.000 ; Fall ; C7M_2 ; +; nWE ; C7M_2 ; 4.000 ; 4.000 ; Fall ; C7M_2 ; ++-----------+------------+---------+---------+------------+-----------------+ +---------------------------------------------------------------------------+ @@ -560,38 +572,38 @@ No paths to report. +-----------+------------+---------+---------+------------+-----------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+---------+---------+------------+-----------------+ -; A[*] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ; -; A[0] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ; -; A[1] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ; -; A[2] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ; -; A[3] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ; -; A[4] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ; -; A[5] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ; -; A[6] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ; -; A[7] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ; -; A[8] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ; -; A[9] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ; -; A[10] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ; -; D[*] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ; -; D[0] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ; -; D[1] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ; -; D[2] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ; -; D[3] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ; -; D[4] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ; -; D[5] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ; -; D[6] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ; -; D[7] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ; -; PHI1in ; C7M ; -12.000 ; -12.000 ; Rise ; C7M ; -; nDEVSEL ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ; -; nIOSEL ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ; -; nIOSTRB ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ; -; nWE ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ; -; A[*] ; C7M_2 ; 4.000 ; 4.000 ; Fall ; C7M_2 ; -; A[0] ; C7M_2 ; 4.000 ; 4.000 ; Fall ; C7M_2 ; -; A[1] ; C7M_2 ; 4.000 ; 4.000 ; Fall ; C7M_2 ; -; A[2] ; C7M_2 ; 4.000 ; 4.000 ; Fall ; C7M_2 ; -; A[3] ; C7M_2 ; 4.000 ; 4.000 ; Fall ; C7M_2 ; -; nDEVSEL ; C7M_2 ; 4.000 ; 4.000 ; Fall ; C7M_2 ; +; A[*] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ; +; A[0] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ; +; A[1] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ; +; A[2] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ; +; A[3] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ; +; A[4] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ; +; A[5] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ; +; A[6] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ; +; A[7] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ; +; A[8] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ; +; A[9] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ; +; A[10] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ; +; D[*] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ; +; D[0] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ; +; D[1] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ; +; D[2] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ; +; D[3] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ; +; D[4] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ; +; D[5] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ; +; D[6] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ; +; D[7] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ; +; PHI1in ; C7M ; -38.000 ; -38.000 ; Rise ; C7M ; +; nDEVSEL ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ; +; nIOSEL ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ; +; nIOSTRB ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ; +; nWE ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ; +; A[*] ; C7M_2 ; -18.000 ; -18.000 ; Fall ; C7M_2 ; +; A[0] ; C7M_2 ; -18.000 ; -18.000 ; Fall ; C7M_2 ; +; A[1] ; C7M_2 ; -18.000 ; -18.000 ; Fall ; C7M_2 ; +; A[2] ; C7M_2 ; -18.000 ; -18.000 ; Fall ; C7M_2 ; +; A[3] ; C7M_2 ; -18.000 ; -18.000 ; Fall ; C7M_2 ; +; nDEVSEL ; C7M_2 ; -18.000 ; -18.000 ; Fall ; C7M_2 ; ; nWE ; C7M_2 ; 4.000 ; 4.000 ; Fall ; C7M_2 ; +-----------+------------+---------+---------+------------+-----------------+ @@ -610,15 +622,15 @@ No paths to report. ; D[5] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ; ; D[6] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ; ; D[7] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ; -; RA[*] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ; +; RA[*] ; C7M ; 29.000 ; 29.000 ; Rise ; C7M ; ; RA[0] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ; ; RA[1] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ; ; RA[2] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ; -; RA[3] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ; -; RA[4] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ; -; RA[5] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ; -; RA[6] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ; -; RA[7] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ; +; RA[3] ; C7M ; 29.000 ; 29.000 ; Rise ; C7M ; +; RA[4] ; C7M ; 29.000 ; 29.000 ; Rise ; C7M ; +; RA[5] ; C7M ; 29.000 ; 29.000 ; Rise ; C7M ; +; RA[6] ; C7M ; 29.000 ; 29.000 ; Rise ; C7M ; +; RA[7] ; C7M ; 29.000 ; 29.000 ; Rise ; C7M ; ; RA[8] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ; ; RA[9] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ; ; RA[10] ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ; @@ -628,9 +640,9 @@ No paths to report. ; nRCS ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ; ; C7Mout ; C7M_2 ; 19.000 ; 19.000 ; Rise ; C7M_2 ; ; C7Mout ; C7M_2 ; 19.000 ; 19.000 ; Fall ; C7M_2 ; -; nCAS0 ; C7M_2 ; 28.000 ; 28.000 ; Fall ; C7M_2 ; -; nCAS1 ; C7M_2 ; 28.000 ; 28.000 ; Fall ; C7M_2 ; -; nRAS ; C7M_2 ; 28.000 ; 28.000 ; Fall ; C7M_2 ; +; nCAS0 ; C7M_2 ; 41.000 ; 41.000 ; Fall ; C7M_2 ; +; nCAS1 ; C7M_2 ; 41.000 ; 41.000 ; Fall ; C7M_2 ; +; nRAS ; C7M_2 ; 41.000 ; 41.000 ; Fall ; C7M_2 ; +-----------+------------+--------+--------+------------+-----------------+ @@ -666,171 +678,132 @@ No paths to report. ; nRCS ; C7M ; 21.000 ; 21.000 ; Rise ; C7M ; ; C7Mout ; C7M_2 ; 19.000 ; 19.000 ; Rise ; C7M_2 ; ; C7Mout ; C7M_2 ; 19.000 ; 19.000 ; Fall ; C7M_2 ; -; nCAS0 ; C7M_2 ; 28.000 ; 28.000 ; Fall ; C7M_2 ; -; nCAS1 ; C7M_2 ; 28.000 ; 28.000 ; Fall ; C7M_2 ; -; nRAS ; C7M_2 ; 28.000 ; 28.000 ; Fall ; C7M_2 ; +; nCAS0 ; C7M_2 ; 41.000 ; 41.000 ; Fall ; C7M_2 ; +; nCAS1 ; C7M_2 ; 41.000 ; 41.000 ; Fall ; C7M_2 ; +; nRAS ; C7M_2 ; 41.000 ; 41.000 ; Fall ; C7M_2 ; +-----------+------------+--------+--------+------------+-----------------+ -+--------------------------------------------------------------+ -; Propagation Delay ; -+------------+-------------+--------+--------+--------+--------+ -; Input Port ; Output Port ; RR ; RF ; FR ; FF ; -+------------+-------------+--------+--------+--------+--------+ -; A[0] ; D[0] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; -; A[0] ; D[1] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; -; A[0] ; D[2] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; -; A[0] ; D[3] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; -; A[0] ; D[4] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; -; A[0] ; D[5] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; -; A[0] ; D[6] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; -; A[0] ; D[7] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; -; A[1] ; D[0] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; -; A[1] ; D[1] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; -; A[1] ; D[2] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; -; A[1] ; D[3] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; -; A[1] ; D[4] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; -; A[1] ; D[5] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; -; A[1] ; D[6] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; -; A[1] ; D[7] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; -; A[2] ; D[0] ; ; 19.000 ; 19.000 ; ; -; A[2] ; D[1] ; ; 19.000 ; 19.000 ; ; -; A[2] ; D[2] ; ; 19.000 ; 19.000 ; ; -; A[2] ; D[3] ; ; 19.000 ; 19.000 ; ; -; A[2] ; D[4] ; ; 19.000 ; 19.000 ; ; -; A[2] ; D[5] ; ; 19.000 ; 19.000 ; ; -; A[2] ; D[6] ; ; 19.000 ; 19.000 ; ; -; A[2] ; D[7] ; ; 19.000 ; 19.000 ; ; -; A[3] ; D[0] ; ; 19.000 ; 19.000 ; ; -; A[3] ; D[1] ; ; 19.000 ; 19.000 ; ; -; A[3] ; D[2] ; ; 19.000 ; 19.000 ; ; -; A[3] ; D[3] ; ; 19.000 ; 19.000 ; ; -; A[3] ; D[4] ; ; 19.000 ; 19.000 ; ; -; A[3] ; D[5] ; ; 19.000 ; 19.000 ; ; -; A[3] ; D[6] ; ; 19.000 ; 19.000 ; ; -; A[3] ; D[7] ; ; 19.000 ; 19.000 ; ; -; A[11] ; RA[0] ; 19.000 ; ; ; 19.000 ; -; A[12] ; nINH ; 15.000 ; ; ; 15.000 ; -; A[13] ; nINH ; 15.000 ; ; ; 15.000 ; -; A[14] ; nINH ; 15.000 ; ; ; 15.000 ; -; A[15] ; nINH ; 15.000 ; ; ; 15.000 ; -; D[0] ; RD[0] ; 19.000 ; ; ; 19.000 ; -; D[1] ; RD[1] ; 19.000 ; ; ; 19.000 ; -; D[2] ; RD[2] ; 19.000 ; ; ; 19.000 ; -; D[3] ; RD[3] ; 19.000 ; ; ; 19.000 ; -; D[4] ; RD[4] ; 19.000 ; ; ; 19.000 ; -; D[5] ; RD[5] ; 19.000 ; ; ; 19.000 ; -; D[6] ; RD[6] ; 19.000 ; ; ; 19.000 ; -; D[7] ; RD[7] ; 19.000 ; ; ; 19.000 ; -; MODE ; nINH ; ; 15.000 ; 15.000 ; ; -; PHI1in ; PHI1out ; 82.000 ; ; ; 82.000 ; -; RD[0] ; D[0] ; 19.000 ; ; ; 19.000 ; -; RD[1] ; D[1] ; 19.000 ; ; ; 19.000 ; -; RD[2] ; D[2] ; 19.000 ; ; ; 19.000 ; -; RD[3] ; D[3] ; 19.000 ; ; ; 19.000 ; -; RD[4] ; D[4] ; 19.000 ; ; ; 19.000 ; -; RD[5] ; D[5] ; 19.000 ; ; ; 19.000 ; -; RD[6] ; D[6] ; 19.000 ; ; ; 19.000 ; -; RD[7] ; D[7] ; 19.000 ; ; ; 19.000 ; -; nDEVSEL ; D[0] ; 19.000 ; 26.000 ; 26.000 ; 19.000 ; -; nDEVSEL ; D[1] ; 19.000 ; 26.000 ; 26.000 ; 19.000 ; -; nDEVSEL ; D[2] ; 19.000 ; 26.000 ; 26.000 ; 19.000 ; -; nDEVSEL ; D[3] ; 19.000 ; 26.000 ; 26.000 ; 19.000 ; -; nDEVSEL ; D[4] ; 19.000 ; 26.000 ; 26.000 ; 19.000 ; -; nDEVSEL ; D[5] ; 19.000 ; 26.000 ; 26.000 ; 19.000 ; -; nDEVSEL ; D[6] ; 19.000 ; 26.000 ; 26.000 ; 19.000 ; -; nDEVSEL ; D[7] ; 19.000 ; 26.000 ; 26.000 ; 19.000 ; -; nDEVSEL ; RA[0] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; -; nDEVSEL ; RA[1] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; -; nDEVSEL ; RA[2] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; -; nDEVSEL ; RA[3] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; -; nDEVSEL ; RA[4] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; -; nDEVSEL ; RA[5] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; -; nDEVSEL ; RA[6] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; -; nDEVSEL ; RA[7] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; -; nDEVSEL ; RD[0] ; 26.000 ; ; ; 26.000 ; -; nDEVSEL ; RD[1] ; 26.000 ; ; ; 26.000 ; -; nDEVSEL ; RD[2] ; 26.000 ; ; ; 26.000 ; -; nDEVSEL ; RD[3] ; 26.000 ; ; ; 26.000 ; -; nDEVSEL ; RD[4] ; 26.000 ; ; ; 26.000 ; -; nDEVSEL ; RD[5] ; 26.000 ; ; ; 26.000 ; -; nDEVSEL ; RD[6] ; 26.000 ; ; ; 26.000 ; -; nDEVSEL ; RD[7] ; 26.000 ; ; ; 26.000 ; -; nDEVSEL ; nCAS0 ; ; 19.000 ; 19.000 ; ; -; nDEVSEL ; nCAS1 ; ; 19.000 ; 19.000 ; ; -; nDEVSEL ; nRWE ; ; 19.000 ; 19.000 ; ; -; nIOSEL ; D[0] ; ; 26.000 ; 26.000 ; ; -; nIOSEL ; D[1] ; ; 26.000 ; 26.000 ; ; -; nIOSEL ; D[2] ; ; 26.000 ; 26.000 ; ; -; nIOSEL ; D[3] ; ; 26.000 ; 26.000 ; ; -; nIOSEL ; D[4] ; ; 26.000 ; 26.000 ; ; -; nIOSEL ; D[5] ; ; 26.000 ; 26.000 ; ; -; nIOSEL ; D[6] ; ; 26.000 ; 26.000 ; ; -; nIOSEL ; D[7] ; ; 26.000 ; 26.000 ; ; -; nIOSEL ; RD[0] ; 26.000 ; ; ; 26.000 ; -; nIOSEL ; RD[1] ; 26.000 ; ; ; 26.000 ; -; nIOSEL ; RD[2] ; 26.000 ; ; ; 26.000 ; -; nIOSEL ; RD[3] ; 26.000 ; ; ; 26.000 ; -; nIOSEL ; RD[4] ; 26.000 ; ; ; 26.000 ; -; nIOSEL ; RD[5] ; 26.000 ; ; ; 26.000 ; -; nIOSEL ; RD[6] ; 26.000 ; ; ; 26.000 ; -; nIOSEL ; RD[7] ; 26.000 ; ; ; 26.000 ; -; nIOSEL ; nRCS ; ; 19.000 ; 19.000 ; ; -; nIOSEL ; nRWE ; ; 19.000 ; 19.000 ; ; -; nIOSTRB ; D[0] ; ; 26.000 ; 26.000 ; ; -; nIOSTRB ; D[1] ; ; 26.000 ; 26.000 ; ; -; nIOSTRB ; D[2] ; ; 26.000 ; 26.000 ; ; -; nIOSTRB ; D[3] ; ; 26.000 ; 26.000 ; ; -; nIOSTRB ; D[4] ; ; 26.000 ; 26.000 ; ; -; nIOSTRB ; D[5] ; ; 26.000 ; 26.000 ; ; -; nIOSTRB ; D[6] ; ; 26.000 ; 26.000 ; ; -; nIOSTRB ; D[7] ; ; 26.000 ; 26.000 ; ; -; nIOSTRB ; RD[0] ; 26.000 ; ; ; 26.000 ; -; nIOSTRB ; RD[1] ; 26.000 ; ; ; 26.000 ; -; nIOSTRB ; RD[2] ; 26.000 ; ; ; 26.000 ; -; nIOSTRB ; RD[3] ; 26.000 ; ; ; 26.000 ; -; nIOSTRB ; RD[4] ; 26.000 ; ; ; 26.000 ; -; nIOSTRB ; RD[5] ; 26.000 ; ; ; 26.000 ; -; nIOSTRB ; RD[6] ; 26.000 ; ; ; 26.000 ; -; nIOSTRB ; RD[7] ; 26.000 ; ; ; 26.000 ; -; nIOSTRB ; nRCS ; ; 19.000 ; 19.000 ; ; -; nIOSTRB ; nRWE ; ; 19.000 ; 19.000 ; ; -; nRES ; D[0] ; 26.000 ; ; ; 26.000 ; -; nRES ; D[1] ; 26.000 ; ; ; 26.000 ; -; nRES ; D[2] ; 26.000 ; ; ; 26.000 ; -; nRES ; D[3] ; 26.000 ; ; ; 26.000 ; -; nRES ; D[4] ; 26.000 ; ; ; 26.000 ; -; nRES ; D[5] ; 26.000 ; ; ; 26.000 ; -; nRES ; D[6] ; 26.000 ; ; ; 26.000 ; -; nRES ; D[7] ; 26.000 ; ; ; 26.000 ; -; nRES ; RD[0] ; 26.000 ; ; ; 26.000 ; -; nRES ; RD[1] ; 26.000 ; ; ; 26.000 ; -; nRES ; RD[2] ; 26.000 ; ; ; 26.000 ; -; nRES ; RD[3] ; 26.000 ; ; ; 26.000 ; -; nRES ; RD[4] ; 26.000 ; ; ; 26.000 ; -; nRES ; RD[5] ; 26.000 ; ; ; 26.000 ; -; nRES ; RD[6] ; 26.000 ; ; ; 26.000 ; -; nRES ; RD[7] ; 26.000 ; ; ; 26.000 ; -; nWE ; D[0] ; 26.000 ; ; ; 26.000 ; -; nWE ; D[1] ; 26.000 ; ; ; 26.000 ; -; nWE ; D[2] ; 26.000 ; ; ; 26.000 ; -; nWE ; D[3] ; 26.000 ; ; ; 26.000 ; -; nWE ; D[4] ; 26.000 ; ; ; 26.000 ; -; nWE ; D[5] ; 26.000 ; ; ; 26.000 ; -; nWE ; D[6] ; 26.000 ; ; ; 26.000 ; -; nWE ; D[7] ; 26.000 ; ; ; 26.000 ; -; nWE ; RD[0] ; ; 26.000 ; 26.000 ; ; -; nWE ; RD[1] ; ; 26.000 ; 26.000 ; ; -; nWE ; RD[2] ; ; 26.000 ; 26.000 ; ; -; nWE ; RD[3] ; ; 26.000 ; 26.000 ; ; -; nWE ; RD[4] ; ; 26.000 ; 26.000 ; ; -; nWE ; RD[5] ; ; 26.000 ; 26.000 ; ; -; nWE ; RD[6] ; ; 26.000 ; 26.000 ; ; -; nWE ; RD[7] ; ; 26.000 ; 26.000 ; ; -; nWE ; nINH ; 15.000 ; ; ; 15.000 ; -; nWE ; nROE ; 19.000 ; ; ; 19.000 ; -; nWE ; nRWE ; ; 19.000 ; 19.000 ; ; -+------------+-------------+--------+--------+--------+--------+ ++----------------------------------------------------------------+ +; Propagation Delay ; ++------------+-------------+---------+--------+--------+---------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+---------+--------+--------+---------+ +; A[0] ; D[0] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; +; A[0] ; D[1] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; +; A[0] ; D[2] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; +; A[0] ; D[3] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; +; A[0] ; D[4] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; +; A[0] ; D[5] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; +; A[0] ; D[6] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; +; A[0] ; D[7] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; +; A[1] ; D[0] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; +; A[1] ; D[1] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; +; A[1] ; D[2] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; +; A[1] ; D[3] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; +; A[1] ; D[4] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; +; A[1] ; D[5] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; +; A[1] ; D[6] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; +; A[1] ; D[7] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; +; A[2] ; D[0] ; ; 19.000 ; 19.000 ; ; +; A[2] ; D[1] ; ; 19.000 ; 19.000 ; ; +; A[2] ; D[2] ; ; 19.000 ; 19.000 ; ; +; A[2] ; D[3] ; ; 19.000 ; 19.000 ; ; +; A[2] ; D[4] ; ; 19.000 ; 19.000 ; ; +; A[2] ; D[5] ; ; 19.000 ; 19.000 ; ; +; A[2] ; D[6] ; ; 19.000 ; 19.000 ; ; +; A[2] ; D[7] ; ; 19.000 ; 19.000 ; ; +; A[3] ; D[0] ; ; 19.000 ; 19.000 ; ; +; A[3] ; D[1] ; ; 19.000 ; 19.000 ; ; +; A[3] ; D[2] ; ; 19.000 ; 19.000 ; ; +; A[3] ; D[3] ; ; 19.000 ; 19.000 ; ; +; A[3] ; D[4] ; ; 19.000 ; 19.000 ; ; +; A[3] ; D[5] ; ; 19.000 ; 19.000 ; ; +; A[3] ; D[6] ; ; 19.000 ; 19.000 ; ; +; A[3] ; D[7] ; ; 19.000 ; 19.000 ; ; +; D[0] ; RD[0] ; 19.000 ; ; ; 19.000 ; +; D[1] ; RD[1] ; 19.000 ; ; ; 19.000 ; +; D[2] ; RD[2] ; 19.000 ; ; ; 19.000 ; +; D[3] ; RD[3] ; 19.000 ; ; ; 19.000 ; +; D[4] ; RD[4] ; 19.000 ; ; ; 19.000 ; +; D[5] ; RD[5] ; 19.000 ; ; ; 19.000 ; +; D[6] ; RD[6] ; 19.000 ; ; ; 19.000 ; +; D[7] ; RD[7] ; 19.000 ; ; ; 19.000 ; +; PHI1in ; PHI1out ; 230.000 ; ; ; 230.000 ; +; RD[0] ; D[0] ; 19.000 ; ; ; 19.000 ; +; RD[1] ; D[1] ; 19.000 ; ; ; 19.000 ; +; RD[2] ; D[2] ; 19.000 ; ; ; 19.000 ; +; RD[3] ; D[3] ; 19.000 ; ; ; 19.000 ; +; RD[4] ; D[4] ; 19.000 ; ; ; 19.000 ; +; RD[5] ; D[5] ; 19.000 ; ; ; 19.000 ; +; RD[6] ; D[6] ; 19.000 ; ; ; 19.000 ; +; RD[7] ; D[7] ; 19.000 ; ; ; 19.000 ; +; nDEVSEL ; D[0] ; 19.000 ; 26.000 ; 26.000 ; 19.000 ; +; nDEVSEL ; D[1] ; 19.000 ; 26.000 ; 26.000 ; 19.000 ; +; nDEVSEL ; D[2] ; 19.000 ; 26.000 ; 26.000 ; 19.000 ; +; nDEVSEL ; D[3] ; 19.000 ; 26.000 ; 26.000 ; 19.000 ; +; nDEVSEL ; D[4] ; 19.000 ; 26.000 ; 26.000 ; 19.000 ; +; nDEVSEL ; D[5] ; 19.000 ; 26.000 ; 26.000 ; 19.000 ; +; nDEVSEL ; D[6] ; 19.000 ; 26.000 ; 26.000 ; 19.000 ; +; nDEVSEL ; D[7] ; 19.000 ; 26.000 ; 26.000 ; 19.000 ; +; nDEVSEL ; nCAS0 ; ; 19.000 ; 19.000 ; ; +; nDEVSEL ; nCAS1 ; ; 19.000 ; 19.000 ; ; +; nDEVSEL ; nRWE ; 19.000 ; ; ; 19.000 ; +; nIOSEL ; D[0] ; ; 26.000 ; 26.000 ; ; +; nIOSEL ; D[1] ; ; 26.000 ; 26.000 ; ; +; nIOSEL ; D[2] ; ; 26.000 ; 26.000 ; ; +; nIOSEL ; D[3] ; ; 26.000 ; 26.000 ; ; +; nIOSEL ; D[4] ; ; 26.000 ; 26.000 ; ; +; nIOSEL ; D[5] ; ; 26.000 ; 26.000 ; ; +; nIOSEL ; D[6] ; ; 26.000 ; 26.000 ; ; +; nIOSEL ; D[7] ; ; 26.000 ; 26.000 ; ; +; nIOSEL ; RA[0] ; 19.000 ; ; ; 19.000 ; +; nIOSEL ; RA[1] ; 19.000 ; ; ; 19.000 ; +; nIOSEL ; RA[2] ; 19.000 ; ; ; 19.000 ; +; nIOSEL ; RA[3] ; 19.000 ; ; ; 19.000 ; +; nIOSEL ; RA[4] ; 19.000 ; ; ; 19.000 ; +; nIOSEL ; RA[5] ; 19.000 ; ; ; 19.000 ; +; nIOSEL ; RA[6] ; 19.000 ; ; ; 19.000 ; +; nIOSEL ; RA[7] ; 19.000 ; ; ; 19.000 ; +; nIOSEL ; nRCS ; ; 19.000 ; 19.000 ; ; +; nIOSEL ; nRWE ; 19.000 ; ; ; 19.000 ; +; nIOSTRB ; D[0] ; ; 26.000 ; 26.000 ; ; +; nIOSTRB ; D[1] ; ; 26.000 ; 26.000 ; ; +; nIOSTRB ; D[2] ; ; 26.000 ; 26.000 ; ; +; nIOSTRB ; D[3] ; ; 26.000 ; 26.000 ; ; +; nIOSTRB ; D[4] ; ; 26.000 ; 26.000 ; ; +; nIOSTRB ; D[5] ; ; 26.000 ; 26.000 ; ; +; nIOSTRB ; D[6] ; ; 26.000 ; 26.000 ; ; +; nIOSTRB ; D[7] ; ; 26.000 ; 26.000 ; ; +; nIOSTRB ; RA[0] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; +; nIOSTRB ; RA[1] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; +; nIOSTRB ; RA[2] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; +; nIOSTRB ; RA[3] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; +; nIOSTRB ; RA[4] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; +; nIOSTRB ; RA[5] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; +; nIOSTRB ; RA[6] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; +; nIOSTRB ; RA[7] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; +; nIOSTRB ; nRCS ; ; 19.000 ; 19.000 ; ; +; nIOSTRB ; nRWE ; 19.000 ; ; ; 19.000 ; +; nWE ; D[0] ; 26.000 ; ; ; 26.000 ; +; nWE ; D[1] ; 26.000 ; ; ; 26.000 ; +; nWE ; D[2] ; 26.000 ; ; ; 26.000 ; +; nWE ; D[3] ; 26.000 ; ; ; 26.000 ; +; nWE ; D[4] ; 26.000 ; ; ; 26.000 ; +; nWE ; D[5] ; 26.000 ; ; ; 26.000 ; +; nWE ; D[6] ; 26.000 ; ; ; 26.000 ; +; nWE ; D[7] ; 26.000 ; ; ; 26.000 ; +; nWE ; RD[0] ; ; 26.000 ; 26.000 ; ; +; nWE ; RD[1] ; ; 26.000 ; 26.000 ; ; +; nWE ; RD[2] ; ; 26.000 ; 26.000 ; ; +; nWE ; RD[3] ; ; 26.000 ; 26.000 ; ; +; nWE ; RD[4] ; ; 26.000 ; 26.000 ; ; +; nWE ; RD[5] ; ; 26.000 ; 26.000 ; ; +; nWE ; RD[6] ; ; 26.000 ; 26.000 ; ; +; nWE ; RD[7] ; ; 26.000 ; 26.000 ; ; +; nWE ; nROE ; ; 19.000 ; 19.000 ; ; +; nWE ; nRWE ; 19.000 ; ; ; 19.000 ; ++------------+-------------+---------+--------+--------+---------+ +--------------------------------------------------------------+ @@ -870,11 +843,6 @@ No paths to report. ; A[3] ; D[5] ; ; 19.000 ; 19.000 ; ; ; A[3] ; D[6] ; ; 19.000 ; 19.000 ; ; ; A[3] ; D[7] ; ; 19.000 ; 19.000 ; ; -; A[11] ; RA[0] ; 19.000 ; ; ; 19.000 ; -; A[12] ; nINH ; 15.000 ; ; ; 15.000 ; -; A[13] ; nINH ; 15.000 ; ; ; 15.000 ; -; A[14] ; nINH ; 15.000 ; ; ; 15.000 ; -; A[15] ; nINH ; 15.000 ; ; ; 15.000 ; ; D[0] ; RD[0] ; 19.000 ; ; ; 19.000 ; ; D[1] ; RD[1] ; 19.000 ; ; ; 19.000 ; ; D[2] ; RD[2] ; 19.000 ; ; ; 19.000 ; @@ -883,8 +851,7 @@ No paths to report. ; D[5] ; RD[5] ; 19.000 ; ; ; 19.000 ; ; D[6] ; RD[6] ; 19.000 ; ; ; 19.000 ; ; D[7] ; RD[7] ; 19.000 ; ; ; 19.000 ; -; MODE ; nINH ; ; 15.000 ; 15.000 ; ; -; PHI1in ; PHI1out ; 19.000 ; ; ; 19.000 ; +; PHI1in ; PHI1out ; 32.000 ; ; ; 32.000 ; ; RD[0] ; D[0] ; 19.000 ; ; ; 19.000 ; ; RD[1] ; D[1] ; 19.000 ; ; ; 19.000 ; ; RD[2] ; D[2] ; 19.000 ; ; ; 19.000 ; @@ -901,25 +868,9 @@ No paths to report. ; nDEVSEL ; D[5] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; ; nDEVSEL ; D[6] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; ; nDEVSEL ; D[7] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; -; nDEVSEL ; RA[0] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; -; nDEVSEL ; RA[1] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; -; nDEVSEL ; RA[2] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; -; nDEVSEL ; RA[3] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; -; nDEVSEL ; RA[4] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; -; nDEVSEL ; RA[5] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; -; nDEVSEL ; RA[6] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; -; nDEVSEL ; RA[7] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; -; nDEVSEL ; RD[0] ; 26.000 ; ; ; 26.000 ; -; nDEVSEL ; RD[1] ; 26.000 ; ; ; 26.000 ; -; nDEVSEL ; RD[2] ; 26.000 ; ; ; 26.000 ; -; nDEVSEL ; RD[3] ; 26.000 ; ; ; 26.000 ; -; nDEVSEL ; RD[4] ; 26.000 ; ; ; 26.000 ; -; nDEVSEL ; RD[5] ; 26.000 ; ; ; 26.000 ; -; nDEVSEL ; RD[6] ; 26.000 ; ; ; 26.000 ; -; nDEVSEL ; RD[7] ; 26.000 ; ; ; 26.000 ; ; nDEVSEL ; nCAS0 ; ; 19.000 ; 19.000 ; ; ; nDEVSEL ; nCAS1 ; ; 19.000 ; 19.000 ; ; -; nDEVSEL ; nRWE ; ; 19.000 ; 19.000 ; ; +; nDEVSEL ; nRWE ; 19.000 ; ; ; 19.000 ; ; nIOSEL ; D[0] ; ; 26.000 ; 26.000 ; ; ; nIOSEL ; D[1] ; ; 26.000 ; 26.000 ; ; ; nIOSEL ; D[2] ; ; 26.000 ; 26.000 ; ; @@ -928,16 +879,16 @@ No paths to report. ; nIOSEL ; D[5] ; ; 26.000 ; 26.000 ; ; ; nIOSEL ; D[6] ; ; 26.000 ; 26.000 ; ; ; nIOSEL ; D[7] ; ; 26.000 ; 26.000 ; ; -; nIOSEL ; RD[0] ; 26.000 ; ; ; 26.000 ; -; nIOSEL ; RD[1] ; 26.000 ; ; ; 26.000 ; -; nIOSEL ; RD[2] ; 26.000 ; ; ; 26.000 ; -; nIOSEL ; RD[3] ; 26.000 ; ; ; 26.000 ; -; nIOSEL ; RD[4] ; 26.000 ; ; ; 26.000 ; -; nIOSEL ; RD[5] ; 26.000 ; ; ; 26.000 ; -; nIOSEL ; RD[6] ; 26.000 ; ; ; 26.000 ; -; nIOSEL ; RD[7] ; 26.000 ; ; ; 26.000 ; +; nIOSEL ; RA[0] ; 19.000 ; ; ; 19.000 ; +; nIOSEL ; RA[1] ; 19.000 ; ; ; 19.000 ; +; nIOSEL ; RA[2] ; 19.000 ; ; ; 19.000 ; +; nIOSEL ; RA[3] ; 19.000 ; ; ; 19.000 ; +; nIOSEL ; RA[4] ; 19.000 ; ; ; 19.000 ; +; nIOSEL ; RA[5] ; 19.000 ; ; ; 19.000 ; +; nIOSEL ; RA[6] ; 19.000 ; ; ; 19.000 ; +; nIOSEL ; RA[7] ; 19.000 ; ; ; 19.000 ; ; nIOSEL ; nRCS ; ; 19.000 ; 19.000 ; ; -; nIOSEL ; nRWE ; ; 19.000 ; 19.000 ; ; +; nIOSEL ; nRWE ; 19.000 ; ; ; 19.000 ; ; nIOSTRB ; D[0] ; ; 26.000 ; 26.000 ; ; ; nIOSTRB ; D[1] ; ; 26.000 ; 26.000 ; ; ; nIOSTRB ; D[2] ; ; 26.000 ; 26.000 ; ; @@ -946,32 +897,16 @@ No paths to report. ; nIOSTRB ; D[5] ; ; 26.000 ; 26.000 ; ; ; nIOSTRB ; D[6] ; ; 26.000 ; 26.000 ; ; ; nIOSTRB ; D[7] ; ; 26.000 ; 26.000 ; ; -; nIOSTRB ; RD[0] ; 26.000 ; ; ; 26.000 ; -; nIOSTRB ; RD[1] ; 26.000 ; ; ; 26.000 ; -; nIOSTRB ; RD[2] ; 26.000 ; ; ; 26.000 ; -; nIOSTRB ; RD[3] ; 26.000 ; ; ; 26.000 ; -; nIOSTRB ; RD[4] ; 26.000 ; ; ; 26.000 ; -; nIOSTRB ; RD[5] ; 26.000 ; ; ; 26.000 ; -; nIOSTRB ; RD[6] ; 26.000 ; ; ; 26.000 ; -; nIOSTRB ; RD[7] ; 26.000 ; ; ; 26.000 ; +; nIOSTRB ; RA[0] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; +; nIOSTRB ; RA[1] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; +; nIOSTRB ; RA[2] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; +; nIOSTRB ; RA[3] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; +; nIOSTRB ; RA[4] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; +; nIOSTRB ; RA[5] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; +; nIOSTRB ; RA[6] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; +; nIOSTRB ; RA[7] ; 19.000 ; 19.000 ; 19.000 ; 19.000 ; ; nIOSTRB ; nRCS ; ; 19.000 ; 19.000 ; ; -; nIOSTRB ; nRWE ; ; 19.000 ; 19.000 ; ; -; nRES ; D[0] ; 26.000 ; ; ; 26.000 ; -; nRES ; D[1] ; 26.000 ; ; ; 26.000 ; -; nRES ; D[2] ; 26.000 ; ; ; 26.000 ; -; nRES ; D[3] ; 26.000 ; ; ; 26.000 ; -; nRES ; D[4] ; 26.000 ; ; ; 26.000 ; -; nRES ; D[5] ; 26.000 ; ; ; 26.000 ; -; nRES ; D[6] ; 26.000 ; ; ; 26.000 ; -; nRES ; D[7] ; 26.000 ; ; ; 26.000 ; -; nRES ; RD[0] ; 26.000 ; ; ; 26.000 ; -; nRES ; RD[1] ; 26.000 ; ; ; 26.000 ; -; nRES ; RD[2] ; 26.000 ; ; ; 26.000 ; -; nRES ; RD[3] ; 26.000 ; ; ; 26.000 ; -; nRES ; RD[4] ; 26.000 ; ; ; 26.000 ; -; nRES ; RD[5] ; 26.000 ; ; ; 26.000 ; -; nRES ; RD[6] ; 26.000 ; ; ; 26.000 ; -; nRES ; RD[7] ; 26.000 ; ; ; 26.000 ; +; nIOSTRB ; nRWE ; 19.000 ; ; ; 19.000 ; ; nWE ; D[0] ; 26.000 ; ; ; 26.000 ; ; nWE ; D[1] ; 26.000 ; ; ; 26.000 ; ; nWE ; D[2] ; 26.000 ; ; ; 26.000 ; @@ -988,9 +923,8 @@ No paths to report. ; nWE ; RD[5] ; ; 26.000 ; 26.000 ; ; ; nWE ; RD[6] ; ; 26.000 ; 26.000 ; ; ; nWE ; RD[7] ; ; 26.000 ; 26.000 ; ; -; nWE ; nINH ; 15.000 ; ; ; 15.000 ; -; nWE ; nROE ; 19.000 ; ; ; 19.000 ; -; nWE ; nRWE ; ; 19.000 ; 19.000 ; ; +; nWE ; nROE ; ; 19.000 ; 19.000 ; ; +; nWE ; nRWE ; 19.000 ; ; ; 19.000 ; +------------+-------------+--------+--------+--------+--------+ @@ -1103,7 +1037,7 @@ No paths to report. +------------+----------+----------+----------+----------+----------+ ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; +------------+----------+----------+----------+----------+----------+ -; C7M ; C7M ; 1017 ; 0 ; 0 ; 0 ; +; C7M ; C7M ; 706 ; 0 ; 0 ; 0 ; ; C7M ; C7M_2 ; 0 ; 0 ; 17 ; 0 ; +------------+----------+----------+----------+----------+----------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. @@ -1114,7 +1048,7 @@ Entries labeled "false path" only account for clock-to-clock false paths and not +------------+----------+----------+----------+----------+----------+ ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; +------------+----------+----------+----------+----------+----------+ -; C7M ; C7M ; 1017 ; 0 ; 0 ; 0 ; +; C7M ; C7M ; 706 ; 0 ; 0 ; 0 ; ; C7M ; C7M_2 ; 0 ; 0 ; 17 ; 0 ; +------------+----------+----------+----------+----------+----------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. @@ -1139,10 +1073,10 @@ No dedicated SERDES Receiver circuitry present in device or used in design +---------------------------------+-------+------+ ; Illegal Clocks ; 0 ; 0 ; ; Unconstrained Clocks ; 0 ; 0 ; -; Unconstrained Input Ports ; 40 ; 40 ; -; Unconstrained Input Port Paths ; 458 ; 458 ; -; Unconstrained Output Ports ; 36 ; 36 ; -; Unconstrained Output Port Paths ; 259 ; 259 ; +; Unconstrained Input Ports ; 34 ; 34 ; +; Unconstrained Input Port Paths ; 421 ; 421 ; +; Unconstrained Output Ports ; 35 ; 35 ; +; Unconstrained Output Port Paths ; 254 ; 254 ; +---------------------------------+-------+------+ @@ -1150,9 +1084,9 @@ No dedicated SERDES Receiver circuitry present in device or used in design ; TimeQuest Timing Analyzer Messages ; +------------------------------------+ Info: ******************************************************************* -Info: Running Quartus II 32-bit TimeQuest Timing Analyzer +Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - Info: Processing started: Sat Aug 31 22:53:44 2019 + Info: Processing started: Sun Sep 01 20:44:17 2019 Info: Command: quartus_sta GR8RAM -c GR8RAM Info: qsta_default_script.tcl version: #1 Warning (20028): Parallel compilation is not licensed and has been disabled @@ -1166,11 +1100,11 @@ Info (332105): Deriving Clocks Info (332105): create_clock -period 1.000 -name C7M_2 C7M_2 Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON Critical Warning (332148): Timing requirements not met -Info (332146): Worst-case setup slack is -29.000 +Info (332146): Worst-case setup slack is -47.000 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== - Info (332119): -29.000 -821.000 C7M - Info (332119): -5.500 -11.000 C7M_2 + Info (332119): -47.000 -1802.000 C7M + Info (332119): -27.500 -33.000 C7M_2 Info (332146): Worst-case hold slack is -1.500 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== @@ -1182,14 +1116,14 @@ Info (332146): Worst-case minimum pulse width slack is -5.500 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== Info (332119): -5.500 -22.000 C7M_2 - Info (332119): -4.500 -414.000 C7M + Info (332119): -4.500 -432.000 C7M Info (332001): The selected device family is not supported by the report_metastability command. Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements -Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings - Info: Peak virtual memory: 260 megabytes - Info: Processing ended: Sat Aug 31 22:53:50 2019 - Info: Elapsed time: 00:00:06 - Info: Total CPU time (on all processors): 00:00:06 +Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings + Info: Peak virtual memory: 4530 megabytes + Info: Processing ended: Sun Sep 01 20:44:17 2019 + Info: Elapsed time: 00:00:00 + Info: Total CPU time (on all processors): 00:00:00 diff --git a/cpld/output_files/GR8RAM.sta.summary b/cpld/output_files/GR8RAM.sta.summary index 30f14d2..a4cd919 100755 --- a/cpld/output_files/GR8RAM.sta.summary +++ b/cpld/output_files/GR8RAM.sta.summary @@ -3,12 +3,12 @@ TimeQuest Timing Analyzer Summary ------------------------------------------------------------ Type : Setup 'C7M' -Slack : -29.000 -TNS : -821.000 +Slack : -47.000 +TNS : -1802.000 Type : Setup 'C7M_2' -Slack : -5.500 -TNS : -11.000 +Slack : -27.500 +TNS : -33.000 Type : Hold 'C7M_2' Slack : -1.500 @@ -24,6 +24,6 @@ TNS : -22.000 Type : Minimum Pulse Width 'C7M' Slack : -4.500 -TNS : -414.000 +TNS : -432.000 ------------------------------------------------------------