diff --git a/Bus.kicad_sch b/Bus.kicad_sch
new file mode 100644
index 0000000..366706a
--- /dev/null
+++ b/Bus.kicad_sch
@@ -0,0 +1,10 @@
+(kicad_sch (version 20230121) (generator eeschema)
+
+  (uuid 03d59670-8c65-499d-9846-d220ccf72801)
+
+  (paper "A4")
+
+  (lib_symbols
+  )
+
+)
diff --git a/Docs.kicad_sch b/Docs.kicad_sch
index 8ef4c2b..29bb765 100644
--- a/Docs.kicad_sch
+++ b/Docs.kicad_sch
@@ -1,4 +1,4 @@
-(kicad_sch (version 20211123) (generator eeschema)
+(kicad_sch (version 20230121) (generator eeschema)
 
   (uuid 750e60a2-e808-4253-8275-b79930fb2714)
 
@@ -37,2299 +37,2299 @@
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+  (text "C25M" (at 36.83 16.51 0)
     (effects (font (size 1.27 1.27)) (justify right bottom))
     (uuid 7114de55-86d9-46c1-a412-07f5eb895435)
   )
@@ -2638,7 +2638,7 @@
     (effects (font (size 1.27 1.27)) (justify left bottom))
     (uuid b4fbe1fb-a9a3-4020-9a82-d3fa1900cd85)
   )
-  (text "~{DEVSEL}" (at 36.83 24.13 180)
+  (text "~{DEVSEL}" (at 36.83 24.13 0)
     (effects (font (size 1.27 1.27)) (justify right bottom))
     (uuid bab3431c-ede6-417b-8033-763748a11a9f)
   )
@@ -2654,7 +2654,7 @@
     (effects (font (size 1.27 1.27)) (justify left bottom))
     (uuid c11e04e4-f63f-46b9-9a9c-9c7df49e614a)
   )
-  (text "SD" (at 36.83 76.2 180)
+  (text "SD" (at 36.83 76.2 0)
     (effects (font (size 1.27 1.27)) (justify right bottom))
     (uuid c2564ecf-bd43-431d-b9a2-c7be54487485)
   )
@@ -2666,7 +2666,7 @@
     (effects (font (size 1.27 1.27)) (justify left bottom))
     (uuid cce1404b-fc30-47cc-b852-e0061990f2bb)
   )
-  (text "MD" (at 36.83 87.63 180)
+  (text "MD" (at 36.83 87.63 0)
     (effects (font (size 1.27 1.27)) (justify right bottom))
     (uuid d1f81642-eb3a-4277-b357-9cbb5a3aa5ac)
   )
@@ -2735,7 +2735,7 @@
     (effects (font (size 1.27 1.27)) (justify left bottom))
     (uuid f931f973-5615-451c-bb04-9a02aede6e6f)
   )
-  (text "CMD (idle)" (at 36.83 54.61 180)
+  (text "CMD (idle)" (at 36.83 54.61 0)
     (effects (font (size 1.27 1.27)) (justify right bottom))
     (uuid faa605d9-8c1c-4d31-b7c1-3dc31a22eb34)
   )
diff --git a/FPGA.kicad_sch b/FPGA.kicad_sch
new file mode 100644
index 0000000..2b0c8c6
--- /dev/null
+++ b/FPGA.kicad_sch
@@ -0,0 +1,10 @@
+(kicad_sch (version 20230121) (generator eeschema)
+
+  (uuid 73789c9c-4faf-4437-8e94-73a6bbbf318f)
+
+  (paper "A4")
+
+  (lib_symbols
+  )
+
+)
diff --git a/GR8RAM.kicad_pcb b/GR8RAM.kicad_pcb
index 2edd78e..c084e70 100644
--- a/GR8RAM.kicad_pcb
+++ b/GR8RAM.kicad_pcb
@@ -1,4 +1,4 @@
-(kicad_pcb (version 20211014) (generator pcbnew)
+(kicad_pcb (version 20221018) (generator pcbnew)
 
   (general
     (thickness 1.6)
@@ -60,14 +60,15 @@
     (pad_to_paste_clearance -0.0381)
     (pcbplotparams
       (layerselection 0x00010f8_ffffffff)
+      (plot_on_all_layers_selection 0x0000000_00000000)
       (disableapertmacros false)
       (usegerberextensions true)
       (usegerberattributes false)
       (usegerberadvancedattributes false)
       (creategerberjobfile false)
-      (svguseinch false)
+      (dashed_line_dash_ratio 12.000000)
+      (dashed_line_gap_ratio 3.000000)
       (svgprecision 6)
-      (excludeedgelayer true)
       (plotframeref false)
       (viasonmask false)
       (mode 1)
@@ -249,7 +250,7 @@
   (net 153 "unconnected-(U11-Pad12)")
 
   (footprint "stdpads:C_0603" (layer "F.Cu")
-    (tedit 5EE29C36) (tstamp 00000000-0000-0000-0000-00005f3d0a23)
+    (tstamp 00000000-0000-0000-0000-00005f3d0a23)
     (at 103.75 100.9 90)
     (tags "capacitor")
     (property "LCSC Part" "C23630")
@@ -260,30 +261,40 @@
     (solder_paste_margin -0.04)
     (attr smd)
     (fp_text reference "C24" (at 0 0 90) (layer "F.Fab")
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
       (tstamp 87dd3f0d-60ab-4c46-961b-49546bc57d04)
     )
     (fp_text value "2u2" (at 0 0.25 90) (layer "F.Fab")
-      (effects (font (size 0.127 0.127) (thickness 0.03175)))
+        (effects (font (size 0.127 0.127) (thickness 0.03175)))
       (tstamp d0bfe201-daa4-4d35-9ccd-fa6a79ba80ae)
     )
     (fp_text user "${REFERENCE}" (at 0 0 90) (layer "F.SilkS") hide
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
       (tstamp baae70b6-0dd8-49ae-afd1-a7595ef75074)
     )
-    (fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer "F.SilkS") (width 0.12) (tstamp 8a481b42-55a3-4c74-b3bd-a1e1e2bf083b))
-    (fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer "F.SilkS") (width 0.12) (tstamp a7a683cc-6e6c-411e-8736-b3c97afc4cf7))
-    (fp_line (start 1.4 -0.7) (end 1.4 0.7) (layer "F.CrtYd") (width 0.05) (tstamp 13f4df76-5af2-405c-b137-958f9a82537a))
-    (fp_line (start -1.4 -0.7) (end 1.4 -0.7) (layer "F.CrtYd") (width 0.05) (tstamp 31a86bef-90f5-47a9-9b95-49abf4ba4160))
-    (fp_line (start -1.4 0.7) (end -1.4 -0.7) (layer "F.CrtYd") (width 0.05) (tstamp 34d17749-c226-4d41-8b18-439e868c88b7))
-    (fp_line (start 1.4 0.7) (end -1.4 0.7) (layer "F.CrtYd") (width 0.05) (tstamp c96e7a55-b8eb-44d6-be3d-c0744c75107b))
-    (fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer "F.Fab") (width 0.1) (tstamp 2df5561c-5d72-4a02-b07b-88bcb9fd2f51))
-    (fp_line (start 0.8 0.4) (end -0.8 0.4) (layer "F.Fab") (width 0.1) (tstamp 320e4724-6d2c-4fdb-8f38-e333191a5637))
-    (fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer "F.Fab") (width 0.1) (tstamp 6ff726eb-39ac-4f14-9931-29153036cf12))
-    (fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer "F.Fab") (width 0.1) (tstamp f3ee1261-d1e2-46db-8b55-a0658d91b6f0))
-    (pad "1" smd roundrect locked (at -0.75 0 90) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (fp_line (start -0.162779 -0.51) (end 0.162779 -0.51)
+      (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp a7a683cc-6e6c-411e-8736-b3c97afc4cf7))
+    (fp_line (start -0.162779 0.51) (end 0.162779 0.51)
+      (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 8a481b42-55a3-4c74-b3bd-a1e1e2bf083b))
+    (fp_line (start -1.4 -0.7) (end 1.4 -0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 31a86bef-90f5-47a9-9b95-49abf4ba4160))
+    (fp_line (start -1.4 0.7) (end -1.4 -0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 34d17749-c226-4d41-8b18-439e868c88b7))
+    (fp_line (start 1.4 -0.7) (end 1.4 0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 13f4df76-5af2-405c-b137-958f9a82537a))
+    (fp_line (start 1.4 0.7) (end -1.4 0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp c96e7a55-b8eb-44d6-be3d-c0744c75107b))
+    (fp_line (start -0.8 -0.4) (end 0.8 -0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp f3ee1261-d1e2-46db-8b55-a0658d91b6f0))
+    (fp_line (start -0.8 0.4) (end -0.8 -0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 6ff726eb-39ac-4f14-9931-29153036cf12))
+    (fp_line (start 0.8 -0.4) (end 0.8 0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 2df5561c-5d72-4a02-b07b-88bcb9fd2f51))
+    (fp_line (start 0.8 0.4) (end -0.8 0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 320e4724-6d2c-4fdb-8f38-e333191a5637))
+    (pad "1" smd roundrect (at -0.75 0 90) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 72 "+3V3") (pintype "passive") (tstamp 00d7bdb8-e5cc-4c48-a1a8-da005ded2e3f))
-    (pad "2" smd roundrect locked (at 0.75 0 90) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "2" smd roundrect (at 0.75 0 90) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pintype "passive") (tstamp 4dcf95d2-8f09-4bdb-8a06-5c371d680091))
     (model "${KICAD6_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_0603_1608Metric.wrl"
       (offset (xyz 0 0 0))
@@ -293,7 +304,7 @@
   )
 
   (footprint "stdpads:C_0603" (layer "F.Cu")
-    (tedit 5EE29C36) (tstamp 00000000-0000-0000-0000-00005f3d0a83)
+    (tstamp 00000000-0000-0000-0000-00005f3d0a83)
     (at 90.15 91.7 180)
     (tags "capacitor")
     (property "LCSC Part" "C23630")
@@ -304,30 +315,40 @@
     (solder_paste_margin -0.04)
     (attr smd)
     (fp_text reference "C26" (at 0 0) (layer "F.Fab")
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
       (tstamp 4c305212-0a8d-47af-a993-c682fdfd43dc)
     )
     (fp_text value "2u2" (at 0 0.25) (layer "F.Fab")
-      (effects (font (size 0.127 0.127) (thickness 0.03175)))
+        (effects (font (size 0.127 0.127) (thickness 0.03175)))
       (tstamp 0542db7c-c6c7-4c1c-927b-967200d43085)
     )
     (fp_text user "${REFERENCE}" (at 0 0) (layer "F.SilkS") hide
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
       (tstamp fcd7587b-250b-43ce-aec7-cf368d21a790)
     )
-    (fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer "F.SilkS") (width 0.12) (tstamp 81a06844-82b9-490f-a008-d12a7e53e709))
-    (fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer "F.SilkS") (width 0.12) (tstamp 911e3d6b-cf86-4464-87b7-5a8ce01698ac))
-    (fp_line (start 1.4 0.7) (end -1.4 0.7) (layer "F.CrtYd") (width 0.05) (tstamp 3e93a0f3-64ae-4ace-8112-ca0fdafa3766))
-    (fp_line (start -1.4 -0.7) (end 1.4 -0.7) (layer "F.CrtYd") (width 0.05) (tstamp 857f8b63-861b-4606-a453-4a0c1a3dfbd6))
-    (fp_line (start 1.4 -0.7) (end 1.4 0.7) (layer "F.CrtYd") (width 0.05) (tstamp cdec5554-e5bc-48fd-a006-a11106ad8ace))
-    (fp_line (start -1.4 0.7) (end -1.4 -0.7) (layer "F.CrtYd") (width 0.05) (tstamp f3f8e943-4a7f-41e4-aa49-89560822c912))
-    (fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer "F.Fab") (width 0.1) (tstamp 2d984774-10c5-4a20-8f63-2c34b15b3e99))
-    (fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer "F.Fab") (width 0.1) (tstamp 3b288875-2ce0-47d9-83ab-a1573d82ddd3))
-    (fp_line (start 0.8 0.4) (end -0.8 0.4) (layer "F.Fab") (width 0.1) (tstamp 55eff66c-f607-4843-9f40-d64a3628cddb))
-    (fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer "F.Fab") (width 0.1) (tstamp e5c8db7e-a584-4c9a-99c5-abdff2b2a1d1))
-    (pad "1" smd roundrect locked (at -0.75 0 180) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (fp_line (start -0.162779 -0.51) (end 0.162779 -0.51)
+      (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 81a06844-82b9-490f-a008-d12a7e53e709))
+    (fp_line (start -0.162779 0.51) (end 0.162779 0.51)
+      (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 911e3d6b-cf86-4464-87b7-5a8ce01698ac))
+    (fp_line (start -1.4 -0.7) (end 1.4 -0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 857f8b63-861b-4606-a453-4a0c1a3dfbd6))
+    (fp_line (start -1.4 0.7) (end -1.4 -0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp f3f8e943-4a7f-41e4-aa49-89560822c912))
+    (fp_line (start 1.4 -0.7) (end 1.4 0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp cdec5554-e5bc-48fd-a006-a11106ad8ace))
+    (fp_line (start 1.4 0.7) (end -1.4 0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 3e93a0f3-64ae-4ace-8112-ca0fdafa3766))
+    (fp_line (start -0.8 -0.4) (end 0.8 -0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 2d984774-10c5-4a20-8f63-2c34b15b3e99))
+    (fp_line (start -0.8 0.4) (end -0.8 -0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 3b288875-2ce0-47d9-83ab-a1573d82ddd3))
+    (fp_line (start 0.8 -0.4) (end 0.8 0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp e5c8db7e-a584-4c9a-99c5-abdff2b2a1d1))
+    (fp_line (start 0.8 0.4) (end -0.8 0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 55eff66c-f607-4843-9f40-d64a3628cddb))
+    (pad "1" smd roundrect (at -0.75 0 180) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 72 "+3V3") (pintype "passive") (tstamp c45cd6e9-669a-4092-b2ea-69846c598647))
-    (pad "2" smd roundrect locked (at 0.75 0 180) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "2" smd roundrect (at 0.75 0 180) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pintype "passive") (tstamp 83cc00d5-9476-491d-b7fa-1ceb05aadf02))
     (model "${KICAD6_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_0603_1608Metric.wrl"
       (offset (xyz 0 0 0))
@@ -337,7 +358,7 @@
   )
 
   (footprint "stdpads:C_0603" (layer "F.Cu")
-    (tedit 5EE29C36) (tstamp 00000000-0000-0000-0000-00005f3d0ab3)
+    (tstamp 00000000-0000-0000-0000-00005f3d0ab3)
     (at 97.15 91.7 180)
     (tags "capacitor")
     (property "LCSC Part" "C23630")
@@ -348,30 +369,40 @@
     (solder_paste_margin -0.04)
     (attr smd)
     (fp_text reference "C25" (at 0 0) (layer "F.Fab")
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
       (tstamp 0a6850b9-6c76-4a15-b2c7-adfe81b113a0)
     )
     (fp_text value "2u2" (at 0 0.25) (layer "F.Fab")
-      (effects (font (size 0.127 0.127) (thickness 0.03175)))
+        (effects (font (size 0.127 0.127) (thickness 0.03175)))
       (tstamp 61c8c7e1-b45c-40a9-a906-069e8954db6f)
     )
     (fp_text user "${REFERENCE}" (at 0 0) (layer "F.SilkS") hide
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
       (tstamp 6268c652-d638-4cca-ac66-175d0b3f43a2)
     )
-    (fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer "F.SilkS") (width 0.12) (tstamp b7a81511-f5c9-4dd3-b797-f8b13d4f2234))
-    (fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer "F.SilkS") (width 0.12) (tstamp fdc7a4e4-172e-491b-b3c1-84a2eb962521))
-    (fp_line (start -1.4 -0.7) (end 1.4 -0.7) (layer "F.CrtYd") (width 0.05) (tstamp 1ec4a888-a5d5-44b6-92f6-4e8b94f3dedd))
-    (fp_line (start 1.4 -0.7) (end 1.4 0.7) (layer "F.CrtYd") (width 0.05) (tstamp 68c2e5ee-bfba-4305-9518-fc0b0f2daa4f))
-    (fp_line (start 1.4 0.7) (end -1.4 0.7) (layer "F.CrtYd") (width 0.05) (tstamp 8a539dc2-f476-48de-9eae-7d7ce05370cf))
-    (fp_line (start -1.4 0.7) (end -1.4 -0.7) (layer "F.CrtYd") (width 0.05) (tstamp a0db2c5f-7239-49ae-ba47-437c621e7ff8))
-    (fp_line (start 0.8 0.4) (end -0.8 0.4) (layer "F.Fab") (width 0.1) (tstamp 31a6abab-2a1c-4858-a076-141d460f469b))
-    (fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer "F.Fab") (width 0.1) (tstamp 9dc37e5b-0117-4b30-bbb6-13710814b0cf))
-    (fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer "F.Fab") (width 0.1) (tstamp aea18c8f-da69-49ff-bccc-e326c38e9829))
-    (fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer "F.Fab") (width 0.1) (tstamp eb49195a-f9b0-43e3-b552-e477ecff063d))
-    (pad "1" smd roundrect locked (at -0.75 0 180) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (fp_line (start -0.162779 -0.51) (end 0.162779 -0.51)
+      (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp b7a81511-f5c9-4dd3-b797-f8b13d4f2234))
+    (fp_line (start -0.162779 0.51) (end 0.162779 0.51)
+      (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp fdc7a4e4-172e-491b-b3c1-84a2eb962521))
+    (fp_line (start -1.4 -0.7) (end 1.4 -0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 1ec4a888-a5d5-44b6-92f6-4e8b94f3dedd))
+    (fp_line (start -1.4 0.7) (end -1.4 -0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp a0db2c5f-7239-49ae-ba47-437c621e7ff8))
+    (fp_line (start 1.4 -0.7) (end 1.4 0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 68c2e5ee-bfba-4305-9518-fc0b0f2daa4f))
+    (fp_line (start 1.4 0.7) (end -1.4 0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 8a539dc2-f476-48de-9eae-7d7ce05370cf))
+    (fp_line (start -0.8 -0.4) (end 0.8 -0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp eb49195a-f9b0-43e3-b552-e477ecff063d))
+    (fp_line (start -0.8 0.4) (end -0.8 -0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp aea18c8f-da69-49ff-bccc-e326c38e9829))
+    (fp_line (start 0.8 -0.4) (end 0.8 0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 9dc37e5b-0117-4b30-bbb6-13710814b0cf))
+    (fp_line (start 0.8 0.4) (end -0.8 0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 31a6abab-2a1c-4858-a076-141d460f469b))
+    (pad "1" smd roundrect (at -0.75 0 180) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 72 "+3V3") (pintype "passive") (tstamp 1da93d0b-7ffa-4107-a474-9c3680373a84))
-    (pad "2" smd roundrect locked (at 0.75 0 180) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "2" smd roundrect (at 0.75 0 180) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pintype "passive") (tstamp 706b8b7e-33b7-4969-a0a6-d35601c9e6e8))
     (model "${KICAD6_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_0603_1608Metric.wrl"
       (offset (xyz 0 0 0))
@@ -381,7 +412,7 @@
   )
 
   (footprint "stdpads:C_0603" (layer "F.Cu")
-    (tedit 5EE29C36) (tstamp 00000000-0000-0000-0000-00005f3d0b13)
+    (tstamp 00000000-0000-0000-0000-00005f3d0b13)
     (at 84.35 100.9 90)
     (tags "capacitor")
     (property "LCSC Part" "C23630")
@@ -392,30 +423,40 @@
     (solder_paste_margin -0.04)
     (attr smd)
     (fp_text reference "C20" (at 0 0 90) (layer "F.Fab")
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
       (tstamp 152462ae-8941-4aed-aaec-87510e0adfc2)
     )
     (fp_text value "2u2" (at 0 0.25 90) (layer "F.Fab")
-      (effects (font (size 0.127 0.127) (thickness 0.03175)))
+        (effects (font (size 0.127 0.127) (thickness 0.03175)))
       (tstamp ca0dd4ea-33e1-45ac-ac40-e969c4627703)
     )
     (fp_text user "${REFERENCE}" (at 0 0 90) (layer "F.SilkS") hide
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
       (tstamp 47d0e121-9040-4b4c-9cb2-92cb3ddca634)
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-    (pad "1" smd roundrect locked (at -0.75 0 90) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (fp_line (start -0.162779 -0.51) (end 0.162779 -0.51)
+      (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 8dd3d482-04ac-42de-bfa4-5bbdc8350196))
+    (fp_line (start -0.162779 0.51) (end 0.162779 0.51)
+      (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 53293114-f068-4c13-81bb-2b7566cccbce))
+    (fp_line (start -1.4 -0.7) (end 1.4 -0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 59b7583e-cb82-4825-a5f4-a44aa4d09aca))
+    (fp_line (start -1.4 0.7) (end -1.4 -0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp a66411bb-7d69-4ecd-b16d-584b5878d88e))
+    (fp_line (start 1.4 -0.7) (end 1.4 0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 86b22f09-59ca-4a8d-81ce-f44eea393466))
+    (fp_line (start 1.4 0.7) (end -1.4 0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp d926ac38-d11c-4d9e-978c-95fd4122b466))
+    (fp_line (start -0.8 -0.4) (end 0.8 -0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 8db05113-bb5d-40cb-916f-5b0147562482))
+    (fp_line (start -0.8 0.4) (end -0.8 -0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 3f8c4ada-3193-43a5-9868-069b43dbca60))
+    (fp_line (start 0.8 -0.4) (end 0.8 0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 37299e3d-49ce-49aa-8376-30d30c6526f0))
+    (fp_line (start 0.8 0.4) (end -0.8 0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp caab02da-e67e-41b8-abc1-6f3bd467a493))
+    (pad "1" smd roundrect (at -0.75 0 90) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 72 "+3V3") (pintype "passive") (tstamp 83867fb3-6ba0-43af-96e8-c8471ca3061a))
-    (pad "2" smd roundrect locked (at 0.75 0 90) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "2" smd roundrect (at 0.75 0 90) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pintype "passive") (tstamp 4442bbd3-d8c0-4204-a455-7ee1bc0d1e7f))
     (model "${KICAD6_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_0603_1608Metric.wrl"
       (offset (xyz 0 0 0))
@@ -425,7 +466,7 @@
   )
 
   (footprint "stdpads:C_0603" (layer "F.Cu")
-    (tedit 5EE29C36) (tstamp 00000000-0000-0000-0000-00005f3d0b73)
+    (tstamp 00000000-0000-0000-0000-00005f3d0b73)
     (at 97.8 111.1)
     (tags "capacitor")
     (property "LCSC Part" "C23630")
@@ -436,30 +477,40 @@
     (solder_paste_margin -0.04)
     (attr smd)
     (fp_text reference "C22" (at 0 0) (layer "F.Fab")
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
       (tstamp 6be724f3-84e2-4f15-86cb-5e411a200e25)
     )
     (fp_text value "2u2" (at 0 0.25) (layer "F.Fab")
-      (effects (font (size 0.127 0.127) (thickness 0.03175)))
+        (effects (font (size 0.127 0.127) (thickness 0.03175)))
       (tstamp 4cb60a9e-dc2d-41fb-bbf5-8affa4ccdb46)
     )
     (fp_text user "${REFERENCE}" (at 0 0) (layer "F.SilkS") hide
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
       (tstamp e5732a90-7446-4a2b-afb4-0f17831210f3)
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-    (fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer "F.SilkS") (width 0.12) (tstamp 42dcf4c2-601f-4248-9d68-3b40103215d8))
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-    (pad "1" smd roundrect locked (at -0.75 0) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (fp_line (start -0.162779 -0.51) (end 0.162779 -0.51)
+      (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 42dcf4c2-601f-4248-9d68-3b40103215d8))
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+    (fp_line (start 1.4 -0.7) (end 1.4 0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 4ffc0e0c-9347-4d35-9453-dabe6b98a910))
+    (fp_line (start 1.4 0.7) (end -1.4 0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp cfd9f318-341d-4688-a5f7-9f02b76cbe65))
+    (fp_line (start -0.8 -0.4) (end 0.8 -0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 5727536a-8c6a-4bb0-af83-c22206ca8d67))
+    (fp_line (start -0.8 0.4) (end -0.8 -0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 721bf5ed-d208-4c96-9ac4-79f167b8d3d5))
+    (fp_line (start 0.8 -0.4) (end 0.8 0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp ed6a7995-c5b4-46cf-b3b3-ce6f24c5c605))
+    (fp_line (start 0.8 0.4) (end -0.8 0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp ba05f146-ce56-491f-b141-b40dae51b132))
+    (pad "1" smd roundrect (at -0.75 0) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 72 "+3V3") (pintype "passive") (tstamp 38a89dcc-e0df-44b2-86bb-b9431bdc48d9))
-    (pad "2" smd roundrect locked (at 0.75 0) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "2" smd roundrect (at 0.75 0) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pintype "passive") (tstamp 8e27167b-bfd1-4762-bf73-25e300f92208))
     (model "${KICAD6_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_0603_1608Metric.wrl"
       (offset (xyz 0 0 0))
@@ -469,7 +520,7 @@
   )
 
   (footprint "stdpads:C_0603" (layer "F.Cu")
-    (tedit 5EE29C36) (tstamp 00000000-0000-0000-0000-00005f3d0ba3)
+    (tstamp 00000000-0000-0000-0000-00005f3d0ba3)
     (at 103.75 104.3 -90)
     (tags "capacitor")
     (property "LCSC Part" "C23630")
@@ -480,30 +531,40 @@
     (solder_paste_margin -0.04)
     (attr smd)
     (fp_text reference "C23" (at 0 0 90) (layer "F.Fab")
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
       (tstamp 5f89a2b1-7f27-4b10-80e4-ace4b437d04b)
     )
     (fp_text value "2u2" (at 0 0.25 90) (layer "F.Fab")
-      (effects (font (size 0.127 0.127) (thickness 0.03175)))
+        (effects (font (size 0.127 0.127) (thickness 0.03175)))
       (tstamp 9d7fcd45-455f-4fd8-bf85-82863fd70975)
     )
     (fp_text user "${REFERENCE}" (at 0 0 90) (layer "F.SilkS") hide
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
       (tstamp e532328d-13c5-48c8-97f2-c71bc34adc3f)
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-    (pad "1" smd roundrect locked (at -0.75 0 270) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (fp_line (start -0.162779 -0.51) (end 0.162779 -0.51)
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+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp b7abf33e-e51f-435d-92a9-82865d2f9e7f))
+    (fp_line (start 1.4 0.7) (end -1.4 0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 07bbfff7-99f4-459c-bb77-18a421617bb2))
+    (fp_line (start -0.8 -0.4) (end 0.8 -0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 3d1c775d-ed73-4c85-8a9b-21201101af2e))
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+    (fp_line (start 0.8 0.4) (end -0.8 0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 82916c6f-d03a-434a-9a9d-482533ae132e))
+    (pad "1" smd roundrect (at -0.75 0 270) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 72 "+3V3") (pintype "passive") (tstamp 01313a5e-7e20-4f63-acc5-b2bd8779e634))
-    (pad "2" smd roundrect locked (at 0.75 0 270) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "2" smd roundrect (at 0.75 0 270) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pintype "passive") (tstamp 9bcf2f5a-dcdd-4cb9-9016-05080097ffef))
     (model "${KICAD6_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_0603_1608Metric.wrl"
       (offset (xyz 0 0 0))
@@ -513,7 +574,7 @@
   )
 
   (footprint "stdpads:C_0805" (layer "F.Cu")
-    (tedit 5F02840E) (tstamp 00000000-0000-0000-0000-00005f3d0e5b)
+    (tstamp 00000000-0000-0000-0000-00005f3d0e5b)
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     (tags "capacitor")
     (property "LCSC Part" "C15850")
@@ -524,30 +585,40 @@
     (solder_paste_margin -0.025)
     (attr smd)
     (fp_text reference "C2" (at 0 -1.5) (layer "F.SilkS") hide
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     (fp_text value "10u" (at 0 0.9) (layer "F.Fab") hide
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     (fp_text user "${REFERENCE}" (at 0 0 90) (layer "F.Fab")
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+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp e713afcb-0ad9-4202-8fce-2fb74830a851))
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+      (stroke (width 0.15) (type solid)) (layer "F.Fab") (tstamp e79f0671-f01d-45ed-880e-82be7512c2d1))
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+      (stroke (width 0.15) (type solid)) (layer "F.Fab") (tstamp 1d03e574-9354-45ba-848e-c84e6726245c))
+    (fp_line (start 1 0.625) (end -1 0.625)
+      (stroke (width 0.15) (type solid)) (layer "F.Fab") (tstamp 7d4690d6-98e7-49ea-8aa6-66bebdebdb93))
+    (pad "1" smd roundrect (at -0.85 0 180) (size 1.05 1.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pintype "passive") (tstamp 82eb6b3d-b2d3-40f2-9b62-2ac01a9ee8f6))
-    (pad "2" smd roundrect locked (at 0.85 0 180) (size 1.05 1.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "2" smd roundrect (at 0.85 0 180) (size 1.05 1.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 23 "-12V") (pintype "passive") (tstamp f534dda9-0971-4076-9717-405f5f6f1264))
     (model "${KICAD6_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_0805_2012Metric.wrl"
       (offset (xyz 0 0 0))
@@ -557,7 +628,7 @@
   )
 
   (footprint "stdpads:C_0805" (layer "F.Cu")
-    (tedit 5F02840E) (tstamp 00000000-0000-0000-0000-00005f3d0e8b)
+    (tstamp 00000000-0000-0000-0000-00005f3d0e8b)
     (at 116.244 128.27)
     (tags "capacitor")
     (property "LCSC Part" "C15850")
@@ -568,30 +639,40 @@
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     (fp_text reference "C3" (at 0 -1.5) (layer "F.SilkS") hide
-      (effects (font (size 0.8128 0.8128) (thickness 0.1524)))
+        (effects (font (size 0.8128 0.8128) (thickness 0.1524)))
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     )
     (fp_text value "10u" (at 0 0.9) (layer "F.Fab") hide
-      (effects (font (size 0.127 0.127) (thickness 0.03175)))
+        (effects (font (size 0.127 0.127) (thickness 0.03175)))
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     (fp_text user "${REFERENCE}" (at 0 0 90) (layer "F.Fab")
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+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
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       (net 2 "GND") (pintype "passive") (tstamp f9956e6f-c3ae-49ff-9b0d-066510b0ba40))
-    (pad "2" smd roundrect locked (at 0.85 0) (size 1.05 1.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "2" smd roundrect (at 0.85 0) (size 1.05 1.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 24 "-5V") (pintype "passive") (tstamp 122b398f-ee45-4e4e-b430-80089f7e6427))
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       (offset (xyz 0 0 0))
@@ -601,134 +682,140 @@
   )
 
   (footprint "stdpads:AppleIIBus_Edge" (layer "F.Cu")
-    (tedit 5E89051C) (tstamp 00000000-0000-0000-0000-00005f3d0f80)
+    (tstamp 00000000-0000-0000-0000-00005f3d0f80)
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+        (effects (font (size 1 1) (thickness 0.15)))
       (tstamp a1c622cd-4fb4-4e53-83e7-417a0ab6ebcd)
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     (fp_text value "AppleIIBus" (at 0 5.207) (layer "F.Fab")
-      (effects (font (size 0.8128 0.8128) (thickness 0.1524)))
+        (effects (font (size 0.8128 0.8128) (thickness 0.1524)))
       (tstamp e0b72a8b-67fb-4e7a-aded-f100d8af0ab6)
     )
     (fp_text user "J1" (at 25.4 -5.08) (layer "B.SilkS") hide
-      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+        (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
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+    (fp_line (start -32.512 4.318) (end -32.512 -3.81)
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       (net 11 "/A2") (pinfunction "Pin_4") (pintype "passive") (tstamp 0383ded5-fa86-42c2-b225-b677173a2e63))
-    (pad "5" smd roundrect locked (at -20.32 -0.1 180) (size 1.524 7.34) (layers "F.Cu" "F.Mask") (roundrect_rratio 0.25)
+    (pad "5" smd roundrect (at -20.32 -0.1 180) (size 1.524 7.34) (layers "F.Cu" "F.Mask") (roundrect_rratio 0.25)
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+    (pad "9" smd roundrect (at -10.16 -0.1 180) (size 1.524 7.34) (layers "F.Cu" "F.Mask") (roundrect_rratio 0.25)
       (net 7 "/A7") (pinfunction "Pin_9") (pintype "passive") (tstamp c85ace76-c1ae-478f-9c4b-eef923a2984d))
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+    (pad "10" smd roundrect (at -7.62 -0.1 180) (size 1.524 7.34) (layers "F.Cu" "F.Mask") (roundrect_rratio 0.25)
       (net 6 "/A8") (pinfunction "Pin_10") (pintype "passive") (tstamp 128013b4-92f0-4f80-a481-fccffd513291))
-    (pad "11" smd roundrect locked (at -5.08 -0.1 180) (size 1.524 7.34) (layers "F.Cu" "F.Mask") (roundrect_rratio 0.25)
+    (pad "11" smd roundrect (at -5.08 -0.1 180) (size 1.524 7.34) (layers "F.Cu" "F.Mask") (roundrect_rratio 0.25)
       (net 14 "/A9") (pinfunction "Pin_11") (pintype "passive") (tstamp 9d209bce-2b1d-4859-b729-fb49b74adacd))
-    (pad "12" smd roundrect locked (at -2.54 -0.1 180) (size 1.524 7.34) (layers "F.Cu" "F.Mask") (roundrect_rratio 0.25)
+    (pad "12" smd roundrect (at -2.54 -0.1 180) (size 1.524 7.34) (layers "F.Cu" "F.Mask") (roundrect_rratio 0.25)
       (net 21 "/A10") (pinfunction "Pin_12") (pintype "passive") (tstamp a7409129-13bc-4d7a-8cc3-d55e89e4a486))
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+    (pad "13" smd roundrect (at 0 -0.1 180) (size 1.524 7.34) (layers "F.Cu" "F.Mask") (roundrect_rratio 0.25)
       (net 26 "/A11") (pinfunction "Pin_13") (pintype "passive") (tstamp 5580f029-0d73-4d2c-af54-06e31f51c0c7))
-    (pad "14" smd roundrect locked (at 2.54 -0.1 180) (size 1.524 7.34) (layers "F.Cu" "F.Mask") (roundrect_rratio 0.25)
+    (pad "14" smd roundrect (at 2.54 -0.1 180) (size 1.524 7.34) (layers "F.Cu" "F.Mask") (roundrect_rratio 0.25)
       (net 27 "/A12") (pinfunction "Pin_14") (pintype "passive") (tstamp a6f5341c-35ea-43dc-87a2-8a9e0eb79996))
-    (pad "15" smd roundrect locked (at 5.08 -0.1 180) (size 1.524 7.34) (layers "F.Cu" "F.Mask") (roundrect_rratio 0.25)
+    (pad "15" smd roundrect (at 5.08 -0.1 180) (size 1.524 7.34) (layers "F.Cu" "F.Mask") (roundrect_rratio 0.25)
       (net 28 "/A13") (pinfunction "Pin_15") (pintype "passive") (tstamp e6daff5c-d445-4c90-98e4-c209d0b5c4d1))
-    (pad "16" smd roundrect locked (at 7.62 -0.1 180) (size 1.524 7.34) (layers "F.Cu" "F.Mask") (roundrect_rratio 0.25)
+    (pad "16" smd roundrect (at 7.62 -0.1 180) (size 1.524 7.34) (layers "F.Cu" "F.Mask") (roundrect_rratio 0.25)
       (net 29 "/A14") (pinfunction "Pin_16") (pintype "passive") (tstamp c7004714-a632-4445-b0df-bb4644d1bf5f))
-    (pad "17" smd roundrect locked (at 10.16 -0.1 180) (size 1.524 7.34) (layers "F.Cu" "F.Mask") (roundrect_rratio 0.25)
+    (pad "17" smd roundrect (at 10.16 -0.1 180) (size 1.524 7.34) (layers "F.Cu" "F.Mask") (roundrect_rratio 0.25)
       (net 30 "/A15") (pinfunction "Pin_17") (pintype "passive") (tstamp 1a74e4ef-9f04-445e-a4d4-879b5e2f061a))
-    (pad "18" smd roundrect locked (at 12.7 -0.1 180) (size 1.524 7.34) (layers "F.Cu" "F.Mask") (roundrect_rratio 0.25)
+    (pad "18" smd roundrect (at 12.7 -0.1 180) (size 1.524 7.34) (layers "F.Cu" "F.Mask") (roundrect_rratio 0.25)
       (net 31 "/R~{W}") (pinfunction "Pin_18") (pintype "passive") (tstamp 7d8c055d-4eed-4649-b6f4-62afe1b9f5a9))
-    (pad "19" smd roundrect locked (at 15.24 -0.1 180) (size 1.524 7.34) (layers "F.Cu" "F.Mask") (roundrect_rratio 0.25)
+    (pad "19" smd roundrect (at 15.24 -0.1 180) (size 1.524 7.34) (layers "F.Cu" "F.Mask") (roundrect_rratio 0.25)
       (net 71 "/VIDSYNC") (pinfunction "Pin_19") (pintype "passive") (tstamp 743faa0d-9458-49ff-804f-08ea0d7c26e5))
-    (pad "20" smd roundrect locked (at 17.78 -0.1 180) (size 1.524 7.34) (layers "F.Cu" "F.Mask") (roundrect_rratio 0.25)
+    (pad "20" smd roundrect (at 17.78 -0.1 180) (size 1.524 7.34) (layers "F.Cu" "F.Mask") (roundrect_rratio 0.25)
       (net 32 "/~{IOSTRB}") (pinfunction "Pin_20") (pintype "passive") (tstamp 8e583f97-15ba-4914-92f3-b244f09eb9dd))
-    (pad "21" smd roundrect locked (at 20.32 -0.1 180) (size 1.524 7.34) (layers "F.Cu" "F.Mask") (roundrect_rratio 0.25)
+    (pad "21" smd roundrect (at 20.32 -0.1 180) (size 1.524 7.34) (layers "F.Cu" "F.Mask") (roundrect_rratio 0.25)
       (net 105 "/~{RDY}") (pinfunction "Pin_21") (pintype "passive") (tstamp 23a2bbba-f5b1-4ac5-afce-63d0bb06e293))
-    (pad "22" smd roundrect locked (at 22.86 -0.1 180) (size 1.524 7.34) (layers "F.Cu" "F.Mask") (roundrect_rratio 0.25)
+    (pad "22" smd roundrect (at 22.86 -0.1 180) (size 1.524 7.34) (layers "F.Cu" "F.Mask") (roundrect_rratio 0.25)
       (net 73 "/~{DMA}") (pinfunction "Pin_22") (pintype "passive") (tstamp a66ae5a0-1026-4e58-8b7d-a865e1e240b4))
-    (pad "23" smd roundrect locked (at 25.4 -0.1 180) (size 1.524 7.34) (layers "F.Cu" "F.Mask") (roundrect_rratio 0.25)
+    (pad "23" smd roundrect (at 25.4 -0.1 180) (size 1.524 7.34) (layers "F.Cu" "F.Mask") (roundrect_rratio 0.25)
       (net 44 "/INTin") (pinfunction "Pin_23") (pintype "passive") (tstamp 72736ef0-440f-445e-90eb-c81ae8522fbc))
-    (pad "24" smd roundrect locked (at 27.94 -0.1 180) (size 1.524 7.34) (layers "F.Cu" "F.Mask") (roundrect_rratio 0.25)
+    (pad "24" smd roundrect (at 27.94 -0.1 180) (size 1.524 7.34) (layers "F.Cu" "F.Mask") (roundrect_rratio 0.25)
       (net 45 "/DMAin") (pinfunction "Pin_24") (pintype "passive") (tstamp 62b9c199-3c77-4c44-a4fe-53867aefe7d2))
-    (pad "25" smd roundrect locked (at 30.48 -0.1 180) (size 1.524 7.34) (layers "F.Cu" "F.Mask") (roundrect_rratio 0.25)
+    (pad "25" smd roundrect (at 30.48 -0.1 180) (size 1.524 7.34) (layers "F.Cu" "F.Mask") (roundrect_rratio 0.25)
       (net 1 "+5V") (pinfunction "Pin_25") (pintype "passive") (tstamp d6b6326d-c925-4334-96f5-218472fffcc2))
-    (pad "26" smd roundrect locked (at 30.48 -0.1 180) (size 1.524 7.34) (layers "B.Cu" "B.Mask") (roundrect_rratio 0.25)
+    (pad "26" smd roundrect (at 30.48 -0.1 180) (size 1.524 7.34) (layers "B.Cu" "B.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pinfunction "Pin_26") (pintype "passive") (tstamp 79ede70e-9855-4371-b98c-b65c34fa0309))
-    (pad "27" smd roundrect locked (at 27.94 -0.1 180) (size 1.524 7.34) (layers "B.Cu" "B.Mask") (roundrect_rratio 0.25)
+    (pad "27" smd roundrect (at 27.94 -0.1 180) (size 1.524 7.34) (layers "B.Cu" "B.Mask") (roundrect_rratio 0.25)
       (net 45 "/DMAin") (pinfunction "Pin_27") (pintype "passive") (tstamp 483b7e8e-4d33-4fa9-ad55-51d1f684cb5f))
-    (pad "28" smd roundrect locked (at 25.4 -0.1 180) (size 1.524 7.34) (layers "B.Cu" "B.Mask") (roundrect_rratio 0.25)
+    (pad "28" smd roundrect (at 25.4 -0.1 180) (size 1.524 7.34) (layers "B.Cu" "B.Mask") (roundrect_rratio 0.25)
       (net 44 "/INTin") (pinfunction "Pin_28") (pintype "passive") (tstamp abd8f63e-8fbf-4ad4-a216-38dee4937522))
-    (pad "29" smd roundrect locked (at 22.86 -0.1 180) (size 1.524 7.34) (layers "B.Cu" "B.Mask") (roundrect_rratio 0.25)
+    (pad "29" smd roundrect (at 22.86 -0.1 180) (size 1.524 7.34) (layers "B.Cu" "B.Mask") (roundrect_rratio 0.25)
       (net 33 "/~{NMI}") (pinfunction "Pin_29") (pintype "passive") (tstamp 038aeddc-6d2a-4762-b5a9-bb808a6321d9))
-    (pad "30" smd roundrect locked (at 20.32 -0.1 180) (size 1.524 7.34) (layers "B.Cu" "B.Mask") (roundrect_rratio 0.25)
+    (pad "30" smd roundrect (at 20.32 -0.1 180) (size 1.524 7.34) (layers "B.Cu" "B.Mask") (roundrect_rratio 0.25)
       (net 34 "/~{IRQ}") (pinfunction "Pin_30") (pintype "passive") (tstamp dc9dea80-2c29-4fad-a713-8cffd4365ce9))
-    (pad "31" smd roundrect locked (at 17.78 -0.1 180) (size 1.524 7.34) (layers "B.Cu" "B.Mask") (roundrect_rratio 0.25)
+    (pad "31" smd roundrect (at 17.78 -0.1 180) (size 1.524 7.34) (layers "B.Cu" "B.Mask") (roundrect_rratio 0.25)
       (net 35 "/~{RES}") (pinfunction "Pin_31") (pintype "passive") (tstamp 5423be76-3cf4-4929-b119-321703c4311f))
-    (pad "32" smd roundrect locked (at 15.24 -0.1 180) (size 1.524 7.34) (layers "B.Cu" "B.Mask") (roundrect_rratio 0.25)
+    (pad "32" smd roundrect (at 15.24 -0.1 180) (size 1.524 7.34) (layers "B.Cu" "B.Mask") (roundrect_rratio 0.25)
       (net 36 "/~{INH}") (pinfunction "Pin_32") (pintype "passive") (tstamp af66195b-d32c-42e8-b5e8-081fb74851c7))
-    (pad "33" smd roundrect locked (at 12.7 -0.1 180) (size 1.524 7.34) (layers "B.Cu" "B.Mask") (roundrect_rratio 0.25)
+    (pad "33" smd roundrect (at 12.7 -0.1 180) (size 1.524 7.34) (layers "B.Cu" "B.Mask") (roundrect_rratio 0.25)
       (net 23 "-12V") (pinfunction "Pin_33") (pintype "passive") (tstamp 857de716-20e5-42ab-af4e-373b887c2e9d))
-    (pad "34" smd roundrect locked (at 10.16 -0.1 180) (size 1.524 7.34) (layers "B.Cu" "B.Mask") (roundrect_rratio 0.25)
+    (pad "34" smd roundrect (at 10.16 -0.1 180) (size 1.524 7.34) (layers "B.Cu" "B.Mask") (roundrect_rratio 0.25)
       (net 24 "-5V") (pinfunction "Pin_34") (pintype "passive") (tstamp df76744a-2672-4df3-b0f1-8632a1e0c956))
-    (pad "35" smd roundrect locked (at 7.62 -0.1 180) (size 1.524 7.34) (layers "B.Cu" "B.Mask") (roundrect_rratio 0.25)
+    (pad "35" smd roundrect (at 7.62 -0.1 180) (size 1.524 7.34) (layers "B.Cu" "B.Mask") (roundrect_rratio 0.25)
       (net 37 "/COLORREF") (pinfunction "Pin_35") (pintype "passive") (tstamp 092bd764-4a2b-48e9-b1b3-8d92072d4239))
-    (pad "36" smd roundrect locked (at 5.08 -0.1 180) (size 1.524 7.34) (layers "B.Cu" "B.Mask") (roundrect_rratio 0.25)
+    (pad "36" smd roundrect (at 5.08 -0.1 180) (size 1.524 7.34) (layers "B.Cu" "B.Mask") (roundrect_rratio 0.25)
       (net 38 "/7M") (pinfunction "Pin_36") (pintype "passive") (tstamp b5fd13b1-afc0-46e0-8a94-ced2c102d545))
-    (pad "37" smd roundrect locked (at 2.54 -0.1 180) (size 1.524 7.34) (layers "B.Cu" "B.Mask") (roundrect_rratio 0.25)
+    (pad "37" smd roundrect (at 2.54 -0.1 180) (size 1.524 7.34) (layers "B.Cu" "B.Mask") (roundrect_rratio 0.25)
       (net 39 "/Q3") (pinfunction "Pin_37") (pintype "passive") (tstamp 62c1f671-9c5a-42d1-bb72-93a0fddab631))
-    (pad "38" smd roundrect locked (at 0 -0.1 180) (size 1.524 7.34) (layers "B.Cu" "B.Mask") (roundrect_rratio 0.25)
+    (pad "38" smd roundrect (at 0 -0.1 180) (size 1.524 7.34) (layers "B.Cu" "B.Mask") (roundrect_rratio 0.25)
       (net 40 "/PHI1") (pinfunction "Pin_38") (pintype "passive") (tstamp 462300d8-5235-4268-b945-a065aa4bccf1))
-    (pad "39" smd roundrect locked (at -2.54 -0.1 180) (size 1.524 7.34) (layers "B.Cu" "B.Mask") (roundrect_rratio 0.25)
+    (pad "39" smd roundrect (at -2.54 -0.1 180) (size 1.524 7.34) (layers "B.Cu" "B.Mask") (roundrect_rratio 0.25)
       (net 41 "/USER1") (pinfunction "Pin_39") (pintype "passive") (tstamp b87a01ba-9438-409e-8ee0-7b599746cffd))
-    (pad "40" smd roundrect locked (at -5.08 -0.1 180) (size 1.524 7.34) (layers "B.Cu" "B.Mask") (roundrect_rratio 0.25)
+    (pad "40" smd roundrect (at -5.08 -0.1 180) (size 1.524 7.34) (layers "B.Cu" "B.Mask") (roundrect_rratio 0.25)
       (net 42 "/PHI0") (pinfunction "Pin_40") (pintype "passive") (tstamp 7879eef7-0cd6-4b28-a2a3-4b84c2150254))
-    (pad "41" smd roundrect locked (at -7.62 -0.1 180) (size 1.524 7.34) (layers "B.Cu" "B.Mask") (roundrect_rratio 0.25)
+    (pad "41" smd roundrect (at -7.62 -0.1 180) (size 1.524 7.34) (layers "B.Cu" "B.Mask") (roundrect_rratio 0.25)
       (net 43 "/~{DEVSEL}") (pinfunction "Pin_41") (pintype "passive") (tstamp af34f5bd-9c3b-44b4-99ba-829473dbca73))
-    (pad "42" smd roundrect locked (at -10.16 -0.1 180) (size 1.524 7.34) (layers "B.Cu" "B.Mask") (roundrect_rratio 0.25)
+    (pad "42" smd roundrect (at -10.16 -0.1 180) (size 1.524 7.34) (layers "B.Cu" "B.Mask") (roundrect_rratio 0.25)
       (net 4 "/D7") (pinfunction "Pin_42") (pintype "passive") (tstamp 07dd891f-9b97-4653-b99a-854fc7239a79))
-    (pad "43" smd roundrect locked (at -12.7 -0.1 180) (size 1.524 7.34) (layers "B.Cu" "B.Mask") (roundrect_rratio 0.25)
+    (pad "43" smd roundrect (at -12.7 -0.1 180) (size 1.524 7.34) (layers "B.Cu" "B.Mask") (roundrect_rratio 0.25)
       (net 5 "/D6") (pinfunction "Pin_43") (pintype "passive") (tstamp 38471577-701a-4bf2-934b-75b2b984b254))
-    (pad "44" smd roundrect locked (at -15.24 -0.1 180) (size 1.524 7.34) (layers "B.Cu" "B.Mask") (roundrect_rratio 0.25)
+    (pad "44" smd roundrect (at -15.24 -0.1 180) (size 1.524 7.34) (layers "B.Cu" "B.Mask") (roundrect_rratio 0.25)
       (net 16 "/D5") (pinfunction "Pin_44") (pintype "passive") (tstamp 4a628444-da22-4536-bd76-0f08b97bd6ad))
-    (pad "45" smd roundrect locked (at -17.78 -0.1 180) (size 1.524 7.34) (layers "B.Cu" "B.Mask") (roundrect_rratio 0.25)
+    (pad "45" smd roundrect (at -17.78 -0.1 180) (size 1.524 7.34) (layers "B.Cu" "B.Mask") (roundrect_rratio 0.25)
       (net 20 "/D4") (pinfunction "Pin_45") (pintype "passive") (tstamp f74d16ce-07bc-40a1-9379-7e7fa809b111))
-    (pad "46" smd roundrect locked (at -20.32 -0.1 180) (size 1.524 7.34) (layers "B.Cu" "B.Mask") (roundrect_rratio 0.25)
+    (pad "46" smd roundrect (at -20.32 -0.1 180) (size 1.524 7.34) (layers "B.Cu" "B.Mask") (roundrect_rratio 0.25)
       (net 19 "/D3") (pinfunction "Pin_46") (pintype "passive") (tstamp 96a5c046-2bb8-4223-addc-0967a661f4f5))
-    (pad "47" smd roundrect locked (at -22.86 -0.1 180) (size 1.524 7.34) (layers "B.Cu" "B.Mask") (roundrect_rratio 0.25)
+    (pad "47" smd roundrect (at -22.86 -0.1 180) (size 1.524 7.34) (layers "B.Cu" "B.Mask") (roundrect_rratio 0.25)
       (net 18 "/D2") (pinfunction "Pin_47") (pintype "passive") (tstamp cebbf6fc-d03b-437a-8cdc-3f5a9d9fca58))
-    (pad "48" smd roundrect locked (at -25.4 -0.1 180) (size 1.524 7.34) (layers "B.Cu" "B.Mask") (roundrect_rratio 0.25)
+    (pad "48" smd roundrect (at -25.4 -0.1 180) (size 1.524 7.34) (layers "B.Cu" "B.Mask") (roundrect_rratio 0.25)
       (net 15 "/D1") (pinfunction "Pin_48") (pintype "passive") (tstamp 830285c1-8bd7-4405-9db4-47f2bd6aa43e))
-    (pad "49" smd roundrect locked (at -27.94 -0.1 180) (size 1.524 7.34) (layers "B.Cu" "B.Mask") (roundrect_rratio 0.25)
+    (pad "49" smd roundrect (at -27.94 -0.1 180) (size 1.524 7.34) (layers "B.Cu" "B.Mask") (roundrect_rratio 0.25)
       (net 17 "/D0") (pinfunction "Pin_49") (pintype "passive") (tstamp a133212b-4ede-4fe9-89c1-db6ffbb2f2e4))
-    (pad "50" smd roundrect locked (at -30.48 -0.1 180) (size 1.524 7.34) (layers "B.Cu" "B.Mask") (roundrect_rratio 0.25)
+    (pad "50" smd roundrect (at -30.48 -0.1 180) (size 1.524 7.34) (layers "B.Cu" "B.Mask") (roundrect_rratio 0.25)
       (net 22 "+12V") (pinfunction "Pin_50") (pintype "passive") (tstamp cb009da4-648f-43fe-9e7c-121350173aa3))
   )
 
   (footprint "stdpads:Fiducial" (layer "F.Cu")
-    (tedit 5F1BCA76) (tstamp 00000000-0000-0000-0000-00005f3d1029)
+    (tstamp 00000000-0000-0000-0000-00005f3d1029)
     (at 143.002 82.423 -90)
     (descr "Circular Fiducial, 1mm bare copper top; 2mm keepout (Level A)")
     (tags "marker")
@@ -737,24 +824,25 @@
     (path "/00000000-0000-0000-0000-00005f45d10c")
     (attr smd)
     (fp_text reference "FID1" (at 0 -1.6 90) (layer "F.SilkS") hide
-      (effects (font (size 0.508 0.508) (thickness 0.127)))
+        (effects (font (size 0.508 0.508) (thickness 0.127)))
       (tstamp ace74cf6-fd28-4884-9baa-d9f2aa9480dc)
     )
     (fp_text value "Fiducial" (at 0 2 90) (layer "F.Fab") hide
-      (effects (font (size 0.508 0.508) (thickness 0.127)))
+        (effects (font (size 0.508 0.508) (thickness 0.127)))
       (tstamp e6c3ab45-2af8-493c-ab47-0c0dc092a8c1)
     )
     (fp_text user "${REFERENCE}" (at 0 0 90) (layer "F.Fab")
-      (effects (font (size 0.4 0.4) (thickness 0.06)))
+        (effects (font (size 0.4 0.4) (thickness 0.06)))
       (tstamp 749d9ed0-2ff2-4b55-abc5-f7231ec3aa28)
     )
-    (fp_circle (center 0 0) (end 1 0) (layer "F.Fab") (width 0.1) (fill none) (tstamp 4be4cec3-a7c3-4cd9-84cd-e328276cb23e))
-    (pad "~" smd circle locked (at 0 0 270) (size 1 1) (layers "F.Cu" "F.Mask")
+    (fp_circle (center 0 0) (end 1 0)
+      (stroke (width 0.1) (type solid)) (fill none) (layer "F.Fab") (tstamp 4be4cec3-a7c3-4cd9-84cd-e328276cb23e))
+    (pad "~" smd circle (at 0 0 270) (size 1 1) (layers "F.Cu" "F.Mask")
       (solder_mask_margin 0.5) (clearance 0.575) (tstamp 86b01ef4-965c-4060-a9de-b3e20d6f4e09))
   )
 
   (footprint "stdpads:Fiducial" (layer "F.Cu")
-    (tedit 5F1BCA76) (tstamp 00000000-0000-0000-0000-00005f3d1053)
+    (tstamp 00000000-0000-0000-0000-00005f3d1053)
     (at 143.002 129.54)
     (descr "Circular Fiducial, 1mm bare copper top; 2mm keepout (Level A)")
     (tags "marker")
@@ -763,24 +851,25 @@
     (path "/00000000-0000-0000-0000-00005f45d10f")
     (attr smd)
     (fp_text reference "FID4" (at 2.032 0) (layer "F.SilkS") hide
-      (effects (font (size 0.508 0.508) (thickness 0.127)))
+        (effects (font (size 0.508 0.508) (thickness 0.127)))
       (tstamp 2d21e9d4-5f95-4bd5-bafa-7195b8da2940)
     )
     (fp_text value "Fiducial" (at 0 2) (layer "F.Fab") hide
-      (effects (font (size 0.508 0.508) (thickness 0.127)))
+        (effects (font (size 0.508 0.508) (thickness 0.127)))
       (tstamp 31aad1ff-f8eb-44a2-b0e6-6f2533cadd8a)
     )
     (fp_text user "${REFERENCE}" (at 0 0) (layer "F.Fab")
-      (effects (font (size 0.4 0.4) (thickness 0.06)))
+        (effects (font (size 0.4 0.4) (thickness 0.06)))
       (tstamp 29126f72-63f7-4275-8b12-6b96a71c6f17)
     )
-    (fp_circle (center 0 0) (end 1 0) (layer "F.Fab") (width 0.1) (fill none) (tstamp e57bcf50-81ce-4f5a-839b-106d5a693317))
-    (pad "~" smd circle locked (at 0 0) (size 1 1) (layers "F.Cu" "F.Mask")
+    (fp_circle (center 0 0) (end 1 0)
+      (stroke (width 0.1) (type solid)) (fill none) (layer "F.Fab") (tstamp e57bcf50-81ce-4f5a-839b-106d5a693317))
+    (pad "~" smd circle (at 0 0) (size 1 1) (layers "F.Cu" "F.Mask")
       (solder_mask_margin 0.5) (clearance 0.575) (tstamp 4cf23c4a-c03c-4897-b0d2-e5da4fd74f72))
   )
 
   (footprint "stdpads:PasteHole_1.1mm_PTH" (layer "F.Cu")
-    (tedit 5E892B4B) (tstamp 00000000-0000-0000-0000-00005f3d1068)
+    (tstamp 00000000-0000-0000-0000-00005f3d1068)
     (at 140.462 129.54)
     (descr "Circular Fiducial, 1mm bare copper top; 2mm keepout (Level A)")
     (tags "marker")
@@ -790,24 +879,25 @@
     (zone_connect 2)
     (attr exclude_from_pos_files)
     (fp_text reference "H1" (at -1.905 0) (layer "F.SilkS") hide
-      (effects (font (size 0.508 0.508) (thickness 0.127)))
+        (effects (font (size 0.508 0.508) (thickness 0.127)))
       (tstamp 662ecc62-5101-4658-ba95-fd6acdb2ca0d)
     )
     (fp_text value " " (at 0 2) (layer "F.Fab") hide
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     (fp_text user "${REFERENCE}" (at 0 0) (layer "F.Fab")
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+        (effects (font (size 0.4 0.4) (thickness 0.06)))
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-    (pad "1" thru_hole circle locked (at 0 0) (size 2 2) (drill 1.1) (layers *.Cu *.Mask)
+    (fp_circle (center 0 0) (end 1 0)
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+    (pad "1" thru_hole circle (at 0 0) (size 2 2) (drill 1.1) (layers "*.Cu" "*.Mask")
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   (footprint "stdpads:C_0805" (layer "F.Cu")
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+    (tstamp 00000000-0000-0000-0000-00005f3d109b)
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     (tags "capacitor")
     (property "LCSC Part" "C15850")
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     (fp_text user "${REFERENCE}" (at 0 0 90) (layer "F.Fab")
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+    (pad "1" smd roundrect (at -0.85 0 180) (size 1.05 1.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 22 "+12V") (pintype "passive") (tstamp 05b544c2-a26d-4af7-9516-78e8af8d4f5d))
-    (pad "2" smd roundrect locked (at 0.85 0 180) (size 1.05 1.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "2" smd roundrect (at 0.85 0 180) (size 1.05 1.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pintype "passive") (tstamp 62c1974a-816e-4477-a1c3-21a16c6b106b))
     (model "${KICAD6_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_0805_2012Metric.wrl"
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@@ -851,7 +951,7 @@
   )
 
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-    (tedit 5F27C9F6) (tstamp 00000000-0000-0000-0000-00005f3d1276)
+    (tstamp 00000000-0000-0000-0000-00005f3d1276)
     (at 99.425 122)
     (descr "20-Lead Plastic Thin Shrink Small Outline (ST)-4.4 mm Body [TSSOP] (see Microchip Packaging Specification 00000049BS.pdf)")
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     (attr smd)
     (fp_text reference "U9" (at 0 0 180) (layer "F.Fab")
-      (effects (font (size 0.8128 0.8128) (thickness 0.2032)))
+        (effects (font (size 0.8128 0.8128) (thickness 0.2032)))
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     (fp_text value "74AHC245PW" (at 0 1.016 180) (layer "F.Fab")
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     (fp_text user "${REFERENCE}" (at 0 0) (layer "F.SilkS")
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+        (effects (font (size 0.8128 0.8128) (thickness 0.2032)))
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-    (pad "18" smd roundrect locked (at -1.625 -2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "18" smd roundrect (at -1.625 -2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 61 "/RA8") (pinfunction "B0") (pintype "bidirectional") (tstamp 1ae5f305-82c0-4608-bb44-6f54108bdca6))
-    (pad "19" smd roundrect locked (at -2.275 -2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "19" smd roundrect (at -2.275 -2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pinfunction "~{OE}") (pintype "input") (tstamp ead84776-ed6d-4174-bd4e-7ec24866ecbd))
-    (pad "20" smd roundrect locked (at -2.925 -2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "20" smd roundrect (at -2.925 -2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 72 "+3V3") (pinfunction "Vcc") (pintype "power_in") (tstamp 1ec0ce2e-e50a-400a-befc-90da75632739))
     (model "${KICAD6_3DMODEL_DIR}/Package_SO.3dshapes/TSSOP-20_4.4x6.5mm_P0.65mm.wrl"
       (offset (xyz 0 0 0))
@@ -933,7 +1044,7 @@
   )
 
   (footprint "stdpads:C_0603" (layer "F.Cu")
-    (tedit 5EE29C36) (tstamp 00000000-0000-0000-0000-00005f3d139e)
+    (tstamp 00000000-0000-0000-0000-00005f3d139e)
     (at 85.8 119.8 -90)
     (tags "capacitor")
     (property "LCSC Part" "C23630")
@@ -944,30 +1055,40 @@
     (solder_paste_margin -0.04)
     (attr smd)
     (fp_text reference "C14" (at 0 0 90) (layer "F.Fab")
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
       (tstamp bf813ca6-c9b0-496b-a4b2-6cd15e7fa5b4)
     )
     (fp_text value "2u2" (at 0 0.25 90) (layer "F.Fab")
-      (effects (font (size 0.127 0.127) (thickness 0.03175)))
+        (effects (font (size 0.127 0.127) (thickness 0.03175)))
       (tstamp 5a6be6a3-f5c4-4588-90de-f3e15e2ac316)
     )
     (fp_text user "${REFERENCE}" (at 0 0 90) (layer "F.SilkS") hide
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
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+    (fp_line (start -0.162779 -0.51) (end 0.162779 -0.51)
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+    (fp_line (start -1.4 0.7) (end -1.4 -0.7)
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+    (fp_line (start 1.4 0.7) (end -1.4 0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 85efdcf2-b2af-4074-a8ec-46a9b78ab437))
+    (fp_line (start -0.8 -0.4) (end 0.8 -0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp db9957af-88ae-4b9b-878b-fca16796b164))
+    (fp_line (start -0.8 0.4) (end -0.8 -0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 5c7c0c83-cf5c-46a4-ae62-2577f5eb25b0))
+    (fp_line (start 0.8 -0.4) (end 0.8 0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp e25678c3-7a6f-406f-b60f-2c8f0cc0a45b))
+    (fp_line (start 0.8 0.4) (end -0.8 0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 477159c8-6842-4fdb-8985-f042f4e62500))
+    (pad "1" smd roundrect (at -0.75 0 270) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 72 "+3V3") (pintype "passive") (tstamp 703150a7-37b9-4b76-9d37-11ae64256376))
-    (pad "2" smd roundrect locked (at 0.75 0 270) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "2" smd roundrect (at 0.75 0 270) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pintype "passive") (tstamp 828b8d03-83cc-420b-b714-b293db456120))
     (model "${KICAD6_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_0603_1608Metric.wrl"
       (offset (xyz 0 0 0))
@@ -977,7 +1098,7 @@
   )
 
   (footprint "stdpads:C_0603" (layer "F.Cu")
-    (tedit 5EE29C36) (tstamp 00000000-0000-0000-0000-00005f3d145b)
+    (tstamp 00000000-0000-0000-0000-00005f3d145b)
     (at 90.8 111.1)
     (tags "capacitor")
     (property "LCSC Part" "C23630")
@@ -988,30 +1109,40 @@
     (solder_paste_margin -0.04)
     (attr smd)
     (fp_text reference "C21" (at 0 0) (layer "F.Fab")
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
       (tstamp e1a2236e-9438-4cf8-9628-4a2edf553390)
     )
     (fp_text value "2u2" (at 0 0.25) (layer "F.Fab")
-      (effects (font (size 0.127 0.127) (thickness 0.03175)))
+        (effects (font (size 0.127 0.127) (thickness 0.03175)))
       (tstamp b3d1a865-d236-4925-8344-02aa33a87f58)
     )
     (fp_text user "${REFERENCE}" (at 0 0) (layer "F.SilkS") hide
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
       (tstamp b34cff2e-78c2-49a6-9001-30a5ac33b0bb)
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+    (fp_line (start -0.162779 -0.51) (end 0.162779 -0.51)
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+    (fp_line (start 1.4 -0.7) (end 1.4 0.7)
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+    (fp_line (start 1.4 0.7) (end -1.4 0.7)
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+    (fp_line (start 0.8 0.4) (end -0.8 0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp e4030a5f-e6b4-4560-aef2-6d9501812e36))
+    (pad "1" smd roundrect (at -0.75 0) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 72 "+3V3") (pintype "passive") (tstamp 75b252a7-0139-4502-9cd4-8ce04a5a16ec))
-    (pad "2" smd roundrect locked (at 0.75 0) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "2" smd roundrect (at 0.75 0) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pintype "passive") (tstamp 2abf9bd9-2e75-4bc7-9218-8b355c67c085))
     (model "${KICAD6_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_0603_1608Metric.wrl"
       (offset (xyz 0 0 0))
@@ -1021,7 +1152,7 @@
   )
 
   (footprint "stdpads:C_0603" (layer "F.Cu")
-    (tedit 5EE29C36) (tstamp 00000000-0000-0000-0000-00005f3d158d)
+    (tstamp 00000000-0000-0000-0000-00005f3d158d)
     (at 95 119.8 -90)
     (tags "capacitor")
     (property "LCSC Part" "C23630")
@@ -1032,30 +1163,40 @@
     (solder_paste_margin -0.04)
     (attr smd)
     (fp_text reference "C15" (at 0 0 90) (layer "F.Fab")
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
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     )
     (fp_text value "2u2" (at 0 0.25 90) (layer "F.Fab")
-      (effects (font (size 0.127 0.127) (thickness 0.03175)))
+        (effects (font (size 0.127 0.127) (thickness 0.03175)))
       (tstamp 483dd64e-74ad-4e0b-8c97-c0bda14b5bdc)
     )
     (fp_text user "${REFERENCE}" (at 0 0 90) (layer "F.SilkS") hide
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
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+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp e44ebcdd-421a-4d0e-a6a9-b5a8694a3c1c))
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       (net 72 "+3V3") (pintype "passive") (tstamp c61301da-1ef8-499e-9a32-cbb3c6153f2c))
-    (pad "2" smd roundrect locked (at 0.75 0 270) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "2" smd roundrect (at 0.75 0 270) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pintype "passive") (tstamp 1bbd18cb-9fc4-4ea0-9bcb-de4193872036))
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       (offset (xyz 0 0 0))
@@ -1065,7 +1206,7 @@
   )
 
   (footprint "stdpads:C_0805" (layer "F.Cu")
-    (tedit 5F02840E) (tstamp 00000000-0000-0000-0000-00005f3d166b)
+    (tstamp 00000000-0000-0000-0000-00005f3d166b)
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@@ -1109,7 +1260,7 @@
   )
 
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     (descr "20-Lead Plastic Thin Shrink Small Outline (ST)-4.4 mm Body [TSSOP] (see Microchip Packaging Specification 00000049BS.pdf)")
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     (model "${KICAD6_3DMODEL_DIR}/Package_SO.3dshapes/TSSOP-20_4.4x6.5mm_P0.65mm.wrl"
       (offset (xyz 0 0 0))
@@ -1191,7 +1353,7 @@
   )
 
   (footprint "stdpads:C_0603" (layer "F.Cu")
-    (tedit 5EE29C36) (tstamp 00000000-0000-0000-0000-00005f4403d9)
+    (tstamp 00000000-0000-0000-0000-00005f4403d9)
     (at 84.35 98 90)
     (tags "capacitor")
     (property "LCSC Part" "C23630")
@@ -1202,30 +1364,40 @@
     (solder_paste_margin -0.04)
     (attr smd)
     (fp_text reference "C19" (at 0 0 90) (layer "F.Fab")
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
       (tstamp 0789c018-baf5-4a9a-94f8-ebb91f545f31)
     )
     (fp_text value "2u2" (at 0 0.25 90) (layer "F.Fab")
-      (effects (font (size 0.127 0.127) (thickness 0.03175)))
+        (effects (font (size 0.127 0.127) (thickness 0.03175)))
       (tstamp 4e7277b8-8a25-4181-95e8-e09bd3dcd4ba)
     )
     (fp_text user "${REFERENCE}" (at 0 0 90) (layer "F.SilkS") hide
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
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-    (pad "1" smd roundrect locked (at -0.75 0 90) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (fp_line (start -0.162779 -0.51) (end 0.162779 -0.51)
+      (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 7897f435-ca2e-4185-ae83-837e505bab70))
+    (fp_line (start -0.162779 0.51) (end 0.162779 0.51)
+      (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 5eb4aecd-e0df-42c4-9716-e679c869f63c))
+    (fp_line (start -1.4 -0.7) (end 1.4 -0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 2954cbf6-557e-41c5-b14d-1c0f3f541f12))
+    (fp_line (start -1.4 0.7) (end -1.4 -0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 93aeef62-c4d4-4345-8487-cc4871395e12))
+    (fp_line (start 1.4 -0.7) (end 1.4 0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 9985c9ac-c2cb-4bc0-a36c-a2fd435d77ee))
+    (fp_line (start 1.4 0.7) (end -1.4 0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp c9dbb32b-71f2-4c94-afae-76ff97321dd5))
+    (fp_line (start -0.8 -0.4) (end 0.8 -0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 13b942f4-70b4-4c16-8221-c0d89d92d9f4))
+    (fp_line (start -0.8 0.4) (end -0.8 -0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 88888024-6d70-4fa8-9829-8295a00fc2c9))
+    (fp_line (start 0.8 -0.4) (end 0.8 0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp eccc4eee-4290-4334-8514-2f5669abdefa))
+    (fp_line (start 0.8 0.4) (end -0.8 0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 5162987c-ba0e-48a9-b339-be2441c4705f))
+    (pad "1" smd roundrect (at -0.75 0 90) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 72 "+3V3") (pintype "passive") (tstamp 575fdc89-9805-4266-a2d9-595fa263b11a))
-    (pad "2" smd roundrect locked (at 0.75 0 90) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "2" smd roundrect (at 0.75 0 90) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pintype "passive") (tstamp 0ad96c7a-dc28-4121-8e73-05b2064bbec3))
     (model "${KICAD6_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_0603_1608Metric.wrl"
       (offset (xyz 0 0 0))
@@ -1235,7 +1407,7 @@
   )
 
   (footprint "stdpads:C_0603" (layer "F.Cu")
-    (tedit 5EE29C36) (tstamp 00000000-0000-0000-0000-00005f4b2625)
+    (tstamp 00000000-0000-0000-0000-00005f4b2625)
     (at 126.45 103.8 -90)
     (tags "capacitor")
     (property "LCSC Part" "C23630")
@@ -1246,30 +1418,40 @@
     (solder_paste_margin -0.04)
     (attr smd)
     (fp_text reference "C31" (at 0 0 90) (layer "F.Fab")
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
       (tstamp daaa414d-49a8-4397-86ba-295d6dedf1a8)
     )
     (fp_text value "2u2" (at 0 0.25 90) (layer "F.Fab")
-      (effects (font (size 0.127 0.127) (thickness 0.03175)))
+        (effects (font (size 0.127 0.127) (thickness 0.03175)))
       (tstamp f8b22858-19d0-4658-8c54-d50707981b51)
     )
     (fp_text user "${REFERENCE}" (at 0 0 90) (layer "F.SilkS") hide
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
       (tstamp 6175e2dc-603e-498f-8d62-339725f0603f)
     )
-    (fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer "F.SilkS") (width 0.12) (tstamp 33d1fa0e-96de-4bd9-8bed-eb3d75d0d7d8))
-    (fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer "F.SilkS") (width 0.12) (tstamp 39156b1c-bf91-438d-afb8-2007458c0b8e))
-    (fp_line (start 1.4 0.7) (end -1.4 0.7) (layer "F.CrtYd") (width 0.05) (tstamp 69ea0263-5b5c-4ce0-8820-f9c214b9e26e))
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-    (pad "1" smd roundrect locked (at -0.75 0 270) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (fp_line (start -0.162779 -0.51) (end 0.162779 -0.51)
+      (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 33d1fa0e-96de-4bd9-8bed-eb3d75d0d7d8))
+    (fp_line (start -0.162779 0.51) (end 0.162779 0.51)
+      (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 39156b1c-bf91-438d-afb8-2007458c0b8e))
+    (fp_line (start -1.4 -0.7) (end 1.4 -0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp a82cc152-d30e-40b2-9e4e-82bb1a5767f8))
+    (fp_line (start -1.4 0.7) (end -1.4 -0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp ecd17538-5422-4aa3-9951-3654d3d4054e))
+    (fp_line (start 1.4 -0.7) (end 1.4 0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp df26e74b-d3e8-42be-a468-53fe16f8ab6b))
+    (fp_line (start 1.4 0.7) (end -1.4 0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 69ea0263-5b5c-4ce0-8820-f9c214b9e26e))
+    (fp_line (start -0.8 -0.4) (end 0.8 -0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp d00fd3c4-c025-4e55-a99a-45a0290a21ff))
+    (fp_line (start -0.8 0.4) (end -0.8 -0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 63f5f9dd-ae0b-4073-8990-df8e590bc1fa))
+    (fp_line (start 0.8 -0.4) (end 0.8 0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp aaaa32a0-360f-4462-b895-9b01f1f86048))
+    (fp_line (start 0.8 0.4) (end -0.8 0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp a9ab4c03-304d-42e9-832e-c69cff939dec))
+    (pad "1" smd roundrect (at -0.75 0 270) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 72 "+3V3") (pintype "passive") (tstamp e302535d-6503-4dfd-b65e-6c8293a3f335))
-    (pad "2" smd roundrect locked (at 0.75 0 270) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "2" smd roundrect (at 0.75 0 270) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pintype "passive") (tstamp 496facad-c51d-4258-aa3e-af4dd0955a5f))
     (model "${KICAD6_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_0603_1608Metric.wrl"
       (offset (xyz 0 0 0))
@@ -1279,7 +1461,7 @@
   )
 
   (footprint "stdpads:C_0603" (layer "F.Cu")
-    (tedit 5EE29C36) (tstamp 00000000-0000-0000-0000-00005f4b2635)
+    (tstamp 00000000-0000-0000-0000-00005f4b2635)
     (at 126.45 112.6 -90)
     (tags "capacitor")
     (property "LCSC Part" "C23630")
@@ -1290,30 +1472,40 @@
     (solder_paste_margin -0.04)
     (attr smd)
     (fp_text reference "C29" (at 0 0 90) (layer "F.Fab")
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
       (tstamp a90e599f-c2fb-475b-92c6-fbc7b041f04b)
     )
     (fp_text value "2u2" (at 0 0.25 90) (layer "F.Fab")
-      (effects (font (size 0.127 0.127) (thickness 0.03175)))
+        (effects (font (size 0.127 0.127) (thickness 0.03175)))
       (tstamp 49339521-16b8-463d-be4d-2afce06e238b)
     )
     (fp_text user "${REFERENCE}" (at 0 0 90) (layer "F.SilkS") hide
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
       (tstamp 3ef4ab53-e075-473a-a75f-e14427f3de70)
     )
-    (fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer "F.SilkS") (width 0.12) (tstamp 2da13d6f-05be-455d-b411-4e9c5197856e))
-    (fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer "F.SilkS") (width 0.12) (tstamp c39ea287-ed92-42cf-a42f-0a058487a5d7))
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-    (pad "1" smd roundrect locked (at -0.75 0 270) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (fp_line (start -0.162779 -0.51) (end 0.162779 -0.51)
+      (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp c39ea287-ed92-42cf-a42f-0a058487a5d7))
+    (fp_line (start -0.162779 0.51) (end 0.162779 0.51)
+      (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 2da13d6f-05be-455d-b411-4e9c5197856e))
+    (fp_line (start -1.4 -0.7) (end 1.4 -0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 81b704e3-ad79-4155-bf9f-926a6d6c3a72))
+    (fp_line (start -1.4 0.7) (end -1.4 -0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp fc2e6937-75ad-4c5e-862d-3bdf44129aa7))
+    (fp_line (start 1.4 -0.7) (end 1.4 0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 2bd656cc-07a1-4b36-bd3d-1849c60a6f25))
+    (fp_line (start 1.4 0.7) (end -1.4 0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 8f87def2-8b5f-4cdc-b76b-7f23b04c3f1e))
+    (fp_line (start -0.8 -0.4) (end 0.8 -0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 1b9e0624-2feb-4d8b-9181-d73925756ba3))
+    (fp_line (start -0.8 0.4) (end -0.8 -0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 4ab5e19c-47cf-42ae-9678-1e36abeeae59))
+    (fp_line (start 0.8 -0.4) (end 0.8 0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 1de85031-9810-4511-a8e5-8fc28f5bb9bb))
+    (fp_line (start 0.8 0.4) (end -0.8 0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 78e288f6-3219-43f5-b222-0b33e0a0eac8))
+    (pad "1" smd roundrect (at -0.75 0 270) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 72 "+3V3") (pintype "passive") (tstamp fc3cefba-b5a8-4781-91cd-bb2492cf8ab6))
-    (pad "2" smd roundrect locked (at 0.75 0 270) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "2" smd roundrect (at 0.75 0 270) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pintype "passive") (tstamp 4216af48-181c-4ad6-9c60-e90f53b26cc9))
     (model "${KICAD6_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_0603_1608Metric.wrl"
       (offset (xyz 0 0 0))
@@ -1323,7 +1515,7 @@
   )
 
   (footprint "stdpads:C_0603" (layer "F.Cu")
-    (tedit 5EE29C36) (tstamp 00000000-0000-0000-0000-00005f4b2645)
+    (tstamp 00000000-0000-0000-0000-00005f4b2645)
     (at 126.45 107.8 -90)
     (tags "capacitor")
     (property "LCSC Part" "C23630")
@@ -1334,30 +1526,40 @@
     (solder_paste_margin -0.04)
     (attr smd)
     (fp_text reference "C30" (at 0 0 90) (layer "F.Fab")
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
       (tstamp 62629d86-7812-48e5-a4ee-cba4cce675c7)
     )
     (fp_text value "2u2" (at 0 0.25 90) (layer "F.Fab")
-      (effects (font (size 0.127 0.127) (thickness 0.03175)))
+        (effects (font (size 0.127 0.127) (thickness 0.03175)))
       (tstamp 20383790-76be-4aaa-94de-c17756682b7b)
     )
     (fp_text user "${REFERENCE}" (at 0 0 90) (layer "F.SilkS") hide
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
       (tstamp 27efb570-bb39-4d73-adb9-f0d14b77f4de)
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       (net 89 "/SD2") (pinfunction "DQ2") (pintype "bidirectional") (tstamp bed53e4e-1d66-4231-aa03-48383d000db6))
-    (pad "6" smd roundrect locked (at -6.4 5.75 180) (size 1.51 0.458) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
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       (net 2 "GND") (pinfunction "VSSQ") (pintype "power_in") (tstamp 340a3c97-4720-46c0-af55-cba214657808))
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       (net 88 "/SD3") (pinfunction "DQ3") (pintype "bidirectional") (tstamp 48db5cc7-6a04-41b6-8cd9-2f0e9a53c028))
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       (net 93 "/SD4") (pinfunction "DQ4") (pintype "bidirectional") (tstamp cf5aade5-95a9-4391-a214-46323ac86f00))
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       (net 72 "+3V3") (pinfunction "VDDQ") (pintype "power_in") (tstamp 16b539e2-6442-4fdd-94ea-e25262a3b780))
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       (net 92 "/SD5") (pinfunction "DQ5") (pintype "bidirectional") (tstamp ab3d7b3a-bd6a-44ad-8cdf-4873210aa41a))
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       (net 90 "/SD6") (pinfunction "DQ6") (pintype "bidirectional") (tstamp b17aea1f-56dd-4513-bc82-c4a6c326f278))
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       (net 2 "GND") (pinfunction "VSSQ") (pintype "power_in") (tstamp 710aa302-c08b-49a6-ae64-eb8d40cfc0b4))
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       (net 91 "/SD7") (pinfunction "DQ7") (pintype "bidirectional") (tstamp 1192a5e1-afd6-41f2-84dc-b2ce7a7ddf4e))
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       (net 72 "+3V3") (pinfunction "VDD") (pintype "power_in") (tstamp 29b46b10-4680-4031-8ebf-b247e083a871))
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       (net 94 "/SDQML") (pinfunction "DQML") (pintype "input") (tstamp bfadb7d7-c745-4ec8-852a-2d5bc4a10414))
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       (net 95 "/S~{WE}") (pinfunction "~{WE}") (pintype "input") (tstamp ff2cca04-7dcf-44e6-b570-048a1f9b5bb5))
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       (net 96 "/S~{CAS}") (pinfunction "~{CAS}") (pintype "input") (tstamp d7f4784a-38a5-47f1-bce1-82f15295dd02))
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       (net 97 "/S~{RAS}") (pinfunction "~{RAS}") (pintype "input") (tstamp b6245759-5959-413b-bba6-48e382636e72))
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       (net 98 "/S~{CS}") (pinfunction "~{CS}") (pintype "input") (tstamp bea3d93c-d179-4fe1-829f-51f109827be1))
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       (net 107 "/SBA0") (pinfunction "BA0") (pintype "input") (tstamp 52632697-1ea5-4741-8c22-5a4aacd71df2))
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       (net 109 "/SBA1") (pinfunction "BA1") (pintype "input") (tstamp 34f54799-d007-4803-95be-90acb9c9fde1))
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       (net 111 "/SA10") (pinfunction "A10") (pintype "input") (tstamp d6a8d6d1-aca0-4ad1-bf65-d90600eaf4be))
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       (net 99 "/SA0") (pinfunction "A0") (pintype "input") (tstamp 79048715-9f92-434f-b411-a3af8b441479))
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       (net 114 "/SA1") (pinfunction "A1") (pintype "input") (tstamp 16753c81-1a3b-47e2-8a5b-29fa84e3a60a))
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       (net 115 "/SA2") (pinfunction "A2") (pintype "input") (tstamp 6d62c5f8-5b9c-4fae-97e5-05b4d9f0a22d))
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       (net 125 "/DONE") (pinfunction "A3") (pintype "input") (tstamp f6248e18-9694-4940-9f52-e9013acaf5de))
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       (net 72 "+3V3") (pinfunction "VDD") (pintype "power_in") (tstamp 7086e12c-1a71-4c57-90ac-c49606d1553f))
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       (net 2 "GND") (pinfunction "VSS") (pintype "power_in") (tstamp 59dcb24e-d4ab-49d8-94a8-9510788c3cb1))
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       (net 100 "/SA4") (pinfunction "A4") (pintype "input") (tstamp eb0627ea-4705-4e2d-904f-1e06af050957))
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       (net 129 "/~{PROGRAM}") (pinfunction "A5") (pintype "input") (tstamp 22092cce-d385-4bb7-a697-ead1917d943f))
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       (net 101 "/SA6") (pinfunction "A6") (pintype "input") (tstamp 5685e99e-ba7e-4c8d-a3d8-8fe2d18b6a06))
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       (net 113 "/SA7") (pinfunction "A7") (pintype "input") (tstamp b82eac96-548e-4330-8147-4c032a9779e8))
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       (net 112 "/SA8") (pinfunction "A8") (pintype "input") (tstamp 6d88bdbe-c888-4646-8a33-0dccb85024be))
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       (net 110 "/SA9") (pinfunction "A9") (pintype "input") (tstamp 35096634-172a-4266-8e0e-bd8ec50b4814))
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       (net 92 "/SD5") (pinfunction "DQ10") (pintype "bidirectional") (tstamp b139b84f-c3af-4879-bcf4-dc1250c4be79))
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       (net 88 "/SD3") (pinfunction "DQ12") (pintype "bidirectional") (tstamp ee5398f2-011c-4cd0-a781-c87bc39f5028))
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-    (pad "51" smd roundrect locked (at -8 -5.75 180) (size 1.51 0.458) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "51" smd roundrect (at -8 -5.75 180) (size 1.51 0.458) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 87 "/SD1") (pinfunction "DQ14") (pintype "bidirectional") (tstamp d0bc009c-d82a-462e-93a3-53eae1df5f45))
-    (pad "52" smd roundrect locked (at -8.8 -5.75 180) (size 1.51 0.458) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "52" smd roundrect (at -8.8 -5.75 180) (size 1.51 0.458) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pinfunction "VSSQ") (pintype "power_in") (tstamp 883fdba5-f647-446e-8db4-99b5492ced0c))
-    (pad "53" smd roundrect locked (at -9.6 -5.75 180) (size 1.51 0.458) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "53" smd roundrect (at -9.6 -5.75 180) (size 1.51 0.458) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 86 "/SD0") (pinfunction "DQ15") (pintype "bidirectional") (tstamp 402e213f-c311-46e7-be4a-e0ac37124efc))
-    (pad "54" smd roundrect locked (at -10.4 -5.75 180) (size 1.51 0.458) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "54" smd roundrect (at -10.4 -5.75 180) (size 1.51 0.458) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pinfunction "VSS") (pintype "power_in") (tstamp ddeb7290-ccba-4429-869f-ccaeb1cc6577))
     (model "${KICAD6_3DMODEL_DIR}/Package_SO.3dshapes/TSOP-II-54_22.2x10.16mm_P0.8mm.wrl"
       (offset (xyz 0 0 0))
@@ -1565,7 +1793,7 @@
   )
 
   (footprint "stdpads:C_0603" (layer "F.Cu")
-    (tedit 5EE29C36) (tstamp 00000000-0000-0000-0000-00005f4b26cf)
+    (tstamp 00000000-0000-0000-0000-00005f4b26cf)
     (at 110.85 108.7 90)
     (tags "capacitor")
     (property "LCSC Part" "C23630")
@@ -1576,30 +1804,40 @@
     (solder_paste_margin -0.04)
     (attr smd)
     (fp_text reference "C34" (at 0 0 90) (layer "F.Fab")
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
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     )
     (fp_text value "2u2" (at 0 0.25 90) (layer "F.Fab")
-      (effects (font (size 0.127 0.127) (thickness 0.03175)))
+        (effects (font (size 0.127 0.127) (thickness 0.03175)))
       (tstamp 960654b4-29a3-4176-bd1f-b4393dae5e89)
     )
     (fp_text user "${REFERENCE}" (at 0 0 90) (layer "F.SilkS") hide
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
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+    (pad "1" smd roundrect (at -0.75 0 90) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
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-    (pad "2" smd roundrect locked (at 0.75 0 90) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "2" smd roundrect (at 0.75 0 90) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pintype "passive") (tstamp d65bfe3e-6a02-45b7-84f0-622ebafa1ff3))
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       (offset (xyz 0 0 0))
@@ -1609,7 +1847,7 @@
   )
 
   (footprint "stdpads:C_0603" (layer "F.Cu")
-    (tedit 5EE29C36) (tstamp 00000000-0000-0000-0000-00005f4dda3e)
+    (tstamp 00000000-0000-0000-0000-00005f4dda3e)
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     (tags "capacitor")
     (property "LCSC Part" "C23630")
@@ -1620,30 +1858,40 @@
     (solder_paste_margin -0.04)
     (attr smd)
     (fp_text reference "C33" (at 0 0 90) (layer "F.Fab")
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
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     )
     (fp_text value "2u2" (at 0 0.25 90) (layer "F.Fab")
-      (effects (font (size 0.127 0.127) (thickness 0.03175)))
+        (effects (font (size 0.127 0.127) (thickness 0.03175)))
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     )
     (fp_text user "${REFERENCE}" (at 0 0 90) (layer "F.SilkS") hide
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
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       (net 72 "+3V3") (pintype "passive") (tstamp e69906cd-1084-40b8-bc4a-8f253ac53ca8))
-    (pad "2" smd roundrect locked (at 0.75 0 90) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "2" smd roundrect (at 0.75 0 90) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pintype "passive") (tstamp 8953531d-425e-47dc-806f-15428ad1c010))
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@@ -1653,7 +1901,7 @@
   )
 
   (footprint "stdpads:C_0603" (layer "F.Cu")
-    (tedit 5EE29C36) (tstamp 00000000-0000-0000-0000-00005f556ca1)
+    (tstamp 00000000-0000-0000-0000-00005f556ca1)
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     (tags "capacitor")
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@@ -1664,30 +1912,40 @@
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     (attr smd)
     (fp_text reference "C28" (at 0 0) (layer "F.Fab")
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
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     (fp_text user "${REFERENCE}" (at 0 0) (layer "F.SilkS") hide
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     (model "${KICAD6_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_0603_1608Metric.wrl"
       (offset (xyz 0 0 0))
@@ -1697,7 +1955,7 @@
   )
 
   (footprint "stdpads:TSSOP-20_4.4x6.5mm_P0.65mm" (layer "F.Cu")
-    (tedit 5F27C9F6) (tstamp 00000000-0000-0000-0000-00005f58ea10)
+    (tstamp 00000000-0000-0000-0000-00005f58ea10)
     (at 90.225 122)
     (descr "20-Lead Plastic Thin Shrink Small Outline (ST)-4.4 mm Body [TSSOP] (see Microchip Packaging Specification 00000049BS.pdf)")
     (tags "SSOP 0.65")
@@ -1709,67 +1967,78 @@
     (solder_paste_margin -0.04)
     (attr smd)
     (fp_text reference "U4" (at 0 0 180) (layer "F.Fab")
-      (effects (font (size 0.8128 0.8128) (thickness 0.2032)))
+        (effects (font (size 0.8128 0.8128) (thickness 0.2032)))
       (tstamp 6d5abaf9-386d-48e2-8d68-f12022156cfb)
     )
     (fp_text value "74AHC245PW" (at 0 1.016 180) (layer "F.Fab")
-      (effects (font (size 0.508 0.508) (thickness 0.127)))
+        (effects (font (size 0.508 0.508) (thickness 0.127)))
       (tstamp 7411876f-dfb5-438e-a6c1-81c5124fafb1)
     )
     (fp_text user "${REFERENCE}" (at 0 0) (layer "F.SilkS")
-      (effects (font (size 0.8128 0.8128) (thickness 0.2032)))
+        (effects (font (size 0.8128 0.8128) (thickness 0.2032)))
       (tstamp 0001fea5-902d-48c7-836e-fc3524aaf22c)
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+    (fp_line (start -3.45 3.75) (end -3.45 -2.225)
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-    (pad "2" smd roundrect locked (at -2.275 2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "2" smd roundrect (at -2.275 2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 13 "/A0") (pinfunction "A0") (pintype "bidirectional") (tstamp 70232c01-7fc0-4126-82cc-0623442915e7))
-    (pad "3" smd roundrect locked (at -1.625 2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "3" smd roundrect (at -1.625 2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 12 "/A1") (pinfunction "A1") (pintype "bidirectional") (tstamp 5047408e-8153-4ca8-8606-252773d7aac6))
-    (pad "4" smd roundrect locked (at -0.975 2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "4" smd roundrect (at -0.975 2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 11 "/A2") (pinfunction "A2") (pintype "bidirectional") (tstamp f1ea9629-0db9-4218-8ce7-dd9e9c262b5b))
-    (pad "5" smd roundrect locked (at -0.325 2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "5" smd roundrect (at -0.325 2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 10 "/A3") (pinfunction "A3") (pintype "bidirectional") (tstamp 7d663b6d-0b70-443a-86ee-8d4b801b2530))
-    (pad "6" smd roundrect locked (at 0.325 2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "6" smd roundrect (at 0.325 2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 3 "/A4") (pinfunction "A4") (pintype "bidirectional") (tstamp 47f9bd50-a0ed-49db-94fa-652b5541b992))
-    (pad "7" smd roundrect locked (at 0.975 2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "7" smd roundrect (at 0.975 2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 9 "/A5") (pinfunction "A5") (pintype "bidirectional") (tstamp 5d9c22fb-42c3-4167-a359-ed95935ae3c8))
-    (pad "8" smd roundrect locked (at 1.625 2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "8" smd roundrect (at 1.625 2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 8 "/A6") (pinfunction "A6") (pintype "bidirectional") (tstamp 74c3cb8b-3314-4879-ad3b-efe14ff14e90))
-    (pad "9" smd roundrect locked (at 2.275 2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "9" smd roundrect (at 2.275 2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 7 "/A7") (pinfunction "A7") (pintype "bidirectional") (tstamp 909c1db5-af41-4110-8cb0-78acc05d1061))
-    (pad "10" smd roundrect locked (at 2.925 2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "10" smd roundrect (at 2.925 2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pinfunction "GND") (pintype "power_in") (tstamp 8c09a0f7-3ec8-49f5-ad5b-5cda9e7460a8))
-    (pad "11" smd roundrect locked (at 2.925 -2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "11" smd roundrect (at 2.925 -2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 60 "/RA7") (pinfunction "B7") (pintype "bidirectional") (tstamp ae34ca85-3607-4b02-a720-7f76e8d7e328))
-    (pad "12" smd roundrect locked (at 2.275 -2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "12" smd roundrect (at 2.275 -2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 59 "/RA6") (pinfunction "B6") (pintype "bidirectional") (tstamp 972f569d-cd89-44b5-a8ee-30e99bf37dfa))
-    (pad "13" smd roundrect locked (at 1.625 -2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "13" smd roundrect (at 1.625 -2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 58 "/RA5") (pinfunction "B5") (pintype "bidirectional") (tstamp 43e183f8-eba8-46d8-a65c-a8d0be153c73))
-    (pad "14" smd roundrect locked (at 0.975 -2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "14" smd roundrect (at 0.975 -2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 57 "/RA4") (pinfunction "B4") (pintype "bidirectional") (tstamp eab7a0f6-bf18-4cd1-9e3d-ecc293d15364))
-    (pad "15" smd roundrect locked (at 0.325 -2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "15" smd roundrect (at 0.325 -2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 56 "/RA3") (pinfunction "B3") (pintype "bidirectional") (tstamp ce6bff41-358d-4602-85a1-56a4f5d110bc))
-    (pad "16" smd roundrect locked (at -0.325 -2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "16" smd roundrect (at -0.325 -2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 55 "/RA2") (pinfunction "B2") (pintype "bidirectional") (tstamp be2a08e0-4c4c-4f3d-89e7-66ba2148d9d7))
-    (pad "17" smd roundrect locked (at -0.975 -2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "17" smd roundrect (at -0.975 -2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 54 "/RA1") (pinfunction "B1") (pintype "bidirectional") (tstamp be1276b1-af91-44c1-849e-7bf34847b6a5))
-    (pad "18" smd roundrect locked (at -1.625 -2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "18" smd roundrect (at -1.625 -2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 53 "/RA0") (pinfunction "B0") (pintype "bidirectional") (tstamp 7dc39591-bc79-4a9b-95c0-417b27d600d5))
-    (pad "19" smd roundrect locked (at -2.275 -2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "19" smd roundrect (at -2.275 -2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pinfunction "~{OE}") (pintype "input") (tstamp fc1fd922-1399-4cf9-995f-3863006e8d86))
-    (pad "20" smd roundrect locked (at -2.925 -2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "20" smd roundrect (at -2.925 -2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 72 "+3V3") (pinfunction "Vcc") (pintype "power_in") (tstamp 51d88d34-e7c1-4ff4-9140-56d9a685a6a7))
     (model "${KICAD6_3DMODEL_DIR}/Package_SO.3dshapes/TSSOP-20_4.4x6.5mm_P0.65mm.wrl"
       (offset (xyz 0 0 0))
@@ -1779,7 +2048,7 @@
   )
 
   (footprint "stdpads:TSSOP-20_4.4x6.5mm_P0.65mm" (layer "F.Cu")
-    (tedit 5F27C9F6) (tstamp 00000000-0000-0000-0000-00005f5a468a)
+    (tstamp 00000000-0000-0000-0000-00005f5a468a)
     (at 81.025 122)
     (descr "20-Lead Plastic Thin Shrink Small Outline (ST)-4.4 mm Body [TSSOP] (see Microchip Packaging Specification 00000049BS.pdf)")
     (tags "SSOP 0.65")
@@ -1791,67 +2060,78 @@
     (solder_paste_margin -0.04)
     (attr smd)
     (fp_text reference "U6" (at 0 0 180) (layer "F.Fab")
-      (effects (font (size 0.8128 0.8128) (thickness 0.2032)))
+        (effects (font (size 0.8128 0.8128) (thickness 0.2032)))
       (tstamp 9ec68018-b9bf-46d4-abca-61860a1554fc)
     )
     (fp_text value "74AHC245PW" (at 0 1.016 180) (layer "F.Fab")
-      (effects (font (size 0.508 0.508) (thickness 0.127)))
+        (effects (font (size 0.508 0.508) (thickness 0.127)))
       (tstamp 368610a4-ce61-4176-ae06-b4809496ef34)
     )
     (fp_text user "${REFERENCE}" (at 0 0) (layer "F.SilkS")
-      (effects (font (size 0.8128 0.8128) (thickness 0.2032)))
+        (effects (font (size 0.8128 0.8128) (thickness 0.2032)))
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+    (fp_line (start -3.45 3.75) (end -3.45 -2.225)
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       (net 83 "/Ddir") (pinfunction "AtoB") (pintype "input") (tstamp 848b9538-2d58-4033-a17d-c5449fb2184a))
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+    (pad "2" smd roundrect (at -2.275 2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
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+    (pad "3" smd roundrect (at -1.625 2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
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+    (pad "4" smd roundrect (at -0.975 2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
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-    (pad "5" smd roundrect locked (at -0.325 2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "5" smd roundrect (at -0.325 2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
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+    (pad "6" smd roundrect (at 0.325 2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
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-    (pad "7" smd roundrect locked (at 0.975 2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "7" smd roundrect (at 0.975 2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
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-    (pad "8" smd roundrect locked (at 1.625 2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "8" smd roundrect (at 1.625 2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
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+    (pad "9" smd roundrect (at 2.275 2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 4 "/D7") (pinfunction "A7") (pintype "bidirectional") (tstamp 31eef6d1-6ebe-404f-bd71-c39600a26bf8))
-    (pad "10" smd roundrect locked (at 2.925 2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "10" smd roundrect (at 2.925 2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pinfunction "GND") (pintype "power_in") (tstamp f44755e3-5528-40e7-b654-c7ee94b81b7b))
-    (pad "11" smd roundrect locked (at 2.925 -2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "11" smd roundrect (at 2.925 -2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
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-    (pad "12" smd roundrect locked (at 2.275 -2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "12" smd roundrect (at 2.275 -2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 69 "/RD6") (pinfunction "B6") (pintype "bidirectional") (tstamp 0ed54a9f-cef2-4aad-aa09-bf9da4b2b979))
-    (pad "13" smd roundrect locked (at 1.625 -2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "13" smd roundrect (at 1.625 -2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 68 "/RD5") (pinfunction "B5") (pintype "bidirectional") (tstamp ac5e020e-ce9e-470e-9c13-077e1d3a37a1))
-    (pad "14" smd roundrect locked (at 0.975 -2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "14" smd roundrect (at 0.975 -2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 67 "/RD4") (pinfunction "B4") (pintype "bidirectional") (tstamp 6d4e8352-b3b3-4e7f-9252-867f20e93f0a))
-    (pad "15" smd roundrect locked (at 0.325 -2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "15" smd roundrect (at 0.325 -2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 66 "/RD3") (pinfunction "B3") (pintype "bidirectional") (tstamp 6a0e9fc4-907e-4e68-949e-61a95824c68c))
-    (pad "16" smd roundrect locked (at -0.325 -2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "16" smd roundrect (at -0.325 -2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 128 "/~{JTAGEN}") (pinfunction "B2") (pintype "bidirectional") (tstamp 1c9f6949-579f-4f7a-8636-af665cf2edf8))
-    (pad "17" smd roundrect locked (at -0.975 -2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "17" smd roundrect (at -0.975 -2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 65 "/RD1") (pinfunction "B1") (pintype "bidirectional") (tstamp 07dda897-b3e5-48e9-9d64-5128b51da11a))
-    (pad "18" smd roundrect locked (at -1.625 -2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "18" smd roundrect (at -1.625 -2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 64 "/RD0") (pinfunction "B0") (pintype "bidirectional") (tstamp e59a45f7-0f09-4246-896d-98146d3ce6bd))
-    (pad "19" smd roundrect locked (at -2.275 -2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "19" smd roundrect (at -2.275 -2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pinfunction "~{OE}") (pintype "input") (tstamp c8ebcf56-ab51-4286-a3b5-56505a1e9990))
-    (pad "20" smd roundrect locked (at -2.925 -2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "20" smd roundrect (at -2.925 -2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 72 "+3V3") (pinfunction "Vcc") (pintype "power_in") (tstamp 75b9c91b-0604-4669-a4db-6d5324694214))
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       (offset (xyz 0 0 0))
@@ -1861,7 +2141,7 @@
   )
 
   (footprint "stdpads:C_0603" (layer "F.Cu")
-    (tedit 5EE29C36) (tstamp 00000000-0000-0000-0000-00005f656d46)
+    (tstamp 00000000-0000-0000-0000-00005f656d46)
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     (tags "capacitor")
     (property "LCSC Part" "C23630")
@@ -1872,30 +2152,40 @@
     (solder_paste_margin -0.04)
     (attr smd)
     (fp_text reference "C16" (at 0 0 90) (layer "F.Fab")
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
       (tstamp 0013ae5a-6b13-491b-83e1-6fe165e71981)
     )
     (fp_text value "2u2" (at 0 0.25 90) (layer "F.Fab")
-      (effects (font (size 0.127 0.127) (thickness 0.03175)))
+        (effects (font (size 0.127 0.127) (thickness 0.03175)))
       (tstamp 56e249b0-5f8f-4e93-8344-b755160032fa)
     )
     (fp_text user "${REFERENCE}" (at 0 0 90) (layer "F.SilkS") hide
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
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-    (pad "2" smd roundrect locked (at 0.75 0 270) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "2" smd roundrect (at 0.75 0 270) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pintype "passive") (tstamp 2db8df86-1062-446b-9531-cb2985ffef06))
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@@ -1905,7 +2195,7 @@
   )
 
   (footprint "stdpads:C_0603" (layer "F.Cu")
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+    (tstamp 00000000-0000-0000-0000-00005f6ddbd1)
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     (tags "capacitor")
     (property "LCSC Part" "C23630")
@@ -1916,30 +2206,40 @@
     (solder_paste_margin -0.04)
     (attr smd)
     (fp_text reference "C32" (at 0 0 90) (layer "F.Fab")
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
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     )
     (fp_text value "2u2" (at 0 0.25 90) (layer "F.Fab")
-      (effects (font (size 0.127 0.127) (thickness 0.03175)))
+        (effects (font (size 0.127 0.127) (thickness 0.03175)))
       (tstamp 69ce9cff-8751-44e9-b0dc-cc3015cf7444)
     )
     (fp_text user "${REFERENCE}" (at 0 0 90) (layer "F.SilkS") hide
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
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+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 8e99b9b4-928e-4520-97fe-abf10b937ad8))
+    (fp_line (start -0.8 -0.4) (end 0.8 -0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp c4cbdec2-7bd4-4cee-8ad0-c4c5f2090f87))
+    (fp_line (start -0.8 0.4) (end -0.8 -0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 0b2cbb30-f928-4117-8c4e-9fa271851416))
+    (fp_line (start 0.8 -0.4) (end 0.8 0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 1081cebc-8caa-46c9-b438-2af5f67fb199))
+    (fp_line (start 0.8 0.4) (end -0.8 0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 811f2797-0046-4316-9b63-b2432002f9d6))
+    (pad "1" smd roundrect (at -0.75 0 270) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 72 "+3V3") (pintype "passive") (tstamp 337197bd-62e7-4a8d-b19c-f1fcdf6c5ad3))
-    (pad "2" smd roundrect locked (at 0.75 0 270) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "2" smd roundrect (at 0.75 0 270) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pintype "passive") (tstamp 059a050b-b794-4975-9d18-0f051a10004c))
     (model "${KICAD6_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_0603_1608Metric.wrl"
       (offset (xyz 0 0 0))
@@ -1949,7 +2249,7 @@
   )
 
   (footprint "stdpads:Fiducial" (layer "F.Cu")
-    (tedit 5F1BCA76) (tstamp 00000000-0000-0000-0000-00005f727df6)
+    (tstamp 00000000-0000-0000-0000-00005f727df6)
     (at 48.133 93.599 90)
     (descr "Circular Fiducial, 1mm bare copper top; 2mm keepout (Level A)")
     (tags "marker")
@@ -1958,24 +2258,25 @@
     (path "/00000000-0000-0000-0000-00005d321d2b")
     (attr smd)
     (fp_text reference "FID2" (at 0 -1.6 90) (layer "F.SilkS") hide
-      (effects (font (size 0.508 0.508) (thickness 0.127)))
+        (effects (font (size 0.508 0.508) (thickness 0.127)))
       (tstamp 0de344d2-7071-44b7-a74b-6ef02cc41e5b)
     )
     (fp_text value "Fiducial" (at 0 2 90) (layer "F.Fab") hide
-      (effects (font (size 0.508 0.508) (thickness 0.127)))
+        (effects (font (size 0.508 0.508) (thickness 0.127)))
       (tstamp d02c62c5-0acf-4b35-97a6-f1f3a880eb8b)
     )
     (fp_text user "${REFERENCE}" (at 0 0 90) (layer "F.Fab")
-      (effects (font (size 0.4 0.4) (thickness 0.06)))
+        (effects (font (size 0.4 0.4) (thickness 0.06)))
       (tstamp 1a6d2848-e78e-49fe-8978-e1890f07836f)
     )
-    (fp_circle (center 0 0) (end 1 0) (layer "F.Fab") (width 0.1) (fill none) (tstamp 17eac3a0-7059-46ed-95c3-c4a565b27154))
-    (pad "~" smd circle locked (at 0 0 90) (size 1 1) (layers "F.Cu" "F.Mask")
+    (fp_circle (center 0 0) (end 1 0)
+      (stroke (width 0.1) (type solid)) (fill none) (layer "F.Fab") (tstamp 17eac3a0-7059-46ed-95c3-c4a565b27154))
+    (pad "~" smd circle (at 0 0 90) (size 1 1) (layers "F.Cu" "F.Mask")
       (solder_mask_margin 0.5) (clearance 0.575) (tstamp 7fc10263-0123-4329-93ac-413dbb014f64))
   )
 
   (footprint "stdpads:Fiducial" (layer "F.Cu")
-    (tedit 5F1BCA76) (tstamp 00000000-0000-0000-0000-00005f727e0b)
+    (tstamp 00000000-0000-0000-0000-00005f727e0b)
     (at 58.801 82.931 90)
     (descr "Circular Fiducial, 1mm bare copper top; 2mm keepout (Level A)")
     (tags "marker")
@@ -1984,24 +2285,25 @@
     (path "/00000000-0000-0000-0000-00005d321da8")
     (attr smd)
     (fp_text reference "FID3" (at 0 -1.6 90) (layer "F.SilkS") hide
-      (effects (font (size 0.508 0.508) (thickness 0.127)))
+        (effects (font (size 0.508 0.508) (thickness 0.127)))
       (tstamp 1f651130-4b16-4a21-8d7d-9225aa15d5e4)
     )
     (fp_text value "Fiducial" (at 0 2 90) (layer "F.Fab") hide
-      (effects (font (size 0.508 0.508) (thickness 0.127)))
+        (effects (font (size 0.508 0.508) (thickness 0.127)))
       (tstamp b7180800-fed1-4ced-9ae9-5f0eaa5fc6f7)
     )
     (fp_text user "${REFERENCE}" (at 0 0 90) (layer "F.Fab")
-      (effects (font (size 0.4 0.4) (thickness 0.06)))
+        (effects (font (size 0.4 0.4) (thickness 0.06)))
       (tstamp 099473f1-6598-46ff-a50f-4c520832170d)
     )
-    (fp_circle (center 0 0) (end 1 0) (layer "F.Fab") (width 0.1) (fill none) (tstamp 7e7c7c11-3faf-4288-b54c-c1a96cdb53f0))
-    (pad "~" smd circle locked (at 0 0 90) (size 1 1) (layers "F.Cu" "F.Mask")
+    (fp_circle (center 0 0) (end 1 0)
+      (stroke (width 0.1) (type solid)) (fill none) (layer "F.Fab") (tstamp 7e7c7c11-3faf-4288-b54c-c1a96cdb53f0))
+    (pad "~" smd circle (at 0 0 90) (size 1 1) (layers "F.Cu" "F.Mask")
       (solder_mask_margin 0.5) (clearance 0.575) (tstamp 19b9118f-9963-408d-98ae-d8338e54c9f0))
   )
 
   (footprint "stdpads:Fiducial" (layer "F.Cu")
-    (tedit 5F1BCA76) (tstamp 00000000-0000-0000-0000-00005f727e20)
+    (tstamp 00000000-0000-0000-0000-00005f727e20)
     (at 48.133 129.54)
     (descr "Circular Fiducial, 1mm bare copper top; 2mm keepout (Level A)")
     (tags "marker")
@@ -2010,24 +2312,25 @@
     (path "/00000000-0000-0000-0000-00005f45d110")
     (attr smd)
     (fp_text reference "FID5" (at 0 -1.6) (layer "F.SilkS") hide
-      (effects (font (size 0.508 0.508) (thickness 0.127)))
+        (effects (font (size 0.508 0.508) (thickness 0.127)))
       (tstamp 56659a02-3d41-4a83-8024-d90208cbdd68)
     )
     (fp_text value "Fiducial" (at 0 2) (layer "F.Fab") hide
-      (effects (font (size 0.508 0.508) (thickness 0.127)))
+        (effects (font (size 0.508 0.508) (thickness 0.127)))
       (tstamp 282c2a00-c620-4c22-b231-af99b73d071e)
     )
     (fp_text user "${REFERENCE}" (at 0 0) (layer "F.Fab")
-      (effects (font (size 0.4 0.4) (thickness 0.06)))
+        (effects (font (size 0.4 0.4) (thickness 0.06)))
       (tstamp 6d2a06fb-0b1e-452a-ab38-11a5f45e1b32)
     )
-    (fp_circle (center 0 0) (end 1 0) (layer "F.Fab") (width 0.1) (fill none) (tstamp fd73bab2-fc71-4b2e-9d46-53bd4b06d591))
-    (pad "~" smd circle locked (at 0 0) (size 1 1) (layers "F.Cu" "F.Mask")
+    (fp_circle (center 0 0) (end 1 0)
+      (stroke (width 0.1) (type solid)) (fill none) (layer "F.Fab") (tstamp fd73bab2-fc71-4b2e-9d46-53bd4b06d591))
+    (pad "~" smd circle (at 0 0) (size 1 1) (layers "F.Cu" "F.Mask")
       (solder_mask_margin 0.5) (clearance 0.575) (tstamp 309a4843-d0f2-44f7-9e6c-5e7259031bd1))
   )
 
   (footprint "stdpads:PasteHole_1.152mm_NPTH" (layer "F.Cu")
-    (tedit 5F27B084) (tstamp 00000000-0000-0000-0000-00005f72b32b)
+    (tstamp 00000000-0000-0000-0000-00005f72b32b)
     (at 48.133 96.139 90)
     (descr "Circular Fiducial, 1mm bare copper top; 2mm keepout (Level A)")
     (tags "marker")
@@ -2036,20 +2339,21 @@
     (path "/00000000-0000-0000-0000-00005f45d123")
     (attr exclude_from_pos_files)
     (fp_text reference "H3" (at 0 0 90) (layer "F.Fab")
-      (effects (font (size 0.4 0.4) (thickness 0.1)))
+        (effects (font (size 0.4 0.4) (thickness 0.1)))
       (tstamp 88e96532-f122-4aca-9226-fff5fca97e61)
     )
     (fp_text value " " (at 0 2 90) (layer "F.Fab") hide
-      (effects (font (size 0.508 0.508) (thickness 0.127)))
+        (effects (font (size 0.508 0.508) (thickness 0.127)))
       (tstamp 9e32ab2a-3d06-45ec-8679-6330988a7a82)
     )
-    (fp_circle (center 0 0) (end 1 0) (layer "F.Fab") (width 0.1) (fill none) (tstamp fcb23687-79e7-494b-b78d-610b9b788477))
-    (pad "" np_thru_hole circle locked (at 0 0 90) (size 1.152 1.152) (drill 1.152) (layers *.Cu *.Mask)
+    (fp_circle (center 0 0) (end 1 0)
+      (stroke (width 0.1) (type solid)) (fill none) (layer "F.Fab") (tstamp fcb23687-79e7-494b-b78d-610b9b788477))
+    (pad "" np_thru_hole circle (at 0 0 90) (size 1.152 1.152) (drill 1.152) (layers "*.Cu" "*.Mask")
       (solder_mask_margin 0.148) (tstamp 5755f436-0e3d-4d45-8c1a-0bdd2b442e0b))
   )
 
   (footprint "stdpads:PasteHole_1.152mm_NPTH" (layer "F.Cu")
-    (tedit 5F27B084) (tstamp 00000000-0000-0000-0000-00005f72b330)
+    (tstamp 00000000-0000-0000-0000-00005f72b330)
     (at 57.023 84.709 90)
     (descr "Circular Fiducial, 1mm bare copper top; 2mm keepout (Level A)")
     (tags "marker")
@@ -2058,20 +2362,21 @@
     (path "/00000000-0000-0000-0000-00005f45d0fd")
     (attr exclude_from_pos_files)
     (fp_text reference "H4" (at 0 0 90) (layer "F.Fab")
-      (effects (font (size 0.4 0.4) (thickness 0.1)))
+        (effects (font (size 0.4 0.4) (thickness 0.1)))
       (tstamp 57252f9a-43d2-40ac-ac6f-0a32208dd743)
     )
     (fp_text value " " (at 0 2 90) (layer "F.Fab") hide
-      (effects (font (size 0.508 0.508) (thickness 0.127)))
+        (effects (font (size 0.508 0.508) (thickness 0.127)))
       (tstamp cc35a772-bde8-4d78-a9ae-b0d5dc36a3f2)
     )
-    (fp_circle (center 0 0) (end 1 0) (layer "F.Fab") (width 0.1) (fill none) (tstamp dbb26299-96da-4f8e-80e9-62a513b64fd3))
-    (pad "" np_thru_hole circle locked (at 0 0 90) (size 1.152 1.152) (drill 1.152) (layers *.Cu *.Mask)
+    (fp_circle (center 0 0) (end 1 0)
+      (stroke (width 0.1) (type solid)) (fill none) (layer "F.Fab") (tstamp dbb26299-96da-4f8e-80e9-62a513b64fd3))
+    (pad "" np_thru_hole circle (at 0 0 90) (size 1.152 1.152) (drill 1.152) (layers "*.Cu" "*.Mask")
       (solder_mask_margin 0.148) (tstamp 94b43586-8936-44b2-a4c2-d7e2f3070afb))
   )
 
   (footprint "stdpads:PasteHole_1.152mm_NPTH" (layer "F.Cu")
-    (tedit 5F27B084) (tstamp 00000000-0000-0000-0000-00005f72b335)
+    (tstamp 00000000-0000-0000-0000-00005f72b335)
     (at 143.002 127)
     (descr "Circular Fiducial, 1mm bare copper top; 2mm keepout (Level A)")
     (tags "marker")
@@ -2080,20 +2385,21 @@
     (path "/00000000-0000-0000-0000-00005ff3d1f9")
     (attr exclude_from_pos_files)
     (fp_text reference "H6" (at 0 0) (layer "F.Fab")
-      (effects (font (size 0.4 0.4) (thickness 0.1)))
+        (effects (font (size 0.4 0.4) (thickness 0.1)))
       (tstamp 64c3b56e-9893-49f5-8367-6228bbe40788)
     )
     (fp_text value " " (at 0 2) (layer "F.Fab") hide
-      (effects (font (size 0.508 0.508) (thickness 0.127)))
+        (effects (font (size 0.508 0.508) (thickness 0.127)))
       (tstamp 83ae7dbf-fe84-437d-ab57-38fb182aa005)
     )
-    (fp_circle (center 0 0) (end 1 0) (layer "F.Fab") (width 0.1) (fill none) (tstamp 63ea53ac-05a8-4a46-9570-149e01f1cbc3))
-    (pad "" np_thru_hole circle locked (at 0 0) (size 1.152 1.152) (drill 1.152) (layers *.Cu *.Mask)
+    (fp_circle (center 0 0) (end 1 0)
+      (stroke (width 0.1) (type solid)) (fill none) (layer "F.Fab") (tstamp 63ea53ac-05a8-4a46-9570-149e01f1cbc3))
+    (pad "" np_thru_hole circle (at 0 0) (size 1.152 1.152) (drill 1.152) (layers "*.Cu" "*.Mask")
       (solder_mask_margin 0.148) (tstamp 68d56830-5948-491b-9668-8360717c16bd))
   )
 
   (footprint "stdpads:PasteHole_1.152mm_NPTH" (layer "F.Cu")
-    (tedit 5F27B084) (tstamp 00000000-0000-0000-0000-00005f72b33a)
+    (tstamp 00000000-0000-0000-0000-00005f72b33a)
     (at 48.133 127)
     (descr "Circular Fiducial, 1mm bare copper top; 2mm keepout (Level A)")
     (tags "marker")
@@ -2102,20 +2408,21 @@
     (path "/00000000-0000-0000-0000-00005f45d122")
     (attr exclude_from_pos_files)
     (fp_text reference "H2" (at 0 0) (layer "F.Fab")
-      (effects (font (size 0.4 0.4) (thickness 0.1)))
+        (effects (font (size 0.4 0.4) (thickness 0.1)))
       (tstamp c8ca09c4-3864-43ce-949c-ef7e8a8f9575)
     )
     (fp_text value " " (at 0 2) (layer "F.Fab") hide
-      (effects (font (size 0.508 0.508) (thickness 0.127)))
+        (effects (font (size 0.508 0.508) (thickness 0.127)))
       (tstamp d9c48155-d6b2-476b-99ba-ae1111eacf7d)
     )
-    (fp_circle (center 0 0) (end 1 0) (layer "F.Fab") (width 0.1) (fill none) (tstamp 172d6b03-a4be-4cff-ac34-9b84e4b169a9))
-    (pad "" np_thru_hole circle locked (at 0 0) (size 1.152 1.152) (drill 1.152) (layers *.Cu *.Mask)
+    (fp_circle (center 0 0) (end 1 0)
+      (stroke (width 0.1) (type solid)) (fill none) (layer "F.Fab") (tstamp 172d6b03-a4be-4cff-ac34-9b84e4b169a9))
+    (pad "" np_thru_hole circle (at 0 0) (size 1.152 1.152) (drill 1.152) (layers "*.Cu" "*.Mask")
       (solder_mask_margin 0.148) (tstamp b4281b35-de41-4fca-89f2-f4ae5132491f))
   )
 
   (footprint "stdpads:PasteHole_1.152mm_NPTH" (layer "F.Cu")
-    (tedit 5F27B084) (tstamp 00000000-0000-0000-0000-00005f77370a)
+    (tstamp 00000000-0000-0000-0000-00005f77370a)
     (at 140.462 82.423 -90)
     (descr "Circular Fiducial, 1mm bare copper top; 2mm keepout (Level A)")
     (tags "marker")
@@ -2124,20 +2431,21 @@
     (path "/00000000-0000-0000-0000-00005f45d0fe")
     (attr exclude_from_pos_files)
     (fp_text reference "H5" (at 0 0 90) (layer "F.Fab")
-      (effects (font (size 0.4 0.4) (thickness 0.1)))
+        (effects (font (size 0.4 0.4) (thickness 0.1)))
       (tstamp a897a025-cdd4-40ed-9dc0-1f46fe662301)
     )
     (fp_text value " " (at 0 2 90) (layer "F.Fab") hide
-      (effects (font (size 0.508 0.508) (thickness 0.127)))
+        (effects (font (size 0.508 0.508) (thickness 0.127)))
       (tstamp 776006be-d866-43cf-9116-5ed82bc41dd3)
     )
-    (fp_circle (center 0 0) (end 1 0) (layer "F.Fab") (width 0.1) (fill none) (tstamp 861f715d-bebd-4107-920a-f8f72fbe705d))
-    (pad "" np_thru_hole circle locked (at 0 0 270) (size 1.152 1.152) (drill 1.152) (layers *.Cu *.Mask)
+    (fp_circle (center 0 0) (end 1 0)
+      (stroke (width 0.1) (type solid)) (fill none) (layer "F.Fab") (tstamp 861f715d-bebd-4107-920a-f8f72fbe705d))
+    (pad "" np_thru_hole circle (at 0 0 270) (size 1.152 1.152) (drill 1.152) (layers "*.Cu" "*.Mask")
       (solder_mask_margin 0.148) (tstamp 5c40247e-5f02-469b-86e7-d7bb4f416cca))
   )
 
   (footprint "stdpads:TQFP-100_14x14mm_P0.5mm" (layer "F.Cu")
-    (tedit 608E5AA2) (tstamp 00000000-0000-0000-0000-00005f7bd125)
+    (tstamp 00000000-0000-0000-0000-00005f7bd125)
     (at 94.05 101.4 -90)
     (descr "TQFP, 100 Pin (http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=131095), generated with kicad-footprint-generator ipc_gullwing_generator.py")
     (tags "TQFP QFP")
@@ -2148,251 +2456,289 @@
     (solder_paste_margin -0.035)
     (attr smd)
     (fp_text reference "U1" (at 0 0) (layer "F.Fab")
-      (effects (font (size 0.8128 0.8128) (thickness 0.2032)))
+        (effects (font (size 0.8128 0.8128) (thickness 0.2032)))
       (tstamp 2bb03519-896f-4cf7-a0cc-f90e3fa5eb89)
     )
     (fp_text value "LCMXO2-640-TG100" (at 1.25 0) (layer "F.Fab")
-      (effects (font (size 0.8128 0.8128) (thickness 0.2032)))
+        (effects (font (size 0.8128 0.8128) (thickness 0.2032)))
       (tstamp b13a7fa4-c7eb-4f15-a166-656a06416050)
     )
     (fp_text user "${REFERENCE}" (at 0 0) (layer "F.SilkS")
-      (effects (font (size 0.8128 0.8128) (thickness 0.2032)))
+        (effects (font (size 0.8128 0.8128) (thickness 0.2032)))
       (tstamp 8067e148-74fb-48f7-89c2-0c30d67886a4)
     )
-    (fp_line (start 7.11 6.41) (end 7.11 7.11) (layer "F.SilkS") (width 0.12) (tstamp 1e583e6b-ac3d-4fbd-a79c-9a027d85f978))
-    (fp_line (start -7.11 6.41) (end -7.11 7.11) (layer "F.SilkS") (width 0.12) (tstamp 3df49ca4-3fdf-42f9-8eae-baf8f360bfb9))
-    (fp_line (start -7.11 -6.41) (end -7.11 -7.11) (layer "F.SilkS") (width 0.12) (tstamp 45693bd3-2758-4dc9-984c-ae0fb6900171))
-    (fp_line (start -7.11 -7.11) (end -6.41 -7.11) (layer "F.SilkS") (width 0.12) (tstamp 4717f17f-41cf-4c5a-92ed-5ad542321215))
-    (fp_line (start -6.41 7.11) (end -6.41 8.4) (layer "F.SilkS") (width 0.12) (tstamp 4e694cae-33a1-4fea-91aa-8afce5008a39))
-    (fp_line (start 7.11 7.11) (end 6.41 7.11) (layer "F.SilkS") (width 0.12) (tstamp 53a5ce38-b209-45ef-b9df-efa5f5858712))
-    (fp_line (start -7.11 7.11) (end -6.41 7.11) (layer "F.SilkS") (width 0.12) (tstamp 6fcbd4b1-8d51-4cf7-b6c3-b9b53cdb01bc))
-    (fp_line (start 7.11 -7.11) (end 6.41 -7.11) (layer "F.SilkS") (width 0.12) (tstamp 88c19d7e-539d-4c4e-8a1c-c36d32707ae8))
-    (fp_line (start 7.11 -6.41) (end 7.11 -7.11) (layer "F.SilkS") (width 0.12) (tstamp a9d5de95-f9fc-4bc9-8240-4dea9673b68c))
-    (fp_line (start -7.25 6.4) (end -7.25 7.25) (layer "F.CrtYd") (width 0.05) (tstamp 2002d5ce-0f2a-4ea6-8925-5f3839cb3fa0))
-    (fp_line (start 7.25 7.25) (end 6.4 7.25) (layer "F.CrtYd") (width 0.05) (tstamp 2a1aef59-5e7a-4662-aaed-0099dfa9fe8d))
-    (fp_line (start -8.65 -6.4) (end -7.25 -6.4) (layer "F.CrtYd") (width 0.05) (tstamp 33a38490-ecf5-4d95-a2fc-3fa9f18870e0))
-    (fp_line (start 8.65 -6.4) (end 7.25 -6.4) (layer "F.CrtYd") (width 0.05) (tstamp 3b63e46e-9a44-4741-a96e-c1c6dd8a6002))
-    (fp_line (start -6.4 -7.25) (end -6.4 -8.65) (layer "F.CrtYd") (width 0.05) (tstamp 4602f25e-67da-4174-86d6-bbb672ef7724))
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-    (pad "20" smd roundrect locked (at 3.5 7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "20" smd roundrect (at 3.5 7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 133 "/RINTin") (pinfunction "PL7A/PCLKT3_0") (pintype "bidirectional") (tstamp fc38854d-c25e-4702-a4ae-ae60743fb063))
-    (pad "21" smd roundrect locked (at 4 7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "21" smd roundrect (at 4 7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 132 "/RINTout") (pinfunction "PL7B/PCLKC3_0") (pintype "bidirectional") (tstamp e6306ac1-b37d-4dce-8052-6ffc57b26d60))
-    (pad "22" smd roundrect locked (at 4.5 7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "22" smd roundrect (at 4.5 7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pinfunction "GND") (pintype "power_in") (tstamp 49da9b1e-de7a-42e1-a530-b587f27f37b4))
-    (pad "23" smd roundrect locked (at 5 7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "23" smd roundrect (at 5 7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 72 "+3V3") (pinfunction "VccIO3") (pintype "power_in") (tstamp d2193c6b-a2a6-402a-ab00-07bd951f8c13))
-    (pad "24" smd roundrect locked (at 5.5 7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "24" smd roundrect (at 5.5 7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 120 "/RES~{OE}") (pinfunction "PL7C") (pintype "bidirectional") (tstamp d563df24-8aae-473c-90ab-d7558a128a7a))
-    (pad "25" smd roundrect locked (at 6 7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "25" smd roundrect (at 6 7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 78 "/RA11") (pinfunction "PL7D") (pintype "bidirectional") (tstamp a225b47c-53ff-49e6-b80b-c1fbd4c67b87))
-    (pad "26" smd roundrect locked (at 7.6625 6) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "26" smd roundrect (at 7.6625 6) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 72 "+3V3") (pinfunction "VccIO2") (pintype "power_in") (tstamp 272ae958-16ef-45f2-9f0d-0fae42f59449))
-    (pad "27" smd roundrect locked (at 7.6625 5.5) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "27" smd roundrect (at 7.6625 5.5) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 79 "/RA12") (pinfunction "PB4A/CSSPIN") (pintype "bidirectional") (tstamp 5f8366f2-fcb9-4ecb-864e-a2552057df23))
-    (pad "28" smd roundrect locked (at 7.6625 5) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "28" smd roundrect (at 7.6625 5) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 80 "/RA13") (pinfunction "PB4B") (pintype "bidirectional") (tstamp e5762204-9e07-48f8-b103-f84e0a819e65))
-    (pad "29" smd roundrect locked (at 7.6625 4.5) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "29" smd roundrect (at 7.6625 4.5) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 81 "/RA14") (pinfunction "PB4C") (pintype "bidirectional") (tstamp 6f468701-74ef-4f73-9cc6-989210aaccf7))
-    (pad "30" smd roundrect locked (at 7.6625 4) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "30" smd roundrect (at 7.6625 4) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 82 "/RA15") (pinfunction "PB4D") (pintype "bidirectional") (tstamp ab3538b4-1758-4218-abbe-e1209be38a1a))
-    (pad "31" smd roundrect locked (at 7.6625 3.5) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "31" smd roundrect (at 7.6625 3.5) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 77 "/R~{IOSEL}") (pinfunction "PB6A/MCLK/CCLK") (pintype "bidirectional") (tstamp 16f927ca-e2a8-4c78-abbe-c12caa86584b))
-    (pad "32" smd roundrect locked (at 7.6625 3) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "32" smd roundrect (at 7.6625 3) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 76 "/R~{DEVSEL}") (pinfunction "PB6B/SO/SPISO") (pintype "bidirectional") (tstamp 4f2b9d7a-4a36-4487-b0bc-898e14ecb261))
-    (pad "33" smd roundrect locked (at 7.6625 2.5) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "33" smd roundrect (at 7.6625 2.5) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pinfunction "GND") (pintype "power_in") (tstamp ea4b0aed-b78a-41f8-b3ee-24489d9d9e4b))
-    (pad "34" smd roundrect locked (at 7.6625 2) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "34" smd roundrect (at 7.6625 2) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 126 "/RPHI0") (pinfunction "PB6C/PCLKT2_0") (pintype "bidirectional") (tstamp 53cd6fe7-9fad-4ab1-896d-8bc104fb96e0))
-    (pad "35" smd roundrect locked (at 7.6625 1.5) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "35" smd roundrect (at 7.6625 1.5) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 75 "/R~{IOSTRB}") (pinfunction "PB6D/PCLKC_0") (pintype "bidirectional") (tstamp 0525c176-3a29-4644-b384-c37966d7948a))
-    (pad "36" smd roundrect locked (at 7.6625 1) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "36" smd roundrect (at 7.6625 1) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 104 "/RR~{W}in") (pinfunction "PB10A") (pintype "bidirectional") (tstamp b219425b-1e3c-402c-9212-80c64265626f))
-    (pad "37" smd roundrect locked (at 7.6625 0.5) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "37" smd roundrect (at 7.6625 0.5) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 74 "/R~{RES}") (pinfunction "PB10B") (pintype "bidirectional") (tstamp 2a8bb1ad-e963-4f2e-8fe0-9df9a81ea98d))
-    (pad "38" smd roundrect locked (at 7.6625 0) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "38" smd roundrect (at 7.6625 0) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 87 "/SD1") (pinfunction "PB10C/PCLKT2_1") (pintype "bidirectional") (tstamp 74a941b3-1107-4d21-99ef-ddeb9693344e))
-    (pad "39" smd roundrect locked (at 7.6625 -0.5) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "39" smd roundrect (at 7.6625 -0.5) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 86 "/SD0") (pinfunction "PB10D/PCLKC2_1") (pintype "bidirectional") (tstamp 0ecfe6bb-f211-42e4-a36a-d001895cf897))
-    (pad "40" smd roundrect locked (at 7.6625 -1) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "40" smd roundrect (at 7.6625 -1) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 93 "/SD4") (pinfunction "PB12A") (pintype "bidirectional") (tstamp e6200739-a290-4f1c-8a4b-c01b538e79f8))
-    (pad "41" smd roundrect locked (at 7.6625 -1.5) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "41" smd roundrect (at 7.6625 -1.5) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 92 "/SD5") (pinfunction "PB12B") (pintype "bidirectional") (tstamp 3efdd4a3-c021-476a-b9c0-c05b5f4b458f))
-    (pad "42" smd roundrect locked (at 7.6625 -2) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "42" smd roundrect (at 7.6625 -2) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 90 "/SD6") (pinfunction "PB12C") (pintype "bidirectional") (tstamp a3bc0f27-8e24-4634-804b-65255a364f99))
-    (pad "43" smd roundrect locked (at 7.6625 -2.5) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "43" smd roundrect (at 7.6625 -2.5) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 91 "/SD7") (pinfunction "PB12D") (pintype "bidirectional") (tstamp 4ee7021d-3d07-45a0-b963-059743232411))
-    (pad "44" smd roundrect locked (at 7.6625 -3) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "44" smd roundrect (at 7.6625 -3) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pinfunction "GND") (pintype "power_in") (tstamp 92c9ecf7-1875-44c0-9340-a240ef6e8a1e))
-    (pad "45" smd roundrect locked (at 7.6625 -3.5) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "45" smd roundrect (at 7.6625 -3.5) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 88 "/SD3") (pinfunction "PB14A") (pintype "bidirectional") (tstamp 769d4241-97a4-44a9-8a0c-d8a3727e03c0))
-    (pad "46" smd roundrect locked (at 7.6625 -4) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "46" smd roundrect (at 7.6625 -4) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 72 "+3V3") (pinfunction "VccIO2") (pintype "power_in") (tstamp 52b8e218-a7cd-4fb2-83e6-4518df4190d5))
-    (pad "47" smd roundrect locked (at 7.6625 -4.5) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "47" smd roundrect (at 7.6625 -4.5) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 89 "/SD2") (pinfunction "PB14") (pintype "bidirectional") (tstamp d0a4ad72-4127-47e8-92cd-43e6b934ba89))
-    (pad "48" smd roundrect locked (at 7.6625 -5) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "48" smd roundrect (at 7.6625 -5) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 57 "/RA4") (pinfunction "PB14C/SN") (pintype "bidirectional") (tstamp 473c1a0c-70e0-4d05-b902-bd616eb7360e))
-    (pad "49" smd roundrect locked (at 7.6625 -5.5) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "49" smd roundrect (at 7.6625 -5.5) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 103 "/SDQMH") (pinfunction "PB14D/SI/SISPI") (pintype "bidirectional") (tstamp 1cbc6c5d-7a35-45cb-ae88-dbb9f3f2a2b7))
-    (pad "50" smd roundrect locked (at 7.6625 -6) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "50" smd roundrect (at 7.6625 -6) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 72 "+3V3") (pinfunction "Vcc") (pintype "power_in") (tstamp b67b3f48-4975-4ee2-89be-c0f6b3d9ca2c))
-    (pad "51" smd roundrect locked (at 6 -7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "51" smd roundrect (at 6 -7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 95 "/S~{WE}") (pinfunction "PR7D") (pintype "bidirectional") (tstamp 68b94f1b-fbf3-49d2-af60-1ff7c3d86e32))
-    (pad "52" smd roundrect locked (at 5.5 -7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "52" smd roundrect (at 5.5 -7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 96 "/S~{CAS}") (pinfunction "PR7C") (pintype "bidirectional") (tstamp 9401c2ec-6cbf-417d-84b9-8770850dc7b2))
-    (pad "53" smd roundrect locked (at 5 -7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "53" smd roundrect (at 5 -7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 97 "/S~{RAS}") (pinfunction "PR7B") (pintype "bidirectional") (tstamp 8ad620c6-b718-4418-8fdb-1e8e4731b28c))
-    (pad "54" smd roundrect locked (at 4.5 -7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "54" smd roundrect (at 4.5 -7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 85 "/RCLK") (pinfunction "PR7A") (pintype "bidirectional") (tstamp 7c756541-de1f-4b68-ae54-a8375e0d71e3))
-    (pad "55" smd roundrect locked (at 4 -7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "55" smd roundrect (at 4 -7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 72 "+3V3") (pinfunction "VccIO1") (pintype "power_in") (tstamp 273bb3e6-4d50-47f7-8edd-3059b9c5cc06))
-    (pad "56" smd roundrect locked (at 3.5 -7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "56" smd roundrect (at 3.5 -7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pinfunction "GNDIO1") (pintype "power_in") (tstamp 46781ffc-36cb-47d3-bb4c-31d33adab846))
-    (pad "57" smd roundrect locked (at 3 -7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "57" smd roundrect (at 3 -7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 102 "/SCKE") (pinfunction "PR6D") (pintype "bidirectional") (tstamp 51c35612-239c-46f4-b749-f339b582bca5))
-    (pad "58" smd roundrect locked (at 2.5 -7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "58" smd roundrect (at 2.5 -7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 98 "/S~{CS}") (pinfunction "PR6C") (pintype "bidirectional") (tstamp 7b835f41-a4ae-413c-9aa8-0345d755cada))
-    (pad "59" smd roundrect locked (at 2 -7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "59" smd roundrect (at 2 -7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 106 "/SA12") (pinfunction "PR6B") (pintype "bidirectional") (tstamp 1046d054-95ff-4eb8-9dd7-fea69f45682b))
-    (pad "60" smd roundrect locked (at 1.5 -7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "60" smd roundrect (at 1.5 -7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 107 "/SBA0") (pinfunction "PR6A") (pintype "bidirectional") (tstamp e68a001f-cb70-45a5-adee-04178ad0205f))
-    (pad "61" smd roundrect locked (at 1 -7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25) (tstamp 829c96b5-8b78-410c-8c40-05e38adec259))
-    (pad "62" smd roundrect locked (at 0.5 -7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "61" smd roundrect (at 1 -7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25) (tstamp 829c96b5-8b78-410c-8c40-05e38adec259))
+    (pad "62" smd roundrect (at 0.5 -7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 108 "/SA11") (pinfunction "PCLKC1_0/PR5D") (pintype "bidirectional") (tstamp 4ebf32c3-aa7d-4215-af82-59b1f156be08))
-    (pad "63" smd roundrect locked (at 0 -7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "63" smd roundrect (at 0 -7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 109 "/SBA1") (pinfunction "PCLKT1_0/PR5C") (pintype "bidirectional") (tstamp 3365d16b-cf28-4d73-bdfb-7189c36cf5d1))
-    (pad "64" smd roundrect locked (at -0.5 -7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "64" smd roundrect (at -0.5 -7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 110 "/SA9") (pinfunction "PR5B") (pintype "bidirectional") (tstamp 6d5b22e2-3bd7-4461-b9c3-170ef4a0afd8))
-    (pad "65" smd roundrect locked (at -1 -7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "65" smd roundrect (at -1 -7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 111 "/SA10") (pinfunction "PR5A") (pintype "bidirectional") (tstamp be53af9c-99ef-40c6-b249-96cc827f8933))
-    (pad "66" smd roundrect locked (at -1.5 -7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "66" smd roundrect (at -1.5 -7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 112 "/SA8") (pinfunction "PR3D") (pintype "bidirectional") (tstamp 7fbb63eb-d109-4d3e-9c03-fc88e695b9e0))
-    (pad "67" smd roundrect locked (at -2 -7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "67" smd roundrect (at -2 -7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 99 "/SA0") (pinfunction "PR3C") (pintype "bidirectional") (tstamp 2bd49722-eefa-46a9-9d92-84f1a85602a5))
-    (pad "68" smd roundrect locked (at -2.5 -7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "68" smd roundrect (at -2.5 -7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 100 "/SA4") (pinfunction "PR3B") (pintype "bidirectional") (tstamp 2be39d4a-0288-46fc-88cd-e57defc6f3ed))
-    (pad "69" smd roundrect locked (at -3 -7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "69" smd roundrect (at -3 -7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 101 "/SA6") (pinfunction "PR3A") (pintype "bidirectional") (tstamp 8957093d-7411-4579-8d2a-4766341ebd21))
-    (pad "70" smd roundrect locked (at -3.5 -7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "70" smd roundrect (at -3.5 -7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 113 "/SA7") (pinfunction "PR2D") (pintype "bidirectional") (tstamp b84b8a72-eea4-4848-bbd3-d8807cc8dbd9))
-    (pad "71" smd roundrect locked (at -4 -7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "71" smd roundrect (at -4 -7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 114 "/SA1") (pinfunction "PR2C") (pintype "bidirectional") (tstamp d361048e-03e4-4300-b107-4773ab57864f))
-    (pad "72" smd roundrect locked (at -4.5 -7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "72" smd roundrect (at -4.5 -7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pinfunction "GNDIO1") (pintype "power_in") (tstamp 5c2fd002-181f-47cf-b659-f3e455c0bf84))
-    (pad "73" smd roundrect locked (at -5 -7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "73" smd roundrect (at -5 -7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 72 "+3V3") (pinfunction "VccIO1") (pintype "power_in") (tstamp 1d9de41e-8178-4029-a5ba-daa900f303d7))
-    (pad "74" smd roundrect locked (at -5.5 -7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "74" smd roundrect (at -5.5 -7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 115 "/SA2") (pinfunction "PR2B") (pintype "bidirectional") (tstamp dc7db200-720e-4148-851d-61f1c7f68e17))
-    (pad "75" smd roundrect locked (at -6 -7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "75" smd roundrect (at -6 -7.6625) (size 1.475 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 64 "/RD0") (pinfunction "PR2A") (pintype "bidirectional") (tstamp 833486ca-7736-4c68-9174-ad7ea336b67f))
-    (pad "76" smd roundrect locked (at -7.6625 -6) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "76" smd roundrect (at -7.6625 -6) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 125 "/DONE") (pinfunction "DONE/PT11D") (pintype "bidirectional") (tstamp 856b513e-c165-417e-bd42-284ab44e0e5f))
-    (pad "77" smd roundrect locked (at -7.6625 -5.5) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "77" smd roundrect (at -7.6625 -5.5) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 94 "/SDQML") (pinfunction "~{INIT}/PT11C") (pintype "bidirectional") (tstamp 140d75c1-82dd-4353-8ae7-cb57f1cbde4f))
-    (pad "78" smd roundrect locked (at -7.6625 -5) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "78" smd roundrect (at -7.6625 -5) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 65 "/RD1") (pinfunction "PT11A") (pintype "bidirectional") (tstamp 3e1e9c4f-a7a5-485c-bbb5-99a3cc68a8a5))
-    (pad "79" smd roundrect locked (at -7.6625 -4.5) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "79" smd roundrect (at -7.6625 -4.5) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pinfunction "GND") (pintype "power_in") (tstamp 2d24cf55-0868-45fd-af1c-f28785251f78))
-    (pad "80" smd roundrect locked (at -7.6625 -4) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "80" smd roundrect (at -7.6625 -4) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 72 "+3V3") (pinfunction "VccIO0") (pintype "power_in") (tstamp 5dae85e2-41a6-483c-aac6-9f2f6ef2b7fe))
-    (pad "81" smd roundrect locked (at -7.6625 -3.5) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "81" smd roundrect (at -7.6625 -3.5) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 129 "/~{PROGRAM}") (pinfunction "~{PROGRAM}/PT10D") (pintype "bidirectional") (tstamp b617f7de-403c-4ac9-8cc0-9cefaed0a266))
-    (pad "82" smd roundrect locked (at -7.6625 -3) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "82" smd roundrect (at -7.6625 -3) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 128 "/~{JTAGEN}") (pinfunction "~{JTAGEN}/PT10C") (pintype "bidirectional") (tstamp 713849ec-d40e-45dd-a95b-d9cc78aa5888))
-    (pad "83" smd roundrect locked (at -7.6625 -2.5) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "83" smd roundrect (at -7.6625 -2.5) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 66 "/RD3") (pinfunction "PT10B") (pintype "bidirectional") (tstamp 799bd4aa-da7a-42c0-928e-76e7f81147bc))
-    (pad "84" smd roundrect locked (at -7.6625 -2) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "84" smd roundrect (at -7.6625 -2) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 67 "/RD4") (pinfunction "PT10A") (pintype "bidirectional") (tstamp d4698f02-08ca-4079-af29-36ea0201e9ca))
-    (pad "85" smd roundrect locked (at -7.6625 -1.5) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "85" smd roundrect (at -7.6625 -1.5) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 68 "/RD5") (pinfunction "SDA/PCLKC0_0/PT9D") (pintype "bidirectional") (tstamp 18c75862-c5fb-4ab2-8303-dcda4de82b09))
-    (pad "86" smd roundrect locked (at -7.6625 -1) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "86" smd roundrect (at -7.6625 -1) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 69 "/RD6") (pinfunction "SCL/PCLKT0_0/PT9C") (pintype "bidirectional") (tstamp 642d20ae-c5e0-48bd-b938-e5d0e34ee32b))
-    (pad "87" smd roundrect locked (at -7.6625 -0.5) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "87" smd roundrect (at -7.6625 -0.5) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 130 "/FW1") (pinfunction "PT9B/PCLKC0_1") (pintype "bidirectional") (tstamp 0ca76e49-9082-464d-8784-09e77db774d2))
-    (pad "88" smd roundrect locked (at -7.6625 0) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "88" smd roundrect (at -7.6625 0) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 131 "/FW0") (pinfunction "PT9A/PCLKT0_1") (pintype "bidirectional") (tstamp c2a57e48-486b-4b03-9956-74f9371d1585))
-    (pad "89" smd roundrect locked (at -7.6625 0.5) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25) (tstamp e9733d40-65e7-4b6b-8dff-ac3db77a22f4))
-    (pad "90" smd roundrect locked (at -7.6625 1) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "89" smd roundrect (at -7.6625 0.5) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25) (tstamp e9733d40-65e7-4b6b-8dff-ac3db77a22f4))
+    (pad "90" smd roundrect (at -7.6625 1) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 48 "/TMS") (pinfunction "TMS/PT7D") (pintype "bidirectional") (tstamp fe99561b-aa95-4a36-97d7-9991ca2a84e3))
-    (pad "91" smd roundrect locked (at -7.6625 1.5) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "91" smd roundrect (at -7.6625 1.5) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 46 "/TCK") (pinfunction "TCK/PT7C") (pintype "bidirectional") (tstamp aa674e63-2fbf-422c-b96d-8d397615fb17))
-    (pad "92" smd roundrect locked (at -7.6625 2) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "92" smd roundrect (at -7.6625 2) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pinfunction "GND") (pintype "power_in") (tstamp c7f83622-d138-4711-a3a0-24a4f4d8a132))
-    (pad "93" smd roundrect locked (at -7.6625 2.5) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "93" smd roundrect (at -7.6625 2.5) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 72 "+3V3") (pinfunction "VccIO0") (pintype "power_in") (tstamp 3ad0079a-f5c2-4d19-8858-62b1390dcf68))
-    (pad "94" smd roundrect locked (at -7.6625 3) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "94" smd roundrect (at -7.6625 3) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 52 "/TDI") (pinfunction "TDI/PT7B") (pintype "bidirectional") (tstamp 7f7be97f-733f-436c-b4c0-c678dbfa2bd9))
-    (pad "95" smd roundrect locked (at -7.6625 3.5) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "95" smd roundrect (at -7.6625 3.5) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 47 "/TDO") (pinfunction "TDO/PT7A") (pintype "bidirectional") (tstamp a9856c1a-046a-4e52-ae6a-3b57ddd09541))
-    (pad "96" smd roundrect locked (at -7.6625 4) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "96" smd roundrect (at -7.6625 4) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 55 "/RA2") (pinfunction "PT6D") (pintype "bidirectional") (tstamp 9d053ddf-727f-4ac3-99a4-04f1659f5de2))
-    (pad "97" smd roundrect locked (at -7.6625 4.5) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "97" smd roundrect (at -7.6625 4.5) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 54 "/RA1") (pinfunction "PT6C") (pintype "bidirectional") (tstamp 9a7ba945-6285-4e95-bb92-a3c60c534114))
-    (pad "98" smd roundrect locked (at -7.6625 5) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "98" smd roundrect (at -7.6625 5) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 70 "/RD7") (pinfunction "PT6B") (pintype "bidirectional") (tstamp 3e9635fe-023d-471e-8e69-40099cf4f4ec))
-    (pad "99" smd roundrect locked (at -7.6625 5.5) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "99" smd roundrect (at -7.6625 5.5) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 53 "/RA0") (pinfunction "PT6A") (pintype "bidirectional") (tstamp 037e429e-1ced-441d-b81b-0a1fc8cbe772))
-    (pad "100" smd roundrect locked (at -7.6625 6) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "100" smd roundrect (at -7.6625 6) (size 0.3 1.475) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 72 "+3V3") (pinfunction "Vcc") (pintype "power_in") (tstamp 9b4a6d70-ed5f-4967-a99e-5336542e686a))
     (model "${KICAD6_3DMODEL_DIR}/Package_QFP.3dshapes/TQFP-100_14x14mm_P0.5mm.wrl"
       (offset (xyz 0 0 0))
@@ -2402,7 +2748,7 @@
   )
 
   (footprint "stdpads:SOT-23" (layer "F.Cu")
-    (tedit 5F29B98F) (tstamp 00000000-0000-0000-0000-00005f8af690)
+    (tstamp 00000000-0000-0000-0000-00005f8af690)
     (at 136.25 124.2 180)
     (tags "SOT-23")
     (property "LCSC Part" "C5446")
@@ -2413,31 +2759,44 @@
     (solder_paste_margin -0.05)
     (attr smd)
     (fp_text reference "U8" (at 0 0 270) (layer "F.Fab")
-      (effects (font (size 0.381 0.381) (thickness 0.09525)))
+        (effects (font (size 0.381 0.381) (thickness 0.09525)))
       (tstamp e64de5f4-ff91-40e3-952f-9e9eece738bc)
     )
     (fp_text value "XC6206P332MR" (at 0.45 0 270) (layer "F.Fab")
-      (effects (font (size 0.127 0.127) (thickness 0.03175)))
+        (effects (font (size 0.127 0.127) (thickness 0.03175)))
       (tstamp b78ef055-b30c-483d-b7e4-23728ac3c7b4)
     )
-    (fp_line (start -0.76 -1.58) (end -0.76 -0.65) (layer "F.SilkS") (width 0.12) (tstamp 4c1ebf08-4672-4223-bb4a-3ab36efa0501))
-    (fp_line (start -0.76 1.58) (end 1.4 1.58) (layer "F.SilkS") (width 0.12) (tstamp b4288231-cf5a-4699-8692-bd3c1e92915a))
-    (fp_line (start -0.76 1.58) (end -0.76 0.65) (layer "F.SilkS") (width 0.12) (tstamp c8b0e906-d6ec-41ce-9673-4bee50d56b94))
-    (fp_line (start -0.76 -1.58) (end 0.7 -1.58) (layer "F.SilkS") (width 0.12) (tstamp cbf837f3-d7f1-4de3-ae80-77587c27131c))
-    (fp_line (start 2 -1.8) (end 2 1.8) (layer "F.CrtYd") (width 0.05) (tstamp 357f3f38-571d-411b-870b-d2de90c010ea))
-    (fp_line (start -2 -1.8) (end 2 -1.8) (layer "F.CrtYd") (width 0.05) (tstamp 509b2109-41dc-4000-8ade-b3a088fe8826))
-    (fp_line (start -2 1.8) (end -2 -1.8) (layer "F.CrtYd") (width 0.05) (tstamp 55fe1573-a6d3-4ce8-a706-99c72cd955c5))
-    (fp_line (start 2 1.8) (end -2 1.8) (layer "F.CrtYd") (width 0.05) (tstamp 6d4a937c-f0ac-45a6-b2b0-6bf7d5647558))
-    (fp_line (start 0.15 1.52) (end -0.7 1.52) (layer "F.Fab") (width 0.1) (tstamp 244a9bff-fad0-4070-811a-ad148eff6f83))
-    (fp_line (start 0.7 0.95) (end 0.15 1.52) (layer "F.Fab") (width 0.1) (tstamp 2bb279c6-7858-44a2-80a7-8b26b3123813))
-    (fp_line (start -0.7 1.52) (end -0.7 -1.52) (layer "F.Fab") (width 0.1) (tstamp 2ce62814-1fd7-4b41-b5b1-ec2bd852795c))
-    (fp_line (start 0.7 -1.52) (end -0.7 -1.52) (layer "F.Fab") (width 0.1) (tstamp 4db07c9f-36cf-4174-abe2-5a7dd4ed0a2f))
-    (fp_line (start 0.7 0.95) (end 0.7 -1.5) (layer "F.Fab") (width 0.1) (tstamp ebf8eae1-a68c-49bc-b8dc-ee758be7a834))
-    (pad "1" smd roundrect locked (at 1.05 0.95) (size 1.35 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (fp_line (start -0.76 -1.58) (end -0.76 -0.65)
+      (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 4c1ebf08-4672-4223-bb4a-3ab36efa0501))
+    (fp_line (start -0.76 -1.58) (end 0.7 -1.58)
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+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 244a9bff-fad0-4070-811a-ad148eff6f83))
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+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 4db07c9f-36cf-4174-abe2-5a7dd4ed0a2f))
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+    (fp_line (start 0.7 0.95) (end 0.7 -1.5)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp ebf8eae1-a68c-49bc-b8dc-ee758be7a834))
+    (pad "1" smd roundrect (at 1.05 0.95) (size 1.35 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pinfunction "GND") (pintype "power_in") (tstamp ad4b1132-3a8b-45eb-a3a4-67e7dc4aa528))
-    (pad "2" smd roundrect locked (at 1.05 -0.95) (size 1.35 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "2" smd roundrect (at 1.05 -0.95) (size 1.35 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 72 "+3V3") (pinfunction "Vout") (pintype "power_out") (tstamp 0097d7da-4004-45ff-ac1d-29bb4ec84929))
-    (pad "3" smd roundrect locked (at -1.05 0) (size 1.35 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "3" smd roundrect (at -1.05 0) (size 1.35 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 1 "+5V") (pinfunction "Vin") (pintype "power_in") (tstamp 290dc87d-1a3b-48ed-8159-46573b5d460e))
     (model "${KICAD6_3DMODEL_DIR}/Package_TO_SOT_SMD.3dshapes/SOT-23.wrl"
       (offset (xyz 0 0 0))
@@ -2447,7 +2806,7 @@
   )
 
   (footprint "stdpads:C_0805" (layer "F.Cu")
-    (tedit 5F02840E) (tstamp 00000000-0000-0000-0000-00005f8af6c6)
+    (tstamp 00000000-0000-0000-0000-00005f8af6c6)
     (at 132.75 124.2 90)
     (tags "capacitor")
     (property "LCSC Part" "C15850")
@@ -2458,30 +2817,40 @@
     (solder_paste_margin -0.025)
     (attr smd)
     (fp_text reference "C10" (at 0 0 270) (layer "F.Fab")
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
       (tstamp 604b004a-8c68-43c6-b47f-3ab31e54b98a)
     )
     (fp_text value "10u" (at 0 0.35 90) (layer "F.Fab")
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
       (tstamp 47b449cf-f719-48ae-957b-b0535fe635bf)
     )
     (fp_text user "${REFERENCE}" (at 0 0 270) (layer "F.SilkS") hide
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
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+      (stroke (width 0.15) (type solid)) (layer "F.Fab") (tstamp 39dbfefa-cbfc-4e2a-b536-78ff7b7d84e1))
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+      (stroke (width 0.15) (type solid)) (layer "F.Fab") (tstamp 76300a2b-40e0-46b4-a77c-0e244bbf4d43))
+    (fp_line (start 1 0.625) (end -1 0.625)
+      (stroke (width 0.15) (type solid)) (layer "F.Fab") (tstamp 2fde3170-8a3c-4d9b-abce-2427992d84af))
+    (pad "1" smd roundrect (at -0.85 0 90) (size 1.05 1.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 72 "+3V3") (pintype "passive") (tstamp 56f4a1e6-5182-4e16-9a37-9794d14bce9e))
-    (pad "2" smd roundrect locked (at 0.85 0 90) (size 1.05 1.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "2" smd roundrect (at 0.85 0 90) (size 1.05 1.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pintype "passive") (tstamp 3a7fbff6-5f27-472a-bcc1-181e9c3ea75e))
     (model "${KICAD6_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_0805_2012Metric.wrl"
       (offset (xyz 0 0 0))
@@ -2491,7 +2860,7 @@
   )
 
   (footprint "stdpads:C_0603" (layer "F.Cu")
-    (tedit 5EE29C36) (tstamp 00000000-0000-0000-0000-00005f9ccfb5)
+    (tstamp 00000000-0000-0000-0000-00005f9ccfb5)
     (at 69 100.65 -90)
     (tags "capacitor")
     (property "LCSC Part" "C23630")
@@ -2502,30 +2871,40 @@
     (solder_paste_margin -0.04)
     (attr smd)
     (fp_text reference "C44" (at 0 0 90) (layer "F.Fab")
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
       (tstamp 70815813-8fc8-447e-a7bf-e7cd5af3ba62)
     )
     (fp_text value "2u2" (at 0 0.25 90) (layer "F.Fab")
-      (effects (font (size 0.127 0.127) (thickness 0.03175)))
+        (effects (font (size 0.127 0.127) (thickness 0.03175)))
       (tstamp db94d2ab-3e2f-40b0-86b3-f05bdf4acb1d)
     )
     (fp_text user "${REFERENCE}" (at 0 0 90) (layer "F.SilkS") hide
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
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+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 107af519-2566-427f-aa88-2a667ee55924))
+    (pad "1" smd roundrect (at -0.75 0 270) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 72 "+3V3") (pintype "passive") (tstamp 973bce1e-0f4c-42c6-b451-69e104eb3f79))
-    (pad "2" smd roundrect locked (at 0.75 0 270) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "2" smd roundrect (at 0.75 0 270) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pintype "passive") (tstamp 8a3d03e2-f2c7-455f-8484-ae69e20feae4))
     (model "${KICAD6_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_0603_1608Metric.wrl"
       (offset (xyz 0 0 0))
@@ -2535,7 +2914,7 @@
   )
 
   (footprint "stdpads:C_0603" (layer "F.Cu")
-    (tedit 5EE29C36) (tstamp 00000000-0000-0000-0000-00005f9fc3b5)
+    (tstamp 00000000-0000-0000-0000-00005f9fc3b5)
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     (tags "capacitor")
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@@ -2546,30 +2925,40 @@
     (solder_paste_margin -0.04)
     (attr smd)
     (fp_text reference "C18" (at 0 0 90) (layer "F.Fab")
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
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     (fp_text value "2u2" (at 0 0.25 90) (layer "F.Fab")
-      (effects (font (size 0.127 0.127) (thickness 0.03175)))
+        (effects (font (size 0.127 0.127) (thickness 0.03175)))
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     (fp_text user "${REFERENCE}" (at 0 0 90) (layer "F.SilkS") hide
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
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+    (fp_line (start -0.8 -0.4) (end 0.8 -0.4)
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+    (fp_line (start -0.8 0.4) (end -0.8 -0.4)
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+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 291dcb04-9602-44a1-ad42-4379a9874dc3))
+    (fp_line (start 0.8 0.4) (end -0.8 0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp bf8b41f1-4b0f-415f-9476-223afd16e22c))
+    (pad "1" smd roundrect (at -0.75 0 90) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 72 "+3V3") (pintype "passive") (tstamp a86f3b62-f619-483b-bccd-2e1837949b48))
-    (pad "2" smd roundrect locked (at 0.75 0 90) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "2" smd roundrect (at 0.75 0 90) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pintype "passive") (tstamp 1c21eeb8-ac17-45e5-ae4d-a94263a012cb))
     (model "${KICAD6_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_0603_1608Metric.wrl"
       (offset (xyz 0 0 0))
@@ -2579,7 +2968,7 @@
   )
 
   (footprint "Connector:Tag-Connect_TC2050-IDC-FP_2x05_P1.27mm_Vertical" (layer "F.Cu")
-    (tedit 5A29CEC3) (tstamp 00000000-0000-0000-0000-00005fe7592e)
+    (tstamp 00000000-0000-0000-0000-00005fe7592e)
     (at 63.881 119.253)
     (descr "Tag-Connect programming header; http://www.tag-connect.com/Materials/TC2050-IDC-430%20Datasheet.pdf")
     (tags "tag connect programming header pogo pins")
@@ -2588,39 +2977,58 @@
     (path "/00000000-0000-0000-0000-00005e4199b1")
     (attr exclude_from_pos_files)
     (fp_text reference "J2" (at -7.366 1.825) (layer "F.Fab")
-      (effects (font (size 0.8128 0.8128) (thickness 0.2032)))
+        (effects (font (size 0.8128 0.8128) (thickness 0.2032)))
       (tstamp 454a4ee0-f295-4a0f-a14a-a979862efa35)
     )
     (fp_text value "JTAG" (at -7.366 3.302) (layer "F.Fab")
-      (effects (font (size 0.8128 0.8128) (thickness 0.2032)))
+        (effects (font (size 0.8128 0.8128) (thickness 0.2032)))
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+    (pad "" np_thru_hole circle (at -3.81 0) (size 0.9906 0.9906) (drill 0.9906) (layers "*.Cu" "*.Mask") (tstamp 3175d492-723d-4038-8b05-68ce2a5b3b7f))
+    (pad "" np_thru_hole circle (at -3.81 2.54) (size 2.3749 2.3749) (drill 2.3749) (layers "*.Cu" "*.Mask") (tstamp 1d2d30db-b500-450a-b39e-6551efbcdc39))
+    (pad "" np_thru_hole circle (at 1.905 -2.54) (size 2.3749 2.3749) (drill 2.3749) (layers "*.Cu" "*.Mask") (tstamp 0d599925-1ab2-42f1-9d14-9aeda5b9e62a))
+    (pad "" np_thru_hole circle (at 1.905 2.54) (size 2.3749 2.3749) (drill 2.3749) (layers "*.Cu" "*.Mask") (tstamp 11fc5a14-1abb-4a8f-954a-c68371176626))
+    (pad "" np_thru_hole circle (at 3.81 -1.016) (size 0.9906 0.9906) (drill 0.9906) (layers "*.Cu" "*.Mask") (tstamp 4ec9364d-b723-45b7-bdba-20e0efd8d7a9))
+    (pad "" np_thru_hole circle (at 3.81 1.016) (size 0.9906 0.9906) (drill 0.9906) (layers "*.Cu" "*.Mask") (tstamp 03f9b782-a494-46cb-99cc-49a29443c36e))
     (pad "1" connect circle (at -2.54 0.635) (size 0.7874 0.7874) (layers "F.Cu" "F.Mask")
       (net 139 "/TCKr") (pinfunction "Pin_1") (pintype "passive") (tstamp 3a0a35db-9488-4ff9-949e-11c81b4f5b78))
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@@ -2644,7 +3052,7 @@
   )
 
   (footprint "stdpads:SOIC-8_5.3mm" (layer "F.Cu")
-    (tedit 5FDA6A09) (tstamp 00000000-0000-0000-0000-00005fea70ba)
+    (tstamp 00000000-0000-0000-0000-00005fea70ba)
     (at 79.121 100.711 180)
     (descr "8-Lead Plastic Small Outline (SM) - Medium, 5.28 mm Body [SOIC] (see Microchip Packaging Specification 00000049BS.pdf)")
     (tags "SOIC 1.27")
@@ -2656,48 +3064,64 @@
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     (attr smd)
     (fp_text reference "U3" (at 0 0 270) (layer "F.Fab")
-      (effects (font (size 0.8128 0.8128) (thickness 0.2032)))
+        (effects (font (size 0.8128 0.8128) (thickness 0.2032)))
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     )
     (fp_text value "W25Q128JVSIQ" (at 1.27 0 270) (layer "F.Fab")
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+        (effects (font (size 0.381 0.381) (thickness 0.09525)))
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     (fp_text user "${REFERENCE}" (at 0 0 270) (layer "F.SilkS")
-      (effects (font (size 0.8128 0.8128) (thickness 0.2032)))
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+      (stroke (width 0.15) (type solid)) (layer "F.Fab") (tstamp 1e1c7634-89d3-4b24-8518-9e1cecb7ae67))
+    (fp_line (start -2.65 1.65) (end -2.65 -2.65)
+      (stroke (width 0.15) (type solid)) (layer "F.Fab") (tstamp 9f2256e4-98e8-4a7c-acfc-3ba65cef95cf))
+    (fp_line (start -1.65 2.65) (end -2.65 1.65)
+      (stroke (width 0.15) (type solid)) (layer "F.Fab") (tstamp f4e3c329-5fff-48f4-a24e-60d0704c077f))
+    (fp_line (start 2.65 -2.65) (end 2.65 2.65)
+      (stroke (width 0.15) (type solid)) (layer "F.Fab") (tstamp ae7594cf-9dde-4afe-9715-f49ab7dc4b9f))
+    (fp_line (start 2.65 2.65) (end -1.65 2.65)
+      (stroke (width 0.15) (type solid)) (layer "F.Fab") (tstamp fe3ba7b8-81c3-4a5a-ae1e-f2f16daf28ce))
+    (pad "1" smd roundrect (at -1.905 3.65 270) (size 1.7 0.7) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 118 "/F~{CS}") (pinfunction "~{CS}") (pintype "input") (tstamp 3fa1556d-ab9f-4dbd-96b1-a5804892d512))
-    (pad "2" smd roundrect locked (at -0.635 3.65 270) (size 1.7 0.7) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "2" smd roundrect (at -0.635 3.65 270) (size 1.7 0.7) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 116 "/MISO") (pinfunction "DO/IO1") (pintype "bidirectional") (tstamp abc6e239-66ab-4918-a061-2e7afcd65035))
-    (pad "3" smd roundrect locked (at 0.635 3.65 270) (size 1.7 0.7) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "3" smd roundrect (at 0.635 3.65 270) (size 1.7 0.7) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 121 "/FD2") (pinfunction "~{WP}/IO2") (pintype "bidirectional") (tstamp bc419036-3013-4eea-94e8-b100b5edffa5))
-    (pad "4" smd roundrect locked (at 1.905 3.65 270) (size 1.7 0.7) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "4" smd roundrect (at 1.905 3.65 270) (size 1.7 0.7) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pinfunction "GND") (pintype "power_in") (tstamp 00b0c225-33b8-4a4d-99aa-80d038217568))
-    (pad "5" smd roundrect locked (at 1.905 -3.65 270) (size 1.7 0.7) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "5" smd roundrect (at 1.905 -3.65 270) (size 1.7 0.7) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 117 "/MOSI") (pinfunction "DI/IO0") (pintype "bidirectional") (tstamp 0121f8aa-cc67-46ce-ad73-af02da4c494d))
-    (pad "6" smd roundrect locked (at 0.635 -3.65 270) (size 1.7 0.7) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "6" smd roundrect (at 0.635 -3.65 270) (size 1.7 0.7) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 119 "/FCK") (pinfunction "CLK") (pintype "input") (tstamp d2b0df5e-da60-46f9-b0de-e69cc740866f))
-    (pad "7" smd roundrect locked (at -0.635 -3.65 270) (size 1.7 0.7) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "7" smd roundrect (at -0.635 -3.65 270) (size 1.7 0.7) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 122 "/FD3") (pinfunction "~{HLD}/IO3") (pintype "bidirectional") (tstamp 39a098e6-513b-420c-bea4-da8aa54a81fe))
-    (pad "8" smd roundrect locked (at -1.905 -3.65 270) (size 1.7 0.7) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "8" smd roundrect (at -1.905 -3.65 270) (size 1.7 0.7) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 72 "+3V3") (pinfunction "Vcc") (pintype "power_in") (tstamp d0654a02-fbf6-4913-9fce-8b01687a8a7e))
     (model "${KICAD6_3DMODEL_DIR}/Package_SO.3dshapes/SOIJ-8_5.3x5.3mm_P1.27mm.wrl"
       (offset (xyz 0 0 0))
@@ -2707,7 +3131,7 @@
   )
 
   (footprint "stdpads:R_0603" (layer "F.Cu")
-    (tedit 5EE29B72) (tstamp 00000000-0000-0000-0000-00005fee6b07)
+    (tstamp 00000000-0000-0000-0000-00005fee6b07)
     (at 70.55 112.1 180)
     (tags "resistor")
     (property "LCSC Part" "C31850")
@@ -2718,30 +3142,40 @@
     (solder_paste_margin -0.05)
     (attr smd)
     (fp_text reference "R29" (at 0 0) (layer "F.Fab")
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
       (tstamp c49325ca-6e5b-4c60-8939-7c88aab7173b)
     )
     (fp_text value "10k" (at 0 0.25) (layer "F.Fab")
-      (effects (font (size 0.127 0.127) (thickness 0.03175)))
+        (effects (font (size 0.127 0.127) (thickness 0.03175)))
       (tstamp 859869d4-902d-438e-92f5-1d82a8870e75)
     )
     (fp_text user "${REFERENCE}" (at 0 0) (layer "F.SilkS") hide
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
       (tstamp 7b041b23-e2dc-4e47-b657-da0dade0c839)
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-    (fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer "F.SilkS") (width 0.12) (tstamp a637d1dd-0cff-48f9-96f5-0ddfa0b83074))
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-    (fp_line (start 1.4 -0.7) (end 1.4 0.7) (layer "F.CrtYd") (width 0.05) (tstamp 1aa09def-c4b9-47ce-aaa8-8798f24f7f4a))
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-    (pad "1" smd roundrect locked (at -0.8 0 180) (size 0.7 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (fp_line (start -0.162779 -0.51) (end 0.162779 -0.51)
+      (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp d36372ad-7ff2-48fe-b98c-626930168fbb))
+    (fp_line (start -0.162779 0.51) (end 0.162779 0.51)
+      (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp a637d1dd-0cff-48f9-96f5-0ddfa0b83074))
+    (fp_line (start -1.4 -0.7) (end 1.4 -0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp dc1bc50b-558e-4cb6-94ac-66fcc09714e2))
+    (fp_line (start -1.4 0.7) (end -1.4 -0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 4e8d2ee4-895b-45d4-ab5d-ac123520bd37))
+    (fp_line (start 1.4 -0.7) (end 1.4 0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 1aa09def-c4b9-47ce-aaa8-8798f24f7f4a))
+    (fp_line (start 1.4 0.7) (end -1.4 0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp eeea16dd-f865-41dc-a96f-ca67425fc4b3))
+    (fp_line (start -0.8 -0.4) (end 0.8 -0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 66d28696-33c7-46d2-830a-d59fa45e0fa4))
+    (fp_line (start -0.8 0.4) (end -0.8 -0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 7ba15a9e-861b-430a-8032-a331bf9e28cb))
+    (fp_line (start 0.8 -0.4) (end 0.8 0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 545ac1fc-0ea7-461f-897f-9295ab6a428f))
+    (fp_line (start 0.8 0.4) (end -0.8 0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp e31de6b5-cb39-4a03-86a6-edc251e9d263))
+    (pad "1" smd roundrect (at -0.8 0 180) (size 0.7 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 46 "/TCK") (pintype "passive") (tstamp 9015c223-c09c-4d00-bdaf-e24ac5b061cb))
-    (pad "2" smd roundrect locked (at 0.8 0 180) (size 0.7 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "2" smd roundrect (at 0.8 0 180) (size 0.7 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pintype "passive") (tstamp 3eec278b-3741-4d98-ba31-0735d26f5e5a))
     (model "${KICAD6_3DMODEL_DIR}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl"
       (offset (xyz 0 0 0))
@@ -2751,7 +3185,7 @@
   )
 
   (footprint "stdpads:R_0603" (layer "F.Cu")
-    (tedit 5EE29B72) (tstamp 00000000-0000-0000-0000-00005ffa9fc0)
+    (tstamp 00000000-0000-0000-0000-00005ffa9fc0)
     (at 70.55 110.65)
     (tags "resistor")
     (property "LCSC Part" "C31850")
@@ -2762,30 +3196,40 @@
     (solder_paste_margin -0.05)
     (attr smd)
     (fp_text reference "R28" (at 0 0) (layer "F.Fab")
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
       (tstamp a702021a-75fa-4937-8e74-1d70aae395cf)
     )
     (fp_text value "10k" (at 0 0.25) (layer "F.Fab")
-      (effects (font (size 0.127 0.127) (thickness 0.03175)))
+        (effects (font (size 0.127 0.127) (thickness 0.03175)))
       (tstamp c1d9b722-2d95-4429-8bc1-423997dfbf46)
     )
     (fp_text user "${REFERENCE}" (at 0 0) (layer "F.SilkS") hide
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
       (tstamp 59b4f748-5947-453e-b4c9-9178c5709e25)
     )
-    (fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer "F.SilkS") (width 0.12) (tstamp 544c60f8-33c3-4072-9128-159b26301f32))
-    (fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer "F.SilkS") (width 0.12) (tstamp 735f37c0-266e-4e04-9f8a-f6cde3127c80))
-    (fp_line (start 1.4 -0.7) (end 1.4 0.7) (layer "F.CrtYd") (width 0.05) (tstamp 26728b6e-9118-480b-99e3-604f9a910611))
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-    (pad "1" smd roundrect locked (at -0.8 0) (size 0.7 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (fp_line (start -0.162779 -0.51) (end 0.162779 -0.51)
+      (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 544c60f8-33c3-4072-9128-159b26301f32))
+    (fp_line (start -0.162779 0.51) (end 0.162779 0.51)
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+    (fp_line (start -1.4 -0.7) (end 1.4 -0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 40e578f2-1ac9-4226-a5eb-3394be61171f))
+    (fp_line (start -1.4 0.7) (end -1.4 -0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 6837edd1-0808-44ba-871a-f13c8040a564))
+    (fp_line (start 1.4 -0.7) (end 1.4 0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 26728b6e-9118-480b-99e3-604f9a910611))
+    (fp_line (start 1.4 0.7) (end -1.4 0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp e83de6d9-e2fe-48ab-aeb7-834d6c1c834b))
+    (fp_line (start -0.8 -0.4) (end 0.8 -0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp c482c94a-1189-49d4-a319-e3ae64100959))
+    (fp_line (start -0.8 0.4) (end -0.8 -0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 329980e2-6d3b-4872-a4a9-f6b4c29649e1))
+    (fp_line (start 0.8 -0.4) (end 0.8 0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp d9b4b9ec-e761-4f6a-8f3c-09025e57fd3d))
+    (fp_line (start 0.8 0.4) (end -0.8 0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 41b76ae1-33a4-4f6a-be62-e7517cb2e6cb))
+    (pad "1" smd roundrect (at -0.8 0) (size 0.7 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 72 "+3V3") (pintype "passive") (tstamp 489d770a-8d64-48be-be65-ba3104a6bb11))
-    (pad "2" smd roundrect locked (at 0.8 0) (size 0.7 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "2" smd roundrect (at 0.8 0) (size 0.7 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 48 "/TMS") (pintype "passive") (tstamp 26e14888-7056-40ff-b5b3-cfe8935186b6))
     (model "${KICAD6_3DMODEL_DIR}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl"
       (offset (xyz 0 0 0))
@@ -2795,7 +3239,7 @@
   )
 
   (footprint "stdpads:R_0603" (layer "F.Cu")
-    (tedit 5EE29B72) (tstamp 00000000-0000-0000-0000-000060217eb5)
+    (tstamp 00000000-0000-0000-0000-000060217eb5)
     (at 80.95 108.5 90)
     (tags "resistor")
     (property "LCSC Part" "C23140")
@@ -2806,30 +3250,40 @@
     (solder_paste_margin -0.05)
     (attr smd)
     (fp_text reference "R31" (at 0 0 90) (layer "F.Fab")
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
       (tstamp efb3bc95-b257-4268-822f-f80ab2b89561)
     )
     (fp_text value "33" (at 0 0.25 90) (layer "F.Fab")
-      (effects (font (size 0.127 0.127) (thickness 0.03175)))
+        (effects (font (size 0.127 0.127) (thickness 0.03175)))
       (tstamp cfa82190-a0ae-430f-bfc8-4113205faaf4)
     )
     (fp_text user "${REFERENCE}" (at 0 0 90) (layer "F.SilkS") hide
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
       (tstamp 16ab3cf3-2a08-482e-99cb-0ca360e40df2)
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-    (pad "1" smd roundrect locked (at -0.8 0 90) (size 0.7 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
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@@ -2966,7 +3470,7 @@
   )
 
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@@ -3010,7 +3524,7 @@
   )
 
   (footprint "stdpads:C_0603" (layer "F.Cu")
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+    (tstamp 00000000-0000-0000-0000-0000606e8738)
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@@ -3021,30 +3535,40 @@
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     (attr smd)
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-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
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+    (pad "2" smd roundrect (at 0.75 0 180) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
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@@ -3054,7 +3578,7 @@
   )
 
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+    (tstamp 00000000-0000-0000-0000-0000606fb5cd)
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     (fp_text user "${REFERENCE}" (at 0 0 90) (layer "F.SilkS") hide
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+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
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+    (fp_line (start -0.162779 -0.51) (end 0.162779 -0.51)
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+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp c5e6356a-6ff9-4d3e-87b8-2db7cc980b64))
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+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 0aa2d383-1bdd-4dcb-b0d1-699efad1e260))
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+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 5a6287cc-e2c6-4796-ac1a-100d7e922017))
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+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 1cbb50a0-15c0-44ab-a4f4-9c88a35f3dc5))
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+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp d1f567e5-4a0e-4704-9a1a-47611a6a97b8))
+    (pad "1" smd roundrect (at -0.75 0 270) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 72 "+3V3") (pintype "passive") (tstamp cab92e7f-c930-4a05-a0ff-e2dc17b22a97))
-    (pad "2" smd roundrect locked (at 0.75 0 270) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "2" smd roundrect (at 0.75 0 270) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pintype "passive") (tstamp 9f30d468-47c0-4633-896e-707b66bc8332))
     (model "${KICAD6_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_0603_1608Metric.wrl"
       (offset (xyz 0 0 0))
@@ -3098,7 +3632,7 @@
   )
 
   (footprint "stdpads:C_0805" (layer "F.Cu")
-    (tedit 5F02840E) (tstamp 00000000-0000-0000-0000-00006071e4b9)
+    (tstamp 00000000-0000-0000-0000-00006071e4b9)
     (at 140.1 124.2 90)
     (tags "capacitor")
     (property "LCSC Part" "C15850")
@@ -3109,30 +3643,40 @@
     (solder_paste_margin -0.025)
     (attr smd)
     (fp_text reference "C7" (at 0 0 270) (layer "F.Fab")
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
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     )
     (fp_text value "10u" (at 0 0.35 90) (layer "F.Fab")
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
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     (fp_text user "${REFERENCE}" (at 0 0 270) (layer "F.SilkS") hide
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
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+    (fp_line (start -0.4064 -0.8) (end 0.4064 -0.8)
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+      (stroke (width 0.15) (type solid)) (layer "F.Fab") (tstamp bd88b8ae-94ec-4f01-a02d-1c2ede5335ce))
+    (pad "1" smd roundrect (at -0.85 0 90) (size 1.05 1.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 1 "+5V") (pintype "passive") (tstamp 10567ef6-5d6c-4204-9c78-4e043ed6b1be))
-    (pad "2" smd roundrect locked (at 0.85 0 90) (size 1.05 1.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "2" smd roundrect (at 0.85 0 90) (size 1.05 1.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pintype "passive") (tstamp 6f0d0817-4305-4493-9b53-68e7055024b0))
     (model "${KICAD6_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_0805_2012Metric.wrl"
       (offset (xyz 0 0 0))
@@ -3142,7 +3686,7 @@
   )
 
   (footprint "stdpads:C_0805" (layer "F.Cu")
-    (tedit 5F02840E) (tstamp 00000000-0000-0000-0000-000060726a8f)
+    (tstamp 00000000-0000-0000-0000-000060726a8f)
     (at 130.35 124.2 90)
     (tags "capacitor")
     (property "LCSC Part" "C15850")
@@ -3153,30 +3697,40 @@
     (solder_paste_margin -0.025)
     (attr smd)
     (fp_text reference "C11" (at 0 0 270) (layer "F.Fab")
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
       (tstamp 66f7278d-9166-450e-85a4-99ad54275601)
     )
     (fp_text value "10u" (at 0 0.35 90) (layer "F.Fab")
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
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     )
     (fp_text user "${REFERENCE}" (at 0 0 270) (layer "F.SilkS") hide
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
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+    (fp_line (start -0.4064 -0.8) (end 0.4064 -0.8)
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+      (stroke (width 0.15) (type solid)) (layer "F.Fab") (tstamp 1225cf11-428c-4935-a428-9817787f3cb2))
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+      (stroke (width 0.15) (type solid)) (layer "F.Fab") (tstamp fc228f37-e30a-4ae5-9295-55ab57c236b2))
+    (fp_line (start 1 -0.625) (end 1 0.625)
+      (stroke (width 0.15) (type solid)) (layer "F.Fab") (tstamp a4de59ef-b1a0-4ee0-8d22-5a9d04a86858))
+    (fp_line (start 1 0.625) (end -1 0.625)
+      (stroke (width 0.15) (type solid)) (layer "F.Fab") (tstamp 02132cb4-54e8-4416-833f-5bf6af50d9c7))
+    (pad "1" smd roundrect (at -0.85 0 90) (size 1.05 1.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 72 "+3V3") (pintype "passive") (tstamp 3c2f55c3-e552-49e6-a345-d7b9fdb60171))
-    (pad "2" smd roundrect locked (at 0.85 0 90) (size 1.05 1.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "2" smd roundrect (at 0.85 0 90) (size 1.05 1.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pintype "passive") (tstamp c9ab3aec-242e-41c2-b166-94dff047d4f7))
     (model "${KICAD6_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_0805_2012Metric.wrl"
       (offset (xyz 0 0 0))
@@ -3186,7 +3740,7 @@
   )
 
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-    (tedit 5EE29C36) (tstamp 091ca369-4426-4a8c-adcd-5f9257da937a)
+    (tstamp 091ca369-4426-4a8c-adcd-5f9257da937a)
     (at 93.3 91.7)
     (tags "capacitor")
     (property "LCSC Part" "")
@@ -3197,30 +3751,40 @@
     (solder_paste_margin -0.04)
     (attr smd)
     (fp_text reference "C6" (at 0 0) (layer "F.Fab")
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
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     )
     (fp_text value "22p" (at 0 0.25) (layer "F.Fab")
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+        (effects (font (size 0.127 0.127) (thickness 0.03175)))
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     (fp_text user "${REFERENCE}" (at 0 0) (layer "F.SilkS") hide
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+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
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+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 198bc75e-4c6b-46a3-bb25-ce87f651d0ec))
+    (pad "1" smd roundrect (at -0.75 0) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 46 "/TCK") (pintype "passive") (tstamp 55c01dee-5a2a-4e30-898c-a9e16cfa3dc3))
-    (pad "2" smd roundrect locked (at 0.75 0) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "2" smd roundrect (at 0.75 0) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pintype "passive") (tstamp 22655d9d-1df2-406c-b1f1-723d5236e6fb))
     (model "${KICAD6_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_0603_1608Metric.wrl"
       (offset (xyz 0 0 0))
@@ -3230,7 +3794,7 @@
   )
 
   (footprint "stdpads:R_0603" (layer "F.Cu")
-    (tedit 5EE29B72) (tstamp 09daa74f-bbdf-489a-a0ef-449efc59783c)
+    (tstamp 09daa74f-bbdf-489a-a0ef-449efc59783c)
     (at 127.8 101 180)
     (tags "resistor")
     (property "LCSC Part" "C31850")
@@ -3241,30 +3805,40 @@
     (solder_paste_margin -0.05)
     (attr smd)
     (fp_text reference "R4" (at 0 0) (layer "F.Fab")
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
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     )
     (fp_text value "10k" (at 0 0.25) (layer "F.Fab")
-      (effects (font (size 0.127 0.127) (thickness 0.03175)))
+        (effects (font (size 0.127 0.127) (thickness 0.03175)))
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     (fp_text user "${REFERENCE}" (at 0 0) (layer "F.SilkS") hide
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+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
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       (net 72 "+3V3") (pintype "passive") (tstamp 95d5c027-4c84-4842-8b4e-5488ea1d7dbe))
-    (pad "2" smd roundrect locked (at 0.8 0 180) (size 0.7 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "2" smd roundrect (at 0.8 0 180) (size 0.7 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
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@@ -3274,7 +3848,7 @@
   )
 
   (footprint "stdpads:SOIC-16_3.9mm" (layer "F.Cu")
-    (tedit 5FDA018C) (tstamp 0d9b8d52-bbea-4051-9c22-5d1d2334ce50)
+    (tstamp 0d9b8d52-bbea-4051-9c22-5d1d2334ce50)
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     (tags "SOIC SO")
@@ -3286,57 +3860,70 @@
     (solder_paste_margin -0.025)
     (attr smd)
     (fp_text reference "U11" (at 0 0) (layer "F.Fab")
-      (effects (font (size 0.8128 0.8128) (thickness 0.2032)))
+        (effects (font (size 0.8128 0.8128) (thickness 0.2032)))
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     )
     (fp_text value "CH340G" (at 0 1.016) (layer "F.Fab")
-      (effects (font (size 0.508 0.508) (thickness 0.127)))
+        (effects (font (size 0.508 0.508) (thickness 0.127)))
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+    (pad "11" smd roundrect (at 1.905 -2.475 270) (size 1.95 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 152 "unconnected-(U11-Pad11)") (pinfunction "~{RI}") (pintype "input+no_connect") (tstamp 1fd542b1-00b6-48c3-bbea-5119f420de56))
-    (pad "12" smd roundrect locked (at 0.635 -2.475 270) (size 1.95 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "12" smd roundrect (at 0.635 -2.475 270) (size 1.95 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 153 "unconnected-(U11-Pad12)") (pinfunction "~{DCD}") (pintype "input+no_connect") (tstamp f0dc7b8b-9133-4ff8-9a2e-3425b1d0d341))
-    (pad "13" smd roundrect locked (at -0.635 -2.475 270) (size 1.95 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "13" smd roundrect (at -0.635 -2.475 270) (size 1.95 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 148 "/TDIu") (pinfunction "~{DTR}") (pintype "output") (tstamp 645ae06c-27e3-44e6-9fa9-ef68eb8d4b8a))
-    (pad "14" smd roundrect locked (at -1.905 -2.475 270) (size 1.95 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "14" smd roundrect (at -1.905 -2.475 270) (size 1.95 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 149 "/TMSu") (pinfunction "~{RTS}") (pintype "output") (tstamp 05ca61fc-fb9c-4afc-84c2-6555bbb75250))
-    (pad "15" smd roundrect locked (at -3.175 -2.475 270) (size 1.95 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "15" smd roundrect (at -3.175 -2.475 270) (size 1.95 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 146 "Net-(R6-Pad1)") (pinfunction "R232") (pintype "input") (tstamp 0981a461-704f-4685-80b3-b0432149711d))
-    (pad "16" smd roundrect locked (at -4.445 -2.475 270) (size 1.95 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "16" smd roundrect (at -4.445 -2.475 270) (size 1.95 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 72 "+3V3") (pinfunction "VCC") (pintype "power_in") (tstamp 5e0b6b1e-4d07-4281-b56b-ebe746cb361f))
     (model "${KICAD6_3DMODEL_DIR}/Package_SO.3dshapes/SOIC-16_3.9x9.9mm_P1.27mm.wrl"
       (offset (xyz 0 0 0))
@@ -3346,7 +3933,7 @@
   )
 
   (footprint "stdpads:C_0603" (layer "F.Cu")
-    (tedit 5EE29C36) (tstamp 10eb3073-dbc1-4115-977e-a45d44a55f41)
+    (tstamp 10eb3073-dbc1-4115-977e-a45d44a55f41)
     (at 64.627 106.848 90)
     (tags "capacitor")
     (property "LCSC Part" "C23630")
@@ -3357,30 +3944,40 @@
     (solder_paste_margin -0.04)
     (attr smd)
     (fp_text reference "C36" (at 0 0 90) (layer "F.Fab")
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
       (tstamp 7beaa67f-5bab-4cb6-b2ba-013eecfd6230)
     )
     (fp_text value "2u2" (at 0 0.25 90) (layer "F.Fab")
-      (effects (font (size 0.127 0.127) (thickness 0.03175)))
+        (effects (font (size 0.127 0.127) (thickness 0.03175)))
       (tstamp b2482309-a766-4915-b345-44ef179418a8)
     )
     (fp_text user "${REFERENCE}" (at 0 0 90) (layer "F.SilkS") hide
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
       (tstamp 5d2d0459-8b89-4d2b-89b8-1fb7961ac675)
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-    (fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer "F.SilkS") (width 0.12) (tstamp 87d61e7a-580d-40f7-81aa-e2dab6222d4f))
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-    (fp_line (start -1.4 0.7) (end -1.4 -0.7) (layer "F.CrtYd") (width 0.05) (tstamp 3f0a3ec1-d966-4fce-930f-a7e84ab4d862))
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+    (fp_line (start -0.162779 -0.51) (end 0.162779 -0.51)
+      (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 87d61e7a-580d-40f7-81aa-e2dab6222d4f))
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+      (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp ffea49f7-3b82-4efe-b380-ff1441d6b59e))
+    (fp_line (start -1.4 -0.7) (end 1.4 -0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp b56461d6-c2c2-494c-986b-e5829b205971))
+    (fp_line (start -1.4 0.7) (end -1.4 -0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 3f0a3ec1-d966-4fce-930f-a7e84ab4d862))
+    (fp_line (start 1.4 -0.7) (end 1.4 0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp dfa9d16e-b764-4909-bfa8-e9e8bb5e3046))
+    (fp_line (start 1.4 0.7) (end -1.4 0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp e02915bc-3fc7-439f-885b-569062a041f5))
+    (fp_line (start -0.8 -0.4) (end 0.8 -0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp b3b59522-1b11-4878-8041-7a56150c9cbe))
+    (fp_line (start -0.8 0.4) (end -0.8 -0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 405e68b4-e648-4343-9303-53df968e7318))
+    (fp_line (start 0.8 -0.4) (end 0.8 0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 3a6ea4d6-2426-41d6-a74a-40dae971b275))
+    (fp_line (start 0.8 0.4) (end -0.8 0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 97340439-d115-48ec-9f6a-075d58386f2c))
+    (pad "1" smd roundrect (at -0.75 0 90) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 72 "+3V3") (pintype "passive") (tstamp 74e46bbe-2caf-4b7b-baac-da296c91294f))
-    (pad "2" smd roundrect locked (at 0.75 0 90) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "2" smd roundrect (at 0.75 0 90) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pintype "passive") (tstamp cd37382e-84e0-4ff6-943b-f74274c068f7))
     (model "${KICAD6_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_0603_1608Metric.wrl"
       (offset (xyz 0 0 0))
@@ -3390,7 +3987,7 @@
   )
 
   (footprint "stdpads:Crystal_SMD_3225-4Pin_3.2x2.5mm" (layer "F.Cu")
-    (tedit 5F326081) (tstamp 13f7b9ef-ebce-4dcb-8984-f362f3edb817)
+    (tstamp 13f7b9ef-ebce-4dcb-8984-f362f3edb817)
     (at 52.4985 99.089 180)
     (descr "SMD Crystal SERIES SMD3225/4 http://www.txccrystal.com/images/pdf/7m-accuracy.pdf, 3.2x2.5mm^2 package")
     (tags "SMD SMT crystal")
@@ -3402,31 +3999,42 @@
     (solder_paste_margin -0.05)
     (attr smd)
     (fp_text reference "Y1" (at 0 0) (layer "F.Fab")
-      (effects (font (size 0.508 0.508) (thickness 0.127)))
+        (effects (font (size 0.508 0.508) (thickness 0.127)))
       (tstamp 99a6a95b-b3e2-49a6-b70f-66853f2c5f70)
     )
     (fp_text value "12M" (at 0 0.75) (layer "F.Fab")
-      (effects (font (size 0.508 0.508) (thickness 0.127)))
+        (effects (font (size 0.508 0.508) (thickness 0.127)))
       (tstamp bd7d7fe3-fc8f-4b9d-ab48-d1edf58d71f5)
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+    (fp_line (start -2.15 -0.85) (end -2.15 1.75)
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+    (pad "1" smd roundrect (at -1.1 0.85 180) (size 1.4 1.2) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 84 "Net-(C8-Pad1)") (pinfunction "1") (pintype "passive") (tstamp 9b9f7445-faae-4f55-99a9-095365147e8f))
-    (pad "2" smd roundrect locked (at 1.1 0.85 180) (size 1.4 1.2) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "2" smd roundrect (at 1.1 0.85 180) (size 1.4 1.2) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pinfunction "2") (pintype "passive") (tstamp d0f9db5c-60b5-4743-a31a-06a1a6c6819a))
-    (pad "3" smd roundrect locked (at 1.1 -0.85 180) (size 1.4 1.2) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "3" smd roundrect (at 1.1 -0.85 180) (size 1.4 1.2) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 137 "Net-(C9-Pad1)") (pinfunction "3") (pintype "passive") (tstamp ebb430b4-7402-4e74-9db7-9efbd42c279a))
-    (pad "4" smd roundrect locked (at -1.1 -0.85 180) (size 1.4 1.2) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "4" smd roundrect (at -1.1 -0.85 180) (size 1.4 1.2) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pinfunction "4") (pintype "passive") (tstamp ed2e8f8c-7324-4ee3-9929-cbb10ff7616c))
     (model "${KICAD6_3DMODEL_DIR}/Crystal.3dshapes/Crystal_SMD_3225-4Pin_3.2x2.5mm.wrl"
       (offset (xyz 0 0 0))
@@ -3436,7 +4044,7 @@
   )
 
   (footprint "stdpads:R_0603" (layer "F.Cu")
-    (tedit 5EE29B72) (tstamp 237a2ec1-321c-426a-bf90-f30416630900)
+    (tstamp 237a2ec1-321c-426a-bf90-f30416630900)
     (at 56.3 116.65 -90)
     (tags "resistor")
     (property "LCSC Part" "C25804")
@@ -3447,30 +4055,40 @@
     (solder_paste_margin -0.05)
     (attr smd)
     (fp_text reference "R7" (at 0 0 90) (layer "F.Fab")
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
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     )
     (fp_text value "10k" (at 0 0.25 90) (layer "F.Fab")
-      (effects (font (size 0.127 0.127) (thickness 0.03175)))
+        (effects (font (size 0.127 0.127) (thickness 0.03175)))
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     )
     (fp_text user "${REFERENCE}" (at 0 0 90) (layer "F.SilkS") hide
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
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+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 1063ded0-04b4-4f20-9e74-8f8fe56b4156))
+    (fp_line (start -1.4 0.7) (end -1.4 -0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 29b629fb-39c7-4868-9944-d05dec889be1))
+    (fp_line (start 1.4 -0.7) (end 1.4 0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 80bae682-eec4-4d11-a0ba-c4fb0bedfa28))
+    (fp_line (start 1.4 0.7) (end -1.4 0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 8d0704fb-c3ab-432f-a9a3-638e632898c0))
+    (fp_line (start -0.8 -0.4) (end 0.8 -0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 828c10bc-246c-420c-b684-3c514e5c9d87))
+    (fp_line (start -0.8 0.4) (end -0.8 -0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp e305c703-57a4-4ed8-a497-e4d45681f9b4))
+    (fp_line (start 0.8 -0.4) (end 0.8 0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 57d91c02-e820-4948-a56e-9705f1c81165))
+    (fp_line (start 0.8 0.4) (end -0.8 0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp fc07aaed-4be3-4390-9720-0a6de646e901))
+    (pad "1" smd roundrect (at -0.8 0 270) (size 0.7 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 72 "+3V3") (pintype "passive") (tstamp a4da2b65-75d5-4e28-bca5-c318b78d8df0))
-    (pad "2" smd roundrect locked (at 0.8 0 270) (size 0.7 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "2" smd roundrect (at 0.8 0 270) (size 0.7 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 144 "/JTAG~{OE}") (pintype "passive") (tstamp ed3c677a-aca0-4216-bd51-947b419c5497))
     (model "${KICAD6_3DMODEL_DIR}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl"
       (offset (xyz 0 0 0))
@@ -3480,7 +4098,7 @@
   )
 
   (footprint "stdpads:R_0603" (layer "F.Cu")
-    (tedit 5EE29B72) (tstamp 30d66150-1ea7-4588-9863-081a4afcea51)
+    (tstamp 30d66150-1ea7-4588-9863-081a4afcea51)
     (at 52.45 109.6 -90)
     (tags "resistor")
     (property "LCSC Part" "C31850")
@@ -3491,30 +4109,40 @@
     (solder_paste_margin -0.05)
     (attr smd)
     (fp_text reference "R8" (at 0 0 90) (layer "F.Fab")
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
       (tstamp aebfa070-8ae1-4fc6-8e81-6b346cffe7c3)
     )
     (fp_text value "10k" (at 0 0.25 90) (layer "F.Fab")
-      (effects (font (size 0.127 0.127) (thickness 0.03175)))
+        (effects (font (size 0.127 0.127) (thickness 0.03175)))
       (tstamp 6a3fbb44-d1f5-4f2a-9ccd-616c45423535)
     )
     (fp_text user "${REFERENCE}" (at 0 0 90) (layer "F.SilkS") hide
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
       (tstamp 16ae228f-312f-434a-8d0b-f5c90b9f5a7e)
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-    (fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer "F.SilkS") (width 0.12) (tstamp 9395be60-77ae-45f5-a135-b979250ae7d5))
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-    (pad "1" smd roundrect locked (at -0.8 0 270) (size 0.7 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (fp_line (start -0.162779 -0.51) (end 0.162779 -0.51)
+      (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 9395be60-77ae-45f5-a135-b979250ae7d5))
+    (fp_line (start -0.162779 0.51) (end 0.162779 0.51)
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+    (fp_line (start -1.4 -0.7) (end 1.4 -0.7)
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+    (fp_line (start 1.4 -0.7) (end 1.4 0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 2f341b03-e875-4d13-b29d-a1e136f936cd))
+    (fp_line (start 1.4 0.7) (end -1.4 0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 78d78710-b96b-499d-88cd-f7e243827df9))
+    (fp_line (start -0.8 -0.4) (end 0.8 -0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 44f67258-708f-49f7-967d-9db221661e42))
+    (fp_line (start -0.8 0.4) (end -0.8 -0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 9d7d8a9a-7262-4811-8225-0345dd685e17))
+    (fp_line (start 0.8 -0.4) (end 0.8 0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 34d1566f-dbc1-49c6-8cb0-2cb54c633cb3))
+    (fp_line (start 0.8 0.4) (end -0.8 0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp d8283dc2-7ff3-49fe-9718-a189bf9e229d))
+    (pad "1" smd roundrect (at -0.8 0 270) (size 0.7 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 138 "/USB5V") (pintype "passive") (tstamp e9483a2d-7ff2-46b9-bc9a-5b3068e1e99d))
-    (pad "2" smd roundrect locked (at 0.8 0 270) (size 0.7 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "2" smd roundrect (at 0.8 0 270) (size 0.7 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 143 "Net-(Q1-Pad1)") (pintype "passive") (tstamp 20481654-b937-4da0-8104-556bc4355376))
     (model "${KICAD6_3DMODEL_DIR}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl"
       (offset (xyz 0 0 0))
@@ -3524,7 +4152,7 @@
   )
 
   (footprint "stdpads:R_0603" (layer "F.Cu")
-    (tedit 5EE29B72) (tstamp 3567791a-9057-436d-9cff-1703d87ee221)
+    (tstamp 3567791a-9057-436d-9cff-1703d87ee221)
     (at 127.8 97.8 180)
     (tags "resistor")
     (property "LCSC Part" "C31850")
@@ -3535,30 +4163,40 @@
     (solder_paste_margin -0.05)
     (attr smd)
     (fp_text reference "R2" (at 0 0) (layer "F.Fab")
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
       (tstamp 030ee9cc-6886-4e10-ae41-9e6bcea3c38f)
     )
     (fp_text value "10k" (at 0 0.25) (layer "F.Fab")
-      (effects (font (size 0.127 0.127) (thickness 0.03175)))
+        (effects (font (size 0.127 0.127) (thickness 0.03175)))
       (tstamp dfc98a48-c1b8-40f3-a374-bf23657f3a5e)
     )
     (fp_text user "${REFERENCE}" (at 0 0) (layer "F.SilkS") hide
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
       (tstamp d7f3b27e-8f7d-4f1f-a99a-859375c15a46)
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+    (fp_line (start -0.162779 -0.51) (end 0.162779 -0.51)
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+    (fp_line (start -1.4 0.7) (end -1.4 -0.7)
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+    (fp_line (start 1.4 -0.7) (end 1.4 0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp a943202a-6ab3-4459-a37f-e83d1e328b69))
+    (fp_line (start 1.4 0.7) (end -1.4 0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 049d6a58-8033-4476-a90c-5cb8bada8899))
+    (fp_line (start -0.8 -0.4) (end 0.8 -0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 9da3f94b-b9c9-4099-9bb0-00931a115833))
+    (fp_line (start -0.8 0.4) (end -0.8 -0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 72e332cf-5392-4d87-b1b3-a1670fb6cb45))
+    (fp_line (start 0.8 -0.4) (end 0.8 0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 223f3d9d-9089-443e-ab73-0a6fe8990e70))
+    (fp_line (start 0.8 0.4) (end -0.8 0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp ccfc3fe4-08d1-4463-b118-955de0230ebc))
+    (pad "1" smd roundrect (at -0.8 0 180) (size 0.7 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 72 "+3V3") (pintype "passive") (tstamp 84bb2617-d5f8-4c96-956b-6977c4233a4c))
-    (pad "2" smd roundrect locked (at 0.8 0 180) (size 0.7 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "2" smd roundrect (at 0.8 0 180) (size 0.7 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 125 "/DONE") (pintype "passive") (tstamp 9a596547-b389-45ce-b267-4af254c992d7))
     (model "${KICAD6_3DMODEL_DIR}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl"
       (offset (xyz 0 0 0))
@@ -3568,7 +4206,7 @@
   )
 
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-    (tedit 5EE29C36) (tstamp 497a855b-1e97-43c0-8213-741b3eb4fecc)
+    (tstamp 497a855b-1e97-43c0-8213-741b3eb4fecc)
     (at 38.2 112.95)
     (tags "capacitor")
     (property "LCSC Part" "C23630")
@@ -3579,30 +4217,40 @@
     (solder_paste_margin -0.04)
     (attr smd)
     (fp_text reference "C27" (at 0 0) (layer "F.Fab")
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
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     )
     (fp_text value "2u2" (at 0 0.25) (layer "F.Fab")
-      (effects (font (size 0.127 0.127) (thickness 0.03175)))
+        (effects (font (size 0.127 0.127) (thickness 0.03175)))
       (tstamp 2fef3453-900a-4add-9423-1f2000619cbf)
     )
     (fp_text user "${REFERENCE}" (at 0 0) (layer "F.SilkS") hide
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
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+    (fp_line (start -0.162779 -0.51) (end 0.162779 -0.51)
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       (net 72 "+3V3") (pintype "passive") (tstamp 4022a88d-5787-47b9-ba51-d069bc4bcc99))
-    (pad "2" smd roundrect locked (at 0.75 0) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "2" smd roundrect (at 0.75 0) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pintype "passive") (tstamp 4155b434-c409-4772-a4b7-66fc06212ac3))
     (model "${KICAD6_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_0603_1608Metric.wrl"
       (offset (xyz 0 0 0))
@@ -3612,7 +4260,7 @@
   )
 
   (footprint "stdpads:SOT-23" (layer "F.Cu")
-    (tedit 5F29B98F) (tstamp 5b625039-6504-4134-8ce4-ef691e3aaf31)
+    (tstamp 5b625039-6504-4134-8ce4-ef691e3aaf31)
     (at 49.9 113.35 180)
     (tags "SOT-23")
     (property "Sheetfile" "GR8RAM.kicad_sch")
@@ -3622,31 +4270,44 @@
     (solder_paste_margin -0.05)
     (attr smd)
     (fp_text reference "Q1" (at 0 0 90) (layer "F.Fab")
-      (effects (font (size 0.381 0.381) (thickness 0.09525)))
+        (effects (font (size 0.381 0.381) (thickness 0.09525)))
       (tstamp 31fcd116-2107-4df2-b4db-9ef3befdd0ea)
     )
     (fp_text value "MMBT3904" (at 0.45 0 90) (layer "F.Fab")
-      (effects (font (size 0.127 0.127) (thickness 0.03175)))
+        (effects (font (size 0.127 0.127) (thickness 0.03175)))
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+    (fp_line (start -0.76 -1.58) (end -0.76 -0.65)
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+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp fa599e80-abdb-434f-b67d-c06ab6add779))
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+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp af6cedfe-1a56-4eb3-8c5e-223c6cb22a51))
+    (fp_line (start 0.7 0.95) (end 0.15 1.52)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp ac4da1d0-a23f-4d51-ac12-f48ea8290426))
+    (fp_line (start 0.7 0.95) (end 0.7 -1.5)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 1563bc3c-020f-472c-bda1-4dcf6f73ced1))
+    (pad "1" smd roundrect (at 1.05 0.95) (size 1.35 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 143 "Net-(Q1-Pad1)") (pinfunction "B") (pintype "input") (tstamp 083f4d96-3b6d-4474-a32c-4b7649e83dfb))
-    (pad "2" smd roundrect locked (at 1.05 -0.95) (size 1.35 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "2" smd roundrect (at 1.05 -0.95) (size 1.35 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pinfunction "E") (pintype "passive") (tstamp f23df0ce-1245-4e8d-8d57-07eba82687df))
-    (pad "3" smd roundrect locked (at -1.05 0) (size 1.35 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "3" smd roundrect (at -1.05 0) (size 1.35 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 144 "/JTAG~{OE}") (pinfunction "C") (pintype "passive") (tstamp 87ffc5a8-f42a-4376-8c22-eb952f1cea3b))
     (model "${KICAD6_3DMODEL_DIR}/Package_TO_SOT_SMD.3dshapes/SOT-23.wrl"
       (offset (xyz 0 0 0))
@@ -3656,7 +4317,7 @@
   )
 
   (footprint "stdpads:C_0603" (layer "F.Cu")
-    (tedit 5EE29C36) (tstamp 5be76271-0e13-4ef0-a09f-92f9a9afb4e5)
+    (tstamp 5be76271-0e13-4ef0-a09f-92f9a9afb4e5)
     (at 55.483 99.0135 -90)
     (tags "capacitor")
     (property "LCSC Part" "C1653")
@@ -3667,30 +4328,40 @@
     (solder_paste_margin -0.04)
     (attr smd)
     (fp_text reference "C9" (at 0 0 -270) (layer "F.Fab")
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
       (tstamp ca4b0e12-10b9-4249-a961-aa54a5bf27ee)
     )
     (fp_text value "22p" (at 0 0.25 -270) (layer "F.Fab")
-      (effects (font (size 0.127 0.127) (thickness 0.03175)))
+        (effects (font (size 0.127 0.127) (thickness 0.03175)))
       (tstamp 611fe7a6-a9ea-4b45-b5ac-911a6f29aea0)
     )
     (fp_text user "${REFERENCE}" (at 0 0 -270) (layer "F.SilkS") hide
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
       (tstamp 41fb6d3d-31c5-4885-9a16-1a1a061e7af7)
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+    (fp_line (start -0.162779 -0.51) (end 0.162779 -0.51)
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+    (fp_line (start 0.8 0.4) (end -0.8 0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 69d2501b-f8ec-423b-bd55-046782bbdb87))
+    (pad "1" smd roundrect (at -0.75 0 270) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 137 "Net-(C9-Pad1)") (pintype "passive") (tstamp 74372ce1-1a32-427a-b58f-552718e455fd))
-    (pad "2" smd roundrect locked (at 0.75 0 270) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "2" smd roundrect (at 0.75 0 270) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pintype "passive") (tstamp fc5991ad-1af8-4279-bf88-016341740d5e))
     (model "${KICAD6_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_0603_1608Metric.wrl"
       (offset (xyz 0 0 0))
@@ -3700,7 +4371,7 @@
   )
 
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-    (tedit 5EE29B72) (tstamp 5cd10bf2-2130-42b7-887a-498f5c2e769f)
+    (tstamp 5cd10bf2-2130-42b7-887a-498f5c2e769f)
     (at 127.8 96.2 180)
     (tags "resistor")
     (property "LCSC Part" "C31850")
@@ -3711,30 +4382,40 @@
     (solder_paste_margin -0.05)
     (attr smd)
     (fp_text reference "R1" (at 0 0) (layer "F.Fab")
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
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     )
     (fp_text value "10k" (at 0 0.25) (layer "F.Fab")
-      (effects (font (size 0.127 0.127) (thickness 0.03175)))
+        (effects (font (size 0.127 0.127) (thickness 0.03175)))
       (tstamp 3b759f5e-fd36-4e32-9fd6-498dbcff008e)
     )
     (fp_text user "${REFERENCE}" (at 0 0) (layer "F.SilkS") hide
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+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
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-    (pad "2" smd roundrect locked (at 0.8 0 180) (size 0.7 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "2" smd roundrect (at 0.8 0 180) (size 0.7 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 94 "/SDQML") (pintype "passive") (tstamp 58e9b82a-10ad-4642-88f4-f9bd2d375fca))
     (model "${KICAD6_3DMODEL_DIR}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl"
       (offset (xyz 0 0 0))
@@ -3744,7 +4425,7 @@
   )
 
   (footprint "stdpads:TSSOP-20_4.4x6.5mm_P0.65mm" (layer "F.Cu")
-    (tedit 5F27C9F6) (tstamp 5ede51ff-cade-4966-a97b-9cf3f3db4e2e)
+    (tstamp 5ede51ff-cade-4966-a97b-9cf3f3db4e2e)
     (at 51.1 119.725 -90)
     (descr "20-Lead Plastic Thin Shrink Small Outline (ST)-4.4 mm Body [TSSOP] (see Microchip Packaging Specification 00000049BS.pdf)")
     (tags "SSOP 0.65")
@@ -3756,28 +4437,39 @@
     (solder_paste_margin -0.04)
     (attr smd)
     (fp_text reference "U10" (at 0 0 90) (layer "F.Fab")
-      (effects (font (size 0.8128 0.8128) (thickness 0.2032)))
+        (effects (font (size 0.8128 0.8128) (thickness 0.2032)))
       (tstamp b5e5849c-9369-40f0-9d90-2cd7650dcc33)
     )
     (fp_text value "74AHC245PW" (at 0 1.016 90) (layer "F.Fab")
-      (effects (font (size 0.508 0.508) (thickness 0.127)))
+        (effects (font (size 0.508 0.508) (thickness 0.127)))
       (tstamp 034dd4ec-0641-4b1a-9c5f-426678f13209)
     )
     (fp_text user "${REFERENCE}" (at 0 0 90) (layer "F.SilkS")
-      (effects (font (size 0.8128 0.8128) (thickness 0.2032)))
+        (effects (font (size 0.8128 0.8128) (thickness 0.2032)))
       (tstamp 4377fdf1-a78d-4042-b240-e439759a7aab)
     )
-    (fp_line (start 3.45 2.225) (end 3.45 -2.225) (layer "F.SilkS") (width 0.15) (tstamp 6d6aeb69-8910-49f1-b6f6-b502e8634dbb))
-    (fp_line (start -3.45 3.75) (end -3.45 -2.225) (layer "F.SilkS") (width 0.15) (tstamp cb733d9b-70cc-4d3d-9d5f-6a16f85e4489))
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+    (fp_line (start -3.45 3.75) (end -3.45 -2.225)
+      (stroke (width 0.15) (type solid)) (layer "F.SilkS") (tstamp cb733d9b-70cc-4d3d-9d5f-6a16f85e4489))
+    (fp_line (start 3.45 2.225) (end 3.45 -2.225)
+      (stroke (width 0.15) (type solid)) (layer "F.SilkS") (tstamp 6d6aeb69-8910-49f1-b6f6-b502e8634dbb))
+    (fp_line (start -3.55 -3.95) (end 3.55 -3.95)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 97bb598e-949e-4b04-99ef-761b6c309f13))
+    (fp_line (start -3.55 3.95) (end -3.55 -3.95)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 044abe59-2d3a-4748-b878-e279ed0d7dc1))
+    (fp_line (start -3.55 3.95) (end 3.55 3.95)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 80b8e27f-ea0c-4594-988f-48a8148f873a))
+    (fp_line (start 3.55 3.95) (end 3.55 -3.95)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 06d53d09-934d-45e8-ad95-e609ba04a1d2))
+    (fp_line (start -3.25 -2.2) (end 3.25 -2.2)
+      (stroke (width 0.15) (type solid)) (layer "F.Fab") (tstamp 5705f504-e63a-42c1-a3fd-cc1eaf8fba54))
+    (fp_line (start -3.25 1.2) (end -3.25 -2.2)
+      (stroke (width 0.15) (type solid)) (layer "F.Fab") (tstamp c957bc7a-2ab2-4ffc-90cf-fabbd3c778f1))
+    (fp_line (start -2.25 2.2) (end -3.25 1.2)
+      (stroke (width 0.15) (type solid)) (layer "F.Fab") (tstamp 4259af76-c02f-4bfd-8577-42f054c0e187))
+    (fp_line (start 3.25 -2.2) (end 3.25 2.2)
+      (stroke (width 0.15) (type solid)) (layer "F.Fab") (tstamp 0881657e-e50d-4ba3-8f01-958cbae4883a))
+    (fp_line (start 3.25 2.2) (end -2.25 2.2)
+      (stroke (width 0.15) (type solid)) (layer "F.Fab") (tstamp bb3687f2-7657-455e-bb0a-2e7fd13ded8e))
     (pad "1" smd roundrect (at -2.925 2.95) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 72 "+3V3") (pinfunction "AtoB") (pintype "input") (tstamp 12479790-970d-4e60-a6f2-8d521f98610b))
     (pad "2" smd roundrect (at -2.275 2.95) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
@@ -3826,7 +4518,7 @@
   )
 
   (footprint "stdpads:C_0603" (layer "F.Cu")
-    (tedit 5EE29C36) (tstamp 6791d2e9-8ccf-4599-9c50-8708a491bb28)
+    (tstamp 6791d2e9-8ccf-4599-9c50-8708a491bb28)
     (at 152.7 142.9)
     (tags "capacitor")
     (property "LCSC Part" "C23630")
@@ -3837,30 +4529,40 @@
     (solder_paste_margin -0.04)
     (attr smd)
     (fp_text reference "C42" (at 0 0) (layer "F.Fab")
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
       (tstamp b8d50ee3-d8b1-49bf-b9aa-b0b427ba69f5)
     )
     (fp_text value "2u2" (at 0 0.25) (layer "F.Fab")
-      (effects (font (size 0.127 0.127) (thickness 0.03175)))
+        (effects (font (size 0.127 0.127) (thickness 0.03175)))
       (tstamp 08927a53-d150-4176-9fab-f5c3b8201161)
     )
     (fp_text user "${REFERENCE}" (at 0 0) (layer "F.SilkS") hide
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
       (tstamp c2569c25-fae8-46bd-9431-71bc40fb958c)
     )
-    (fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer "F.SilkS") (width 0.12) (tstamp 674d718d-dd4a-4275-90e1-fa92fe2bf205))
-    (fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer "F.SilkS") (width 0.12) (tstamp c674e71b-3dde-42d2-9221-a2e79651f94a))
-    (fp_line (start -1.4 0.7) (end -1.4 -0.7) (layer "F.CrtYd") (width 0.05) (tstamp 64850343-cd94-49d3-bc03-2422b054786c))
-    (fp_line (start -1.4 -0.7) (end 1.4 -0.7) (layer "F.CrtYd") (width 0.05) (tstamp 7512a4cf-d674-49fb-b4cd-c765e0ebbbdf))
-    (fp_line (start 1.4 -0.7) (end 1.4 0.7) (layer "F.CrtYd") (width 0.05) (tstamp ac85b037-2184-46fc-8e39-c13fc3e492ba))
-    (fp_line (start 1.4 0.7) (end -1.4 0.7) (layer "F.CrtYd") (width 0.05) (tstamp f83cce3f-ba23-4d0a-927f-ed07be2254e9))
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-    (pad "1" smd roundrect locked (at -0.75 0) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (fp_line (start -0.162779 -0.51) (end 0.162779 -0.51)
+      (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 674d718d-dd4a-4275-90e1-fa92fe2bf205))
+    (fp_line (start -0.162779 0.51) (end 0.162779 0.51)
+      (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp c674e71b-3dde-42d2-9221-a2e79651f94a))
+    (fp_line (start -1.4 -0.7) (end 1.4 -0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 7512a4cf-d674-49fb-b4cd-c765e0ebbbdf))
+    (fp_line (start -1.4 0.7) (end -1.4 -0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 64850343-cd94-49d3-bc03-2422b054786c))
+    (fp_line (start 1.4 -0.7) (end 1.4 0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp ac85b037-2184-46fc-8e39-c13fc3e492ba))
+    (fp_line (start 1.4 0.7) (end -1.4 0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp f83cce3f-ba23-4d0a-927f-ed07be2254e9))
+    (fp_line (start -0.8 -0.4) (end 0.8 -0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 0df4501c-4c49-4981-b997-c05ef8c8bb4f))
+    (fp_line (start -0.8 0.4) (end -0.8 -0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 767e9973-ef44-40a5-a7fb-55ab09f176a4))
+    (fp_line (start 0.8 -0.4) (end 0.8 0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 68b8020f-ad2f-4142-846b-6e7ae326ebe0))
+    (fp_line (start 0.8 0.4) (end -0.8 0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 051d38dd-c1b9-4850-9994-54e2efab21e2))
+    (pad "1" smd roundrect (at -0.75 0) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 72 "+3V3") (pintype "passive") (tstamp 85dca8af-ed01-44c2-acb0-61fcd7593d5a))
-    (pad "2" smd roundrect locked (at 0.75 0) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "2" smd roundrect (at 0.75 0) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pintype "passive") (tstamp 23d0e33c-26a2-4b0a-8c6c-df609cccb2de))
     (model "${KICAD6_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_0603_1608Metric.wrl"
       (offset (xyz 0 0 0))
@@ -3870,7 +4572,7 @@
   )
 
   (footprint "stdpads:R_0603" (layer "F.Cu")
-    (tedit 5EE29B72) (tstamp 7858b7dd-dd75-4850-bfbd-e814545fea18)
+    (tstamp 7858b7dd-dd75-4850-bfbd-e814545fea18)
     (at 69.4 95.4 -90)
     (tags "resistor")
     (property "LCSC Part" "C31850")
@@ -3881,30 +4583,40 @@
     (solder_paste_margin -0.05)
     (attr smd)
     (fp_text reference "R12" (at 0 0 90) (layer "F.Fab")
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
       (tstamp f2009e54-625e-4586-b5fd-bc10775310d2)
     )
     (fp_text value "10k" (at 0 0.25 90) (layer "F.Fab")
-      (effects (font (size 0.127 0.127) (thickness 0.03175)))
+        (effects (font (size 0.127 0.127) (thickness 0.03175)))
       (tstamp e72fd412-2637-4f64-9136-d1770d6a3c8d)
     )
     (fp_text user "${REFERENCE}" (at 0 0 90) (layer "F.SilkS") hide
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
       (tstamp 5782ea70-39af-4095-9308-b1f9d74ed4fa)
     )
-    (fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer "F.SilkS") (width 0.12) (tstamp 5fe227ab-a5bd-47c6-accb-68adfdc7a944))
-    (fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer "F.SilkS") (width 0.12) (tstamp cb4ea0d1-c35e-40c1-b8e4-00cb54f72a76))
-    (fp_line (start -1.4 0.7) (end -1.4 -0.7) (layer "F.CrtYd") (width 0.05) (tstamp 06641e88-2093-476f-8494-84609eb00db3))
-    (fp_line (start 1.4 -0.7) (end 1.4 0.7) (layer "F.CrtYd") (width 0.05) (tstamp 38bcc72f-7e9c-4ad8-a1fc-0ae6c31232e1))
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-    (fp_line (start 1.4 0.7) (end -1.4 0.7) (layer "F.CrtYd") (width 0.05) (tstamp a4cca132-a65d-41a9-a777-d38abd340e1c))
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-    (pad "1" smd roundrect locked (at -0.8 0 270) (size 0.7 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (fp_line (start -0.162779 -0.51) (end 0.162779 -0.51)
+      (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 5fe227ab-a5bd-47c6-accb-68adfdc7a944))
+    (fp_line (start -0.162779 0.51) (end 0.162779 0.51)
+      (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp cb4ea0d1-c35e-40c1-b8e4-00cb54f72a76))
+    (fp_line (start -1.4 -0.7) (end 1.4 -0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 4b2bf9e2-00c6-493d-8f98-6e535fe80215))
+    (fp_line (start -1.4 0.7) (end -1.4 -0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 06641e88-2093-476f-8494-84609eb00db3))
+    (fp_line (start 1.4 -0.7) (end 1.4 0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 38bcc72f-7e9c-4ad8-a1fc-0ae6c31232e1))
+    (fp_line (start 1.4 0.7) (end -1.4 0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp a4cca132-a65d-41a9-a777-d38abd340e1c))
+    (fp_line (start -0.8 -0.4) (end 0.8 -0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp b292aa8c-7529-4737-a82e-28490d72cecb))
+    (fp_line (start -0.8 0.4) (end -0.8 -0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 20ec51d7-8264-4a94-b347-4def372c9344))
+    (fp_line (start 0.8 -0.4) (end 0.8 0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp e62b4b0c-72b1-45f0-a810-1a0b39b60ff5))
+    (fp_line (start 0.8 0.4) (end -0.8 0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 5c588463-69e2-4997-ba86-cf5fae35f166))
+    (pad "1" smd roundrect (at -0.8 0 270) (size 0.7 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 72 "+3V3") (pintype "passive") (tstamp bd0a73e7-aea8-4aad-8c62-579ea6bc9b42))
-    (pad "2" smd roundrect locked (at 0.8 0 270) (size 0.7 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "2" smd roundrect (at 0.8 0 270) (size 0.7 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 121 "/FD2") (pintype "passive") (tstamp fbaa2f32-b014-4c56-b816-26dee7a4568b))
     (model "${KICAD6_3DMODEL_DIR}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl"
       (offset (xyz 0 0 0))
@@ -3914,7 +4626,7 @@
   )
 
   (footprint "stdpads:R_0603" (layer "F.Cu")
-    (tedit 5EE29B72) (tstamp 7c6f9f94-5c0a-4e36-ae67-f6f745cc0e0e)
+    (tstamp 7c6f9f94-5c0a-4e36-ae67-f6f745cc0e0e)
     (at 64.627 103.9405 -90)
     (tags "resistor")
     (property "LCSC Part" "C25804")
@@ -3925,30 +4637,40 @@
     (solder_paste_margin -0.05)
     (attr smd)
     (fp_text reference "R5" (at 0 0 -270) (layer "F.Fab")
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
       (tstamp 0a0d2192-3f02-44d3-ac4d-df9571c3b6e6)
     )
     (fp_text value "10k" (at 0 0.25 -270) (layer "F.Fab")
-      (effects (font (size 0.127 0.127) (thickness 0.03175)))
+        (effects (font (size 0.127 0.127) (thickness 0.03175)))
       (tstamp 90c570cd-12d2-4cc2-95d4-d48396ea78b4)
     )
     (fp_text user "${REFERENCE}" (at 0 0 -270) (layer "F.SilkS") hide
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
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-    (pad "2" smd roundrect locked (at 0.8 0 270) (size 0.7 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "2" smd roundrect (at 0.8 0 270) (size 0.7 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
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@@ -3958,7 +4680,7 @@
   )
 
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     (attr smd)
     (fp_text reference "C35" (at 0 0) (layer "F.Fab")
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
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-    (pad "2" smd roundrect locked (at 0.75 0 180) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "2" smd roundrect (at 0.75 0 180) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
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@@ -4002,7 +4734,7 @@
   )
 
   (footprint "stdpads:C_0603" (layer "F.Cu")
-    (tedit 5EE29C36) (tstamp 9777003e-10f5-4719-9eba-0d7636697d08)
+    (tstamp 9777003e-10f5-4719-9eba-0d7636697d08)
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     (tags "capacitor")
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     (attr smd)
     (fp_text reference "C39" (at 0 0) (layer "F.Fab")
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
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     (fp_text value "2u2" (at 0 0.25) (layer "F.Fab")
-      (effects (font (size 0.127 0.127) (thickness 0.03175)))
+        (effects (font (size 0.127 0.127) (thickness 0.03175)))
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     (fp_text user "${REFERENCE}" (at 0 0) (layer "F.SilkS") hide
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-    (pad "2" smd roundrect locked (at 0.75 0 180) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "2" smd roundrect (at 0.75 0 180) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
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@@ -4046,7 +4788,7 @@
   )
 
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+    (fp_line (start -0.162779 -0.51) (end 0.162779 -0.51)
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+    (fp_line (start 1.4 -0.7) (end 1.4 0.7)
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+    (fp_line (start 1.4 0.7) (end -1.4 0.7)
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+    (fp_line (start -0.8 -0.4) (end 0.8 -0.4)
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+    (fp_line (start -0.8 0.4) (end -0.8 -0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp e8d14a85-0084-411d-bef7-45bfbabd1dff))
+    (fp_line (start 0.8 -0.4) (end 0.8 0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 881c13df-7641-4739-9f21-eeffc82890b8))
+    (fp_line (start 0.8 0.4) (end -0.8 0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp c390871e-5e99-4811-bbce-7261ec540bf7))
+    (pad "1" smd roundrect (at -0.75 0 90) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 84 "Net-(C8-Pad1)") (pintype "passive") (tstamp 63c79ca6-1b61-4c7d-ac5c-60e1c5b795ea))
-    (pad "2" smd roundrect locked (at 0.75 0 90) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "2" smd roundrect (at 0.75 0 90) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pintype "passive") (tstamp 9b56e101-86f8-4e1b-8239-49524bdca690))
     (model "${KICAD6_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_0603_1608Metric.wrl"
       (offset (xyz 0 0 0))
@@ -4090,7 +4842,7 @@
   )
 
   (footprint "stdpads:R_0603" (layer "F.Cu")
-    (tedit 5EE29B72) (tstamp a21188eb-176d-401b-95d0-388669a91132)
+    (tstamp a21188eb-176d-401b-95d0-388669a91132)
     (at 47.1 113.2 -90)
     (tags "resistor")
     (property "LCSC Part" "C31850")
@@ -4101,30 +4853,40 @@
     (solder_paste_margin -0.05)
     (attr smd)
     (fp_text reference "R9" (at 0 0 90) (layer "F.Fab")
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
       (tstamp bda35dc1-f601-4283-94fd-2febbdacf723)
     )
     (fp_text value "10k" (at 0 0.25 90) (layer "F.Fab")
-      (effects (font (size 0.127 0.127) (thickness 0.03175)))
+        (effects (font (size 0.127 0.127) (thickness 0.03175)))
       (tstamp cfa1a4e8-e474-4c54-bac2-9ac5849df000)
     )
     (fp_text user "${REFERENCE}" (at 0 0 90) (layer "F.SilkS") hide
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
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+    (fp_line (start -0.162779 -0.51) (end 0.162779 -0.51)
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+    (fp_line (start 1.4 0.7) (end -1.4 0.7)
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+    (fp_line (start 0.8 0.4) (end -0.8 0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 7f252522-df05-4f50-a3bc-0afde8dd2bef))
+    (pad "1" smd roundrect (at -0.8 0 270) (size 0.7 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 143 "Net-(Q1-Pad1)") (pintype "passive") (tstamp 51a0c9c3-26d5-4852-9830-17ad49e3c878))
-    (pad "2" smd roundrect locked (at 0.8 0 270) (size 0.7 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "2" smd roundrect (at 0.8 0 270) (size 0.7 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pintype "passive") (tstamp 4ac635d0-3984-4a52-8f4e-d84555261940))
     (model "${KICAD6_3DMODEL_DIR}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl"
       (offset (xyz 0 0 0))
@@ -4134,7 +4896,7 @@
   )
 
   (footprint "stdpads:R_0603" (layer "F.Cu")
-    (tedit 5EE29B72) (tstamp b32fd077-1172-413d-8913-35f44d78e78b)
+    (tstamp b32fd077-1172-413d-8913-35f44d78e78b)
     (at 127.8 99.4 180)
     (tags "resistor")
     (property "LCSC Part" "C31850")
@@ -4145,30 +4907,40 @@
     (solder_paste_margin -0.05)
     (attr smd)
     (fp_text reference "R3" (at 0 0) (layer "F.Fab")
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
       (tstamp 6357f01f-2ed7-4335-a83e-f0ddcb562d7a)
     )
     (fp_text value "10k" (at 0 0.25) (layer "F.Fab")
-      (effects (font (size 0.127 0.127) (thickness 0.03175)))
+        (effects (font (size 0.127 0.127) (thickness 0.03175)))
       (tstamp 0a0a1159-2d41-4d95-9b2d-925316af613e)
     )
     (fp_text user "${REFERENCE}" (at 0 0) (layer "F.SilkS") hide
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
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+    (fp_line (start -0.162779 -0.51) (end 0.162779 -0.51)
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+    (fp_line (start 1.4 0.7) (end -1.4 0.7)
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+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp a1987285-9f22-4fae-aaec-af7af1d84d78))
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+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 655f1024-63b2-4acd-84cd-39126762e045))
+    (pad "1" smd roundrect (at -0.8 0 180) (size 0.7 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 72 "+3V3") (pintype "passive") (tstamp c3aad3d9-dc60-490d-aa60-6f3611cd0715))
-    (pad "2" smd roundrect locked (at 0.8 0 180) (size 0.7 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "2" smd roundrect (at 0.8 0 180) (size 0.7 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 128 "/~{JTAGEN}") (pintype "passive") (tstamp 14f401c8-8c53-48ef-89aa-3b4c1f514813))
     (model "${KICAD6_3DMODEL_DIR}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl"
       (offset (xyz 0 0 0))
@@ -4178,7 +4950,7 @@
   )
 
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-    (tedit 5EE29C36) (tstamp b5f50ecd-dcee-4396-ad7c-79a5ed59e5cd)
+    (tstamp b5f50ecd-dcee-4396-ad7c-79a5ed59e5cd)
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     (tags "capacitor")
     (property "LCSC Part" "C23630")
@@ -4189,30 +4961,40 @@
     (solder_paste_margin -0.04)
     (attr smd)
     (fp_text reference "C38" (at 0 0 90) (layer "F.Fab")
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
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     )
     (fp_text value "2u2" (at 0 0.25 90) (layer "F.Fab")
-      (effects (font (size 0.127 0.127) (thickness 0.03175)))
+        (effects (font (size 0.127 0.127) (thickness 0.03175)))
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     )
     (fp_text user "${REFERENCE}" (at 0 0 90) (layer "F.SilkS") hide
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
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+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp bfab34fd-92de-4ad6-b790-260e94444cd3))
+    (fp_line (start -0.8 0.4) (end -0.8 -0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 66c3b094-94e8-48d9-9718-568165e9e2f3))
+    (fp_line (start 0.8 -0.4) (end 0.8 0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 70f7e041-721f-4754-9488-ee839cd68512))
+    (fp_line (start 0.8 0.4) (end -0.8 0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 24351546-7b7c-42a3-9bb9-592dc9902bfe))
+    (pad "1" smd roundrect (at -0.75 0 90) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 138 "/USB5V") (pintype "passive") (tstamp ff3993e3-3406-43ac-93ed-28cf57abcf2c))
-    (pad "2" smd roundrect locked (at 0.75 0 90) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "2" smd roundrect (at 0.75 0 90) (size 0.85 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pintype "passive") (tstamp 5f138f0d-3bf5-4b8c-a041-449e5aea259f))
     (model "${KICAD6_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_0603_1608Metric.wrl"
       (offset (xyz 0 0 0))
@@ -4222,7 +5004,7 @@
   )
 
   (footprint "stdpads:R_0603" (layer "F.Cu")
-    (tedit 5EE29B72) (tstamp b614483c-4092-46d0-a4ea-26a66ea4aa25)
+    (tstamp b614483c-4092-46d0-a4ea-26a66ea4aa25)
     (at 62.4 124.75 180)
     (tags "resistor")
     (property "LCSC Part" "C23140")
@@ -4233,30 +5015,40 @@
     (solder_paste_margin -0.05)
     (attr smd)
     (fp_text reference "R10" (at 0 0) (layer "F.Fab")
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
       (tstamp 82562c82-ab27-46ff-989a-d5d7e5616bb8)
     )
     (fp_text value "33" (at 0 0.25) (layer "F.Fab")
-      (effects (font (size 0.127 0.127) (thickness 0.03175)))
+        (effects (font (size 0.127 0.127) (thickness 0.03175)))
       (tstamp b5d45c3f-3c52-4de9-bacc-c8dc9ade6042)
     )
     (fp_text user "${REFERENCE}" (at 0 0) (layer "F.SilkS") hide
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
       (tstamp f76aad2e-a8b5-4a6b-a05a-9507b6f2f5c0)
     )
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-    (pad "1" smd roundrect locked (at -0.8 0 180) (size 0.7 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (fp_line (start -0.162779 -0.51) (end 0.162779 -0.51)
+      (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp da0ff716-3bb1-479b-b52d-dfa60a7a3f96))
+    (fp_line (start -0.162779 0.51) (end 0.162779 0.51)
+      (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp af73bb6c-f7fa-4c77-8b73-01abadca5e3c))
+    (fp_line (start -1.4 -0.7) (end 1.4 -0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp a4f5ee25-00f8-4602-9f77-a90916710e57))
+    (fp_line (start -1.4 0.7) (end -1.4 -0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 89979d6c-7726-4739-90d0-b42b3e80af37))
+    (fp_line (start 1.4 -0.7) (end 1.4 0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 750ea727-b38f-434b-bf4e-db1de80a7e32))
+    (fp_line (start 1.4 0.7) (end -1.4 0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 3b99cef1-8299-4df8-8c8b-031d3a9cacb7))
+    (fp_line (start -0.8 -0.4) (end 0.8 -0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 6fe590c9-1751-47e8-aee6-92ca856c2436))
+    (fp_line (start -0.8 0.4) (end -0.8 -0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp af944c00-2e7a-43b1-8a77-9c8b38c541f5))
+    (fp_line (start 0.8 -0.4) (end 0.8 0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 0bdc2f18-01d5-4e18-b2ed-ec3dff052b4e))
+    (fp_line (start 0.8 0.4) (end -0.8 0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp f7b026d6-83c4-400b-a474-3547398ea7dc))
+    (pad "1" smd roundrect (at -0.8 0 180) (size 0.7 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 46 "/TCK") (pintype "passive") (tstamp 0ab1de5b-7b5e-4052-8852-88d64189eaf5))
-    (pad "2" smd roundrect locked (at 0.8 0 180) (size 0.7 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "2" smd roundrect (at 0.8 0 180) (size 0.7 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 139 "/TCKr") (pintype "passive") (tstamp 9fea3d20-baad-4304-ab9a-c84f0d19ca1b))
     (model "${KICAD6_3DMODEL_DIR}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl"
       (offset (xyz 0 0 0))
@@ -4266,7 +5058,7 @@
   )
 
   (footprint "stdpads:R_0603" (layer "F.Cu")
-    (tedit 5EE29B72) (tstamp bbcd5a11-e961-4ac6-8571-52f58a343b8c)
+    (tstamp bbcd5a11-e961-4ac6-8571-52f58a343b8c)
     (at 63.865001 110.328499)
     (tags "resistor")
     (property "LCSC Part" "C25804")
@@ -4277,30 +5069,40 @@
     (solder_paste_margin -0.05)
     (attr smd)
     (fp_text reference "R6" (at 0 0) (layer "F.Fab")
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
       (tstamp d59821e6-4030-4065-bd45-c327208bbd0c)
     )
     (fp_text value "10k" (at 0 0.25) (layer "F.Fab")
-      (effects (font (size 0.127 0.127) (thickness 0.03175)))
+        (effects (font (size 0.127 0.127) (thickness 0.03175)))
       (tstamp ccce0497-a389-44fa-9392-bed93e73a846)
     )
     (fp_text user "${REFERENCE}" (at 0 0) (layer "F.SilkS") hide
-      (effects (font (size 0.254 0.254) (thickness 0.0635)))
+        (effects (font (size 0.254 0.254) (thickness 0.0635)))
       (tstamp c1ca524b-ccab-42d0-a1fe-017f34c1ecf9)
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-    (fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer "F.SilkS") (width 0.12) (tstamp 224611dc-26fb-49a7-be24-eedcc9a8f20e))
-    (fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer "F.SilkS") (width 0.12) (tstamp 4e41c66c-1677-4c92-b48d-f40b31bcebf6))
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-    (pad "1" smd roundrect locked (at -0.8 0) (size 0.7 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (fp_line (start -0.162779 -0.51) (end 0.162779 -0.51)
+      (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 224611dc-26fb-49a7-be24-eedcc9a8f20e))
+    (fp_line (start -0.162779 0.51) (end 0.162779 0.51)
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+    (fp_line (start -1.4 -0.7) (end 1.4 -0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 6ef4d742-c408-4654-995c-7d2e7e2ca9c9))
+    (fp_line (start -1.4 0.7) (end -1.4 -0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 016480e0-9e07-4657-a285-429711ba11a9))
+    (fp_line (start 1.4 -0.7) (end 1.4 0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp dcfc683b-d99f-4dcf-a37c-5f287812217c))
+    (fp_line (start 1.4 0.7) (end -1.4 0.7)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp b2358700-89cb-49a4-9ab8-8b7c334c26ca))
+    (fp_line (start -0.8 -0.4) (end 0.8 -0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp d7a4b18e-bb1c-4ffe-b78f-a93fb2408a2e))
+    (fp_line (start -0.8 0.4) (end -0.8 -0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 2a419547-fbe1-4e45-892d-f306410f3c9d))
+    (fp_line (start 0.8 -0.4) (end 0.8 0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp c979942a-e12c-49e7-8331-d06ba6e2e2d6))
+    (fp_line (start 0.8 0.4) (end -0.8 0.4)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 8ca8aec0-c29c-4dda-8317-fb7f86d4b5d9))
+    (pad "1" smd roundrect (at -0.8 0) (size 0.7 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 146 "Net-(R6-Pad1)") (pintype "passive") (tstamp a5e9e330-7f77-4916-87de-782b6e93a1b3))
-    (pad "2" smd roundrect locked (at 0.8 0) (size 0.7 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+    (pad "2" smd roundrect (at 0.8 0) (size 0.7 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
       (net 2 "GND") (pintype "passive") (tstamp 60ff78cc-9473-45b1-8e6d-3497c278551e))
     (model "${KICAD6_3DMODEL_DIR}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl"
       (offset (xyz 0 0 0))
@@ -4310,7 +5112,7 @@
   )
 
   (footprint "stdpads:USB_Micro-B_ShouHan_MicroXNJ" (layer "F.Cu")
-    (tedit 602BA043) (tstamp be164a42-8327-47c0-80a6-827b416bf9b7)
+    (tstamp be164a42-8327-47c0-80a6-827b416bf9b7)
     (at 48.175 106.5 180)
     (descr "http://www.molex.com/pdm_docs/sd/1050170001_sd.pdf")
     (tags "Micro-USB SMD Typ-B")
@@ -4322,61 +5124,83 @@
     (solder_paste_margin -0.025)
     (attr smd)
     (fp_text reference "J3" (at -0.45 0 90) (layer "F.Fab")
-      (effects (font (size 0.8128 0.8128) (thickness 0.2032)))
+        (effects (font (size 0.8128 0.8128) (thickness 0.2032)))
       (tstamp 2b4b9b25-cad6-49b0-9896-bb1fcd67833f)
     )
     (fp_text value "microUSB" (at -3.5 0 90) (layer "F.Fab")
-      (effects (font (size 0.8128 0.8128) (thickness 0.2032)))
+        (effects (font (size 0.8128 0.8128) (thickness 0.2032)))
       (tstamp 321ad49a-f0b5-441f-8013-1c01d956847c)
     )
     (fp_text user "PCB Edge" (at 2.05 0 90) (layer "Dwgs.User")
-      (effects (font (size 0.5 0.5) (thickness 0.08)))
+        (effects (font (size 0.5 0.5) (thickness 0.08)))
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+    (pad "10" smd roundrect (at 0.65 -2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
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+    (pad "12" smd roundrect (at -0.65 -2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
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+    (pad "13" smd roundrect (at -1.3 -2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
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+    (pad "14" smd roundrect (at -1.95 -2.95 90) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
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@@ -4459,7 +5299,7 @@
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+        (xy 91.948 135.128)
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+    )
+  )
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+    (min_thickness 0.254) (filled_areas_thickness no)
+    (keepout (tracks allowed) (vias allowed) (pads allowed) (copperpour not_allowed) (footprints allowed))
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+    (polygon
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+    (keepout (tracks allowed) (vias allowed) (pads allowed) (copperpour not_allowed) (footprints allowed))
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+    (min_thickness 0.254) (filled_areas_thickness no)
+    (keepout (tracks allowed) (vias allowed) (pads allowed) (copperpour not_allowed) (footprints allowed))
+    (fill (thermal_gap 0.508) (thermal_bridge_width 0.508))
+    (polygon
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+    (connect_pads (clearance 0))
+    (min_thickness 0.254) (filled_areas_thickness no)
+    (keepout (tracks allowed) (vias allowed) (pads allowed) (copperpour not_allowed) (footprints allowed))
+    (fill (thermal_gap 0.508) (thermal_bridge_width 0.508))
+    (polygon
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+        (xy 94.107 136.779)
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+        (xy 94.488 136.398)
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+  )
+  (zone (net 0) (net_name "") (layers "In1.Cu" "In2.Cu") (tstamp 00000000-0000-0000-0000-00005f3d160e) (hatch edge 0.508)
+    (connect_pads (clearance 0))
+    (min_thickness 0.254) (filled_areas_thickness no)
+    (keepout (tracks allowed) (vias allowed) (pads allowed) (copperpour not_allowed) (footprints allowed))
+    (fill (thermal_gap 0.508) (thermal_bridge_width 0.508))
+    (polygon
+      (pts
+        (xy 86.487 134.493)
+        (xy 86.487 134.874)
+        (xy 86.868 134.874)
+        (xy 86.868 134.493)
+      )
+    )
+  )
   (zone (net 72) (net_name "+3V3") (layer "In2.Cu") (tstamp 00000000-0000-0000-0000-00005ff6ab96) (hatch edge 0.508)
     (connect_pads (clearance 0.1524))
     (min_thickness 0.1524) (filled_areas_thickness no)
diff --git a/GR8RAM.kicad_prl b/GR8RAM.kicad_prl
index 828ab63..8428f7a 100644
--- a/GR8RAM.kicad_prl
+++ b/GR8RAM.kicad_prl
@@ -3,10 +3,12 @@
     "active_layer": 0,
     "active_layer_preset": "All Layers",
     "auto_track_width": true,
+    "hidden_netclasses": [],
     "hidden_nets": [],
     "high_contrast_mode": 0,
     "net_color_mode": 1,
     "opacity": {
+      "images": 0.6,
       "pads": 1.0,
       "tracks": 1.0,
       "vias": 1.0,
@@ -38,7 +40,6 @@
       10,
       12,
       13,
-      14,
       15,
       16,
       17,
@@ -59,7 +60,9 @@
       33,
       34,
       35,
-      36
+      36,
+      39,
+      40
     ],
     "visible_layers": "fffffff_ffffffff",
     "zone_display_mode": 0
diff --git a/GR8RAM.kicad_pro b/GR8RAM.kicad_pro
index f5001aa..4936733 100644
--- a/GR8RAM.kicad_pro
+++ b/GR8RAM.kicad_pro
@@ -1,5 +1,6 @@
 {
   "board": {
+    "3dviewports": [],
     "design_settings": {
       "defaults": {
         "board_outline_line_width": 0.15,
@@ -63,20 +64,26 @@
       "rule_severities": {
         "annular_width": "error",
         "clearance": "error",
+        "connection_width": "warning",
         "copper_edge_clearance": "error",
+        "copper_sliver": "warning",
         "courtyards_overlap": "error",
         "diff_pair_gap_out_of_range": "error",
         "diff_pair_uncoupled_length_too_long": "error",
         "drill_out_of_range": "error",
         "duplicate_footprints": "warning",
         "extra_footprint": "warning",
+        "footprint": "error",
         "footprint_type_mismatch": "error",
         "hole_clearance": "error",
         "hole_near_hole": "error",
         "invalid_outline": "error",
+        "isolated_copper": "warning",
         "item_on_disabled_layer": "error",
         "items_not_allowed": "error",
         "length_out_of_range": "error",
+        "lib_footprint_issues": "warning",
+        "lib_footprint_mismatch": "warning",
         "malformed_courtyard": "error",
         "microvia_drill_out_of_range": "error",
         "missing_courtyard": "ignore",
@@ -86,9 +93,14 @@
         "padstack": "error",
         "pth_inside_courtyard": "ignore",
         "shorting_items": "error",
+        "silk_edge_clearance": "warning",
         "silk_over_copper": "warning",
         "silk_overlap": "warning",
         "skew_out_of_range": "error",
+        "solder_mask_bridge": "error",
+        "starved_thermal": "error",
+        "text_height": "warning",
+        "text_thickness": "warning",
         "through_hole_pad_without_hole": "error",
         "too_many_vias": "error",
         "track_dangling": "warning",
@@ -97,7 +109,6 @@
         "unconnected_items": "error",
         "unresolved_variable": "error",
         "via_dangling": "warning",
-        "zone_has_empty_net": "error",
         "zones_intersect": "error"
       },
       "rule_severitieslegacy_courtyards_overlap": true,
@@ -107,18 +118,63 @@
         "allow_microvias": false,
         "max_error": 0.005,
         "min_clearance": 0.0,
+        "min_connection": 0.0,
         "min_copper_edge_clearance": 0.075,
         "min_hole_clearance": 0.25,
         "min_hole_to_hole": 0.25,
         "min_microvia_diameter": 0.19999999999999998,
         "min_microvia_drill": 0.09999999999999999,
+        "min_resolved_spokes": 2,
         "min_silk_clearance": 0.0,
+        "min_text_height": 0.7999999999999999,
+        "min_text_thickness": 0.08,
         "min_through_hole_diameter": 0.19999999999999998,
         "min_track_width": 0.15,
         "min_via_annular_width": 0.049999999999999996,
         "min_via_diameter": 0.5,
+        "solder_mask_to_copper_clearance": 0.0,
         "use_height_for_length_calcs": true
       },
+      "teardrop_options": [
+        {
+          "td_allow_use_two_tracks": true,
+          "td_curve_segcount": 5,
+          "td_on_pad_in_zone": false,
+          "td_onpadsmd": true,
+          "td_onroundshapesonly": false,
+          "td_ontrackend": false,
+          "td_onviapad": true
+        }
+      ],
+      "teardrop_parameters": [
+        {
+          "td_curve_segcount": 0,
+          "td_height_ratio": 1.0,
+          "td_length_ratio": 0.5,
+          "td_maxheight": 2.0,
+          "td_maxlen": 1.0,
+          "td_target_name": "td_round_shape",
+          "td_width_to_size_filter_ratio": 0.9
+        },
+        {
+          "td_curve_segcount": 0,
+          "td_height_ratio": 1.0,
+          "td_length_ratio": 0.5,
+          "td_maxheight": 2.0,
+          "td_maxlen": 1.0,
+          "td_target_name": "td_rect_shape",
+          "td_width_to_size_filter_ratio": 0.9
+        },
+        {
+          "td_curve_segcount": 0,
+          "td_height_ratio": 1.0,
+          "td_length_ratio": 0.5,
+          "td_maxheight": 2.0,
+          "td_maxlen": 1.0,
+          "td_target_name": "td_track_end",
+          "td_width_to_size_filter_ratio": 0.9
+        }
+      ],
       "track_widths": [
         0.0,
         0.15,
@@ -165,7 +221,8 @@
       "zones_allow_external_fillets": false,
       "zones_use_no_outline": true
     },
-    "layer_presets": []
+    "layer_presets": [],
+    "viewports": []
   },
   "boards": [],
   "cvpcb": {
@@ -349,18 +406,23 @@
     "rule_severities": {
       "bus_definition_conflict": "error",
       "bus_entry_needed": "error",
-      "bus_label_syntax": "error",
       "bus_to_bus_conflict": "error",
       "bus_to_net_conflict": "error",
+      "conflicting_netclasses": "error",
       "different_unit_footprint": "error",
       "different_unit_net": "error",
       "duplicate_reference": "error",
       "duplicate_sheet_names": "error",
+      "endpoint_off_grid": "warning",
       "extra_units": "error",
       "global_label_dangling": "warning",
       "hier_label_mismatch": "error",
       "label_dangling": "error",
       "lib_symbol_issues": "warning",
+      "missing_bidi_pin": "warning",
+      "missing_input_pin": "warning",
+      "missing_power_pin": "error",
+      "missing_unit": "warning",
       "multiple_net_names": "warning",
       "net_not_bus_member": "warning",
       "no_connect_connected": "warning",
@@ -370,6 +432,7 @@
       "pin_to_pin": "warning",
       "power_pin_not_driven": "error",
       "similar_labels": "warning",
+      "simulation_model_issue": "error",
       "unannotated": "error",
       "unit_value_mismatch": "error",
       "unresolved_variable": "error",
@@ -387,7 +450,7 @@
   "net_settings": {
     "classes": [
       {
-        "bus_width": 12.0,
+        "bus_width": 12,
         "clearance": 0.15,
         "diff_pair_gap": 0.25,
         "diff_pair_via_gap": 0.25,
@@ -401,13 +464,15 @@
         "track_width": 0.15,
         "via_diameter": 0.5,
         "via_drill": 0.2,
-        "wire_width": 6.0
+        "wire_width": 6
       }
     ],
     "meta": {
-      "version": 2
+      "version": 3
     },
-    "net_colors": null
+    "net_colors": null,
+    "netclass_assignments": null,
+    "netclass_patterns": []
   },
   "pcbnew": {
     "last_paths": {
@@ -423,6 +488,8 @@
   "schematic": {
     "annotate_start_num": 0,
     "drawing": {
+      "dashed_lines_dash_length_ratio": 12.0,
+      "dashed_lines_gap_length_ratio": 3.0,
       "default_line_thickness": 6.0,
       "default_text_size": 50.0,
       "field_names": [],
@@ -454,7 +521,11 @@
     "page_layout_descr_file": "",
     "plot_directory": "",
     "spice_adjust_passive_values": false,
+    "spice_current_sheet_as_root": false,
     "spice_external_command": "spice \"%I\"",
+    "spice_model_current_sheet_as_root": true,
+    "spice_save_all_currents": false,
+    "spice_save_all_voltages": false,
     "subpart_first_id": 65,
     "subpart_id_separator": 0
   },
@@ -466,6 +537,18 @@
     [
       "00000000-0000-0000-0000-00005d4d21a0",
       "Docs"
+    ],
+    [
+      "b38206eb-cbcb-4774-86d5-3e407357811e",
+      "Bus"
+    ],
+    [
+      "5e16a16a-d8a6-4780-b76e-bb404ed87b79",
+      "FPGA"
+    ],
+    [
+      "8ff39fed-057b-492d-8c59-5abc49c84644",
+      "Power"
     ]
   ],
   "text_variables": {}
diff --git a/GR8RAM.kicad_sch b/GR8RAM.kicad_sch
index 40f7782..be068cc 100644
--- a/GR8RAM.kicad_sch
+++ b/GR8RAM.kicad_sch
@@ -1,4 +1,4 @@
-(kicad_sch (version 20211123) (generator eeschema)
+(kicad_sch (version 20230121) (generator eeschema)
 
   (uuid a29f8df0-3fae-4edf-8d9c-bd5a875b13e3)
 
@@ -13,42 +13,42 @@
 
   (lib_symbols
     (symbol "Connector:USB_B_Micro" (pin_names (offset 1.016)) (in_bom yes) (on_board yes)
-      (property "Reference" "J" (id 0) (at -5.08 11.43 0)
+      (property "Reference" "J" (at -5.08 11.43 0)
         (effects (font (size 1.27 1.27)) (justify left))
       )
-      (property "Value" "USB_B_Micro" (id 1) (at -5.08 8.89 0)
+      (property "Value" "USB_B_Micro" (at -5.08 8.89 0)
         (effects (font (size 1.27 1.27)) (justify left))
       )
-      (property "Footprint" "" (id 2) (at 3.81 -1.27 0)
+      (property "Footprint" "" (at 3.81 -1.27 0)
         (effects (font (size 1.27 1.27)) hide)
       )
-      (property "Datasheet" "~" (id 3) (at 3.81 -1.27 0)
+      (property "Datasheet" "~" (at 3.81 -1.27 0)
         (effects (font (size 1.27 1.27)) hide)
       )
-      (property "ki_keywords" "connector USB micro" (id 4) (at 0 0 0)
+      (property "ki_keywords" "connector USB micro" (at 0 0 0)
         (effects (font (size 1.27 1.27)) hide)
       )
-      (property "ki_description" "USB Micro Type B connector" (id 5) (at 0 0 0)
+      (property "ki_description" "USB Micro Type B connector" (at 0 0 0)
         (effects (font (size 1.27 1.27)) hide)
       )
-      (property "ki_fp_filters" "USB*" (id 6) (at 0 0 0)
+      (property "ki_fp_filters" "USB*" (at 0 0 0)
         (effects (font (size 1.27 1.27)) hide)
       )
       (symbol "USB_B_Micro_0_1"
         (rectangle (start -5.08 -7.62) (end 5.08 7.62)
-          (stroke (width 0.254) (type default) (color 0 0 0 0))
+          (stroke (width 0.254) (type default))
           (fill (type background))
         )
         (circle (center -3.81 2.159) (radius 0.635)
-          (stroke (width 0.254) (type default) (color 0 0 0 0))
+          (stroke (width 0.254) (type default))
           (fill (type outline))
         )
         (circle (center -0.635 3.429) (radius 0.381)
-          (stroke (width 0.254) (type default) (color 0 0 0 0))
+          (stroke (width 0.254) (type default))
           (fill (type outline))
         )
         (rectangle (start -0.127 -7.62) (end 0.127 -6.858)
-          (stroke (width 0) (type default) (color 0 0 0 0))
+          (stroke (width 0) (type default))
           (fill (type none))
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         (polyline
@@ -56,7 +56,7 @@
             (xy -1.905 2.159)
             (xy 0.635 2.159)
           )
-          (stroke (width 0.254) (type default) (color 0 0 0 0))
+          (stroke (width 0.254) (type default))
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@@ -66,7 +66,7 @@
             (xy -1.27 3.429)
             (xy -0.635 3.429)
           )
-          (stroke (width 0.254) (type default) (color 0 0 0 0))
+          (stroke (width 0.254) (type default))
           (fill (type none))
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         (polyline
@@ -76,7 +76,7 @@
             (xy -1.27 0.889)
             (xy 0 0.889)
           )
-          (stroke (width 0.254) (type default) (color 0 0 0 0))
+          (stroke (width 0.254) (type default))
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@@ -86,7 +86,7 @@
             (xy 1.905 2.159)
             (xy 0.635 2.794)
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-          (stroke (width 0.254) (type default) (color 0 0 0 0))
+          (stroke (width 0.254) (type default))
           (fill (type outline))
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         (polyline
@@ -97,7 +97,7 @@
             (xy -4.064 4.826)
             (xy -4.318 5.588)
           )
-          (stroke (width 0) (type default) (color 0 0 0 0))
+          (stroke (width 0) (type default))
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         (polyline
@@ -112,27 +112,27 @@
             (xy -1.397 5.842)
             (xy -4.699 5.842)
           )
-          (stroke (width 0) (type default) (color 0 0 0 0))
+          (stroke (width 0) (type default))
           (fill (type none))
         )
         (rectangle (start 0.254 1.27) (end -0.508 0.508)
-          (stroke (width 0.254) (type default) (color 0 0 0 0))
+          (stroke (width 0.254) (type default))
           (fill (type outline))
         )
         (rectangle (start 5.08 -5.207) (end 4.318 -4.953)
-          (stroke (width 0) (type default) (color 0 0 0 0))
+          (stroke (width 0) (type default))
           (fill (type none))
         )
         (rectangle (start 5.08 -2.667) (end 4.318 -2.413)
-          (stroke (width 0) (type default) (color 0 0 0 0))
+          (stroke (width 0) (type default))
           (fill (type none))
         )
         (rectangle (start 5.08 -0.127) (end 4.318 0.127)
-          (stroke (width 0) (type default) (color 0 0 0 0))
+          (stroke (width 0) (type default))
           (fill (type none))
         )
         (rectangle (start 5.08 4.953) (end 4.318 5.207)
-          (stroke (width 0) (type default) (color 0 0 0 0))
+          (stroke (width 0) (type default))
           (fill (type none))
         )
       )
@@ -164,70 +164,70 @@
       )
     )
     (symbol "Connector_Generic:Conn_02x05_Odd_Even" (pin_names (offset 1.016) hide) (in_bom yes) (on_board yes)
-      (property "Reference" "J" (id 0) (at 1.27 7.62 0)
+      (property "Reference" "J" (at 1.27 7.62 0)
         (effects (font (size 1.27 1.27)))
       )
-      (property "Value" "Conn_02x05_Odd_Even" (id 1) (at 1.27 -7.62 0)
+      (property "Value" "Conn_02x05_Odd_Even" (at 1.27 -7.62 0)
         (effects (font (size 1.27 1.27)))
       )
-      (property "Footprint" "" (id 2) (at 0 0 0)
+      (property "Footprint" "" (at 0 0 0)
         (effects (font (size 1.27 1.27)) hide)
       )
-      (property "Datasheet" "~" (id 3) (at 0 0 0)
+      (property "Datasheet" "~" (at 0 0 0)
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@@ -1785,30 +1785,30 @@
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-      (property "Footprint" "Package_SO:SOIC-16_3.9x9.9mm_P1.27mm" (id 2) (at 1.27 -13.97 0)
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-      (property "ki_description" "USB serial converter, UART, SOIC-16" (id 5) (at 0 0 0)
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-      (property "ki_fp_filters" "SOIC*3.9x9.9mm*P1.27mm*" (id 6) (at 0 0 0)
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@@ -1880,88 +1880,88 @@
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         (effects (font (size 1.27 1.27)) hide)
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@@ -1973,34 +1973,34 @@
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     (effects (font (size 1.27 1.27)) (justify right bottom))
     (uuid f6c644f4-3036-41a6-9e14-2c08c079c6cd)
   )
-  (label "R~{IOSTRB}" (at 95.25 123.19 180)
+  (label "R~{IOSTRB}" (at 95.25 377.19 180) (fields_autoplaced)
     (effects (font (size 1.27 1.27)) (justify right bottom))
     (uuid f6dcb5b4-0971-448a-b9ab-6db37a750704)
   )
-  (label "S~{CAS}" (at 198.12 107.95 0)
+  (label "S~{CAS}" (at 198.12 361.95 0) (fields_autoplaced)
     (effects (font (size 1.27 1.27)) (justify left bottom))
     (uuid f73b5500-6337-4860-a114-6e307f65ec9f)
   )
-  (label "TCK" (at 36.83 144.78 180)
+  (label "TCK" (at 36.83 398.78 180) (fields_autoplaced)
     (effects (font (size 1.27 1.27)) (justify right bottom))
     (uuid f835e0f4-2b7c-4e87-ba7a-f599e812d67c)
   )
-  (label "A11" (at 35.56 82.55 0)
+  (label "A11" (at 35.56 336.55 0) (fields_autoplaced)
     (effects (font (size 1.27 1.27)) (justify left bottom))
     (uuid f8fc38ec-0b98-40bc-ae2f-e5cc29973bca)
   )
-  (label "RA15" (at 76.2 82.55 0)
+  (label "RA15" (at 76.2 336.55 0) (fields_autoplaced)
     (effects (font (size 1.27 1.27)) (justify left bottom))
     (uuid f988d6ea-11c5-4837-b1d1-5c292ded50c6)
   )
-  (label "D0" (at 55.88 123.19 180)
+  (label "D0" (at 55.88 377.19 180) (fields_autoplaced)
     (effects (font (size 1.27 1.27)) (justify right bottom))
     (uuid f9b1563b-384a-447c-9f47-736504e995c8)
   )
-  (label "SD1" (at 95.25 130.81 180)
+  (label "SD1" (at 95.25 384.81 180) (fields_autoplaced)
     (effects (font (size 1.27 1.27)) (justify right bottom))
     (uuid fa123f6a-f365-4df0-ac29-30247b4aec2a)
   )
-  (label "TCKu" (at 218.44 93.98 0)
+  (label "TCKu" (at 218.44 347.98 0) (fields_autoplaced)
     (effects (font (size 1.27 1.27)) (justify left bottom))
     (uuid fc3230d9-7c47-401e-afdd-e7652078f921)
   )
-  (label "A8" (at 55.88 62.23 180)
+  (label "A8" (at 55.88 316.23 180) (fields_autoplaced)
     (effects (font (size 1.27 1.27)) (justify right bottom))
     (uuid fc4ad874-c922-4070-89f9-7262080469d8)
   )
-  (label "RA14" (at 90.17 110.49 0)
+  (label "RA14" (at 90.17 364.49 0) (fields_autoplaced)
     (effects (font (size 1.27 1.27)) (justify left bottom))
     (uuid fe4869dc-e96e-4bb4-a38d-2ca990635f2d)
   )
-  (label "VIDSYNC" (at 35.56 67.31 0)
+  (label "VIDSYNC" (at 35.56 321.31 0) (fields_autoplaced)
     (effects (font (size 1.27 1.27)) (justify left bottom))
     (uuid fef37e8b-0ff0-4da2-8a57-acaf19551d1a)
   )
 
-  (symbol (lib_id "Device:C_Small") (at 238.76 20.32 0) (unit 1)
-    (in_bom yes) (on_board yes)
+  (global_label "Vflash" (shape input) (at 245.11 313.69 0) (fields_autoplaced)
+    (effects (font (size 1.27 1.27)) (justify left))
+    (uuid 05e1f9b2-72bc-459a-9d82-c3932044a6df)
+    (property "Intersheetrefs" "${INTERSHEET_REFS}" (at 253.1672 313.69 0)
+      (effects (font (size 1.27 1.27)) (justify left) hide)
+    )
+  )
+
+  (symbol (lib_id "Device:C_Small") (at 238.76 274.32 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 00000000-0000-0000-0000-00005cc13929)
-    (property "Reference" "C11" (id 0) (at 240.03 19.05 0)
+    (property "Reference" "C11" (at 240.03 273.05 0)
       (effects (font (size 1.27 1.27)) (justify left))
     )
-    (property "Value" "10u" (id 1) (at 240.03 21.59 0)
+    (property "Value" "10u" (at 240.03 275.59 0)
       (effects (font (size 1.27 1.27)) (justify left))
     )
-    (property "Footprint" "stdpads:C_0805" (id 2) (at 238.76 20.32 0)
+    (property "Footprint" "stdpads:C_0805" (at 238.76 274.32 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "~" (id 3) (at 238.76 20.32 0)
+    (property "Datasheet" "~" (at 238.76 274.32 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "LCSC Part" "C15850" (id 4) (at 238.76 20.32 0)
+    (property "LCSC Part" "C15850" (at 238.76 274.32 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid a0695738-7af6-419e-8116-01442839aacb))
     (pin "2" (uuid dc2ae10b-7309-4ed2-baee-9111e5e1cbc9))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "C11") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "Connector_Generic:Conn_02x25_Counter_Clockwise") (at 30.48 82.55 180) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "Connector_Generic:Conn_02x25_Counter_Clockwise") (at 30.48 336.55 180) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 00000000-0000-0000-0000-00005cfc517d)
-    (property "Reference" "J1" (id 0) (at 29.21 49.53 0))
-    (property "Value" "AppleIIBus" (id 1) (at 29.21 115.57 0))
-    (property "Footprint" "stdpads:AppleIIBus_Edge" (id 2) (at 30.48 82.55 0)
+    (property "Reference" "J1" (at 29.21 303.53 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Value" "AppleIIBus" (at 29.21 369.57 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Footprint" "stdpads:AppleIIBus_Edge" (at 30.48 336.55 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "~" (id 3) (at 30.48 82.55 0)
+    (property "Datasheet" "~" (at 30.48 336.55 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid 9ff5177b-4bfb-4aae-a415-94e6368c412a))
@@ -5756,157 +5927,230 @@
     (pin "7" (uuid 22092cce-d385-4bb7-a697-ead1917d943f))
     (pin "8" (uuid 5685e99e-ba7e-4c8d-a3d8-8fe2d18b6a06))
     (pin "9" (uuid b82eac96-548e-4330-8147-4c032a9779e8))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "J1") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "power:-12V") (at 22.86 69.85 90) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "power:-12V") (at 22.86 323.85 90) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 00000000-0000-0000-0000-00005cfeec44)
-    (property "Reference" "#PWR0102" (id 0) (at 20.32 69.85 0)
+    (property "Reference" "#PWR0102" (at 20.32 323.85 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Value" "-12V" (id 1) (at 20.32 69.85 90)
+    (property "Value" "-12V" (at 20.32 323.85 90)
       (effects (font (size 1.27 1.27)) (justify left))
     )
-    (property "Footprint" "" (id 2) (at 22.86 69.85 0)
+    (property "Footprint" "" (at 22.86 323.85 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "" (id 3) (at 22.86 69.85 0)
+    (property "Datasheet" "" (at 22.86 323.85 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid d9f2cfc8-d883-4942-b0f7-7f5925afaaa3))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "#PWR0102") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "power:-5V") (at 22.86 72.39 90) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "power:-5V") (at 22.86 326.39 90) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 00000000-0000-0000-0000-00005cfefece)
-    (property "Reference" "#PWR0101" (id 0) (at 20.32 72.39 0)
+    (property "Reference" "#PWR0101" (at 20.32 326.39 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Value" "-5V" (id 1) (at 20.32 72.39 90)
+    (property "Value" "-5V" (at 20.32 326.39 90)
       (effects (font (size 1.27 1.27)) (justify left))
     )
-    (property "Footprint" "" (id 2) (at 22.86 72.39 0)
+    (property "Footprint" "" (at 22.86 326.39 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "" (id 3) (at 22.86 72.39 0)
+    (property "Datasheet" "" (at 22.86 326.39 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid 914358ab-9943-4c36-80c6-af02d9fa347e))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "#PWR0101") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "power:GND") (at 22.86 52.07 270) (mirror x) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "power:GND") (at 22.86 306.07 270) (mirror x) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 00000000-0000-0000-0000-00005d11fea8)
-    (property "Reference" "#PWR0108" (id 0) (at 16.51 52.07 0)
+    (property "Reference" "#PWR0108" (at 16.51 306.07 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Value" "GND" (id 1) (at 17.78 52.07 90))
-    (property "Footprint" "" (id 2) (at 22.86 52.07 0)
+    (property "Value" "GND" (at 17.78 306.07 90)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Footprint" "" (at 22.86 306.07 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "" (id 3) (at 22.86 52.07 0)
+    (property "Datasheet" "" (at 22.86 306.07 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid bdea12a2-2bc1-4239-be1f-49df65c20ec0))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "#PWR0108") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "Device:C_Small") (at 133.35 186.69 0) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "Device:C_Small") (at 133.35 440.69 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 00000000-0000-0000-0000-00005d12ab6d)
-    (property "Reference" "C3" (id 0) (at 134.62 185.42 0)
+    (property "Reference" "C3" (at 134.62 439.42 0)
       (effects (font (size 1.27 1.27)) (justify left))
     )
-    (property "Value" "10u" (id 1) (at 134.62 187.96 0)
+    (property "Value" "10u" (at 134.62 441.96 0)
       (effects (font (size 1.27 1.27)) (justify left))
     )
-    (property "Footprint" "stdpads:C_0805" (id 2) (at 133.35 186.69 0)
+    (property "Footprint" "stdpads:C_0805" (at 133.35 440.69 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "~" (id 3) (at 133.35 186.69 0)
+    (property "Datasheet" "~" (at 133.35 440.69 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "LCSC Part" "C15850" (id 4) (at 133.35 186.69 0)
+    (property "LCSC Part" "C15850" (at 133.35 440.69 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid 889b7988-1077-42f7-83aa-edd157867819))
     (pin "2" (uuid e79f0671-f01d-45ed-880e-82be7512c2d1))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "C3") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "power:-5V") (at 133.35 189.23 180) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "power:-5V") (at 133.35 443.23 180) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 00000000-0000-0000-0000-00005d12d2df)
-    (property "Reference" "#PWR0112" (id 0) (at 133.35 191.77 0)
+    (property "Reference" "#PWR0112" (at 133.35 445.77 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Value" "-5V" (id 1) (at 133.35 193.04 0))
-    (property "Footprint" "" (id 2) (at 133.35 189.23 0)
+    (property "Value" "-5V" (at 133.35 447.04 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Footprint" "" (at 133.35 443.23 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "" (id 3) (at 133.35 189.23 0)
+    (property "Datasheet" "" (at 133.35 443.23 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid 43d45407-1872-4d43-a661-973a38a988da))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "#PWR0112") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "Mechanical:Fiducial") (at 16.51 199.39 0) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "Mechanical:Fiducial") (at 16.51 453.39 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 00000000-0000-0000-0000-00005d321d2b)
-    (property "Reference" "FID2" (id 0) (at 18.669 198.2216 0)
+    (property "Reference" "FID2" (at 18.669 452.2216 0)
       (effects (font (size 1.27 1.27)) (justify left))
     )
-    (property "Value" "Fiducial" (id 1) (at 18.669 200.533 0)
+    (property "Value" "Fiducial" (at 18.669 454.533 0)
       (effects (font (size 1.27 1.27)) (justify left))
     )
-    (property "Footprint" "stdpads:Fiducial" (id 2) (at 16.51 199.39 0)
+    (property "Footprint" "stdpads:Fiducial" (at 16.51 453.39 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "~" (id 3) (at 16.51 199.39 0)
+    (property "Datasheet" "~" (at 16.51 453.39 0)
       (effects (font (size 1.27 1.27)) hide)
     )
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "FID2") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "Mechanical:Fiducial") (at 31.75 194.31 0) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "Mechanical:Fiducial") (at 31.75 448.31 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 00000000-0000-0000-0000-00005d321da8)
-    (property "Reference" "FID3" (id 0) (at 33.909 193.1416 0)
+    (property "Reference" "FID3" (at 33.909 447.1416 0)
       (effects (font (size 1.27 1.27)) (justify left))
     )
-    (property "Value" "Fiducial" (id 1) (at 33.909 195.453 0)
+    (property "Value" "Fiducial" (at 33.909 449.453 0)
       (effects (font (size 1.27 1.27)) (justify left))
     )
-    (property "Footprint" "stdpads:Fiducial" (id 2) (at 31.75 194.31 0)
+    (property "Footprint" "stdpads:Fiducial" (at 31.75 448.31 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "~" (id 3) (at 31.75 194.31 0)
+    (property "Datasheet" "~" (at 31.75 448.31 0)
       (effects (font (size 1.27 1.27)) hide)
     )
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "FID3") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "power:GND") (at 128.27 184.15 0) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "power:GND") (at 128.27 438.15 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 00000000-0000-0000-0000-00005d908483)
-    (property "Reference" "#PWR0115" (id 0) (at 128.27 190.5 0)
+    (property "Reference" "#PWR0115" (at 128.27 444.5 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Value" "GND" (id 1) (at 128.27 187.96 0))
-    (property "Footprint" "" (id 2) (at 128.27 184.15 0)
+    (property "Value" "GND" (at 128.27 441.96 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Footprint" "" (at 128.27 438.15 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "" (id 3) (at 128.27 184.15 0)
+    (property "Datasheet" "" (at 128.27 438.15 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid 5bce6910-55ea-4910-b304-87259c09561e))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "#PWR0115") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "Connector_Generic:Conn_02x05_Odd_Even") (at 27.94 128.27 0) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "Connector_Generic:Conn_02x05_Odd_Even") (at 27.94 382.27 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 00000000-0000-0000-0000-00005e4199b1)
-    (property "Reference" "J2" (id 0) (at 29.21 120.65 0))
-    (property "Value" "JTAG" (id 1) (at 29.21 135.89 0))
-    (property "Footprint" "Connector:Tag-Connect_TC2050-IDC-FP_2x05_P1.27mm_Vertical" (id 2) (at 27.94 128.27 0)
+    (property "Reference" "J2" (at 29.21 374.65 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Value" "JTAG" (at 29.21 389.89 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Footprint" "Connector:Tag-Connect_TC2050-IDC-FP_2x05_P1.27mm_Vertical" (at 27.94 382.27 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "~" (id 3) (at 27.94 128.27 0)
+    (property "Datasheet" "~" (at 27.94 382.27 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid f981648a-9051-4db0-ae04-701549d3961c))
@@ -5919,118 +6163,168 @@
     (pin "7" (uuid 5162987c-ba0e-48a9-b339-be2441c4705f))
     (pin "8" (uuid 7897f435-ca2e-4185-ae83-837e505bab70))
     (pin "9" (uuid 5eb4aecd-e0df-42c4-9716-e679c869f63c))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "J2") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "Device:C_Small") (at 162.56 30.48 0) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "Device:C_Small") (at 162.56 284.48 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 00000000-0000-0000-0000-00005e680811)
-    (property "Reference" "C12" (id 0) (at 163.83 29.21 0)
+    (property "Reference" "C12" (at 163.83 283.21 0)
       (effects (font (size 1.27 1.27)) (justify left))
     )
-    (property "Value" "2u2" (id 1) (at 163.83 31.75 0)
+    (property "Value" "2u2" (at 163.83 285.75 0)
       (effects (font (size 1.27 1.27)) (justify left))
     )
-    (property "Footprint" "stdpads:C_0603" (id 2) (at 162.56 30.48 0)
+    (property "Footprint" "stdpads:C_0603" (at 162.56 284.48 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "~" (id 3) (at 162.56 30.48 0)
+    (property "Datasheet" "~" (at 162.56 284.48 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "LCSC Part" "C23630" (id 4) (at 162.56 30.48 0)
+    (property "LCSC Part" "C23630" (at 162.56 284.48 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid 2d97daf5-8313-4876-b8d6-0e364fe2f148))
     (pin "2" (uuid 9a744607-d61d-4f17-b3bc-8c366b63de19))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "C12") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "Device:C_Small") (at 143.51 181.61 0) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "Device:C_Small") (at 143.51 435.61 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 00000000-0000-0000-0000-00005e8640a9)
-    (property "Reference" "C4" (id 0) (at 144.78 180.34 0)
+    (property "Reference" "C4" (at 144.78 434.34 0)
       (effects (font (size 1.27 1.27)) (justify left))
     )
-    (property "Value" "10u" (id 1) (at 144.78 182.88 0)
+    (property "Value" "10u" (at 144.78 436.88 0)
       (effects (font (size 1.27 1.27)) (justify left))
     )
-    (property "Footprint" "stdpads:C_0805" (id 2) (at 143.51 181.61 0)
+    (property "Footprint" "stdpads:C_0805" (at 143.51 435.61 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "~" (id 3) (at 143.51 181.61 0)
+    (property "Datasheet" "~" (at 143.51 435.61 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "LCSC Part" "C15850" (id 4) (at 143.51 181.61 0)
+    (property "LCSC Part" "C15850" (at 143.51 435.61 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid 5bc4085b-1275-4275-91d1-1be3e047a6ab))
     (pin "2" (uuid 66a471df-9e27-4c02-97f6-035bd21a62a3))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "C4") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "Device:C_Small") (at 143.51 186.69 0) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "Device:C_Small") (at 143.51 440.69 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 00000000-0000-0000-0000-00005e8640ba)
-    (property "Reference" "C2" (id 0) (at 144.78 185.42 0)
+    (property "Reference" "C2" (at 144.78 439.42 0)
       (effects (font (size 1.27 1.27)) (justify left))
     )
-    (property "Value" "10u" (id 1) (at 144.78 187.96 0)
+    (property "Value" "10u" (at 144.78 441.96 0)
       (effects (font (size 1.27 1.27)) (justify left))
     )
-    (property "Footprint" "stdpads:C_0805" (id 2) (at 143.51 186.69 0)
+    (property "Footprint" "stdpads:C_0805" (at 143.51 440.69 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "~" (id 3) (at 143.51 186.69 0)
+    (property "Datasheet" "~" (at 143.51 440.69 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "LCSC Part" "C15850" (id 4) (at 143.51 186.69 0)
+    (property "LCSC Part" "C15850" (at 143.51 440.69 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid 913eb625-8010-4705-9dba-28581a25b3e0))
     (pin "2" (uuid d1c434bf-b7f0-418c-819d-86a4a535331b))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "C2") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "power:-12V") (at 143.51 189.23 0) (mirror x) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "power:-12V") (at 143.51 443.23 0) (mirror x) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 00000000-0000-0000-0000-00005e86fe3d)
-    (property "Reference" "#PWR0127" (id 0) (at 143.51 191.77 0)
+    (property "Reference" "#PWR0127" (at 143.51 445.77 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Value" "-12V" (id 1) (at 143.51 193.04 0))
-    (property "Footprint" "" (id 2) (at 143.51 189.23 0)
+    (property "Value" "-12V" (at 143.51 447.04 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Footprint" "" (at 143.51 443.23 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "" (id 3) (at 143.51 189.23 0)
+    (property "Datasheet" "" (at 143.51 443.23 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid e0b72a8b-67fb-4e7a-aded-f100d8af0ab6))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "#PWR0127") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "power:+12V") (at 143.51 179.07 0) (mirror y) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "power:+12V") (at 143.51 433.07 0) (mirror y) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 00000000-0000-0000-0000-00005e875a47)
-    (property "Reference" "#PWR0128" (id 0) (at 143.51 182.88 0)
+    (property "Reference" "#PWR0128" (at 143.51 436.88 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Value" "+12V" (id 1) (at 143.51 175.26 0))
-    (property "Footprint" "" (id 2) (at 143.51 179.07 0)
+    (property "Value" "+12V" (at 143.51 429.26 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Footprint" "" (at 143.51 433.07 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "" (id 3) (at 143.51 179.07 0)
+    (property "Datasheet" "" (at 143.51 433.07 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid f9956e6f-c3ae-49ff-9b0d-066510b0ba40))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "#PWR0128") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "GW_Logic:74245") (at 66.04 71.12 0) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "GW_Logic:74245") (at 66.04 325.12 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 00000000-0000-0000-0000-00005f3a6cfe)
-    (property "Reference" "U9" (id 0) (at 66.04 55.88 0))
-    (property "Value" "74AHC245PW" (id 1) (at 66.04 71.12 90))
-    (property "Footprint" "stdpads:TSSOP-20_4.4x6.5mm_P0.65mm" (id 2) (at 66.04 87.63 0)
+    (property "Reference" "U9" (at 66.04 309.88 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Value" "74AHC245PW" (at 66.04 325.12 90)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Footprint" "stdpads:TSSOP-20_4.4x6.5mm_P0.65mm" (at 66.04 341.63 0)
       (effects (font (size 1.27 1.27)) (justify top) hide)
     )
-    (property "Datasheet" "" (id 3) (at 66.04 68.58 0)
+    (property "Datasheet" "" (at 66.04 322.58 0)
       (effects (font (size 1.524 1.524)) hide)
     )
-    (property "LCSC Part" "C5516" (id 4) (at 66.04 71.12 0)
+    (property "LCSC Part" "C5516" (at 66.04 325.12 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid d62acfcd-78e9-48e2-8cfb-4057b64de403))
@@ -6053,20 +6347,31 @@
     (pin "7" (uuid bf5bff82-2993-4c62-8b41-21e2a1a34eab))
     (pin "8" (uuid 2108f818-6fd7-4088-b15a-befe58ba058e))
     (pin "9" (uuid e8e183ef-e20b-4007-8bc1-334764b225d3))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "U9") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "GW_Logic:74245") (at 66.04 101.6 0) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "GW_Logic:74245") (at 66.04 355.6 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 00000000-0000-0000-0000-00005f3ca754)
-    (property "Reference" "U4" (id 0) (at 66.04 86.36 0))
-    (property "Value" "74AHC245PW" (id 1) (at 66.04 101.6 90))
-    (property "Footprint" "stdpads:TSSOP-20_4.4x6.5mm_P0.65mm" (id 2) (at 66.04 118.11 0)
+    (property "Reference" "U4" (at 66.04 340.36 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Value" "74AHC245PW" (at 66.04 355.6 90)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Footprint" "stdpads:TSSOP-20_4.4x6.5mm_P0.65mm" (at 66.04 372.11 0)
       (effects (font (size 1.27 1.27)) (justify top) hide)
     )
-    (property "Datasheet" "" (id 3) (at 66.04 99.06 0)
+    (property "Datasheet" "" (at 66.04 353.06 0)
       (effects (font (size 1.524 1.524)) hide)
     )
-    (property "LCSC Part" "C5516" (id 4) (at 66.04 101.6 0)
+    (property "LCSC Part" "C5516" (at 66.04 355.6 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid e16ced8b-d26f-4435-8a0f-f0bef66c43ad))
@@ -6089,20 +6394,31 @@
     (pin "7" (uuid 5427ddc0-d96f-43bd-a5d9-b8b11c7e0a97))
     (pin "8" (uuid 171a73d0-178b-4eb4-abc7-99b18df5c0d6))
     (pin "9" (uuid 4e47e4af-bbb8-4836-acf7-ed8caa23763c))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "U4") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "GW_RAM:SDRAM-16Mx16-TSOP2-54") (at 185.42 77.47 0) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "GW_RAM:SDRAM-16Mx16-TSOP2-54") (at 185.42 331.47 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 00000000-0000-0000-0000-00005f3e609f)
-    (property "Reference" "U2" (id 0) (at 185.42 48.26 0))
-    (property "Value" "W9825" (id 1) (at 185.42 77.47 90))
-    (property "Footprint" "stdpads:TSOP-II-54_22.2x10.16mm_P0.8mm" (id 2) (at 185.42 119.38 0)
+    (property "Reference" "U2" (at 185.42 302.26 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Value" "W9825" (at 185.42 331.47 90)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Footprint" "stdpads:TSOP-II-54_22.2x10.16mm_P0.8mm" (at 185.42 373.38 0)
       (effects (font (size 1.27 1.27) italic) hide)
     )
-    (property "Datasheet" "" (id 3) (at 185.42 83.82 0)
+    (property "Datasheet" "" (at 185.42 337.82 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "LCSC Part" "C62246" (id 4) (at 185.42 77.47 0)
+    (property "LCSC Part" "C62246" (at 185.42 331.47 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid f4d1b110-55bd-41b0-a39c-5dabf4472eb2))
@@ -6158,375 +6474,540 @@
     (pin "7" (uuid 86b22f09-59ca-4a8d-81ce-f44eea393466))
     (pin "8" (uuid d926ac38-d11c-4d9e-978c-95fd4122b466))
     (pin "9" (uuid 47d0e121-9040-4b4c-9cb2-92cb3ddca634))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "U2") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "power:+3V3") (at 172.72 52.07 0) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "power:+3V3") (at 172.72 306.07 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 00000000-0000-0000-0000-00005f3e79b8)
-    (property "Reference" "#PWR0151" (id 0) (at 172.72 55.88 0)
+    (property "Reference" "#PWR0151" (at 172.72 309.88 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Value" "+3V3" (id 1) (at 172.72 48.26 0))
-    (property "Footprint" "" (id 2) (at 172.72 52.07 0)
+    (property "Value" "+3V3" (at 172.72 302.26 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Footprint" "" (at 172.72 306.07 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "" (id 3) (at 172.72 52.07 0)
+    (property "Datasheet" "" (at 172.72 306.07 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid a234104b-29ee-46dd-b1c7-a7162f374fcf))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "#PWR0151") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "power:+3V3") (at 76.2 59.69 0) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "power:+3V3") (at 76.2 313.69 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 00000000-0000-0000-0000-00005f3fdcf2)
-    (property "Reference" "#PWR0117" (id 0) (at 76.2 63.5 0)
+    (property "Reference" "#PWR0117" (at 76.2 317.5 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Value" "+3V3" (id 1) (at 73.66 55.88 0))
-    (property "Footprint" "" (id 2) (at 76.2 59.69 0)
+    (property "Value" "+3V3" (at 73.66 309.88 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Footprint" "" (at 76.2 313.69 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "" (id 3) (at 76.2 59.69 0)
+    (property "Datasheet" "" (at 76.2 313.69 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid 1b9e0624-2feb-4d8b-9181-d73925756ba3))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "#PWR0117") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "power:+3V3") (at 76.2 90.17 0) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "power:+3V3") (at 76.2 344.17 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 00000000-0000-0000-0000-00005f3fe31a)
-    (property "Reference" "#PWR0116" (id 0) (at 76.2 93.98 0)
+    (property "Reference" "#PWR0116" (at 76.2 347.98 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Value" "+3V3" (id 1) (at 76.2 86.36 0))
-    (property "Footprint" "" (id 2) (at 76.2 90.17 0)
+    (property "Value" "+3V3" (at 76.2 340.36 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Footprint" "" (at 76.2 344.17 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "" (id 3) (at 76.2 90.17 0)
+    (property "Datasheet" "" (at 76.2 344.17 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid e82faff1-b691-4551-94bb-116aeaab8477))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "#PWR0116") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "power:GND") (at 55.88 82.55 0) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "power:GND") (at 55.88 336.55 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 00000000-0000-0000-0000-00005f3fe8f9)
-    (property "Reference" "#PWR0114" (id 0) (at 55.88 88.9 0)
+    (property "Reference" "#PWR0114" (at 55.88 342.9 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Value" "GND" (id 1) (at 55.88 86.36 0))
-    (property "Footprint" "" (id 2) (at 55.88 82.55 0)
+    (property "Value" "GND" (at 55.88 340.36 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Footprint" "" (at 55.88 336.55 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "" (id 3) (at 55.88 82.55 0)
+    (property "Datasheet" "" (at 55.88 336.55 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid f1af136d-fc23-40d6-9ece-115c567a709f))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "#PWR0114") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "power:GND") (at 55.88 113.03 0) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "power:GND") (at 55.88 367.03 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 00000000-0000-0000-0000-00005f3fed6f)
-    (property "Reference" "#PWR0106" (id 0) (at 55.88 119.38 0)
+    (property "Reference" "#PWR0106" (at 55.88 373.38 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Value" "GND" (id 1) (at 55.88 116.84 0))
-    (property "Footprint" "" (id 2) (at 55.88 113.03 0)
+    (property "Value" "GND" (at 55.88 370.84 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Footprint" "" (at 55.88 367.03 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "" (id 3) (at 55.88 113.03 0)
+    (property "Datasheet" "" (at 55.88 367.03 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid 85efdcf2-b2af-4074-a8ec-46a9b78ab437))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "#PWR0106") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "power:GND") (at 172.72 110.49 0) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "power:GND") (at 172.72 364.49 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 00000000-0000-0000-0000-00005f400f2c)
-    (property "Reference" "#PWR0152" (id 0) (at 172.72 116.84 0)
+    (property "Reference" "#PWR0152" (at 172.72 370.84 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Value" "GND" (id 1) (at 172.72 114.3 0))
-    (property "Footprint" "" (id 2) (at 172.72 110.49 0)
+    (property "Value" "GND" (at 172.72 368.3 0)
+      (effects (font (size 1.27 1.27)))
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+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "H3") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "GW_Logic:74245") (at 66.04 40.64 0) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "GW_Logic:74245") (at 66.04 294.64 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 00000000-0000-0000-0000-00005f5039e1)
-    (property "Reference" "U5" (id 0) (at 66.04 25.4 0))
-    (property "Value" "74AHC245PW" (id 1) (at 66.04 40.64 90))
-    (property "Footprint" "stdpads:TSSOP-20_4.4x6.5mm_P0.65mm" (id 2) (at 66.04 57.15 0)
+    (property "Reference" "U5" (at 66.04 279.4 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Value" "74AHC245PW" (at 66.04 294.64 90)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Footprint" "stdpads:TSSOP-20_4.4x6.5mm_P0.65mm" (at 66.04 311.15 0)
       (effects (font (size 1.27 1.27)) (justify top) hide)
     )
-    (property "Datasheet" "" (id 3) (at 66.04 38.1 0)
+    (property "Datasheet" "" (at 66.04 292.1 0)
       (effects (font (size 1.524 1.524)) hide)
     )
-    (property "LCSC Part" "C5516" (id 4) (at 66.04 40.64 0)
+    (property "LCSC Part" "C5516" (at 66.04 294.64 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid 9be2511d-ade2-4226-92b7-3aaaf18f4666))
@@ -6549,100 +7030,156 @@
     (pin "7" (uuid 178bb273-5a55-4b3d-8fce-d62581bd2b81))
     (pin "8" (uuid b6b5d245-df61-4abd-8a5e-4327b4e28372))
     (pin "9" (uuid bf3377ce-92eb-435f-aeed-d28c36d72737))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "U5") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "power:+5V") (at 35.56 52.07 0) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "power:+5V") (at 35.56 306.07 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 00000000-0000-0000-0000-00005f518eba)
-    (property "Reference" "#PWR0105" (id 0) (at 35.56 55.88 0)
+    (property "Reference" "#PWR0105" (at 35.56 309.88 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Value" "+5V" (id 1) (at 35.56 48.26 0))
-    (property "Footprint" "" (id 2) (at 35.56 52.07 0)
+    (property "Value" "+5V" (at 35.56 302.26 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Footprint" "" (at 35.56 306.07 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "" (id 3) (at 35.56 52.07 0)
+    (property "Datasheet" "" (at 35.56 306.07 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid 914c5b3a-21b5-462d-8f55-ca0b3cc81d2e))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "#PWR0105") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "power:+3V3") (at 76.2 29.21 0) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "power:+3V3") (at 76.2 283.21 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 00000000-0000-0000-0000-00005f7523bc)
-    (property "Reference" "#PWR0118" (id 0) (at 76.2 33.02 0)
+    (property "Reference" "#PWR0118" (at 76.2 287.02 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Value" "+3V3" (id 1) (at 76.2 25.4 0))
-    (property "Footprint" "" (id 2) (at 76.2 29.21 0)
+    (property "Value" "+3V3" (at 76.2 279.4 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Footprint" "" (at 76.2 283.21 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "" (id 3) (at 76.2 29.21 0)
+    (property "Datasheet" "" (at 76.2 283.21 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid 27efb570-bb39-4d73-adb9-f0d14b77f4de))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "#PWR0118") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "power:GND") (at 81.28 26.67 0) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "power:GND") (at 81.28 280.67 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 00000000-0000-0000-0000-00005f7669d3)
-    (property "Reference" "#PWR0119" (id 0) (at 81.28 33.02 0)
+    (property "Reference" "#PWR0119" (at 81.28 287.02 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Value" "GND" (id 1) (at 81.28 30.48 0))
-    (property "Footprint" "" (id 2) (at 81.28 26.67 0)
+    (property "Value" "GND" (at 81.28 284.48 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Footprint" "" (at 81.28 280.67 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "" (id 3) (at 81.28 26.67 0)
+    (property "Datasheet" "" (at 81.28 280.67 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid cad2873e-719f-4144-9660-5fc414d59799))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "#PWR0119") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "power:+3V3") (at 50.8 29.21 0) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "power:+3V3") (at 50.8 283.21 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 00000000-0000-0000-0000-00005f7c78ed)
-    (property "Reference" "#PWR0121" (id 0) (at 50.8 33.02 0)
+    (property "Reference" "#PWR0121" (at 50.8 287.02 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Value" "+3V3" (id 1) (at 50.8 25.4 0))
-    (property "Footprint" "" (id 2) (at 50.8 29.21 0)
+    (property "Value" "+3V3" (at 50.8 279.4 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Footprint" "" (at 50.8 283.21 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "" (id 3) (at 50.8 29.21 0)
+    (property "Datasheet" "" (at 50.8 283.21 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid d475b65c-8aff-4afb-97e1-c54e2ac8b8df))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "#PWR0121") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "power:GND") (at 55.88 52.07 0) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "power:GND") (at 55.88 306.07 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 00000000-0000-0000-0000-00005f83aa58)
-    (property "Reference" "#PWR0122" (id 0) (at 55.88 58.42 0)
+    (property "Reference" "#PWR0122" (at 55.88 312.42 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Value" "GND" (id 1) (at 55.88 55.88 0))
-    (property "Footprint" "" (id 2) (at 55.88 52.07 0)
+    (property "Value" "GND" (at 55.88 309.88 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Footprint" "" (at 55.88 306.07 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "" (id 3) (at 55.88 52.07 0)
+    (property "Datasheet" "" (at 55.88 306.07 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid dd287ecc-48c7-4569-84ef-5639ce72358e))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "#PWR0122") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "GW_Logic:74245") (at 66.04 132.08 0) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "GW_Logic:74245") (at 66.04 386.08 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 00000000-0000-0000-0000-00005fd6dfdd)
-    (property "Reference" "U6" (id 0) (at 66.04 116.84 0))
-    (property "Value" "74AHC245PW" (id 1) (at 66.04 132.08 90))
-    (property "Footprint" "stdpads:TSSOP-20_4.4x6.5mm_P0.65mm" (id 2) (at 66.04 148.59 0)
+    (property "Reference" "U6" (at 66.04 370.84 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Value" "74AHC245PW" (at 66.04 386.08 90)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Footprint" "stdpads:TSSOP-20_4.4x6.5mm_P0.65mm" (at 66.04 402.59 0)
       (effects (font (size 1.27 1.27)) (justify top) hide)
     )
-    (property "Datasheet" "" (id 3) (at 66.04 129.54 0)
+    (property "Datasheet" "" (at 66.04 383.54 0)
       (effects (font (size 1.524 1.524)) hide)
     )
-    (property "LCSC Part" "C5516" (id 4) (at 66.04 132.08 0)
+    (property "LCSC Part" "C5516" (at 66.04 386.08 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid 6d6ba75b-1862-4e3b-9547-9c8624ed35d7))
@@ -6665,117 +7202,180 @@
     (pin "7" (uuid 07b460de-371b-40e0-90f0-93226a458746))
     (pin "8" (uuid 9b222da4-70a1-43e3-bfee-4b3715b4e51c))
     (pin "9" (uuid 8f84dd96-de49-4917-98a1-dcaa5ccefa9d))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "U6") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "power:+3V3") (at 76.2 120.65 0) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "power:+3V3") (at 76.2 374.65 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 00000000-0000-0000-0000-00005fd6f855)
-    (property "Reference" "#PWR0123" (id 0) (at 76.2 124.46 0)
+    (property "Reference" "#PWR0123" (at 76.2 378.46 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Value" "+3V3" (id 1) (at 76.2 116.84 0))
-    (property "Footprint" "" (id 2) (at 76.2 120.65 0)
+    (property "Value" "+3V3" (at 76.2 370.84 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Footprint" "" (at 76.2 374.65 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "" (id 3) (at 76.2 120.65 0)
+    (property "Datasheet" "" (at 76.2 374.65 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid c7e381d8-ee41-45c6-90eb-5d8a70d113f4))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "#PWR0123") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "power:GND") (at 53.34 143.51 0) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "power:GND") (at 53.34 397.51 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 00000000-0000-0000-0000-00005fd721d9)
-    (property "Reference" "#PWR0126" (id 0) (at 53.34 149.86 0)
+    (property "Reference" "#PWR0126" (at 53.34 403.86 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Value" "GND" (id 1) (at 53.34 147.32 0))
-    (property "Footprint" "" (id 2) (at 53.34 143.51 0)
+    (property "Value" "GND" (at 53.34 401.32 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Footprint" "" (at 53.34 397.51 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "" (id 3) (at 53.34 143.51 0)
+    (property "Datasheet" "" (at 53.34 397.51 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid fa579a4b-0a1e-45bd-8ebd-0fe5f24110b3))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "#PWR0126") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "power:GND") (at 81.28 57.15 0) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "power:GND") (at 81.28 311.15 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 00000000-0000-0000-0000-00005fe804c8)
-    (property "Reference" "#PWR0107" (id 0) (at 81.28 63.5 0)
+    (property "Reference" "#PWR0107" (at 81.28 317.5 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Value" "GND" (id 1) (at 81.28 60.96 0))
-    (property "Footprint" "" (id 2) (at 81.28 57.15 0)
+    (property "Value" "GND" (at 81.28 314.96 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Footprint" "" (at 81.28 311.15 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "" (id 3) (at 81.28 57.15 0)
+    (property "Datasheet" "" (at 81.28 311.15 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid fc2e6937-75ad-4c5e-862d-3bdf44129aa7))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "#PWR0107") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "power:GND") (at 81.28 87.63 0) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "power:GND") (at 81.28 341.63 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 00000000-0000-0000-0000-00005fea8027)
-    (property "Reference" "#PWR0113" (id 0) (at 81.28 93.98 0)
+    (property "Reference" "#PWR0113" (at 81.28 347.98 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Value" "GND" (id 1) (at 81.28 91.44 0))
-    (property "Footprint" "" (id 2) (at 81.28 87.63 0)
+    (property "Value" "GND" (at 81.28 345.44 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Footprint" "" (at 81.28 341.63 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "" (id 3) (at 81.28 87.63 0)
+    (property "Datasheet" "" (at 81.28 341.63 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid 327dfcfa-f52d-4951-82e8-820abf17d1b1))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "#PWR0113") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "power:GND") (at 17.78 30.48 0) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "power:GND") (at 17.78 284.48 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 00000000-0000-0000-0000-00005ff3d1f3)
-    (property "Reference" "#PWR0109" (id 0) (at 17.78 36.83 0)
+    (property "Reference" "#PWR0109" (at 17.78 290.83 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Value" "GND" (id 1) (at 17.78 34.29 0))
-    (property "Footprint" "" (id 2) (at 17.78 30.48 0)
+    (property "Value" "GND" (at 17.78 288.29 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Footprint" "" (at 17.78 284.48 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "" (id 3) (at 17.78 30.48 0)
+    (property "Datasheet" "" (at 17.78 284.48 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid d0bc009c-d82a-462e-93a3-53eae1df5f45))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "#PWR0109") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "Mechanical:MountingHole") (at 33.02 33.02 0) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "Mechanical:MountingHole") (at 33.02 287.02 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 00000000-0000-0000-0000-00005ff3d1f9)
-    (property "Reference" "H6" (id 0) (at 35.56 33.02 0)
+    (property "Reference" "H6" (at 35.56 287.02 0)
       (effects (font (size 1.27 1.27)) (justify left))
     )
-    (property "Value" " " (id 1) (at 35.56 34.036 0)
+    (property "Value" " " (at 35.56 288.036 0)
       (effects (font (size 1.27 1.27)) (justify left))
     )
-    (property "Footprint" "stdpads:PasteHole_1.152mm_NPTH" (id 2) (at 33.02 33.02 0)
+    (property "Footprint" "stdpads:PasteHole_1.152mm_NPTH" (at 33.02 287.02 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "~" (id 3) (at 33.02 33.02 0)
+    (property "Datasheet" "~" (at 33.02 287.02 0)
       (effects (font (size 1.27 1.27)) hide)
     )
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "H6") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "GW_RAM:SPIFlash-SO-8") (at 231.14 64.77 0) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "GW_RAM:SPIFlash-SO-8") (at 231.14 318.77 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 00000000-0000-0000-0000-00006009ebad)
-    (property "Reference" "U3" (id 0) (at 231.14 55.88 0))
-    (property "Value" "W25Q128JVSIQ" (id 1) (at 231.14 71.12 0))
-    (property "Footprint" "stdpads:SOIC-8_5.3mm" (id 2) (at 231.14 72.39 0)
+    (property "Reference" "U3" (at 231.14 309.88 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Value" "W25Q128JVSIQ" (at 231.14 325.12 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Footprint" "stdpads:SOIC-8_5.3mm" (at 231.14 326.39 0)
       (effects (font (size 1.27 1.27)) (justify top) hide)
     )
-    (property "Datasheet" "" (id 3) (at 231.14 64.77 0)
+    (property "Datasheet" "" (at 231.14 318.77 0)
       (effects (font (size 1.27 1.27)) (justify top) hide)
     )
-    (property "LCSC Part" "C164122" (id 4) (at 231.14 64.77 0)
+    (property "LCSC Part" "C164122" (at 231.14 318.77 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid fcd7587b-250b-43ce-aec7-cf368d21a790))
@@ -6786,173 +7386,236 @@
     (pin "6" (uuid 1b4ddb93-8b89-4cee-8edf-377cf41d0c0a))
     (pin "7" (uuid 06223826-442d-48ae-af5b-7e727ec15539))
     (pin "8" (uuid 00d7bdb8-e5cc-4c48-a1a8-da005ded2e3f))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "U3") (unit 1)
+        )
+      )
+    )
   )
 
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-    (pin "1" (uuid 2d984774-10c5-4a20-8f63-2c34b15b3e99))
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-
-  (symbol (lib_id "power:GND") (at 217.17 67.31 0) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "power:GND") (at 217.17 321.31 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 00000000-0000-0000-0000-0000600a3591)
-    (property "Reference" "#PWR0143" (id 0) (at 217.17 73.66 0)
+    (property "Reference" "#PWR0143" (at 217.17 327.66 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Value" "GND" (id 1) (at 217.17 71.12 0))
-    (property "Footprint" "" (id 2) (at 217.17 67.31 0)
+    (property "Value" "GND" (at 217.17 325.12 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Footprint" "" (at 217.17 321.31 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "" (id 3) (at 217.17 67.31 0)
+    (property "Datasheet" "" (at 217.17 321.31 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid 320e4724-6d2c-4fdb-8f38-e333191a5637))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "#PWR0143") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "power:GND") (at 81.28 118.11 0) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "power:GND") (at 81.28 372.11 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 00000000-0000-0000-0000-00006033a776)
-    (property "Reference" "#PWR0162" (id 0) (at 81.28 124.46 0)
+    (property "Reference" "#PWR0162" (at 81.28 378.46 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Value" "GND" (id 1) (at 81.28 121.92 0))
-    (property "Footprint" "" (id 2) (at 81.28 118.11 0)
+    (property "Value" "GND" (at 81.28 375.92 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Footprint" "" (at 81.28 372.11 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "" (id 3) (at 81.28 118.11 0)
+    (property "Datasheet" "" (at 81.28 372.11 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid b0cf295d-b814-41ea-ba36-4580ee138ec6))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "#PWR0162") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "power:+3V3") (at 50.8 90.17 0) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "power:+3V3") (at 50.8 344.17 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 00000000-0000-0000-0000-00006070cf46)
-    (property "Reference" "#PWR0134" (id 0) (at 50.8 93.98 0)
+    (property "Reference" "#PWR0134" (at 50.8 347.98 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Value" "+3V3" (id 1) (at 50.8 86.36 0))
-    (property "Footprint" "" (id 2) (at 50.8 90.17 0)
+    (property "Value" "+3V3" (at 50.8 340.36 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Footprint" "" (at 50.8 344.17 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "" (id 3) (at 50.8 90.17 0)
+    (property "Datasheet" "" (at 50.8 344.17 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid 5e0e1251-015c-4df1-8b19-0718597c2462))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "#PWR0134") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "power:+3V3") (at 35.56 161.29 0) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "power:+3V3") (at 35.56 415.29 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 00000000-0000-0000-0000-000060783041)
-    (property "Reference" "#PWR0140" (id 0) (at 35.56 165.1 0)
+    (property "Reference" "#PWR0140" (at 35.56 419.1 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Value" "+3V3" (id 1) (at 35.56 157.48 0))
-    (property "Footprint" "" (id 2) (at 35.56 161.29 0)
+    (property "Value" "+3V3" (at 35.56 411.48 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Footprint" "" (at 35.56 415.29 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "" (id 3) (at 35.56 161.29 0)
+    (property "Datasheet" "" (at 35.56 415.29 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid b20cab7f-487c-496f-a37f-94ed3e2e9e68))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "#PWR0140") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "power:GND") (at 20.32 168.91 0) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "power:GND") (at 20.32 422.91 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 00000000-0000-0000-0000-00006078304a)
-    (property "Reference" "#PWR0183" (id 0) (at 20.32 175.26 0)
+    (property "Reference" "#PWR0183" (at 20.32 429.26 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Value" "GND" (id 1) (at 20.32 172.72 0))
-    (property "Footprint" "" (id 2) (at 20.32 168.91 0)
+    (property "Value" "GND" (at 20.32 426.72 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Footprint" "" (at 20.32 422.91 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "" (id 3) (at 20.32 168.91 0)
+    (property "Datasheet" "" (at 20.32 422.91 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid c7439e90-c6b8-47b2-9d17-a06c395fe26e))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "#PWR0183") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "Device:R_Small") (at 30.48 182.88 0) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "Device:R_Small") (at 30.48 436.88 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 00000000-0000-0000-0000-0000607acb3c)
-    (property "Reference" "R28" (id 0) (at 31.75 181.61 0)
+    (property "Reference" "R28" (at 31.75 435.61 0)
       (effects (font (size 1.27 1.27)) (justify left))
     )
-    (property "Value" "10k" (id 1) (at 31.75 184.15 0)
+    (property "Value" "10k" (at 31.75 438.15 0)
       (effects (font (size 1.27 1.27)) (justify left))
     )
-    (property "Footprint" "stdpads:R_0603" (id 2) (at 30.48 182.88 0)
+    (property "Footprint" "stdpads:R_0603" (at 30.48 436.88 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "~" (id 3) (at 30.48 182.88 0)
+    (property "Datasheet" "~" (at 30.48 436.88 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "LCSC Part" "C31850" (id 4) (at 30.48 182.88 0)
+    (property "LCSC Part" "C31850" (at 30.48 436.88 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid e0620f9d-14ab-44ef-b2d9-f963a77b47d1))
     (pin "2" (uuid 2992f162-3bfb-436e-88d2-ef9157d22121))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "R28") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "Device:R_Small") (at 38.1 182.88 0) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "Device:R_Small") (at 38.1 436.88 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 00000000-0000-0000-0000-0000607ad37b)
-    (property "Reference" "R29" (id 0) (at 39.37 181.61 0)
+    (property "Reference" "R29" (at 39.37 435.61 0)
       (effects (font (size 1.27 1.27)) (justify left))
     )
-    (property "Value" "10k" (id 1) (at 39.37 184.15 0)
+    (property "Value" "10k" (at 39.37 438.15 0)
       (effects (font (size 1.27 1.27)) (justify left))
     )
-    (property "Footprint" "stdpads:R_0603" (id 2) (at 38.1 182.88 0)
+    (property "Footprint" "stdpads:R_0603" (at 38.1 436.88 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "~" (id 3) (at 38.1 182.88 0)
+    (property "Datasheet" "~" (at 38.1 436.88 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "LCSC Part" "C31850" (id 4) (at 38.1 182.88 0)
+    (property "LCSC Part" "C31850" (at 38.1 436.88 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid dfc6c58b-b2d7-478a-8280-348471912cc8))
     (pin "2" (uuid b4182176-94b4-4042-a047-ced8894735c1))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "R29") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "power:GND") (at 38.1 185.42 0) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "power:GND") (at 38.1 439.42 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 00000000-0000-0000-0000-0000607adade)
-    (property "Reference" "#PWR0161" (id 0) (at 38.1 191.77 0)
+    (property "Reference" "#PWR0161" (at 38.1 445.77 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Value" "GND" (id 1) (at 38.1 189.23 0))
-    (property "Footprint" "" (id 2) (at 38.1 185.42 0)
+    (property "Value" "GND" (at 38.1 443.23 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Footprint" "" (at 38.1 439.42 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "" (id 3) (at 38.1 185.42 0)
+    (property "Datasheet" "" (at 38.1 439.42 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid 97526e5b-f3c1-4be4-bbaf-223c60948cda))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "#PWR0161") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "Connector_Generic:Conn_02x05_Odd_Even") (at 27.94 166.37 0) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "Connector_Generic:Conn_02x05_Odd_Even") (at 27.94 420.37 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 00000000-0000-0000-0000-0000607c0f47)
-    (property "Reference" "J5" (id 0) (at 29.21 158.75 0))
-    (property "Value" "SPI" (id 1) (at 29.21 173.99 0))
-    (property "Footprint" "Connector:Tag-Connect_TC2050-IDC-FP_2x05_P1.27mm_Vertical" (id 2) (at 27.94 166.37 0)
+    (property "Reference" "J5" (at 29.21 412.75 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Value" "SPI" (at 29.21 427.99 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Footprint" "Connector:Tag-Connect_TC2050-IDC-FP_2x05_P1.27mm_Vertical" (at 27.94 420.37 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "~" (id 3) (at 27.94 166.37 0)
+    (property "Datasheet" "~" (at 27.94 420.37 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid 54b4b40d-a786-41e6-9f87-4dcc19fce6d5))
@@ -6965,929 +7628,1304 @@
     (pin "7" (uuid e109b596-defe-4fa5-8030-057b98f07ef8))
     (pin "8" (uuid 039b5e6d-01aa-4a6d-ae69-1ff629b7ab9d))
     (pin "9" (uuid 5ffe0a63-1ea9-40af-83d8-b3d2717da57e))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "J5") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "power:+5V") (at 208.28 17.78 0) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "power:+5V") (at 208.28 271.78 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 00000000-0000-0000-0000-0000607fa428)
-    (property "Reference" "#PWR0120" (id 0) (at 208.28 21.59 0)
+    (property "Reference" "#PWR0120" (at 208.28 275.59 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Value" "+5V" (id 1) (at 208.28 13.97 0))
-    (property "Footprint" "" (id 2) (at 208.28 17.78 0)
+    (property "Value" "+5V" (at 208.28 267.97 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Footprint" "" (at 208.28 271.78 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "" (id 3) (at 208.28 17.78 0)
+    (property "Datasheet" "" (at 208.28 271.78 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid 45d0be27-92b3-4bdb-8caf-0545fa02b1bd))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "#PWR0120") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "Device:C_Small") (at 246.38 30.48 0) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "Device:C_Small") (at 246.38 284.48 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 00000000-0000-0000-0000-000060865cde)
-    (property "Reference" "C5" (id 0) (at 247.65 29.21 0)
+    (property "Reference" "C5" (at 247.65 283.21 0)
       (effects (font (size 1.27 1.27)) (justify left))
     )
-    (property "Value" "2u2" (id 1) (at 247.65 31.75 0)
+    (property "Value" "2u2" (at 247.65 285.75 0)
       (effects (font (size 1.27 1.27)) (justify left))
     )
-    (property "Footprint" "stdpads:C_0603" (id 2) (at 246.38 30.48 0)
+    (property "Footprint" "stdpads:C_0603" (at 246.38 284.48 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "~" (id 3) (at 246.38 30.48 0)
+    (property "Datasheet" "~" (at 246.38 284.48 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "LCSC Part" "C23630" (id 4) (at 246.38 30.48 0)
+    (property "LCSC Part" "C23630" (at 246.38 284.48 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid 6aa6a254-6dca-4eff-802c-f8352985b98b))
     (pin "2" (uuid e8158edc-20a3-40c7-babc-1f71692cea6b))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "C5") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "power:GND") (at 246.38 33.02 0) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "power:GND") (at 246.38 287.02 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 00000000-0000-0000-0000-0000608796ed)
-    (property "Reference" "#PWR0135" (id 0) (at 246.38 39.37 0)
+    (property "Reference" "#PWR0135" (at 246.38 293.37 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Value" "GND" (id 1) (at 246.38 36.83 0))
-    (property "Footprint" "" (id 2) (at 246.38 33.02 0)
+    (property "Value" "GND" (at 246.38 290.83 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Footprint" "" (at 246.38 287.02 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "" (id 3) (at 246.38 33.02 0)
+    (property "Datasheet" "" (at 246.38 287.02 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid 1545871b-4439-4ca7-937c-38293a364c16))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "#PWR0135") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "power:GND") (at 238.76 22.86 0) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "power:GND") (at 238.76 276.86 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 00000000-0000-0000-0000-0000608bc858)
-    (property "Reference" "#PWR0145" (id 0) (at 238.76 29.21 0)
+    (property "Reference" "#PWR0145" (at 238.76 283.21 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Value" "GND" (id 1) (at 238.76 26.67 0))
-    (property "Footprint" "" (id 2) (at 238.76 22.86 0)
+    (property "Value" "GND" (at 238.76 280.67 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Footprint" "" (at 238.76 276.86 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "" (id 3) (at 238.76 22.86 0)
+    (property "Datasheet" "" (at 238.76 276.86 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid 7143a182-7a9c-425b-bad6-52a2349997b2))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "#PWR0145") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "power:GND") (at 100.33 184.15 0) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "power:GND") (at 100.33 438.15 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 00000000-0000-0000-0000-0000609b96f7)
-    (property "Reference" "#PWR0144" (id 0) (at 100.33 190.5 0)
+    (property "Reference" "#PWR0144" (at 100.33 444.5 0)
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+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 00000000-0000-0000-0000-000062d6c729)
-    (property "Reference" "#PWR0146" (id 0) (at 104.14 200.66 0)
+    (property "Reference" "#PWR0146" (at 104.14 454.66 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Value" "GND" (id 1) (at 104.14 198.12 0))
-    (property "Footprint" "" (id 2) (at 104.14 194.31 0)
+    (property "Value" "GND" (at 104.14 452.12 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Footprint" "" (at 104.14 448.31 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "" (id 3) (at 104.14 194.31 0)
+    (property "Datasheet" "" (at 104.14 448.31 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid 5ab73428-d0c8-4ba7-be53-e4ec8278507c))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "#PWR0146") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "Device:C_Small") (at 215.9 162.56 0) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "Device:C_Small") (at 215.9 416.56 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 0c8146fa-7c31-40e4-add9-e470e4586e59)
-    (property "Reference" "C17" (id 0) (at 217.17 161.29 0)
+    (property "Reference" "C17" (at 217.17 415.29 0)
       (effects (font (size 1.27 1.27)) (justify left))
     )
-    (property "Value" "2u2" (id 1) (at 217.17 163.83 0)
+    (property "Value" "2u2" (at 217.17 417.83 0)
       (effects (font (size 1.27 1.27)) (justify left))
     )
-    (property "Footprint" "stdpads:C_0603" (id 2) (at 215.9 162.56 0)
+    (property "Footprint" "stdpads:C_0603" (at 215.9 416.56 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "~" (id 3) (at 215.9 162.56 0)
+    (property "Datasheet" "~" (at 215.9 416.56 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "LCSC Part" "C23630" (id 4) (at 215.9 162.56 0)
+    (property "LCSC Part" "C23630" (at 215.9 416.56 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid e4f0c0e4-f6a1-4a84-be8a-9d4522e3c5e5))
     (pin "2" (uuid 26f42b64-9dab-4ef3-a885-d06e69f6bae7))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "C17") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "Device:C_Small") (at 220.98 147.32 0) (mirror y) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "Device:C_Small") (at 220.98 401.32 0) (mirror y) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 0db1a486-f3d1-452d-8309-75a10cca1e2b)
-    (property "Reference" "C9" (id 0) (at 218.44 146.05 0)
+    (property "Reference" "C9" (at 218.44 400.05 0)
       (effects (font (size 1.27 1.27)) (justify left))
     )
-    (property "Value" "22p" (id 1) (at 218.44 148.59 0)
+    (property "Value" "22p" (at 218.44 402.59 0)
       (effects (font (size 1.27 1.27)) (justify left))
     )
-    (property "Footprint" "stdpads:C_0603" (id 2) (at 220.98 147.32 0)
+    (property "Footprint" "stdpads:C_0603" (at 220.98 401.32 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "~" (id 3) (at 220.98 147.32 0)
+    (property "Datasheet" "~" (at 220.98 401.32 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "LCSC Part" "C1653" (id 4) (at 220.98 147.32 0)
+    (property "LCSC Part" "C1653" (at 220.98 401.32 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid c3dd8dac-d5ff-4133-8556-e5d21fd7b648))
     (pin "2" (uuid 0c64324a-ee19-4590-9e47-d8f7e87abfb6))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "C9") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "GW_Logic:74245") (at 233.68 92.71 0) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "GW_Logic:74245") (at 233.68 346.71 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 106802e7-abad-4031-b6d4-b1f144dc98b1)
-    (property "Reference" "U10" (id 0) (at 233.68 77.47 0))
-    (property "Value" "74AHC245PW" (id 1) (at 233.68 92.71 90))
-    (property "Footprint" "stdpads:TSSOP-20_4.4x6.5mm_P0.65mm" (id 2) (at 233.68 109.22 0)
+    (property "Reference" "U10" (at 233.68 331.47 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Value" "74AHC245PW" (at 233.68 346.71 90)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Footprint" "stdpads:TSSOP-20_4.4x6.5mm_P0.65mm" (at 233.68 363.22 0)
       (effects (font (size 1.27 1.27)) (justify top) hide)
     )
-    (property "Datasheet" "" (id 3) (at 233.68 90.17 0)
+    (property "Datasheet" "" (at 233.68 344.17 0)
       (effects (font (size 1.524 1.524)) hide)
     )
-    (property "LCSC Part" "C5516" (id 4) (at 233.68 92.71 0)
+    (property "LCSC Part" "C5516" (at 233.68 346.71 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid 583dda1c-c129-4c54-bcc5-5b7e134ce22f))
@@ -7910,96 +8948,166 @@
     (pin "7" (uuid 3758dab9-54f0-43e4-8e0a-b634eb2616e3))
     (pin "8" (uuid e1c11209-17d5-47a2-a0c1-994c069c1604))
     (pin "9" (uuid 4647dc0e-dafa-40cd-953c-a75e1fd5d3b8))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "U10") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "Device:C_Small") (at 210.82 147.32 0) (mirror y) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "Device:C_Small") (at 210.82 401.32 0) (mirror y) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 14fb66de-c389-4aae-9a94-faf05b965227)
-    (property "Reference" "C8" (id 0) (at 208.28 146.05 0)
+    (property "Reference" "C8" (at 208.28 400.05 0)
       (effects (font (size 1.27 1.27)) (justify left))
     )
-    (property "Value" "22p" (id 1) (at 208.28 148.59 0)
+    (property "Value" "22p" (at 208.28 402.59 0)
       (effects (font (size 1.27 1.27)) (justify left))
     )
-    (property "Footprint" "stdpads:C_0603" (id 2) (at 210.82 147.32 0)
+    (property "Footprint" "stdpads:C_0603" (at 210.82 401.32 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "~" (id 3) (at 210.82 147.32 0)
+    (property "Datasheet" "~" (at 210.82 401.32 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "LCSC Part" "C1653" (id 4) (at 210.82 147.32 0)
+    (property "LCSC Part" "C1653" (at 210.82 401.32 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid 79e8cce1-23ac-4c50-a421-88054aab74ad))
     (pin "2" (uuid 4d5f5876-a009-4f5a-bfa0-7bc78954b855))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "C8") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "power:GND") (at 251.46 104.14 0) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "power:GND") (at 251.46 358.14 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 17885acf-865a-41b7-8b06-dea12ed2273b)
-    (property "Reference" "#PWR0149" (id 0) (at 251.46 110.49 0)
+    (property "Reference" "#PWR0149" (at 251.46 364.49 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Value" "GND" (id 1) (at 251.46 107.95 0))
-    (property "Footprint" "" (id 2) (at 251.46 104.14 0)
+    (property "Value" "GND" (at 251.46 361.95 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Footprint" "" (at 251.46 358.14 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "" (id 3) (at 251.46 104.14 0)
+    (property "Datasheet" "" (at 251.46 358.14 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid 3e27d4a4-9d36-44e2-8ed5-e9d31c3b6136))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "#PWR0149") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "power:+3V3") (at 22.86 180.34 0) (mirror y) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "Transistor_FET:BSS84") (at 76.2 438.15 90) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
+    (uuid 18d7e9e2-4741-4d3e-9851-0abafe534ce4)
+    (property "Reference" "Q3" (at 76.2 429.26 90)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Value" "BSS84" (at 76.2 431.8 90)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Footprint" "Package_TO_SOT_SMD:SOT-23" (at 78.105 433.07 0)
+      (effects (font (size 1.27 1.27) italic) (justify left) hide)
+    )
+    (property "Datasheet" "http://assets.nexperia.com/documents/data-sheet/BSS84.pdf" (at 76.2 438.15 0)
+      (effects (font (size 1.27 1.27)) (justify left) hide)
+    )
+    (pin "1" (uuid d2ee7d0d-923c-43f9-a3a1-649b8bca22ff))
+    (pin "2" (uuid dc4b4c49-4784-43cd-a989-97fef8041a27))
+    (pin "3" (uuid fbdfd230-44d0-4db2-847b-a56fcbbb3d7d))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "Q3") (unit 1)
+        )
+      )
+    )
+  )
+
+  (symbol (lib_id "power:+3V3") (at 22.86 434.34 0) (mirror y) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 191864f6-4a4f-42d8-ae4c-4affeefdbc49)
-    (property "Reference" "#PWR0164" (id 0) (at 22.86 184.15 0)
+    (property "Reference" "#PWR0164" (at 22.86 438.15 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Value" "+3V3" (id 1) (at 22.86 176.53 0))
-    (property "Footprint" "" (id 2) (at 22.86 180.34 0)
+    (property "Value" "+3V3" (at 22.86 430.53 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Footprint" "" (at 22.86 434.34 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "" (id 3) (at 22.86 180.34 0)
+    (property "Datasheet" "" (at 22.86 434.34 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid 906892c3-5534-40d7-a867-e04285ef1e11))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "#PWR0164") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "Device:C_Small") (at 226.06 162.56 0) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "Device:C_Small") (at 226.06 416.56 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 1f438a81-bc9b-413e-827f-08f096a4976c)
-    (property "Reference" "C36" (id 0) (at 227.33 161.29 0)
+    (property "Reference" "C36" (at 227.33 415.29 0)
       (effects (font (size 1.27 1.27)) (justify left))
     )
-    (property "Value" "2u2" (id 1) (at 227.33 163.83 0)
+    (property "Value" "2u2" (at 227.33 417.83 0)
       (effects (font (size 1.27 1.27)) (justify left))
     )
-    (property "Footprint" "stdpads:C_0603" (id 2) (at 226.06 162.56 0)
+    (property "Footprint" "stdpads:C_0603" (at 226.06 416.56 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "~" (id 3) (at 226.06 162.56 0)
+    (property "Datasheet" "~" (at 226.06 416.56 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "LCSC Part" "C23630" (id 4) (at 226.06 162.56 0)
+    (property "LCSC Part" "C23630" (at 226.06 416.56 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid 46139d79-f468-45de-ad74-3f9f8deeb54f))
     (pin "2" (uuid 62f5ca37-22be-49b1-9fbb-87e3b481913c))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "C36") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "Connector:USB_B_Micro") (at 198.12 132.08 0) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "Connector:USB_B_Micro") (at 198.12 386.08 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 29f9bb5f-28cf-4856-b1cf-a53b814bd81c)
-    (property "Reference" "J3" (id 0) (at 198.12 120.65 0))
-    (property "Value" "microUSB" (id 1) (at 198.12 123.19 0))
-    (property "Footprint" "stdpads:USB_Micro-B_ShouHan_MicroXNJ" (id 2) (at 201.93 133.35 0)
+    (property "Reference" "J3" (at 198.12 374.65 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Value" "microUSB" (at 198.12 377.19 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Footprint" "stdpads:USB_Micro-B_ShouHan_MicroXNJ" (at 201.93 387.35 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "~" (id 3) (at 201.93 133.35 0)
+    (property "Datasheet" "~" (at 201.93 387.35 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "LCSC Part" "C404969" (id 4) (at 198.12 132.08 0)
+    (property "LCSC Part" "C404969" (at 198.12 386.08 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid 7121719e-23e3-485a-bdd7-00c7f349c417))
@@ -8008,43 +9116,57 @@
     (pin "4" (uuid 66a5de09-5c0c-46e4-a8ce-7bbaec4673c5))
     (pin "5" (uuid 3232d94a-1d4e-4385-86f2-445ee8731415))
     (pin "6" (uuid f7119886-a010-4d13-b5f5-0935fb7482db))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "J3") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "Device:R_Small") (at 226.06 124.46 0) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "Device:R_Small") (at 226.06 378.46 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 2a8041ad-07b9-4e8f-a69d-43295ae21e4e)
-    (property "Reference" "R6" (id 0) (at 224.79 123.19 0)
+    (property "Reference" "R6" (at 224.79 377.19 0)
       (effects (font (size 1.27 1.27)) (justify right))
     )
-    (property "Value" "10k" (id 1) (at 224.79 125.73 0)
+    (property "Value" "10k" (at 224.79 379.73 0)
       (effects (font (size 1.27 1.27)) (justify right))
     )
-    (property "Footprint" "stdpads:R_0603" (id 2) (at 226.06 124.46 0)
+    (property "Footprint" "stdpads:R_0603" (at 226.06 378.46 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "~" (id 3) (at 226.06 124.46 0)
+    (property "Datasheet" "~" (at 226.06 378.46 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "LCSC Part" "C25804" (id 4) (at 226.06 124.46 0)
+    (property "LCSC Part" "C25804" (at 226.06 378.46 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid ec6027e4-1b99-48b7-94c6-a4574382d527))
     (pin "2" (uuid 5dc7fff0-64c5-4425-92f5-32a059b86da8))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "R6") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "GW_PLD:LCMXO2-640-TG100") (at 119.38 102.87 0) (unit 1)
-    (in_bom yes) (on_board yes) (fields_autoplaced)
+  (symbol (lib_id "GW_PLD:LCMXO2-640-TG100") (at 119.38 356.87 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no) (fields_autoplaced)
     (uuid 2fbd2625-e248-40ce-b05e-a181a8495e84)
-    (property "Reference" "U1" (id 0) (at 133.82 161.29 0)
+    (property "Reference" "U1" (at 133.82 415.29 0)
       (effects (font (size 1.27 1.27)) (justify left))
     )
-    (property "Value" "LCMXO2-640-TG100" (id 1) (at 133.82 163.83 0)
+    (property "Value" "LCMXO2-640-TG100" (at 133.82 417.83 0)
       (effects (font (size 1.016 1.016)) (justify left))
     )
-    (property "Footprint" "stdpads:TQFP-100_14x14mm_P0.5mm" (id 2) (at 119.38 107.95 0)
+    (property "Footprint" "stdpads:TQFP-100_14x14mm_P0.5mm" (at 119.38 361.95 0)
       (effects (font (size 1.016 1.016)) hide)
     )
-    (property "Datasheet" "" (id 3) (at 119.38 100.33 0)
+    (property "Datasheet" "" (at 119.38 354.33 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid 453bf853-896d-4cd0-839c-7e2f0b39e920))
@@ -8144,284 +9266,411 @@
     (pin "97" (uuid 1b7a9970-942b-45f7-b530-d35affb1cdcd))
     (pin "98" (uuid 40a4bb11-7421-4976-a489-9725280dcd13))
     (pin "99" (uuid c678d185-044c-408b-8a00-10bfef8bb58d))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "U1") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "power:+3V3") (at 243.84 81.28 0) (mirror y) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "power:+3V3") (at 243.84 335.28 0) (mirror y) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 30af1d7e-71b2-410e-af00-1a25355e30aa)
-    (property "Reference" "#PWR0157" (id 0) (at 243.84 85.09 0)
+    (property "Reference" "#PWR0157" (at 243.84 339.09 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Value" "+3V3" (id 1) (at 243.84 77.47 0))
-    (property "Footprint" "" (id 2) (at 243.84 81.28 0)
+    (property "Value" "+3V3" (at 243.84 331.47 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Footprint" "" (at 243.84 335.28 0)
       (effects (font (size 1.27 1.27)) hide)
     )
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       (effects (font (size 1.27 1.27)) hide)
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       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid c2ec3314-a44d-4479-aee6-35a72e348616))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "#PWR0153") (unit 1)
+        )
+      )
+    )
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-  (symbol (lib_id "Interface_USB:CH340G") (at 238.76 134.62 0) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "Interface_USB:CH340G") (at 238.76 388.62 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 83e778d4-8564-4987-b157-c60bceef4a29)
-    (property "Reference" "U11" (id 0) (at 238.76 134.62 0))
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-    (property "Footprint" "stdpads:SOIC-16_3.9mm" (id 2) (at 240.03 148.59 0)
+    (property "Reference" "U11" (at 238.76 388.62 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Value" "CH340G" (at 238.76 391.16 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Footprint" "stdpads:SOIC-16_3.9mm" (at 240.03 402.59 0)
       (effects (font (size 1.27 1.27)) (justify left) hide)
     )
-    (property "Datasheet" "http://www.datasheet5.com/pdf-local-2195953" (id 3) (at 229.87 114.3 0)
+    (property "Datasheet" "http://www.datasheet5.com/pdf-local-2195953" (at 229.87 368.3 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "LCSC Part" "C14267" (id 4) (at 238.76 134.62 0)
+    (property "LCSC Part" "C14267" (at 238.76 388.62 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid f07d7600-e2c0-4a65-9f54-1c28c9309db3))
@@ -8440,339 +9689,487 @@
     (pin "7" (uuid b65658e2-2810-433f-8f87-98e92e342d4b))
     (pin "8" (uuid 631a1573-6133-429a-af6f-e35d1111be8b))
     (pin "9" (uuid 05def391-6274-4768-ab5d-c59ffa292d75))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "U11") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "power:+3V3") (at 160.02 161.29 0) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "power:+3V3") (at 160.02 415.29 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 85684abd-ca4e-4a33-8ee2-0d44c535df58)
-    (property "Reference" "#PWR0133" (id 0) (at 160.02 165.1 0)
+    (property "Reference" "#PWR0133" (at 160.02 419.1 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Value" "+3V3" (id 1) (at 160.02 157.48 0))
-    (property "Footprint" "" (id 2) (at 160.02 161.29 0)
+    (property "Value" "+3V3" (at 160.02 411.48 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Footprint" "" (at 160.02 415.29 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "" (id 3) (at 160.02 161.29 0)
+    (property "Datasheet" "" (at 160.02 415.29 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid 4343e73c-9369-49c5-9c41-d9bc11457a88))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "#PWR0133") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "Transistor_BJT:MMBT3904") (at 171.45 140.97 0) (unit 1)
-    (in_bom yes) (on_board yes) (fields_autoplaced)
+  (symbol (lib_id "Transistor_BJT:MMBT3904") (at 171.45 394.97 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no) (fields_autoplaced)
     (uuid 86475fad-be9b-4f38-918e-b4e2c0dea248)
-    (property "Reference" "Q1" (id 0) (at 176.53 139.6999 0)
+    (property "Reference" "Q1" (at 176.53 393.6999 0)
       (effects (font (size 1.27 1.27)) (justify left))
     )
-    (property "Value" "MMBT3904" (id 1) (at 176.53 142.2399 0)
+    (property "Value" "MMBT3904" (at 176.53 396.2399 0)
       (effects (font (size 1.27 1.27)) (justify left))
     )
-    (property "Footprint" "stdpads:SOT-23" (id 2) (at 176.53 142.875 0)
+    (property "Footprint" "stdpads:SOT-23" (at 176.53 396.875 0)
       (effects (font (size 1.27 1.27) italic) (justify left) hide)
     )
-    (property "Datasheet" "https://www.onsemi.com/pub/Collateral/2N3903-D.PDF" (id 3) (at 171.45 140.97 0)
+    (property "Datasheet" "https://www.onsemi.com/pub/Collateral/2N3903-D.PDF" (at 171.45 394.97 0)
       (effects (font (size 1.27 1.27)) (justify left) hide)
     )
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     (pin "2" (uuid d50231f9-660b-4983-8fcd-69bbb5b40cb4))
     (pin "3" (uuid a4e629e9-91cc-4d6d-a33c-bc0040486c2e))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "Q1") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "Device:C_Small") (at 36.83 147.32 0) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "Device:C_Small") (at 36.83 401.32 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 8678dc10-a9b8-4223-80e1-4efa6a9114c7)
-    (property "Reference" "C6" (id 0) (at 38.1 146.05 0)
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       (effects (font (size 1.27 1.27)) (justify left))
     )
-    (property "Value" "22p" (id 1) (at 38.1 148.59 0)
+    (property "Value" "22p" (at 38.1 402.59 0)
       (effects (font (size 1.27 1.27)) (justify left))
     )
-    (property "Footprint" "stdpads:C_0603" (id 2) (at 36.83 147.32 0)
+    (property "Footprint" "stdpads:C_0603" (at 36.83 401.32 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "~" (id 3) (at 36.83 147.32 0)
+    (property "Datasheet" "~" (at 36.83 401.32 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "LCSC Part" "" (id 4) (at 36.83 147.32 0)
+    (property "LCSC Part" "" (at 36.83 401.32 0)
       (effects (font (size 1.27 1.27)) hide)
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     (pin "1" (uuid 87c3a5b2-328a-4f54-8751-ba0a57a22374))
     (pin "2" (uuid 64d62154-9549-4c26-ae26-62aa5dcd36e9))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "C6") (unit 1)
+        )
+      )
+    )
   )
 
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-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "Device:R_Small") (at 251.46 373.38 0) (mirror y) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 88a2b88a-4d21-466e-98fb-3a61ec8218c6)
-    (property "Reference" "R5" (id 0) (at 252.73 118.11 0)
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       (effects (font (size 1.27 1.27)) (justify right))
     )
-    (property "Value" "10k" (id 1) (at 252.73 120.65 0)
+    (property "Value" "10k" (at 252.73 374.65 0)
       (effects (font (size 1.27 1.27)) (justify right))
     )
-    (property "Footprint" "stdpads:R_0603" (id 2) (at 251.46 119.38 0)
+    (property "Footprint" "stdpads:R_0603" (at 251.46 373.38 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "~" (id 3) (at 251.46 119.38 0)
+    (property "Datasheet" "~" (at 251.46 373.38 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "LCSC Part" "C25804" (id 4) (at 251.46 119.38 0)
+    (property "LCSC Part" "C25804" (at 251.46 373.38 0)
       (effects (font (size 1.27 1.27)) hide)
     )
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     (pin "2" (uuid 48bdd9bc-e9a4-4a82-a864-14523f22e035))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "R5") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "Device:R_Small") (at 29.21 144.78 270) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "Device:R_Small") (at 29.21 398.78 270) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 8b916b44-7f55-467f-a4f2-e3f7808df8c3)
-    (property "Reference" "R10" (id 0) (at 29.21 140.97 90))
-    (property "Value" "33" (id 1) (at 29.21 143.51 90)
+    (property "Reference" "R10" (at 29.21 394.97 90)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Value" "33" (at 29.21 397.51 90)
       (effects (font (size 1.27 1.27)) (justify bottom))
     )
-    (property "Footprint" "stdpads:R_0603" (id 2) (at 29.21 144.78 0)
+    (property "Footprint" "stdpads:R_0603" (at 29.21 398.78 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "~" (id 3) (at 29.21 144.78 0)
+    (property "Datasheet" "~" (at 29.21 398.78 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "LCSC Part" "C23140" (id 4) (at 29.21 144.78 0)
+    (property "LCSC Part" "C23140" (at 29.21 398.78 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid d0fdf193-f2b5-45c1-adfb-fa6e22e1cd86))
     (pin "2" (uuid d5148733-7cdf-46fe-b57f-855c13f455c7))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "R10") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "power:+3V3") (at 15.24 180.34 0) (mirror y) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "power:+3V3") (at 15.24 434.34 0) (mirror y) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 8e1869df-2774-436e-a9be-2f9c2d9c0e15)
-    (property "Reference" "#PWR0166" (id 0) (at 15.24 184.15 0)
+    (property "Reference" "#PWR0166" (at 15.24 438.15 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Value" "+3V3" (id 1) (at 15.24 176.53 0))
-    (property "Footprint" "" (id 2) (at 15.24 180.34 0)
+    (property "Value" "+3V3" (at 15.24 430.53 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Footprint" "" (at 15.24 434.34 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "" (id 3) (at 15.24 180.34 0)
+    (property "Datasheet" "" (at 15.24 434.34 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid c7f32efe-5776-473a-ae77-835444231694))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "#PWR0166") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "Device:R_Small") (at 173.99 130.81 0) (mirror y) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "Device:R_Small") (at 173.99 384.81 0) (mirror y) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 9b96634d-1918-4e0e-9224-9f0d3d2f9a49)
-    (property "Reference" "R7" (id 0) (at 175.26 129.54 0)
+    (property "Reference" "R7" (at 175.26 383.54 0)
       (effects (font (size 1.27 1.27)) (justify right))
     )
-    (property "Value" "10k" (id 1) (at 175.26 132.08 0)
+    (property "Value" "10k" (at 175.26 386.08 0)
       (effects (font (size 1.27 1.27)) (justify right))
     )
-    (property "Footprint" "stdpads:R_0603" (id 2) (at 173.99 130.81 0)
+    (property "Footprint" "stdpads:R_0603" (at 173.99 384.81 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "~" (id 3) (at 173.99 130.81 0)
+    (property "Datasheet" "~" (at 173.99 384.81 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "LCSC Part" "C25804" (id 4) (at 173.99 130.81 0)
+    (property "LCSC Part" "C25804" (at 173.99 384.81 0)
       (effects (font (size 1.27 1.27)) hide)
     )
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     (pin "2" (uuid 8a0fd654-7988-4050-96af-fb67075ff16d))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "R7") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "power:+3V3") (at 223.52 81.28 0) (mirror y) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "power:+3V3") (at 223.52 335.28 0) (mirror y) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid 9fcab238-8e55-4252-b189-bff3964d3be2)
-    (property "Reference" "#PWR0158" (id 0) (at 223.52 85.09 0)
+    (property "Reference" "#PWR0158" (at 223.52 339.09 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Value" "+3V3" (id 1) (at 223.52 77.47 0))
-    (property "Footprint" "" (id 2) (at 223.52 81.28 0)
+    (property "Value" "+3V3" (at 223.52 331.47 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Footprint" "" (at 223.52 335.28 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "" (id 3) (at 223.52 81.28 0)
+    (property "Datasheet" "" (at 223.52 335.28 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid 276db393-e08f-421e-a509-5ca9007666cb))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "#PWR0158") (unit 1)
+        )
+      )
+    )
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-  (symbol (lib_id "Device:R_Small") (at 22.86 182.88 0) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "Device:R_Small") (at 22.86 436.88 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid a60e8ce8-fdf3-49be-8e49-77b8870d9f63)
-    (property "Reference" "R12" (id 0) (at 24.13 181.61 0)
+    (property "Reference" "R12" (at 24.13 435.61 0)
       (effects (font (size 1.27 1.27)) (justify left))
     )
-    (property "Value" "10k" (id 1) (at 24.13 184.15 0)
+    (property "Value" "10k" (at 24.13 438.15 0)
       (effects (font (size 1.27 1.27)) (justify left))
     )
-    (property "Footprint" "stdpads:R_0603" (id 2) (at 22.86 182.88 0)
+    (property "Footprint" "stdpads:R_0603" (at 22.86 436.88 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "~" (id 3) (at 22.86 182.88 0)
+    (property "Datasheet" "~" (at 22.86 436.88 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "LCSC Part" "C31850" (id 4) (at 22.86 182.88 0)
+    (property "LCSC Part" "C31850" (at 22.86 436.88 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid b678292b-6449-4c59-935e-e228aa9c0827))
     (pin "2" (uuid 38de35db-ba54-4500-b6e0-ab8b0b73baa8))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "R12") (unit 1)
+        )
+      )
+    )
   )
 
-  (symbol (lib_id "Device:C_Small") (at 205.74 162.56 0) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "Device:C_Small") (at 205.74 416.56 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid a871a30b-1268-44b1-badb-8bd3f28f9842)
-    (property "Reference" "C39" (id 0) (at 207.01 161.29 0)
+    (property "Reference" "C39" (at 207.01 415.29 0)
       (effects (font (size 1.27 1.27)) (justify left))
     )
-    (property "Value" "2u2" (id 1) (at 207.01 163.83 0)
+    (property "Value" "2u2" (at 207.01 417.83 0)
       (effects (font (size 1.27 1.27)) (justify left))
     )
-    (property "Footprint" "stdpads:C_0603" (id 2) (at 205.74 162.56 0)
+    (property "Footprint" "stdpads:C_0603" (at 205.74 416.56 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "~" (id 3) (at 205.74 162.56 0)
+    (property "Datasheet" "~" (at 205.74 416.56 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "LCSC Part" "C23630" (id 4) (at 205.74 162.56 0)
+    (property "LCSC Part" "C23630" (at 205.74 416.56 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid 8687a17e-8dfb-469b-be69-f13b4ce6bd5f))
     (pin "2" (uuid 768b10f0-ade3-482d-9e39-c31da9d61486))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "C39") (unit 1)
+        )
+      )
+    )
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-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "power:GND") (at 173.99 400.05 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid aab4e33b-d015-4a00-aecd-58b134630312)
-    (property "Reference" "#PWR0159" (id 0) (at 173.99 152.4 0)
+    (property "Reference" "#PWR0159" (at 173.99 406.4 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Value" "GND" (id 1) (at 173.99 149.86 0))
-    (property "Footprint" "" (id 2) (at 173.99 146.05 0)
+    (property "Value" "GND" (at 173.99 403.86 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Footprint" "" (at 173.99 400.05 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" "" (id 3) (at 173.99 146.05 0)
+    (property "Datasheet" "" (at 173.99 400.05 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "1" (uuid f7d3aef8-312d-4d95-909a-ce8e047af9b6))
+    (instances
+      (project "GR8RAM"
+        (path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
+          (reference "#PWR0159") (unit 1)
+        )
+      )
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-  (symbol (lib_id "power:+3V3") (at 238.76 119.38 0) (unit 1)
-    (in_bom yes) (on_board yes)
+  (symbol (lib_id "power:+3V3") (at 238.76 373.38 0) (unit 1)
+    (in_bom yes) (on_board yes) (dnp no)
     (uuid aaf7e9a8-6967-43c0-92b8-bd3d9e464e67)
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diff --git a/Power.kicad_sch b/Power.kicad_sch
new file mode 100644
index 0000000..304a528
--- /dev/null
+++ b/Power.kicad_sch
@@ -0,0 +1,3441 @@
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diff --git a/cpld/GR8RAM.qsf b/cpld/GR8RAM.qsf
index 189a496..fa2370d 100755
--- a/cpld/GR8RAM.qsf
+++ b/cpld/GR8RAM.qsf
@@ -41,7 +41,7 @@ set_global_assignment -name DEVICE EPM240T100C5
 set_global_assignment -name TOP_LEVEL_ENTITY GR8RAM
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:41:40  MARCH 15, 2021"
-set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition"
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
diff --git a/cpld/GR8RAM.v b/cpld/GR8RAM.v
index 41dd3b5..870ace1 100644
--- a/cpld/GR8RAM.v
+++ b/cpld/GR8RAM.v
@@ -21,17 +21,9 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
 
 	/* Firmware select */
 	input [1:0] SetFW;
-	reg [1:0] SetFWr;
-	reg SetFWLoaded = 0;
-	always @(posedge C25M) begin
-		if (~SetFWLoaded) begin
-			SetFWLoaded <= 1;
-			SetFWr[1:0] <= SetFW[1:0];
-		end
-	end
-	wire [1:0] SetROM = ~SetFWr[1:0];
-	wire SetEN16MB = SetROM[1:0]==2'b11;
-	wire SetEN24bit = SetROM[1];
+	wire [1:0] SetROM = 2'b00;
+	wire SetEN16MB = 0;
+	wire SetEN24bit = 1;
 
 	/* State counter from PHI0 rising edge */
 	reg [3:0] PS = 0;
@@ -77,6 +69,8 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
 	wire ROMSpecRD = CXXXr && RAr[11:8]!=4'h0 && nWEr && ((RAr[11] && IOROMEN) || (~RAr[11]));
 	wire REGSpecSEL = CXXXr && RAr[11:8]==4'h0 && RAr[7] && REGEN;
 	wire BankSpecSEL = REGSpecSEL && RAr[3:0]==4'hF;
+	wire SPITX1SpecSEL = REGSpecSEL && RAr[3:0]==4'hD;
+	wire SPITX0SpecSEL = REGSpecSEL && RAr[3:0]==4'hC;
 	wire RAMRegSpecSEL = REGSpecSEL && RAr[3:0]==4'h3;
 	wire RAMSpecSEL = RAMRegSpecSEL && (~SetEN24bit || SetEN16MB || ~Addr[23]);
 	wire AddrHSpecSEL = REGSpecSEL && RAr[3:0]==4'h2;
@@ -153,18 +147,19 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
 
 	/* ROM bank register */
 	reg Bank = 0;
+	reg RestoreDone = 0;
 	always @(posedge C25M, negedge nRESr) begin
 		if (~nRESr) Bank <= 0;
 		else if (PS==8 && BankSEL && ~nWEr) begin
-			Bank <= RD[0];
+			if (!RestoreDone) begin
+				RestoreDone <= RD[1:0]==2'b11;
+			end else Bank <= RD[0];
 		end
 	end
-
+	
 	/* SPI flash control signals */
-	output nFCS = FCKOE ? ~FCS : 1'bZ;
-	reg FCS = 0;
-	output FCK = FCKOE ? FCKout : 1'bZ;
-	reg FCKOE = 0;
+	output reg nFCS = 1;
+	output FCK = FCKout;
 	reg FCKout = 0;
 	inout MOSI = MOSIOE ? MOSIout : 1'bZ;
 	reg MOSIOE = 0;
@@ -186,7 +181,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
 			end 6: begin // NOP CKE
 				FCKout <= 1'b1;
 			end 7: begin // NOP CKE
-				FCKout <= ~(IS==5 || IS==6);
+				FCKout <= ~(IS==5 || IS==6 || (!nDEVSEL && RestoreDone && (SPITX0SpecSEL || SPITX1SpecSEL)));
 			end 8: begin // WR AP
 				FCKout <= 1'b1;
 			end 9: begin // NOP CKE
@@ -205,9 +200,9 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
 				FCKout <= ~(IS==5);
 			end
 		endcase
-		FCS <= IS==4 || IS==5 || IS==6;
-		MOSIOE <= IS==5;
-		FCKOE <= IS==1 || IS==4 || IS==5 || IS==6 || IS==7;
+		
+		nFCS <= !(IS==4 || IS==5 || IS==6 || Bank);
+		MOSIOE <= IS==5 || IS==7;
 	end
 
 	/* SPI flash MOSI control */
@@ -218,7 +213,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
 				case (LS[2:0])
 					3'h3: MOSIout <= 1'b0; // Command bit 7
 					3'h4: MOSIout <= 1'b0; // Address bit 23
-					3'h5: MOSIout <= 1'b0; // Address bit 15
+					3'h5: MOSIout <= 1'b1; // Address bit 15
 					3'h6: MOSIout <= 1'b0; // Address bit 7
 					default MOSIout <= 1'b0;
 				endcase
@@ -239,13 +234,13 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
 					default MOSIout <= 1'b0;
 				endcase
 			end 7: begin
-				case (LS[2:0])
-					3'h3: MOSIout <= 1'b1; // Command bit 4
-					3'h4: MOSIout <= 1'b0; // Address bit 20
-					3'h5: MOSIout <= 1'b0; // Address bit 12
-					3'h6: MOSIout <= 1'b0; // Address bit 4
-					default MOSIout <= 1'b0;
-				endcase
+				if (nRES) case (LS[2:0])
+						3'h3: MOSIout <= 1'b1; // Command bit 4
+						3'h4: MOSIout <= 1'b0; // Address bit 20
+						3'h5: MOSIout <= 1'b0; // Address bit 12
+						3'h6: MOSIout <= 1'b0; // Address bit 4
+						default MOSIout <= 1'b0;
+				endcase else  MOSIout <= RAr[0];
 			end 9: begin
 				case (LS[2:0])
 					3'h3: MOSIout <= 1'b1; // Command bit 3
@@ -330,6 +325,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
 			if (AddrLSpecSEL) RDD[7:0] <= Addr[7:0];
 			else if (AddrMSpecSEL) RDD[7:0] <= Addr[15:8];
 			else if (AddrHSpecSEL) RDD[7:0] <= { SetEN24bit ? Addr[23:20] : 4'hF, Addr[19:16] };
+			else if (BankSpecSEL) RDD[7:0] <= { MISO, 7'h7F };
 			else RDD[7:0] <= SD[7:0];
 		end
 	end
@@ -454,19 +450,19 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
 				DQML <= 1'b1;
 				DQMH <= 1'b1;
 				if (IS==6) begin
-					SBA[1:0] <= { 2'b10 };
+					SBA[1:0] <= 2'b10;
 					SA[12:0] <= { 10'b0011000100, LS[12:10] };
 				end else if (RAMSpecSEL) begin
-					SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 };
+					SBA[1:0] <= { 1'b0, 1'b0 };
 					SA[12:10] <= SetEN24bit ? Addr[22:20] : 3'b000;
 					SA[9:0] <= Addr[19:10];
 				end else begin
 					SBA[1:0] <= 2'b10;
-					SA[12:0] <= { 10'b0011000100, Bank, RAr[11:10] };
+					SA[12:0] <= { 10'b0011000100, RestoreDone ? (nIOSEL ? 1'b0 : Bank) : 1'b1, RAr[11:10] };
 				end
 			end 2: begin // RD
 				if (RAMSpecSEL) begin
-					SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 };
+					SBA[1:0] <= 2'b00;
 					SA[12:0] <= { 4'b0011, Addr[9:1] };
 					DQML <= Addr[0];
 					DQMH <= ~Addr[0];
@@ -508,7 +504,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
 					DQML <= LS[0];
 					DQMH <= ~LS[0];
 				end else begin
-					SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 };
+					SBA[1:0] <= 2'b00;
 					SA[12:0] <= { 4'b0011, Addr[9:1] };
 					DQML <= Addr[0];
 					DQMH <= ~Addr[0];
diff --git a/cpld/GR8RAM_assignment_defaults.qdf b/cpld/GR8RAM_assignment_defaults.qdf
new file mode 100644
index 0000000..bb62e93
--- /dev/null
+++ b/cpld/GR8RAM_assignment_defaults.qdf
@@ -0,0 +1,808 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2019  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and any partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details, at
+# https://fpgasoftware.intel.com/eula.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+# Date created = 19:21:05  March 25, 2023
+#
+# -------------------------------------------------------------------------- #
+#
+# Note:
+#
+# 1) Do not modify this file. This file was generated
+#    automatically by the Quartus Prime software and is used
+#    to preserve global assignments across Quartus Prime versions.
+#
+# -------------------------------------------------------------------------- #
+
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+set_global_assignment -name IP_COMPONENT_INTERNAL Off
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+set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
+set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
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+set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off
+set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off
+set_global_assignment -name HC_OUTPUT_DIR hc_output
+set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
+set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
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+set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings"
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+set_global_assignment -name DEVICE_FILTER_PACKAGE Any
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+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V"
+set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
+set_global_assignment -name HDL_MESSAGE_LEVEL Level2
+set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
+set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100
+set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000
+set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000
+set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off
+set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000
+set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
+set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
+set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
+set_global_assignment -name BLOCK_DESIGN_NAMING Auto
+set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
+set_global_assignment -name SYNTHESIS_EFFORT Auto
+set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On
+set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
+set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
+set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone 10 LP"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX"
+set_global_assignment -name MAX_LABS "-1 (Unlimited)"
+set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On
+set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)"
+set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On
+set_global_assignment -name PRPOF_ID Off
+set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off
+set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On
+set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On
+set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off
+set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
+set_global_assignment -name AUTO_MERGE_PLLS On
+set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
+set_global_assignment -name TXPMA_SLEW_RATE Low
+set_global_assignment -name ADCE_ENABLED Auto
+set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
+set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off
+set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
+set_global_assignment -name PHYSICAL_SYNTHESIS Off
+set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
+set_global_assignment -name DEVICE AUTO
+set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
+set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
+set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
+set_global_assignment -name ENABLE_NCEO_OUTPUT Off
+set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
+set_global_assignment -name STRATIX_UPDATE_MODE Standard
+set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image"
+set_global_assignment -name CVP_MODE Off
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V"
+set_global_assignment -name VID_OPERATION_MODE "PMBus Slave"
+set_global_assignment -name USE_CONF_DONE AUTO
+set_global_assignment -name USE_PWRMGT_SCL AUTO
+set_global_assignment -name USE_PWRMGT_SDA AUTO
+set_global_assignment -name USE_PWRMGT_ALERT AUTO
+set_global_assignment -name USE_INIT_DONE AUTO
+set_global_assignment -name USE_CVP_CONFDONE AUTO
+set_global_assignment -name USE_SEU_ERROR AUTO
+set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name USER_START_UP_CLOCK Off
+set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off
+set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off
+set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On
+set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On
+set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC
+set_global_assignment -name ENABLE_VREFA_PIN Off
+set_global_assignment -name ENABLE_VREFB_PIN Off
+set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
+set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
+set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
+set_global_assignment -name INIT_DONE_OPEN_DRAIN On
+set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name ENABLE_CONFIGURATION_PINS On
+set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off
+set_global_assignment -name ENABLE_NCE_PIN Off
+set_global_assignment -name ENABLE_BOOT_SEL_PIN On
+set_global_assignment -name CRC_ERROR_CHECKING Off
+set_global_assignment -name INTERNAL_SCRUBBING Off
+set_global_assignment -name PR_ERROR_OPEN_DRAIN On
+set_global_assignment -name PR_READY_OPEN_DRAIN On
+set_global_assignment -name ENABLE_CVP_CONFDONE Off
+set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On
+set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone 10 LP"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone 10 LP"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V"
+set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV"
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10"
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V"
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ"
+set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
+set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
+set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
+set_global_assignment -name OPTIMIZE_SSN Off
+set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
+set_global_assignment -name ECO_OPTIMIZE_TIMING Off
+set_global_assignment -name ECO_REGENERATE_REPORT Off
+set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal
+set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
+set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
+set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
+set_global_assignment -name SEED 1
+set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF
+set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off
+set_global_assignment -name SLOW_SLEW_RATE Off
+set_global_assignment -name PCI_IO Off
+set_global_assignment -name TURBO_BIT On
+set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
+set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
+set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
+set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
+set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto
+set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto
+set_global_assignment -name NORMAL_LCELL_INSERT On
+set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone 10 LP"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V"
+set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF
+set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
+set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
+set_global_assignment -name AUTO_TURBO_BIT ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
+set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
+set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
+set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
+set_global_assignment -name FITTER_EFFORT "Auto Fit"
+set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
+set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto
+set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto
+set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK On
+set_global_assignment -name AUTO_GLOBAL_OE On
+set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
+set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
+set_global_assignment -name ENABLE_HOLD_BACK_OFF On
+set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
+set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto
+set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On
+set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone 10 LP"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V"
+set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX"
+set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off
+set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
+set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
+set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off
+set_global_assignment -name PR_DONE_OPEN_DRAIN On
+set_global_assignment -name NCEO_OPEN_DRAIN On
+set_global_assignment -name ENABLE_CRC_ERROR_PIN Off
+set_global_assignment -name ENABLE_PR_PINS Off
+set_global_assignment -name RESERVE_PR_PINS Off
+set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off
+set_global_assignment -name PR_PINS_OPEN_DRAIN Off
+set_global_assignment -name CLAMPING_DIODE Off
+set_global_assignment -name TRI_STATE_SPI_PINS Off
+set_global_assignment -name UNUSED_TSD_PINS_GND Off
+set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off
+set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off
+set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V"
+set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0
+set_global_assignment -name SEU_FIT_REPORT Off
+set_global_assignment -name HYPER_RETIMER Off -family "Arria 10"
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1"
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On
+set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
+set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
+set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
+set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
+set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
+set_global_assignment -name COMPRESSION_MODE Off
+set_global_assignment -name CLOCK_SOURCE Internal
+set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
+set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
+set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
+set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
+set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
+set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name USE_CHECKSUM_AS_USERCODE On
+set_global_assignment -name SECURITY_BIT Off
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone 10 LP"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130"
+set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000
+set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery"
+set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0
+set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0
+set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0
+set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
+set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
+set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
+set_global_assignment -name GENERATE_TTF_FILE Off
+set_global_assignment -name GENERATE_RBF_FILE Off
+set_global_assignment -name GENERATE_HEX_FILE Off
+set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
+set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
+set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
+set_global_assignment -name AUTO_RESTART_CONFIGURATION On
+set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
+set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
+set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone 10 LP"
+set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V"
+set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF
+set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off
+set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off
+set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off
+set_global_assignment -name POR_SCHEME "Instant ON"
+set_global_assignment -name EN_USER_IO_WEAK_PULLUP On
+set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On
+set_global_assignment -name POF_VERIFY_PROTECT Off
+set_global_assignment -name ENABLE_SPI_MODE_CHECK Off
+set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On
+set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off
+set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0
+set_global_assignment -name GENERATE_PMSF_FILES On
+set_global_assignment -name START_TIME 0ns
+set_global_assignment -name SIMULATION_MODE TIMING
+set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
+set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
+set_global_assignment -name SETUP_HOLD_DETECTION Off
+set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
+set_global_assignment -name CHECK_OUTPUTS Off
+set_global_assignment -name SIMULATION_COVERAGE On
+set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name GLITCH_DETECTION Off
+set_global_assignment -name GLITCH_INTERVAL 1ns
+set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
+set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On
+set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
+set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
+set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
+set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
+set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
+set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO
+set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO
+set_global_assignment -name DRC_TOP_FANOUT 50
+set_global_assignment -name DRC_FANOUT_EXCEEDING 30
+set_global_assignment -name DRC_GATED_CLOCK_FEED 30
+set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
+set_global_assignment -name ENABLE_DRC_SETTINGS Off
+set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
+set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
+set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
+set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
+set_global_assignment -name MERGE_HEX_FILE Off
+set_global_assignment -name GENERATE_SVF_FILE Off
+set_global_assignment -name GENERATE_ISC_FILE Off
+set_global_assignment -name GENERATE_JAM_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
+set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
+set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
+set_global_assignment -name HPS_EARLY_IO_RELEASE Off
+set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
+set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
+set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_USE_PVA On
+set_global_assignment -name POWER_USE_INPUT_FILE "No File"
+set_global_assignment -name POWER_USE_INPUT_FILES Off
+set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
+set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off
+set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off
+set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
+set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
+set_global_assignment -name POWER_TJ_VALUE 25
+set_global_assignment -name POWER_USE_TA_VALUE 25
+set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
+set_global_assignment -name POWER_BOARD_TEMPERATURE 25
+set_global_assignment -name POWER_HPS_ENABLE Off
+set_global_assignment -name POWER_HPS_PROC_FREQ 0.0
+set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off
+set_global_assignment -name IGNORE_PARTITIONS Off
+set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
+set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On
+set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End"
+set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
+set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
+set_global_assignment -name RTLV_GROUP_RELATED_NODES On
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off
+set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On
+set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
+set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
+set_global_assignment -name EQC_BBOX_MERGE On
+set_global_assignment -name EQC_LVDS_MERGE On
+set_global_assignment -name EQC_RAM_UNMERGING On
+set_global_assignment -name EQC_DFF_SS_EMULATION On
+set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
+set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
+set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
+set_global_assignment -name EQC_STRUCTURE_MATCHING On
+set_global_assignment -name EQC_AUTO_BREAK_CONE On
+set_global_assignment -name EQC_POWER_UP_COMPARE Off
+set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
+set_global_assignment -name EQC_AUTO_INVERSION On
+set_global_assignment -name EQC_AUTO_TERMINATE On
+set_global_assignment -name EQC_SUB_CONE_REPORT Off
+set_global_assignment -name EQC_RENAMING_RULES On
+set_global_assignment -name EQC_PARAMETER_CHECK On
+set_global_assignment -name EQC_AUTO_PORTSWAP On
+set_global_assignment -name EQC_DETECT_DONT_CARES On
+set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
+set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
+set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
+set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
+set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
+set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
+set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
+set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
+set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
+set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
+set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "<None>" -section_id ?
+set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
+set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ?
+set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ?
+set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ?
+set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?
+set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
+set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
+set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
+set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
+set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
+set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
+set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
+set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ?
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST On -section_id ?
+set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?
+set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
+set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
+set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
+set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
+set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
+set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
+set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR Off -section_id ?
+set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ?
+set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?
+set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?
+set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
+set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ?
+set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ?
+set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ?
+set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ?
+set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ?
+set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ?
+set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ?
+set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ?
+set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ?
diff --git a/cpld/db/.cmp.kpt b/cpld/db/.cmp.kpt
new file mode 100644
index 0000000..888a8c7
Binary files /dev/null and b/cpld/db/.cmp.kpt differ
diff --git a/cpld/db/GR8RAM.(0).cnf.cdb b/cpld/db/GR8RAM.(0).cnf.cdb
old mode 100755
new mode 100644
index ae22efc..6451a87
Binary files a/cpld/db/GR8RAM.(0).cnf.cdb and b/cpld/db/GR8RAM.(0).cnf.cdb differ
diff --git a/cpld/db/GR8RAM.(0).cnf.hdb b/cpld/db/GR8RAM.(0).cnf.hdb
old mode 100755
new mode 100644
index d932c80..f7d56bd
Binary files a/cpld/db/GR8RAM.(0).cnf.hdb and b/cpld/db/GR8RAM.(0).cnf.hdb differ
diff --git a/cpld/db/GR8RAM.asm.qmsg b/cpld/db/GR8RAM.asm.qmsg
old mode 100755
new mode 100644
index c8aa5e2..7337d4d
--- a/cpld/db/GR8RAM.asm.qmsg
+++ b/cpld/db/GR8RAM.asm.qmsg
@@ -1,6 +1,7 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1631597731746 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1631597731746 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 14 01:35:31 2021 " "Processing started: Tue Sep 14 01:35:31 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1631597731746 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1631597731746 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1631597731746 ""}
-{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1631597731986 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1631597731986 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "381 " "Peak virtual memory: 381 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1631597732146 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 14 01:35:32 2021 " "Processing ended: Tue Sep 14 01:35:32 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1631597732146 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1631597732146 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1631597732146 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1631597732146 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1679994396726 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1679994396726 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 28 05:06:36 2023 " "Processing started: Tue Mar 28 05:06:36 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1679994396726 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1679994396726 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1679994396726 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1679994396991 ""}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1679994397038 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1679994397038 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13057 " "Peak virtual memory: 13057 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679994397272 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 28 05:06:37 2023 " "Processing ended: Tue Mar 28 05:06:37 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679994397272 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679994397272 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679994397272 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1679994397272 ""}
diff --git a/cpld/db/GR8RAM.asm.rdb b/cpld/db/GR8RAM.asm.rdb
old mode 100755
new mode 100644
index a0f1646..6ee78a0
Binary files a/cpld/db/GR8RAM.asm.rdb and b/cpld/db/GR8RAM.asm.rdb differ
diff --git a/cpld/db/GR8RAM.asm_labs.ddb b/cpld/db/GR8RAM.asm_labs.ddb
old mode 100755
new mode 100644
index 365caf7..f73294e
Binary files a/cpld/db/GR8RAM.asm_labs.ddb and b/cpld/db/GR8RAM.asm_labs.ddb differ
diff --git a/cpld/db/GR8RAM.cbx.xml b/cpld/db/GR8RAM.cbx.xml
old mode 100755
new mode 100644
diff --git a/cpld/db/GR8RAM.cmp.cdb b/cpld/db/GR8RAM.cmp.cdb
old mode 100755
new mode 100644
index 54bf809..b931878
Binary files a/cpld/db/GR8RAM.cmp.cdb and b/cpld/db/GR8RAM.cmp.cdb differ
diff --git a/cpld/db/GR8RAM.cmp.hdb b/cpld/db/GR8RAM.cmp.hdb
old mode 100755
new mode 100644
index d982e47..65e8f23
Binary files a/cpld/db/GR8RAM.cmp.hdb and b/cpld/db/GR8RAM.cmp.hdb differ
diff --git a/cpld/db/GR8RAM.cmp.idb b/cpld/db/GR8RAM.cmp.idb
old mode 100755
new mode 100644
index 4057977..f8b13a1
Binary files a/cpld/db/GR8RAM.cmp.idb and b/cpld/db/GR8RAM.cmp.idb differ
diff --git a/cpld/db/GR8RAM.cmp.kpt b/cpld/db/GR8RAM.cmp.kpt
deleted file mode 100755
index 2f27ca1..0000000
Binary files a/cpld/db/GR8RAM.cmp.kpt and /dev/null differ
diff --git a/cpld/db/GR8RAM.cmp.logdb b/cpld/db/GR8RAM.cmp.logdb
old mode 100755
new mode 100644
diff --git a/cpld/db/GR8RAM.cmp.rdb b/cpld/db/GR8RAM.cmp.rdb
old mode 100755
new mode 100644
index e4ec603..10d7877
Binary files a/cpld/db/GR8RAM.cmp.rdb and b/cpld/db/GR8RAM.cmp.rdb differ
diff --git a/cpld/db/GR8RAM.cmp0.ddb b/cpld/db/GR8RAM.cmp0.ddb
old mode 100755
new mode 100644
index ac484d5..a72f1d6
Binary files a/cpld/db/GR8RAM.cmp0.ddb and b/cpld/db/GR8RAM.cmp0.ddb differ
diff --git a/cpld/db/GR8RAM.fit.qmsg b/cpld/db/GR8RAM.fit.qmsg
old mode 100755
new mode 100644
index fb6216a..10b095c
--- a/cpld/db/GR8RAM.fit.qmsg
+++ b/cpld/db/GR8RAM.fit.qmsg
@@ -1,38 +1,40 @@
-{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1631597728526 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1631597728536 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1631597728586 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1631597728586 ""}
-{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" {  } {  } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1631597728726 ""}
-{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1631597728736 ""}
-{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1631597728876 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1631597728876 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1631597728876 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1631597728876 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1631597728876 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1631597728876 ""}
-{ "Info" "ISTA_SDC_FOUND" "GR8RAM.sdc " "Reading SDC File: 'GR8RAM.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1631597729026 ""}
-{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1631597729036 ""}
-{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "  Period   Clock Name" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1631597729036 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1631597729036 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "  40.000         C25M " "  40.000         C25M" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1631597729036 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 978.000         PHI0 " " 978.000         PHI0" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1631597729036 ""}  } {  } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1631597729036 ""}
-{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1631597729046 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1631597729046 ""}
-{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1631597729046 ""}
-{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" {  } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } }  } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1631597729066 ""}
-{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI0 Global clock " "Automatically promoted some destinations of signal \"PHI0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~0 " "Destination \"comb~0\" may be non-global or may not use global clock" {  } {  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1631597729066 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI0r1 " "Destination \"PHI0r1\" may be non-global or may not use global clock" {  } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1631597729066 ""}  } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } }  } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1631597729066 ""}
-{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI0 " "Pin \"PHI0\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { PHI0 } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PHI0" } } } } { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { PHI0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/" { { 0 { 0 ""} 0 418 9224 9983 0}  }  } }  } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1631597729066 ""}
-{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nRESr Global clock " "Automatically promoted some destinations of signal \"nRESr\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "IOROMEN " "Destination \"IOROMEN\" may be non-global or may not use global clock" {  } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 94 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1631597729066 ""}  } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 16 -1 0 } }  } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1631597729066 ""}
-{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" {  } {  } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1631597729066 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1631597729066 ""}
-{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" {  } {  } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1631597729086 ""}
-{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" {  } {  } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1631597729116 ""}
-{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" {  } {  } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1631597729116 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" {  } {  } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1631597729116 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" {  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1631597729116 ""}
-{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1631597729186 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1631597729306 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1631597729566 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1631597729576 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1631597730096 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1631597730096 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1631597730126 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "34 " "Router estimated average interconnect usage is 34% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "34 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" {  } { { "loc" "" { Generic "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1631597730346 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1631597730346 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1631597730656 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.27 " "Total time spent on timing analysis during the Fitter is 0.27 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1631597730666 ""}
-{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1631597730666 ""}
-{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1631597730716 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1631597730776 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "544 " "Peak virtual memory: 544 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1631597730806 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 14 01:35:30 2021 " "Processing ended: Tue Sep 14 01:35:30 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1631597730806 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1631597730806 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1631597730806 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1631597730806 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1679994392961 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1679994392961 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1679994392961 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1679994393007 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1679994393007 ""}
+{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" {  } {  } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1679994393038 ""}
+{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1679994393054 ""}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679994393132 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679994393132 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679994393132 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679994393132 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679994393132 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1679994393132 ""}
+{ "Info" "ISTA_SDC_FOUND" "GR8RAM.sdc " "Reading SDC File: 'GR8RAM.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1679994393225 ""}
+{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1679994393241 ""}
+{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "  Period   Clock Name" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1679994393241 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1679994393241 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "  40.000         C25M " "  40.000         C25M" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1679994393241 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 978.000         PHI0 " " 978.000         PHI0" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1679994393241 ""}  } {  } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1679994393241 ""}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1679994393257 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1679994393257 ""}
+{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1679994393257 ""}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" {  } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } }  } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1679994393272 ""}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI0 Global clock " "Automatically promoted some destinations of signal \"PHI0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~0 " "Destination \"comb~0\" may be non-global or may not use global clock" {  } {  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1679994393272 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI0r1 " "Destination \"PHI0r1\" may be non-global or may not use global clock" {  } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1679994393272 ""}  } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } }  } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1679994393272 ""}
+{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI0 " "Pin \"PHI0\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { PHI0 } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PHI0" } } } } { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } { "temporary_test_loc" "" { Generic "Y:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 417 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1679994393272 ""}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nRESr Global clock " "Automatically promoted some destinations of signal \"nRESr\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "IOROMEN " "Destination \"IOROMEN\" may be non-global or may not use global clock" {  } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 88 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1679994393272 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RestoreDone~0 " "Destination \"RestoreDone~0\" may be non-global or may not use global clock" {  } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 150 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1679994393272 ""}  } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 16 -1 0 } }  } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1679994393272 ""}
+{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" {  } {  } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1679994393272 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1679994393272 ""}
+{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" {  } {  } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1679994393319 ""}
+{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" {  } {  } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1679994393366 ""}
+{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" {  } {  } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1679994393366 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" {  } {  } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1679994393366 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" {  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1679994393366 ""}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1679994393413 ""}
+{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." {  } {  } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1679994393429 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1679994393554 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1679994393804 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1679994393804 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1679994394585 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1679994394585 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1679994394632 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "31 " "Router estimated average interconnect usage is 31% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "31 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 31% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" {  } { { "loc" "" { Generic "Y:/Repos/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 31% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 12 { 0 ""} 0 0 9 6 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1679994394866 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1679994394866 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1679994395147 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.31 " "Total time spent on timing analysis during the Fitter is 0.31 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1679994395163 ""}
+{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1679994395179 ""}
+{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1679994395225 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1679994395272 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13733 " "Peak virtual memory: 13733 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679994395319 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 28 05:06:35 2023 " "Processing ended: Tue Mar 28 05:06:35 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679994395319 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679994395319 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679994395319 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1679994395319 ""}
diff --git a/cpld/db/GR8RAM.hier_info b/cpld/db/GR8RAM.hier_info
old mode 100755
new mode 100644
index 554e4da..1680337
--- a/cpld/db/GR8RAM.hier_info
+++ b/cpld/db/GR8RAM.hier_info
@@ -31,10 +31,10 @@ C25M => WRD[5].CLK
 C25M => WRD[6].CLK
 C25M => WRD[7].CLK
 C25M => MOSIout.CLK
-C25M => FCKOE.CLK
 C25M => MOSIOE.CLK
-C25M => FCS.CLK
+C25M => nFCS~reg0.CLK
 C25M => FCKout.CLK
+C25M => RestoreDone.CLK
 C25M => Bank.CLK
 C25M => AddrIncH.CLK
 C25M => AddrIncM.CLK
@@ -85,9 +85,6 @@ C25M => PS[0].CLK
 C25M => PS[1].CLK
 C25M => PS[2].CLK
 C25M => PS[3].CLK
-C25M => SetFWr[0].CLK
-C25M => SetFWr[1].CLK
-C25M => SetFWLoaded.CLK
 C25M => nRESr.CLK
 C25M => nRESf[0].CLK
 C25M => nRESf[1].CLK
@@ -120,10 +117,11 @@ PHI0 => RAr[10].CLK
 PHI0 => RAr[11].CLK
 PHI0 => CXXXr.CLK
 PHI0 => PHI0r1.DATAIN
+nRES => MOSIout.OUTPUTSELECT
 nRES => nRESf[0].DATAIN
 nRESout <= nRESout~reg0.DB_MAX_OUTPUT_PORT_TYPE
-SetFW[0] => SetFWr[0].DATAIN
-SetFW[1] => SetFWr[1].DATAIN
+SetFW[0] => ~NO_FANOUT~
+SetFW[1] => ~NO_FANOUT~
 INTin => INTout.DATAIN
 INTout <= INTin.DB_MAX_OUTPUT_PORT_TYPE
 DMAin => DMAout.DATAIN
@@ -135,32 +133,32 @@ nINHout <= <VCC>
 RWout <= <VCC>
 nDMAout <= <VCC>
 RA[0] => RAr[0].DATAIN
-RA[0] => Equal16.IN10
+RA[0] => Equal17.IN10
 RA[1] => RAr[1].DATAIN
-RA[1] => Equal16.IN9
+RA[1] => Equal17.IN9
 RA[2] => RAr[2].DATAIN
-RA[2] => Equal16.IN8
+RA[2] => Equal17.IN8
 RA[3] => RAr[3].DATAIN
-RA[3] => Equal16.IN7
+RA[3] => Equal17.IN7
 RA[4] => RAr[4].DATAIN
-RA[4] => Equal16.IN6
+RA[4] => Equal17.IN6
 RA[5] => RAr[5].DATAIN
-RA[5] => Equal16.IN5
+RA[5] => Equal17.IN5
 RA[6] => RAr[6].DATAIN
-RA[6] => Equal16.IN4
+RA[6] => Equal17.IN4
 RA[7] => RAr[7].DATAIN
-RA[7] => Equal16.IN3
+RA[7] => Equal17.IN3
 RA[8] => RAr[8].DATAIN
-RA[8] => Equal16.IN2
+RA[8] => Equal17.IN2
 RA[9] => RAr[9].DATAIN
-RA[9] => Equal16.IN1
+RA[9] => Equal17.IN1
 RA[10] => RAr[10].DATAIN
-RA[10] => Equal16.IN0
+RA[10] => Equal17.IN0
 RA[11] => RAr[11].DATAIN
-RA[12] => Equal8.IN1
-RA[13] => Equal8.IN0
-RA[14] => Equal8.IN3
-RA[15] => Equal8.IN2
+RA[12] => Equal7.IN1
+RA[13] => Equal7.IN0
+RA[14] => Equal7.IN3
+RA[15] => Equal7.IN2
 nWE => comb.IN1
 nWE => nWEr.DATAIN
 RD[0] <> RD[0]
@@ -173,10 +171,12 @@ RD[6] <> RD[6]
 RD[7] <> RD[7]
 RAdir <= <VCC>
 RDdir <= comb.DB_MAX_OUTPUT_PORT_TYPE
+nIOSEL => SA.OUTPUTSELECT
 nIOSEL => comb.IN0
-nIOSEL => always7.IN1
+nIOSEL => always6.IN1
 nDEVSEL => comb.IN1
 nDEVSEL => RAMSEL.IN1
+nDEVSEL => FCKout.IN1
 nDEVSEL => comb.IN1
 nDEVSEL => RAMRegSEL.IN1
 nIOSTRB => nIOSTRBr.DATAIN
@@ -212,9 +212,10 @@ SD[4] <> SD[4]
 SD[5] <> SD[5]
 SD[6] <> SD[6]
 SD[7] <> SD[7]
-nFCS <= nFCS.DB_MAX_OUTPUT_PORT_TYPE
-FCK <= FCK.DB_MAX_OUTPUT_PORT_TYPE
+nFCS <= nFCS~reg0.DB_MAX_OUTPUT_PORT_TYPE
+FCK <= FCKout.DB_MAX_OUTPUT_PORT_TYPE
 MISO => WRD.DATAB
+MISO => RDD.DATAB
 MOSI <> MOSI
 
 
diff --git a/cpld/db/GR8RAM.hif b/cpld/db/GR8RAM.hif
old mode 100755
new mode 100644
index 6af5f23..3eb0cef
Binary files a/cpld/db/GR8RAM.hif and b/cpld/db/GR8RAM.hif differ
diff --git a/cpld/db/GR8RAM.ipinfo b/cpld/db/GR8RAM.ipinfo
deleted file mode 100755
index fa2304d..0000000
Binary files a/cpld/db/GR8RAM.ipinfo and /dev/null differ
diff --git a/cpld/db/GR8RAM.lpc.html b/cpld/db/GR8RAM.lpc.html
old mode 100755
new mode 100644
diff --git a/cpld/db/GR8RAM.lpc.rdb b/cpld/db/GR8RAM.lpc.rdb
old mode 100755
new mode 100644
index adf8589..c804a63
Binary files a/cpld/db/GR8RAM.lpc.rdb and b/cpld/db/GR8RAM.lpc.rdb differ
diff --git a/cpld/db/GR8RAM.lpc.txt b/cpld/db/GR8RAM.lpc.txt
old mode 100755
new mode 100644
diff --git a/cpld/db/GR8RAM.map.cdb b/cpld/db/GR8RAM.map.cdb
old mode 100755
new mode 100644
index d641494..4caad7f
Binary files a/cpld/db/GR8RAM.map.cdb and b/cpld/db/GR8RAM.map.cdb differ
diff --git a/cpld/db/GR8RAM.map.hdb b/cpld/db/GR8RAM.map.hdb
old mode 100755
new mode 100644
index e1ab595..e385e48
Binary files a/cpld/db/GR8RAM.map.hdb and b/cpld/db/GR8RAM.map.hdb differ
diff --git a/cpld/db/GR8RAM.map.logdb b/cpld/db/GR8RAM.map.logdb
old mode 100755
new mode 100644
diff --git a/cpld/db/GR8RAM.map.qmsg b/cpld/db/GR8RAM.map.qmsg
old mode 100755
new mode 100644
index bb3a4cf..d503ea7
--- a/cpld/db/GR8RAM.map.qmsg
+++ b/cpld/db/GR8RAM.map.qmsg
@@ -1,19 +1,21 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1631597725836 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1631597725836 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 14 01:35:25 2021 " "Processing started: Tue Sep 14 01:35:25 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1631597725836 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1631597725836 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1631597725836 ""}
-{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1631597726126 ""}
-{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(110) " "Verilog HDL warning at GR8RAM.v(110): extended using \"x\" or \"z\"" {  } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 110 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1631597726216 ""}
-{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(286) " "Verilog HDL warning at GR8RAM.v(286): extended using \"x\" or \"z\"" {  } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 286 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1631597726216 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" {  } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1631597726226 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1631597726226 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1631597726256 ""}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(42) " "Verilog HDL assignment warning at GR8RAM.v(42): truncated value with size 32 to match size of target (4)" {  } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 42 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1631597726266 "|GR8RAM"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(47) " "Verilog HDL assignment warning at GR8RAM.v(47): truncated value with size 32 to match size of target (14)" {  } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 47 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1631597726266 "|GR8RAM"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(134) " "Verilog HDL assignment warning at GR8RAM.v(134): truncated value with size 32 to match size of target (8)" {  } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 134 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1631597726266 "|GR8RAM"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(142) " "Verilog HDL assignment warning at GR8RAM.v(142): truncated value with size 32 to match size of target (8)" {  } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 142 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1631597726266 "|GR8RAM"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(149) " "Verilog HDL assignment warning at GR8RAM.v(149): truncated value with size 32 to match size of target (8)" {  } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 149 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1631597726266 "|GR8RAM"}
-{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" {  } {  } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 -1 1631597726806 ""}
-{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "nNMIout VCC " "Pin \"nNMIout\" is stuck at VCC" {  } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 563 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1631597726986 "|GR8RAM|nNMIout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nIRQout VCC " "Pin \"nIRQout\" is stuck at VCC" {  } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 566 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1631597726986 "|GR8RAM|nIRQout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nRDYout VCC " "Pin \"nRDYout\" is stuck at VCC" {  } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 565 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1631597726986 "|GR8RAM|nRDYout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nINHout VCC " "Pin \"nINHout\" is stuck at VCC" {  } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 564 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1631597726986 "|GR8RAM|nINHout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RWout VCC " "Pin \"RWout\" is stuck at VCC" {  } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 567 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1631597726986 "|GR8RAM|RWout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nDMAout VCC " "Pin \"nDMAout\" is stuck at VCC" {  } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 562 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1631597726986 "|GR8RAM|nDMAout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" {  } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 561 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1631597726986 "|GR8RAM|RAdir"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1631597726986 ""}
-{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1631597727226 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "337 " "Implemented 337 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "28 " "Implemented 28 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1631597727256 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1631597727256 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" {  } {  } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1631597727256 ""} { "Info" "ICUT_CUT_TM_LCELLS" "257 " "Implemented 257 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1631597727256 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1631597727256 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1631597727336 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 14 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 14 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "422 " "Peak virtual memory: 422 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1631597727356 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 14 01:35:27 2021 " "Processing ended: Tue Sep 14 01:35:27 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1631597727356 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1631597727356 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1631597727356 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1631597727356 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1679994373538 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1679994373554 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 28 05:06:13 2023 " "Processing started: Tue Mar 28 05:06:13 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1679994373554 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679994373554 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679994373554 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1679994373897 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1679994373897 ""}
+{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(104) " "Verilog HDL warning at GR8RAM.v(104): extended using \"x\" or \"z\"" {  } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 104 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1679994390038 ""}
+{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(281) " "Verilog HDL warning at GR8RAM.v(281): extended using \"x\" or \"z\"" {  } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 281 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1679994390038 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" {  } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679994390038 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679994390038 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1679994390069 ""}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(34) " "Verilog HDL assignment warning at GR8RAM.v(34): truncated value with size 32 to match size of target (4)" {  } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 34 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1679994390085 "|GR8RAM"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(39) " "Verilog HDL assignment warning at GR8RAM.v(39): truncated value with size 32 to match size of target (14)" {  } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 39 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1679994390085 "|GR8RAM"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(128) " "Verilog HDL assignment warning at GR8RAM.v(128): truncated value with size 32 to match size of target (8)" {  } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 128 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1679994390085 "|GR8RAM"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(136) " "Verilog HDL assignment warning at GR8RAM.v(136): truncated value with size 32 to match size of target (8)" {  } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 136 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1679994390085 "|GR8RAM"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(143) " "Verilog HDL assignment warning at GR8RAM.v(143): truncated value with size 32 to match size of target (8)" {  } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 143 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1679994390085 "|GR8RAM"}
+{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" {  } {  } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Analysis & Synthesis" 0 -1 1679994390538 ""}
+{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "nNMIout VCC " "Pin \"nNMIout\" is stuck at VCC" {  } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 559 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1679994390757 "|GR8RAM|nNMIout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nIRQout VCC " "Pin \"nIRQout\" is stuck at VCC" {  } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 562 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1679994390757 "|GR8RAM|nIRQout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nRDYout VCC " "Pin \"nRDYout\" is stuck at VCC" {  } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 561 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1679994390757 "|GR8RAM|nRDYout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nINHout VCC " "Pin \"nINHout\" is stuck at VCC" {  } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 560 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1679994390757 "|GR8RAM|nINHout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RWout VCC " "Pin \"RWout\" is stuck at VCC" {  } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 563 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1679994390757 "|GR8RAM|RWout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nDMAout VCC " "Pin \"nDMAout\" is stuck at VCC" {  } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 558 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1679994390757 "|GR8RAM|nDMAout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" {  } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 557 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1679994390757 "|GR8RAM|RAdir"} { "Warning" "WMLS_MLS_STUCK_PIN" "SBA\[0\] GND " "Pin \"SBA\[0\]\" is stuck at GND" {  } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 442 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1679994390757 "|GR8RAM|SBA[0]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1679994390757 ""}
+{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1679994391085 ""}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SetFW\[0\] " "No output dependent on input pin \"SetFW\[0\]\"" {  } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 23 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1679994391100 "|GR8RAM|SetFW[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SetFW\[1\] " "No output dependent on input pin \"SetFW\[1\]\"" {  } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 23 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1679994391100 "|GR8RAM|SetFW[1]"}  } {  } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1679994391100 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "336 " "Implemented 336 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "28 " "Implemented 28 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1679994391100 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1679994391100 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" {  } {  } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Design Software" 0 -1 1679994391100 ""} { "Info" "ICUT_CUT_TM_LCELLS" "256 " "Implemented 256 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1679994391100 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1679994391100 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679994391147 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 18 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 18 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13094 " "Peak virtual memory: 13094 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679994391179 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 28 05:06:31 2023 " "Processing ended: Tue Mar 28 05:06:31 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679994391179 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:18 " "Elapsed time: 00:00:18" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679994391179 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:39 " "Total CPU time (on all processors): 00:00:39" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679994391179 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1679994391179 ""}
diff --git a/cpld/db/GR8RAM.map.rdb b/cpld/db/GR8RAM.map.rdb
old mode 100755
new mode 100644
index 30bc868..999fd86
Binary files a/cpld/db/GR8RAM.map.rdb and b/cpld/db/GR8RAM.map.rdb differ
diff --git a/cpld/db/GR8RAM.pplq.rdb b/cpld/db/GR8RAM.pplq.rdb
new file mode 100644
index 0000000..9a85185
Binary files /dev/null and b/cpld/db/GR8RAM.pplq.rdb differ
diff --git a/cpld/db/GR8RAM.pre_map.hdb b/cpld/db/GR8RAM.pre_map.hdb
old mode 100755
new mode 100644
index f232fe4..07e0e17
Binary files a/cpld/db/GR8RAM.pre_map.hdb and b/cpld/db/GR8RAM.pre_map.hdb differ
diff --git a/cpld/db/GR8RAM.pti_db_list.ddb b/cpld/db/GR8RAM.pti_db_list.ddb
deleted file mode 100755
index 89aa9b4..0000000
Binary files a/cpld/db/GR8RAM.pti_db_list.ddb and /dev/null differ
diff --git a/cpld/db/GR8RAM.syn_hier_info b/cpld/db/GR8RAM.quiproj.10860.rdr.flock
old mode 100755
new mode 100644
similarity index 100%
rename from cpld/db/GR8RAM.syn_hier_info
rename to cpld/db/GR8RAM.quiproj.10860.rdr.flock
diff --git a/cpld/db/GR8RAM.root_partition.map.reg_db.cdb b/cpld/db/GR8RAM.root_partition.map.reg_db.cdb
old mode 100755
new mode 100644
index 0278be2..142d755
Binary files a/cpld/db/GR8RAM.root_partition.map.reg_db.cdb and b/cpld/db/GR8RAM.root_partition.map.reg_db.cdb differ
diff --git a/cpld/db/GR8RAM.routing.rdb b/cpld/db/GR8RAM.routing.rdb
old mode 100755
new mode 100644
index 86d39e0..02debe0
Binary files a/cpld/db/GR8RAM.routing.rdb and b/cpld/db/GR8RAM.routing.rdb differ
diff --git a/cpld/db/GR8RAM.rtlv.hdb b/cpld/db/GR8RAM.rtlv.hdb
old mode 100755
new mode 100644
index 3d01036..672d736
Binary files a/cpld/db/GR8RAM.rtlv.hdb and b/cpld/db/GR8RAM.rtlv.hdb differ
diff --git a/cpld/db/GR8RAM.rtlv_sg.cdb b/cpld/db/GR8RAM.rtlv_sg.cdb
old mode 100755
new mode 100644
index aca72e9..e3abbbc
Binary files a/cpld/db/GR8RAM.rtlv_sg.cdb and b/cpld/db/GR8RAM.rtlv_sg.cdb differ
diff --git a/cpld/db/GR8RAM.rtlv_sg_swap.cdb b/cpld/db/GR8RAM.rtlv_sg_swap.cdb
old mode 100755
new mode 100644
index bf4c983..5f0f08a
Binary files a/cpld/db/GR8RAM.rtlv_sg_swap.cdb and b/cpld/db/GR8RAM.rtlv_sg_swap.cdb differ
diff --git a/cpld/db/GR8RAM.sgdiff.cdb b/cpld/db/GR8RAM.sgdiff.cdb
deleted file mode 100755
index 4597751..0000000
Binary files a/cpld/db/GR8RAM.sgdiff.cdb and /dev/null differ
diff --git a/cpld/db/GR8RAM.sgdiff.hdb b/cpld/db/GR8RAM.sgdiff.hdb
deleted file mode 100755
index e983e2f..0000000
Binary files a/cpld/db/GR8RAM.sgdiff.hdb and /dev/null differ
diff --git a/cpld/db/GR8RAM.sld_design_entry.sci b/cpld/db/GR8RAM.sld_design_entry.sci
old mode 100755
new mode 100644
index 1d6d60f..dcd2274
Binary files a/cpld/db/GR8RAM.sld_design_entry.sci and b/cpld/db/GR8RAM.sld_design_entry.sci differ
diff --git a/cpld/db/GR8RAM.sld_design_entry_dsc.sci b/cpld/db/GR8RAM.sld_design_entry_dsc.sci
old mode 100755
new mode 100644
index 1d6d60f..dcd2274
Binary files a/cpld/db/GR8RAM.sld_design_entry_dsc.sci and b/cpld/db/GR8RAM.sld_design_entry_dsc.sci differ
diff --git a/cpld/db/GR8RAM.smart_action.txt b/cpld/db/GR8RAM.smart_action.txt
old mode 100755
new mode 100644
diff --git a/cpld/db/GR8RAM.smp_dump.txt b/cpld/db/GR8RAM.smp_dump.txt
old mode 100755
new mode 100644
diff --git a/cpld/db/GR8RAM.sta.qmsg b/cpld/db/GR8RAM.sta.qmsg
old mode 100755
new mode 100644
index 9811367..59e52fd
--- a/cpld/db/GR8RAM.sta.qmsg
+++ b/cpld/db/GR8RAM.sta.qmsg
@@ -1,20 +1,22 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1631597733226 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733226 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 14 01:35:32 2021 " "Processing started: Tue Sep 14 01:35:32 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1631597733226 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1631597733226 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1631597733226 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1631597733306 ""}
-{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1631597733426 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1631597733476 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1631597733476 ""}
-{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1631597733536 ""}
-{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1631597733876 ""}
-{ "Info" "ISTA_SDC_FOUND" "GR8RAM.sdc " "Reading SDC File: 'GR8RAM.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1631597733926 ""}
-{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1631597733926 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup 12.419 " "Worst-case setup slack is 12.419" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733936 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733936 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   12.419         0.000 C25M  " "   12.419         0.000 C25M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733936 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1631597733936 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.393 " "Worst-case hold slack is 1.393" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.393         0.000 C25M  " "    1.393         0.000 C25M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 33.300 " "Worst-case recovery slack is 33.300" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   33.300         0.000 C25M  " "   33.300         0.000 C25M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "removal 6.146 " "Worst-case removal slack is 6.146" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    6.146         0.000 C25M  " "    6.146         0.000 C25M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 19.734 " "Worst-case minimum pulse width slack is 19.734" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   19.734         0.000 C25M  " "   19.734         0.000 C25M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  488.734         0.000 PHI0  " "  488.734         0.000 PHI0 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""}
-{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." {  } {  } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1631597733996 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1631597734016 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1631597734016 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 1  Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "374 " "Peak virtual memory: 374 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1631597734056 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 14 01:35:34 2021 " "Processing ended: Tue Sep 14 01:35:34 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1631597734056 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1631597734056 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1631597734056 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1631597734056 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1679994398756 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1679994398756 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 28 05:06:38 2023 " "Processing started: Tue Mar 28 05:06:38 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1679994398756 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1679994398756 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" {  } {  } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1679994398756 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1679994398866 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1679994399077 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1679994399077 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679994399112 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679994399112 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1679994399175 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1679994399581 ""}
+{ "Info" "ISTA_SDC_FOUND" "GR8RAM.sdc " "Reading SDC File: 'GR8RAM.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Timing Analyzer" 0 -1 1679994399659 ""}
+{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1679994399659 ""}
+{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." {  } {  } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1679994399690 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 12.472 " "Worst-case setup slack is 12.472" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399706 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399706 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   12.472               0.000 C25M  " "   12.472               0.000 C25M " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399706 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679994399706 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.383 " "Worst-case hold slack is 1.383" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399706 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399706 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.383               0.000 C25M  " "    1.383               0.000 C25M " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399706 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679994399706 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 33.331 " "Worst-case recovery slack is 33.331" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399722 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399722 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   33.331               0.000 C25M  " "   33.331               0.000 C25M " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399722 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679994399722 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "removal 6.115 " "Worst-case removal slack is 6.115" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399722 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399722 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    6.115               0.000 C25M  " "    6.115               0.000 C25M " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399722 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679994399722 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 19.734 " "Worst-case minimum pulse width slack is 19.734" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399722 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399722 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   19.734               0.000 C25M  " "   19.734               0.000 C25M " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399722 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  488.734               0.000 PHI0  " "  488.734               0.000 PHI0 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679994399722 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679994399722 ""}
+{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." {  } {  } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Timing Analyzer" 0 -1 1679994399769 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1679994399784 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1679994399784 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13052 " "Peak virtual memory: 13052 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679994399847 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 28 05:06:39 2023 " "Processing ended: Tue Mar 28 05:06:39 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679994399847 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679994399847 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679994399847 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1679994399847 ""}
diff --git a/cpld/db/GR8RAM.sta.rdb b/cpld/db/GR8RAM.sta.rdb
old mode 100755
new mode 100644
index a3f53ba..691152f
Binary files a/cpld/db/GR8RAM.sta.rdb and b/cpld/db/GR8RAM.sta.rdb differ
diff --git a/cpld/db/GR8RAM.sta_cmp.5_slow.tdb b/cpld/db/GR8RAM.sta_cmp.5_slow.tdb
old mode 100755
new mode 100644
index 599251e..1779d3b
Binary files a/cpld/db/GR8RAM.sta_cmp.5_slow.tdb and b/cpld/db/GR8RAM.sta_cmp.5_slow.tdb differ
diff --git a/cpld/db/GR8RAM.tis_db_list.ddb b/cpld/db/GR8RAM.tis_db_list.ddb
old mode 100755
new mode 100644
index 91bbe10..7ca0133
Binary files a/cpld/db/GR8RAM.tis_db_list.ddb and b/cpld/db/GR8RAM.tis_db_list.ddb differ
diff --git a/cpld/db/GR8RAM.vpr.ammdb b/cpld/db/GR8RAM.vpr.ammdb
old mode 100755
new mode 100644
index c3f8e94..4a5bb33
Binary files a/cpld/db/GR8RAM.vpr.ammdb and b/cpld/db/GR8RAM.vpr.ammdb differ
diff --git a/cpld/db/prev_cmp_GR8RAM.qmsg b/cpld/db/prev_cmp_GR8RAM.qmsg
old mode 100755
new mode 100644
index a48d744..3ae229c
--- a/cpld/db/prev_cmp_GR8RAM.qmsg
+++ b/cpld/db/prev_cmp_GR8RAM.qmsg
@@ -1,91 +1,11 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1619049425619 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1619049425619 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 21 19:57:05 2021 " "Processing started: Wed Apr 21 19:57:05 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1619049425619 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1619049425619 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1619049425635 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1619049427276 ""}
-{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(110) " "Verilog HDL warning at GR8RAM.v(110): extended using \"x\" or \"z\"" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 110 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1619049427432 ""}
-{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(286) " "Verilog HDL warning at GR8RAM.v(286): extended using \"x\" or \"z\"" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 286 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1619049427432 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1619049427448 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1619049427448 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1619049427557 ""}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(42) " "Verilog HDL assignment warning at GR8RAM.v(42): truncated value with size 32 to match size of target (4)" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 42 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1619049427557 "|GR8RAM"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(47) " "Verilog HDL assignment warning at GR8RAM.v(47): truncated value with size 32 to match size of target (14)" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 47 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1619049427557 "|GR8RAM"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(134) " "Verilog HDL assignment warning at GR8RAM.v(134): truncated value with size 32 to match size of target (8)" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 134 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1619049427573 "|GR8RAM"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(142) " "Verilog HDL assignment warning at GR8RAM.v(142): truncated value with size 32 to match size of target (8)" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 142 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1619049427573 "|GR8RAM"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(149) " "Verilog HDL assignment warning at GR8RAM.v(149): truncated value with size 32 to match size of target (8)" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 149 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1619049427589 "|GR8RAM"}
-{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" {  } {  } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 -1 1619049429167 ""}
-{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "nNMIout VCC " "Pin \"nNMIout\" is stuck at VCC" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 563 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1619049429543 "|GR8RAM|nNMIout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nIRQout VCC " "Pin \"nIRQout\" is stuck at VCC" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 566 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1619049429543 "|GR8RAM|nIRQout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nRDYout VCC " "Pin \"nRDYout\" is stuck at VCC" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 565 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1619049429543 "|GR8RAM|nRDYout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nINHout VCC " "Pin \"nINHout\" is stuck at VCC" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 564 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1619049429543 "|GR8RAM|nINHout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RWout VCC " "Pin \"RWout\" is stuck at VCC" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 567 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1619049429543 "|GR8RAM|RWout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nDMAout VCC " "Pin \"nDMAout\" is stuck at VCC" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 562 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1619049429543 "|GR8RAM|nDMAout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 561 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1619049429543 "|GR8RAM|RAdir"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1619049429543 ""}
-{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1619049430027 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "337 " "Implemented 337 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "28 " "Implemented 28 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1619049430074 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1619049430074 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" {  } {  } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1619049430074 ""} { "Info" "ICUT_CUT_TM_LCELLS" "257 " "Implemented 257 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1619049430074 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1619049430074 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1619049430324 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 13 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 13 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "301 " "Peak virtual memory: 301 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1619049430496 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 21 19:57:10 2021 " "Processing ended: Wed Apr 21 19:57:10 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1619049430496 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1619049430496 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1619049430496 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1619049430496 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1619049433591 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 32-bit " "Running Quartus II 32-bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1619049433606 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 21 19:57:12 2021 " "Processing started: Wed Apr 21 19:57:12 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1619049433606 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1619049433606 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" {  } {  } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1619049433606 ""}
-{ "Info" "0" "" "qfit2_default_script.tcl version: #1" {  } {  } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1619049433810 ""}
-{ "Info" "0" "" "Project  = GR8RAM" {  } {  } 0 0 "Project  = GR8RAM" 0 0 "Fitter" 0 0 1619049433810 ""}
-{ "Info" "0" "" "Revision = GR8RAM" {  } {  } 0 0 "Revision = GR8RAM" 0 0 "Fitter" 0 0 1619049433810 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1619049434576 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1619049434607 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1619049435513 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1619049435513 ""}
-{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" {  } {  } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1619049435826 ""}
-{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1619049435873 ""}
-{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1619049436217 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1619049436217 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1619049436217 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1619049436217 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1619049436217 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1619049436217 ""}
-{ "Info" "ISTA_SDC_FOUND" "GR8RAM.sdc " "Reading SDC File: 'GR8RAM.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1619049436389 ""}
-{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1619049436436 ""}
-{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "  Period   Clock Name" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1619049436451 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1619049436451 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "  40.000         C25M " "  40.000         C25M" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1619049436451 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 978.000         PHI0 " " 978.000         PHI0" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1619049436451 ""}  } {  } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1619049436451 ""}
-{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1619049436451 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1619049436451 ""}
-{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1619049436467 ""}
-{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } }  } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1619049436514 ""}
-{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI0 Global clock " "Automatically promoted some destinations of signal \"PHI0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~0 " "Destination \"comb~0\" may be non-global or may not use global clock" {  } {  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1619049436514 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI0r1 " "Destination \"PHI0r1\" may be non-global or may not use global clock" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1619049436514 ""}  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } }  } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1619049436514 ""}
-{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI0 " "Pin \"PHI0\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI0 } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "PHI0" } } } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 419 9224 9983 0}  }  } }  } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1619049436514 ""}
-{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nRESr Global clock " "Automatically promoted some destinations of signal \"nRESr\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "IOROMEN " "Destination \"IOROMEN\" may be non-global or may not use global clock" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 94 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1619049436514 ""}  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 16 -1 0 } }  } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1619049436514 ""}
-{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" {  } {  } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1619049436514 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1619049436529 ""}
-{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" {  } {  } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1619049436592 ""}
-{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" {  } {  } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1619049436654 ""}
-{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" {  } {  } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1619049436670 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" {  } {  } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1619049436670 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" {  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1619049436670 ""}
-{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619049436701 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1619049436967 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619049437342 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1619049437373 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1619049438593 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619049438593 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1619049438686 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "34 " "Router estimated average interconnect usage is 34% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "34 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" {  } { { "loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1619049439186 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1619049439186 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619049439702 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.56 " "Total time spent on timing analysis during the Fitter is 0.56 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1619049439718 ""}
-{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619049439718 ""}
-{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1619049439765 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1619049440124 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "383 " "Peak virtual memory: 383 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1619049440312 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 21 19:57:20 2021 " "Processing ended: Wed Apr 21 19:57:20 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1619049440312 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1619049440312 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1619049440312 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1619049440312 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1619049443282 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1619049443297 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 21 19:57:22 2021 " "Processing started: Wed Apr 21 19:57:22 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1619049443297 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1619049443297 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1619049443297 ""}
-{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1619049444797 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1619049444985 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "293 " "Peak virtual memory: 293 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1619049446001 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 21 19:57:26 2021 " "Processing ended: Wed Apr 21 19:57:26 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1619049446001 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1619049446001 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1619049446001 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1619049446001 ""}
-{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" {  } {  } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1619049446923 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1619049449251 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1619049449267 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 21 19:57:27 2021 " "Processing started: Wed Apr 21 19:57:27 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1619049449267 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1619049449267 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1619049449267 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1619049449455 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1619049450502 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1619049450705 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1619049450705 ""}
-{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1619049450877 ""}
-{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1619049451408 ""}
-{ "Info" "ISTA_SDC_FOUND" "GR8RAM.sdc " "Reading SDC File: 'GR8RAM.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1619049451564 ""}
-{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1619049451627 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup 12.419 " "Worst-case setup slack is 12.419" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451721 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451721 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   12.419         0.000 C25M  " "   12.419         0.000 C25M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451721 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1619049451721 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.393 " "Worst-case hold slack is 1.393" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451721 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451721 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.393         0.000 C25M  " "    1.393         0.000 C25M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451721 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1619049451721 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 33.300 " "Worst-case recovery slack is 33.300" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451736 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451736 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   33.300         0.000 C25M  " "   33.300         0.000 C25M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451736 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1619049451736 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "removal 6.146 " "Worst-case removal slack is 6.146" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451736 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451736 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    6.146         0.000 C25M  " "    6.146         0.000 C25M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451736 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1619049451736 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 19.734 " "Worst-case minimum pulse width slack is 19.734" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451752 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451752 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   19.734         0.000 C25M  " "   19.734         0.000 C25M " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451752 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  488.734         0.000 PHI0  " "  488.734         0.000 PHI0 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451752 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1619049451752 ""}
-{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." {  } {  } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1619049451861 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1619049451924 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1619049451939 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "278 " "Peak virtual memory: 278 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1619049452143 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 21 19:57:32 2021 " "Processing ended: Wed Apr 21 19:57:32 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1619049452143 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1619049452143 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1619049452143 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1619049452143 ""}
-{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 15 s " "Quartus II Full Compilation was successful. 0 errors, 15 warnings" {  } {  } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1619049453283 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1679994334673 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1679994334673 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 28 05:05:34 2023 " "Processing started: Tue Mar 28 05:05:34 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1679994334673 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679994334673 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679994334673 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1679994335048 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1679994335048 ""}
+{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(103) " "Verilog HDL warning at GR8RAM.v(103): extended using \"x\" or \"z\"" {  } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 103 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1679994351125 ""}
+{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(280) " "Verilog HDL warning at GR8RAM.v(280): extended using \"x\" or \"z\"" {  } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 280 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1679994351125 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" {  } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679994351125 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679994351125 ""}
+{ "Error" "EVRFX_VERI_UNDECLARED_OBJECT" "SetFW GR8RAM.v(1) " "Verilog HDL error at GR8RAM.v(1): object \"SetFW\" is not declared. Verify the object name is correct. If the name is correct, declare the object." {  } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 1 0 0 } }  } 0 10161 "Verilog HDL error at %2!s!: object \"%1!s!\" is not declared. Verify the object name is correct. If the name is correct, declare the object." 0 0 "Analysis & Synthesis" 0 -1 1679994351125 ""}
+{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1  1  Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 1 error, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "13076 " "Peak virtual memory: 13076 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679994351157 ""} { "Error" "EQEXE_END_BANNER_TIME" "Tue Mar 28 05:05:51 2023 " "Processing ended: Tue Mar 28 05:05:51 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679994351157 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:17 " "Elapsed time: 00:00:17" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679994351157 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:39 " "Total CPU time (on all processors): 00:00:39" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679994351157 ""}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1679994351157 ""}
+{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 3 s 1  " "Quartus Prime Full Compilation was unsuccessful. 3 errors, 1 warning" {  } {  } 0 293001 "Quartus Prime %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1679994351875 ""}
diff --git a/cpld/incremental_db/compiled_partitions/GR8RAM.db_info b/cpld/incremental_db/compiled_partitions/GR8RAM.db_info
old mode 100755
new mode 100644
index c41e730..0955bae
--- a/cpld/incremental_db/compiled_partitions/GR8RAM.db_info
+++ b/cpld/incremental_db/compiled_partitions/GR8RAM.db_info
@@ -1,3 +1,3 @@
-Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
-Version_Index = 302049280
-Creation_Time = Thu Mar 18 03:51:58 2021
+Quartus_Version = Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+Version_Index = 503488000
+Creation_Time = Sat Mar 25 19:21:05 2023
diff --git a/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt b/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt
index c535fa4..7381f89 100755
Binary files a/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt and b/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt differ
diff --git a/cpld/output_files/GR8RAM.asm.rpt b/cpld/output_files/GR8RAM.asm.rpt
old mode 100755
new mode 100644
index 37daa67..f69645f
--- a/cpld/output_files/GR8RAM.asm.rpt
+++ b/cpld/output_files/GR8RAM.asm.rpt
@@ -1,6 +1,6 @@
 Assembler report for GR8RAM
-Tue Sep 14 01:35:32 2021
-Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+Tue Mar 28 05:06:37 2023
+Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
 
 
 ---------------------
@@ -10,7 +10,7 @@ Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit
   2. Assembler Summary
   3. Assembler Settings
   4. Assembler Generated Files
-  5. Assembler Device Options: C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.pof
+  5. Assembler Device Options: Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.pof
   6. Assembler Messages
 
 
@@ -18,26 +18,27 @@ Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit
 ----------------
 ; Legal Notice ;
 ----------------
-Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
+Copyright (C) 2019  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
 functions, and any output files from any of the foregoing 
 (including device programming or simulation files), and any 
 associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
 
 
 
 +---------------------------------------------------------------+
 ; Assembler Summary                                             ;
 +-----------------------+---------------------------------------+
-; Assembler Status      ; Successful - Tue Sep 14 01:35:32 2021 ;
+; Assembler Status      ; Successful - Tue Mar 28 05:06:37 2023 ;
 ; Revision Name         ; GR8RAM                                ;
 ; Top-level Entity Name ; GR8RAM                                ;
 ; Family                ; MAX II                                ;
@@ -45,69 +46,46 @@ applicable agreement for further details.
 +-----------------------+---------------------------------------+
 
 
-+---------------------------------------------------------------------------------------------------------+
-; Assembler Settings                                                                                      ;
-+-----------------------------------------------------------------------------+-----------+---------------+
-; Option                                                                      ; Setting   ; Default Value ;
-+-----------------------------------------------------------------------------+-----------+---------------+
-; Use smart compilation                                                       ; Off       ; Off           ;
-; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation  ; On        ; On            ;
-; Enable compact report table                                                 ; Off       ; Off           ;
-; Compression mode                                                            ; Off       ; Off           ;
-; Clock source for configuration device                                       ; Internal  ; Internal      ;
-; Clock frequency of the configuration device                                 ; 10 MHZ    ; 10 MHz        ;
-; Divide clock frequency by                                                   ; 1         ; 1             ;
-; Auto user code                                                              ; On        ; On            ;
-; Security bit                                                                ; Off       ; Off           ;
-; Use configuration device                                                    ; On        ; On            ;
-; Configuration device                                                        ; Auto      ; Auto          ;
-; Configuration device auto user code                                         ; Off       ; Off           ;
-; Generate Tabular Text File (.ttf) For Target Device                         ; Off       ; Off           ;
-; Generate Raw Binary File (.rbf) For Target Device                           ; Off       ; Off           ;
-; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off       ; Off           ;
-; Hexadecimal Output File start address                                       ; 0         ; 0             ;
-; Hexadecimal Output File count direction                                     ; Up        ; Up            ;
-; Generate Serial Vector Format File (.svf) for Target Device                 ; Off       ; Off           ;
-; Generate a JEDEC STAPL Format File (.jam) for Target Device                 ; Off       ; Off           ;
-; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off       ; Off           ;
-; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On        ; On            ;
-; In-System Programming Default Clamp State                                   ; Tri-state ; Tri-state     ;
-+-----------------------------------------------------------------------------+-----------+---------------+
++----------------------------------+
+; Assembler Settings               ;
++--------+---------+---------------+
+; Option ; Setting ; Default Value ;
++--------+---------+---------------+
 
 
-+-------------------------------------------------------------------+
-; Assembler Generated Files                                         ;
-+-------------------------------------------------------------------+
-; File Name                                                         ;
-+-------------------------------------------------------------------+
-; C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.pof ;
-+-------------------------------------------------------------------+
++----------------------------------------------+
+; Assembler Generated Files                    ;
++----------------------------------------------+
+; File Name                                    ;
++----------------------------------------------+
+; Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.pof ;
++----------------------------------------------+
 
 
-+---------------------------------------------------------------------------------------------+
-; Assembler Device Options: C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.pof ;
-+----------------+----------------------------------------------------------------------------+
-; Option         ; Setting                                                                    ;
-+----------------+----------------------------------------------------------------------------+
-; Device         ; EPM240T100C5                                                               ;
-; JTAG usercode  ; 0x00161CF0                                                                 ;
-; Checksum       ; 0x001620E8                                                                 ;
-+----------------+----------------------------------------------------------------------------+
++------------------------------------------------------------------------+
+; Assembler Device Options: Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.pof ;
++----------------+-------------------------------------------------------+
+; Option         ; Setting                                               ;
++----------------+-------------------------------------------------------+
+; JTAG usercode  ; 0x001615F8                                            ;
+; Checksum       ; 0x001618F8                                            ;
++----------------+-------------------------------------------------------+
 
 
 +--------------------+
 ; Assembler Messages ;
 +--------------------+
 Info: *******************************************************************
-Info: Running Quartus II 64-Bit Assembler
-    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
-    Info: Processing started: Tue Sep 14 01:35:31 2021
+Info: Running Quartus Prime Assembler
+    Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+    Info: Processing started: Tue Mar 28 05:06:36 2023
 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
 Info (115031): Writing out detailed assembly data for power analysis
 Info (115030): Assembler is generating device programming files
-Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
-    Info: Peak virtual memory: 381 megabytes
-    Info: Processing ended: Tue Sep 14 01:35:32 2021
+Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
+    Info: Peak virtual memory: 13057 megabytes
+    Info: Processing ended: Tue Mar 28 05:06:37 2023
     Info: Elapsed time: 00:00:01
     Info: Total CPU time (on all processors): 00:00:01
 
diff --git a/cpld/output_files/GR8RAM.done b/cpld/output_files/GR8RAM.done
index 3f077ca..582637b 100755
--- a/cpld/output_files/GR8RAM.done
+++ b/cpld/output_files/GR8RAM.done
@@ -1 +1 @@
-Tue Sep 14 01:35:34 2021
+Tue Mar 28 05:06:40 2023
diff --git a/cpld/output_files/GR8RAM.fit.rpt b/cpld/output_files/GR8RAM.fit.rpt
old mode 100755
new mode 100644
index 60461ed..544622d
--- a/cpld/output_files/GR8RAM.fit.rpt
+++ b/cpld/output_files/GR8RAM.fit.rpt
@@ -1,6 +1,6 @@
 Fitter report for GR8RAM
-Tue Sep 14 01:35:30 2021
-Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+Tue Mar 28 05:06:35 2023
+Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
 
 
 ---------------------
@@ -22,200 +22,212 @@ Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit
  14. Delay Chain Summary
  15. Control Signals
  16. Global & Other Fast Signals
- 17. Non-Global High Fan-Out Signals
- 18. Other Routing Usage Summary
- 19. LAB Logic Elements
- 20. LAB-wide Signals
- 21. LAB Signals Sourced
- 22. LAB Signals Sourced Out
- 23. LAB Distinct Inputs
- 24. Fitter Device Options
- 25. Fitter Messages
- 26. Fitter Suppressed Messages
+ 17. Routing Usage Summary
+ 18. LAB Logic Elements
+ 19. LAB-wide Signals
+ 20. LAB Signals Sourced
+ 21. LAB Signals Sourced Out
+ 22. LAB Distinct Inputs
+ 23. Fitter Device Options
+ 24. Fitter Messages
+ 25. Fitter Suppressed Messages
 
 
 
 ----------------
 ; Legal Notice ;
 ----------------
-Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
+Copyright (C) 2019  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
 functions, and any output files from any of the foregoing 
 (including device programming or simulation files), and any 
 associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
 
 
 
-+-----------------------------------------------------------------------------+
-; Fitter Summary                                                              ;
-+---------------------------+-------------------------------------------------+
-; Fitter Status             ; Successful - Tue Sep 14 01:35:30 2021           ;
-; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
-; Revision Name             ; GR8RAM                                          ;
-; Top-level Entity Name     ; GR8RAM                                          ;
-; Family                    ; MAX II                                          ;
-; Device                    ; EPM240T100C5                                    ;
-; Timing Models             ; Final                                           ;
-; Total logic elements      ; 234 / 240 ( 98 % )                              ;
-; Total pins                ; 80 / 80 ( 100 % )                               ;
-; Total virtual pins        ; 0                                               ;
-; UFM blocks                ; 0 / 1 ( 0 % )                                   ;
-+---------------------------+-------------------------------------------------+
++---------------------------------------------------------------------+
+; Fitter Summary                                                      ;
++-----------------------+---------------------------------------------+
+; Fitter Status         ; Successful - Tue Mar 28 05:06:35 2023       ;
+; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
+; Revision Name         ; GR8RAM                                      ;
+; Top-level Entity Name ; GR8RAM                                      ;
+; Family                ; MAX II                                      ;
+; Device                ; EPM240T100C5                                ;
+; Timing Models         ; Final                                       ;
+; Total logic elements  ; 236 / 240 ( 98 % )                          ;
+; Total pins            ; 80 / 80 ( 100 % )                           ;
+; Total virtual pins    ; 0                                           ;
+; UFM blocks            ; 0 / 1 ( 0 % )                               ;
++-----------------------+---------------------------------------------+
 
 
-+----------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Settings                                                                                                                              ;
-+----------------------------------------------------------------------------+--------------------------------+--------------------------------+
-; Option                                                                     ; Setting                        ; Default Value                  ;
-+----------------------------------------------------------------------------+--------------------------------+--------------------------------+
-; Device                                                                     ; EPM240T100C5                   ;                                ;
-; Minimum Core Junction Temperature                                          ; 0                              ;                                ;
-; Maximum Core Junction Temperature                                          ; 85                             ;                                ;
-; Placement Effort Multiplier                                                ; 2.0                            ; 1.0                            ;
-; Router Effort Multiplier                                                   ; 2.0                            ; 1.0                            ;
-; Fit Attempts to Skip                                                       ; 0                              ; 0.0                            ;
-; Device I/O Standard                                                        ; 3.3-V LVTTL                    ;                                ;
-; Final Placement Optimizations                                              ; Always                         ; Automatically                  ;
-; Fitter Initial Placement Seed                                              ; 235                            ; 1                              ;
-; Fitter Effort                                                              ; Standard Fit                   ; Auto Fit                       ;
-; Auto Register Duplication                                                  ; Off                            ; Auto                           ;
-; Use smart compilation                                                      ; Off                            ; Off                            ;
-; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                             ; On                             ;
-; Enable compact report table                                                ; Off                            ; Off                            ;
-; Router Timing Optimization Level                                           ; Normal                         ; Normal                         ;
-; Always Enable Input Buffers                                                ; Off                            ; Off                            ;
-; Optimize Hold Timing                                                       ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
-; Optimize Multi-Corner Timing                                               ; Off                            ; Off                            ;
-; Guarantee I/O Paths Have Zero Hold Time at Fast Corner                     ; On                             ; On                             ;
-; PowerPlay Power Optimization                                               ; Normal compilation             ; Normal compilation             ;
-; Optimize Timing                                                            ; Normal compilation             ; Normal compilation             ;
-; Optimize Timing for ECOs                                                   ; Off                            ; Off                            ;
-; Regenerate full fit report during ECO compiles                             ; Off                            ; Off                            ;
-; Optimize IOC Register Placement for Timing                                 ; Normal                         ; Normal                         ;
-; Limit to One Fitting Attempt                                               ; Off                            ; Off                            ;
-; Fitter Aggressive Routability Optimizations                                ; Automatically                  ; Automatically                  ;
-; Slow Slew Rate                                                             ; Off                            ; Off                            ;
-; PCI I/O                                                                    ; Off                            ; Off                            ;
-; Weak Pull-Up Resistor                                                      ; Off                            ; Off                            ;
-; Enable Bus-Hold Circuitry                                                  ; Off                            ; Off                            ;
-; Auto Delay Chains                                                          ; On                             ; On                             ;
-; Auto Delay Chains for High Fanout Input Pins                               ; Off                            ; Off                            ;
-; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                            ; Off                            ;
-; Perform Register Duplication for Performance                               ; Off                            ; Off                            ;
-; Perform Register Retiming for Performance                                  ; Off                            ; Off                            ;
-; Perform Asynchronous Signal Pipelining                                     ; Off                            ; Off                            ;
-; Physical Synthesis Effort Level                                            ; Normal                         ; Normal                         ;
-; Logic Cell Insertion - Logic Duplication                                   ; Auto                           ; Auto                           ;
-; Auto Global Clock                                                          ; On                             ; On                             ;
-; Auto Global Register Control Signals                                       ; On                             ; On                             ;
-; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                            ; Off                            ;
-+----------------------------------------------------------------------------+--------------------------------+--------------------------------+
++--------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings                                                                                                                      ;
++--------------------------------------------------------------------+--------------------------------+--------------------------------+
+; Option                                                             ; Setting                        ; Default Value                  ;
++--------------------------------------------------------------------+--------------------------------+--------------------------------+
+; Device                                                             ; EPM240T100C5                   ;                                ;
+; Minimum Core Junction Temperature                                  ; 0                              ;                                ;
+; Maximum Core Junction Temperature                                  ; 85                             ;                                ;
+; Placement Effort Multiplier                                        ; 2.0                            ; 1.0                            ;
+; Router Effort Multiplier                                           ; 2.0                            ; 1.0                            ;
+; Fit Attempts to Skip                                               ; 0                              ; 0.0                            ;
+; Device I/O Standard                                                ; 3.3-V LVTTL                    ;                                ;
+; Final Placement Optimizations                                      ; Always                         ; Automatically                  ;
+; Fitter Initial Placement Seed                                      ; 235                            ; 1                              ;
+; Fitter Effort                                                      ; Standard Fit                   ; Auto Fit                       ;
+; Auto Register Duplication                                          ; Off                            ; Auto                           ;
+; Use smart compilation                                              ; Off                            ; Off                            ;
+; Enable parallel Assembler and Timing Analyzer during compilation   ; On                             ; On                             ;
+; Enable compact report table                                        ; Off                            ; Off                            ;
+; Router Timing Optimization Level                                   ; Normal                         ; Normal                         ;
+; Always Enable Input Buffers                                        ; Off                            ; Off                            ;
+; Optimize Hold Timing                                               ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
+; Optimize Multi-Corner Timing                                       ; Off                            ; Off                            ;
+; Guarantee I/O Paths Have Zero Hold Time at Fast Corner             ; On                             ; On                             ;
+; Power Optimization During Fitting                                  ; Normal compilation             ; Normal compilation             ;
+; Optimize Timing                                                    ; Normal compilation             ; Normal compilation             ;
+; Optimize Timing for ECOs                                           ; Off                            ; Off                            ;
+; Regenerate Full Fit Report During ECO Compiles                     ; Off                            ; Off                            ;
+; Optimize IOC Register Placement for Timing                         ; Normal                         ; Normal                         ;
+; Limit to One Fitting Attempt                                       ; Off                            ; Off                            ;
+; Fitter Aggressive Routability Optimizations                        ; Automatically                  ; Automatically                  ;
+; Periphery to Core Placement and Routing Optimization               ; Off                            ; Off                            ;
+; Slow Slew Rate                                                     ; Off                            ; Off                            ;
+; PCI I/O                                                            ; Off                            ; Off                            ;
+; Weak Pull-Up Resistor                                              ; Off                            ; Off                            ;
+; Enable Bus-Hold Circuitry                                          ; Off                            ; Off                            ;
+; Auto Delay Chains                                                  ; On                             ; On                             ;
+; Auto Delay Chains for High Fanout Input Pins                       ; Off                            ; Off                            ;
+; Perform Physical Synthesis for Combinational Logic for Performance ; Off                            ; Off                            ;
+; Perform Register Duplication for Performance                       ; Off                            ; Off                            ;
+; Perform Register Retiming for Performance                          ; Off                            ; Off                            ;
+; Perform Asynchronous Signal Pipelining                             ; Off                            ; Off                            ;
+; Physical Synthesis Effort Level                                    ; Normal                         ; Normal                         ;
+; Logic Cell Insertion - Logic Duplication                           ; Auto                           ; Auto                           ;
+; Auto Global Clock                                                  ; On                             ; On                             ;
+; Auto Global Register Control Signals                               ; On                             ; On                             ;
+; Force Fitter to Avoid Periphery Placement Warnings                 ; Off                            ; Off                            ;
++--------------------------------------------------------------------+--------------------------------+--------------------------------+
 
 
-Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
-+-------------------------------------+
-; Parallel Compilation                ;
-+----------------------------+--------+
-; Processors                 ; Number ;
-+----------------------------+--------+
-; Number detected on machine ; 12     ;
-; Maximum allowed            ; 1      ;
-+----------------------------+--------+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 4           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.04        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processor 2            ;   1.6%      ;
+;     Processors 3-4         ;   1.2%      ;
++----------------------------+-------------+
 
 
 +--------------+
 ; Pin-Out File ;
 +--------------+
-The pin-out file can be found in C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.pin.
+The pin-out file can be found in Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin.
 
 
-+------------------------------------------------------------------+
-; Fitter Resource Usage Summary                                    ;
-+---------------------------------------------+--------------------+
-; Resource                                    ; Usage              ;
-+---------------------------------------------+--------------------+
-; Total logic elements                        ; 234 / 240 ( 98 % ) ;
-;     -- Combinational with no register       ; 113                ;
-;     -- Register only                        ; 1                  ;
-;     -- Combinational with a register        ; 120                ;
-;                                             ;                    ;
-; Logic element usage by number of LUT inputs ;                    ;
-;     -- 4 input functions                    ; 126                ;
-;     -- 3 input functions                    ; 41                 ;
-;     -- 2 input functions                    ; 65                 ;
-;     -- 1 input functions                    ; 0                  ;
-;     -- 0 input functions                    ; 1                  ;
-;                                             ;                    ;
-; Logic elements by mode                      ;                    ;
-;     -- normal mode                          ; 201                ;
-;     -- arithmetic mode                      ; 33                 ;
-;     -- qfbk mode                            ; 18                 ;
-;     -- register cascade mode                ; 0                  ;
-;     -- synchronous clear/load mode          ; 67                 ;
-;     -- asynchronous clear/load mode         ; 29                 ;
-;                                             ;                    ;
-; Total registers                             ; 121 / 240 ( 50 % ) ;
-; Total LABs                                  ; 24 / 24 ( 100 % )  ;
-; Logic elements in carry chains              ; 37                 ;
-; Virtual pins                                ; 0                  ;
-; I/O pins                                    ; 80 / 80 ( 100 % )  ;
-;     -- Clock pins                           ; 4 / 4 ( 100 % )    ;
-;                                             ;                    ;
-; Global signals                              ; 3                  ;
-; UFM blocks                                  ; 0 / 1 ( 0 % )      ;
-; Global clocks                               ; 3 / 4 ( 75 % )     ;
-; JTAGs                                       ; 0 / 1 ( 0 % )      ;
-; Average interconnect usage (total/H/V)      ; 40% / 44% / 37%    ;
-; Peak interconnect usage (total/H/V)         ; 40% / 44% / 37%    ;
-; Maximum fan-out                             ; 107                ;
-; Highest non-global fan-out                  ; 47                 ;
-; Total fan-out                               ; 1091               ;
-; Average fan-out                             ; 3.47               ;
-+---------------------------------------------+--------------------+
++---------------------------------------------------------------------+
+; Fitter Resource Usage Summary                                       ;
++---------------------------------------------+-----------------------+
+; Resource                                    ; Usage                 ;
++---------------------------------------------+-----------------------+
+; Total logic elements                        ; 236 / 240 ( 98 % )    ;
+;     -- Combinational with no register       ; 119                   ;
+;     -- Register only                        ; 1                     ;
+;     -- Combinational with a register        ; 116                   ;
+;                                             ;                       ;
+; Logic element usage by number of LUT inputs ;                       ;
+;     -- 4 input functions                    ; 137                   ;
+;     -- 3 input functions                    ; 35                    ;
+;     -- 2 input functions                    ; 63                    ;
+;     -- 1 input functions                    ; 0                     ;
+;     -- 0 input functions                    ; 0                     ;
+;                                             ;                       ;
+; Logic elements by mode                      ;                       ;
+;     -- normal mode                          ; 203                   ;
+;     -- arithmetic mode                      ; 33                    ;
+;     -- qfbk mode                            ; 15                    ;
+;     -- register cascade mode                ; 0                     ;
+;     -- synchronous clear/load mode          ; 64                    ;
+;     -- asynchronous clear/load mode         ; 29                    ;
+;                                             ;                       ;
+; Total registers                             ; 117 / 240 ( 49 % )    ;
+; Total LABs                                  ; 24 / 24 ( 100 % )     ;
+; Logic elements in carry chains              ; 37                    ;
+; Virtual pins                                ; 0                     ;
+; I/O pins                                    ; 80 / 80 ( 100 % )     ;
+;     -- Clock pins                           ; 4 / 4 ( 100 % )       ;
+;                                             ;                       ;
+; UFM blocks                                  ; 0 / 1 ( 0 % )         ;
+;                                             ;                       ;
+;     -- Total Fixed Point DSP Blocks         ; 0                     ;
+;     -- Total Floating Point DSP Blocks      ; 0                     ;
+;                                             ;                       ;
+; Global signals                              ; 3                     ;
+;     -- Global clocks                        ; 3 / 4 ( 75 % )        ;
+; JTAGs                                       ; 0 / 1 ( 0 % )         ;
+; Average interconnect usage (total/H/V)      ; 38.7% / 42.5% / 34.6% ;
+; Peak interconnect usage (total/H/V)         ; 38.7% / 42.5% / 34.6% ;
+; Maximum fan-out                             ; 103                   ;
+; Highest non-global fan-out                  ; 53                    ;
+; Total fan-out                               ; 1101                  ;
+; Average fan-out                             ; 3.48                  ;
++---------------------------------------------+-----------------------+
 
 
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Input Pins                                                                                                                                                                                                                    ;
-+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+----------------------------+----------------------+
-; Name     ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard               ; Location assigned by ;
-+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+----------------------------+----------------------+
-; C25M     ; 64    ; 2        ; 8            ; 3            ; 4           ; 107                   ; 0                  ; yes    ; no              ; no       ; Off          ; 3.3-V LVTTL                ; User                 ;
-; DMAin    ; 48    ; 1        ; 6            ; 0            ; 0           ; 1                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVTTL                ; User                 ;
-; INTin    ; 49    ; 1        ; 7            ; 0            ; 2           ; 1                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVTTL                ; User                 ;
-; MISO     ; 16    ; 1        ; 1            ; 2            ; 2           ; 1                     ; 0                  ; no     ; no              ; yes      ; Off          ; 3.3-V LVTTL                ; User                 ;
-; PHI0     ; 41    ; 1        ; 5            ; 0            ; 1           ; 16                    ; 0                  ; yes    ; no              ; no       ; Off          ; 3.3V Schmitt Trigger Input ; User                 ;
-; RA[0]    ; 100   ; 2        ; 2            ; 5            ; 2           ; 2                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVTTL                ; User                 ;
-; RA[10]   ; 14    ; 1        ; 1            ; 2            ; 0           ; 2                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVTTL                ; User                 ;
-; RA[11]   ; 34    ; 1        ; 3            ; 0            ; 1           ; 1                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVTTL                ; User                 ;
-; RA[12]   ; 35    ; 1        ; 3            ; 0            ; 0           ; 1                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVTTL                ; User                 ;
-; RA[13]   ; 36    ; 1        ; 4            ; 0            ; 2           ; 1                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVTTL                ; User                 ;
-; RA[14]   ; 37    ; 1        ; 4            ; 0            ; 1           ; 1                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVTTL                ; User                 ;
-; RA[15]   ; 38    ; 1        ; 4            ; 0            ; 0           ; 1                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVTTL                ; User                 ;
-; RA[1]    ; 98    ; 2        ; 2            ; 5            ; 0           ; 2                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVTTL                ; User                 ;
-; RA[2]    ; 97    ; 2        ; 3            ; 5            ; 3           ; 2                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVTTL                ; User                 ;
-; RA[3]    ; 4     ; 1        ; 1            ; 4            ; 2           ; 2                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVTTL                ; User                 ;
-; RA[4]    ; 1     ; 2        ; 2            ; 5            ; 3           ; 2                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVTTL                ; User                 ;
-; RA[5]    ; 2     ; 1        ; 1            ; 4            ; 0           ; 2                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVTTL                ; User                 ;
-; RA[6]    ; 3     ; 1        ; 1            ; 4            ; 1           ; 2                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVTTL                ; User                 ;
-; RA[7]    ; 6     ; 1        ; 1            ; 3            ; 0           ; 2                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVTTL                ; User                 ;
-; RA[8]    ; 7     ; 1        ; 1            ; 3            ; 1           ; 2                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVTTL                ; User                 ;
-; RA[9]    ; 8     ; 1        ; 1            ; 3            ; 2           ; 2                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVTTL                ; User                 ;
-; SetFW[0] ; 96    ; 2        ; 3            ; 5            ; 2           ; 1                     ; 0                  ; no     ; no              ; no       ; On           ; 3.3V Schmitt Trigger Input ; User                 ;
-; SetFW[1] ; 95    ; 2        ; 3            ; 5            ; 1           ; 1                     ; 0                  ; no     ; no              ; no       ; On           ; 3.3V Schmitt Trigger Input ; User                 ;
-; nDEVSEL  ; 40    ; 1        ; 5            ; 0            ; 2           ; 4                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3V Schmitt Trigger Input ; User                 ;
-; nIOSEL   ; 39    ; 1        ; 5            ; 0            ; 3           ; 3                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3V Schmitt Trigger Input ; User                 ;
-; nIOSTRB  ; 42    ; 1        ; 5            ; 0            ; 0           ; 3                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3V Schmitt Trigger Input ; User                 ;
-; nRES     ; 44    ; 1        ; 6            ; 0            ; 2           ; 1                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3V Schmitt Trigger Input ; User                 ;
-; nWE      ; 43    ; 1        ; 6            ; 0            ; 3           ; 2                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3V Schmitt Trigger Input ; User                 ;
-+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+----------------------------+----------------------+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins                                                                                                                                                                                                                                     ;
++----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+----------------------------+----------------------+----------------+
+; Name     ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard               ; Location assigned by ; Slow Slew Rate ;
++----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+----------------------------+----------------------+----------------+
+; C25M     ; 64    ; 2        ; 8            ; 3            ; 4           ; 103                   ; 0                  ; yes    ; no              ; no       ; Off          ; 3.3-V LVTTL                ; User                 ; no             ;
+; DMAin    ; 48    ; 1        ; 6            ; 0            ; 0           ; 1                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVTTL                ; User                 ; no             ;
+; INTin    ; 49    ; 1        ; 7            ; 0            ; 2           ; 1                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVTTL                ; User                 ; no             ;
+; MISO     ; 16    ; 1        ; 1            ; 2            ; 2           ; 2                     ; 0                  ; no     ; no              ; yes      ; Off          ; 3.3-V LVTTL                ; User                 ; no             ;
+; PHI0     ; 41    ; 1        ; 5            ; 0            ; 1           ; 15                    ; 0                  ; yes    ; no              ; no       ; Off          ; 3.3V Schmitt Trigger Input ; User                 ; no             ;
+; RA[0]    ; 100   ; 2        ; 2            ; 5            ; 2           ; 2                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVTTL                ; User                 ; no             ;
+; RA[10]   ; 14    ; 1        ; 1            ; 2            ; 0           ; 2                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVTTL                ; User                 ; no             ;
+; RA[11]   ; 34    ; 1        ; 3            ; 0            ; 1           ; 1                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVTTL                ; User                 ; no             ;
+; RA[12]   ; 35    ; 1        ; 3            ; 0            ; 0           ; 1                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVTTL                ; User                 ; no             ;
+; RA[13]   ; 36    ; 1        ; 4            ; 0            ; 2           ; 1                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVTTL                ; User                 ; no             ;
+; RA[14]   ; 37    ; 1        ; 4            ; 0            ; 1           ; 1                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVTTL                ; User                 ; no             ;
+; RA[15]   ; 38    ; 1        ; 4            ; 0            ; 0           ; 1                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVTTL                ; User                 ; no             ;
+; RA[1]    ; 98    ; 2        ; 2            ; 5            ; 0           ; 2                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVTTL                ; User                 ; no             ;
+; RA[2]    ; 97    ; 2        ; 3            ; 5            ; 3           ; 2                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVTTL                ; User                 ; no             ;
+; RA[3]    ; 4     ; 1        ; 1            ; 4            ; 2           ; 2                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVTTL                ; User                 ; no             ;
+; RA[4]    ; 1     ; 2        ; 2            ; 5            ; 3           ; 2                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVTTL                ; User                 ; no             ;
+; RA[5]    ; 2     ; 1        ; 1            ; 4            ; 0           ; 2                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVTTL                ; User                 ; no             ;
+; RA[6]    ; 3     ; 1        ; 1            ; 4            ; 1           ; 2                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVTTL                ; User                 ; no             ;
+; RA[7]    ; 6     ; 1        ; 1            ; 3            ; 0           ; 2                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVTTL                ; User                 ; no             ;
+; RA[8]    ; 7     ; 1        ; 1            ; 3            ; 1           ; 2                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVTTL                ; User                 ; no             ;
+; RA[9]    ; 8     ; 1        ; 1            ; 3            ; 2           ; 2                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3-V LVTTL                ; User                 ; no             ;
+; SetFW[0] ; 96    ; 2        ; 3            ; 5            ; 2           ; 0                     ; 0                  ; no     ; no              ; no       ; On           ; 3.3V Schmitt Trigger Input ; User                 ; no             ;
+; SetFW[1] ; 95    ; 2        ; 3            ; 5            ; 1           ; 0                     ; 0                  ; no     ; no              ; no       ; On           ; 3.3V Schmitt Trigger Input ; User                 ; no             ;
+; nDEVSEL  ; 40    ; 1        ; 5            ; 0            ; 2           ; 5                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3V Schmitt Trigger Input ; User                 ; no             ;
+; nIOSEL   ; 39    ; 1        ; 5            ; 0            ; 3           ; 4                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3V Schmitt Trigger Input ; User                 ; no             ;
+; nIOSTRB  ; 42    ; 1        ; 5            ; 0            ; 0           ; 3                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3V Schmitt Trigger Input ; User                 ; no             ;
+; nRES     ; 44    ; 1        ; 6            ; 0            ; 2           ; 1                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3V Schmitt Trigger Input ; User                 ; no             ;
+; nWE      ; 43    ; 1        ; 6            ; 0            ; 3           ; 2                     ; 0                  ; no     ; no              ; no       ; Off          ; 3.3V Schmitt Trigger Input ; User                 ; no             ;
++----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+----------------------------+----------------------+----------------+
 
 
 +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
@@ -226,13 +238,13 @@ The pin-out file can be found in C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/outpu
 ; DMAout  ; 18    ; 1        ; 1            ; 1            ; 0           ; no              ; no             ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
 ; DQMH    ; 57    ; 2        ; 8            ; 2            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
 ; DQML    ; 85    ; 2        ; 5            ; 5            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; FCK     ; 12    ; 1        ; 1            ; 3            ; 3           ; no              ; yes            ; no              ; no         ; yes           ; yes      ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; FCK     ; 12    ; 1        ; 1            ; 3            ; 3           ; no              ; yes            ; no              ; no         ; no            ; yes      ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
 ; INTout  ; 20    ; 1        ; 1            ; 1            ; 2           ; no              ; no             ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
 ; RAdir   ; 19    ; 1        ; 1            ; 1            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; On           ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
 ; RCKE    ; 66    ; 2        ; 8            ; 3            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
 ; RDdir   ; 17    ; 1        ; 1            ; 2            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; On           ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
 ; RWout   ; 33    ; 1        ; 3            ; 0            ; 2           ; no              ; no             ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; SA[0]   ; 75    ; 2        ; 7            ; 5            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
+; SA[0]   ; 75    ; 2        ; 7            ; 5            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
 ; SA[10]  ; 73    ; 2        ; 8            ; 4            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
 ; SA[11]  ; 70    ; 2        ; 8            ; 4            ; 4           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
 ; SA[12]  ; 68    ; 2        ; 8            ; 3            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
@@ -240,7 +252,7 @@ The pin-out file can be found in C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/outpu
 ; SA[2]   ; 82    ; 2        ; 6            ; 5            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
 ; SA[3]   ; 84    ; 2        ; 6            ; 5            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
 ; SA[4]   ; 76    ; 2        ; 7            ; 5            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; SA[5]   ; 83    ; 2        ; 6            ; 5            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; SA[5]   ; 83    ; 2        ; 6            ; 5            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
 ; SA[6]   ; 77    ; 2        ; 7            ; 5            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
 ; SA[7]   ; 78    ; 2        ; 7            ; 5            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
 ; SA[8]   ; 74    ; 2        ; 8            ; 4            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
@@ -249,14 +261,14 @@ The pin-out file can be found in C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/outpu
 ; SBA[1]  ; 71    ; 2        ; 8            ; 4            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
 ; nCAS    ; 61    ; 2        ; 8            ; 2            ; 1           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
 ; nDMAout ; 21    ; 1        ; 1            ; 1            ; 3           ; no              ; no             ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; nFCS    ; 5     ; 1        ; 1            ; 4            ; 3           ; no              ; yes            ; no              ; no         ; yes           ; no       ; On           ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; nFCS    ; 5     ; 1        ; 1            ; 4            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; On           ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
 ; nINHout ; 27    ; 1        ; 2            ; 0            ; 2           ; no              ; no             ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
 ; nIRQout ; 29    ; 1        ; 2            ; 0            ; 0           ; no              ; no             ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
 ; nNMIout ; 26    ; 1        ; 2            ; 0            ; 3           ; no              ; no             ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
 ; nRAS    ; 62    ; 2        ; 8            ; 2            ; 0           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
 ; nRCS    ; 67    ; 2        ; 8            ; 3            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
 ; nRDYout ; 28    ; 1        ; 2            ; 0            ; 1           ; no              ; no             ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
-; nRESout ; 30    ; 1        ; 3            ; 0            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; On           ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
+; nRESout ; 30    ; 1        ; 3            ; 0            ; 3           ; no              ; yes            ; no              ; no         ; no            ; no       ; On           ; 3.3-V LVTTL  ; 8mA              ; yes                    ; User                 ; 10 pF ; -                    ; -                   ;
 ; nSWE    ; 58    ; 2        ; 8            ; 2            ; 2           ; no              ; yes            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; -                    ; -                   ;
 +---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
 
@@ -267,12 +279,12 @@ The pin-out file can be found in C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/outpu
 ; Name  ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load  ; Output Enable Source ; Output Enable Group ;
 +-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
 ; MOSI  ; 15    ; 1        ; 1            ; 2            ; 1           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; yes      ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; MOSIOE               ; -                   ;
-; RD[0] ; 86    ; 2        ; 5            ; 5            ; 1           ; 5                     ; 0                  ; no     ; no              ; no             ; no              ; no         ; yes      ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; comb~2               ; -                   ;
-; RD[1] ; 87    ; 2        ; 5            ; 5            ; 2           ; 4                     ; 0                  ; no     ; no              ; no             ; no              ; no         ; yes      ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; comb~2               ; -                   ;
+; RD[0] ; 86    ; 2        ; 5            ; 5            ; 1           ; 6                     ; 0                  ; no     ; no              ; no             ; no              ; no         ; yes      ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; comb~2               ; -                   ;
+; RD[1] ; 87    ; 2        ; 5            ; 5            ; 2           ; 5                     ; 0                  ; no     ; no              ; no             ; no              ; no         ; yes      ; Off          ; 3.3-V LVTTL  ; 8mA              ; yes                    ; User                 ; 10 pF ; comb~2               ; -                   ;
 ; RD[2] ; 88    ; 2        ; 5            ; 5            ; 3           ; 4                     ; 0                  ; no     ; no              ; no             ; no              ; no         ; yes      ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; comb~2               ; -                   ;
-; RD[3] ; 89    ; 2        ; 4            ; 5            ; 0           ; 4                     ; 0                  ; no     ; no              ; no             ; no              ; no         ; yes      ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; comb~2               ; -                   ;
+; RD[3] ; 89    ; 2        ; 4            ; 5            ; 0           ; 4                     ; 0                  ; no     ; no              ; no             ; no              ; no         ; yes      ; Off          ; 3.3-V LVTTL  ; 8mA              ; yes                    ; User                 ; 10 pF ; comb~2               ; -                   ;
 ; RD[4] ; 90    ; 2        ; 4            ; 5            ; 1           ; 4                     ; 0                  ; no     ; no              ; no             ; no              ; no         ; yes      ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; comb~2               ; -                   ;
-; RD[5] ; 91    ; 2        ; 4            ; 5            ; 2           ; 4                     ; 0                  ; no     ; no              ; no             ; no              ; no         ; yes      ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; comb~2               ; -                   ;
+; RD[5] ; 91    ; 2        ; 4            ; 5            ; 2           ; 4                     ; 0                  ; no     ; no              ; no             ; no              ; no         ; yes      ; Off          ; 3.3-V LVTTL  ; 8mA              ; yes                    ; User                 ; 10 pF ; comb~2               ; -                   ;
 ; RD[6] ; 92    ; 2        ; 3            ; 5            ; 0           ; 4                     ; 0                  ; no     ; no              ; no             ; no              ; no         ; yes      ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; comb~2               ; -                   ;
 ; RD[7] ; 99    ; 2        ; 2            ; 5            ; 1           ; 6                     ; 0                  ; no     ; no              ; no             ; no              ; no         ; yes      ; Off          ; 3.3-V LVTTL  ; 8mA              ; no                     ; User                 ; 10 pF ; comb~2               ; -                   ;
 ; SD[0] ; 50    ; 1        ; 7            ; 0            ; 1           ; 1                     ; 0                  ; no     ; no              ; yes            ; no              ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; no                     ; User                 ; 10 pF ; SDOE                 ; -                   ;
@@ -421,13 +433,13 @@ Note: Pin directions (input, output or bidir) are based on device operating in u
 Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.
 
 
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Resource Utilization by Entity                                                                                                                                                                                ;
-+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
-; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
-+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
-; |GR8RAM                    ; 234 (234)   ; 121          ; 0          ; 80   ; 0            ; 113 (113)    ; 1 (1)             ; 120 (120)        ; 37 (37)         ; 22 (22)    ; |GR8RAM             ; work         ;
-+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity                                                                                                                                                                                              ;
++----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+
+; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
++----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+
+; |GR8RAM                    ; 236 (236)   ; 117          ; 0          ; 80   ; 0            ; 119 (119)    ; 1 (1)             ; 116 (116)        ; 37 (37)         ; 20 (20)    ; |GR8RAM             ; GR8RAM      ; work         ;
++----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+
 Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
 
 
@@ -436,35 +448,9 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 +----------+----------+---------------+
 ; Name     ; Pin Type ; Pad to Core 0 ;
 +----------+----------+---------------+
-; INTin    ; Input    ; (1)           ;
-; DMAin    ; Input    ; (1)           ;
-; PHI0     ; Input    ; (0)           ;
-; nWE      ; Input    ; (1)           ;
-; RA[0]    ; Input    ; (1)           ;
-; RA[1]    ; Input    ; (1)           ;
-; RA[2]    ; Input    ; (1)           ;
-; RA[3]    ; Input    ; (1)           ;
-; RA[4]    ; Input    ; (1)           ;
-; RA[5]    ; Input    ; (1)           ;
-; RA[6]    ; Input    ; (1)           ;
-; RA[7]    ; Input    ; (1)           ;
-; RA[8]    ; Input    ; (1)           ;
-; RA[9]    ; Input    ; (1)           ;
-; RA[10]   ; Input    ; (1)           ;
-; nIOSTRB  ; Input    ; (1)           ;
-; nIOSEL   ; Input    ; (1)           ;
-; nDEVSEL  ; Input    ; (1)           ;
-; C25M     ; Input    ; (0)           ;
-; RA[11]   ; Input    ; (1)           ;
-; RA[14]   ; Input    ; (1)           ;
-; RA[15]   ; Input    ; (1)           ;
-; RA[12]   ; Input    ; (1)           ;
-; RA[13]   ; Input    ; (1)           ;
-; SetFW[1] ; Input    ; (1)           ;
-; SetFW[0] ; Input    ; (1)           ;
-; nRES     ; Input    ; (1)           ;
-; MISO     ; Input    ; (1)           ;
 ; nRESout  ; Output   ; --            ;
+; SetFW[0] ; Input    ; (0)           ;
+; SetFW[1] ; Input    ; (0)           ;
 ; INTout   ; Output   ; --            ;
 ; DMAout   ; Output   ; --            ;
 ; nNMIout  ; Output   ; --            ;
@@ -516,30 +502,54 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 ; SD[6]    ; Bidir    ; (1)           ;
 ; SD[7]    ; Bidir    ; (1)           ;
 ; MOSI     ; Bidir    ; (1)           ;
+; INTin    ; Input    ; (1)           ;
+; DMAin    ; Input    ; (1)           ;
+; PHI0     ; Input    ; (0)           ;
+; nWE      ; Input    ; (1)           ;
+; RA[0]    ; Input    ; (1)           ;
+; RA[1]    ; Input    ; (1)           ;
+; RA[2]    ; Input    ; (1)           ;
+; RA[3]    ; Input    ; (1)           ;
+; RA[4]    ; Input    ; (1)           ;
+; RA[5]    ; Input    ; (1)           ;
+; RA[6]    ; Input    ; (1)           ;
+; RA[7]    ; Input    ; (1)           ;
+; RA[8]    ; Input    ; (1)           ;
+; RA[9]    ; Input    ; (1)           ;
+; RA[10]   ; Input    ; (1)           ;
+; nIOSTRB  ; Input    ; (1)           ;
+; nIOSEL   ; Input    ; (1)           ;
+; nDEVSEL  ; Input    ; (1)           ;
+; C25M     ; Input    ; (0)           ;
+; RA[11]   ; Input    ; (1)           ;
+; RA[14]   ; Input    ; (1)           ;
+; RA[15]   ; Input    ; (1)           ;
+; RA[12]   ; Input    ; (1)           ;
+; RA[13]   ; Input    ; (1)           ;
+; nRES     ; Input    ; (1)           ;
+; MISO     ; Input    ; (1)           ;
 +----------+----------+---------------+
 
 
-+--------------------------------------------------------------------------------------------------------------------------------+
-; Control Signals                                                                                                                ;
-+-------------+-------------+---------+---------------------------------------+--------+----------------------+------------------+
-; Name        ; Location    ; Fan-Out ; Usage                                 ; Global ; Global Resource Used ; Global Line Name ;
-+-------------+-------------+---------+---------------------------------------+--------+----------------------+------------------+
-; C25M        ; PIN_64      ; 107     ; Clock                                 ; yes    ; Global Clock         ; GCLK3            ;
-; Equal20~0   ; LC_X7_Y2_N8 ; 8       ; Clock enable                          ; no     ; --                   ; --               ;
-; Equal2~1    ; LC_X3_Y2_N5 ; 19      ; Clock enable                          ; no     ; --                   ; --               ;
-; FCKOE       ; LC_X2_Y2_N8 ; 2       ; Output enable                         ; no     ; --                   ; --               ;
-; MOSIOE      ; LC_X2_Y2_N4 ; 1       ; Output enable                         ; no     ; --                   ; --               ;
-; PHI0        ; PIN_41      ; 16      ; Clock                                 ; yes    ; Global Clock         ; GCLK2            ;
-; PS[0]       ; LC_X3_Y2_N8 ; 46      ; Clock enable, Sync. clear, Sync. load ; no     ; --                   ; --               ;
-; PS[2]       ; LC_X3_Y2_N9 ; 27      ; Sync. clear, Sync. load               ; no     ; --                   ; --               ;
-; SDOE        ; LC_X4_Y2_N1 ; 8       ; Output enable                         ; no     ; --                   ; --               ;
-; SetFWLoaded ; LC_X7_Y3_N6 ; 2       ; Clock enable                          ; no     ; --                   ; --               ;
-; always9~2   ; LC_X4_Y4_N9 ; 8       ; Sync. load                            ; no     ; --                   ; --               ;
-; always9~3   ; LC_X4_Y4_N8 ; 9       ; Sync. load                            ; no     ; --                   ; --               ;
-; always9~4   ; LC_X5_Y4_N8 ; 9       ; Sync. load                            ; no     ; --                   ; --               ;
-; comb~2      ; LC_X3_Y3_N9 ; 9       ; Output enable                         ; no     ; --                   ; --               ;
-; nRESr       ; LC_X7_Y3_N2 ; 30      ; Async. clear, Sync. clear             ; yes    ; Global Clock         ; GCLK1            ;
-+-------------+-------------+---------+---------------------------------------+--------+----------------------+------------------+
++------------------------------------------------------------------------------------------------------------------------------+
+; Control Signals                                                                                                              ;
++-----------+-------------+---------+---------------------------------------+--------+----------------------+------------------+
+; Name      ; Location    ; Fan-Out ; Usage                                 ; Global ; Global Resource Used ; Global Line Name ;
++-----------+-------------+---------+---------------------------------------+--------+----------------------+------------------+
+; C25M      ; PIN_64      ; 103     ; Clock                                 ; yes    ; Global Clock         ; GCLK3            ;
+; Equal1~0  ; LC_X7_Y3_N5 ; 19      ; Clock enable                          ; no     ; --                   ; --               ;
+; Equal22~1 ; LC_X6_Y4_N6 ; 8       ; Clock enable                          ; no     ; --                   ; --               ;
+; MOSIOE    ; LC_X4_Y1_N9 ; 1       ; Output enable                         ; no     ; --                   ; --               ;
+; PHI0      ; PIN_41      ; 15      ; Clock                                 ; yes    ; Global Clock         ; GCLK2            ;
+; PS[0]     ; LC_X6_Y4_N5 ; 52      ; Clock enable, Sync. clear, Sync. load ; no     ; --                   ; --               ;
+; PS[2]     ; LC_X7_Y3_N1 ; 29      ; Sync. clear, Sync. load               ; no     ; --                   ; --               ;
+; SDOE      ; LC_X7_Y1_N5 ; 8       ; Output enable                         ; no     ; --                   ; --               ;
+; always8~2 ; LC_X6_Y2_N5 ; 8       ; Sync. load                            ; no     ; --                   ; --               ;
+; always8~3 ; LC_X6_Y2_N2 ; 9       ; Sync. load                            ; no     ; --                   ; --               ;
+; always8~4 ; LC_X5_Y2_N4 ; 9       ; Sync. load                            ; no     ; --                   ; --               ;
+; comb~2    ; LC_X5_Y2_N1 ; 9       ; Output enable                         ; no     ; --                   ; --               ;
+; nRESr     ; LC_X4_Y2_N9 ; 31      ; Async. clear, Sync. clear             ; yes    ; Global Clock         ; GCLK1            ;
++-----------+-------------+---------+---------------------------------------+--------+----------------------+------------------+
 
 
 +-------------------------------------------------------------------------+
@@ -547,397 +557,31 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 +-------+-------------+---------+----------------------+------------------+
 ; Name  ; Location    ; Fan-Out ; Global Resource Used ; Global Line Name ;
 +-------+-------------+---------+----------------------+------------------+
-; C25M  ; PIN_64      ; 107     ; Global Clock         ; GCLK3            ;
-; PHI0  ; PIN_41      ; 16      ; Global Clock         ; GCLK2            ;
-; nRESr ; LC_X7_Y3_N2 ; 30      ; Global Clock         ; GCLK1            ;
+; C25M  ; PIN_64      ; 103     ; Global Clock         ; GCLK3            ;
+; PHI0  ; PIN_41      ; 15      ; Global Clock         ; GCLK2            ;
+; nRESr ; LC_X4_Y2_N9 ; 31      ; Global Clock         ; GCLK1            ;
 +-------+-------------+---------+----------------------+------------------+
 
 
-+---------------------------------+
-; Non-Global High Fan-Out Signals ;
-+---------------------+-----------+
-; Name                ; Fan-Out   ;
-+---------------------+-----------+
-; PS[0]               ; 47        ;
-; PS[1]               ; 33        ;
-; PS[3]               ; 29        ;
-; PS[2]               ; 27        ;
-; IS.state_bit_0      ; 20        ;
-; Equal2~1            ; 19        ;
-; IS.state_bit_1      ; 17        ;
-; IS.110~0            ; 16        ;
-; RAMSpecSEL~0        ; 16        ;
-; LS[0]               ; 13        ;
-; RDD[1]~23           ; 9         ;
-; always9~4           ; 9         ;
-; always9~3           ; 9         ;
-; comb~2              ; 9         ;
-; RDD[1]~22           ; 8         ;
-; Equal20~0           ; 8         ;
-; SDOE                ; 8         ;
-; always9~2           ; 8         ;
-; IS.state_bit_2      ; 8         ;
-; LS[2]               ; 8         ;
-; RAr[0]              ; 8         ;
-; SA[1]~6             ; 7         ;
-; SetFWr[1]           ; 7         ;
-; RAr[1]              ; 7         ;
-; RD[7]~7             ; 6         ;
-; SA[3]~9             ; 6         ;
-; SA[3]~8             ; 6         ;
-; SA[3]~7             ; 6         ;
-; LS[1]               ; 6         ;
-; Equal19~0           ; 6         ;
-; RD[0]~0             ; 5         ;
-; RDD[4]~12           ; 5         ;
-; Addr[0]             ; 5         ;
-; LS[6]~17            ; 5         ;
-; SA[1]~5             ; 5         ;
-; LS[1]~3             ; 5         ;
-; Mux14~2             ; 5         ;
-; Addr[23]            ; 5         ;
-; always9~0           ; 5         ;
-; RAMRegSpecSEL~0     ; 5         ;
-; RD[6]~6             ; 4         ;
-; RD[5]~5             ; 4         ;
-; RD[4]~4             ; 4         ;
-; RD[3]~3             ; 4         ;
-; RD[2]~2             ; 4         ;
-; RD[1]~1             ; 4         ;
-; nDEVSEL             ; 4         ;
-; RDD[4]~13           ; 4         ;
-; always9~1           ; 4         ;
-; LS[13]              ; 4         ;
-; Equal3~2            ; 4         ;
-; nRCS~1              ; 4         ;
-; Addr[9]             ; 4         ;
-; Addr[8]             ; 4         ;
-; Addr[7]             ; 4         ;
-; Addr[6]             ; 4         ;
-; Addr[15]            ; 4         ;
-; Addr[5]             ; 4         ;
-; LS[5]               ; 4         ;
-; Addr[14]            ; 4         ;
-; Addr[4]             ; 4         ;
-; LS[4]               ; 4         ;
-; Addr[13]            ; 4         ;
-; Addr[3]             ; 4         ;
-; RAr[3]              ; 4         ;
-; Addr[12]            ; 4         ;
-; Addr[2]             ; 4         ;
-; Addr[11]            ; 4         ;
-; Addr[1]             ; 4         ;
-; Addr[10]            ; 4         ;
-; RAr[2]              ; 4         ;
-; nIOSEL              ; 3         ;
-; nIOSTRB             ; 3         ;
-; SA[1]~15            ; 3         ;
-; WRD[5]              ; 3         ;
-; WRD[4]              ; 3         ;
-; WRD[3]              ; 3         ;
-; WRD[2]              ; 3         ;
-; WRD[1]              ; 3         ;
-; WRD[0]              ; 3         ;
-; Equal4~0            ; 3         ;
-; Equal5~0            ; 3         ;
-; Equal3~3            ; 3         ;
-; IS.111~0            ; 3         ;
-; nWEr                ; 3         ;
-; Addr[22]            ; 3         ;
-; Addr[21]            ; 3         ;
-; Addr[20]~41         ; 3         ;
-; Addr[20]            ; 3         ;
-; SA~10               ; 3         ;
-; Equal1~0            ; 3         ;
-; Addr[19]            ; 3         ;
-; LS[9]               ; 3         ;
-; Addr[18]            ; 3         ;
-; LS[8]               ; 3         ;
-; Addr[17]            ; 3         ;
-; LS[7]               ; 3         ;
-; Addr[16]            ; 3         ;
-; LS[6]               ; 3         ;
-; Addr[4]~17          ; 3         ;
-; LS[3]               ; 3         ;
-; LS[12]              ; 3         ;
-; Addr[12]~11         ; 3         ;
-; LS[11]              ; 3         ;
-; SA[1]~3             ; 3         ;
-; LS[10]              ; 3         ;
-; SA[1]~2             ; 3         ;
-; IOROMEN             ; 3         ;
-; RA[10]              ; 2         ;
-; RA[9]               ; 2         ;
-; RA[8]               ; 2         ;
-; RA[7]               ; 2         ;
-; RA[6]               ; 2         ;
-; RA[5]               ; 2         ;
-; RA[4]               ; 2         ;
-; RA[3]               ; 2         ;
-; RA[2]               ; 2         ;
-; RA[1]               ; 2         ;
-; RA[0]               ; 2         ;
-; nWE                 ; 2         ;
-; WRD[7]              ; 2         ;
-; WRD[6]              ; 2         ;
-; AddrIncL            ; 2         ;
-; AddrIncM            ; 2         ;
-; SetFWLoaded         ; 2         ;
-; IS.state_bit_1~3    ; 2         ;
-; IS.state_bit_1~0    ; 2         ;
-; Equal5~1            ; 2         ;
-; FCKOE               ; 2         ;
-; PS~0                ; 2         ;
-; Equal1~1            ; 2         ;
-; DQMH~0              ; 2         ;
-; Mux12~1             ; 2         ;
-; nRCS~5              ; 2         ;
-; nRCS~4              ; 2         ;
-; nRCS~2              ; 2         ;
-; RAr[9]              ; 2         ;
-; Bank                ; 2         ;
-; RAr[11]             ; 2         ;
-; LS[11]~5            ; 2         ;
-; SA[1]~4             ; 2         ;
-; RAr[10]             ; 2         ;
-; nRESf[2]            ; 2         ;
-; nRESf[1]            ; 2         ;
-; nRESf[0]            ; 2         ;
-; RAMRegSpecSEL       ; 2         ;
-; CXXXr               ; 2         ;
-; REGEN               ; 2         ;
-; RAr[8]              ; 2         ;
-; Equal9~0            ; 2         ;
-; RAr[7]              ; 2         ;
-; always8~0           ; 2         ;
-; nRESout~reg0        ; 2         ;
-; MOSI~0              ; 1         ;
-; SD[7]~7             ; 1         ;
-; SD[6]~6             ; 1         ;
-; SD[5]~5             ; 1         ;
-; SD[4]~4             ; 1         ;
-; SD[3]~3             ; 1         ;
-; SD[2]~2             ; 1         ;
-; SD[1]~1             ; 1         ;
-; SD[0]~0             ; 1         ;
-; MISO                ; 1         ;
-; nRES                ; 1         ;
-; SetFW[0]            ; 1         ;
-; SetFW[1]            ; 1         ;
-; RA[13]              ; 1         ;
-; RA[12]              ; 1         ;
-; RA[15]              ; 1         ;
-; RA[14]              ; 1         ;
-; RA[11]              ; 1         ;
-; DMAin               ; 1         ;
-; INTin               ; 1         ;
-; Mux2~3              ; 1         ;
-; SetFWr[0]           ; 1         ;
-; Mux2~2              ; 1         ;
-; Mux2~1              ; 1         ;
-; Mux2~0              ; 1         ;
-; SA[1]~14            ; 1         ;
-; RDD~20              ; 1         ;
-; RDD~18              ; 1         ;
-; RDD~16              ; 1         ;
-; RDD~14              ; 1         ;
-; RDD~10              ; 1         ;
-; RDD~8               ; 1         ;
-; RDD~6               ; 1         ;
-; RDD~4               ; 1         ;
-; AddrIncM~2          ; 1         ;
-; AddrIncM~1          ; 1         ;
-; AddrIncM~0          ; 1         ;
-; AddrIncH~2          ; 1         ;
-; AddrIncH~1          ; 1         ;
-; AddrIncH~0          ; 1         ;
-; MOSIout             ; 1         ;
-; RDD[7]              ; 1         ;
-; RDD[6]              ; 1         ;
-; RDD[5]              ; 1         ;
-; RDD[4]              ; 1         ;
-; RDD[3]              ; 1         ;
-; RDD[2]              ; 1         ;
-; RDD[1]              ; 1         ;
-; RDD[0]              ; 1         ;
-; MOSIOE              ; 1         ;
-; IS.101~0            ; 1         ;
-; IS.state_bit_2~1    ; 1         ;
-; IS.state_bit_2~0    ; 1         ;
-; Equal3~4            ; 1         ;
-; AddrIncH            ; 1         ;
-; IS.state_bit_1~2    ; 1         ;
-; IS.state_bit_1~1    ; 1         ;
-; IS.state_bit_0~5    ; 1         ;
-; IS.state_bit_0~4    ; 1         ;
-; Equal6~0            ; 1         ;
-; Equal3~1            ; 1         ;
-; Equal3~0            ; 1         ;
-; FCKout              ; 1         ;
-; FCS                 ; 1         ;
-; Equal2~0            ; 1         ;
-; Mux11~3             ; 1         ;
-; Mux11~2             ; 1         ;
-; Mux11~1             ; 1         ;
-; PHI0r1              ; 1         ;
-; Mux11~0             ; 1         ;
-; Selector2~0         ; 1         ;
-; Selector1~0         ; 1         ;
-; Addr[0]~47COUT1_92  ; 1         ;
-; Addr[0]~47          ; 1         ;
-; Selector0~0         ; 1         ;
-; Mux12~2             ; 1         ;
-; nRCS~3              ; 1         ;
-; Mux12~0             ; 1         ;
-; IS.000~0            ; 1         ;
-; nRCS~0              ; 1         ;
-; Addr[22]~45COUT1_78 ; 1         ;
-; Addr[22]~45         ; 1         ;
-; Addr[21]~43COUT1_76 ; 1         ;
-; Addr[21]~43         ; 1         ;
-; Mux15~1             ; 1         ;
-; Mux15~0             ; 1         ;
-; Addr[19]~39COUT1_74 ; 1         ;
-; Addr[19]~39         ; 1         ;
-; Mux16~2             ; 1         ;
-; Addr[9]~37COUT1_82  ; 1         ;
-; Addr[9]~37          ; 1         ;
-; LS[9]~23COUT1_50    ; 1         ;
-; LS[9]~23            ; 1         ;
-; Mux16~1             ; 1         ;
-; Mux16~0             ; 1         ;
-; Addr[18]~35COUT1_72 ; 1         ;
-; Addr[18]~35         ; 1         ;
-; Mux17~2             ; 1         ;
-; Addr[8]~33COUT1_80  ; 1         ;
-; Addr[8]~33          ; 1         ;
-; LS[8]~21COUT1_48    ; 1         ;
-; LS[8]~21            ; 1         ;
-; Mux17~1             ; 1         ;
-; Mux17~0             ; 1         ;
-; Addr[17]~31COUT1_70 ; 1         ;
-; Addr[17]~31         ; 1         ;
-; Mux18~2             ; 1         ;
-; LS[7]~19COUT1_46    ; 1         ;
-; LS[7]~19            ; 1         ;
-; Mux18~1             ; 1         ;
-; Mux18~0             ; 1         ;
-; Addr[16]~27COUT1_68 ; 1         ;
-; Addr[16]~27         ; 1         ;
-; Mux19~3             ; 1         ;
-; Mux19~2             ; 1         ;
-; Addr[6]~25COUT1_102 ; 1         ;
-; Addr[6]~25          ; 1         ;
-; RAr[6]              ; 1         ;
-; Mux19~1             ; 1         ;
-; Mux19~0             ; 1         ;
-; Mux20~2             ; 1         ;
-; Addr[5]~21COUT1_100 ; 1         ;
-; Addr[5]~21          ; 1         ;
-; LS[5]~15COUT1_44    ; 1         ;
-; LS[5]~15            ; 1         ;
-; Mux20~1             ; 1         ;
-; Mux20~0             ; 1         ;
-; Addr[14]~19COUT1_90 ; 1         ;
-; Addr[14]~19         ; 1         ;
-; Mux21~2             ; 1         ;
-; LS[4]~13COUT1_42    ; 1         ;
-; LS[4]~13            ; 1         ;
-; RAr[4]              ; 1         ;
-; Mux21~1             ; 1         ;
-; Mux21~0             ; 1         ;
-; Addr[13]~15COUT1_88 ; 1         ;
-; Addr[13]~15         ; 1         ;
-; Addr[3]~13COUT1_98  ; 1         ;
-; Addr[3]~13          ; 1         ;
-; Mux22~3             ; 1         ;
-; LS[3]~11COUT1_40    ; 1         ;
-; LS[3]~11            ; 1         ;
-; Mux22~2             ; 1         ;
-; Mux22~1             ; 1         ;
-; Mux22~0             ; 1         ;
-; LS[12]~9COUT1_54    ; 1         ;
-; LS[12]~9            ; 1         ;
-; Addr[2]~9COUT1_96   ; 1         ;
-; Addr[2]~9           ; 1         ;
-; Mux23~3             ; 1         ;
-; LS[2]~7COUT1_38     ; 1         ;
-; LS[2]~7             ; 1         ;
-; Mux23~2             ; 1         ;
-; Mux23~1             ; 1         ;
-; nRESf[3]            ; 1         ;
-; Mux23~0             ; 1         ;
-; Addr[11]~7COUT1_86  ; 1         ;
-; Addr[11]~7          ; 1         ;
-; Addr[1]~5COUT1_94   ; 1         ;
-; Addr[1]~5           ; 1         ;
-; Mux24~3             ; 1         ;
-; Mux24~2             ; 1         ;
-; Mux24~1             ; 1         ;
-; Mux24~0             ; 1         ;
-; LS[10]~1COUT1_52    ; 1         ;
-; LS[10]~1            ; 1         ;
-; Addr[10]~3COUT1_84  ; 1         ;
-; Addr[10]~3          ; 1         ;
-; Mux13~0             ; 1         ;
-; Mux14~3             ; 1         ;
-; Mux14~1             ; 1         ;
-; Mux14~0             ; 1         ;
-; always8~4           ; 1         ;
-; RAr[5]              ; 1         ;
-; always8~3           ; 1         ;
-; always8~2           ; 1         ;
-; always8~1           ; 1         ;
-; RCKE~reg0           ; 1         ;
-; DQMH~reg0           ; 1         ;
-; DQML~reg0           ; 1         ;
-; nSWE~reg0           ; 1         ;
-; nCAS~reg0           ; 1         ;
-; nRAS~reg0           ; 1         ;
-; nRCS~reg0           ; 1         ;
-; SA[12]~reg0         ; 1         ;
-; SA[11]~reg0         ; 1         ;
-; SA[10]~reg0         ; 1         ;
-; SA[9]~reg0          ; 1         ;
-; SA[8]~reg0          ; 1         ;
-; SA[7]~reg0          ; 1         ;
-; SA[6]~reg0          ; 1         ;
-; SA[5]~reg0          ; 1         ;
-; SA[4]~reg0          ; 1         ;
-; SA[3]~reg0          ; 1         ;
-; SA[2]~reg0          ; 1         ;
-; SA[1]~reg0          ; 1         ;
-; SA[0]~reg0          ; 1         ;
-; SBA[1]~reg0         ; 1         ;
-; SBA[0]~reg0         ; 1         ;
-; comb~1              ; 1         ;
-; Equal16~2           ; 1         ;
-; Equal16~1           ; 1         ;
-; Equal16~0           ; 1         ;
-; PHI0r2              ; 1         ;
-; comb~0              ; 1         ;
-+---------------------+-----------+
-
-
-+--------------------------------------------------+
-; Other Routing Usage Summary                      ;
-+-----------------------------+--------------------+
-; Other Routing Resource Type ; Usage              ;
-+-----------------------------+--------------------+
-; C4s                         ; 226 / 784 ( 29 % ) ;
-; Direct links                ; 67 / 888 ( 8 % )   ;
-; Global clocks               ; 3 / 4 ( 75 % )     ;
-; LAB clocks                  ; 14 / 32 ( 44 % )   ;
-; LUT chains                  ; 24 / 216 ( 11 % )  ;
-; Local interconnects         ; 434 / 888 ( 49 % ) ;
-; R4s                         ; 255 / 704 ( 36 % ) ;
-+-----------------------------+--------------------+
++--------------------------------------------+
+; Routing Usage Summary                      ;
++-----------------------+--------------------+
+; Routing Resource Type ; Usage              ;
++-----------------------+--------------------+
+; C4s                   ; 224 / 784 ( 29 % ) ;
+; Direct links          ; 55 / 888 ( 6 % )   ;
+; Global clocks         ; 3 / 4 ( 75 % )     ;
+; LAB clocks            ; 14 / 32 ( 44 % )   ;
+; LUT chains            ; 32 / 216 ( 15 % )  ;
+; Local interconnects   ; 418 / 888 ( 47 % ) ;
+; R4s                   ; 228 / 704 ( 32 % ) ;
++-----------------------+--------------------+
 
 
 +---------------------------------------------------------------------------+
 ; LAB Logic Elements                                                        ;
 +--------------------------------------------+------------------------------+
-; Number of Logic Elements  (Average = 9.75) ; Number of LABs  (Total = 24) ;
+; Number of Logic Elements  (Average = 9.83) ; Number of LABs  (Total = 24) ;
 +--------------------------------------------+------------------------------+
 ; 1                                          ; 0                            ;
 ; 2                                          ; 0                            ;
@@ -945,9 +589,9 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 ; 4                                          ; 0                            ;
 ; 5                                          ; 0                            ;
 ; 6                                          ; 0                            ;
-; 7                                          ; 1                            ;
+; 7                                          ; 0                            ;
 ; 8                                          ; 1                            ;
-; 9                                          ; 1                            ;
+; 9                                          ; 2                            ;
 ; 10                                         ; 21                           ;
 +--------------------------------------------+------------------------------+
 
@@ -955,21 +599,21 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 +-------------------------------------------------------------------+
 ; LAB-wide Signals                                                  ;
 +------------------------------------+------------------------------+
-; LAB-wide Signals  (Average = 1.71) ; Number of LABs  (Total = 24) ;
+; LAB-wide Signals  (Average = 1.88) ; Number of LABs  (Total = 24) ;
 +------------------------------------+------------------------------+
-; 1 Async. clear                     ; 3                            ;
-; 1 Clock                            ; 19                           ;
+; 1 Async. clear                     ; 5                            ;
+; 1 Clock                            ; 20                           ;
 ; 1 Clock enable                     ; 5                            ;
-; 1 Sync. clear                      ; 6                            ;
-; 1 Sync. load                       ; 3                            ;
-; 2 Clocks                           ; 5                            ;
+; 1 Sync. clear                      ; 7                            ;
+; 1 Sync. load                       ; 4                            ;
+; 2 Clocks                           ; 4                            ;
 +------------------------------------+------------------------------+
 
 
 +-----------------------------------------------------------------------------+
 ; LAB Signals Sourced                                                         ;
 +----------------------------------------------+------------------------------+
-; Number of Signals Sourced  (Average = 10.67) ; Number of LABs  (Total = 24) ;
+; Number of Signals Sourced  (Average = 10.63) ; Number of LABs  (Total = 24) ;
 +----------------------------------------------+------------------------------+
 ; 0                                            ; 0                            ;
 ; 1                                            ; 0                            ;
@@ -978,15 +622,15 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 ; 4                                            ; 0                            ;
 ; 5                                            ; 0                            ;
 ; 6                                            ; 0                            ;
-; 7                                            ; 1                            ;
-; 8                                            ; 0                            ;
-; 9                                            ; 1                            ;
-; 10                                           ; 16                           ;
+; 7                                            ; 0                            ;
+; 8                                            ; 1                            ;
+; 9                                            ; 2                            ;
+; 10                                           ; 14                           ;
 ; 11                                           ; 2                            ;
-; 12                                           ; 0                            ;
+; 12                                           ; 2                            ;
 ; 13                                           ; 1                            ;
 ; 14                                           ; 1                            ;
-; 15                                           ; 1                            ;
+; 15                                           ; 0                            ;
 ; 16                                           ; 1                            ;
 +----------------------------------------------+------------------------------+
 
@@ -994,55 +638,51 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 +--------------------------------------------------------------------------------+
 ; LAB Signals Sourced Out                                                        ;
 +-------------------------------------------------+------------------------------+
-; Number of Signals Sourced Out  (Average = 7.54) ; Number of LABs  (Total = 24) ;
+; Number of Signals Sourced Out  (Average = 7.21) ; Number of LABs  (Total = 24) ;
 +-------------------------------------------------+------------------------------+
 ; 0                                               ; 0                            ;
 ; 1                                               ; 0                            ;
-; 2                                               ; 1                            ;
-; 3                                               ; 0                            ;
-; 4                                               ; 0                            ;
-; 5                                               ; 4                            ;
+; 2                                               ; 0                            ;
+; 3                                               ; 2                            ;
+; 4                                               ; 1                            ;
+; 5                                               ; 3                            ;
 ; 6                                               ; 2                            ;
-; 7                                               ; 4                            ;
-; 8                                               ; 4                            ;
-; 9                                               ; 4                            ;
-; 10                                              ; 4                            ;
-; 11                                              ; 1                            ;
+; 7                                               ; 3                            ;
+; 8                                               ; 5                            ;
+; 9                                               ; 5                            ;
+; 10                                              ; 3                            ;
 +-------------------------------------------------+------------------------------+
 
 
 +-----------------------------------------------------------------------------+
 ; LAB Distinct Inputs                                                         ;
 +----------------------------------------------+------------------------------+
-; Number of Distinct Inputs  (Average = 16.08) ; Number of LABs  (Total = 24) ;
+; Number of Distinct Inputs  (Average = 15.50) ; Number of LABs  (Total = 24) ;
 +----------------------------------------------+------------------------------+
 ; 0                                            ; 0                            ;
 ; 1                                            ; 0                            ;
 ; 2                                            ; 0                            ;
 ; 3                                            ; 0                            ;
-; 4                                            ; 0                            ;
+; 4                                            ; 1                            ;
 ; 5                                            ; 0                            ;
-; 6                                            ; 1                            ;
-; 7                                            ; 0                            ;
-; 8                                            ; 1                            ;
-; 9                                            ; 1                            ;
-; 10                                           ; 3                            ;
-; 11                                           ; 0                            ;
-; 12                                           ; 1                            ;
-; 13                                           ; 2                            ;
-; 14                                           ; 0                            ;
-; 15                                           ; 3                            ;
-; 16                                           ; 1                            ;
-; 17                                           ; 1                            ;
-; 18                                           ; 2                            ;
-; 19                                           ; 1                            ;
+; 6                                            ; 0                            ;
+; 7                                            ; 1                            ;
+; 8                                            ; 0                            ;
+; 9                                            ; 0                            ;
+; 10                                           ; 1                            ;
+; 11                                           ; 1                            ;
+; 12                                           ; 0                            ;
+; 13                                           ; 4                            ;
+; 14                                           ; 4                            ;
+; 15                                           ; 0                            ;
+; 16                                           ; 2                            ;
+; 17                                           ; 2                            ;
+; 18                                           ; 0                            ;
+; 19                                           ; 2                            ;
 ; 20                                           ; 2                            ;
-; 21                                           ; 0                            ;
+; 21                                           ; 1                            ;
 ; 22                                           ; 2                            ;
-; 23                                           ; 0                            ;
-; 24                                           ; 0                            ;
-; 25                                           ; 0                            ;
-; 26                                           ; 3                            ;
+; 23                                           ; 1                            ;
 +----------------------------------------------+------------------------------+
 
 
@@ -1057,14 +697,14 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 ; Enable INIT_DONE output                      ; Off                      ;
 ; Configuration scheme                         ; Passive Serial           ;
 ; Reserve all unused pins                      ; As output driving ground ;
-; Base pin-out file on sameframe device        ; Off                      ;
 +----------------------------------------------+--------------------------+
 
 
 +-----------------+
 ; Fitter Messages ;
 +-----------------+
-Warning (20028): Parallel compilation is not licensed and has been disabled
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
 Info (119006): Selected device EPM240T100C5 for design "GR8RAM"
 Info (21077): Low junction temperature is 0 degrees C
 Info (21077): High junction temperature is 85 degrees C
@@ -1084,42 +724,44 @@ Info (332111): Found 2 clocks
     Info (332111):   40.000         C25M
     Info (332111):  978.000         PHI0
 Info (186079): Completed User Assigned Global Signals Promotion Operation
-Info (186215): Automatically promoted signal "C25M" to use Global clock in PIN 64
-Info (186216): Automatically promoted some destinations of signal "PHI0" to use Global clock
+Info (186215): Automatically promoted signal "C25M" to use Global clock in PIN 64 File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 9
+Info (186216): Automatically promoted some destinations of signal "PHI0" to use Global clock File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 9
     Info (186217): Destination "comb~0" may be non-global or may not use global clock
-    Info (186217): Destination "PHI0r1" may be non-global or may not use global clock
-Info (186228): Pin "PHI0" drives global clock, but is not placed in a dedicated clock pin position
-Info (186216): Automatically promoted some destinations of signal "nRESr" to use Global clock
-    Info (186217): Destination "IOROMEN" may be non-global or may not use global clock
+    Info (186217): Destination "PHI0r1" may be non-global or may not use global clock File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 10
+Info (186228): Pin "PHI0" drives global clock, but is not placed in a dedicated clock pin position File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 9
+Info (186216): Automatically promoted some destinations of signal "nRESr" to use Global clock File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 16
+    Info (186217): Destination "IOROMEN" may be non-global or may not use global clock File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 88
+    Info (186217): Destination "RestoreDone~0" may be non-global or may not use global clock File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 150
 Info (186079): Completed Auto Global Promotion Operation
 Info (176234): Starting register packing
 Info (186468): Started processing fast register assignments
 Info (186469): Finished processing fast register assignments
 Info (176235): Finished register packing
-Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
+Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00
+Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
 Info (170189): Fitter placement preparation operations beginning
 Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
 Info (170191): Fitter placement operations beginning
 Info (170137): Fitter placement was successful
 Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
 Info (170193): Fitter routing operations beginning
-Info (170195): Router estimated average interconnect usage is 34% of the available device resources
-    Info (170196): Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
+Info (170195): Router estimated average interconnect usage is 31% of the available device resources
+    Info (170196): Router estimated peak interconnect usage is 31% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
 Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
-Info (11888): Total time spent on timing analysis during the Fitter is 0.27 seconds.
+Info (11888): Total time spent on timing analysis during the Fitter is 0.31 seconds.
 Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
 Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
-Info (144001): Generated suppressed messages file C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.fit.smsg
-Info: Quartus II 64-Bit Fitter was successful. 0 errors, 3 warnings
-    Info: Peak virtual memory: 544 megabytes
-    Info: Processing ended: Tue Sep 14 01:35:30 2021
-    Info: Elapsed time: 00:00:02
-    Info: Total CPU time (on all processors): 00:00:03
+Info (144001): Generated suppressed messages file Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg
+Info: Quartus Prime Fitter was successful. 0 errors, 3 warnings
+    Info: Peak virtual memory: 13733 megabytes
+    Info: Processing ended: Tue Mar 28 05:06:35 2023
+    Info: Elapsed time: 00:00:03
+    Info: Total CPU time (on all processors): 00:00:04
 
 
 +----------------------------+
 ; Fitter Suppressed Messages ;
 +----------------------------+
-The suppressed messages can be found in C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.fit.smsg.
+The suppressed messages can be found in Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg.
 
 
diff --git a/cpld/output_files/GR8RAM.fit.summary b/cpld/output_files/GR8RAM.fit.summary
index 5d9e773..ac928d0 100755
--- a/cpld/output_files/GR8RAM.fit.summary
+++ b/cpld/output_files/GR8RAM.fit.summary
@@ -1,11 +1,11 @@
-Fitter Status : Successful - Tue Sep 14 01:35:30 2021
-Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+Fitter Status : Successful - Tue Mar 28 05:06:35 2023
+Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
 Revision Name : GR8RAM
 Top-level Entity Name : GR8RAM
 Family : MAX II
 Device : EPM240T100C5
 Timing Models : Final
-Total logic elements : 234 / 240 ( 98 % )
+Total logic elements : 236 / 240 ( 98 % )
 Total pins : 80 / 80 ( 100 % )
 Total virtual pins : 0
 UFM blocks : 0 / 1 ( 0 % )
diff --git a/cpld/output_files/GR8RAM.flow.rpt b/cpld/output_files/GR8RAM.flow.rpt
old mode 100755
new mode 100644
index e7cc3c2..13b17f9
--- a/cpld/output_files/GR8RAM.flow.rpt
+++ b/cpld/output_files/GR8RAM.flow.rpt
@@ -1,6 +1,6 @@
 Flow report for GR8RAM
-Tue Sep 14 01:35:34 2021
-Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+Tue Mar 28 05:06:39 2023
+Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
 
 
 ---------------------
@@ -21,37 +21,38 @@ Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit
 ----------------
 ; Legal Notice ;
 ----------------
-Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
+Copyright (C) 2019  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
 functions, and any output files from any of the foregoing 
 (including device programming or simulation files), and any 
 associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
 
 
 
-+-----------------------------------------------------------------------------+
-; Flow Summary                                                                ;
-+---------------------------+-------------------------------------------------+
-; Flow Status               ; Successful - Tue Sep 14 01:35:32 2021           ;
-; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
-; Revision Name             ; GR8RAM                                          ;
-; Top-level Entity Name     ; GR8RAM                                          ;
-; Family                    ; MAX II                                          ;
-; Device                    ; EPM240T100C5                                    ;
-; Timing Models             ; Final                                           ;
-; Total logic elements      ; 234 / 240 ( 98 % )                              ;
-; Total pins                ; 80 / 80 ( 100 % )                               ;
-; Total virtual pins        ; 0                                               ;
-; UFM blocks                ; 0 / 1 ( 0 % )                                   ;
-+---------------------------+-------------------------------------------------+
++---------------------------------------------------------------------+
+; Flow Summary                                                        ;
++-----------------------+---------------------------------------------+
+; Flow Status           ; Successful - Tue Mar 28 05:06:37 2023       ;
+; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
+; Revision Name         ; GR8RAM                                      ;
+; Top-level Entity Name ; GR8RAM                                      ;
+; Family                ; MAX II                                      ;
+; Device                ; EPM240T100C5                                ;
+; Timing Models         ; Final                                       ;
+; Total logic elements  ; 236 / 240 ( 98 % )                          ;
+; Total pins            ; 80 / 80 ( 100 % )                           ;
+; Total virtual pins    ; 0                                           ;
+; UFM blocks            ; 0 / 1 ( 0 % )                               ;
++-----------------------+---------------------------------------------+
 
 
 +-----------------------------------------+
@@ -59,67 +60,67 @@ applicable agreement for further details.
 +-------------------+---------------------+
 ; Option            ; Setting             ;
 +-------------------+---------------------+
-; Start date & time ; 09/14/2021 01:35:26 ;
+; Start date & time ; 03/28/2023 05:06:13 ;
 ; Main task         ; Compilation         ;
 ; Revision Name     ; GR8RAM              ;
 +-------------------+---------------------+
 
 
-+---------------------------------------------------------------------------------------------------------------------------+
-; Flow Non-Default Global Settings                                                                                          ;
-+-------------------------------------------------+------------------------------+---------------+-------------+------------+
-; Assignment Name                                 ; Value                        ; Default Value ; Entity Name ; Section Id ;
-+-------------------------------------------------+------------------------------+---------------+-------------+------------+
-; ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP             ; On                           ; Off           ; --          ; --         ;
-; ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES ; Always                       ; Auto          ; --          ; --         ;
-; ALM_REGISTER_PACKING_EFFORT                     ; High                         ; Medium        ; --          ; --         ;
-; AUTO_PACKED_REGISTERS_MAXII                     ; Minimize Area                ; Auto          ; --          ; --         ;
-; AUTO_RESOURCE_SHARING                           ; On                           ; Off           ; --          ; --         ;
-; COMPILER_SIGNATURE_ID                           ; 962837114763.163159772501756 ; --            ; --          ; --         ;
-; FINAL_PLACEMENT_OPTIMIZATION                    ; Always                       ; Automatically ; --          ; --         ;
-; FITTER_EFFORT                                   ; Standard Fit                 ; Auto Fit      ; --          ; --         ;
-; IOBANK_VCCIO                                    ; 3.3V                         ; --            ; --          ; 1          ;
-; IOBANK_VCCIO                                    ; 3.3V                         ; --            ; --          ; 2          ;
-; MAXII_OPTIMIZATION_TECHNIQUE                    ; Area                         ; Balanced      ; --          ; --         ;
-; MAX_CORE_JUNCTION_TEMP                          ; 85                           ; --            ; --          ; --         ;
-; MIN_CORE_JUNCTION_TEMP                          ; 0                            ; --            ; --          ; --         ;
-; MUX_RESTRUCTURE                                 ; On                           ; Auto          ; --          ; --         ;
-; PLACEMENT_EFFORT_MULTIPLIER                     ; 2.0                          ; 1.0           ; --          ; --         ;
-; POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR           ; 3.3V                         ; --            ; --          ; --         ;
-; PROJECT_OUTPUT_DIRECTORY                        ; output_files                 ; --            ; --          ; --         ;
-; REMOVE_REDUNDANT_LOGIC_CELLS                    ; On                           ; Off           ; --          ; --         ;
-; ROUTER_EFFORT_MULTIPLIER                        ; 2.0                          ; 1.0           ; --          ; --         ;
-; ROUTER_REGISTER_DUPLICATION                     ; Off                          ; Auto          ; --          ; --         ;
-; SEED                                            ; 235                          ; 1             ; --          ; --         ;
-; STATE_MACHINE_PROCESSING                        ; Minimal Bits                 ; Auto          ; --          ; --         ;
-; SYNTHESIS_SEED                                  ; 123                          ; 1             ; --          ; --         ;
-; SYNTH_TIMING_DRIVEN_SYNTHESIS                   ; Off                          ; --            ; --          ; --         ;
-+-------------------------------------------------+------------------------------+---------------+-------------+------------+
++-------------------------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings                                                                                                    ;
++-------------------------------------------------+----------------------------------------+---------------+-------------+------------+
+; Assignment Name                                 ; Value                                  ; Default Value ; Entity Name ; Section Id ;
++-------------------------------------------------+----------------------------------------+---------------+-------------+------------+
+; ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP             ; On                                     ; Off           ; --          ; --         ;
+; ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES ; Always                                 ; Auto          ; --          ; --         ;
+; ALM_REGISTER_PACKING_EFFORT                     ; High                                   ; Medium        ; --          ; --         ;
+; AUTO_PACKED_REGISTERS_MAX                       ; Minimize Area                          ; Auto          ; --          ; --         ;
+; AUTO_RESOURCE_SHARING                           ; On                                     ; Off           ; --          ; --         ;
+; COMPILER_SIGNATURE_ID                           ; 121381084694.167999437303928           ; --            ; --          ; --         ;
+; FINAL_PLACEMENT_OPTIMIZATION                    ; Always                                 ; Automatically ; --          ; --         ;
+; FITTER_EFFORT                                   ; Standard Fit                           ; Auto Fit      ; --          ; --         ;
+; IOBANK_VCCIO                                    ; -- (Not supported for targeted family) ; --            ; --          ; 1          ;
+; IOBANK_VCCIO                                    ; -- (Not supported for targeted family) ; --            ; --          ; 2          ;
+; MAXII_OPTIMIZATION_TECHNIQUE                    ; Area                                   ; Balanced      ; --          ; --         ;
+; MAX_CORE_JUNCTION_TEMP                          ; 85                                     ; --            ; --          ; --         ;
+; MIN_CORE_JUNCTION_TEMP                          ; 0                                      ; --            ; --          ; --         ;
+; MUX_RESTRUCTURE                                 ; On                                     ; Auto          ; --          ; --         ;
+; PLACEMENT_EFFORT_MULTIPLIER                     ; 2.0                                    ; 1.0           ; --          ; --         ;
+; POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR           ; 3.3V                                   ; --            ; --          ; --         ;
+; PROJECT_OUTPUT_DIRECTORY                        ; output_files                           ; --            ; --          ; --         ;
+; REMOVE_REDUNDANT_LOGIC_CELLS                    ; On                                     ; Off           ; --          ; --         ;
+; ROUTER_EFFORT_MULTIPLIER                        ; 2.0                                    ; 1.0           ; --          ; --         ;
+; ROUTER_REGISTER_DUPLICATION                     ; Off                                    ; Auto          ; --          ; --         ;
+; SEED                                            ; 235                                    ; 1             ; --          ; --         ;
+; STATE_MACHINE_PROCESSING                        ; Minimal Bits                           ; Auto          ; --          ; --         ;
+; SYNTHESIS_SEED                                  ; 123                                    ; 1             ; --          ; --         ;
+; SYNTH_TIMING_DRIVEN_SYNTHESIS                   ; -- (Not supported for targeted family) ; --            ; --          ; --         ;
++-------------------------------------------------+----------------------------------------+---------------+-------------+------------+
 
 
-+-------------------------------------------------------------------------------------------------------------------------------+
-; Flow Elapsed Time                                                                                                             ;
-+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Module Name               ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
-+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis      ; 00:00:02     ; 1.0                     ; 422 MB              ; 00:00:01                           ;
-; Fitter                    ; 00:00:02     ; 1.0                     ; 544 MB              ; 00:00:02                           ;
-; Assembler                 ; 00:00:01     ; 1.0                     ; 381 MB              ; 00:00:01                           ;
-; TimeQuest Timing Analyzer ; 00:00:02     ; 1.0                     ; 374 MB              ; 00:00:01                           ;
-; Total                     ; 00:00:07     ; --                      ; --                  ; 00:00:05                           ;
-+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
++--------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time                                                                                                        ;
++----------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name          ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++----------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis ; 00:00:18     ; 1.0                     ; 13094 MB            ; 00:00:39                           ;
+; Fitter               ; 00:00:03     ; 1.0                     ; 13733 MB            ; 00:00:04                           ;
+; Assembler            ; 00:00:01     ; 1.0                     ; 13053 MB            ; 00:00:01                           ;
+; Timing Analyzer      ; 00:00:01     ; 1.0                     ; 13052 MB            ; 00:00:01                           ;
+; Total                ; 00:00:23     ; --                      ; --                  ; 00:00:45                           ;
++----------------------+--------------+-------------------------+---------------------+------------------------------------+
 
 
-+----------------------------------------------------------------------------------------+
-; Flow OS Summary                                                                        ;
-+---------------------------+------------------+-----------+------------+----------------+
-; Module Name               ; Machine Hostname ; OS Name   ; OS Version ; Processor type ;
-+---------------------------+------------------+-----------+------------+----------------+
-; Analysis & Synthesis      ; Dog-PC           ; Windows 7 ; 6.1        ; x86_64         ;
-; Fitter                    ; Dog-PC           ; Windows 7 ; 6.1        ; x86_64         ;
-; Assembler                 ; Dog-PC           ; Windows 7 ; 6.1        ; x86_64         ;
-; TimeQuest Timing Analyzer ; Dog-PC           ; Windows 7 ; 6.1        ; x86_64         ;
-+---------------------------+------------------+-----------+------------+----------------+
++------------------------------------------------------------------------------------+
+; Flow OS Summary                                                                    ;
++----------------------+------------------+------------+------------+----------------+
+; Module Name          ; Machine Hostname ; OS Name    ; OS Version ; Processor type ;
++----------------------+------------------+------------+------------+----------------+
+; Analysis & Synthesis ; ZaneMacWin11     ; Windows 10 ; 10.0       ; x86_64         ;
+; Fitter               ; ZaneMacWin11     ; Windows 10 ; 10.0       ; x86_64         ;
+; Assembler            ; ZaneMacWin11     ; Windows 10 ; 10.0       ; x86_64         ;
+; Timing Analyzer      ; ZaneMacWin11     ; Windows 10 ; 10.0       ; x86_64         ;
++----------------------+------------------+------------+------------+----------------+
 
 
 ------------
diff --git a/cpld/output_files/GR8RAM.jdi b/cpld/output_files/GR8RAM.jdi
index 1b5d781..a8d07fd 100755
--- a/cpld/output_files/GR8RAM.jdi
+++ b/cpld/output_files/GR8RAM.jdi
@@ -1,6 +1,6 @@
 <sld_project_info>
   <project>
-    <hash md5_digest_80b="5cae6640443712869b47"/>
+    <hash md5_digest_80b="d50e59ac0621234423dc"/>
   </project>
   <file_info>
     <file device="EPM240T100C5" path="GR8RAM.sof" usercode="0xFFFFFFFF"/>
diff --git a/cpld/output_files/GR8RAM.map.rpt b/cpld/output_files/GR8RAM.map.rpt
old mode 100755
new mode 100644
index 766c357..b358e9c
--- a/cpld/output_files/GR8RAM.map.rpt
+++ b/cpld/output_files/GR8RAM.map.rpt
@@ -1,6 +1,6 @@
 Analysis & Synthesis report for GR8RAM
-Tue Sep 14 01:35:27 2021
-Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+Tue Mar 28 05:06:31 2023
+Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
 
 
 ---------------------
@@ -26,128 +26,132 @@ Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit
 ----------------
 ; Legal Notice ;
 ----------------
-Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
+Copyright (C) 2019  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
 functions, and any output files from any of the foregoing 
 (including device programming or simulation files), and any 
 associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
 
 
 
-+-------------------------------------------------------------------------------+
-; Analysis & Synthesis Summary                                                  ;
-+-----------------------------+-------------------------------------------------+
-; Analysis & Synthesis Status ; Successful - Tue Sep 14 01:35:27 2021           ;
-; Quartus II 64-Bit Version   ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
-; Revision Name               ; GR8RAM                                          ;
-; Top-level Entity Name       ; GR8RAM                                          ;
-; Family                      ; MAX II                                          ;
-; Total logic elements        ; 257                                             ;
-; Total pins                  ; 80                                              ;
-; Total virtual pins          ; 0                                               ;
-; UFM blocks                  ; 0 / 1 ( 0 % )                                   ;
-+-----------------------------+-------------------------------------------------+
++---------------------------------------------------------------------------+
+; Analysis & Synthesis Summary                                              ;
++-----------------------------+---------------------------------------------+
+; Analysis & Synthesis Status ; Successful - Tue Mar 28 05:06:31 2023       ;
+; Quartus Prime Version       ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
+; Revision Name               ; GR8RAM                                      ;
+; Top-level Entity Name       ; GR8RAM                                      ;
+; Family                      ; MAX II                                      ;
+; Total logic elements        ; 256                                         ;
+; Total pins                  ; 80                                          ;
+; Total virtual pins          ; 0                                           ;
+; UFM blocks                  ; 0 / 1 ( 0 % )                               ;
++-----------------------------+---------------------------------------------+
 
 
-+----------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Settings                                                                                        ;
-+----------------------------------------------------------------------------+--------------------+--------------------+
-; Option                                                                     ; Setting            ; Default Value      ;
-+----------------------------------------------------------------------------+--------------------+--------------------+
-; Device                                                                     ; EPM240T100C5       ;                    ;
-; Top-level entity name                                                      ; GR8RAM             ; GR8RAM             ;
-; Family name                                                                ; MAX II             ; Cyclone IV GX      ;
-; Restructure Multiplexers                                                   ; On                 ; Auto               ;
-; State Machine Processing                                                   ; Minimal Bits       ; Auto               ;
-; Remove Redundant Logic Cells                                               ; On                 ; Off                ;
-; Optimization Technique                                                     ; Area               ; Balanced           ;
-; Perform WYSIWYG Primitive Resynthesis                                      ; On                 ; Off                ;
-; Allow Shift Register Merging across Hierarchies                            ; Always             ; Auto               ;
-; Auto Resource Sharing                                                      ; On                 ; Off                ;
-; Synthesis Seed                                                             ; 123                ; 1                  ;
-; Use smart compilation                                                      ; Off                ; Off                ;
-; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
-; Enable compact report table                                                ; Off                ; Off                ;
-; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
-; Preserve fewer node names                                                  ; On                 ; On                 ;
-; Disable OpenCore Plus hardware evaluation                                  ; Off                ; Off                ;
-; Verilog Version                                                            ; Verilog_2001       ; Verilog_2001       ;
-; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
-; Safe State Machine                                                         ; Off                ; Off                ;
-; Extract Verilog State Machines                                             ; On                 ; On                 ;
-; Extract VHDL State Machines                                                ; On                 ; On                 ;
-; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
-; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
-; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
-; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
-; Infer RAMs from Raw Logic                                                  ; On                 ; On                 ;
-; Parallel Synthesis                                                         ; On                 ; On                 ;
-; NOT Gate Push-Back                                                         ; On                 ; On                 ;
-; Power-Up Don't Care                                                        ; On                 ; On                 ;
-; Remove Duplicate Registers                                                 ; On                 ; On                 ;
-; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
-; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
-; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
-; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
-; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
-; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
-; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
-; Carry Chain Length                                                         ; 70                 ; 70                 ;
-; Auto Carry Chains                                                          ; On                 ; On                 ;
-; Auto Open-Drain Pins                                                       ; On                 ; On                 ;
-; Auto Shift Register Replacement                                            ; Auto               ; Auto               ;
-; Auto Clock Enable Replacement                                              ; On                 ; On                 ;
-; Allow Synchronous Control Signals                                          ; On                 ; On                 ;
-; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
-; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
-; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
-; Report Parameter Settings                                                  ; On                 ; On                 ;
-; Report Source Assignments                                                  ; On                 ; On                 ;
-; Report Connectivity Checks                                                 ; On                 ; On                 ;
-; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
-; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
-; PowerPlay Power Optimization                                               ; Normal compilation ; Normal compilation ;
-; HDL message level                                                          ; Level2             ; Level2             ;
-; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
-; Number of Removed Registers Reported in Synthesis Report                   ; 5000               ; 5000               ;
-; Number of Swept Nodes Reported in Synthesis Report                         ; 5000               ; 5000               ;
-; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
-; Clock MUX Protection                                                       ; On                 ; On                 ;
-; Block Design Naming                                                        ; Auto               ; Auto               ;
-; Synthesis Effort                                                           ; Auto               ; Auto               ;
-; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
-; Pre-Mapping Resynthesis Optimization                                       ; Off                ; Off                ;
-; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
-; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
-+----------------------------------------------------------------------------+--------------------+--------------------+
++------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings                                                                              ;
++------------------------------------------------------------------+--------------------+--------------------+
+; Option                                                           ; Setting            ; Default Value      ;
++------------------------------------------------------------------+--------------------+--------------------+
+; Device                                                           ; EPM240T100C5       ;                    ;
+; Top-level entity name                                            ; GR8RAM             ; GR8RAM             ;
+; Family name                                                      ; MAX II             ; Cyclone V          ;
+; Restructure Multiplexers                                         ; On                 ; Auto               ;
+; State Machine Processing                                         ; Minimal Bits       ; Auto               ;
+; Remove Redundant Logic Cells                                     ; On                 ; Off                ;
+; Optimization Technique                                           ; Area               ; Balanced           ;
+; Perform WYSIWYG Primitive Resynthesis                            ; On                 ; Off                ;
+; Allow Shift Register Merging across Hierarchies                  ; Always             ; Auto               ;
+; Auto Resource Sharing                                            ; On                 ; Off                ;
+; Use smart compilation                                            ; Off                ; Off                ;
+; Enable parallel Assembler and Timing Analyzer during compilation ; On                 ; On                 ;
+; Enable compact report table                                      ; Off                ; Off                ;
+; Create Debugging Nodes for IP Cores                              ; Off                ; Off                ;
+; Preserve fewer node names                                        ; On                 ; On                 ;
+; Intel FPGA IP Evaluation Mode                                    ; Enable             ; Enable             ;
+; Verilog Version                                                  ; Verilog_2001       ; Verilog_2001       ;
+; VHDL Version                                                     ; VHDL_1993          ; VHDL_1993          ;
+; Safe State Machine                                               ; Off                ; Off                ;
+; Extract Verilog State Machines                                   ; On                 ; On                 ;
+; Extract VHDL State Machines                                      ; On                 ; On                 ;
+; Ignore Verilog initial constructs                                ; Off                ; Off                ;
+; Iteration limit for constant Verilog loops                       ; 5000               ; 5000               ;
+; Iteration limit for non-constant Verilog loops                   ; 250                ; 250                ;
+; Add Pass-Through Logic to Inferred RAMs                          ; On                 ; On                 ;
+; Infer RAMs from Raw Logic                                        ; On                 ; On                 ;
+; Parallel Synthesis                                               ; On                 ; On                 ;
+; NOT Gate Push-Back                                               ; On                 ; On                 ;
+; Power-Up Don't Care                                              ; On                 ; On                 ;
+; Remove Duplicate Registers                                       ; On                 ; On                 ;
+; Ignore CARRY Buffers                                             ; Off                ; Off                ;
+; Ignore CASCADE Buffers                                           ; Off                ; Off                ;
+; Ignore GLOBAL Buffers                                            ; Off                ; Off                ;
+; Ignore ROW GLOBAL Buffers                                        ; Off                ; Off                ;
+; Ignore LCELL Buffers                                             ; Off                ; Off                ;
+; Ignore SOFT Buffers                                              ; On                 ; On                 ;
+; Limit AHDL Integers to 32 Bits                                   ; Off                ; Off                ;
+; Carry Chain Length                                               ; 70                 ; 70                 ;
+; Auto Carry Chains                                                ; On                 ; On                 ;
+; Auto Open-Drain Pins                                             ; On                 ; On                 ;
+; Auto Shift Register Replacement                                  ; Auto               ; Auto               ;
+; Auto Clock Enable Replacement                                    ; On                 ; On                 ;
+; Allow Synchronous Control Signals                                ; On                 ; On                 ;
+; Force Use of Synchronous Clear Signals                           ; Off                ; Off                ;
+; Use LogicLock Constraints during Resource Balancing              ; On                 ; On                 ;
+; Ignore translate_off and synthesis_off directives                ; Off                ; Off                ;
+; Report Parameter Settings                                        ; On                 ; On                 ;
+; Report Source Assignments                                        ; On                 ; On                 ;
+; Report Connectivity Checks                                       ; On                 ; On                 ;
+; Ignore Maximum Fan-Out Assignments                               ; Off                ; Off                ;
+; Synchronization Register Chain Length                            ; 2                  ; 2                  ;
+; Power Optimization During Synthesis                              ; Normal compilation ; Normal compilation ;
+; HDL message level                                                ; Level2             ; Level2             ;
+; Suppress Register Optimization Related Messages                  ; Off                ; Off                ;
+; Number of Removed Registers Reported in Synthesis Report         ; 5000               ; 5000               ;
+; Number of Swept Nodes Reported in Synthesis Report               ; 5000               ; 5000               ;
+; Number of Inverted Registers Reported in Synthesis Report        ; 100                ; 100                ;
+; Clock MUX Protection                                             ; On                 ; On                 ;
+; Block Design Naming                                              ; Auto               ; Auto               ;
+; Synthesis Effort                                                 ; Auto               ; Auto               ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal     ; On                 ; On                 ;
+; Analysis & Synthesis Message Level                               ; Medium             ; Medium             ;
+; Disable Register Merging Across Hierarchies                      ; Auto               ; Auto               ;
++------------------------------------------------------------------+--------------------+--------------------+
 
 
-Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
-+-------------------------------------+
-; Parallel Compilation                ;
-+----------------------------+--------+
-; Processors                 ; Number ;
-+----------------------------+--------+
-; Number detected on machine ; 12     ;
-; Maximum allowed            ; 1      ;
-+----------------------------+--------+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 4           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 1           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
++----------------------------+-------------+
 
 
-+--------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Source Files Read                                                                                                     ;
-+----------------------------------+-----------------+------------------------+----------------------------------------------------+---------+
-; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path                       ; Library ;
-+----------------------------------+-----------------+------------------------+----------------------------------------------------+---------+
-; GR8RAM.v                         ; yes             ; User Verilog HDL File  ; C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v ;         ;
-+----------------------------------+-----------------+------------------------+----------------------------------------------------+---------+
++-----------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read                                                                                ;
++----------------------------------+-----------------+------------------------+-------------------------------+---------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path  ; Library ;
++----------------------------------+-----------------+------------------------+-------------------------------+---------+
+; GR8RAM.v                         ; yes             ; User Verilog HDL File  ; Y:/Repos/GR8RAM/cpld/GR8RAM.v ;         ;
++----------------------------------+-----------------+------------------------+-------------------------------+---------+
 
 
 +-----------------------------------------------------+
@@ -155,43 +159,43 @@ Parallel compilation was disabled, but you have multiple processors available. E
 +---------------------------------------------+-------+
 ; Resource                                    ; Usage ;
 +---------------------------------------------+-------+
-; Total logic elements                        ; 257   ;
-;     -- Combinational with no register       ; 136   ;
-;     -- Register only                        ; 24    ;
-;     -- Combinational with a register        ; 97    ;
+; Total logic elements                        ; 256   ;
+;     -- Combinational with no register       ; 139   ;
+;     -- Register only                        ; 21    ;
+;     -- Combinational with a register        ; 96    ;
 ;                                             ;       ;
 ; Logic element usage by number of LUT inputs ;       ;
-;     -- 4 input functions                    ; 126   ;
-;     -- 3 input functions                    ; 41    ;
-;     -- 2 input functions                    ; 65    ;
+;     -- 4 input functions                    ; 137   ;
+;     -- 3 input functions                    ; 35    ;
+;     -- 2 input functions                    ; 63    ;
 ;     -- 1 input functions                    ; 0     ;
-;     -- 0 input functions                    ; 1     ;
+;     -- 0 input functions                    ; 0     ;
 ;                                             ;       ;
 ; Logic elements by mode                      ;       ;
-;     -- normal mode                          ; 224   ;
+;     -- normal mode                          ; 223   ;
 ;     -- arithmetic mode                      ; 33    ;
 ;     -- qfbk mode                            ; 0     ;
 ;     -- register cascade mode                ; 0     ;
-;     -- synchronous clear/load mode          ; 45    ;
+;     -- synchronous clear/load mode          ; 44    ;
 ;     -- asynchronous clear/load mode         ; 29    ;
 ;                                             ;       ;
-; Total registers                             ; 121   ;
+; Total registers                             ; 117   ;
 ; Total logic cells in carry chains           ; 37    ;
 ; I/O pins                                    ; 80    ;
 ; Maximum fan-out node                        ; C25M  ;
-; Maximum fan-out                             ; 107   ;
-; Total fan-out                               ; 1095  ;
-; Average fan-out                             ; 3.25  ;
+; Maximum fan-out                             ; 103   ;
+; Total fan-out                               ; 1104  ;
+; Average fan-out                             ; 3.29  ;
 +---------------------------------------------+-------+
 
 
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                  ;
-+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
-; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
-+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
-; |GR8RAM                    ; 257 (257)   ; 121          ; 0          ; 80   ; 0            ; 136 (136)    ; 24 (24)           ; 97 (97)          ; 37 (37)         ; 0 (0)      ; |GR8RAM             ; work         ;
-+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                ;
++----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+
+; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
++----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+
+; |GR8RAM                    ; 256 (256)   ; 117          ; 0          ; 80   ; 0            ; 139 (139)    ; 21 (21)           ; 96 (96)          ; 37 (37)         ; 0 (0)      ; |GR8RAM             ; GR8RAM      ; work         ;
++----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+
 Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
 
 
@@ -210,14 +214,15 @@ Encoding Type:  Minimal Bits
 +--------+----------------+----------------+----------------+
 
 
-+------------------------------------------------------------+
-; Registers Removed During Synthesis                         ;
-+---------------------------------------+--------------------+
-; Register name                         ; Reason for Removal ;
-+---------------------------------------+--------------------+
-; IS~10                                 ; Lost fanout        ;
-; Total Number of Removed Registers = 1 ;                    ;
-+---------------------------------------+--------------------+
++--------------------------------------------------------------------------------+
+; Registers Removed During Synthesis                                             ;
++---------------------------------------+----------------------------------------+
+; Register name                         ; Reason for Removal                     ;
++---------------------------------------+----------------------------------------+
+; SBA[0]~reg0                           ; Stuck at GND due to stuck port data_in ;
+; IS~10                                 ; Lost fanout                            ;
+; Total Number of Removed Registers = 2 ;                                        ;
++---------------------------------------+----------------------------------------+
 
 
 +------------------------------------------------------+
@@ -225,12 +230,12 @@ Encoding Type:  Minimal Bits
 +----------------------------------------------+-------+
 ; Statistic                                    ; Value ;
 +----------------------------------------------+-------+
-; Total registers                              ; 121   ;
-; Number of registers using Synchronous Clear  ; 12    ;
+; Total registers                              ; 117   ;
+; Number of registers using Synchronous Clear  ; 11    ;
 ; Number of registers using Synchronous Load   ; 33    ;
 ; Number of registers using Asynchronous Clear ; 29    ;
 ; Number of registers using Asynchronous Load  ; 0     ;
-; Number of registers using Clock Enable       ; 24    ;
+; Number of registers using Clock Enable       ; 22    ;
 ; Number of registers using Preset             ; 0     ;
 +----------------------------------------------+-------+
 
@@ -247,7 +252,8 @@ Encoding Type:  Minimal Bits
 ; DQML~reg0                              ; 1       ;
 ; DQMH~reg0                              ; 1       ;
 ; RCKE~reg0                              ; 1       ;
-; Total number of inverted registers = 7 ;         ;
+; nFCS~reg0                              ; 1       ;
+; Total number of inverted registers = 8 ;         ;
 +----------------------------------------+---------+
 
 
@@ -257,14 +263,13 @@ Encoding Type:  Minimal Bits
 ; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
 +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
 ; 3:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; Yes        ; |GR8RAM|PS[2]              ;
-; 5:1                ; 2 bits    ; 6 LEs         ; 2 LEs                ; 4 LEs                  ; Yes        ; |GR8RAM|SA[11]~reg0        ;
-; 20:1               ; 6 bits    ; 78 LEs        ; 24 LEs               ; 54 LEs                 ; Yes        ; |GR8RAM|SA[3]~reg0         ;
-; 20:1               ; 3 bits    ; 39 LEs        ; 18 LEs               ; 21 LEs                 ; Yes        ; |GR8RAM|SA[1]~reg0         ;
-; 3:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |GR8RAM|WRD[7]             ;
-; 4:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; Yes        ; |GR8RAM|RDD[1]             ;
-; 5:1                ; 4 bits    ; 12 LEs        ; 8 LEs                ; 4 LEs                  ; Yes        ; |GR8RAM|RDD[4]             ;
+; 4:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |GR8RAM|SA[9]~reg0         ;
+; 20:1               ; 6 bits    ; 78 LEs        ; 24 LEs               ; 54 LEs                 ; Yes        ; |GR8RAM|SA[8]~reg0         ;
+; 20:1               ; 2 bits    ; 26 LEs        ; 12 LEs               ; 14 LEs                 ; Yes        ; |GR8RAM|SA[1]~reg0         ;
+; 3:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |GR8RAM|WRD[0]             ;
+; 5:1                ; 7 bits    ; 21 LEs        ; 14 LEs               ; 7 LEs                  ; Yes        ; |GR8RAM|RDD[0]             ;
 ; 18:1               ; 2 bits    ; 24 LEs        ; 8 LEs                ; 16 LEs                 ; Yes        ; |GR8RAM|DQMH~reg0          ;
-; 8:1                ; 5 bits    ; 25 LEs        ; 20 LEs               ; 5 LEs                  ; No         ; |GR8RAM|IS                 ;
+; 7:1                ; 5 bits    ; 20 LEs        ; 20 LEs               ; 0 LEs                  ; No         ; |GR8RAM|IS                 ;
 +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
 
 
@@ -272,45 +277,50 @@ Encoding Type:  Minimal Bits
 ; Analysis & Synthesis Messages ;
 +-------------------------------+
 Info: *******************************************************************
-Info: Running Quartus II 64-Bit Analysis & Synthesis
-    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
-    Info: Processing started: Tue Sep 14 01:35:25 2021
+Info: Running Quartus Prime Analysis & Synthesis
+    Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+    Info: Processing started: Tue Mar 28 05:06:13 2023
 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM
-Warning (20028): Parallel compilation is not licensed and has been disabled
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
 Info (12021): Found 1 design units, including 1 entities, in source file gr8ram.v
-    Info (12023): Found entity 1: GR8RAM
+    Info (12023): Found entity 1: GR8RAM File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 1
 Info (12127): Elaborating entity "GR8RAM" for the top level hierarchy
-Warning (10230): Verilog HDL assignment warning at GR8RAM.v(42): truncated value with size 32 to match size of target (4)
-Warning (10230): Verilog HDL assignment warning at GR8RAM.v(47): truncated value with size 32 to match size of target (14)
-Warning (10230): Verilog HDL assignment warning at GR8RAM.v(134): truncated value with size 32 to match size of target (8)
-Warning (10230): Verilog HDL assignment warning at GR8RAM.v(142): truncated value with size 32 to match size of target (8)
-Warning (10230): Verilog HDL assignment warning at GR8RAM.v(149): truncated value with size 32 to match size of target (8)
+Warning (10230): Verilog HDL assignment warning at GR8RAM.v(34): truncated value with size 32 to match size of target (4) File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 34
+Warning (10230): Verilog HDL assignment warning at GR8RAM.v(39): truncated value with size 32 to match size of target (14) File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 39
+Warning (10230): Verilog HDL assignment warning at GR8RAM.v(128): truncated value with size 32 to match size of target (8) File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 128
+Warning (10230): Verilog HDL assignment warning at GR8RAM.v(136): truncated value with size 32 to match size of target (8) File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 136
+Warning (10230): Verilog HDL assignment warning at GR8RAM.v(143): truncated value with size 32 to match size of target (8) File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 143
 Info (17026): Resynthesizing 0 WYSIWYG logic cells and I/Os using "area" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched
 Warning (13024): Output pins are stuck at VCC or GND
-    Warning (13410): Pin "nNMIout" is stuck at VCC
-    Warning (13410): Pin "nIRQout" is stuck at VCC
-    Warning (13410): Pin "nRDYout" is stuck at VCC
-    Warning (13410): Pin "nINHout" is stuck at VCC
-    Warning (13410): Pin "RWout" is stuck at VCC
-    Warning (13410): Pin "nDMAout" is stuck at VCC
-    Warning (13410): Pin "RAdir" is stuck at VCC
+    Warning (13410): Pin "nNMIout" is stuck at VCC File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 559
+    Warning (13410): Pin "nIRQout" is stuck at VCC File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 562
+    Warning (13410): Pin "nRDYout" is stuck at VCC File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 561
+    Warning (13410): Pin "nINHout" is stuck at VCC File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 560
+    Warning (13410): Pin "RWout" is stuck at VCC File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 563
+    Warning (13410): Pin "nDMAout" is stuck at VCC File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 558
+    Warning (13410): Pin "RAdir" is stuck at VCC File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 557
+    Warning (13410): Pin "SBA[0]" is stuck at GND File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 442
 Info (17049): 1 registers lost all their fanouts during netlist optimizations.
-Info (21057): Implemented 337 device resources after synthesis - the final resource count might be different
+Warning (21074): Design contains 2 input pin(s) that do not drive logic
+    Warning (15610): No output dependent on input pin "SetFW[0]" File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 23
+    Warning (15610): No output dependent on input pin "SetFW[1]" File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 23
+Info (21057): Implemented 336 device resources after synthesis - the final resource count might be different
     Info (21058): Implemented 28 input pins
     Info (21059): Implemented 35 output pins
     Info (21060): Implemented 17 bidirectional pins
-    Info (21061): Implemented 257 logic cells
-Info (144001): Generated suppressed messages file C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg
-Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 14 warnings
-    Info: Peak virtual memory: 422 megabytes
-    Info: Processing ended: Tue Sep 14 01:35:27 2021
-    Info: Elapsed time: 00:00:02
-    Info: Total CPU time (on all processors): 00:00:01
+    Info (21061): Implemented 256 logic cells
+Info (144001): Generated suppressed messages file Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg
+Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 18 warnings
+    Info: Peak virtual memory: 13094 megabytes
+    Info: Processing ended: Tue Mar 28 05:06:31 2023
+    Info: Elapsed time: 00:00:18
+    Info: Total CPU time (on all processors): 00:00:39
 
 
 +------------------------------------------+
 ; Analysis & Synthesis Suppressed Messages ;
 +------------------------------------------+
-The suppressed messages can be found in C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg.
+The suppressed messages can be found in Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg.
 
 
diff --git a/cpld/output_files/GR8RAM.map.smsg b/cpld/output_files/GR8RAM.map.smsg
index 91314af..c551f98 100755
--- a/cpld/output_files/GR8RAM.map.smsg
+++ b/cpld/output_files/GR8RAM.map.smsg
@@ -1,2 +1,2 @@
-Warning (10273): Verilog HDL warning at GR8RAM.v(110): extended using "x" or "z"
-Warning (10273): Verilog HDL warning at GR8RAM.v(286): extended using "x" or "z"
+Warning (10273): Verilog HDL warning at GR8RAM.v(104): extended using "x" or "z" File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 104
+Warning (10273): Verilog HDL warning at GR8RAM.v(281): extended using "x" or "z" File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 281
diff --git a/cpld/output_files/GR8RAM.map.summary b/cpld/output_files/GR8RAM.map.summary
index 6277dc1..9859dd1 100755
--- a/cpld/output_files/GR8RAM.map.summary
+++ b/cpld/output_files/GR8RAM.map.summary
@@ -1,9 +1,9 @@
-Analysis & Synthesis Status : Successful - Tue Sep 14 01:35:27 2021
-Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+Analysis & Synthesis Status : Successful - Tue Mar 28 05:06:31 2023
+Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
 Revision Name : GR8RAM
 Top-level Entity Name : GR8RAM
 Family : MAX II
-Total logic elements : 257
+Total logic elements : 256
 Total pins : 80
 Total virtual pins : 0
 UFM blocks : 0 / 1 ( 0 % )
diff --git a/cpld/output_files/GR8RAM.pin b/cpld/output_files/GR8RAM.pin
old mode 100755
new mode 100644
index c0079bd..de2fc19
--- a/cpld/output_files/GR8RAM.pin
+++ b/cpld/output_files/GR8RAM.pin
@@ -1,21 +1,22 @@
- -- Copyright (C) 1991-2013 Altera Corporation
- -- Your use of Altera Corporation's design tools, logic functions 
- -- and other software and tools, and its AMPP partner logic 
+ -- Copyright (C) 2019  Intel Corporation. All rights reserved.
+ -- Your use of Intel Corporation's design tools, logic functions 
+ -- and other software and tools, and any partner logic 
  -- functions, and any output files from any of the foregoing 
  -- (including device programming or simulation files), and any 
  -- associated documentation or information are expressly subject 
- -- to the terms and conditions of the Altera Program License 
- -- Subscription Agreement, Altera MegaCore Function License 
- -- Agreement, or other applicable license agreement, including, 
- -- without limitation, that your use is for the sole purpose of 
- -- programming logic devices manufactured by Altera and sold by 
- -- Altera or its authorized distributors.  Please refer to the 
- -- applicable agreement for further details.
+ -- to the terms and conditions of the Intel Program License 
+ -- Subscription Agreement, the Intel Quartus Prime License Agreement,
+ -- the Intel FPGA IP License Agreement, or other applicable license
+ -- agreement, including, without limitation, that your use is for
+ -- the sole purpose of programming logic devices manufactured by
+ -- Intel and sold by Intel or its authorized distributors.  Please
+ -- refer to the applicable agreement for further details, at
+ -- https://fpgasoftware.intel.com/eula.
  -- 
- -- This is a Quartus II output file. It is for reporting purposes only, and is
- -- not intended for use as a Quartus II input file. This file cannot be used
- -- to make Quartus II pin assignments - for instructions on how to make pin
- -- assignments, please see Quartus II help.
+ -- This is a Quartus Prime output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus Prime input file. This file cannot be used
+ -- to make Quartus Prime pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus Prime help.
  ---------------------------------------------------------------------------------
 
 
@@ -26,24 +27,24 @@
  -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (2.5V/3.3V).
  -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
  --                 of its bank.
- --					Bank 1:		3.3V
- --					Bank 2:		3.3V
+ --                  Bank 1:       3.3V
+ --                  Bank 2:       3.3V
  -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
- --					It can also be used to report unused dedicated pins. The connection
- --					on the board for unused dedicated pins depends on whether this will
- --					be used in a future design. One example is device migration. When
- --					using device migration, refer to the device pin-tables. If it is a
- --					GND pin in the pin table or if it will not be used in a future design
- --					for another purpose the it MUST be connected to GND. If it is an unused
- --					dedicated pin, then it can be connected to a valid signal on the board
- --					(low, high, or toggling) if that signal is required for a different
- --					revision of the design.
+ --                  It can also be used to report unused dedicated pins. The connection
+ --                  on the board for unused dedicated pins depends on whether this will
+ --                  be used in a future design. One example is device migration. When
+ --                  using device migration, refer to the device pin-tables. If it is a
+ --                  GND pin in the pin table or if it will not be used in a future design
+ --                  for another purpose the it MUST be connected to GND. If it is an unused
+ --                  dedicated pin, then it can be connected to a valid signal on the board
+ --                  (low, high, or toggling) if that signal is required for a different
+ --                  revision of the design.
  -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
- --					This pin should be connected to GND. It may also be connected  to a
- --					valid signal  on the board  (low, high, or toggling)  if that signal
- --					is required for a different revision of the design.
+ --                  This pin should be connected to GND. It may also be connected  to a
+ --                  valid signal  on the board  (low, high, or toggling)  if that signal
+ --                  is required for a different revision of the design.
  -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND
- --           	    or leave it unconnected.
+ --                  or leave it unconnected.
  -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
  -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
  -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
@@ -57,7 +58,7 @@
  -- Pin directions (input, output or bidir) are based on device operating in user mode.
  ---------------------------------------------------------------------------------
 
-Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
 CHIP  "GR8RAM"  ASSIGNED TO AN: EPM240T100C5
 
 Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
diff --git a/cpld/output_files/GR8RAM.pof b/cpld/output_files/GR8RAM.pof
index f433911..46b446e 100755
Binary files a/cpld/output_files/GR8RAM.pof and b/cpld/output_files/GR8RAM.pof differ
diff --git a/cpld/output_files/GR8RAM.sld b/cpld/output_files/GR8RAM.sld
new file mode 100644
index 0000000..f7d3ed7
--- /dev/null
+++ b/cpld/output_files/GR8RAM.sld
@@ -0,0 +1 @@
+<sld_project_info/>
diff --git a/cpld/output_files/GR8RAM.sta.rpt b/cpld/output_files/GR8RAM.sta.rpt
old mode 100755
new mode 100644
index 07fc1a7..a0539b9
--- a/cpld/output_files/GR8RAM.sta.rpt
+++ b/cpld/output_files/GR8RAM.sta.rpt
@@ -1,13 +1,13 @@
-TimeQuest Timing Analyzer report for GR8RAM
-Tue Sep 14 01:35:34 2021
-Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+Timing Analyzer report for GR8RAM
+Tue Mar 28 05:06:39 2023
+Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
 
 
 ---------------------
 ; Table of Contents ;
 ---------------------
   1. Legal Notice
-  2. TimeQuest Timing Analyzer Summary
+  2. Timing Analyzer Summary
   3. Parallel Compilation
   4. SDC File List
   5. Clocks
@@ -21,70 +21,71 @@ Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit
  13. Hold: 'C25M'
  14. Recovery: 'C25M'
  15. Removal: 'C25M'
- 16. Minimum Pulse Width: 'C25M'
- 17. Minimum Pulse Width: 'PHI0'
- 18. Setup Times
- 19. Hold Times
- 20. Clock to Output Times
- 21. Minimum Clock to Output Times
- 22. Propagation Delay
- 23. Minimum Propagation Delay
- 24. Output Enable Times
- 25. Minimum Output Enable Times
- 26. Output Disable Times
- 27. Minimum Output Disable Times
- 28. Setup Transfers
- 29. Hold Transfers
- 30. Recovery Transfers
- 31. Removal Transfers
- 32. Report TCCS
- 33. Report RSKM
- 34. Unconstrained Paths
- 35. TimeQuest Timing Analyzer Messages
+ 16. Setup Transfers
+ 17. Hold Transfers
+ 18. Recovery Transfers
+ 19. Removal Transfers
+ 20. Report TCCS
+ 21. Report RSKM
+ 22. Unconstrained Paths Summary
+ 23. Clock Status Summary
+ 24. Unconstrained Input Ports
+ 25. Unconstrained Output Ports
+ 26. Unconstrained Input Ports
+ 27. Unconstrained Output Ports
+ 28. Timing Analyzer Messages
 
 
 
 ----------------
 ; Legal Notice ;
 ----------------
-Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
+Copyright (C) 2019  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
 functions, and any output files from any of the foregoing 
 (including device programming or simulation files), and any 
 associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
 
 
 
-+----------------------------------------------------------------------------------------+
-; TimeQuest Timing Analyzer Summary                                                      ;
-+--------------------+-------------------------------------------------------------------+
-; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ;
-; Revision Name      ; GR8RAM                                                            ;
-; Device Family      ; MAX II                                                            ;
-; Device Name        ; EPM240T100C5                                                      ;
-; Timing Models      ; Final                                                             ;
-; Delay Model        ; Slow Model                                                        ;
-; Rise/Fall Delays   ; Unavailable                                                       ;
-+--------------------+-------------------------------------------------------------------+
++-----------------------------------------------------------------------------+
+; Timing Analyzer Summary                                                     ;
++-----------------------+-----------------------------------------------------+
+; Quartus Prime Version ; Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
+; Timing Analyzer       ; Legacy Timing Analyzer                              ;
+; Revision Name         ; GR8RAM                                              ;
+; Device Family         ; MAX II                                              ;
+; Device Name           ; EPM240T100C5                                        ;
+; Timing Models         ; Final                                               ;
+; Delay Model           ; Slow Model                                          ;
+; Rise/Fall Delays      ; Unavailable                                         ;
++-----------------------+-----------------------------------------------------+
 
 
-Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
-+-------------------------------------+
-; Parallel Compilation                ;
-+----------------------------+--------+
-; Processors                 ; Number ;
-+----------------------------+--------+
-; Number detected on machine ; 12     ;
-; Maximum allowed            ; 1      ;
-+----------------------------+--------+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 4           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 2           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processor 2            ;   0.2%      ;
++----------------------------+-------------+
 
 
 +---------------------------------------------------+
@@ -92,7 +93,7 @@ Parallel compilation was disabled, but you have multiple processors available. E
 +---------------+--------+--------------------------+
 ; SDC File Path ; Status ; Read at                  ;
 +---------------+--------+--------------------------+
-; GR8RAM.sdc    ; OK     ; Tue Sep 14 01:35:33 2021 ;
+; GR8RAM.sdc    ; OK     ; Tue Mar 28 05:06:39 2023 ;
 +---------------+--------+--------------------------+
 
 
@@ -111,7 +112,7 @@ Parallel compilation was disabled, but you have multiple processors available. E
 +-----------+-----------------+------------+------+
 ; Fmax      ; Restricted Fmax ; Clock Name ; Note ;
 +-----------+-----------------+------------+------+
-; 65.95 MHz ; 65.95 MHz       ; C25M       ;      ;
+; 66.42 MHz ; 66.42 MHz       ; C25M       ;      ;
 +-----------+-----------------+------------+------+
 This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
 
@@ -121,7 +122,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
 +-------+--------+---------------+
 ; Clock ; Slack  ; End Point TNS ;
 +-------+--------+---------------+
-; C25M  ; 12.419 ; 0.000         ;
+; C25M  ; 12.472 ; 0.000         ;
 +-------+--------+---------------+
 
 
@@ -130,7 +131,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
 +-------+-------+---------------+
 ; Clock ; Slack ; End Point TNS ;
 +-------+-------+---------------+
-; C25M  ; 1.393 ; 0.000         ;
+; C25M  ; 1.383 ; 0.000         ;
 +-------+-------+---------------+
 
 
@@ -139,7 +140,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
 +-------+--------+---------------+
 ; Clock ; Slack  ; End Point TNS ;
 +-------+--------+---------------+
-; C25M  ; 33.300 ; 0.000         ;
+; C25M  ; 33.331 ; 0.000         ;
 +-------+--------+---------------+
 
 
@@ -148,7 +149,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
 +-------+-------+---------------+
 ; Clock ; Slack ; End Point TNS ;
 +-------+-------+---------------+
-; C25M  ; 6.146 ; 0.000         ;
+; C25M  ; 6.115 ; 0.000         ;
 +-------+-------+---------------+
 
 
@@ -167,106 +168,106 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
 +--------+----------------+----------------+--------------+-------------+--------------+------------+------------+
 ; Slack  ; From Node      ; To Node        ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
 +--------+----------------+----------------+--------------+-------------+--------------+------------+------------+
-; 12.419 ; REGEN          ; RDD[7]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 7.248      ;
-; 12.825 ; REGEN          ; RDD[4]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 6.842      ;
-; 12.826 ; REGEN          ; RDD[6]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 6.841      ;
-; 12.830 ; REGEN          ; RDD[5]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 6.837      ;
-; 12.861 ; REGEN          ; RDD[3]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 6.806      ;
-; 12.948 ; Addr[7]        ; RDD[7]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 6.719      ;
-; 13.317 ; REGEN          ; RDD[2]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 6.350      ;
-; 13.332 ; PS[2]          ; RDD[0]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 6.335      ;
-; 13.332 ; PS[2]          ; RDD[1]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 6.335      ;
-; 13.485 ; REGEN          ; RDD[1]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 6.182      ;
-; 13.494 ; REGEN          ; RDD[0]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 6.173      ;
-; 13.610 ; PS[1]          ; RDD[0]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 6.057      ;
-; 13.610 ; PS[1]          ; RDD[1]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 6.057      ;
-; 13.611 ; PS[3]          ; RDD[0]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 6.056      ;
-; 13.611 ; PS[3]          ; RDD[1]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 6.056      ;
-; 13.692 ; Addr[14]       ; RDD[6]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.975      ;
-; 13.794 ; Addr[15]       ; RDD[7]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.873      ;
-; 13.950 ; Addr[10]       ; RDD[2]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.717      ;
-; 13.955 ; PS[2]          ; RDD[3]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.712      ;
-; 13.958 ; Addr[12]       ; RDD[4]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.709      ;
-; 13.965 ; Addr[4]        ; RDD[4]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.702      ;
-; 14.046 ; PS[0]          ; RDD[0]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.621      ;
-; 14.046 ; PS[0]          ; RDD[1]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.621      ;
-; 14.233 ; PS[1]          ; RDD[3]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.434      ;
-; 14.234 ; PS[3]          ; RDD[3]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.433      ;
-; 14.257 ; Addr[13]       ; RDD[5]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.410      ;
-; 14.387 ; PS[2]          ; RDD[2]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.280      ;
-; 14.387 ; PS[2]          ; RDD[4]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.280      ;
-; 14.387 ; PS[2]          ; RDD[5]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.280      ;
-; 14.387 ; PS[2]          ; RDD[6]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.280      ;
-; 14.387 ; PS[2]          ; RDD[7]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.280      ;
-; 14.407 ; Addr[11]       ; RDD[3]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.260      ;
-; 14.442 ; Addr[6]        ; RDD[6]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.225      ;
-; 14.448 ; Addr[5]        ; RDD[5]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.219      ;
-; 14.638 ; Addr[19]       ; RDD[3]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.029      ;
-; 14.650 ; Addr[3]        ; RDD[3]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.017      ;
-; 14.665 ; PS[1]          ; RDD[2]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.002      ;
-; 14.665 ; PS[1]          ; RDD[4]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.002      ;
-; 14.665 ; PS[1]          ; RDD[5]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.002      ;
-; 14.665 ; PS[1]          ; RDD[6]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.002      ;
-; 14.665 ; PS[1]          ; RDD[7]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.002      ;
-; 14.666 ; PS[3]          ; RDD[2]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.001      ;
-; 14.666 ; PS[3]          ; RDD[4]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.001      ;
-; 14.666 ; PS[3]          ; RDD[5]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.001      ;
-; 14.666 ; PS[3]          ; RDD[6]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.001      ;
-; 14.666 ; PS[3]          ; RDD[7]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.001      ;
-; 14.669 ; PS[0]          ; RDD[3]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 4.998      ;
-; 14.690 ; Addr[22]       ; RDD[6]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 4.977      ;
-; 14.700 ; Addr[16]       ; RDD[0]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 4.967      ;
-; 14.800 ; SetFWr[1]      ; RDD[4]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 4.867      ;
-; 14.801 ; SetFWr[1]      ; RDD[6]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 4.866      ;
-; 14.805 ; SetFWr[1]      ; RDD[5]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 4.862      ;
-; 14.871 ; Addr[9]        ; RDD[1]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 4.796      ;
-; 14.878 ; Addr[8]        ; RDD[0]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 4.789      ;
-; 15.101 ; PS[0]          ; RDD[2]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 4.566      ;
-; 15.101 ; PS[0]          ; RDD[4]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 4.566      ;
-; 15.101 ; PS[0]          ; RDD[5]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 4.566      ;
-; 15.101 ; PS[0]          ; RDD[6]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 4.566      ;
-; 15.101 ; PS[0]          ; RDD[7]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 4.566      ;
-; 15.384 ; Addr[21]       ; RDD[5]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 4.283      ;
-; 15.456 ; Addr[2]        ; RDD[2]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 4.211      ;
-; 15.469 ; Addr[20]       ; RDD[4]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 4.198      ;
-; 15.505 ; Addr[23]       ; RDD[7]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 4.162      ;
-; 15.510 ; SetFWr[1]      ; RDD[7]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 4.157      ;
-; 15.817 ; Addr[18]       ; RDD[2]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 3.850      ;
-; 15.897 ; Addr[17]       ; RDD[1]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 3.770      ;
-; 16.230 ; Addr[1]        ; RDD[1]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 3.437      ;
-; 16.377 ; Addr[0]        ; RDD[0]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 3.290      ;
-; 25.936 ; REGEN          ; SA[1]~reg0     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 13.731     ;
-; 26.182 ; REGEN          ; SA[0]~reg0     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 13.485     ;
-; 26.524 ; REGEN          ; SA[2]~reg0     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 13.143     ;
-; 26.906 ; Addr[23]       ; SA[1]~reg0     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 12.761     ;
-; 27.133 ; REGEN          ; RCKE~reg0      ; C25M         ; C25M        ; 40.000       ; 0.000      ; 12.534     ;
-; 27.152 ; Addr[23]       ; SA[0]~reg0     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 12.515     ;
-; 27.487 ; REGEN          ; SA[8]~reg0     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 12.180     ;
-; 27.494 ; Addr[23]       ; SA[2]~reg0     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 12.173     ;
-; 27.513 ; IS.state_bit_1 ; SA[1]~reg0     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 12.154     ;
-; 27.759 ; IS.state_bit_1 ; SA[0]~reg0     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 11.908     ;
-; 27.761 ; REGEN          ; SA[5]~reg0     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 11.906     ;
-; 27.882 ; IS.state_bit_0 ; SA[1]~reg0     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 11.785     ;
-; 27.915 ; REGEN          ; SA[4]~reg0     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 11.752     ;
-; 28.015 ; IS.state_bit_1 ; RCKE~reg0      ; C25M         ; C25M        ; 40.000       ; 0.000      ; 11.652     ;
-; 28.101 ; IS.state_bit_1 ; SA[2]~reg0     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 11.566     ;
-; 28.103 ; Addr[23]       ; RCKE~reg0      ; C25M         ; C25M        ; 40.000       ; 0.000      ; 11.564     ;
-; 28.107 ; PS[1]          ; SA[1]~reg0     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 11.560     ;
-; 28.128 ; IS.state_bit_0 ; SA[0]~reg0     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 11.539     ;
-; 28.154 ; REGEN          ; SA[6]~reg0     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 11.513     ;
-; 28.192 ; IS.state_bit_0 ; RCKE~reg0      ; C25M         ; C25M        ; 40.000       ; 0.000      ; 11.475     ;
-; 28.245 ; PS[1]          ; SA[2]~reg0     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 11.422     ;
-; 28.350 ; REGEN          ; nRCS~reg0      ; C25M         ; C25M        ; 40.000       ; 0.000      ; 11.317     ;
-; 28.456 ; PS[0]          ; SA[1]~reg0     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 11.211     ;
-; 28.457 ; Addr[23]       ; SA[8]~reg0     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 11.210     ;
-; 28.470 ; IS.state_bit_0 ; SA[2]~reg0     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 11.197     ;
-; 28.515 ; REGEN          ; SA[3]~reg0     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 11.152     ;
-; 28.594 ; PS[0]          ; SA[2]~reg0     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 11.073     ;
-; 28.638 ; SetFWr[0]      ; SA[1]~reg0     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 11.029     ;
-; 28.731 ; Addr[23]       ; SA[5]~reg0     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 10.936     ;
-; 28.806 ; LS[10]         ; IS.state_bit_0 ; C25M         ; C25M        ; 40.000       ; 0.000      ; 10.861     ;
-; 28.812 ; REGEN          ; SA[7]~reg0     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 10.855     ;
-; 28.884 ; SetFWr[0]      ; SA[0]~reg0     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 10.783     ;
+; 12.472 ; REGEN          ; RDD[5]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 7.195      ;
+; 12.473 ; REGEN          ; RDD[3]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 7.194      ;
+; 12.485 ; REGEN          ; RDD[6]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 7.182      ;
+; 12.571 ; REGEN          ; RDD[0]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 7.096      ;
+; 12.858 ; REGEN          ; RDD[2]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 6.809      ;
+; 12.946 ; REGEN          ; RDD[1]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 6.721      ;
+; 12.947 ; REGEN          ; RDD[4]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 6.720      ;
+; 13.462 ; PS[3]          ; RDD[7]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 6.205      ;
+; 13.543 ; PS[3]          ; RDD[3]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 6.124      ;
+; 13.543 ; PS[3]          ; RDD[5]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 6.124      ;
+; 13.543 ; PS[3]          ; RDD[6]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 6.124      ;
+; 13.649 ; PS[2]          ; RDD[7]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 6.018      ;
+; 13.668 ; Addr[3]        ; RDD[3]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.999      ;
+; 13.730 ; PS[2]          ; RDD[3]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.937      ;
+; 13.730 ; PS[2]          ; RDD[5]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.937      ;
+; 13.730 ; PS[2]          ; RDD[6]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.937      ;
+; 13.825 ; REGEN          ; RDD[7]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.842      ;
+; 13.979 ; PS[1]          ; RDD[7]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.688      ;
+; 14.060 ; PS[1]          ; RDD[3]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.607      ;
+; 14.060 ; PS[1]          ; RDD[5]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.607      ;
+; 14.060 ; PS[1]          ; RDD[6]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.607      ;
+; 14.184 ; PS[3]          ; RDD[1]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.483      ;
+; 14.184 ; PS[3]          ; RDD[2]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.483      ;
+; 14.184 ; PS[3]          ; RDD[4]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.483      ;
+; 14.210 ; Addr[0]        ; RDD[0]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.457      ;
+; 14.328 ; PS[0]          ; RDD[7]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.339      ;
+; 14.366 ; Addr[2]        ; RDD[2]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.301      ;
+; 14.371 ; PS[2]          ; RDD[1]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.296      ;
+; 14.371 ; PS[2]          ; RDD[2]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.296      ;
+; 14.371 ; PS[2]          ; RDD[4]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.296      ;
+; 14.390 ; Addr[1]        ; RDD[1]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.277      ;
+; 14.409 ; PS[0]          ; RDD[3]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.258      ;
+; 14.409 ; PS[0]          ; RDD[5]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.258      ;
+; 14.409 ; PS[0]          ; RDD[6]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.258      ;
+; 14.445 ; Addr[4]        ; RDD[4]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.222      ;
+; 14.496 ; Addr[23]       ; RDD[7]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.171      ;
+; 14.622 ; PS[3]          ; RDD[0]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 5.045      ;
+; 14.701 ; PS[1]          ; RDD[1]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 4.966      ;
+; 14.701 ; PS[1]          ; RDD[2]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 4.966      ;
+; 14.701 ; PS[1]          ; RDD[4]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 4.966      ;
+; 14.707 ; Addr[8]        ; RDD[0]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 4.960      ;
+; 14.709 ; Addr[15]       ; RDD[7]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 4.958      ;
+; 14.809 ; PS[2]          ; RDD[0]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 4.858      ;
+; 15.050 ; PS[0]          ; RDD[1]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 4.617      ;
+; 15.050 ; PS[0]          ; RDD[2]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 4.617      ;
+; 15.050 ; PS[0]          ; RDD[4]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 4.617      ;
+; 15.061 ; Addr[5]        ; RDD[5]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 4.606      ;
+; 15.128 ; Addr[6]        ; RDD[6]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 4.539      ;
+; 15.139 ; PS[1]          ; RDD[0]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 4.528      ;
+; 15.199 ; Addr[10]       ; RDD[2]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 4.468      ;
+; 15.284 ; Addr[12]       ; RDD[4]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 4.383      ;
+; 15.322 ; Addr[7]        ; RDD[7]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 4.345      ;
+; 15.488 ; PS[0]          ; RDD[0]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 4.179      ;
+; 15.722 ; Addr[9]        ; RDD[1]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 3.945      ;
+; 16.006 ; Addr[16]       ; RDD[0]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 3.661      ;
+; 16.012 ; Addr[20]       ; RDD[4]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 3.655      ;
+; 16.089 ; Addr[22]       ; RDD[6]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 3.578      ;
+; 16.110 ; Addr[21]       ; RDD[5]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 3.557      ;
+; 16.112 ; Addr[14]       ; RDD[6]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 3.555      ;
+; 16.133 ; Addr[17]       ; RDD[1]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 3.534      ;
+; 16.142 ; Addr[13]       ; RDD[5]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 3.525      ;
+; 16.144 ; Addr[18]       ; RDD[2]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 3.523      ;
+; 16.144 ; Addr[19]       ; RDD[3]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 3.523      ;
+; 16.300 ; Addr[11]       ; RDD[3]         ; C25M         ; C25M        ; 20.000       ; 0.000      ; 3.367      ;
+; 27.034 ; IS.state_bit_0 ; SA[3]~reg0     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 12.633     ;
+; 27.416 ; IS.state_bit_0 ; SA[6]~reg0     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 12.251     ;
+; 27.568 ; Addr[23]       ; SA[4]~reg0     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 12.099     ;
+; 27.654 ; REGEN          ; SA[4]~reg0     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 12.013     ;
+; 27.717 ; Addr[23]       ; SA[5]~reg0     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 11.950     ;
+; 27.803 ; REGEN          ; SA[5]~reg0     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 11.864     ;
+; 27.841 ; IS.state_bit_1 ; SA[3]~reg0     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 11.826     ;
+; 28.219 ; Addr[23]       ; SA[3]~reg0     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 11.448     ;
+; 28.223 ; IS.state_bit_1 ; SA[6]~reg0     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 11.444     ;
+; 28.238 ; LS[1]          ; IS.state_bit_1 ; C25M         ; C25M        ; 40.000       ; 0.000      ; 11.429     ;
+; 28.251 ; Addr[23]       ; SA[7]~reg0     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 11.416     ;
+; 28.266 ; Addr[23]       ; SA[8]~reg0     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 11.401     ;
+; 28.305 ; REGEN          ; SA[3]~reg0     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 11.362     ;
+; 28.337 ; REGEN          ; SA[7]~reg0     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 11.330     ;
+; 28.352 ; REGEN          ; SA[8]~reg0     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 11.315     ;
+; 28.419 ; IS.state_bit_0 ; SA[8]~reg0     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 11.248     ;
+; 28.423 ; IS.state_bit_0 ; SA[7]~reg0     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 11.244     ;
+; 28.431 ; LS[7]          ; IS.state_bit_1 ; C25M         ; C25M        ; 40.000       ; 0.000      ; 11.236     ;
+; 28.447 ; LS[10]         ; IS.state_bit_1 ; C25M         ; C25M        ; 40.000       ; 0.000      ; 11.220     ;
+; 28.462 ; LS[3]          ; IS.state_bit_1 ; C25M         ; C25M        ; 40.000       ; 0.000      ; 11.205     ;
+; 28.464 ; LS[1]          ; IS.state_bit_0 ; C25M         ; C25M        ; 40.000       ; 0.000      ; 11.203     ;
+; 28.566 ; Addr[23]       ; SA[6]~reg0     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 11.101     ;
+; 28.594 ; LS[9]          ; IS.state_bit_1 ; C25M         ; C25M        ; 40.000       ; 0.000      ; 11.073     ;
+; 28.605 ; Addr[23]       ; nRCS~reg0      ; C25M         ; C25M        ; 40.000       ; 0.000      ; 11.062     ;
+; 28.611 ; Addr[23]       ; SA[0]~reg0     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 11.056     ;
+; 28.652 ; REGEN          ; SA[6]~reg0     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 11.015     ;
+; 28.657 ; LS[7]          ; IS.state_bit_0 ; C25M         ; C25M        ; 40.000       ; 0.000      ; 11.010     ;
+; 28.673 ; LS[10]         ; IS.state_bit_0 ; C25M         ; C25M        ; 40.000       ; 0.000      ; 10.994     ;
+; 28.688 ; LS[3]          ; IS.state_bit_0 ; C25M         ; C25M        ; 40.000       ; 0.000      ; 10.979     ;
+; 28.691 ; REGEN          ; nRCS~reg0      ; C25M         ; C25M        ; 40.000       ; 0.000      ; 10.976     ;
+; 28.696 ; Addr[23]       ; RCKE~reg0      ; C25M         ; C25M        ; 40.000       ; 0.000      ; 10.971     ;
+; 28.697 ; REGEN          ; SA[0]~reg0     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 10.970     ;
+; 28.720 ; Addr[23]       ; SA[1]~reg0     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 10.947     ;
+; 28.782 ; REGEN          ; RCKE~reg0      ; C25M         ; C25M        ; 40.000       ; 0.000      ; 10.885     ;
+; 28.784 ; LS[11]         ; IS.state_bit_1 ; C25M         ; C25M        ; 40.000       ; 0.000      ; 10.883     ;
+; 28.806 ; REGEN          ; SA[1]~reg0     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 10.861     ;
 +--------+----------------+----------------+--------------+-------------+--------------+------------+------------+
 
 
@@ -275,106 +276,106 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
 +-------+----------------+----------------+--------------+-------------+--------------+------------+------------+
 ; Slack ; From Node      ; To Node        ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
 +-------+----------------+----------------+--------------+-------------+--------------+------------+------------+
-; 1.393 ; WRD[0]         ; WRD[0]         ; C25M         ; C25M        ; 0.000        ; 0.000      ; 1.614      ;
-; 1.400 ; PHI0r1         ; PHI0r2         ; C25M         ; C25M        ; 0.000        ; 0.000      ; 1.621      ;
-; 1.411 ; WRD[7]         ; WRD[7]         ; C25M         ; C25M        ; 0.000        ; 0.000      ; 1.632      ;
-; 1.413 ; nRESf[1]       ; nRESf[2]       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 1.634      ;
-; 1.418 ; WRD[4]         ; WRD[4]         ; C25M         ; C25M        ; 0.000        ; 0.000      ; 1.639      ;
-; 1.418 ; WRD[5]         ; WRD[5]         ; C25M         ; C25M        ; 0.000        ; 0.000      ; 1.639      ;
-; 1.420 ; WRD[1]         ; WRD[1]         ; C25M         ; C25M        ; 0.000        ; 0.000      ; 1.641      ;
-; 1.421 ; WRD[2]         ; WRD[2]         ; C25M         ; C25M        ; 0.000        ; 0.000      ; 1.642      ;
-; 1.645 ; WRD[3]         ; WRD[5]         ; C25M         ; C25M        ; 0.000        ; 0.000      ; 1.866      ;
-; 1.649 ; nRESout~reg0   ; nRESout~reg0   ; C25M         ; C25M        ; 0.000        ; 0.000      ; 1.870      ;
-; 1.661 ; REGEN          ; REGEN          ; C25M         ; C25M        ; 0.000        ; 0.000      ; 1.882      ;
-; 1.695 ; PS[2]          ; PS[2]          ; C25M         ; C25M        ; 0.000        ; 0.000      ; 1.916      ;
-; 1.734 ; PS[0]          ; PS[1]          ; C25M         ; C25M        ; 0.000        ; 0.000      ; 1.955      ;
-; 1.778 ; WRD[3]         ; WRD[3]         ; C25M         ; C25M        ; 0.000        ; 0.000      ; 1.999      ;
-; 1.840 ; nRESf[2]       ; nRESf[3]       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.061      ;
-; 1.930 ; Addr[15]       ; AddrIncH       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.151      ;
-; 1.939 ; Addr[7]        ; AddrIncM       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.160      ;
-; 1.944 ; nRESf[1]       ; nRESr          ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.165      ;
-; 1.958 ; PS[3]          ; PS[3]          ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.179      ;
-; 1.994 ; PS[1]          ; PS[1]          ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.215      ;
-; 2.003 ; PS[1]          ; PS[2]          ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.224      ;
-; 2.063 ; LS[13]         ; LS[13]         ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.284      ;
-; 2.117 ; Addr[10]       ; Addr[10]       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.338      ;
-; 2.117 ; Addr[1]        ; Addr[1]        ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.338      ;
-; 2.117 ; Addr[2]        ; Addr[2]        ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.338      ;
-; 2.117 ; Addr[9]        ; Addr[9]        ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.338      ;
+; 1.383 ; WRD[7]         ; WRD[7]         ; C25M         ; C25M        ; 0.000        ; 0.000      ; 1.604      ;
+; 1.384 ; WRD[6]         ; WRD[6]         ; C25M         ; C25M        ; 0.000        ; 0.000      ; 1.605      ;
+; 1.396 ; WRD[4]         ; WRD[4]         ; C25M         ; C25M        ; 0.000        ; 0.000      ; 1.617      ;
+; 1.412 ; nRESf[1]       ; nRESf[2]       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 1.633      ;
+; 1.422 ; nRESf[2]       ; nRESf[3]       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 1.643      ;
+; 1.652 ; WRD[1]         ; WRD[3]         ; C25M         ; C25M        ; 0.000        ; 0.000      ; 1.873      ;
+; 1.654 ; nRESf[3]       ; nRESr          ; C25M         ; C25M        ; 0.000        ; 0.000      ; 1.875      ;
+; 1.667 ; nRESout~reg0   ; nRESout~reg0   ; C25M         ; C25M        ; 0.000        ; 0.000      ; 1.888      ;
+; 1.667 ; REGEN          ; REGEN          ; C25M         ; C25M        ; 0.000        ; 0.000      ; 1.888      ;
+; 1.779 ; PS[1]          ; PS[1]          ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.000      ;
+; 1.780 ; PS[1]          ; nCAS~reg0      ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.001      ;
+; 1.785 ; PS[1]          ; PS[3]          ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.006      ;
+; 1.787 ; PS[1]          ; PS[2]          ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.008      ;
+; 1.825 ; nRESf[0]       ; nRESf[1]       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.046      ;
+; 1.880 ; WRD[0]         ; WRD[0]         ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.101      ;
+; 1.920 ; Addr[7]        ; AddrIncM       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.141      ;
+; 1.937 ; RestoreDone    ; RestoreDone    ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.158      ;
+; 1.942 ; nRESf[1]       ; nRESr          ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.163      ;
+; 1.961 ; PS[0]          ; PS[0]          ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.182      ;
+; 1.978 ; IS.state_bit_1 ; IS.state_bit_0 ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.199      ;
+; 1.996 ; LS[0]          ; LS[0]          ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.217      ;
+; 2.049 ; LS[13]         ; LS[13]         ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.270      ;
+; 2.108 ; Addr[15]       ; Addr[15]       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.329      ;
+; 2.117 ; Addr[17]       ; Addr[17]       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.338      ;
+; 2.117 ; Addr[18]       ; Addr[18]       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.338      ;
+; 2.117 ; WRD[5]         ; WRD[7]         ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.338      ;
 ; 2.125 ; Addr[16]       ; Addr[16]       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.346      ;
-; 2.125 ; Addr[8]        ; Addr[8]        ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.346      ;
 ; 2.126 ; Addr[23]       ; Addr[23]       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.347      ;
-; 2.126 ; Addr[17]       ; Addr[17]       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.347      ;
-; 2.127 ; LS[6]          ; LS[6]          ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.348      ;
-; 2.127 ; Addr[18]       ; Addr[18]       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.348      ;
-; 2.133 ; Addr[0]        ; Addr[0]        ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.354      ;
+; 2.126 ; Addr[10]       ; Addr[10]       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.347      ;
+; 2.126 ; Addr[9]        ; Addr[9]        ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.347      ;
+; 2.128 ; LS[6]          ; LS[6]          ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.349      ;
+; 2.129 ; Addr[7]        ; Addr[7]        ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.350      ;
 ; 2.133 ; LS[7]          ; LS[7]          ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.354      ;
-; 2.135 ; LS[0]          ; LS[0]          ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.356      ;
-; 2.137 ; Addr[15]       ; Addr[15]       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.358      ;
-; 2.138 ; LS[0]          ; LS[1]          ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.359      ;
-; 2.145 ; IOROMEN        ; IOROMEN        ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.366      ;
-; 2.145 ; Addr[7]        ; Addr[7]        ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.366      ;
-; 2.151 ; LS[8]          ; LS[8]          ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.372      ;
-; 2.153 ; LS[9]          ; LS[9]          ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.374      ;
-; 2.160 ; LS[4]          ; LS[4]          ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.381      ;
-; 2.160 ; WRD[5]         ; WRD[7]         ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.381      ;
-; 2.161 ; WRD[4]         ; WRD[6]         ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.382      ;
-; 2.166 ; PS[2]          ; PS[0]          ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.387      ;
-; 2.169 ; PS[2]          ; MOSIout        ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.390      ;
-; 2.222 ; Addr[19]       ; Addr[19]       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.443      ;
-; 2.230 ; Addr[5]        ; Addr[5]        ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.451      ;
+; 2.133 ; IS.state_bit_2 ; MOSIOE         ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.354      ;
+; 2.134 ; Addr[1]        ; Addr[1]        ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.355      ;
+; 2.136 ; IS.state_bit_2 ; nFCS~reg0      ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.357      ;
+; 2.143 ; LS[9]          ; LS[9]          ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.364      ;
+; 2.144 ; Addr[2]        ; Addr[2]        ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.365      ;
+; 2.144 ; LS[4]          ; LS[4]          ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.365      ;
+; 2.144 ; LS[8]          ; LS[8]          ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.365      ;
+; 2.148 ; RestoreDone    ; Bank           ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.369      ;
+; 2.199 ; IS.state_bit_0 ; IS.state_bit_0 ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.420      ;
+; 2.203 ; PS[2]          ; PS[2]          ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.424      ;
+; 2.210 ; PS[2]          ; MOSIout        ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.431      ;
+; 2.212 ; Addr[11]       ; Addr[11]       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.433      ;
+; 2.212 ; Addr[3]        ; Addr[3]        ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.433      ;
+; 2.212 ; LS[5]          ; LS[5]          ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.433      ;
+; 2.213 ; PS[2]          ; PS[3]          ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.434      ;
+; 2.214 ; IS.state_bit_0 ; nRESout~reg0   ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.435      ;
+; 2.221 ; Bank           ; Bank           ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.442      ;
+; 2.221 ; Addr[13]       ; Addr[13]       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.442      ;
+; 2.221 ; Addr[5]        ; Addr[5]        ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.442      ;
+; 2.222 ; PS[2]          ; nCAS~reg0      ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.443      ;
+; 2.222 ; Addr[14]       ; Addr[14]       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.443      ;
+; 2.222 ; Addr[6]        ; Addr[6]        ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.443      ;
+; 2.230 ; LS[12]         ; LS[12]         ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.451      ;
 ; 2.230 ; Addr[21]       ; Addr[21]       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.451      ;
-; 2.230 ; PS[0]          ; FCKout         ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.451      ;
-; 2.231 ; Addr[3]        ; Addr[3]        ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.452      ;
-; 2.231 ; Addr[4]        ; Addr[4]        ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.452      ;
-; 2.231 ; Addr[6]        ; Addr[6]        ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.452      ;
+; 2.231 ; Addr[19]       ; Addr[19]       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.452      ;
 ; 2.231 ; Addr[20]       ; Addr[20]       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.452      ;
 ; 2.231 ; Addr[22]       ; Addr[22]       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.452      ;
-; 2.232 ; Addr[11]       ; Addr[11]       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.453      ;
+; 2.234 ; WRD[4]         ; WRD[6]         ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.455      ;
+; 2.237 ; AddrIncH       ; Addr[16]       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.458      ;
+; 2.239 ; LS[2]          ; LS[2]          ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.460      ;
 ; 2.240 ; LS[1]          ; LS[1]          ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.461      ;
-; 2.240 ; LS[3]          ; LS[3]          ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.461      ;
-; 2.242 ; LS[10]         ; LS[10]         ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.463      ;
-; 2.248 ; LS[12]         ; LS[12]         ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.469      ;
-; 2.249 ; Addr[12]       ; Addr[12]       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.470      ;
-; 2.250 ; LS[11]         ; LS[11]         ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.471      ;
-; 2.251 ; LS[5]          ; LS[5]          ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.472      ;
-; 2.252 ; LS[2]          ; LS[2]          ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.473      ;
-; 2.260 ; Addr[13]       ; Addr[13]       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.481      ;
-; 2.261 ; WRD[2]         ; WRD[4]         ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.482      ;
-; 2.262 ; Addr[14]       ; Addr[14]       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.483      ;
-; 2.264 ; WRD[1]         ; WRD[3]         ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.485      ;
-; 2.310 ; PS[0]          ; PS[0]          ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.531      ;
-; 2.312 ; PS[0]          ; PS[2]          ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.533      ;
-; 2.317 ; Bank           ; Bank           ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.538      ;
-; 2.319 ; IS.state_bit_0 ; IS.state_bit_0 ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.540      ;
-; 2.333 ; IS.state_bit_0 ; nRESout~reg0   ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.554      ;
-; 2.345 ; PS[0]          ; MOSIout        ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.566      ;
-; 2.448 ; WRD[6]         ; WRD[6]         ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.669      ;
-; 2.521 ; nRESf[3]       ; nRESr          ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.742      ;
-; 2.531 ; IS.state_bit_1 ; nRESout~reg0   ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.752      ;
-; 2.660 ; PS[1]          ; nCAS~reg0      ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.881      ;
-; 2.673 ; nRESf[2]       ; nRESr          ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.894      ;
-; 2.708 ; PS[2]          ; nCAS~reg0      ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.929      ;
-; 2.709 ; PS[0]          ; nSWE~reg0      ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.930      ;
-; 2.753 ; IS.state_bit_1 ; IS.state_bit_0 ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.974      ;
-; 2.782 ; PS[0]          ; nCAS~reg0      ; C25M         ; C25M        ; 0.000        ; 0.000      ; 3.003      ;
-; 2.829 ; PS[0]          ; nRAS~reg0      ; C25M         ; C25M        ; 0.000        ; 0.000      ; 3.050      ;
-; 2.949 ; Addr[9]        ; Addr[10]       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 3.170      ;
-; 2.949 ; Addr[10]       ; Addr[11]       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 3.170      ;
-; 2.949 ; Addr[1]        ; Addr[2]        ; C25M         ; C25M        ; 0.000        ; 0.000      ; 3.170      ;
-; 2.949 ; Addr[2]        ; Addr[3]        ; C25M         ; C25M        ; 0.000        ; 0.000      ; 3.170      ;
+; 2.241 ; LS[10]         ; LS[10]         ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.462      ;
+; 2.241 ; LS[11]         ; LS[11]         ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.462      ;
+; 2.251 ; LS[3]          ; LS[3]          ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.472      ;
+; 2.253 ; nRESf[2]       ; nRESr          ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.474      ;
+; 2.262 ; IOROMEN        ; IOROMEN        ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.483      ;
+; 2.276 ; PS[3]          ; PS[3]          ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.497      ;
+; 2.283 ; PS[3]          ; nCAS~reg0      ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.504      ;
+; 2.290 ; WRD[2]         ; WRD[4]         ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.511      ;
+; 2.291 ; IS.state_bit_1 ; nRESout~reg0   ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.512      ;
+; 2.313 ; WRD[5]         ; WRD[5]         ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.534      ;
+; 2.364 ; PS[1]          ; MOSIout        ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.585      ;
+; 2.370 ; WRD[1]         ; WRD[1]         ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.591      ;
+; 2.448 ; WRD[3]         ; WRD[3]         ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.669      ;
+; 2.508 ; Addr[12]       ; Addr[12]       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.729      ;
+; 2.542 ; Addr[4]        ; Addr[4]        ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.763      ;
+; 2.547 ; LS[4]          ; SA[3]~reg0     ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.768      ;
+; 2.554 ; WRD[2]         ; WRD[2]         ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.775      ;
+; 2.557 ; nRESf[0]       ; nRESr          ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.778      ;
+; 2.582 ; PS[3]          ; nRCS~reg0      ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.803      ;
+; 2.595 ; Addr[0]        ; Addr[0]        ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.816      ;
+; 2.638 ; PHI0r1         ; PHI0r2         ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.859      ;
+; 2.652 ; IS.state_bit_0 ; MOSIOE         ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.873      ;
+; 2.655 ; IS.state_bit_0 ; nFCS~reg0      ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.876      ;
+; 2.656 ; PHI0r2         ; RCKE~reg0      ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.877      ;
+; 2.676 ; PS[2]          ; nRCS~reg0      ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.897      ;
+; 2.719 ; LS[7]          ; SA[6]~reg0     ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.940      ;
+; 2.720 ; WRD[0]         ; WRD[2]         ; C25M         ; C25M        ; 0.000        ; 0.000      ; 2.941      ;
+; 2.838 ; IS.state_bit_1 ; nFCS~reg0      ; C25M         ; C25M        ; 0.000        ; 0.000      ; 3.059      ;
+; 2.848 ; IS.state_bit_1 ; MOSIOE         ; C25M         ; C25M        ; 0.000        ; 0.000      ; 3.069      ;
+; 2.928 ; Addr[14]       ; SA[4]~reg0     ; C25M         ; C25M        ; 0.000        ; 0.000      ; 3.149      ;
+; 2.949 ; Addr[17]       ; Addr[18]       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 3.170      ;
+; 2.949 ; Addr[18]       ; Addr[19]       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 3.170      ;
 ; 2.957 ; Addr[16]       ; Addr[17]       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 3.178      ;
-; 2.957 ; Addr[8]        ; Addr[9]        ; C25M         ; C25M        ; 0.000        ; 0.000      ; 3.178      ;
-; 2.958 ; Addr[17]       ; Addr[18]       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 3.179      ;
-; 2.959 ; Addr[18]       ; Addr[19]       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 3.180      ;
-; 2.965 ; Addr[0]        ; Addr[1]        ; C25M         ; C25M        ; 0.000        ; 0.000      ; 3.186      ;
+; 2.958 ; Addr[9]        ; Addr[10]       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 3.179      ;
+; 2.958 ; Addr[10]       ; Addr[11]       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 3.179      ;
 ; 2.965 ; LS[7]          ; LS[8]          ; C25M         ; C25M        ; 0.000        ; 0.000      ; 3.186      ;
-; 2.983 ; LS[8]          ; LS[9]          ; C25M         ; C25M        ; 0.000        ; 0.000      ; 3.204      ;
-; 2.985 ; LS[9]          ; LS[10]         ; C25M         ; C25M        ; 0.000        ; 0.000      ; 3.206      ;
-; 2.992 ; LS[4]          ; LS[5]          ; C25M         ; C25M        ; 0.000        ; 0.000      ; 3.213      ;
-; 3.034 ; Addr[0]        ; DQMH~reg0      ; C25M         ; C25M        ; 0.000        ; 0.000      ; 3.255      ;
-; 3.060 ; Addr[10]       ; Addr[12]       ; C25M         ; C25M        ; 0.000        ; 0.000      ; 3.281      ;
-; 3.060 ; Addr[2]        ; Addr[4]        ; C25M         ; C25M        ; 0.000        ; 0.000      ; 3.281      ;
 +-------+----------------+----------------+--------------+-------------+--------------+------------+------------+
 
 
@@ -383,35 +384,35 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
 +--------+-----------+----------+--------------+-------------+--------------+------------+------------+
 ; Slack  ; From Node ; To Node  ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
 +--------+-----------+----------+--------------+-------------+--------------+------------+------------+
-; 33.300 ; nRESr     ; Addr[0]  ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.367      ;
-; 33.300 ; nRESr     ; REGEN    ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.367      ;
-; 33.300 ; nRESr     ; Addr[23] ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.367      ;
-; 33.300 ; nRESr     ; Addr[10] ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.367      ;
-; 33.300 ; nRESr     ; Addr[1]  ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.367      ;
-; 33.300 ; nRESr     ; Addr[11] ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.367      ;
-; 33.300 ; nRESr     ; Addr[2]  ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.367      ;
-; 33.300 ; nRESr     ; Addr[12] ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.367      ;
-; 33.300 ; nRESr     ; Bank     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.367      ;
-; 33.300 ; nRESr     ; Addr[3]  ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.367      ;
-; 33.300 ; nRESr     ; Addr[13] ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.367      ;
-; 33.300 ; nRESr     ; Addr[4]  ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.367      ;
-; 33.300 ; nRESr     ; Addr[14] ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.367      ;
-; 33.300 ; nRESr     ; Addr[5]  ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.367      ;
-; 33.300 ; nRESr     ; Addr[15] ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.367      ;
-; 33.300 ; nRESr     ; Addr[6]  ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.367      ;
-; 33.300 ; nRESr     ; Addr[16] ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.367      ;
-; 33.300 ; nRESr     ; Addr[7]  ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.367      ;
-; 33.300 ; nRESr     ; Addr[17] ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.367      ;
-; 33.300 ; nRESr     ; Addr[8]  ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.367      ;
-; 33.300 ; nRESr     ; Addr[18] ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.367      ;
-; 33.300 ; nRESr     ; Addr[9]  ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.367      ;
-; 33.300 ; nRESr     ; Addr[19] ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.367      ;
-; 33.300 ; nRESr     ; Addr[20] ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.367      ;
-; 33.300 ; nRESr     ; Addr[21] ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.367      ;
-; 33.300 ; nRESr     ; Addr[22] ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.367      ;
-; 33.300 ; nRESr     ; AddrIncH ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.367      ;
-; 33.300 ; nRESr     ; AddrIncM ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.367      ;
-; 33.300 ; nRESr     ; AddrIncL ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.367      ;
+; 33.331 ; nRESr     ; Addr[23] ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.336      ;
+; 33.331 ; nRESr     ; Addr[0]  ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.336      ;
+; 33.331 ; nRESr     ; REGEN    ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.336      ;
+; 33.331 ; nRESr     ; Addr[10] ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.336      ;
+; 33.331 ; nRESr     ; Addr[1]  ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.336      ;
+; 33.331 ; nRESr     ; Addr[11] ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.336      ;
+; 33.331 ; nRESr     ; Addr[2]  ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.336      ;
+; 33.331 ; nRESr     ; Addr[12] ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.336      ;
+; 33.331 ; nRESr     ; Bank     ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.336      ;
+; 33.331 ; nRESr     ; Addr[3]  ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.336      ;
+; 33.331 ; nRESr     ; Addr[13] ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.336      ;
+; 33.331 ; nRESr     ; Addr[4]  ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.336      ;
+; 33.331 ; nRESr     ; Addr[14] ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.336      ;
+; 33.331 ; nRESr     ; Addr[5]  ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.336      ;
+; 33.331 ; nRESr     ; Addr[15] ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.336      ;
+; 33.331 ; nRESr     ; Addr[6]  ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.336      ;
+; 33.331 ; nRESr     ; Addr[16] ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.336      ;
+; 33.331 ; nRESr     ; Addr[7]  ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.336      ;
+; 33.331 ; nRESr     ; Addr[17] ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.336      ;
+; 33.331 ; nRESr     ; Addr[8]  ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.336      ;
+; 33.331 ; nRESr     ; Addr[18] ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.336      ;
+; 33.331 ; nRESr     ; Addr[9]  ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.336      ;
+; 33.331 ; nRESr     ; Addr[19] ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.336      ;
+; 33.331 ; nRESr     ; Addr[20] ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.336      ;
+; 33.331 ; nRESr     ; Addr[21] ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.336      ;
+; 33.331 ; nRESr     ; Addr[22] ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.336      ;
+; 33.331 ; nRESr     ; AddrIncH ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.336      ;
+; 33.331 ; nRESr     ; AddrIncM ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.336      ;
+; 33.331 ; nRESr     ; AddrIncL ; C25M         ; C25M        ; 40.000       ; 0.000      ; 6.336      ;
 +--------+-----------+----------+--------------+-------------+--------------+------------+------------+
 
 
@@ -420,917 +421,44 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
 +-------+-----------+----------+--------------+-------------+--------------+------------+------------+
 ; Slack ; From Node ; To Node  ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
 +-------+-----------+----------+--------------+-------------+--------------+------------+------------+
-; 6.146 ; nRESr     ; Addr[0]  ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.367      ;
-; 6.146 ; nRESr     ; REGEN    ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.367      ;
-; 6.146 ; nRESr     ; Addr[23] ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.367      ;
-; 6.146 ; nRESr     ; Addr[10] ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.367      ;
-; 6.146 ; nRESr     ; Addr[1]  ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.367      ;
-; 6.146 ; nRESr     ; Addr[11] ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.367      ;
-; 6.146 ; nRESr     ; Addr[2]  ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.367      ;
-; 6.146 ; nRESr     ; Addr[12] ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.367      ;
-; 6.146 ; nRESr     ; Bank     ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.367      ;
-; 6.146 ; nRESr     ; Addr[3]  ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.367      ;
-; 6.146 ; nRESr     ; Addr[13] ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.367      ;
-; 6.146 ; nRESr     ; Addr[4]  ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.367      ;
-; 6.146 ; nRESr     ; Addr[14] ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.367      ;
-; 6.146 ; nRESr     ; Addr[5]  ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.367      ;
-; 6.146 ; nRESr     ; Addr[15] ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.367      ;
-; 6.146 ; nRESr     ; Addr[6]  ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.367      ;
-; 6.146 ; nRESr     ; Addr[16] ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.367      ;
-; 6.146 ; nRESr     ; Addr[7]  ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.367      ;
-; 6.146 ; nRESr     ; Addr[17] ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.367      ;
-; 6.146 ; nRESr     ; Addr[8]  ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.367      ;
-; 6.146 ; nRESr     ; Addr[18] ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.367      ;
-; 6.146 ; nRESr     ; Addr[9]  ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.367      ;
-; 6.146 ; nRESr     ; Addr[19] ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.367      ;
-; 6.146 ; nRESr     ; Addr[20] ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.367      ;
-; 6.146 ; nRESr     ; Addr[21] ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.367      ;
-; 6.146 ; nRESr     ; Addr[22] ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.367      ;
-; 6.146 ; nRESr     ; AddrIncH ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.367      ;
-; 6.146 ; nRESr     ; AddrIncM ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.367      ;
-; 6.146 ; nRESr     ; AddrIncL ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.367      ;
+; 6.115 ; nRESr     ; Addr[23] ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.336      ;
+; 6.115 ; nRESr     ; Addr[0]  ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.336      ;
+; 6.115 ; nRESr     ; REGEN    ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.336      ;
+; 6.115 ; nRESr     ; Addr[10] ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.336      ;
+; 6.115 ; nRESr     ; Addr[1]  ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.336      ;
+; 6.115 ; nRESr     ; Addr[11] ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.336      ;
+; 6.115 ; nRESr     ; Addr[2]  ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.336      ;
+; 6.115 ; nRESr     ; Addr[12] ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.336      ;
+; 6.115 ; nRESr     ; Bank     ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.336      ;
+; 6.115 ; nRESr     ; Addr[3]  ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.336      ;
+; 6.115 ; nRESr     ; Addr[13] ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.336      ;
+; 6.115 ; nRESr     ; Addr[4]  ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.336      ;
+; 6.115 ; nRESr     ; Addr[14] ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.336      ;
+; 6.115 ; nRESr     ; Addr[5]  ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.336      ;
+; 6.115 ; nRESr     ; Addr[15] ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.336      ;
+; 6.115 ; nRESr     ; Addr[6]  ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.336      ;
+; 6.115 ; nRESr     ; Addr[16] ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.336      ;
+; 6.115 ; nRESr     ; Addr[7]  ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.336      ;
+; 6.115 ; nRESr     ; Addr[17] ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.336      ;
+; 6.115 ; nRESr     ; Addr[8]  ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.336      ;
+; 6.115 ; nRESr     ; Addr[18] ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.336      ;
+; 6.115 ; nRESr     ; Addr[9]  ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.336      ;
+; 6.115 ; nRESr     ; Addr[19] ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.336      ;
+; 6.115 ; nRESr     ; Addr[20] ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.336      ;
+; 6.115 ; nRESr     ; Addr[21] ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.336      ;
+; 6.115 ; nRESr     ; Addr[22] ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.336      ;
+; 6.115 ; nRESr     ; AddrIncH ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.336      ;
+; 6.115 ; nRESr     ; AddrIncM ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.336      ;
+; 6.115 ; nRESr     ; AddrIncL ; C25M         ; C25M        ; 0.000        ; 0.000      ; 6.336      ;
 +-------+-----------+----------+--------------+-------------+--------------+------------+------------+
 
 
-+-------------------------------------------------------------------------------------------------+
-; Minimum Pulse Width: 'C25M'                                                                     ;
-+--------+--------------+----------------+------------------+-------+------------+----------------+
-; Slack  ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target         ;
-+--------+--------------+----------------+------------------+-------+------------+----------------+
-; 19.734 ; 20.000       ; 0.266          ; High Pulse Width ; C25M  ; Rise       ; AddrIncH       ;
-; 19.734 ; 20.000       ; 0.266          ; Low Pulse Width  ; C25M  ; Rise       ; AddrIncH       ;
-; 19.734 ; 20.000       ; 0.266          ; High Pulse Width ; C25M  ; Rise       ; AddrIncL       ;
-; 19.734 ; 20.000       ; 0.266          ; Low Pulse Width  ; C25M  ; Rise       ; AddrIncL       ;
-; 19.734 ; 20.000       ; 0.266          ; High Pulse Width ; C25M  ; Rise       ; AddrIncM       ;
-; 19.734 ; 20.000       ; 0.266          ; Low Pulse Width  ; C25M  ; Rise       ; AddrIncM       ;
-; 19.734 ; 20.000       ; 0.266          ; High Pulse Width ; C25M  ; Rise       ; Addr[0]        ;
-; 19.734 ; 20.000       ; 0.266          ; Low Pulse Width  ; C25M  ; Rise       ; Addr[0]        ;
-; 19.734 ; 20.000       ; 0.266          ; High Pulse Width ; C25M  ; Rise       ; Addr[10]       ;
-; 19.734 ; 20.000       ; 0.266          ; Low Pulse Width  ; C25M  ; Rise       ; Addr[10]       ;
-; 19.734 ; 20.000       ; 0.266          ; High Pulse Width ; C25M  ; Rise       ; Addr[11]       ;
-; 19.734 ; 20.000       ; 0.266          ; Low Pulse Width  ; C25M  ; Rise       ; Addr[11]       ;
-; 19.734 ; 20.000       ; 0.266          ; High Pulse Width ; C25M  ; Rise       ; Addr[12]       ;
-; 19.734 ; 20.000       ; 0.266          ; Low Pulse Width  ; C25M  ; Rise       ; Addr[12]       ;
-; 19.734 ; 20.000       ; 0.266          ; High Pulse Width ; C25M  ; Rise       ; Addr[13]       ;
-; 19.734 ; 20.000       ; 0.266          ; Low Pulse Width  ; C25M  ; Rise       ; Addr[13]       ;
-; 19.734 ; 20.000       ; 0.266          ; High Pulse Width ; C25M  ; Rise       ; Addr[14]       ;
-; 19.734 ; 20.000       ; 0.266          ; Low Pulse Width  ; C25M  ; Rise       ; Addr[14]       ;
-; 19.734 ; 20.000       ; 0.266          ; High Pulse Width ; C25M  ; Rise       ; Addr[15]       ;
-; 19.734 ; 20.000       ; 0.266          ; Low Pulse Width  ; C25M  ; Rise       ; Addr[15]       ;
-; 19.734 ; 20.000       ; 0.266          ; High Pulse Width ; C25M  ; Rise       ; Addr[16]       ;
-; 19.734 ; 20.000       ; 0.266          ; Low Pulse Width  ; C25M  ; Rise       ; Addr[16]       ;
-; 19.734 ; 20.000       ; 0.266          ; High Pulse Width ; C25M  ; Rise       ; Addr[17]       ;
-; 19.734 ; 20.000       ; 0.266          ; Low Pulse Width  ; C25M  ; Rise       ; Addr[17]       ;
-; 19.734 ; 20.000       ; 0.266          ; High Pulse Width ; C25M  ; Rise       ; Addr[18]       ;
-; 19.734 ; 20.000       ; 0.266          ; Low Pulse Width  ; C25M  ; Rise       ; Addr[18]       ;
-; 19.734 ; 20.000       ; 0.266          ; High Pulse Width ; C25M  ; Rise       ; Addr[19]       ;
-; 19.734 ; 20.000       ; 0.266          ; Low Pulse Width  ; C25M  ; Rise       ; Addr[19]       ;
-; 19.734 ; 20.000       ; 0.266          ; High Pulse Width ; C25M  ; Rise       ; Addr[1]        ;
-; 19.734 ; 20.000       ; 0.266          ; Low Pulse Width  ; C25M  ; Rise       ; Addr[1]        ;
-; 19.734 ; 20.000       ; 0.266          ; High Pulse Width ; C25M  ; Rise       ; Addr[20]       ;
-; 19.734 ; 20.000       ; 0.266          ; Low Pulse Width  ; C25M  ; Rise       ; Addr[20]       ;
-; 19.734 ; 20.000       ; 0.266          ; High Pulse Width ; C25M  ; Rise       ; Addr[21]       ;
-; 19.734 ; 20.000       ; 0.266          ; Low Pulse Width  ; C25M  ; Rise       ; Addr[21]       ;
-; 19.734 ; 20.000       ; 0.266          ; High Pulse Width ; C25M  ; Rise       ; Addr[22]       ;
-; 19.734 ; 20.000       ; 0.266          ; Low Pulse Width  ; C25M  ; Rise       ; Addr[22]       ;
-; 19.734 ; 20.000       ; 0.266          ; High Pulse Width ; C25M  ; Rise       ; Addr[23]       ;
-; 19.734 ; 20.000       ; 0.266          ; Low Pulse Width  ; C25M  ; Rise       ; Addr[23]       ;
-; 19.734 ; 20.000       ; 0.266          ; High Pulse Width ; C25M  ; Rise       ; Addr[2]        ;
-; 19.734 ; 20.000       ; 0.266          ; Low Pulse Width  ; C25M  ; Rise       ; Addr[2]        ;
-; 19.734 ; 20.000       ; 0.266          ; High Pulse Width ; C25M  ; Rise       ; Addr[3]        ;
-; 19.734 ; 20.000       ; 0.266          ; Low Pulse Width  ; C25M  ; Rise       ; Addr[3]        ;
-; 19.734 ; 20.000       ; 0.266          ; High Pulse Width ; C25M  ; Rise       ; Addr[4]        ;
-; 19.734 ; 20.000       ; 0.266          ; Low Pulse Width  ; C25M  ; Rise       ; Addr[4]        ;
-; 19.734 ; 20.000       ; 0.266          ; High Pulse Width ; C25M  ; Rise       ; Addr[5]        ;
-; 19.734 ; 20.000       ; 0.266          ; Low Pulse Width  ; C25M  ; Rise       ; Addr[5]        ;
-; 19.734 ; 20.000       ; 0.266          ; High Pulse Width ; C25M  ; Rise       ; Addr[6]        ;
-; 19.734 ; 20.000       ; 0.266          ; Low Pulse Width  ; C25M  ; Rise       ; Addr[6]        ;
-; 19.734 ; 20.000       ; 0.266          ; High Pulse Width ; C25M  ; Rise       ; Addr[7]        ;
-; 19.734 ; 20.000       ; 0.266          ; Low Pulse Width  ; C25M  ; Rise       ; Addr[7]        ;
-; 19.734 ; 20.000       ; 0.266          ; High Pulse Width ; C25M  ; Rise       ; Addr[8]        ;
-; 19.734 ; 20.000       ; 0.266          ; Low Pulse Width  ; C25M  ; Rise       ; Addr[8]        ;
-; 19.734 ; 20.000       ; 0.266          ; High Pulse Width ; C25M  ; Rise       ; Addr[9]        ;
-; 19.734 ; 20.000       ; 0.266          ; Low Pulse Width  ; C25M  ; Rise       ; Addr[9]        ;
-; 19.734 ; 20.000       ; 0.266          ; High Pulse Width ; C25M  ; Rise       ; Bank           ;
-; 19.734 ; 20.000       ; 0.266          ; Low Pulse Width  ; C25M  ; Rise       ; Bank           ;
-; 19.734 ; 20.000       ; 0.266          ; High Pulse Width ; C25M  ; Rise       ; DQMH~reg0      ;
-; 19.734 ; 20.000       ; 0.266          ; Low Pulse Width  ; C25M  ; Rise       ; DQMH~reg0      ;
-; 19.734 ; 20.000       ; 0.266          ; High Pulse Width ; C25M  ; Rise       ; DQML~reg0      ;
-; 19.734 ; 20.000       ; 0.266          ; Low Pulse Width  ; C25M  ; Rise       ; DQML~reg0      ;
-; 19.734 ; 20.000       ; 0.266          ; High Pulse Width ; C25M  ; Rise       ; FCKOE          ;
-; 19.734 ; 20.000       ; 0.266          ; Low Pulse Width  ; C25M  ; Rise       ; FCKOE          ;
-; 19.734 ; 20.000       ; 0.266          ; High Pulse Width ; C25M  ; Rise       ; FCKout         ;
-; 19.734 ; 20.000       ; 0.266          ; Low Pulse Width  ; C25M  ; Rise       ; FCKout         ;
-; 19.734 ; 20.000       ; 0.266          ; High Pulse Width ; C25M  ; Rise       ; FCS            ;
-; 19.734 ; 20.000       ; 0.266          ; Low Pulse Width  ; C25M  ; Rise       ; FCS            ;
-; 19.734 ; 20.000       ; 0.266          ; High Pulse Width ; C25M  ; Rise       ; IOROMEN        ;
-; 19.734 ; 20.000       ; 0.266          ; Low Pulse Width  ; C25M  ; Rise       ; IOROMEN        ;
-; 19.734 ; 20.000       ; 0.266          ; High Pulse Width ; C25M  ; Rise       ; IS.state_bit_0 ;
-; 19.734 ; 20.000       ; 0.266          ; Low Pulse Width  ; C25M  ; Rise       ; IS.state_bit_0 ;
-; 19.734 ; 20.000       ; 0.266          ; High Pulse Width ; C25M  ; Rise       ; IS.state_bit_1 ;
-; 19.734 ; 20.000       ; 0.266          ; Low Pulse Width  ; C25M  ; Rise       ; IS.state_bit_1 ;
-; 19.734 ; 20.000       ; 0.266          ; High Pulse Width ; C25M  ; Rise       ; IS.state_bit_2 ;
-; 19.734 ; 20.000       ; 0.266          ; Low Pulse Width  ; C25M  ; Rise       ; IS.state_bit_2 ;
-; 19.734 ; 20.000       ; 0.266          ; High Pulse Width ; C25M  ; Rise       ; LS[0]          ;
-; 19.734 ; 20.000       ; 0.266          ; Low Pulse Width  ; C25M  ; Rise       ; LS[0]          ;
-; 19.734 ; 20.000       ; 0.266          ; High Pulse Width ; C25M  ; Rise       ; LS[10]         ;
-; 19.734 ; 20.000       ; 0.266          ; Low Pulse Width  ; C25M  ; Rise       ; LS[10]         ;
-; 19.734 ; 20.000       ; 0.266          ; High Pulse Width ; C25M  ; Rise       ; LS[11]         ;
-; 19.734 ; 20.000       ; 0.266          ; Low Pulse Width  ; C25M  ; Rise       ; LS[11]         ;
-; 19.734 ; 20.000       ; 0.266          ; High Pulse Width ; C25M  ; Rise       ; LS[12]         ;
-; 19.734 ; 20.000       ; 0.266          ; Low Pulse Width  ; C25M  ; Rise       ; LS[12]         ;
-; 19.734 ; 20.000       ; 0.266          ; High Pulse Width ; C25M  ; Rise       ; LS[13]         ;
-; 19.734 ; 20.000       ; 0.266          ; Low Pulse Width  ; C25M  ; Rise       ; LS[13]         ;
-; 19.734 ; 20.000       ; 0.266          ; High Pulse Width ; C25M  ; Rise       ; LS[1]          ;
-; 19.734 ; 20.000       ; 0.266          ; Low Pulse Width  ; C25M  ; Rise       ; LS[1]          ;
-; 19.734 ; 20.000       ; 0.266          ; High Pulse Width ; C25M  ; Rise       ; LS[2]          ;
-; 19.734 ; 20.000       ; 0.266          ; Low Pulse Width  ; C25M  ; Rise       ; LS[2]          ;
-; 19.734 ; 20.000       ; 0.266          ; High Pulse Width ; C25M  ; Rise       ; LS[3]          ;
-; 19.734 ; 20.000       ; 0.266          ; Low Pulse Width  ; C25M  ; Rise       ; LS[3]          ;
-; 19.734 ; 20.000       ; 0.266          ; High Pulse Width ; C25M  ; Rise       ; LS[4]          ;
-; 19.734 ; 20.000       ; 0.266          ; Low Pulse Width  ; C25M  ; Rise       ; LS[4]          ;
-; 19.734 ; 20.000       ; 0.266          ; High Pulse Width ; C25M  ; Rise       ; LS[5]          ;
-; 19.734 ; 20.000       ; 0.266          ; Low Pulse Width  ; C25M  ; Rise       ; LS[5]          ;
-; 19.734 ; 20.000       ; 0.266          ; High Pulse Width ; C25M  ; Rise       ; LS[6]          ;
-; 19.734 ; 20.000       ; 0.266          ; Low Pulse Width  ; C25M  ; Rise       ; LS[6]          ;
-; 19.734 ; 20.000       ; 0.266          ; High Pulse Width ; C25M  ; Rise       ; LS[7]          ;
-; 19.734 ; 20.000       ; 0.266          ; Low Pulse Width  ; C25M  ; Rise       ; LS[7]          ;
-; 19.734 ; 20.000       ; 0.266          ; High Pulse Width ; C25M  ; Rise       ; LS[8]          ;
-; 19.734 ; 20.000       ; 0.266          ; Low Pulse Width  ; C25M  ; Rise       ; LS[8]          ;
-+--------+--------------+----------------+------------------+-------+------------+----------------+
-
-
-+------------------------------------------------------------------------------------------------+
-; Minimum Pulse Width: 'PHI0'                                                                    ;
-+---------+--------------+----------------+------------------+-------+------------+--------------+
-; Slack   ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target       ;
-+---------+--------------+----------------+------------------+-------+------------+--------------+
-; 488.734 ; 489.000      ; 0.266          ; High Pulse Width ; PHI0  ; Rise       ; CXXXr        ;
-; 488.734 ; 489.000      ; 0.266          ; Low Pulse Width  ; PHI0  ; Rise       ; CXXXr        ;
-; 488.734 ; 489.000      ; 0.266          ; High Pulse Width ; PHI0  ; Rise       ; RAr[0]       ;
-; 488.734 ; 489.000      ; 0.266          ; Low Pulse Width  ; PHI0  ; Rise       ; RAr[0]       ;
-; 488.734 ; 489.000      ; 0.266          ; High Pulse Width ; PHI0  ; Rise       ; RAr[10]      ;
-; 488.734 ; 489.000      ; 0.266          ; Low Pulse Width  ; PHI0  ; Rise       ; RAr[10]      ;
-; 488.734 ; 489.000      ; 0.266          ; High Pulse Width ; PHI0  ; Rise       ; RAr[11]      ;
-; 488.734 ; 489.000      ; 0.266          ; Low Pulse Width  ; PHI0  ; Rise       ; RAr[11]      ;
-; 488.734 ; 489.000      ; 0.266          ; High Pulse Width ; PHI0  ; Rise       ; RAr[1]       ;
-; 488.734 ; 489.000      ; 0.266          ; Low Pulse Width  ; PHI0  ; Rise       ; RAr[1]       ;
-; 488.734 ; 489.000      ; 0.266          ; High Pulse Width ; PHI0  ; Rise       ; RAr[2]       ;
-; 488.734 ; 489.000      ; 0.266          ; Low Pulse Width  ; PHI0  ; Rise       ; RAr[2]       ;
-; 488.734 ; 489.000      ; 0.266          ; High Pulse Width ; PHI0  ; Rise       ; RAr[3]       ;
-; 488.734 ; 489.000      ; 0.266          ; Low Pulse Width  ; PHI0  ; Rise       ; RAr[3]       ;
-; 488.734 ; 489.000      ; 0.266          ; High Pulse Width ; PHI0  ; Rise       ; RAr[4]       ;
-; 488.734 ; 489.000      ; 0.266          ; Low Pulse Width  ; PHI0  ; Rise       ; RAr[4]       ;
-; 488.734 ; 489.000      ; 0.266          ; High Pulse Width ; PHI0  ; Rise       ; RAr[5]       ;
-; 488.734 ; 489.000      ; 0.266          ; Low Pulse Width  ; PHI0  ; Rise       ; RAr[5]       ;
-; 488.734 ; 489.000      ; 0.266          ; High Pulse Width ; PHI0  ; Rise       ; RAr[6]       ;
-; 488.734 ; 489.000      ; 0.266          ; Low Pulse Width  ; PHI0  ; Rise       ; RAr[6]       ;
-; 488.734 ; 489.000      ; 0.266          ; High Pulse Width ; PHI0  ; Rise       ; RAr[7]       ;
-; 488.734 ; 489.000      ; 0.266          ; Low Pulse Width  ; PHI0  ; Rise       ; RAr[7]       ;
-; 488.734 ; 489.000      ; 0.266          ; High Pulse Width ; PHI0  ; Rise       ; RAr[8]       ;
-; 488.734 ; 489.000      ; 0.266          ; Low Pulse Width  ; PHI0  ; Rise       ; RAr[8]       ;
-; 488.734 ; 489.000      ; 0.266          ; High Pulse Width ; PHI0  ; Rise       ; RAr[9]       ;
-; 488.734 ; 489.000      ; 0.266          ; Low Pulse Width  ; PHI0  ; Rise       ; RAr[9]       ;
-; 488.734 ; 489.000      ; 0.266          ; High Pulse Width ; PHI0  ; Rise       ; nWEr         ;
-; 488.734 ; 489.000      ; 0.266          ; Low Pulse Width  ; PHI0  ; Rise       ; nWEr         ;
-; 489.000 ; 489.000      ; 0.000          ; High Pulse Width ; PHI0  ; Rise       ; CXXXr|clk    ;
-; 489.000 ; 489.000      ; 0.000          ; Low Pulse Width  ; PHI0  ; Rise       ; CXXXr|clk    ;
-; 489.000 ; 489.000      ; 0.000          ; High Pulse Width ; PHI0  ; Rise       ; PHI0|combout ;
-; 489.000 ; 489.000      ; 0.000          ; Low Pulse Width  ; PHI0  ; Rise       ; PHI0|combout ;
-; 489.000 ; 489.000      ; 0.000          ; High Pulse Width ; PHI0  ; Rise       ; RAr[0]|clk   ;
-; 489.000 ; 489.000      ; 0.000          ; Low Pulse Width  ; PHI0  ; Rise       ; RAr[0]|clk   ;
-; 489.000 ; 489.000      ; 0.000          ; High Pulse Width ; PHI0  ; Rise       ; RAr[10]|clk  ;
-; 489.000 ; 489.000      ; 0.000          ; Low Pulse Width  ; PHI0  ; Rise       ; RAr[10]|clk  ;
-; 489.000 ; 489.000      ; 0.000          ; High Pulse Width ; PHI0  ; Rise       ; RAr[11]|clk  ;
-; 489.000 ; 489.000      ; 0.000          ; Low Pulse Width  ; PHI0  ; Rise       ; RAr[11]|clk  ;
-; 489.000 ; 489.000      ; 0.000          ; High Pulse Width ; PHI0  ; Rise       ; RAr[1]|clk   ;
-; 489.000 ; 489.000      ; 0.000          ; Low Pulse Width  ; PHI0  ; Rise       ; RAr[1]|clk   ;
-; 489.000 ; 489.000      ; 0.000          ; High Pulse Width ; PHI0  ; Rise       ; RAr[2]|clk   ;
-; 489.000 ; 489.000      ; 0.000          ; Low Pulse Width  ; PHI0  ; Rise       ; RAr[2]|clk   ;
-; 489.000 ; 489.000      ; 0.000          ; High Pulse Width ; PHI0  ; Rise       ; RAr[3]|clk   ;
-; 489.000 ; 489.000      ; 0.000          ; Low Pulse Width  ; PHI0  ; Rise       ; RAr[3]|clk   ;
-; 489.000 ; 489.000      ; 0.000          ; High Pulse Width ; PHI0  ; Rise       ; RAr[4]|clk   ;
-; 489.000 ; 489.000      ; 0.000          ; Low Pulse Width  ; PHI0  ; Rise       ; RAr[4]|clk   ;
-; 489.000 ; 489.000      ; 0.000          ; High Pulse Width ; PHI0  ; Rise       ; RAr[5]|clk   ;
-; 489.000 ; 489.000      ; 0.000          ; Low Pulse Width  ; PHI0  ; Rise       ; RAr[5]|clk   ;
-; 489.000 ; 489.000      ; 0.000          ; High Pulse Width ; PHI0  ; Rise       ; RAr[6]|clk   ;
-; 489.000 ; 489.000      ; 0.000          ; Low Pulse Width  ; PHI0  ; Rise       ; RAr[6]|clk   ;
-; 489.000 ; 489.000      ; 0.000          ; High Pulse Width ; PHI0  ; Rise       ; RAr[7]|clk   ;
-; 489.000 ; 489.000      ; 0.000          ; Low Pulse Width  ; PHI0  ; Rise       ; RAr[7]|clk   ;
-; 489.000 ; 489.000      ; 0.000          ; High Pulse Width ; PHI0  ; Rise       ; RAr[8]|clk   ;
-; 489.000 ; 489.000      ; 0.000          ; Low Pulse Width  ; PHI0  ; Rise       ; RAr[8]|clk   ;
-; 489.000 ; 489.000      ; 0.000          ; High Pulse Width ; PHI0  ; Rise       ; RAr[9]|clk   ;
-; 489.000 ; 489.000      ; 0.000          ; Low Pulse Width  ; PHI0  ; Rise       ; RAr[9]|clk   ;
-; 489.000 ; 489.000      ; 0.000          ; High Pulse Width ; PHI0  ; Rise       ; nWEr|clk     ;
-; 489.000 ; 489.000      ; 0.000          ; Low Pulse Width  ; PHI0  ; Rise       ; nWEr|clk     ;
-; 974.000 ; 978.000      ; 4.000          ; Port Rate        ; PHI0  ; Rise       ; PHI0         ;
-+---------+--------------+----------------+------------------+-------+------------+--------------+
-
-
-+-------------------------------------------------------------------------+
-; Setup Times                                                             ;
-+-----------+------------+--------+--------+------------+-----------------+
-; Data Port ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
-+-----------+------------+--------+--------+------------+-----------------+
-; MISO      ; C25M       ; 4.863  ; 4.863  ; Rise       ; C25M            ;
-; MOSI      ; C25M       ; 3.316  ; 3.316  ; Rise       ; C25M            ;
-; RD[*]     ; C25M       ; 6.278  ; 6.278  ; Rise       ; C25M            ;
-;  RD[0]    ; C25M       ; 4.055  ; 4.055  ; Rise       ; C25M            ;
-;  RD[1]    ; C25M       ; 3.822  ; 3.822  ; Rise       ; C25M            ;
-;  RD[2]    ; C25M       ; 3.312  ; 3.312  ; Rise       ; C25M            ;
-;  RD[3]    ; C25M       ; 3.974  ; 3.974  ; Rise       ; C25M            ;
-;  RD[4]    ; C25M       ; 3.441  ; 3.441  ; Rise       ; C25M            ;
-;  RD[5]    ; C25M       ; 3.969  ; 3.969  ; Rise       ; C25M            ;
-;  RD[6]    ; C25M       ; 6.278  ; 6.278  ; Rise       ; C25M            ;
-;  RD[7]    ; C25M       ; 4.093  ; 4.093  ; Rise       ; C25M            ;
-; SetFW[*]  ; C25M       ; 4.149  ; 4.149  ; Rise       ; C25M            ;
-;  SetFW[0] ; C25M       ; 4.149  ; 4.149  ; Rise       ; C25M            ;
-;  SetFW[1] ; C25M       ; 3.738  ; 3.738  ; Rise       ; C25M            ;
-; nDEVSEL   ; C25M       ; 9.957  ; 9.957  ; Rise       ; C25M            ;
-; nIOSEL    ; C25M       ; 4.637  ; 4.637  ; Rise       ; C25M            ;
-; nIOSTRB   ; C25M       ; 5.052  ; 5.052  ; Rise       ; C25M            ;
-; nRES      ; C25M       ; 3.763  ; 3.763  ; Rise       ; C25M            ;
-; SD[*]     ; C25M       ; 5.269  ; 5.269  ; Fall       ; C25M            ;
-;  SD[0]    ; C25M       ; 4.676  ; 4.676  ; Fall       ; C25M            ;
-;  SD[1]    ; C25M       ; 4.064  ; 4.064  ; Fall       ; C25M            ;
-;  SD[2]    ; C25M       ; 3.916  ; 3.916  ; Fall       ; C25M            ;
-;  SD[3]    ; C25M       ; 5.158  ; 5.158  ; Fall       ; C25M            ;
-;  SD[4]    ; C25M       ; 3.719  ; 3.719  ; Fall       ; C25M            ;
-;  SD[5]    ; C25M       ; 3.149  ; 3.149  ; Fall       ; C25M            ;
-;  SD[6]    ; C25M       ; 3.295  ; 3.295  ; Fall       ; C25M            ;
-;  SD[7]    ; C25M       ; 5.269  ; 5.269  ; Fall       ; C25M            ;
-; RA[*]     ; PHI0       ; 0.892  ; 0.892  ; Rise       ; PHI0            ;
-;  RA[0]    ; PHI0       ; 0.414  ; 0.414  ; Rise       ; PHI0            ;
-;  RA[1]    ; PHI0       ; 0.713  ; 0.713  ; Rise       ; PHI0            ;
-;  RA[2]    ; PHI0       ; 0.008  ; 0.008  ; Rise       ; PHI0            ;
-;  RA[3]    ; PHI0       ; 0.464  ; 0.464  ; Rise       ; PHI0            ;
-;  RA[4]    ; PHI0       ; -0.520 ; -0.520 ; Rise       ; PHI0            ;
-;  RA[5]    ; PHI0       ; 0.727  ; 0.727  ; Rise       ; PHI0            ;
-;  RA[6]    ; PHI0       ; -0.603 ; -0.603 ; Rise       ; PHI0            ;
-;  RA[7]    ; PHI0       ; -0.772 ; -0.772 ; Rise       ; PHI0            ;
-;  RA[8]    ; PHI0       ; -1.522 ; -1.522 ; Rise       ; PHI0            ;
-;  RA[9]    ; PHI0       ; -1.478 ; -1.478 ; Rise       ; PHI0            ;
-;  RA[10]   ; PHI0       ; 0.892  ; 0.892  ; Rise       ; PHI0            ;
-;  RA[11]   ; PHI0       ; -0.105 ; -0.105 ; Rise       ; PHI0            ;
-;  RA[12]   ; PHI0       ; -0.073 ; -0.073 ; Rise       ; PHI0            ;
-;  RA[13]   ; PHI0       ; -0.133 ; -0.133 ; Rise       ; PHI0            ;
-;  RA[14]   ; PHI0       ; -0.434 ; -0.434 ; Rise       ; PHI0            ;
-;  RA[15]   ; PHI0       ; 0.054  ; 0.054  ; Rise       ; PHI0            ;
-; nWE       ; PHI0       ; 1.076  ; 1.076  ; Rise       ; PHI0            ;
-+-----------+------------+--------+--------+------------+-----------------+
-
-
-+-------------------------------------------------------------------------+
-; Hold Times                                                              ;
-+-----------+------------+--------+--------+------------+-----------------+
-; Data Port ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
-+-----------+------------+--------+--------+------------+-----------------+
-; MISO      ; C25M       ; -4.309 ; -4.309 ; Rise       ; C25M            ;
-; MOSI      ; C25M       ; -2.762 ; -2.762 ; Rise       ; C25M            ;
-; RD[*]     ; C25M       ; -1.878 ; -1.878 ; Rise       ; C25M            ;
-;  RD[0]    ; C25M       ; -2.106 ; -2.106 ; Rise       ; C25M            ;
-;  RD[1]    ; C25M       ; -2.899 ; -2.899 ; Rise       ; C25M            ;
-;  RD[2]    ; C25M       ; -1.911 ; -1.911 ; Rise       ; C25M            ;
-;  RD[3]    ; C25M       ; -2.031 ; -2.031 ; Rise       ; C25M            ;
-;  RD[4]    ; C25M       ; -2.065 ; -2.065 ; Rise       ; C25M            ;
-;  RD[5]    ; C25M       ; -1.878 ; -1.878 ; Rise       ; C25M            ;
-;  RD[6]    ; C25M       ; -2.052 ; -2.052 ; Rise       ; C25M            ;
-;  RD[7]    ; C25M       ; -1.899 ; -1.899 ; Rise       ; C25M            ;
-; SetFW[*]  ; C25M       ; -3.184 ; -3.184 ; Rise       ; C25M            ;
-;  SetFW[0] ; C25M       ; -3.595 ; -3.595 ; Rise       ; C25M            ;
-;  SetFW[1] ; C25M       ; -3.184 ; -3.184 ; Rise       ; C25M            ;
-; nDEVSEL   ; C25M       ; -4.698 ; -4.698 ; Rise       ; C25M            ;
-; nIOSEL    ; C25M       ; -4.076 ; -4.076 ; Rise       ; C25M            ;
-; nIOSTRB   ; C25M       ; -3.232 ; -3.232 ; Rise       ; C25M            ;
-; nRES      ; C25M       ; -3.209 ; -3.209 ; Rise       ; C25M            ;
-; SD[*]     ; C25M       ; -2.595 ; -2.595 ; Fall       ; C25M            ;
-;  SD[0]    ; C25M       ; -4.122 ; -4.122 ; Fall       ; C25M            ;
-;  SD[1]    ; C25M       ; -3.510 ; -3.510 ; Fall       ; C25M            ;
-;  SD[2]    ; C25M       ; -3.362 ; -3.362 ; Fall       ; C25M            ;
-;  SD[3]    ; C25M       ; -4.604 ; -4.604 ; Fall       ; C25M            ;
-;  SD[4]    ; C25M       ; -3.165 ; -3.165 ; Fall       ; C25M            ;
-;  SD[5]    ; C25M       ; -2.595 ; -2.595 ; Fall       ; C25M            ;
-;  SD[6]    ; C25M       ; -2.741 ; -2.741 ; Fall       ; C25M            ;
-;  SD[7]    ; C25M       ; -4.715 ; -4.715 ; Fall       ; C25M            ;
-; RA[*]     ; PHI0       ; 2.076  ; 2.076  ; Rise       ; PHI0            ;
-;  RA[0]    ; PHI0       ; 0.140  ; 0.140  ; Rise       ; PHI0            ;
-;  RA[1]    ; PHI0       ; -0.159 ; -0.159 ; Rise       ; PHI0            ;
-;  RA[2]    ; PHI0       ; 0.546  ; 0.546  ; Rise       ; PHI0            ;
-;  RA[3]    ; PHI0       ; 0.090  ; 0.090  ; Rise       ; PHI0            ;
-;  RA[4]    ; PHI0       ; 1.074  ; 1.074  ; Rise       ; PHI0            ;
-;  RA[5]    ; PHI0       ; -0.173 ; -0.173 ; Rise       ; PHI0            ;
-;  RA[6]    ; PHI0       ; 1.157  ; 1.157  ; Rise       ; PHI0            ;
-;  RA[7]    ; PHI0       ; 1.326  ; 1.326  ; Rise       ; PHI0            ;
-;  RA[8]    ; PHI0       ; 2.076  ; 2.076  ; Rise       ; PHI0            ;
-;  RA[9]    ; PHI0       ; 2.032  ; 2.032  ; Rise       ; PHI0            ;
-;  RA[10]   ; PHI0       ; -0.338 ; -0.338 ; Rise       ; PHI0            ;
-;  RA[11]   ; PHI0       ; 0.659  ; 0.659  ; Rise       ; PHI0            ;
-;  RA[12]   ; PHI0       ; 0.627  ; 0.627  ; Rise       ; PHI0            ;
-;  RA[13]   ; PHI0       ; 0.687  ; 0.687  ; Rise       ; PHI0            ;
-;  RA[14]   ; PHI0       ; 0.988  ; 0.988  ; Rise       ; PHI0            ;
-;  RA[15]   ; PHI0       ; 0.500  ; 0.500  ; Rise       ; PHI0            ;
-; nWE       ; PHI0       ; -0.522 ; -0.522 ; Rise       ; PHI0            ;
-+-----------+------------+--------+--------+------------+-----------------+
-
-
-+-------------------------------------------------------------------------+
-; Clock to Output Times                                                   ;
-+-----------+------------+--------+--------+------------+-----------------+
-; Data Port ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
-+-----------+------------+--------+--------+------------+-----------------+
-; DQMH      ; C25M       ; 17.381 ; 17.381 ; Rise       ; C25M            ;
-; DQML      ; C25M       ; 17.650 ; 17.650 ; Rise       ; C25M            ;
-; FCK       ; C25M       ; 17.362 ; 17.362 ; Rise       ; C25M            ;
-; MOSI      ; C25M       ; 17.251 ; 17.251 ; Rise       ; C25M            ;
-; RCKE      ; C25M       ; 17.169 ; 17.169 ; Rise       ; C25M            ;
-; RDdir     ; C25M       ; 23.995 ; 23.995 ; Rise       ; C25M            ;
-; SA[*]     ; C25M       ; 18.571 ; 18.571 ; Rise       ; C25M            ;
-;  SA[0]    ; C25M       ; 15.989 ; 15.989 ; Rise       ; C25M            ;
-;  SA[1]    ; C25M       ; 17.051 ; 17.051 ; Rise       ; C25M            ;
-;  SA[2]    ; C25M       ; 17.460 ; 17.460 ; Rise       ; C25M            ;
-;  SA[3]    ; C25M       ; 18.571 ; 18.571 ; Rise       ; C25M            ;
-;  SA[4]    ; C25M       ; 17.861 ; 17.861 ; Rise       ; C25M            ;
-;  SA[5]    ; C25M       ; 17.846 ; 17.846 ; Rise       ; C25M            ;
-;  SA[6]    ; C25M       ; 17.924 ; 17.924 ; Rise       ; C25M            ;
-;  SA[7]    ; C25M       ; 17.771 ; 17.771 ; Rise       ; C25M            ;
-;  SA[8]    ; C25M       ; 17.826 ; 17.826 ; Rise       ; C25M            ;
-;  SA[9]    ; C25M       ; 17.029 ; 17.029 ; Rise       ; C25M            ;
-;  SA[10]   ; C25M       ; 17.820 ; 17.820 ; Rise       ; C25M            ;
-;  SA[11]   ; C25M       ; 17.097 ; 17.097 ; Rise       ; C25M            ;
-;  SA[12]   ; C25M       ; 18.520 ; 18.520 ; Rise       ; C25M            ;
-; SBA[*]    ; C25M       ; 18.530 ; 18.530 ; Rise       ; C25M            ;
-;  SBA[0]   ; C25M       ; 17.892 ; 17.892 ; Rise       ; C25M            ;
-;  SBA[1]   ; C25M       ; 18.530 ; 18.530 ; Rise       ; C25M            ;
-; SD[*]     ; C25M       ; 17.061 ; 17.061 ; Rise       ; C25M            ;
-;  SD[0]    ; C25M       ; 17.061 ; 17.061 ; Rise       ; C25M            ;
-;  SD[1]    ; C25M       ; 15.918 ; 15.918 ; Rise       ; C25M            ;
-;  SD[2]    ; C25M       ; 16.402 ; 16.402 ; Rise       ; C25M            ;
-;  SD[3]    ; C25M       ; 16.297 ; 16.297 ; Rise       ; C25M            ;
-;  SD[4]    ; C25M       ; 15.834 ; 15.834 ; Rise       ; C25M            ;
-;  SD[5]    ; C25M       ; 16.821 ; 16.821 ; Rise       ; C25M            ;
-;  SD[6]    ; C25M       ; 16.477 ; 16.477 ; Rise       ; C25M            ;
-;  SD[7]    ; C25M       ; 16.328 ; 16.328 ; Rise       ; C25M            ;
-; nCAS      ; C25M       ; 17.133 ; 17.133 ; Rise       ; C25M            ;
-; nFCS      ; C25M       ; 17.510 ; 17.510 ; Rise       ; C25M            ;
-; nRAS      ; C25M       ; 15.968 ; 15.968 ; Rise       ; C25M            ;
-; nRCS      ; C25M       ; 17.139 ; 17.139 ; Rise       ; C25M            ;
-; nRESout   ; C25M       ; 17.067 ; 17.067 ; Rise       ; C25M            ;
-; nSWE      ; C25M       ; 17.830 ; 17.830 ; Rise       ; C25M            ;
-; RD[*]     ; C25M       ; 10.221 ; 10.221 ; Fall       ; C25M            ;
-;  RD[0]    ; C25M       ; 8.885  ; 8.885  ; Fall       ; C25M            ;
-;  RD[1]    ; C25M       ; 9.048  ; 9.048  ; Fall       ; C25M            ;
-;  RD[2]    ; C25M       ; 9.448  ; 9.448  ; Fall       ; C25M            ;
-;  RD[3]    ; C25M       ; 9.926  ; 9.926  ; Fall       ; C25M            ;
-;  RD[4]    ; C25M       ; 9.443  ; 9.443  ; Fall       ; C25M            ;
-;  RD[5]    ; C25M       ; 10.114 ; 10.114 ; Fall       ; C25M            ;
-;  RD[6]    ; C25M       ; 9.651  ; 9.651  ; Fall       ; C25M            ;
-;  RD[7]    ; C25M       ; 10.221 ; 10.221 ; Fall       ; C25M            ;
-; RDdir     ; PHI0       ; 21.935 ; 21.935 ; Rise       ; PHI0            ;
-; RDdir     ; PHI0       ; 21.935 ; 21.935 ; Fall       ; PHI0            ;
-+-----------+------------+--------+--------+------------+-----------------+
-
-
-+-------------------------------------------------------------------------+
-; Minimum Clock to Output Times                                           ;
-+-----------+------------+--------+--------+------------+-----------------+
-; Data Port ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
-+-----------+------------+--------+--------+------------+-----------------+
-; DQMH      ; C25M       ; 17.381 ; 17.381 ; Rise       ; C25M            ;
-; DQML      ; C25M       ; 17.650 ; 17.650 ; Rise       ; C25M            ;
-; FCK       ; C25M       ; 17.362 ; 17.362 ; Rise       ; C25M            ;
-; MOSI      ; C25M       ; 17.251 ; 17.251 ; Rise       ; C25M            ;
-; RCKE      ; C25M       ; 17.169 ; 17.169 ; Rise       ; C25M            ;
-; RDdir     ; C25M       ; 20.487 ; 20.487 ; Rise       ; C25M            ;
-; SA[*]     ; C25M       ; 15.989 ; 15.989 ; Rise       ; C25M            ;
-;  SA[0]    ; C25M       ; 15.989 ; 15.989 ; Rise       ; C25M            ;
-;  SA[1]    ; C25M       ; 17.051 ; 17.051 ; Rise       ; C25M            ;
-;  SA[2]    ; C25M       ; 17.460 ; 17.460 ; Rise       ; C25M            ;
-;  SA[3]    ; C25M       ; 18.571 ; 18.571 ; Rise       ; C25M            ;
-;  SA[4]    ; C25M       ; 17.861 ; 17.861 ; Rise       ; C25M            ;
-;  SA[5]    ; C25M       ; 17.846 ; 17.846 ; Rise       ; C25M            ;
-;  SA[6]    ; C25M       ; 17.924 ; 17.924 ; Rise       ; C25M            ;
-;  SA[7]    ; C25M       ; 17.771 ; 17.771 ; Rise       ; C25M            ;
-;  SA[8]    ; C25M       ; 17.826 ; 17.826 ; Rise       ; C25M            ;
-;  SA[9]    ; C25M       ; 17.029 ; 17.029 ; Rise       ; C25M            ;
-;  SA[10]   ; C25M       ; 17.820 ; 17.820 ; Rise       ; C25M            ;
-;  SA[11]   ; C25M       ; 17.097 ; 17.097 ; Rise       ; C25M            ;
-;  SA[12]   ; C25M       ; 18.520 ; 18.520 ; Rise       ; C25M            ;
-; SBA[*]    ; C25M       ; 17.892 ; 17.892 ; Rise       ; C25M            ;
-;  SBA[0]   ; C25M       ; 17.892 ; 17.892 ; Rise       ; C25M            ;
-;  SBA[1]   ; C25M       ; 18.530 ; 18.530 ; Rise       ; C25M            ;
-; SD[*]     ; C25M       ; 15.834 ; 15.834 ; Rise       ; C25M            ;
-;  SD[0]    ; C25M       ; 17.061 ; 17.061 ; Rise       ; C25M            ;
-;  SD[1]    ; C25M       ; 15.918 ; 15.918 ; Rise       ; C25M            ;
-;  SD[2]    ; C25M       ; 16.402 ; 16.402 ; Rise       ; C25M            ;
-;  SD[3]    ; C25M       ; 16.297 ; 16.297 ; Rise       ; C25M            ;
-;  SD[4]    ; C25M       ; 15.834 ; 15.834 ; Rise       ; C25M            ;
-;  SD[5]    ; C25M       ; 16.821 ; 16.821 ; Rise       ; C25M            ;
-;  SD[6]    ; C25M       ; 16.477 ; 16.477 ; Rise       ; C25M            ;
-;  SD[7]    ; C25M       ; 16.328 ; 16.328 ; Rise       ; C25M            ;
-; nCAS      ; C25M       ; 17.133 ; 17.133 ; Rise       ; C25M            ;
-; nFCS      ; C25M       ; 17.510 ; 17.510 ; Rise       ; C25M            ;
-; nRAS      ; C25M       ; 15.968 ; 15.968 ; Rise       ; C25M            ;
-; nRCS      ; C25M       ; 17.139 ; 17.139 ; Rise       ; C25M            ;
-; nRESout   ; C25M       ; 17.067 ; 17.067 ; Rise       ; C25M            ;
-; nSWE      ; C25M       ; 17.830 ; 17.830 ; Rise       ; C25M            ;
-; RD[*]     ; C25M       ; 8.885  ; 8.885  ; Fall       ; C25M            ;
-;  RD[0]    ; C25M       ; 8.885  ; 8.885  ; Fall       ; C25M            ;
-;  RD[1]    ; C25M       ; 9.048  ; 9.048  ; Fall       ; C25M            ;
-;  RD[2]    ; C25M       ; 9.448  ; 9.448  ; Fall       ; C25M            ;
-;  RD[3]    ; C25M       ; 9.926  ; 9.926  ; Fall       ; C25M            ;
-;  RD[4]    ; C25M       ; 9.443  ; 9.443  ; Fall       ; C25M            ;
-;  RD[5]    ; C25M       ; 10.114 ; 10.114 ; Fall       ; C25M            ;
-;  RD[6]    ; C25M       ; 9.651  ; 9.651  ; Fall       ; C25M            ;
-;  RD[7]    ; C25M       ; 10.221 ; 10.221 ; Fall       ; C25M            ;
-; RDdir     ; PHI0       ; 21.935 ; 21.935 ; Rise       ; PHI0            ;
-; RDdir     ; PHI0       ; 21.935 ; 21.935 ; Fall       ; PHI0            ;
-+-----------+------------+--------+--------+------------+-----------------+
-
-
-+------------------------------------------------------+
-; Propagation Delay                                    ;
-+------------+-------------+--------+----+----+--------+
-; Input Port ; Output Port ; RR     ; RF ; FR ; FF     ;
-+------------+-------------+--------+----+----+--------+
-; DMAin      ; DMAout      ; 8.665  ;    ;    ; 8.665  ;
-; INTin      ; INTout      ; 8.862  ;    ;    ; 8.862  ;
-; RA[0]      ; RD[0]       ; 13.610 ;    ;    ; 13.610 ;
-; RA[0]      ; RD[1]       ; 13.610 ;    ;    ; 13.610 ;
-; RA[0]      ; RD[2]       ; 13.610 ;    ;    ; 13.610 ;
-; RA[0]      ; RD[3]       ; 13.610 ;    ;    ; 13.610 ;
-; RA[0]      ; RD[4]       ; 13.610 ;    ;    ; 13.610 ;
-; RA[0]      ; RD[5]       ; 13.610 ;    ;    ; 13.610 ;
-; RA[0]      ; RD[6]       ; 13.565 ;    ;    ; 13.565 ;
-; RA[0]      ; RD[7]       ; 13.565 ;    ;    ; 13.565 ;
-; RA[0]      ; RDdir       ; 23.870 ;    ;    ; 23.870 ;
-; RA[1]      ; RD[0]       ; 12.760 ;    ;    ; 12.760 ;
-; RA[1]      ; RD[1]       ; 12.760 ;    ;    ; 12.760 ;
-; RA[1]      ; RD[2]       ; 12.760 ;    ;    ; 12.760 ;
-; RA[1]      ; RD[3]       ; 12.760 ;    ;    ; 12.760 ;
-; RA[1]      ; RD[4]       ; 12.760 ;    ;    ; 12.760 ;
-; RA[1]      ; RD[5]       ; 12.760 ;    ;    ; 12.760 ;
-; RA[1]      ; RD[6]       ; 12.715 ;    ;    ; 12.715 ;
-; RA[1]      ; RD[7]       ; 12.715 ;    ;    ; 12.715 ;
-; RA[1]      ; RDdir       ; 23.020 ;    ;    ; 23.020 ;
-; RA[2]      ; RD[0]       ; 13.252 ;    ;    ; 13.252 ;
-; RA[2]      ; RD[1]       ; 13.252 ;    ;    ; 13.252 ;
-; RA[2]      ; RD[2]       ; 13.252 ;    ;    ; 13.252 ;
-; RA[2]      ; RD[3]       ; 13.252 ;    ;    ; 13.252 ;
-; RA[2]      ; RD[4]       ; 13.252 ;    ;    ; 13.252 ;
-; RA[2]      ; RD[5]       ; 13.252 ;    ;    ; 13.252 ;
-; RA[2]      ; RD[6]       ; 13.207 ;    ;    ; 13.207 ;
-; RA[2]      ; RD[7]       ; 13.207 ;    ;    ; 13.207 ;
-; RA[2]      ; RDdir       ; 23.512 ;    ;    ; 23.512 ;
-; RA[3]      ; RD[0]       ; 13.532 ;    ;    ; 13.532 ;
-; RA[3]      ; RD[1]       ; 13.532 ;    ;    ; 13.532 ;
-; RA[3]      ; RD[2]       ; 13.532 ;    ;    ; 13.532 ;
-; RA[3]      ; RD[3]       ; 13.532 ;    ;    ; 13.532 ;
-; RA[3]      ; RD[4]       ; 13.532 ;    ;    ; 13.532 ;
-; RA[3]      ; RD[5]       ; 13.532 ;    ;    ; 13.532 ;
-; RA[3]      ; RD[6]       ; 13.487 ;    ;    ; 13.487 ;
-; RA[3]      ; RD[7]       ; 13.487 ;    ;    ; 13.487 ;
-; RA[3]      ; RDdir       ; 23.792 ;    ;    ; 23.792 ;
-; RA[4]      ; RD[0]       ; 13.442 ;    ;    ; 13.442 ;
-; RA[4]      ; RD[1]       ; 13.442 ;    ;    ; 13.442 ;
-; RA[4]      ; RD[2]       ; 13.442 ;    ;    ; 13.442 ;
-; RA[4]      ; RD[3]       ; 13.442 ;    ;    ; 13.442 ;
-; RA[4]      ; RD[4]       ; 13.442 ;    ;    ; 13.442 ;
-; RA[4]      ; RD[5]       ; 13.442 ;    ;    ; 13.442 ;
-; RA[4]      ; RD[6]       ; 13.397 ;    ;    ; 13.397 ;
-; RA[4]      ; RD[7]       ; 13.397 ;    ;    ; 13.397 ;
-; RA[4]      ; RDdir       ; 23.702 ;    ;    ; 23.702 ;
-; RA[5]      ; RD[0]       ; 13.393 ;    ;    ; 13.393 ;
-; RA[5]      ; RD[1]       ; 13.393 ;    ;    ; 13.393 ;
-; RA[5]      ; RD[2]       ; 13.393 ;    ;    ; 13.393 ;
-; RA[5]      ; RD[3]       ; 13.393 ;    ;    ; 13.393 ;
-; RA[5]      ; RD[4]       ; 13.393 ;    ;    ; 13.393 ;
-; RA[5]      ; RD[5]       ; 13.393 ;    ;    ; 13.393 ;
-; RA[5]      ; RD[6]       ; 13.348 ;    ;    ; 13.348 ;
-; RA[5]      ; RD[7]       ; 13.348 ;    ;    ; 13.348 ;
-; RA[5]      ; RDdir       ; 23.653 ;    ;    ; 23.653 ;
-; RA[6]      ; RD[0]       ; 13.690 ;    ;    ; 13.690 ;
-; RA[6]      ; RD[1]       ; 13.690 ;    ;    ; 13.690 ;
-; RA[6]      ; RD[2]       ; 13.690 ;    ;    ; 13.690 ;
-; RA[6]      ; RD[3]       ; 13.690 ;    ;    ; 13.690 ;
-; RA[6]      ; RD[4]       ; 13.690 ;    ;    ; 13.690 ;
-; RA[6]      ; RD[5]       ; 13.690 ;    ;    ; 13.690 ;
-; RA[6]      ; RD[6]       ; 13.645 ;    ;    ; 13.645 ;
-; RA[6]      ; RD[7]       ; 13.645 ;    ;    ; 13.645 ;
-; RA[6]      ; RDdir       ; 23.950 ;    ;    ; 23.950 ;
-; RA[7]      ; RD[0]       ; 12.122 ;    ;    ; 12.122 ;
-; RA[7]      ; RD[1]       ; 12.122 ;    ;    ; 12.122 ;
-; RA[7]      ; RD[2]       ; 12.122 ;    ;    ; 12.122 ;
-; RA[7]      ; RD[3]       ; 12.122 ;    ;    ; 12.122 ;
-; RA[7]      ; RD[4]       ; 12.122 ;    ;    ; 12.122 ;
-; RA[7]      ; RD[5]       ; 12.122 ;    ;    ; 12.122 ;
-; RA[7]      ; RD[6]       ; 12.077 ;    ;    ; 12.077 ;
-; RA[7]      ; RD[7]       ; 12.077 ;    ;    ; 12.077 ;
-; RA[7]      ; RDdir       ; 22.382 ;    ;    ; 22.382 ;
-; RA[8]      ; RD[0]       ; 11.505 ;    ;    ; 11.505 ;
-; RA[8]      ; RD[1]       ; 11.505 ;    ;    ; 11.505 ;
-; RA[8]      ; RD[2]       ; 11.505 ;    ;    ; 11.505 ;
-; RA[8]      ; RD[3]       ; 11.505 ;    ;    ; 11.505 ;
-; RA[8]      ; RD[4]       ; 11.505 ;    ;    ; 11.505 ;
-; RA[8]      ; RD[5]       ; 11.505 ;    ;    ; 11.505 ;
-; RA[8]      ; RD[6]       ; 11.460 ;    ;    ; 11.460 ;
-; RA[8]      ; RD[7]       ; 11.460 ;    ;    ; 11.460 ;
-; RA[8]      ; RDdir       ; 21.765 ;    ;    ; 21.765 ;
-; RA[9]      ; RD[0]       ; 11.899 ;    ;    ; 11.899 ;
-; RA[9]      ; RD[1]       ; 11.899 ;    ;    ; 11.899 ;
-; RA[9]      ; RD[2]       ; 11.899 ;    ;    ; 11.899 ;
-; RA[9]      ; RD[3]       ; 11.899 ;    ;    ; 11.899 ;
-; RA[9]      ; RD[4]       ; 11.899 ;    ;    ; 11.899 ;
-; RA[9]      ; RD[5]       ; 11.899 ;    ;    ; 11.899 ;
-; RA[9]      ; RD[6]       ; 11.854 ;    ;    ; 11.854 ;
-; RA[9]      ; RD[7]       ; 11.854 ;    ;    ; 11.854 ;
-; RA[9]      ; RDdir       ; 22.159 ;    ;    ; 22.159 ;
-; RA[10]     ; RD[0]       ; 13.038 ;    ;    ; 13.038 ;
-; RA[10]     ; RD[1]       ; 13.038 ;    ;    ; 13.038 ;
-; RA[10]     ; RD[2]       ; 13.038 ;    ;    ; 13.038 ;
-; RA[10]     ; RD[3]       ; 13.038 ;    ;    ; 13.038 ;
-; RA[10]     ; RD[4]       ; 13.038 ;    ;    ; 13.038 ;
-; RA[10]     ; RD[5]       ; 13.038 ;    ;    ; 13.038 ;
-; RA[10]     ; RD[6]       ; 12.993 ;    ;    ; 12.993 ;
-; RA[10]     ; RD[7]       ; 12.993 ;    ;    ; 12.993 ;
-; RA[10]     ; RDdir       ; 23.298 ;    ;    ; 23.298 ;
-; nDEVSEL    ; RD[0]       ; 11.136 ;    ;    ; 11.136 ;
-; nDEVSEL    ; RD[1]       ; 11.136 ;    ;    ; 11.136 ;
-; nDEVSEL    ; RD[2]       ; 11.136 ;    ;    ; 11.136 ;
-; nDEVSEL    ; RD[3]       ; 11.136 ;    ;    ; 11.136 ;
-; nDEVSEL    ; RD[4]       ; 11.136 ;    ;    ; 11.136 ;
-; nDEVSEL    ; RD[5]       ; 11.136 ;    ;    ; 11.136 ;
-; nDEVSEL    ; RD[6]       ; 11.091 ;    ;    ; 11.091 ;
-; nDEVSEL    ; RD[7]       ; 11.091 ;    ;    ; 11.091 ;
-; nDEVSEL    ; RDdir       ; 21.396 ;    ;    ; 21.396 ;
-; nIOSEL     ; RD[0]       ; 11.071 ;    ;    ; 11.071 ;
-; nIOSEL     ; RD[1]       ; 11.071 ;    ;    ; 11.071 ;
-; nIOSEL     ; RD[2]       ; 11.071 ;    ;    ; 11.071 ;
-; nIOSEL     ; RD[3]       ; 11.071 ;    ;    ; 11.071 ;
-; nIOSEL     ; RD[4]       ; 11.071 ;    ;    ; 11.071 ;
-; nIOSEL     ; RD[5]       ; 11.071 ;    ;    ; 11.071 ;
-; nIOSEL     ; RD[6]       ; 11.026 ;    ;    ; 11.026 ;
-; nIOSEL     ; RD[7]       ; 11.026 ;    ;    ; 11.026 ;
-; nIOSEL     ; RDdir       ; 21.331 ;    ;    ; 21.331 ;
-; nIOSTRB    ; RD[0]       ; 12.415 ;    ;    ; 12.415 ;
-; nIOSTRB    ; RD[1]       ; 12.415 ;    ;    ; 12.415 ;
-; nIOSTRB    ; RD[2]       ; 12.415 ;    ;    ; 12.415 ;
-; nIOSTRB    ; RD[3]       ; 12.415 ;    ;    ; 12.415 ;
-; nIOSTRB    ; RD[4]       ; 12.415 ;    ;    ; 12.415 ;
-; nIOSTRB    ; RD[5]       ; 12.415 ;    ;    ; 12.415 ;
-; nIOSTRB    ; RD[6]       ; 12.370 ;    ;    ; 12.370 ;
-; nIOSTRB    ; RD[7]       ; 12.370 ;    ;    ; 12.370 ;
-; nIOSTRB    ; RDdir       ; 22.675 ;    ;    ; 22.675 ;
-; nWE        ; RD[0]       ; 13.158 ;    ;    ; 13.158 ;
-; nWE        ; RD[1]       ; 13.158 ;    ;    ; 13.158 ;
-; nWE        ; RD[2]       ; 13.158 ;    ;    ; 13.158 ;
-; nWE        ; RD[3]       ; 13.158 ;    ;    ; 13.158 ;
-; nWE        ; RD[4]       ; 13.158 ;    ;    ; 13.158 ;
-; nWE        ; RD[5]       ; 13.158 ;    ;    ; 13.158 ;
-; nWE        ; RD[6]       ; 13.113 ;    ;    ; 13.113 ;
-; nWE        ; RD[7]       ; 13.113 ;    ;    ; 13.113 ;
-; nWE        ; RDdir       ; 23.418 ;    ;    ; 23.418 ;
-+------------+-------------+--------+----+----+--------+
-
-
-+------------------------------------------------------+
-; Minimum Propagation Delay                            ;
-+------------+-------------+--------+----+----+--------+
-; Input Port ; Output Port ; RR     ; RF ; FR ; FF     ;
-+------------+-------------+--------+----+----+--------+
-; DMAin      ; DMAout      ; 8.665  ;    ;    ; 8.665  ;
-; INTin      ; INTout      ; 8.862  ;    ;    ; 8.862  ;
-; RA[0]      ; RD[0]       ; 13.610 ;    ;    ; 13.610 ;
-; RA[0]      ; RD[1]       ; 13.610 ;    ;    ; 13.610 ;
-; RA[0]      ; RD[2]       ; 13.610 ;    ;    ; 13.610 ;
-; RA[0]      ; RD[3]       ; 13.610 ;    ;    ; 13.610 ;
-; RA[0]      ; RD[4]       ; 13.610 ;    ;    ; 13.610 ;
-; RA[0]      ; RD[5]       ; 13.610 ;    ;    ; 13.610 ;
-; RA[0]      ; RD[6]       ; 13.565 ;    ;    ; 13.565 ;
-; RA[0]      ; RD[7]       ; 13.565 ;    ;    ; 13.565 ;
-; RA[0]      ; RDdir       ; 23.870 ;    ;    ; 23.870 ;
-; RA[1]      ; RD[0]       ; 12.760 ;    ;    ; 12.760 ;
-; RA[1]      ; RD[1]       ; 12.760 ;    ;    ; 12.760 ;
-; RA[1]      ; RD[2]       ; 12.760 ;    ;    ; 12.760 ;
-; RA[1]      ; RD[3]       ; 12.760 ;    ;    ; 12.760 ;
-; RA[1]      ; RD[4]       ; 12.760 ;    ;    ; 12.760 ;
-; RA[1]      ; RD[5]       ; 12.760 ;    ;    ; 12.760 ;
-; RA[1]      ; RD[6]       ; 12.715 ;    ;    ; 12.715 ;
-; RA[1]      ; RD[7]       ; 12.715 ;    ;    ; 12.715 ;
-; RA[1]      ; RDdir       ; 23.020 ;    ;    ; 23.020 ;
-; RA[2]      ; RD[0]       ; 13.252 ;    ;    ; 13.252 ;
-; RA[2]      ; RD[1]       ; 13.252 ;    ;    ; 13.252 ;
-; RA[2]      ; RD[2]       ; 13.252 ;    ;    ; 13.252 ;
-; RA[2]      ; RD[3]       ; 13.252 ;    ;    ; 13.252 ;
-; RA[2]      ; RD[4]       ; 13.252 ;    ;    ; 13.252 ;
-; RA[2]      ; RD[5]       ; 13.252 ;    ;    ; 13.252 ;
-; RA[2]      ; RD[6]       ; 13.207 ;    ;    ; 13.207 ;
-; RA[2]      ; RD[7]       ; 13.207 ;    ;    ; 13.207 ;
-; RA[2]      ; RDdir       ; 23.512 ;    ;    ; 23.512 ;
-; RA[3]      ; RD[0]       ; 13.532 ;    ;    ; 13.532 ;
-; RA[3]      ; RD[1]       ; 13.532 ;    ;    ; 13.532 ;
-; RA[3]      ; RD[2]       ; 13.532 ;    ;    ; 13.532 ;
-; RA[3]      ; RD[3]       ; 13.532 ;    ;    ; 13.532 ;
-; RA[3]      ; RD[4]       ; 13.532 ;    ;    ; 13.532 ;
-; RA[3]      ; RD[5]       ; 13.532 ;    ;    ; 13.532 ;
-; RA[3]      ; RD[6]       ; 13.487 ;    ;    ; 13.487 ;
-; RA[3]      ; RD[7]       ; 13.487 ;    ;    ; 13.487 ;
-; RA[3]      ; RDdir       ; 23.792 ;    ;    ; 23.792 ;
-; RA[4]      ; RD[0]       ; 13.442 ;    ;    ; 13.442 ;
-; RA[4]      ; RD[1]       ; 13.442 ;    ;    ; 13.442 ;
-; RA[4]      ; RD[2]       ; 13.442 ;    ;    ; 13.442 ;
-; RA[4]      ; RD[3]       ; 13.442 ;    ;    ; 13.442 ;
-; RA[4]      ; RD[4]       ; 13.442 ;    ;    ; 13.442 ;
-; RA[4]      ; RD[5]       ; 13.442 ;    ;    ; 13.442 ;
-; RA[4]      ; RD[6]       ; 13.397 ;    ;    ; 13.397 ;
-; RA[4]      ; RD[7]       ; 13.397 ;    ;    ; 13.397 ;
-; RA[4]      ; RDdir       ; 23.702 ;    ;    ; 23.702 ;
-; RA[5]      ; RD[0]       ; 13.393 ;    ;    ; 13.393 ;
-; RA[5]      ; RD[1]       ; 13.393 ;    ;    ; 13.393 ;
-; RA[5]      ; RD[2]       ; 13.393 ;    ;    ; 13.393 ;
-; RA[5]      ; RD[3]       ; 13.393 ;    ;    ; 13.393 ;
-; RA[5]      ; RD[4]       ; 13.393 ;    ;    ; 13.393 ;
-; RA[5]      ; RD[5]       ; 13.393 ;    ;    ; 13.393 ;
-; RA[5]      ; RD[6]       ; 13.348 ;    ;    ; 13.348 ;
-; RA[5]      ; RD[7]       ; 13.348 ;    ;    ; 13.348 ;
-; RA[5]      ; RDdir       ; 23.653 ;    ;    ; 23.653 ;
-; RA[6]      ; RD[0]       ; 13.690 ;    ;    ; 13.690 ;
-; RA[6]      ; RD[1]       ; 13.690 ;    ;    ; 13.690 ;
-; RA[6]      ; RD[2]       ; 13.690 ;    ;    ; 13.690 ;
-; RA[6]      ; RD[3]       ; 13.690 ;    ;    ; 13.690 ;
-; RA[6]      ; RD[4]       ; 13.690 ;    ;    ; 13.690 ;
-; RA[6]      ; RD[5]       ; 13.690 ;    ;    ; 13.690 ;
-; RA[6]      ; RD[6]       ; 13.645 ;    ;    ; 13.645 ;
-; RA[6]      ; RD[7]       ; 13.645 ;    ;    ; 13.645 ;
-; RA[6]      ; RDdir       ; 23.950 ;    ;    ; 23.950 ;
-; RA[7]      ; RD[0]       ; 12.122 ;    ;    ; 12.122 ;
-; RA[7]      ; RD[1]       ; 12.122 ;    ;    ; 12.122 ;
-; RA[7]      ; RD[2]       ; 12.122 ;    ;    ; 12.122 ;
-; RA[7]      ; RD[3]       ; 12.122 ;    ;    ; 12.122 ;
-; RA[7]      ; RD[4]       ; 12.122 ;    ;    ; 12.122 ;
-; RA[7]      ; RD[5]       ; 12.122 ;    ;    ; 12.122 ;
-; RA[7]      ; RD[6]       ; 12.077 ;    ;    ; 12.077 ;
-; RA[7]      ; RD[7]       ; 12.077 ;    ;    ; 12.077 ;
-; RA[7]      ; RDdir       ; 22.382 ;    ;    ; 22.382 ;
-; RA[8]      ; RD[0]       ; 11.505 ;    ;    ; 11.505 ;
-; RA[8]      ; RD[1]       ; 11.505 ;    ;    ; 11.505 ;
-; RA[8]      ; RD[2]       ; 11.505 ;    ;    ; 11.505 ;
-; RA[8]      ; RD[3]       ; 11.505 ;    ;    ; 11.505 ;
-; RA[8]      ; RD[4]       ; 11.505 ;    ;    ; 11.505 ;
-; RA[8]      ; RD[5]       ; 11.505 ;    ;    ; 11.505 ;
-; RA[8]      ; RD[6]       ; 11.460 ;    ;    ; 11.460 ;
-; RA[8]      ; RD[7]       ; 11.460 ;    ;    ; 11.460 ;
-; RA[8]      ; RDdir       ; 21.765 ;    ;    ; 21.765 ;
-; RA[9]      ; RD[0]       ; 11.899 ;    ;    ; 11.899 ;
-; RA[9]      ; RD[1]       ; 11.899 ;    ;    ; 11.899 ;
-; RA[9]      ; RD[2]       ; 11.899 ;    ;    ; 11.899 ;
-; RA[9]      ; RD[3]       ; 11.899 ;    ;    ; 11.899 ;
-; RA[9]      ; RD[4]       ; 11.899 ;    ;    ; 11.899 ;
-; RA[9]      ; RD[5]       ; 11.899 ;    ;    ; 11.899 ;
-; RA[9]      ; RD[6]       ; 11.854 ;    ;    ; 11.854 ;
-; RA[9]      ; RD[7]       ; 11.854 ;    ;    ; 11.854 ;
-; RA[9]      ; RDdir       ; 22.159 ;    ;    ; 22.159 ;
-; RA[10]     ; RD[0]       ; 13.038 ;    ;    ; 13.038 ;
-; RA[10]     ; RD[1]       ; 13.038 ;    ;    ; 13.038 ;
-; RA[10]     ; RD[2]       ; 13.038 ;    ;    ; 13.038 ;
-; RA[10]     ; RD[3]       ; 13.038 ;    ;    ; 13.038 ;
-; RA[10]     ; RD[4]       ; 13.038 ;    ;    ; 13.038 ;
-; RA[10]     ; RD[5]       ; 13.038 ;    ;    ; 13.038 ;
-; RA[10]     ; RD[6]       ; 12.993 ;    ;    ; 12.993 ;
-; RA[10]     ; RD[7]       ; 12.993 ;    ;    ; 12.993 ;
-; RA[10]     ; RDdir       ; 23.298 ;    ;    ; 23.298 ;
-; nDEVSEL    ; RD[0]       ; 11.136 ;    ;    ; 11.136 ;
-; nDEVSEL    ; RD[1]       ; 11.136 ;    ;    ; 11.136 ;
-; nDEVSEL    ; RD[2]       ; 11.136 ;    ;    ; 11.136 ;
-; nDEVSEL    ; RD[3]       ; 11.136 ;    ;    ; 11.136 ;
-; nDEVSEL    ; RD[4]       ; 11.136 ;    ;    ; 11.136 ;
-; nDEVSEL    ; RD[5]       ; 11.136 ;    ;    ; 11.136 ;
-; nDEVSEL    ; RD[6]       ; 11.091 ;    ;    ; 11.091 ;
-; nDEVSEL    ; RD[7]       ; 11.091 ;    ;    ; 11.091 ;
-; nDEVSEL    ; RDdir       ; 21.396 ;    ;    ; 21.396 ;
-; nIOSEL     ; RD[0]       ; 11.071 ;    ;    ; 11.071 ;
-; nIOSEL     ; RD[1]       ; 11.071 ;    ;    ; 11.071 ;
-; nIOSEL     ; RD[2]       ; 11.071 ;    ;    ; 11.071 ;
-; nIOSEL     ; RD[3]       ; 11.071 ;    ;    ; 11.071 ;
-; nIOSEL     ; RD[4]       ; 11.071 ;    ;    ; 11.071 ;
-; nIOSEL     ; RD[5]       ; 11.071 ;    ;    ; 11.071 ;
-; nIOSEL     ; RD[6]       ; 11.026 ;    ;    ; 11.026 ;
-; nIOSEL     ; RD[7]       ; 11.026 ;    ;    ; 11.026 ;
-; nIOSEL     ; RDdir       ; 21.331 ;    ;    ; 21.331 ;
-; nIOSTRB    ; RD[0]       ; 12.415 ;    ;    ; 12.415 ;
-; nIOSTRB    ; RD[1]       ; 12.415 ;    ;    ; 12.415 ;
-; nIOSTRB    ; RD[2]       ; 12.415 ;    ;    ; 12.415 ;
-; nIOSTRB    ; RD[3]       ; 12.415 ;    ;    ; 12.415 ;
-; nIOSTRB    ; RD[4]       ; 12.415 ;    ;    ; 12.415 ;
-; nIOSTRB    ; RD[5]       ; 12.415 ;    ;    ; 12.415 ;
-; nIOSTRB    ; RD[6]       ; 12.370 ;    ;    ; 12.370 ;
-; nIOSTRB    ; RD[7]       ; 12.370 ;    ;    ; 12.370 ;
-; nIOSTRB    ; RDdir       ; 22.675 ;    ;    ; 22.675 ;
-; nWE        ; RD[0]       ; 13.158 ;    ;    ; 13.158 ;
-; nWE        ; RD[1]       ; 13.158 ;    ;    ; 13.158 ;
-; nWE        ; RD[2]       ; 13.158 ;    ;    ; 13.158 ;
-; nWE        ; RD[3]       ; 13.158 ;    ;    ; 13.158 ;
-; nWE        ; RD[4]       ; 13.158 ;    ;    ; 13.158 ;
-; nWE        ; RD[5]       ; 13.158 ;    ;    ; 13.158 ;
-; nWE        ; RD[6]       ; 13.113 ;    ;    ; 13.113 ;
-; nWE        ; RD[7]       ; 13.113 ;    ;    ; 13.113 ;
-; nWE        ; RDdir       ; 23.418 ;    ;    ; 23.418 ;
-+------------+-------------+--------+----+----+--------+
-
-
-+-----------------------------------------------------------------------+
-; Output Enable Times                                                   ;
-+-----------+------------+--------+------+------------+-----------------+
-; Data Port ; Clock Port ; Rise   ; Fall ; Clock Edge ; Clock Reference ;
-+-----------+------------+--------+------+------------+-----------------+
-; FCK       ; C25M       ; 15.951 ;      ; Rise       ; C25M            ;
-; MOSI      ; C25M       ; 15.242 ;      ; Rise       ; C25M            ;
-; RD[*]     ; C25M       ; 13.690 ;      ; Rise       ; C25M            ;
-;  RD[0]    ; C25M       ; 13.735 ;      ; Rise       ; C25M            ;
-;  RD[1]    ; C25M       ; 13.735 ;      ; Rise       ; C25M            ;
-;  RD[2]    ; C25M       ; 13.735 ;      ; Rise       ; C25M            ;
-;  RD[3]    ; C25M       ; 13.735 ;      ; Rise       ; C25M            ;
-;  RD[4]    ; C25M       ; 13.735 ;      ; Rise       ; C25M            ;
-;  RD[5]    ; C25M       ; 13.735 ;      ; Rise       ; C25M            ;
-;  RD[6]    ; C25M       ; 13.690 ;      ; Rise       ; C25M            ;
-;  RD[7]    ; C25M       ; 13.690 ;      ; Rise       ; C25M            ;
-; SD[*]     ; C25M       ; 13.373 ;      ; Rise       ; C25M            ;
-;  SD[0]    ; C25M       ; 13.829 ;      ; Rise       ; C25M            ;
-;  SD[1]    ; C25M       ; 13.829 ;      ; Rise       ; C25M            ;
-;  SD[2]    ; C25M       ; 13.373 ;      ; Rise       ; C25M            ;
-;  SD[3]    ; C25M       ; 13.373 ;      ; Rise       ; C25M            ;
-;  SD[4]    ; C25M       ; 13.829 ;      ; Rise       ; C25M            ;
-;  SD[5]    ; C25M       ; 13.373 ;      ; Rise       ; C25M            ;
-;  SD[6]    ; C25M       ; 13.373 ;      ; Rise       ; C25M            ;
-;  SD[7]    ; C25M       ; 13.373 ;      ; Rise       ; C25M            ;
-; nFCS      ; C25M       ; 15.969 ;      ; Rise       ; C25M            ;
-; RD[*]     ; PHI0       ; 11.630 ;      ; Rise       ; PHI0            ;
-;  RD[0]    ; PHI0       ; 11.675 ;      ; Rise       ; PHI0            ;
-;  RD[1]    ; PHI0       ; 11.675 ;      ; Rise       ; PHI0            ;
-;  RD[2]    ; PHI0       ; 11.675 ;      ; Rise       ; PHI0            ;
-;  RD[3]    ; PHI0       ; 11.675 ;      ; Rise       ; PHI0            ;
-;  RD[4]    ; PHI0       ; 11.675 ;      ; Rise       ; PHI0            ;
-;  RD[5]    ; PHI0       ; 11.675 ;      ; Rise       ; PHI0            ;
-;  RD[6]    ; PHI0       ; 11.630 ;      ; Rise       ; PHI0            ;
-;  RD[7]    ; PHI0       ; 11.630 ;      ; Rise       ; PHI0            ;
-; RD[*]     ; PHI0       ; 11.630 ;      ; Fall       ; PHI0            ;
-;  RD[0]    ; PHI0       ; 11.675 ;      ; Fall       ; PHI0            ;
-;  RD[1]    ; PHI0       ; 11.675 ;      ; Fall       ; PHI0            ;
-;  RD[2]    ; PHI0       ; 11.675 ;      ; Fall       ; PHI0            ;
-;  RD[3]    ; PHI0       ; 11.675 ;      ; Fall       ; PHI0            ;
-;  RD[4]    ; PHI0       ; 11.675 ;      ; Fall       ; PHI0            ;
-;  RD[5]    ; PHI0       ; 11.675 ;      ; Fall       ; PHI0            ;
-;  RD[6]    ; PHI0       ; 11.630 ;      ; Fall       ; PHI0            ;
-;  RD[7]    ; PHI0       ; 11.630 ;      ; Fall       ; PHI0            ;
-+-----------+------------+--------+------+------------+-----------------+
-
-
-+-----------------------------------------------------------------------+
-; Minimum Output Enable Times                                           ;
-+-----------+------------+--------+------+------------+-----------------+
-; Data Port ; Clock Port ; Rise   ; Fall ; Clock Edge ; Clock Reference ;
-+-----------+------------+--------+------+------------+-----------------+
-; FCK       ; C25M       ; 15.951 ;      ; Rise       ; C25M            ;
-; MOSI      ; C25M       ; 15.242 ;      ; Rise       ; C25M            ;
-; RD[*]     ; C25M       ; 10.182 ;      ; Rise       ; C25M            ;
-;  RD[0]    ; C25M       ; 10.227 ;      ; Rise       ; C25M            ;
-;  RD[1]    ; C25M       ; 10.227 ;      ; Rise       ; C25M            ;
-;  RD[2]    ; C25M       ; 10.227 ;      ; Rise       ; C25M            ;
-;  RD[3]    ; C25M       ; 10.227 ;      ; Rise       ; C25M            ;
-;  RD[4]    ; C25M       ; 10.227 ;      ; Rise       ; C25M            ;
-;  RD[5]    ; C25M       ; 10.227 ;      ; Rise       ; C25M            ;
-;  RD[6]    ; C25M       ; 10.182 ;      ; Rise       ; C25M            ;
-;  RD[7]    ; C25M       ; 10.182 ;      ; Rise       ; C25M            ;
-; SD[*]     ; C25M       ; 13.373 ;      ; Rise       ; C25M            ;
-;  SD[0]    ; C25M       ; 13.829 ;      ; Rise       ; C25M            ;
-;  SD[1]    ; C25M       ; 13.829 ;      ; Rise       ; C25M            ;
-;  SD[2]    ; C25M       ; 13.373 ;      ; Rise       ; C25M            ;
-;  SD[3]    ; C25M       ; 13.373 ;      ; Rise       ; C25M            ;
-;  SD[4]    ; C25M       ; 13.829 ;      ; Rise       ; C25M            ;
-;  SD[5]    ; C25M       ; 13.373 ;      ; Rise       ; C25M            ;
-;  SD[6]    ; C25M       ; 13.373 ;      ; Rise       ; C25M            ;
-;  SD[7]    ; C25M       ; 13.373 ;      ; Rise       ; C25M            ;
-; nFCS      ; C25M       ; 15.969 ;      ; Rise       ; C25M            ;
-; RD[*]     ; PHI0       ; 11.630 ;      ; Rise       ; PHI0            ;
-;  RD[0]    ; PHI0       ; 11.675 ;      ; Rise       ; PHI0            ;
-;  RD[1]    ; PHI0       ; 11.675 ;      ; Rise       ; PHI0            ;
-;  RD[2]    ; PHI0       ; 11.675 ;      ; Rise       ; PHI0            ;
-;  RD[3]    ; PHI0       ; 11.675 ;      ; Rise       ; PHI0            ;
-;  RD[4]    ; PHI0       ; 11.675 ;      ; Rise       ; PHI0            ;
-;  RD[5]    ; PHI0       ; 11.675 ;      ; Rise       ; PHI0            ;
-;  RD[6]    ; PHI0       ; 11.630 ;      ; Rise       ; PHI0            ;
-;  RD[7]    ; PHI0       ; 11.630 ;      ; Rise       ; PHI0            ;
-; RD[*]     ; PHI0       ; 11.630 ;      ; Fall       ; PHI0            ;
-;  RD[0]    ; PHI0       ; 11.675 ;      ; Fall       ; PHI0            ;
-;  RD[1]    ; PHI0       ; 11.675 ;      ; Fall       ; PHI0            ;
-;  RD[2]    ; PHI0       ; 11.675 ;      ; Fall       ; PHI0            ;
-;  RD[3]    ; PHI0       ; 11.675 ;      ; Fall       ; PHI0            ;
-;  RD[4]    ; PHI0       ; 11.675 ;      ; Fall       ; PHI0            ;
-;  RD[5]    ; PHI0       ; 11.675 ;      ; Fall       ; PHI0            ;
-;  RD[6]    ; PHI0       ; 11.630 ;      ; Fall       ; PHI0            ;
-;  RD[7]    ; PHI0       ; 11.630 ;      ; Fall       ; PHI0            ;
-+-----------+------------+--------+------+------------+-----------------+
-
-
-+-------------------------------------------------------------------------------+
-; Output Disable Times                                                          ;
-+-----------+------------+-----------+-----------+------------+-----------------+
-; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ;
-+-----------+------------+-----------+-----------+------------+-----------------+
-; FCK       ; C25M       ; 15.951    ;           ; Rise       ; C25M            ;
-; MOSI      ; C25M       ; 15.242    ;           ; Rise       ; C25M            ;
-; RD[*]     ; C25M       ; 13.690    ;           ; Rise       ; C25M            ;
-;  RD[0]    ; C25M       ; 13.735    ;           ; Rise       ; C25M            ;
-;  RD[1]    ; C25M       ; 13.735    ;           ; Rise       ; C25M            ;
-;  RD[2]    ; C25M       ; 13.735    ;           ; Rise       ; C25M            ;
-;  RD[3]    ; C25M       ; 13.735    ;           ; Rise       ; C25M            ;
-;  RD[4]    ; C25M       ; 13.735    ;           ; Rise       ; C25M            ;
-;  RD[5]    ; C25M       ; 13.735    ;           ; Rise       ; C25M            ;
-;  RD[6]    ; C25M       ; 13.690    ;           ; Rise       ; C25M            ;
-;  RD[7]    ; C25M       ; 13.690    ;           ; Rise       ; C25M            ;
-; SD[*]     ; C25M       ; 13.373    ;           ; Rise       ; C25M            ;
-;  SD[0]    ; C25M       ; 13.829    ;           ; Rise       ; C25M            ;
-;  SD[1]    ; C25M       ; 13.829    ;           ; Rise       ; C25M            ;
-;  SD[2]    ; C25M       ; 13.373    ;           ; Rise       ; C25M            ;
-;  SD[3]    ; C25M       ; 13.373    ;           ; Rise       ; C25M            ;
-;  SD[4]    ; C25M       ; 13.829    ;           ; Rise       ; C25M            ;
-;  SD[5]    ; C25M       ; 13.373    ;           ; Rise       ; C25M            ;
-;  SD[6]    ; C25M       ; 13.373    ;           ; Rise       ; C25M            ;
-;  SD[7]    ; C25M       ; 13.373    ;           ; Rise       ; C25M            ;
-; nFCS      ; C25M       ; 15.969    ;           ; Rise       ; C25M            ;
-; RD[*]     ; PHI0       ; 11.630    ;           ; Rise       ; PHI0            ;
-;  RD[0]    ; PHI0       ; 11.675    ;           ; Rise       ; PHI0            ;
-;  RD[1]    ; PHI0       ; 11.675    ;           ; Rise       ; PHI0            ;
-;  RD[2]    ; PHI0       ; 11.675    ;           ; Rise       ; PHI0            ;
-;  RD[3]    ; PHI0       ; 11.675    ;           ; Rise       ; PHI0            ;
-;  RD[4]    ; PHI0       ; 11.675    ;           ; Rise       ; PHI0            ;
-;  RD[5]    ; PHI0       ; 11.675    ;           ; Rise       ; PHI0            ;
-;  RD[6]    ; PHI0       ; 11.630    ;           ; Rise       ; PHI0            ;
-;  RD[7]    ; PHI0       ; 11.630    ;           ; Rise       ; PHI0            ;
-; RD[*]     ; PHI0       ; 11.630    ;           ; Fall       ; PHI0            ;
-;  RD[0]    ; PHI0       ; 11.675    ;           ; Fall       ; PHI0            ;
-;  RD[1]    ; PHI0       ; 11.675    ;           ; Fall       ; PHI0            ;
-;  RD[2]    ; PHI0       ; 11.675    ;           ; Fall       ; PHI0            ;
-;  RD[3]    ; PHI0       ; 11.675    ;           ; Fall       ; PHI0            ;
-;  RD[4]    ; PHI0       ; 11.675    ;           ; Fall       ; PHI0            ;
-;  RD[5]    ; PHI0       ; 11.675    ;           ; Fall       ; PHI0            ;
-;  RD[6]    ; PHI0       ; 11.630    ;           ; Fall       ; PHI0            ;
-;  RD[7]    ; PHI0       ; 11.630    ;           ; Fall       ; PHI0            ;
-+-----------+------------+-----------+-----------+------------+-----------------+
-
-
-+-------------------------------------------------------------------------------+
-; Minimum Output Disable Times                                                  ;
-+-----------+------------+-----------+-----------+------------+-----------------+
-; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ;
-+-----------+------------+-----------+-----------+------------+-----------------+
-; FCK       ; C25M       ; 15.951    ;           ; Rise       ; C25M            ;
-; MOSI      ; C25M       ; 15.242    ;           ; Rise       ; C25M            ;
-; RD[*]     ; C25M       ; 10.182    ;           ; Rise       ; C25M            ;
-;  RD[0]    ; C25M       ; 10.227    ;           ; Rise       ; C25M            ;
-;  RD[1]    ; C25M       ; 10.227    ;           ; Rise       ; C25M            ;
-;  RD[2]    ; C25M       ; 10.227    ;           ; Rise       ; C25M            ;
-;  RD[3]    ; C25M       ; 10.227    ;           ; Rise       ; C25M            ;
-;  RD[4]    ; C25M       ; 10.227    ;           ; Rise       ; C25M            ;
-;  RD[5]    ; C25M       ; 10.227    ;           ; Rise       ; C25M            ;
-;  RD[6]    ; C25M       ; 10.182    ;           ; Rise       ; C25M            ;
-;  RD[7]    ; C25M       ; 10.182    ;           ; Rise       ; C25M            ;
-; SD[*]     ; C25M       ; 13.373    ;           ; Rise       ; C25M            ;
-;  SD[0]    ; C25M       ; 13.829    ;           ; Rise       ; C25M            ;
-;  SD[1]    ; C25M       ; 13.829    ;           ; Rise       ; C25M            ;
-;  SD[2]    ; C25M       ; 13.373    ;           ; Rise       ; C25M            ;
-;  SD[3]    ; C25M       ; 13.373    ;           ; Rise       ; C25M            ;
-;  SD[4]    ; C25M       ; 13.829    ;           ; Rise       ; C25M            ;
-;  SD[5]    ; C25M       ; 13.373    ;           ; Rise       ; C25M            ;
-;  SD[6]    ; C25M       ; 13.373    ;           ; Rise       ; C25M            ;
-;  SD[7]    ; C25M       ; 13.373    ;           ; Rise       ; C25M            ;
-; nFCS      ; C25M       ; 15.969    ;           ; Rise       ; C25M            ;
-; RD[*]     ; PHI0       ; 11.630    ;           ; Rise       ; PHI0            ;
-;  RD[0]    ; PHI0       ; 11.675    ;           ; Rise       ; PHI0            ;
-;  RD[1]    ; PHI0       ; 11.675    ;           ; Rise       ; PHI0            ;
-;  RD[2]    ; PHI0       ; 11.675    ;           ; Rise       ; PHI0            ;
-;  RD[3]    ; PHI0       ; 11.675    ;           ; Rise       ; PHI0            ;
-;  RD[4]    ; PHI0       ; 11.675    ;           ; Rise       ; PHI0            ;
-;  RD[5]    ; PHI0       ; 11.675    ;           ; Rise       ; PHI0            ;
-;  RD[6]    ; PHI0       ; 11.630    ;           ; Rise       ; PHI0            ;
-;  RD[7]    ; PHI0       ; 11.630    ;           ; Rise       ; PHI0            ;
-; RD[*]     ; PHI0       ; 11.630    ;           ; Fall       ; PHI0            ;
-;  RD[0]    ; PHI0       ; 11.675    ;           ; Fall       ; PHI0            ;
-;  RD[1]    ; PHI0       ; 11.675    ;           ; Fall       ; PHI0            ;
-;  RD[2]    ; PHI0       ; 11.675    ;           ; Fall       ; PHI0            ;
-;  RD[3]    ; PHI0       ; 11.675    ;           ; Fall       ; PHI0            ;
-;  RD[4]    ; PHI0       ; 11.675    ;           ; Fall       ; PHI0            ;
-;  RD[5]    ; PHI0       ; 11.675    ;           ; Fall       ; PHI0            ;
-;  RD[6]    ; PHI0       ; 11.630    ;           ; Fall       ; PHI0            ;
-;  RD[7]    ; PHI0       ; 11.630    ;           ; Fall       ; PHI0            ;
-+-----------+------------+-----------+-----------+------------+-----------------+
-
-
 +-------------------------------------------------------------------------+
 ; Setup Transfers                                                         ;
 +------------+----------+------------+------------+------------+----------+
 ; From Clock ; To Clock ; RR Paths   ; FR Paths   ; RF Paths   ; FF Paths ;
 +------------+----------+------------+------------+------------+----------+
-; C25M       ; C25M     ; 1526       ; 0          ; 88         ; 0        ;
+; C25M       ; C25M     ; 1405       ; 0          ; 95         ; 0        ;
 ; PHI0       ; C25M     ; false path ; false path ; false path ; 0        ;
 +------------+----------+------------+------------+------------+----------+
 Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
@@ -1341,7 +469,7 @@ Entries labeled "false path" only account for clock-to-clock false paths and not
 +------------+----------+------------+------------+------------+----------+
 ; From Clock ; To Clock ; RR Paths   ; FR Paths   ; RF Paths   ; FF Paths ;
 +------------+----------+------------+------------+------------+----------+
-; C25M       ; C25M     ; 1526       ; 0          ; 88         ; 0        ;
+; C25M       ; C25M     ; 1405       ; 0          ; 95         ; 0        ;
 ; PHI0       ; C25M     ; false path ; false path ; false path ; 0        ;
 +------------+----------+------------+------------+------------+----------+
 Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
@@ -1376,67 +504,283 @@ No dedicated SERDES Transmitter circuitry present in device or used in design
 ---------------
 ; Report RSKM ;
 ---------------
-No dedicated SERDES Receiver circuitry present in device or used in design
+No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
 
 
 +------------------------------------------------+
-; Unconstrained Paths                            ;
+; Unconstrained Paths Summary                    ;
 +---------------------------------+-------+------+
 ; Property                        ; Setup ; Hold ;
 +---------------------------------+-------+------+
 ; Illegal Clocks                  ; 0     ; 0    ;
 ; Unconstrained Clocks            ; 0     ; 0    ;
-; Unconstrained Input Ports       ; 44    ; 44   ;
-; Unconstrained Input Port Paths  ; 246   ; 246  ;
-; Unconstrained Output Ports      ; 45    ; 45   ;
-; Unconstrained Output Port Paths ; 217   ; 217  ;
+; Unconstrained Input Ports       ; 42    ; 42   ;
+; Unconstrained Input Port Paths  ; 251   ; 251  ;
+; Unconstrained Output Ports      ; 44    ; 44   ;
+; Unconstrained Output Port Paths ; 214   ; 214  ;
 +---------------------------------+-------+------+
 
 
-+------------------------------------+
-; TimeQuest Timing Analyzer Messages ;
-+------------------------------------+
++-------------------------------------+
+; Clock Status Summary                ;
++--------+-------+------+-------------+
+; Target ; Clock ; Type ; Status      ;
++--------+-------+------+-------------+
+; C25M   ; C25M  ; Base ; Constrained ;
+; PHI0   ; PHI0  ; Base ; Constrained ;
++--------+-------+------+-------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Unconstrained Input Ports                                                                         ;
++------------+--------------------------------------------------------------------------------------+
+; Input Port ; Comment                                                                              ;
++------------+--------------------------------------------------------------------------------------+
+; DMAin      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; INTin      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; MISO       ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; MOSI       ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; PHI0       ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[0]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[1]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[2]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[3]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[4]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[5]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[6]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[7]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[8]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[9]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[10]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[11]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[12]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[13]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[14]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[15]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[0]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[1]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[2]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[3]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[4]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[5]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[6]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[7]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[0]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[1]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[2]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[3]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[4]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[5]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[6]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[7]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nDEVSEL    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nIOSEL     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nIOSTRB    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nRES       ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nWE        ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
++------------+--------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Unconstrained Output Ports                                                                          ;
++-------------+---------------------------------------------------------------------------------------+
+; Output Port ; Comment                                                                               ;
++-------------+---------------------------------------------------------------------------------------+
+; DMAout      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; DQMH        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; DQML        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; FCK         ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; INTout      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; MOSI        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RCKE        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[0]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[1]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[2]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[3]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[4]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[5]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[6]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[7]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RDdir       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SA[0]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SA[1]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SA[2]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SA[3]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SA[4]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SA[5]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SA[6]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SA[7]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SA[8]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SA[9]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SA[10]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SA[11]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SA[12]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SBA[1]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[0]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[1]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[2]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[3]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[4]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[5]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[6]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[7]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nCAS        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nFCS        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nRAS        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nRCS        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nRESout     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nSWE        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
++-------------+---------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Unconstrained Input Ports                                                                         ;
++------------+--------------------------------------------------------------------------------------+
+; Input Port ; Comment                                                                              ;
++------------+--------------------------------------------------------------------------------------+
+; DMAin      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; INTin      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; MISO       ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; MOSI       ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; PHI0       ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[0]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[1]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[2]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[3]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[4]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[5]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[6]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[7]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[8]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[9]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[10]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[11]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[12]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[13]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[14]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RA[15]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[0]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[1]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[2]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[3]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[4]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[5]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[6]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[7]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[0]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[1]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[2]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[3]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[4]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[5]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[6]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[7]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nDEVSEL    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nIOSEL     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nIOSTRB    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nRES       ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nWE        ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
++------------+--------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Unconstrained Output Ports                                                                          ;
++-------------+---------------------------------------------------------------------------------------+
+; Output Port ; Comment                                                                               ;
++-------------+---------------------------------------------------------------------------------------+
+; DMAout      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; DQMH        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; DQML        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; FCK         ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; INTout      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; MOSI        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RCKE        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[0]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[1]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[2]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[3]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[4]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[5]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[6]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RD[7]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; RDdir       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SA[0]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SA[1]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SA[2]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SA[3]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SA[4]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SA[5]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SA[6]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SA[7]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SA[8]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SA[9]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SA[10]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SA[11]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SA[12]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SBA[1]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[0]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[1]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[2]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[3]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[4]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[5]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[6]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SD[7]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nCAS        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nFCS        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nRAS        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nRCS        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nRESout     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; nSWE        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
++-------------+---------------------------------------------------------------------------------------+
+
+
++--------------------------+
+; Timing Analyzer Messages ;
++--------------------------+
 Info: *******************************************************************
-Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
-    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
-    Info: Processing started: Tue Sep 14 01:35:32 2021
+Info: Running Quartus Prime Timing Analyzer
+    Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+    Info: Processing started: Tue Mar 28 05:06:38 2023
 Info: Command: quartus_sta GR8RAM -c GR8RAM
 Info: qsta_default_script.tcl version: #1
-Warning (20028): Parallel compilation is not licensed and has been disabled
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
 Info (21077): Low junction temperature is 0 degrees C
 Info (21077): High junction temperature is 85 degrees C
-Info (306004): Started post-fitting delay annotation
-Info (306005): Delay annotation completed successfully
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
 Info (332104): Reading SDC File: 'GR8RAM.sdc'
-Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
-Info (332146): Worst-case setup slack is 12.419
-    Info (332119):     Slack End Point TNS Clock 
-    Info (332119): ========= ============= =====================
-    Info (332119):    12.419         0.000 C25M 
-Info (332146): Worst-case hold slack is 1.393
-    Info (332119):     Slack End Point TNS Clock 
-    Info (332119): ========= ============= =====================
-    Info (332119):     1.393         0.000 C25M 
-Info (332146): Worst-case recovery slack is 33.300
-    Info (332119):     Slack End Point TNS Clock 
-    Info (332119): ========= ============= =====================
-    Info (332119):    33.300         0.000 C25M 
-Info (332146): Worst-case removal slack is 6.146
-    Info (332119):     Slack End Point TNS Clock 
-    Info (332119): ========= ============= =====================
-    Info (332119):     6.146         0.000 C25M 
+Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
+Info: Can't run Report Timing Closure Recommendations. The current device family is not supported.
+Info (332146): Worst-case setup slack is 12.472
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    12.472               0.000 C25M 
+Info (332146): Worst-case hold slack is 1.383
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     1.383               0.000 C25M 
+Info (332146): Worst-case recovery slack is 33.331
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    33.331               0.000 C25M 
+Info (332146): Worst-case removal slack is 6.115
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     6.115               0.000 C25M 
 Info (332146): Worst-case minimum pulse width slack is 19.734
-    Info (332119):     Slack End Point TNS Clock 
-    Info (332119): ========= ============= =====================
-    Info (332119):    19.734         0.000 C25M 
-    Info (332119):   488.734         0.000 PHI0 
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    19.734               0.000 C25M 
+    Info (332119):   488.734               0.000 PHI0 
 Info (332001): The selected device family is not supported by the report_metastability command.
 Info (332102): Design is not fully constrained for setup requirements
 Info (332102): Design is not fully constrained for hold requirements
-Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 1 warning
-    Info: Peak virtual memory: 374 megabytes
-    Info: Processing ended: Tue Sep 14 01:35:34 2021
-    Info: Elapsed time: 00:00:02
+Info: Quartus Prime Timing Analyzer was successful. 0 errors, 1 warning
+    Info: Peak virtual memory: 13052 megabytes
+    Info: Processing ended: Tue Mar 28 05:06:39 2023
+    Info: Elapsed time: 00:00:01
     Info: Total CPU time (on all processors): 00:00:01
 
 
diff --git a/cpld/output_files/GR8RAM.sta.summary b/cpld/output_files/GR8RAM.sta.summary
old mode 100755
new mode 100644
index d814531..4d1c4a1
--- a/cpld/output_files/GR8RAM.sta.summary
+++ b/cpld/output_files/GR8RAM.sta.summary
@@ -1,21 +1,21 @@
 ------------------------------------------------------------
-TimeQuest Timing Analyzer Summary
+Timing Analyzer Summary
 ------------------------------------------------------------
 
 Type  : Setup 'C25M'
-Slack : 12.419
+Slack : 12.472
 TNS   : 0.000
 
 Type  : Hold 'C25M'
-Slack : 1.393
+Slack : 1.383
 TNS   : 0.000
 
 Type  : Recovery 'C25M'
-Slack : 33.300
+Slack : 33.331
 TNS   : 0.000
 
 Type  : Removal 'C25M'
-Slack : 6.146
+Slack : 6.115
 TNS   : 0.000
 
 Type  : Minimum Pulse Width 'C25M'
diff --git a/sym-lib-table b/sym-lib-table
index ffd84bc..c2935de 100644
--- a/sym-lib-table
+++ b/sym-lib-table
@@ -1,6 +1,8 @@
 (sym_lib_table
+  (version 7)
   (lib (name "GW_RAM")(type "KiCad")(uri "${KIPRJMOD}/../GW_Parts/GW_RAM.kicad_sym")(options "")(descr ""))
   (lib (name "GW_PLD")(type "KiCad")(uri "${KIPRJMOD}/../GW_Parts/GW_PLD.kicad_sym")(options "")(descr ""))
   (lib (name "GW_Logic")(type "KiCad")(uri "${KIPRJMOD}/../GW_Parts/GW_Logic.kicad_sym")(options "")(descr ""))
   (lib (name "GW_Power")(type "KiCad")(uri "${KIPRJMOD}/../GW_Parts/GW_Power.kicad_sym")(options "")(descr ""))
+  (lib (name "GW_Analog")(type "KiCad")(uri "${KIPRJMOD}/../GW_Parts/GW_Analog.kicad_sym")(options "")(descr ""))
 )