mirror of
https://github.com/garrettsworkshop/GR8RAM.git
synced 2024-06-11 14:29:30 +00:00
A.1.0 RC2/3
This commit is contained in:
Zane Kaminski
parent
2aa9051954
commit
6d7f8ad3a2
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@ -15,7 +15,7 @@
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!
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!Quartus Prime SVF converter 19.1
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!
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!Device #1: EPM240 - //Mac/iCloud/Repos/GR8RAM/CPLD/output_files/GR8RAM.pof Sun May 12 22:39:19 2024
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!Device #1: EPM240 - //Mac/iCloud/Repos/GR8RAM/CPLD/output_files/GR8RAM.pof Tue May 14 02:45:43 2024
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!
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!NOTE "USERCODE" "00160A1C";
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!
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@ -1,5 +1,5 @@
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Assembler report for GR8RAM
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Sun May 12 22:39:19 2024
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Tue May 14 02:45:43 2024
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Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
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@ -38,7 +38,7 @@ https://fpgasoftware.intel.com/eula.
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+---------------------------------------------------------------+
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; Assembler Summary ;
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+-----------------------+---------------------------------------+
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; Assembler Status ; Successful - Sun May 12 22:39:19 2024 ;
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; Assembler Status ; Successful - Tue May 14 02:45:43 2024 ;
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; Revision Name ; GR8RAM ;
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; Top-level Entity Name ; GR8RAM ;
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; Family ; MAX II ;
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@ -78,14 +78,14 @@ https://fpgasoftware.intel.com/eula.
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Info: *******************************************************************
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Info: Running Quartus Prime Assembler
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Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
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Info: Processing started: Sun May 12 22:39:19 2024
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Info: Processing started: Tue May 14 02:45:42 2024
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Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM
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Info (115031): Writing out detailed assembly data for power analysis
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Info (115030): Assembler is generating device programming files
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Info: Quartus Prime Assembler was successful. 0 errors, 0 warnings
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Info: Peak virtual memory: 13107 megabytes
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Info: Processing ended: Sun May 12 22:39:19 2024
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Info: Elapsed time: 00:00:00
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Info: Peak virtual memory: 13100 megabytes
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Info: Processing ended: Tue May 14 02:45:43 2024
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Info: Elapsed time: 00:00:01
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Info: Total CPU time (on all processors): 00:00:01
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@ -1,13 +0,0 @@
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/* Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition */
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JedecChain;
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FileRevision(JESD32A);
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DefaultMfr(6E);
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P ActionCode(Cfg)
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Device PartName(EPM240T100) Path("//Mac/iCloud/Repos/GR8RAM/CPLD/output_files/") File("GR8RAM.pof") MfrSpec(OpMask(1) SEC_Device(EPM240T100) Child_OpMask(2 3 3));
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ChainEnd;
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AlteraBegin;
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ChainType(JTAG);
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AlteraEnd;
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@ -1 +1 @@
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Sun May 12 22:39:23 2024
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Tue May 14 02:45:47 2024
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@ -1,94 +0,0 @@
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EDA Netlist Writer report for GR8RAM
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Tue Feb 28 11:21:31 2023
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Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
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---------------------
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; Table of Contents ;
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---------------------
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1. Legal Notice
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2. EDA Netlist Writer Summary
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3. Simulation Settings
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4. Simulation Generated Files
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5. EDA Netlist Writer Messages
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----------------
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; Legal Notice ;
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----------------
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Copyright (C) 2022 Intel Corporation. All rights reserved.
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Your use of Intel Corporation's design tools, logic functions
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and other software and tools, and any partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Intel Program License
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Subscription Agreement, the Intel Quartus Prime License Agreement,
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the Intel FPGA IP License Agreement, or other applicable license
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agreement, including, without limitation, that your use is for
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the sole purpose of programming logic devices manufactured by
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Intel and sold by Intel or its authorized distributors. Please
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refer to the applicable agreement for further details, at
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https://fpgasoftware.intel.com/eula.
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+-------------------------------------------------------------------+
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; EDA Netlist Writer Summary ;
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+---------------------------+---------------------------------------+
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; EDA Netlist Writer Status ; Successful - Tue Feb 28 11:21:31 2023 ;
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; Revision Name ; GR8RAM ;
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; Top-level Entity Name ; GR8RAM ;
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; Family ; MAX II ;
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; Simulation Files Creation ; Successful ;
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+---------------------------+---------------------------------------+
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+---------------------------------------------------------------------------------------------------------------------------------+
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; Simulation Settings ;
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+---------------------------------------------------------------------------------------------------+-----------------------------+
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; Option ; Setting ;
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+---------------------------------------------------------------------------------------------------+-----------------------------+
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; Tool Name ; Questa Intel FPGA (Verilog) ;
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; Generate functional simulation netlist ; On ;
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; Truncate long hierarchy paths ; Off ;
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; Map illegal HDL characters ; Off ;
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; Flatten buses into individual nodes ; Off ;
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; Maintain hierarchy ; Off ;
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; Bring out device-wide set/reset signals as ports ; Off ;
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; Enable glitch filtering ; Off ;
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; Do not write top level VHDL entity ; Off ;
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; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ;
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; Architecture name in VHDL output netlist ; structure ;
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; Generate third-party EDA tool command script for RTL functional simulation ; Off ;
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; Generate third-party EDA tool command script for gate-level simulation ; Off ;
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+---------------------------------------------------------------------------------------------------+-----------------------------+
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+--------------------------------------------------+
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; Simulation Generated Files ;
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+--------------------------------------------------+
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; Generated Files ;
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+--------------------------------------------------+
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; /Repos2/GR8RAM/cpld2/simulation/questa/GR8RAM.vo ;
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+--------------------------------------------------+
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+-----------------------------+
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; EDA Netlist Writer Messages ;
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+-----------------------------+
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Info: *******************************************************************
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Info: Running Quartus Prime EDA Netlist Writer
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Info: Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
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Info: Processing started: Tue Feb 28 11:21:30 2023
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Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM
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Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
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Info (204019): Generated file GR8RAM.vo in folder "/Repos2/GR8RAM/cpld2/simulation/questa/" for EDA simulation tool
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Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
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Info: Peak virtual memory: 13024 megabytes
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Info: Processing ended: Tue Feb 28 11:21:31 2023
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Info: Elapsed time: 00:00:01
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Info: Total CPU time (on all processors): 00:00:01
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@ -1,5 +1,5 @@
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Fitter report for GR8RAM
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Sun May 12 22:39:17 2024
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Tue May 14 02:45:40 2024
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Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
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@ -57,7 +57,7 @@ https://fpgasoftware.intel.com/eula.
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+---------------------------------------------------------------------+
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; Fitter Summary ;
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+-----------------------+---------------------------------------------+
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; Fitter Status ; Successful - Sun May 12 22:39:17 2024 ;
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; Fitter Status ; Successful - Tue May 14 02:45:40 2024 ;
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; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
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; Revision Name ; GR8RAM ;
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; Top-level Entity Name ; GR8RAM ;
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@ -134,8 +134,8 @@ https://fpgasoftware.intel.com/eula.
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; ; ;
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; Usage by Processor ; % Time Used ;
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; Processor 1 ; 100.0% ;
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; Processor 2 ; 1.3% ;
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; Processors 3-4 ; 1.1% ;
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; Processor 2 ; 1.2% ;
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; Processors 3-4 ; 1.0% ;
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+----------------------------+-------------+
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@ -754,16 +754,16 @@ Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
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Info (170193): Fitter routing operations beginning
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Info (170195): Router estimated average interconnect usage is 35% of the available device resources
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Info (170196): Router estimated peak interconnect usage is 35% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
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Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
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Info (11888): Total time spent on timing analysis during the Fitter is 0.35 seconds.
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Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
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Info (11888): Total time spent on timing analysis during the Fitter is 0.31 seconds.
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Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
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Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
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Info (144001): Generated suppressed messages file /Repos/GR8RAM/CPLD/output_files/GR8RAM.fit.smsg
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Info: Quartus Prime Fitter was successful. 0 errors, 2 warnings
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Info: Peak virtual memory: 13774 megabytes
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Info: Processing ended: Sun May 12 22:39:17 2024
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Info: Peak virtual memory: 13776 megabytes
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Info: Processing ended: Tue May 14 02:45:40 2024
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Info: Elapsed time: 00:00:03
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Info: Total CPU time (on all processors): 00:00:05
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Info: Total CPU time (on all processors): 00:00:04
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+----------------------------+
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@ -1,4 +1,4 @@
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Fitter Status : Successful - Sun May 12 22:39:17 2024
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Fitter Status : Successful - Tue May 14 02:45:40 2024
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Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
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Revision Name : GR8RAM
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Top-level Entity Name : GR8RAM
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@ -1,5 +1,5 @@
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Flow report for GR8RAM
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Sun May 12 22:39:22 2024
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Tue May 14 02:45:46 2024
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Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
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@ -41,7 +41,7 @@ https://fpgasoftware.intel.com/eula.
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+---------------------------------------------------------------------+
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; Flow Summary ;
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+-----------------------+---------------------------------------------+
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; Flow Status ; Successful - Sun May 12 22:39:19 2024 ;
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; Flow Status ; Successful - Tue May 14 02:45:43 2024 ;
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; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
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; Revision Name ; GR8RAM ;
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; Top-level Entity Name ; GR8RAM ;
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@ -60,7 +60,7 @@ https://fpgasoftware.intel.com/eula.
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+-------------------+---------------------+
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; Option ; Setting ;
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+-------------------+---------------------+
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; Start date & time ; 05/12/2024 22:38:54 ;
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; Start date & time ; 05/14/2024 02:45:12 ;
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; Main task ; Compilation ;
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; Revision Name ; GR8RAM ;
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+-------------------+---------------------+
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@ -72,7 +72,7 @@ https://fpgasoftware.intel.com/eula.
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; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
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+---------------------------------------+----------------------------------------+---------------+-------------+------------+
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; ALM_REGISTER_PACKING_EFFORT ; High ; Medium ; -- ; -- ;
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; COMPILER_SIGNATURE_ID ; 121380219419.171556793410016 ; -- ; -- ; -- ;
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; COMPILER_SIGNATURE_ID ; 121380219419.171566911200836 ; -- ; -- ; -- ;
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; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ;
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; IOBANK_VCCIO ; -- (Not supported for targeted family) ; -- ; -- ; 1 ;
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; IOBANK_VCCIO ; -- (Not supported for targeted family) ; -- ; -- ; 2 ;
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@ -91,11 +91,11 @@ https://fpgasoftware.intel.com/eula.
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+----------------------+--------------+-------------------------+---------------------+------------------------------------+
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; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
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+----------------------+--------------+-------------------------+---------------------+------------------------------------+
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; Analysis & Synthesis ; 00:00:19 ; 1.0 ; 13135 MB ; 00:00:41 ;
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; Fitter ; 00:00:03 ; 1.0 ; 13774 MB ; 00:00:05 ;
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; Assembler ; 00:00:00 ; 1.0 ; 13103 MB ; 00:00:01 ;
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; Timing Analyzer ; 00:00:01 ; 1.0 ; 13094 MB ; 00:00:01 ;
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; Total ; 00:00:23 ; -- ; -- ; 00:00:48 ;
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; Analysis & Synthesis ; 00:00:23 ; 1.0 ; 13137 MB ; 00:00:49 ;
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; Fitter ; 00:00:03 ; 1.0 ; 13776 MB ; 00:00:04 ;
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; Assembler ; 00:00:01 ; 1.0 ; 13096 MB ; 00:00:01 ;
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; Timing Analyzer ; 00:00:02 ; 1.0 ; 13095 MB ; 00:00:01 ;
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; Total ; 00:00:29 ; -- ; -- ; 00:00:55 ;
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+----------------------+--------------+-------------------------+---------------------+------------------------------------+
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@ -1,5 +1,5 @@
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Analysis & Synthesis report for GR8RAM
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Sun May 12 22:39:13 2024
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Tue May 14 02:45:35 2024
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Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
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||||
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||||
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@ -46,7 +46,7 @@ https://fpgasoftware.intel.com/eula.
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+---------------------------------------------------------------------------+
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; Analysis & Synthesis Summary ;
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+-----------------------------+---------------------------------------------+
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; Analysis & Synthesis Status ; Successful - Sun May 12 22:39:13 2024 ;
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; Analysis & Synthesis Status ; Successful - Tue May 14 02:45:35 2024 ;
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; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
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; Revision Name ; GR8RAM ;
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; Top-level Entity Name ; GR8RAM ;
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@ -281,7 +281,7 @@ Encoding Type: One-Hot
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Info: *******************************************************************
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Info: Running Quartus Prime Analysis & Synthesis
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Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
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Info: Processing started: Sun May 12 22:38:54 2024
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Info: Processing started: Tue May 14 02:45:12 2024
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Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM
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Info (16303): Aggressive Area optimization mode selected -- logic area will be prioritized at the potential cost of reduced timing performance
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Info (20032): Parallel compilation is enabled and will use up to 4 processors
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@ -304,10 +304,10 @@ Info (21057): Implemented 334 device resources after synthesis - the final resou
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Info (21061): Implemented 254 logic cells
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Info (144001): Generated suppressed messages file /Repos/GR8RAM/CPLD/output_files/GR8RAM.map.smsg
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Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 8 warnings
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Info: Peak virtual memory: 13135 megabytes
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Info: Processing ended: Sun May 12 22:39:13 2024
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Info: Elapsed time: 00:00:19
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Info: Total CPU time (on all processors): 00:00:41
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Info: Peak virtual memory: 13137 megabytes
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Info: Processing ended: Tue May 14 02:45:35 2024
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Info: Elapsed time: 00:00:23
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Info: Total CPU time (on all processors): 00:00:49
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+------------------------------------------+
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@ -1,4 +1,4 @@
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Analysis & Synthesis Status : Successful - Sun May 12 22:39:13 2024
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Analysis & Synthesis Status : Successful - Tue May 14 02:45:35 2024
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||||
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Revision Name : GR8RAM
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Top-level Entity Name : GR8RAM
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@ -1,5 +1,5 @@
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Timing Analyzer report for GR8RAM
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Sun May 12 22:39:22 2024
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Tue May 14 02:45:46 2024
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||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
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||||
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||||
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@ -93,7 +93,7 @@ https://fpgasoftware.intel.com/eula.
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+---------------+--------+--------------------------+
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; SDC File Path ; Status ; Read at ;
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+---------------+--------+--------------------------+
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; GR8RAM.sdc ; OK ; Sun May 12 22:39:22 2024 ;
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; GR8RAM.sdc ; OK ; Tue May 14 02:45:45 2024 ;
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+---------------+--------+--------------------------+
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@ -745,7 +745,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
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Info: *******************************************************************
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||||
Info: Running Quartus Prime Timing Analyzer
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||||
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
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Info: Processing started: Sun May 12 22:39:21 2024
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Info: Processing started: Tue May 14 02:45:44 2024
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Info: Command: quartus_sta GR8RAM -c GR8RAM
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Info: qsta_default_script.tcl version: #1
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Info (20032): Parallel compilation is enabled and will use up to 4 processors
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@ -781,9 +781,9 @@ Info (332001): The selected device family is not supported by the report_metasta
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Info (332102): Design is not fully constrained for setup requirements
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Info (332102): Design is not fully constrained for hold requirements
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Info: Quartus Prime Timing Analyzer was successful. 0 errors, 0 warnings
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Info: Peak virtual memory: 13094 megabytes
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Info: Processing ended: Sun May 12 22:39:22 2024
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Info: Elapsed time: 00:00:01
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Info: Peak virtual memory: 13095 megabytes
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Info: Processing ended: Tue May 14 02:45:46 2024
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Info: Elapsed time: 00:00:02
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Info: Total CPU time (on all processors): 00:00:01
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@ -15,7 +15,7 @@
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!
|
||||
!Quartus Prime SVF converter 19.1
|
||||
!
|
||||
!Device #1: EPM240 - //Mac/iCloud/Repos/GR8RAM/CPLD/output_files/GR8RAM.pof Sun May 12 22:39:19 2024
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!Device #1: EPM240 - //Mac/iCloud/Repos/GR8RAM/CPLD/output_files/GR8RAM.pof Tue May 14 02:45:43 2024
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!
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||||
!NOTE "USERCODE" "00160A1C";
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||||
!
|
||||
|
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|
|||
Loading…
Reference in New Issue
Block a user