diff --git a/cpld/GR8RAM.qsf b/cpld/GR8RAM.qsf index 886cda8..cae00f8 100755 --- a/cpld/GR8RAM.qsf +++ b/cpld/GR8RAM.qsf @@ -56,4 +56,13 @@ set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF set_global_assignment -name FITTER_EFFORT "STANDARD FIT" set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE AREA -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF \ No newline at end of file +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF +set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON +set_global_assignment -name SAFE_STATE_MACHINE ON +set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON +set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES ALWAYS +set_global_assignment -name AUTO_RESOURCE_SHARING ON +set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 2.0 +set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 2.0 +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS +set_global_assignment -name ALM_REGISTER_PACKING_EFFORT HIGH \ No newline at end of file diff --git a/cpld/GR8RAM.qws b/cpld/GR8RAM.qws new file mode 100755 index 0000000..5ef41df Binary files /dev/null and b/cpld/GR8RAM.qws differ diff --git a/cpld/GR8RAM.v b/cpld/GR8RAM.v index e2451ef..0aec353 100644 --- a/cpld/GR8RAM.v +++ b/cpld/GR8RAM.v @@ -230,78 +230,81 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, reg RTPBr = 0; // RTPBusy registered to sync with C25M always @(negedge C25M) begin UFMBr0 <= UFMB; RTPBr0 <= RTPB; end always @(posedge C25M) begin UFMBr <= UFMBr0; RTPBr <= RTPBr0; end - reg SetLoaded = 0; + reg [1:0] SS = 0; reg SetFW; reg SetLim8M; always @(posedge C25M) begin - if (~SetLoaded) begin - if (LS[15:0]<=16'h0FB0) begin - ARCLK <= 0; - ARShift <= 1; - DRCLK <= 0; - DRShift <= 0; - end else if (LS[15:0]<=16'h0FFF) begin - ARCLK <= ~LS[1]; - ARShift <= 1; - DRCLK <= 0; - DRShift <= 0; - SetFW <= 1'b1; - SetLim8M <= 1'b1; - end else if (LS[15:0]<=16'h1FFF) begin - case (LS[3:1]) - 3'h0: begin - ARCLK <= 0; - ARShift <= 0; - DRCLK <= 1; - DRShift <= 0; - end 3'h1: begin - ARCLK <= 0; - ARShift <= 0; - DRCLK <= 0; - DRShift <= 1; - end 3'h2: begin - ARCLK <= 0; - ARShift <= 0; - DRCLK <= 1; - DRShift <= 1; - if (LS[3:0]==4'h2 && DRDOut) SetLoaded <= 1; - end 3'h3: begin - ARCLK <= 0; - ARShift <= 0; - DRCLK <= 0; - DRShift <= 1; - end 3'h4: begin - ARCLK <= 0; - ARShift <= 0; - DRCLK <= 1; - DRShift <= 1; - if (LS[3:0]==4'h4) SetFW <= DRDOut; - end 3'h5: begin - ARCLK <= 0; - ARShift <= 0; - DRCLK <= 0; - DRShift <= 1; - end 3'h6: begin - ARCLK <= 1; - ARShift <= 0; - DRCLK <= 0; - DRShift <= 1; - if (LS[3:0]==4'h6) SetLim8M <= DRDOut; - end 3'h7: begin - ARCLK <= 0; - ARShift <= 0; - DRCLK <= 0; - DRShift <= 0; - end - endcase - end else SetLoaded <= 1; + if (SS[1:0]!=2'b11) begin + if (SS[1:0]==2'b10 && LS[3:0]==4'h2 && DRDOut) SS[1:0] <= 2'b11; + else if (LS[15:0]==16'h0FB0) SS[1:0] <= 2'b01; + else if (LS[15:0]==16'h0FFF) SS[1:0] <= 2'b10; + else if (LS[15:0]==16'h1FFF) SS[1:0] <= 2'b11; + end + end + always @(posedge C25M) begin + if (SS[1:0]==2'b00 /* LS[15:0]<=16'h0FB0 */) begin + ARCLK <= 0; + ARShift <= 1; + DRCLK <= 0; + DRShift <= 0; + end else if (SS[1:0]==2'b01 /* LS[15:0]<=16'h0FFF */) begin + ARCLK <= ~LS[1]; + ARShift <= 1; + DRCLK <= 0; + DRShift <= 0; + SetFW <= 1'b1; + SetLim8M <= 1'b1; + end else if (SS[1:0]==2'b10 /* LS[15:0]<=16'h1FFF */) begin + case (LS[3:1]) + 3'h0: begin + ARCLK <= 0; + ARShift <= 0; + DRCLK <= 1; + DRShift <= 0; + end 3'h1: begin + ARCLK <= 0; + ARShift <= 0; + DRCLK <= 0; + DRShift <= 1; + end 3'h2: begin + ARCLK <= 0; + ARShift <= 0; + DRCLK <= 1; + DRShift <= 1; + end 3'h3: begin + ARCLK <= 0; + ARShift <= 0; + DRCLK <= 0; + DRShift <= 1; + end 3'h4: begin + ARCLK <= 0; + ARShift <= 0; + DRCLK <= 1; + DRShift <= 1; + if (LS[3:0]==4'h4) SetFW <= DRDOut; + end 3'h5: begin + ARCLK <= 0; + ARShift <= 0; + DRCLK <= 0; + DRShift <= 1; + end 3'h6: begin + ARCLK <= 1; + ARShift <= 0; + DRCLK <= 0; + DRShift <= 1; + if (LS[3:0]==4'h6) SetLim8M <= DRDOut; + end 3'h7: begin + ARCLK <= 0; + ARShift <= 0; + DRCLK <= 0; + DRShift <= 0; + end + endcase DRDIn <= 0; - end else if (PS==7 /* && ... FIXME */) begin + end else begin ARCLK <= 0; ARShift <= 0; DRShift <= 1; - - DRCLK <= 0; DRDIn <= 0; end @@ -337,22 +340,25 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, /* SDRAM address/command */ output [1:0] SBA; assign SBA[1:0] = - Amux[2:0]==2'h0 ? 2'b00 : // mode register / "all" - Amux[2:0]==2'h1 ? 2'b00 : // FIXME: init row / col - Amux[2:0]==2'h2 ? 2'b10 : // ROM row / col - /* 2'h3 */ { 1'b0, Addr[23] & SetFW & ~SetLim8M }; // RAM col - output [12:0] SA; assign SA[12:0] = - Amux[2:0]==3'h0 ? 13'b0001000100000 : // mode register - Amux[2:0]==3'h1 ? 13'b0011000100000 : // "all" - Amux[2:0]==3'h2 ? 13'b0011000100000 : // FIXME: init row - Amux[2:0]==3'h3 ? 13'b0011000100000 : // FIXME: init col + Amux[2:1]==2'h0 ? 2'b00 : // mode register / "all" + Amux[2:1]==2'h1 ? 2'b00 : // FIXME: init row / col + Amux[2:1]==2'h2 ? 2'b10 : // ROM row / col + /* 2'h3 */ { 1'b0, Addr[23] & SetFW & ~SetLim8M }; // RAM row/col + output [12:0] SA; + assign SA[12] = Amux[2:0]==3'h6 && Addr[22] && SetFW; + /*assign SA[12:0] = + Amux[2:0]==3'h0 ? 13'b0001000100000 : // mode register + Amux[2:0]==3'h1 ? 13'b0011000100000 : // "all" + Amux[2:0]==3'h2 ? { 9'b001100010, LS[16:13] } : // init row + Amux[2:0]==3'h3 ? { 4'b0011, LS[12:4] } : // init col Amux[2:0]==3'h4 ? { 9'b000000000, Bank[1:0], RAcur[11:10] } : // ROM row Amux[2:0]==3'h5 ? { 4'b0000, RAcur[9:1]} : // ROM col - Amux[2:0]==3'h6 ? { Addr[22] & SetFW, - Addr[21] & SetFW, + Amux[2:0]==3'h6 ? { Addr[22] & SetFW, + Addr[21] & SetFW, Addr[20] & SetFW, Addr[19:10] } : // RAM row - /* 3'h7 */ { 4'b0000, Addr[9:1] }; // RAM col + { 4'b0000, Addr[9:1] }; // RAM col + */ output DQML; assign DQML = Amux[2:0]==3'h0 ? 1'b1 : // mode register Amux[2:0]==3'h1 ? 1'b1 : // "all" @@ -362,7 +368,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, Amux[2:0]==3'h5 ? RAcur[0]: // ROM col Amux[2:0]==3'h6 ? 1'b1 : // RAM row /* 3'h7 */ Addr[0]; // RAM col - output DQMH; assign DQMH = + output DQMH; assign DQMH = Amux[2:0]==3'h0 ? 1'b1 : // mode register Amux[2:0]==3'h1 ? 1'b1 : // "all" Amux[2:0]==3'h2 ? 1'b1 : // FIXME: init row diff --git a/cpld/db/GR8RAM.(0).cnf.cdb b/cpld/db/GR8RAM.(0).cnf.cdb index 8dab69a..e16e272 100755 Binary files a/cpld/db/GR8RAM.(0).cnf.cdb and b/cpld/db/GR8RAM.(0).cnf.cdb differ diff --git a/cpld/db/GR8RAM.(0).cnf.hdb b/cpld/db/GR8RAM.(0).cnf.hdb index bc535ff..acb7f66 100755 Binary files a/cpld/db/GR8RAM.(0).cnf.hdb and b/cpld/db/GR8RAM.(0).cnf.hdb differ diff --git a/cpld/db/GR8RAM.asm.qmsg b/cpld/db/GR8RAM.asm.qmsg index e41c033..8242e42 100755 --- a/cpld/db/GR8RAM.asm.qmsg +++ b/cpld/db/GR8RAM.asm.qmsg @@ -1,6 +1,6 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616153593678 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616153593694 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 19 07:33:13 2021 " "Processing started: Fri Mar 19 07:33:13 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616153593694 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1616153593694 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1616153593694 ""} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1616153594788 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1616153594819 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "293 " "Peak virtual memory: 293 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616153595398 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 19 07:33:15 2021 " "Processing ended: Fri Mar 19 07:33:15 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616153595398 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616153595398 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616153595398 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1616153595398 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616186128983 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616186128983 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 19 16:35:28 2021 " "Processing started: Fri Mar 19 16:35:28 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616186128983 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1616186128983 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1616186128983 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1616186130343 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1616186130390 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "293 " "Peak virtual memory: 293 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616186131124 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 19 16:35:31 2021 " "Processing ended: Fri Mar 19 16:35:31 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616186131124 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616186131124 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616186131124 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1616186131124 ""} diff --git a/cpld/db/GR8RAM.asm.rdb b/cpld/db/GR8RAM.asm.rdb index cb16983..eae3550 100755 Binary files a/cpld/db/GR8RAM.asm.rdb and b/cpld/db/GR8RAM.asm.rdb differ diff --git a/cpld/db/GR8RAM.asm_labs.ddb b/cpld/db/GR8RAM.asm_labs.ddb index 3c1e725..02c3aeb 100755 Binary files a/cpld/db/GR8RAM.asm_labs.ddb and b/cpld/db/GR8RAM.asm_labs.ddb differ diff --git a/cpld/db/GR8RAM.cmp.cdb b/cpld/db/GR8RAM.cmp.cdb index 3d14fb7..eac4ca1 100755 Binary files a/cpld/db/GR8RAM.cmp.cdb and b/cpld/db/GR8RAM.cmp.cdb differ diff --git a/cpld/db/GR8RAM.cmp.hdb b/cpld/db/GR8RAM.cmp.hdb index b8180eb..7f2a9fc 100755 Binary files a/cpld/db/GR8RAM.cmp.hdb and b/cpld/db/GR8RAM.cmp.hdb differ diff --git a/cpld/db/GR8RAM.cmp.idb b/cpld/db/GR8RAM.cmp.idb index d51f9c6..460bf9e 100755 Binary files a/cpld/db/GR8RAM.cmp.idb and b/cpld/db/GR8RAM.cmp.idb differ diff --git a/cpld/db/GR8RAM.cmp.rdb b/cpld/db/GR8RAM.cmp.rdb index 9b0882b..b0e7317 100755 Binary files a/cpld/db/GR8RAM.cmp.rdb and b/cpld/db/GR8RAM.cmp.rdb differ diff --git a/cpld/db/GR8RAM.cmp0.ddb b/cpld/db/GR8RAM.cmp0.ddb index 2ffb76c..96a07a0 100755 Binary files a/cpld/db/GR8RAM.cmp0.ddb and b/cpld/db/GR8RAM.cmp0.ddb differ diff --git a/cpld/db/GR8RAM.fit.qmsg b/cpld/db/GR8RAM.fit.qmsg index f68eb3e..e38a15c 100755 --- a/cpld/db/GR8RAM.fit.qmsg +++ b/cpld/db/GR8RAM.fit.qmsg @@ -1,40 +1,40 @@ -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1616153584815 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1616153584846 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1616153585049 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1616153585049 ""} -{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1616153585331 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1616153585378 ""} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1616153585784 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1616153585784 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1616153585784 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1616153585784 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1616153585784 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1616153585784 ""} -{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "68 68 " "No exact pin location assignment(s) for 68 pins of 68 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nRESout " "Pin nRESout not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nRESout } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 27 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nRESout } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 178 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RAdir " "Pin RAdir not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RAdir } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 53 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RAdir } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 306 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RDdir " "Pin RDdir not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RDdir } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 88 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RDdir } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 307 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SBA\[0\] " "Pin SBA\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SBA[0] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 339 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SBA[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 157 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SBA\[1\] " "Pin SBA\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SBA[1] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 339 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SBA[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 158 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[0\] " "Pin SA\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[0] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 344 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 159 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[1\] " "Pin SA\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[1] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 344 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 160 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[2\] " "Pin SA\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[2] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 344 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 161 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[3\] " "Pin SA\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[3] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 344 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 162 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[4\] " "Pin SA\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[4] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 344 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 163 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[5\] " "Pin SA\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[5] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 344 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 164 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[6\] " "Pin SA\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[6] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 344 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 165 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[7\] " "Pin SA\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[7] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 344 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 166 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[8\] " "Pin SA\[8\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[8] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 344 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 167 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[9\] " "Pin SA\[9\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[9] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 344 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 168 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[10\] " "Pin SA\[10\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[10] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 344 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 169 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[11\] " "Pin SA\[11\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[11] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 344 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 170 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[12\] " "Pin SA\[12\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[12] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 344 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 171 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nRCS " "Pin nRCS not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nRCS } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 376 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nRCS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 282 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nRAS " "Pin nRAS not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nRAS } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 377 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nRAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 284 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nCAS " "Pin nCAS not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nCAS } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 378 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nCAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 286 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nSWE " "Pin nSWE not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nSWE } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 379 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nSWE } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 288 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DQML " "Pin DQML not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { DQML } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 356 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { DQML } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 279 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DQMH " "Pin DQMH not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { DQMH } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 365 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { DQMH } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 290 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RCKE " "Pin RCKE not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RCKE } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 375 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RCKE } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 280 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nFCS " "Pin nFCS not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nFCS } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 128 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nFCS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 308 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "FCK " "Pin FCK not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { FCK } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 130 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { FCK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 205 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "MOSI " "Pin MOSI not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { MOSI } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 132 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { MOSI } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 242 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[0\] " "Pin RD\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[0] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 85 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 92 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[1\] " "Pin RD\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[1] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 85 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 91 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[2\] " "Pin RD\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[2] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 85 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 90 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[3\] " "Pin RD\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[3] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 85 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 89 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[4\] " "Pin RD\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[4] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 85 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 88 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[5\] " "Pin RD\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[5] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 85 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 87 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[6\] " "Pin RD\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[6] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 85 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 86 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[7\] " "Pin RD\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[7] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 85 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 54 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[0\] " "Pin SD\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[0] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 311 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 126 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[1\] " "Pin SD\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[1] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 311 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 125 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[2\] " "Pin SD\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[2] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 311 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 124 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[3\] " "Pin SD\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[3] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 311 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 123 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[4\] " "Pin SD\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[4] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 311 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 121 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[5\] " "Pin SD\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[5] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 311 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 120 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[6\] " "Pin SD\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[6] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 311 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 119 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[7\] " "Pin SD\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[7] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 311 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 118 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "PHI0 " "Pin PHI0 not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI0 } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 9 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 300 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nWE " "Pin nWE not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nWE } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 50 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nWE } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 305 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nDEVSEL " "Pin nDEVSEL not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nDEVSEL } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 36 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nDEVSEL } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 303 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nIOSTRB " "Pin nIOSTRB not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nIOSTRB } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 36 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nIOSTRB } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 304 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nIOSEL " "Pin nIOSEL not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nIOSEL } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 36 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nIOSEL } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 302 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "C25M " "Pin C25M not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { C25M } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 9 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { C25M } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 299 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[1\] " "Pin RA\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[1] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 142 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[10\] " "Pin RA\[10\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[10] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 151 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[2\] " "Pin RA\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[2] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 143 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[11\] " "Pin RA\[11\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[11] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 152 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[3\] " "Pin RA\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[3] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 144 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[4\] " "Pin RA\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[4] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 145 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[5\] " "Pin RA\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[5] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 146 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[6\] " "Pin RA\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[6] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 147 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[7\] " "Pin RA\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[7] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 148 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[8\] " "Pin RA\[8\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[8] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 149 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[9\] " "Pin RA\[9\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[9] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 150 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[0\] " "Pin RA\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[0] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 141 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[14\] " "Pin RA\[14\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[14] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 155 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[15\] " "Pin RA\[15\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[15] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 156 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[12\] " "Pin RA\[12\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[12] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 153 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[13\] " "Pin RA\[13\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[13] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 154 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nRES " "Pin nRES not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nRES } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 16 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nRES } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 301 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "MISO " "Pin MISO not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { MISO } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 135 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { MISO } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 309 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1616153585800 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1616153586097 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1616153586112 ""} -{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1616153586128 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1616153586128 ""} -{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1616153586128 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1616153586128 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 C25M " " 1.000 C25M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1616153586128 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1616153586128 ""} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1616153586143 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1616153586143 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1616153586143 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 14 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 14" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 9 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1616153586159 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1616153586159 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1616153586175 ""} -{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0 186391 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "Fitter" 0 -1 1616153586222 ""} -{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1616153586222 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1616153586315 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1616153586331 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1616153586347 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1616153586362 ""} -{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "67 unused 3.3V 23 28 16 " "Number of I/O pins in group: 67 (unused VREF, 3.3V VCCIO, 23 input, 28 output, 16 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "I/O standards used: 3.3-V LVTTL." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1616153586394 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1616153586394 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1616153586394 ""} -{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 1 37 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 37 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1616153586409 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 42 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 42 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1616153586409 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1616153586409 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1616153586409 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1616153586456 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1616153586722 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1616153587050 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1616153587066 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1616153589676 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:03 " "Fitter placement operations ending: elapsed time is 00:00:03" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1616153589676 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1616153589723 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "27 " "Router estimated average interconnect usage is 27% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "27 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 27% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 27% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 27% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1616153590051 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1616153590051 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1616153590474 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.39 " "Total time spent on timing analysis during the Fitter is 0.39 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1616153590520 ""} -{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1616153590520 ""} -{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1616153590552 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1616153590849 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "373 " "Peak virtual memory: 373 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616153591161 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 19 07:33:11 2021 " "Processing ended: Fri Mar 19 07:33:11 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616153591161 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616153591161 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:09 " "Total CPU time (on all processors): 00:00:09" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616153591161 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1616153591161 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1616186118624 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1616186118639 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1616186118905 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1616186118905 ""} +{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1616186119514 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1616186119561 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1616186119999 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1616186119999 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1616186119999 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1616186119999 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1616186119999 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1616186119999 ""} +{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "68 68 " "No exact pin location assignment(s) for 68 pins of 68 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nRESout " "Pin nRESout not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nRESout } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 27 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nRESout } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 179 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RAdir " "Pin RAdir not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RAdir } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 53 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RAdir } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 311 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RDdir " "Pin RDdir not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RDdir } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 88 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RDdir } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 312 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SBA\[0\] " "Pin SBA\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SBA[0] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 342 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SBA[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 158 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SBA\[1\] " "Pin SBA\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SBA[1] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 342 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SBA[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 159 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[0\] " "Pin SA\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[0] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 347 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 160 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[1\] " "Pin SA\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[1] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 347 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 161 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[2\] " "Pin SA\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[2] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 347 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 162 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[3\] " "Pin SA\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[3] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 347 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 163 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[4\] " "Pin SA\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[4] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 347 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 164 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[5\] " "Pin SA\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[5] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 347 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 165 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[6\] " "Pin SA\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[6] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 347 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 166 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[7\] " "Pin SA\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[7] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 347 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 167 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[8\] " "Pin SA\[8\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[8] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 347 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 168 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[9\] " "Pin SA\[9\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[9] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 347 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 169 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[10\] " "Pin SA\[10\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[10] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 347 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 170 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[11\] " "Pin SA\[11\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[11] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 347 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 171 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[12\] " "Pin SA\[12\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[12] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 347 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 172 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nRCS " "Pin nRCS not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nRCS } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 382 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nRCS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 287 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nRAS " "Pin nRAS not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nRAS } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 383 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nRAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 289 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nCAS " "Pin nCAS not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nCAS } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 384 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nCAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 291 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nSWE " "Pin nSWE not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nSWE } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 385 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nSWE } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 293 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DQML " "Pin DQML not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { DQML } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 362 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { DQML } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 284 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DQMH " "Pin DQMH not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { DQMH } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 371 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { DQMH } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 295 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RCKE " "Pin RCKE not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RCKE } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 381 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RCKE } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 285 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nFCS " "Pin nFCS not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nFCS } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 128 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nFCS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 313 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "FCK " "Pin FCK not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { FCK } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 130 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { FCK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 204 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "MOSI " "Pin MOSI not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { MOSI } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 132 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { MOSI } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 241 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[0\] " "Pin RD\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[0] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 85 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 92 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[1\] " "Pin RD\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[1] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 85 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 91 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[2\] " "Pin RD\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[2] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 85 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 90 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[3\] " "Pin RD\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[3] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 85 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 89 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[4\] " "Pin RD\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[4] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 85 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 88 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[5\] " "Pin RD\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[5] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 85 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 87 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[6\] " "Pin RD\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[6] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 85 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 86 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[7\] " "Pin RD\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[7] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 85 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 55 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[0\] " "Pin SD\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[0] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 314 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 125 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[1\] " "Pin SD\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[1] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 314 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 124 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[2\] " "Pin SD\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[2] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 314 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 123 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[3\] " "Pin SD\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[3] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 314 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 122 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[4\] " "Pin SD\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[4] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 314 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 121 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[5\] " "Pin SD\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[5] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 314 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 120 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[6\] " "Pin SD\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[6] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 314 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 119 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[7\] " "Pin SD\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[7] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 314 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 118 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "PHI0 " "Pin PHI0 not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI0 } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 9 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 305 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nWE " "Pin nWE not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nWE } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 50 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nWE } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 310 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nDEVSEL " "Pin nDEVSEL not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nDEVSEL } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 36 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nDEVSEL } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 308 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nIOSTRB " "Pin nIOSTRB not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nIOSTRB } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 36 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nIOSTRB } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 309 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nIOSEL " "Pin nIOSEL not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nIOSEL } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 36 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nIOSEL } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 307 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "C25M " "Pin C25M not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { C25M } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 9 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { C25M } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 304 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[0\] " "Pin RA\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[0] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 142 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[10\] " "Pin RA\[10\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[10] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 152 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[7\] " "Pin RA\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[7] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 149 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[1\] " "Pin RA\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[1] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 143 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[9\] " "Pin RA\[9\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[9] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 151 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[8\] " "Pin RA\[8\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[8] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 150 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[6\] " "Pin RA\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[6] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 148 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[5\] " "Pin RA\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[5] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 147 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[4\] " "Pin RA\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[4] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 146 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[3\] " "Pin RA\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[3] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 145 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[2\] " "Pin RA\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[2] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 144 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[14\] " "Pin RA\[14\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[14] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 156 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[15\] " "Pin RA\[15\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[15] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 157 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[12\] " "Pin RA\[12\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[12] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 154 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[13\] " "Pin RA\[13\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[13] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 155 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[11\] " "Pin RA\[11\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[11] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 153 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nRES " "Pin nRES not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nRES } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 16 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nRES } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 306 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "MISO " "Pin MISO not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { MISO } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 135 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { MISO } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 314 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616186120014 ""} } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1616186120014 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1616186120233 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1616186120233 ""} +{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1616186120249 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1616186120249 ""} +{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 3 clocks " "Found 3 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1616186120249 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1616186120249 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 ARCLK " " 1.000 ARCLK" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1616186120249 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 C25M " " 1.000 C25M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1616186120249 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 DRCLK " " 1.000 DRCLK" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1616186120249 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1616186120249 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1616186120264 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1616186120264 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1616186120280 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 14 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 14" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 9 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1616186120296 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1616186120296 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1616186120296 ""} +{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0 186391 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "Fitter" 0 -1 1616186120358 ""} +{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1616186120358 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1616186120421 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1616186120436 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1616186120436 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1616186120436 ""} +{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "67 unused 3.3V 23 28 16 " "Number of I/O pins in group: 67 (unused VREF, 3.3V VCCIO, 23 input, 28 output, 16 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "I/O standards used: 3.3-V LVTTL." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1616186120452 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1616186120452 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1616186120452 ""} +{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 1 37 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 37 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1616186120452 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 42 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 42 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1616186120452 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1616186120452 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1616186120452 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1616186120514 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1616186120749 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1616186121061 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1616186121077 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1616186123921 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:03 " "Fitter placement operations ending: elapsed time is 00:00:03" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1616186123936 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1616186123968 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "19 " "Router estimated average interconnect usage is 19% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "19 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1616186124296 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1616186124296 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1616186124843 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.52 " "Total time spent on timing analysis during the Fitter is 0.52 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1616186124889 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1616186124905 ""} +{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1616186124936 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1616186125139 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "376 " "Peak virtual memory: 376 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616186125436 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 19 16:35:25 2021 " "Processing ended: Fri Mar 19 16:35:25 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616186125436 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616186125436 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616186125436 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1616186125436 ""} diff --git a/cpld/db/GR8RAM.hier_info b/cpld/db/GR8RAM.hier_info index f7b1be7..0c4180a 100755 --- a/cpld/db/GR8RAM.hier_info +++ b/cpld/db/GR8RAM.hier_info @@ -15,20 +15,19 @@ C25M => SDOE.CLK C25M => WRD[6].CLK C25M => WRD[7].CLK C25M => DRDIn.CLK -C25M => SetLoaded.CLK C25M => SetLim8M.CLK C25M => SetFW.CLK C25M => DRShift.CLK C25M => DRCLK.CLK C25M => ARShift.CLK C25M => ARCLK.CLK +C25M => SS[0].CLK +C25M => SS[1].CLK C25M => MOSIOE.CLK C25M => MOSIout.CLK C25M => FCKEN.CLK C25M => FCS.CLK C25M => FCK~reg0.CLK -C25M => Bank[0].CLK -C25M => Bank[1].CLK C25M => Addr[0].CLK C25M => Addr[1].CLK C25M => Addr[2].CLK @@ -139,18 +138,18 @@ RD[7] <> RD[7] RDdir <= comb.DB_MAX_OUTPUT_PORT_TYPE SBA[0] <= SBA.DB_MAX_OUTPUT_PORT_TYPE SBA[1] <= SBA.DB_MAX_OUTPUT_PORT_TYPE -SA[0] <= SA.DB_MAX_OUTPUT_PORT_TYPE -SA[1] <= SA.DB_MAX_OUTPUT_PORT_TYPE -SA[2] <= SA.DB_MAX_OUTPUT_PORT_TYPE -SA[3] <= SA.DB_MAX_OUTPUT_PORT_TYPE -SA[4] <= SA.DB_MAX_OUTPUT_PORT_TYPE -SA[5] <= SA.DB_MAX_OUTPUT_PORT_TYPE -SA[6] <= SA.DB_MAX_OUTPUT_PORT_TYPE -SA[7] <= SA.DB_MAX_OUTPUT_PORT_TYPE -SA[8] <= SA.DB_MAX_OUTPUT_PORT_TYPE -SA[9] <= SA.DB_MAX_OUTPUT_PORT_TYPE -SA[10] <= SA.DB_MAX_OUTPUT_PORT_TYPE -SA[11] <= SA.DB_MAX_OUTPUT_PORT_TYPE +SA[0] <= +SA[1] <= +SA[2] <= +SA[3] <= +SA[4] <= +SA[5] <= +SA[6] <= +SA[7] <= +SA[8] <= +SA[9] <= +SA[10] <= +SA[11] <= SA[12] <= SA.DB_MAX_OUTPUT_PORT_TYPE nRCS <= nRCS~reg0.DB_MAX_OUTPUT_PORT_TYPE nRAS <= nRAS~reg0.DB_MAX_OUTPUT_PORT_TYPE diff --git a/cpld/db/GR8RAM.hif b/cpld/db/GR8RAM.hif index 64cfa8d..4af01ce 100755 Binary files a/cpld/db/GR8RAM.hif and b/cpld/db/GR8RAM.hif differ diff --git a/cpld/db/GR8RAM.ipinfo b/cpld/db/GR8RAM.ipinfo index fd31def..6d333ce 100755 Binary files a/cpld/db/GR8RAM.ipinfo and b/cpld/db/GR8RAM.ipinfo differ diff --git a/cpld/db/GR8RAM.map.cdb b/cpld/db/GR8RAM.map.cdb index b74821b..f5d09df 100755 Binary files a/cpld/db/GR8RAM.map.cdb and b/cpld/db/GR8RAM.map.cdb differ diff --git a/cpld/db/GR8RAM.map.hdb b/cpld/db/GR8RAM.map.hdb index 2370599..22da009 100755 Binary files a/cpld/db/GR8RAM.map.hdb and b/cpld/db/GR8RAM.map.hdb differ diff --git a/cpld/db/GR8RAM.map.qmsg b/cpld/db/GR8RAM.map.qmsg index 20b9c46..f6aff5e 100755 --- a/cpld/db/GR8RAM.map.qmsg +++ b/cpld/db/GR8RAM.map.qmsg @@ -1,31 +1,34 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616153574982 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616153574998 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 19 07:32:54 2021 " "Processing started: Fri Mar 19 07:32:54 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616153574998 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1616153574998 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1616153574998 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1616153576561 ""} -{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 72 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1616153576764 ""} -{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 188 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1616153576764 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_0ep " "Found entity 1: UFM_altufm_none_0ep" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616153576780 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616153576780 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1616153576780 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "gr8ram.v(85) " "Verilog HDL warning at gr8ram.v(85): extended using \"x\" or \"z\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 85 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1616153577046 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "gr8ram.v(311) " "Verilog HDL warning at gr8ram.v(311): extended using \"x\" or \"z\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 311 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1616153577046 ""} -{ "Warning" "WSGN_SEARCH_FILE" "gr8ram.v 1 1 " "Using design file gr8ram.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616153577061 ""} } { } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Quartus II" 0 -1 1616153577061 ""} -{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "UFMB gr8ram.v(223) " "Verilog HDL Implicit Net warning at gr8ram.v(223): created implicit net for \"UFMB\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 223 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1616153577061 ""} -{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "RTPB gr8ram.v(226) " "Verilog HDL Implicit Net warning at gr8ram.v(226): created implicit net for \"RTPB\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 226 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1616153577061 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1616153577093 ""} -{ "Warning" "WVRFX_VERI_2106_UNCONVERTED" "RDout gr8ram.v(86) " "Verilog HDL warning at gr8ram.v(86): object RDout used but never assigned" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 86 0 0 } } } 0 10858 "Verilog HDL warning at %2!s!: object %1!s! used but never assigned" 0 0 "Quartus II" 0 -1 1616153577093 "|GR8RAM"} -{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "UFMBr gr8ram.v(228) " "Verilog HDL or VHDL warning at gr8ram.v(228): object \"UFMBr\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 228 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616153577093 "|GR8RAM"} -{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "RTPBr gr8ram.v(230) " "Verilog HDL or VHDL warning at gr8ram.v(230): object \"RTPBr\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 230 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616153577093 "|GR8RAM"} -{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "RefReady gr8ram.v(332) " "Verilog HDL or VHDL warning at gr8ram.v(332): object \"RefReady\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 332 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616153577093 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 gr8ram.v(24) " "Verilog HDL assignment warning at gr8ram.v(24): truncated value with size 32 to match size of target (18)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 24 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616153577093 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 24 gr8ram.v(100) " "Verilog HDL assignment warning at gr8ram.v(100): truncated value with size 32 to match size of target (24)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 100 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616153577093 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 gr8ram.v(104) " "Verilog HDL assignment warning at gr8ram.v(104): truncated value with size 32 to match size of target (16)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 104 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616153577093 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 gr8ram.v(109) " "Verilog HDL assignment warning at gr8ram.v(109): truncated value with size 32 to match size of target (8)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 109 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616153577093 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 gr8ram.v(327) " "Verilog HDL assignment warning at gr8ram.v(327): truncated value with size 32 to match size of target (3)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 327 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616153577108 "|GR8RAM"} -{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "RDout 0 gr8ram.v(86) " "Net \"RDout\" at gr8ram.v(86) has no driver or initial value, using a default initial value '0'" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 86 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Quartus II" 0 -1 1616153577124 "|GR8RAM"} -{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "WRD\[5..0\] 0 gr8ram.v(312) " "Net \"WRD\[5..0\]\" at gr8ram.v(312) has no driver or initial value, using a default initial value '0'" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 312 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Quartus II" 0 -1 1616153577124 "|GR8RAM"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "gr8ram.v" "UFM_inst" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 226 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1616153577249 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_0ep UFM:UFM_inst\|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component " "Elaborating entity \"UFM_altufm_none_0ep\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component\"" { } { { "UFM.v" "UFM_altufm_none_0ep_component" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 216 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1616153577280 ""} -{ "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR_HDR" "" "Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "MOSI WRD\[6\] " "Converted the fan-out from the tri-state buffer \"MOSI\" to the node \"WRD\[6\]\" into an OR gate" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 132 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1616153578484 ""} } { } 0 13046 "Tri-state node(s) do not directly drive top-level pin(s)" 0 0 "Quartus II" 0 -1 1616153578484 ""} -{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616153578734 "|GR8RAM|RAdir"} { "Warning" "WMLS_MLS_STUCK_PIN" "SBA\[0\] GND " "Pin \"SBA\[0\]\" is stuck at GND" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 339 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616153578734 "|GR8RAM|SBA[0]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1616153578734 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "329 " "Implemented 329 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "24 " "Implemented 24 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1616153579297 ""} { "Info" "ICUT_CUT_TM_OPINS" "28 " "Implemented 28 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1616153579297 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Implemented 16 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1616153579297 ""} { "Info" "ICUT_CUT_TM_LCELLS" "260 " "Implemented 260 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1616153579297 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Quartus II" 0 -1 1616153579297 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1616153579297 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1616153579562 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 19 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 19 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "301 " "Peak virtual memory: 301 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616153579797 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 19 07:32:59 2021 " "Processing ended: Fri Mar 19 07:32:59 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616153579797 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616153579797 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616153579797 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1616153579797 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616186109748 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616186109764 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 19 16:35:09 2021 " "Processing started: Fri Mar 19 16:35:09 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616186109764 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1616186109764 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1616186109764 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1616186111186 ""} +{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 72 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1616186111498 ""} +{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 188 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1616186111498 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_0ep " "Found entity 1: UFM_altufm_none_0ep" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616186111498 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616186111498 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1616186111498 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "gr8ram.v(85) " "Verilog HDL warning at gr8ram.v(85): extended using \"x\" or \"z\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 85 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1616186111717 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "gr8ram.v(314) " "Verilog HDL warning at gr8ram.v(314): extended using \"x\" or \"z\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 314 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1616186111733 ""} +{ "Warning" "WSGN_SEARCH_FILE" "gr8ram.v 1 1 " "Using design file gr8ram.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616186111733 ""} } { } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Quartus II" 0 -1 1616186111733 ""} +{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "UFMB gr8ram.v(223) " "Verilog HDL Implicit Net warning at gr8ram.v(223): created implicit net for \"UFMB\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 223 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1616186111733 ""} +{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "RTPB gr8ram.v(226) " "Verilog HDL Implicit Net warning at gr8ram.v(226): created implicit net for \"RTPB\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 226 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1616186111733 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1616186111764 ""} +{ "Warning" "WVRFX_VERI_2106_UNCONVERTED" "RDout gr8ram.v(86) " "Verilog HDL warning at gr8ram.v(86): object RDout used but never assigned" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 86 0 0 } } } 0 10858 "Verilog HDL warning at %2!s!: object %1!s! used but never assigned" 0 0 "Quartus II" 0 -1 1616186111764 "|GR8RAM"} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "Bank gr8ram.v(118) " "Verilog HDL or VHDL warning at gr8ram.v(118): object \"Bank\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 118 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616186111764 "|GR8RAM"} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "UFMBr gr8ram.v(228) " "Verilog HDL or VHDL warning at gr8ram.v(228): object \"UFMBr\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 228 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616186111764 "|GR8RAM"} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "RTPBr gr8ram.v(230) " "Verilog HDL or VHDL warning at gr8ram.v(230): object \"RTPBr\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 230 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616186111764 "|GR8RAM"} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "RefReady gr8ram.v(335) " "Verilog HDL or VHDL warning at gr8ram.v(335): object \"RefReady\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 335 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616186111764 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 gr8ram.v(24) " "Verilog HDL assignment warning at gr8ram.v(24): truncated value with size 32 to match size of target (18)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 24 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616186111764 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 24 gr8ram.v(100) " "Verilog HDL assignment warning at gr8ram.v(100): truncated value with size 32 to match size of target (24)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 100 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616186111764 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 gr8ram.v(104) " "Verilog HDL assignment warning at gr8ram.v(104): truncated value with size 32 to match size of target (16)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 104 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616186111764 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 gr8ram.v(109) " "Verilog HDL assignment warning at gr8ram.v(109): truncated value with size 32 to match size of target (8)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 109 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616186111764 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 gr8ram.v(330) " "Verilog HDL assignment warning at gr8ram.v(330): truncated value with size 32 to match size of target (3)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 330 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616186111780 "|GR8RAM"} +{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "RDout 0 gr8ram.v(86) " "Net \"RDout\" at gr8ram.v(86) has no driver or initial value, using a default initial value '0'" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 86 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Quartus II" 0 -1 1616186111780 "|GR8RAM"} +{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "WRD\[5..0\] 0 gr8ram.v(315) " "Net \"WRD\[5..0\]\" at gr8ram.v(315) has no driver or initial value, using a default initial value '0'" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 315 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Quartus II" 0 -1 1616186111780 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "SA\[11..0\] gr8ram.v(347) " "Output port \"SA\[11..0\]\" at gr8ram.v(347) has no driver" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 347 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1616186111795 "|GR8RAM"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "gr8ram.v" "UFM_inst" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 226 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1616186111967 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_0ep UFM:UFM_inst\|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component " "Elaborating entity \"UFM_altufm_none_0ep\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component\"" { } { { "UFM.v" "UFM_altufm_none_0ep_component" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 216 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1616186112030 ""} +{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 -1 1616186113280 ""} +{ "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR_HDR" "" "Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "MOSI WRD\[6\] " "Converted the fan-out from the tri-state buffer \"MOSI\" to the node \"WRD\[6\]\" into an OR gate" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 132 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1616186113327 ""} } { } 0 13046 "Tri-state node(s) do not directly drive top-level pin(s)" 0 0 "Quartus II" 0 -1 1616186113327 ""} +{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616186113608 "|GR8RAM|RAdir"} { "Warning" "WMLS_MLS_STUCK_PIN" "SBA\[0\] GND " "Pin \"SBA\[0\]\" is stuck at GND" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 342 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616186113608 "|GR8RAM|SBA[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "SA\[0\] GND " "Pin \"SA\[0\]\" is stuck at GND" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 347 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616186113608 "|GR8RAM|SA[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "SA\[1\] GND " "Pin \"SA\[1\]\" is stuck at GND" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 347 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616186113608 "|GR8RAM|SA[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "SA\[2\] GND " "Pin \"SA\[2\]\" is stuck at GND" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 347 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616186113608 "|GR8RAM|SA[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "SA\[3\] GND " "Pin \"SA\[3\]\" is stuck at GND" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 347 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616186113608 "|GR8RAM|SA[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "SA\[4\] GND " "Pin \"SA\[4\]\" is stuck at GND" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 347 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616186113608 "|GR8RAM|SA[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "SA\[5\] GND " "Pin \"SA\[5\]\" is stuck at GND" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 347 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616186113608 "|GR8RAM|SA[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "SA\[6\] GND " "Pin \"SA\[6\]\" is stuck at GND" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 347 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616186113608 "|GR8RAM|SA[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "SA\[7\] GND " "Pin \"SA\[7\]\" is stuck at GND" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 347 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616186113608 "|GR8RAM|SA[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "SA\[8\] GND " "Pin \"SA\[8\]\" is stuck at GND" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 347 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616186113608 "|GR8RAM|SA[8]"} { "Warning" "WMLS_MLS_STUCK_PIN" "SA\[9\] GND " "Pin \"SA\[9\]\" is stuck at GND" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 347 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616186113608 "|GR8RAM|SA[9]"} { "Warning" "WMLS_MLS_STUCK_PIN" "SA\[10\] GND " "Pin \"SA\[10\]\" is stuck at GND" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 347 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616186113608 "|GR8RAM|SA[10]"} { "Warning" "WMLS_MLS_STUCK_PIN" "SA\[11\] GND " "Pin \"SA\[11\]\" is stuck at GND" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 347 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616186113608 "|GR8RAM|SA[11]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1616186113608 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "306 " "Implemented 306 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "24 " "Implemented 24 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1616186113983 ""} { "Info" "ICUT_CUT_TM_OPINS" "28 " "Implemented 28 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1616186113983 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Implemented 16 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1616186113983 ""} { "Info" "ICUT_CUT_TM_LCELLS" "237 " "Implemented 237 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1616186113983 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Quartus II" 0 -1 1616186113983 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1616186113983 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1616186114420 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 33 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 33 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "301 " "Peak virtual memory: 301 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616186114655 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 19 16:35:14 2021 " "Processing ended: Fri Mar 19 16:35:14 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616186114655 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616186114655 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616186114655 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1616186114655 ""} diff --git a/cpld/db/GR8RAM.map.rdb b/cpld/db/GR8RAM.map.rdb index b9c92fa..6c18dca 100755 Binary files a/cpld/db/GR8RAM.map.rdb and b/cpld/db/GR8RAM.map.rdb differ diff --git a/cpld/db/GR8RAM.pre_map.hdb b/cpld/db/GR8RAM.pre_map.hdb index a45efbb..a79fb57 100755 Binary files a/cpld/db/GR8RAM.pre_map.hdb and b/cpld/db/GR8RAM.pre_map.hdb differ diff --git a/cpld/db/GR8RAM.quiproj.3716.rdr.flock b/cpld/db/GR8RAM.quiproj.3716.rdr.flock deleted file mode 100755 index e69de29..0000000 diff --git a/cpld/db/GR8RAM.root_partition.map.reg_db.cdb b/cpld/db/GR8RAM.root_partition.map.reg_db.cdb index e374c49..25bc02f 100755 Binary files a/cpld/db/GR8RAM.root_partition.map.reg_db.cdb and b/cpld/db/GR8RAM.root_partition.map.reg_db.cdb differ diff --git a/cpld/db/GR8RAM.routing.rdb b/cpld/db/GR8RAM.routing.rdb index 46897b8..64bf999 100755 Binary files a/cpld/db/GR8RAM.routing.rdb and b/cpld/db/GR8RAM.routing.rdb differ diff --git a/cpld/db/GR8RAM.rtlv.hdb b/cpld/db/GR8RAM.rtlv.hdb index f2c61e9..7bc2300 100755 Binary files a/cpld/db/GR8RAM.rtlv.hdb and b/cpld/db/GR8RAM.rtlv.hdb differ diff --git a/cpld/db/GR8RAM.rtlv_sg.cdb b/cpld/db/GR8RAM.rtlv_sg.cdb index d558b57..aeaee93 100755 Binary files a/cpld/db/GR8RAM.rtlv_sg.cdb and b/cpld/db/GR8RAM.rtlv_sg.cdb differ diff --git a/cpld/db/GR8RAM.rtlv_sg_swap.cdb b/cpld/db/GR8RAM.rtlv_sg_swap.cdb index 2ddae33..f2dcbda 100755 Binary files a/cpld/db/GR8RAM.rtlv_sg_swap.cdb and b/cpld/db/GR8RAM.rtlv_sg_swap.cdb differ diff --git a/cpld/db/GR8RAM.sgdiff.cdb b/cpld/db/GR8RAM.sgdiff.cdb index 809d13f..c8b2ef8 100755 Binary files a/cpld/db/GR8RAM.sgdiff.cdb and b/cpld/db/GR8RAM.sgdiff.cdb differ diff --git a/cpld/db/GR8RAM.sgdiff.hdb b/cpld/db/GR8RAM.sgdiff.hdb index 3251251..b77be27 100755 Binary files a/cpld/db/GR8RAM.sgdiff.hdb and b/cpld/db/GR8RAM.sgdiff.hdb differ diff --git a/cpld/db/GR8RAM.sta.qmsg b/cpld/db/GR8RAM.sta.qmsg index 8036029..3baff35 100755 --- a/cpld/db/GR8RAM.sta.qmsg +++ b/cpld/db/GR8RAM.sta.qmsg @@ -1,23 +1,23 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616153598352 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616153598368 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 19 07:33:17 2021 " "Processing started: Fri Mar 19 07:33:17 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616153598368 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1616153598368 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1616153598383 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1616153598555 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1616153599509 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1616153599790 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1616153599790 ""} -{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1616153600103 ""} -{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1616153600759 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1616153601103 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1616153601119 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C25M C25M " "create_clock -period 1.000 -name C25M C25M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1616153601135 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1616153601135 ""} -{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1616153601197 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1616153601432 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -9.506 " "Worst-case setup slack is -9.506" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616153601447 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616153601447 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.506 -540.769 C25M " " -9.506 -540.769 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616153601447 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1616153601447 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.639 " "Worst-case hold slack is 1.639" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616153601463 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616153601463 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.639 0.000 C25M " " 1.639 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616153601463 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1616153601463 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1616153601478 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1616153601494 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.289 " "Worst-case minimum pulse width slack is -2.289" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616153601510 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616153601510 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 C25M " " -2.289 -2.289 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616153601510 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1616153601510 ""} -{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1616153601635 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1616153601901 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1616153601901 ""} -{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "275 " "Peak virtual memory: 275 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616153602213 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 19 07:33:22 2021 " "Processing ended: Fri Mar 19 07:33:22 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616153602213 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616153602213 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616153602213 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1616153602213 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616186134749 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616186134780 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 19 16:35:33 2021 " "Processing started: Fri Mar 19 16:35:33 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616186134780 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1616186134780 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1616186134780 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1616186134968 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1616186135733 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1616186135937 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1616186135937 ""} +{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1616186136155 ""} +{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1616186136718 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1616186136905 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1616186136905 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1616186136921 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1616186136921 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C25M C25M " "create_clock -period 1.000 -name C25M C25M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1616186136921 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1616186136921 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1616186136952 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1616186137124 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616186137187 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616186137187 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 ARCLK " " -99.000 -99.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616186137187 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 DRCLK " " -99.000 -99.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616186137187 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.555 -547.115 C25M " " -9.555 -547.115 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616186137187 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1616186137187 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold -16.276 " "Worst-case hold slack is -16.276" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616186137218 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616186137218 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.276 -16.276 ARCLK " " -16.276 -16.276 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616186137218 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.256 -16.256 DRCLK " " -16.256 -16.256 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616186137218 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.377 0.000 C25M " " 1.377 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616186137218 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1616186137218 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1616186137312 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1616186137343 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616186137358 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616186137358 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 ARCLK " " -29.500 -59.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616186137358 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 DRCLK " " -29.500 -59.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616186137358 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 C25M " " -2.289 -2.289 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616186137358 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1616186137358 ""} +{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1616186137671 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1616186137827 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1616186137843 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "275 " "Peak virtual memory: 275 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616186138155 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 19 16:35:38 2021 " "Processing ended: Fri Mar 19 16:35:38 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616186138155 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616186138155 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616186138155 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1616186138155 ""} diff --git a/cpld/db/GR8RAM.sta.rdb b/cpld/db/GR8RAM.sta.rdb index e7463ee..4a83ee3 100755 Binary files a/cpld/db/GR8RAM.sta.rdb and b/cpld/db/GR8RAM.sta.rdb differ diff --git a/cpld/db/GR8RAM.sta_cmp.5_slow.tdb b/cpld/db/GR8RAM.sta_cmp.5_slow.tdb index 847bdbf..7161a87 100755 Binary files a/cpld/db/GR8RAM.sta_cmp.5_slow.tdb and b/cpld/db/GR8RAM.sta_cmp.5_slow.tdb differ diff --git a/cpld/db/GR8RAM.tmw_info b/cpld/db/GR8RAM.tmw_info new file mode 100755 index 0000000..a0b049c --- /dev/null +++ b/cpld/db/GR8RAM.tmw_info @@ -0,0 +1,6 @@ +start_full_compilation:s:00:00:32 +start_analysis_synthesis:s:00:00:08-start_full_compilation +start_analysis_elaboration:s-start_full_compilation +start_fitter:s:00:00:11-start_full_compilation +start_assembler:s:00:00:05-start_full_compilation +start_timing_analyzer:s:00:00:08-start_full_compilation diff --git a/cpld/db/GR8RAM.vpr.ammdb b/cpld/db/GR8RAM.vpr.ammdb index d42d098..688626a 100755 Binary files a/cpld/db/GR8RAM.vpr.ammdb and b/cpld/db/GR8RAM.vpr.ammdb differ diff --git a/cpld/db/logic_util_heursitic.dat b/cpld/db/logic_util_heursitic.dat index 3d321f6..b4eec2b 100755 Binary files a/cpld/db/logic_util_heursitic.dat and b/cpld/db/logic_util_heursitic.dat differ diff --git a/cpld/db/prev_cmp_GR8RAM.qmsg b/cpld/db/prev_cmp_GR8RAM.qmsg index d17d7fe..2cc8ff2 100755 --- a/cpld/db/prev_cmp_GR8RAM.qmsg +++ b/cpld/db/prev_cmp_GR8RAM.qmsg @@ -1,108 +1,16 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616153517201 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616153517201 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 19 07:31:56 2021 " "Processing started: Fri Mar 19 07:31:56 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616153517201 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1616153517201 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1616153517201 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1616153518951 ""} -{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 72 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1616153519217 ""} -{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 188 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1616153519232 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_0ep " "Found entity 1: UFM_altufm_none_0ep" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616153519232 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616153519232 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1616153519232 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "gr8ram.v(85) " "Verilog HDL warning at gr8ram.v(85): extended using \"x\" or \"z\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 85 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1616153519529 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "gr8ram.v(311) " "Verilog HDL warning at gr8ram.v(311): extended using \"x\" or \"z\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 311 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1616153519545 ""} -{ "Warning" "WSGN_SEARCH_FILE" "gr8ram.v 1 1 " "Using design file gr8ram.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616153519545 ""} } { } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Quartus II" 0 -1 1616153519545 ""} -{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "UFMB gr8ram.v(223) " "Verilog HDL Implicit Net warning at gr8ram.v(223): created implicit net for \"UFMB\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 223 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1616153519545 ""} -{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "RTPB gr8ram.v(226) " "Verilog HDL Implicit Net warning at gr8ram.v(226): created implicit net for \"RTPB\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 226 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1616153519545 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1616153519592 ""} -{ "Warning" "WVRFX_VERI_2106_UNCONVERTED" "RDout gr8ram.v(86) " "Verilog HDL warning at gr8ram.v(86): object RDout used but never assigned" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 86 0 0 } } } 0 10858 "Verilog HDL warning at %2!s!: object %1!s! used but never assigned" 0 0 "Quartus II" 0 -1 1616153519592 "|GR8RAM"} -{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "UFMBr gr8ram.v(228) " "Verilog HDL or VHDL warning at gr8ram.v(228): object \"UFMBr\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 228 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616153519592 "|GR8RAM"} -{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "RTPBr gr8ram.v(230) " "Verilog HDL or VHDL warning at gr8ram.v(230): object \"RTPBr\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 230 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616153519592 "|GR8RAM"} -{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "RefReady gr8ram.v(332) " "Verilog HDL or VHDL warning at gr8ram.v(332): object \"RefReady\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 332 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616153519592 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 gr8ram.v(24) " "Verilog HDL assignment warning at gr8ram.v(24): truncated value with size 32 to match size of target (18)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 24 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616153519592 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 24 gr8ram.v(100) " "Verilog HDL assignment warning at gr8ram.v(100): truncated value with size 32 to match size of target (24)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 100 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616153519592 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 gr8ram.v(104) " "Verilog HDL assignment warning at gr8ram.v(104): truncated value with size 32 to match size of target (16)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 104 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616153519592 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 gr8ram.v(109) " "Verilog HDL assignment warning at gr8ram.v(109): truncated value with size 32 to match size of target (8)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 109 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616153519592 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 gr8ram.v(327) " "Verilog HDL assignment warning at gr8ram.v(327): truncated value with size 32 to match size of target (3)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 327 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616153519607 "|GR8RAM"} -{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "RDout 0 gr8ram.v(86) " "Net \"RDout\" at gr8ram.v(86) has no driver or initial value, using a default initial value '0'" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 86 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Quartus II" 0 -1 1616153519607 "|GR8RAM"} -{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "WRD\[5..0\] 0 gr8ram.v(312) " "Net \"WRD\[5..0\]\" at gr8ram.v(312) has no driver or initial value, using a default initial value '0'" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 312 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Quartus II" 0 -1 1616153519607 "|GR8RAM"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "gr8ram.v" "UFM_inst" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 226 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1616153519779 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_0ep UFM:UFM_inst\|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component " "Elaborating entity \"UFM_altufm_none_0ep\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component\"" { } { { "UFM.v" "UFM_altufm_none_0ep_component" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 216 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1616153519811 ""} -{ "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR_HDR" "" "Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "MOSI WRD\[6\] " "Converted the fan-out from the tri-state buffer \"MOSI\" to the node \"WRD\[6\]\" into an OR gate" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 132 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1616153521326 ""} } { } 0 13046 "Tri-state node(s) do not directly drive top-level pin(s)" 0 0 "Quartus II" 0 -1 1616153521326 ""} -{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616153521670 "|GR8RAM|RAdir"} { "Warning" "WMLS_MLS_STUCK_PIN" "SBA\[0\] GND " "Pin \"SBA\[0\]\" is stuck at GND" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 339 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616153521670 "|GR8RAM|SBA[0]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1616153521670 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "329 " "Implemented 329 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "24 " "Implemented 24 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1616153522530 ""} { "Info" "ICUT_CUT_TM_OPINS" "28 " "Implemented 28 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1616153522530 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Implemented 16 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1616153522530 ""} { "Info" "ICUT_CUT_TM_LCELLS" "260 " "Implemented 260 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1616153522530 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Quartus II" 0 -1 1616153522530 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1616153522530 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1616153522936 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 19 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 19 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "301 " "Peak virtual memory: 301 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616153523358 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 19 07:32:03 2021 " "Processing ended: Fri Mar 19 07:32:03 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616153523358 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616153523358 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616153523358 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1616153523358 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616153526608 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 32-bit " "Running Quartus II 32-bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616153526624 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 19 07:32:04 2021 " "Processing started: Fri Mar 19 07:32:04 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616153526624 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1616153526624 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1616153526639 ""} -{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1616153526811 ""} -{ "Info" "0" "" "Project = GR8RAM" { } { } 0 0 "Project = GR8RAM" 0 0 "Fitter" 0 0 1616153526811 ""} -{ "Info" "0" "" "Revision = GR8RAM" { } { } 0 0 "Revision = GR8RAM" 0 0 "Fitter" 0 0 1616153526811 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1616153527530 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1616153527577 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1616153527796 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1616153527796 ""} -{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1616153528171 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1616153528218 ""} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1616153528671 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1616153528671 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1616153528671 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1616153528671 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1616153528671 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1616153528671 ""} -{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "68 68 " "No exact pin location assignment(s) for 68 pins of 68 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nRESout " "Pin nRESout not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nRESout } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 27 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nRESout } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 178 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RAdir " "Pin RAdir not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RAdir } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 53 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RAdir } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 307 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RDdir " "Pin RDdir not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RDdir } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 88 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RDdir } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 308 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SBA\[0\] " "Pin SBA\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SBA[0] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 339 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SBA[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 157 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SBA\[1\] " "Pin SBA\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SBA[1] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 339 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SBA[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 158 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[0\] " "Pin SA\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[0] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 344 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 159 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[1\] " "Pin SA\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[1] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 344 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 160 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[2\] " "Pin SA\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[2] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 344 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 161 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[3\] " "Pin SA\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[3] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 344 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 162 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[4\] " "Pin SA\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[4] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 344 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 163 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[5\] " "Pin SA\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[5] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 344 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 164 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[6\] " "Pin SA\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[6] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 344 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 165 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[7\] " "Pin SA\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[7] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 344 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 166 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[8\] " "Pin SA\[8\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[8] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 344 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 167 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[9\] " "Pin SA\[9\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[9] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 344 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 168 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[10\] " "Pin SA\[10\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[10] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 344 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 169 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[11\] " "Pin SA\[11\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[11] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 344 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 170 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[12\] " "Pin SA\[12\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[12] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 344 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 171 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nRCS " "Pin nRCS not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nRCS } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 376 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nRCS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 282 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nRAS " "Pin nRAS not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nRAS } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 377 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nRAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 284 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nCAS " "Pin nCAS not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nCAS } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 378 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nCAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 286 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nSWE " "Pin nSWE not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nSWE } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 379 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nSWE } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 288 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DQML " "Pin DQML not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { DQML } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 356 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { DQML } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 279 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DQMH " "Pin DQMH not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { DQMH } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 365 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { DQMH } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 290 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RCKE " "Pin RCKE not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RCKE } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 375 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RCKE } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 280 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nFCS " "Pin nFCS not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nFCS } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 128 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nFCS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 309 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "FCK " "Pin FCK not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { FCK } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 130 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { FCK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 205 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "MOSI " "Pin MOSI not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { MOSI } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 132 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { MOSI } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 242 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[0\] " "Pin RD\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[0] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 85 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 92 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[1\] " "Pin RD\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[1] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 85 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 91 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[2\] " "Pin RD\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[2] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 85 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 90 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[3\] " "Pin RD\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[3] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 85 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 89 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[4\] " "Pin RD\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[4] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 85 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 88 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[5\] " "Pin RD\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[5] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 85 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 87 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[6\] " "Pin RD\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[6] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 85 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 86 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[7\] " "Pin RD\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[7] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 85 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 54 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[0\] " "Pin SD\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[0] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 311 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 126 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[1\] " "Pin SD\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[1] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 311 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 125 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[2\] " "Pin SD\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[2] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 311 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 124 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[3\] " "Pin SD\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[3] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 311 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 123 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[4\] " "Pin SD\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[4] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 311 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 121 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[5\] " "Pin SD\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[5] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 311 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 120 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[6\] " "Pin SD\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[6] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 311 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 119 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[7\] " "Pin SD\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[7] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 311 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 118 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "PHI0 " "Pin PHI0 not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI0 } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 9 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 301 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nWE " "Pin nWE not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nWE } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 50 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nWE } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 306 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nDEVSEL " "Pin nDEVSEL not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nDEVSEL } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 36 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nDEVSEL } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 304 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nIOSTRB " "Pin nIOSTRB not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nIOSTRB } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 36 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nIOSTRB } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 305 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nIOSEL " "Pin nIOSEL not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nIOSEL } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 36 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nIOSEL } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 303 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "C25M " "Pin C25M not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { C25M } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 9 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { C25M } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 300 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[1\] " "Pin RA\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[1] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 142 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[10\] " "Pin RA\[10\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[10] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 151 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[2\] " "Pin RA\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[2] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 143 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[11\] " "Pin RA\[11\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[11] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 152 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[3\] " "Pin RA\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[3] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 144 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[4\] " "Pin RA\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[4] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 145 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[5\] " "Pin RA\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[5] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 146 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[6\] " "Pin RA\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[6] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 147 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[7\] " "Pin RA\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[7] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 148 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[8\] " "Pin RA\[8\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[8] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 149 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[9\] " "Pin RA\[9\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[9] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 150 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[0\] " "Pin RA\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[0] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 141 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[14\] " "Pin RA\[14\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[14] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 155 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[15\] " "Pin RA\[15\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[15] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 156 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[12\] " "Pin RA\[12\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[12] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 153 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[13\] " "Pin RA\[13\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[13] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 154 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nRES " "Pin nRES not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nRES } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 16 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nRES } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 302 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "MISO " "Pin MISO not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { MISO } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 135 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { MISO } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 310 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1616153528702 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1616153528843 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1616153528858 ""} -{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1616153528905 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1616153528905 ""} -{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1616153528905 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1616153528905 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 C25M " " 1.000 C25M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1616153528905 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1616153528905 ""} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1616153528921 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1616153528937 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1616153528968 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 14 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 14" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 9 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1616153528983 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1616153528983 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1616153528999 ""} -{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0 186391 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "Fitter" 0 -1 1616153529046 ""} -{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1616153529046 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1616153529108 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1616153529108 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1616153529108 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1616153529124 ""} -{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "67 unused 3.3V 23 28 16 " "Number of I/O pins in group: 67 (unused VREF, 3.3V VCCIO, 23 input, 28 output, 16 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "I/O standards used: 3.3-V LVTTL." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1616153529140 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1616153529140 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1616153529140 ""} -{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 1 37 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 37 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1616153529155 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 42 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 42 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1616153529155 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1616153529155 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1616153529155 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1616153529171 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1616153529374 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1616153529702 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1616153529734 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1616153532703 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:03 " "Fitter placement operations ending: elapsed time is 00:00:03" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1616153532718 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1616153532765 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "22 " "Router estimated average interconnect usage is 22% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "22 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 22% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 22% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 22% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1616153533140 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1616153533140 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1616153533593 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.36 " "Total time spent on timing analysis during the Fitter is 0.36 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1616153533625 ""} -{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1616153533625 ""} -{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1616153533640 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1616153533921 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "373 " "Peak virtual memory: 373 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616153534203 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 19 07:32:14 2021 " "Processing ended: Fri Mar 19 07:32:14 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616153534203 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616153534203 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:09 " "Total CPU time (on all processors): 00:00:09" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616153534203 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1616153534203 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1616153537812 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616153537812 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 19 07:32:17 2021 " "Processing started: Fri Mar 19 07:32:17 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616153537812 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1616153537812 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1616153537812 ""} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1616153539344 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1616153539360 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "293 " "Peak virtual memory: 293 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616153540016 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 19 07:32:20 2021 " "Processing ended: Fri Mar 19 07:32:20 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616153540016 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616153540016 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616153540016 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1616153540016 ""} -{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1616153540907 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1616153543094 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616153543110 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 19 07:32:21 2021 " "Processing started: Fri Mar 19 07:32:21 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616153543110 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1616153543110 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1616153543110 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1616153543297 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1616153544063 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1616153544219 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1616153544219 ""} -{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1616153544376 ""} -{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1616153544844 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1616153545032 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1616153545048 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C25M C25M " "create_clock -period 1.000 -name C25M C25M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1616153545048 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1616153545048 ""} -{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1616153545079 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1616153545235 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -9.078 " "Worst-case setup slack is -9.078" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616153545266 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616153545266 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.078 -545.414 C25M " " -9.078 -545.414 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616153545266 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1616153545266 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.414 " "Worst-case hold slack is 1.414" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616153545266 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616153545266 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.414 0.000 C25M " " 1.414 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616153545266 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1616153545266 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1616153545282 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1616153545298 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.289 " "Worst-case minimum pulse width slack is -2.289" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616153545298 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616153545298 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 C25M " " -2.289 -2.289 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616153545298 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1616153545298 ""} -{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1616153545423 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1616153545579 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1616153545579 ""} -{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "275 " "Peak virtual memory: 275 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616153545938 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 19 07:32:25 2021 " "Processing ended: Fri Mar 19 07:32:25 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616153545938 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616153545938 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616153545938 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1616153545938 ""} -{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 25 s " "Quartus II Full Compilation was successful. 0 errors, 25 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1616153547063 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616186090623 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616186090638 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 19 16:34:50 2021 " "Processing started: Fri Mar 19 16:34:50 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616186090638 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1616186090638 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1616186090638 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1616186092107 ""} +{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 72 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1616186092388 ""} +{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 188 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1616186092388 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_0ep " "Found entity 1: UFM_altufm_none_0ep" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616186092404 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616186092404 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1616186092404 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "gr8ram.v(85) " "Verilog HDL warning at gr8ram.v(85): extended using \"x\" or \"z\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 85 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1616186092623 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "gr8ram.v(315) " "Verilog HDL warning at gr8ram.v(315): extended using \"x\" or \"z\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 315 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1616186092623 ""} +{ "Warning" "WSGN_SEARCH_FILE" "gr8ram.v 1 1 " "Using design file gr8ram.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616186092638 ""} } { } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Quartus II" 0 -1 1616186092638 ""} +{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "UFMB gr8ram.v(223) " "Verilog HDL Implicit Net warning at gr8ram.v(223): created implicit net for \"UFMB\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 223 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1616186092638 ""} +{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "RTPB gr8ram.v(226) " "Verilog HDL Implicit Net warning at gr8ram.v(226): created implicit net for \"RTPB\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 226 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1616186092638 ""} +{ "Error" "EVRFX_VERI_UNDECLARED_OBJECT" "SetLoaded gr8ram.v(274) " "Verilog HDL error at gr8ram.v(274): object \"SetLoaded\" is not declared" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 274 0 0 } } } 0 10161 "Verilog HDL error at %2!s!: object \"%1!s!\" is not declared" 0 0 "Quartus II" 0 -1 1616186092638 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1616186092795 ""} +{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1 3 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was unsuccessful. 1 error, 3 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "296 " "Peak virtual memory: 296 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616186093013 ""} { "Error" "EQEXE_END_BANNER_TIME" "Fri Mar 19 16:34:53 2021 " "Processing ended: Fri Mar 19 16:34:53 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616186093013 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616186093013 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616186093013 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1616186093013 ""} +{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 3 s 3 s " "Quartus II Full Compilation was unsuccessful. 3 errors, 3 warnings" { } { } 0 293001 "Quartus II %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1616186093966 ""} diff --git a/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt b/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt index f518336..e3c3412 100755 Binary files a/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt and b/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt differ diff --git a/cpld/output_files/GR8RAM.asm.rpt b/cpld/output_files/GR8RAM.asm.rpt index 01eec4e..af658b4 100755 --- a/cpld/output_files/GR8RAM.asm.rpt +++ b/cpld/output_files/GR8RAM.asm.rpt @@ -1,5 +1,5 @@ Assembler report for GR8RAM -Fri Mar 19 07:33:15 2021 +Fri Mar 19 16:35:30 2021 Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition @@ -37,7 +37,7 @@ applicable agreement for further details. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Fri Mar 19 07:33:15 2021 ; +; Assembler Status ; Successful - Fri Mar 19 16:35:30 2021 ; ; Revision Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ; ; Family ; MAX II ; @@ -90,8 +90,8 @@ applicable agreement for further details. ; Option ; Setting ; +----------------+-------------------------------------------------------+ ; Device ; EPM240T100C5 ; -; JTAG usercode ; 0x00164F11 ; -; Checksum ; 0x00165309 ; +; JTAG usercode ; 0x0016B2B7 ; +; Checksum ; 0x0016B52F ; +----------------+-------------------------------------------------------+ @@ -101,14 +101,14 @@ applicable agreement for further details. Info: ******************************************************************* Info: Running Quartus II 32-bit Assembler Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - Info: Processing started: Fri Mar 19 07:33:13 2021 + Info: Processing started: Fri Mar 19 16:35:28 2021 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM Info (115031): Writing out detailed assembly data for power analysis Info (115030): Assembler is generating device programming files Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings Info: Peak virtual memory: 293 megabytes - Info: Processing ended: Fri Mar 19 07:33:15 2021 - Info: Elapsed time: 00:00:02 + Info: Processing ended: Fri Mar 19 16:35:31 2021 + Info: Elapsed time: 00:00:03 Info: Total CPU time (on all processors): 00:00:02 diff --git a/cpld/output_files/GR8RAM.done b/cpld/output_files/GR8RAM.done index ac942b9..9a0673b 100755 --- a/cpld/output_files/GR8RAM.done +++ b/cpld/output_files/GR8RAM.done @@ -1 +1 @@ -Fri Mar 19 07:33:23 2021 +Fri Mar 19 16:35:39 2021 diff --git a/cpld/output_files/GR8RAM.fit.rpt b/cpld/output_files/GR8RAM.fit.rpt index d4a1357..56df282 100755 --- a/cpld/output_files/GR8RAM.fit.rpt +++ b/cpld/output_files/GR8RAM.fit.rpt @@ -1,5 +1,5 @@ Fitter report for GR8RAM -Fri Mar 19 07:33:10 2021 +Fri Mar 19 16:35:25 2021 Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition @@ -57,14 +57,14 @@ applicable agreement for further details. +-----------------------------------------------------------------------------+ ; Fitter Summary ; +---------------------------+-------------------------------------------------+ -; Fitter Status ; Successful - Fri Mar 19 07:33:10 2021 ; +; Fitter Status ; Successful - Fri Mar 19 16:35:25 2021 ; ; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; ; Revision Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ; ; Family ; MAX II ; ; Device ; EPM240T100C5 ; ; Timing Models ; Final ; -; Total logic elements ; 235 / 240 ( 98 % ) ; +; Total logic elements ; 217 / 240 ( 90 % ) ; ; Total pins ; 68 / 80 ( 85 % ) ; ; Total virtual pins ; 0 ; ; UFM blocks ; 1 / 1 ( 100 % ) ; @@ -79,15 +79,16 @@ applicable agreement for further details. ; Device ; EPM240T100C5 ; ; ; Minimum Core Junction Temperature ; 0 ; ; ; Maximum Core Junction Temperature ; 85 ; ; +; Placement Effort Multiplier ; 2.0 ; 1.0 ; +; Router Effort Multiplier ; 2.0 ; 1.0 ; ; Fit Attempts to Skip ; 0 ; 0.0 ; ; Device I/O Standard ; 3.3-V LVTTL ; ; +; Final Placement Optimizations ; Always ; Automatically ; ; Fitter Effort ; Standard Fit ; Auto Fit ; ; Use smart compilation ; Off ; Off ; ; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; ; Enable compact report table ; Off ; Off ; ; Router Timing Optimization Level ; Normal ; Normal ; -; Placement Effort Multiplier ; 1.0 ; 1.0 ; -; Router Effort Multiplier ; 1.0 ; 1.0 ; ; Always Enable Input Buffers ; Off ; Off ; ; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ; ; Optimize Multi-Corner Timing ; Off ; Off ; @@ -98,7 +99,6 @@ applicable agreement for further details. ; Regenerate full fit report during ECO compiles ; Off ; Off ; ; Optimize IOC Register Placement for Timing ; Normal ; Normal ; ; Limit to One Fitting Attempt ; Off ; Off ; -; Final Placement Optimizations ; Automatically ; Automatically ; ; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; ; Fitter Initial Placement Seed ; 1 ; 1 ; ; Slow Slew Rate ; Off ; Off ; @@ -128,12 +128,12 @@ applicable agreement for further details. ; Number detected on machine ; 2 ; ; Maximum allowed ; 2 ; ; ; ; -; Average used ; 1.33 ; +; Average used ; 1.50 ; ; Maximum used ; 2 ; ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; -; Processor 2 ; 33.3% ; +; Processor 2 ; 50.0% ; +----------------------------+-------------+ @@ -148,28 +148,28 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin. +---------------------------------------------+--------------------+ ; Resource ; Usage ; +---------------------------------------------+--------------------+ -; Total logic elements ; 235 / 240 ( 98 % ) ; -; -- Combinational with no register ; 139 ; -; -- Register only ; 4 ; -; -- Combinational with a register ; 92 ; +; Total logic elements ; 217 / 240 ( 90 % ) ; +; -- Combinational with no register ; 122 ; +; -- Register only ; 9 ; +; -- Combinational with a register ; 86 ; ; ; ; ; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 96 ; +; -- 4 input functions ; 80 ; ; -- 3 input functions ; 45 ; -; -- 2 input functions ; 80 ; -; -- 1 input functions ; 9 ; +; -- 2 input functions ; 71 ; +; -- 1 input functions ; 11 ; ; -- 0 input functions ; 1 ; ; ; ; ; Logic elements by mode ; ; -; -- normal mode ; 177 ; +; -- normal mode ; 159 ; ; -- arithmetic mode ; 58 ; -; -- qfbk mode ; 18 ; +; -- qfbk mode ; 13 ; ; -- register cascade mode ; 0 ; -; -- synchronous clear/load mode ; 45 ; +; -- synchronous clear/load mode ; 43 ; ; -- asynchronous clear/load mode ; 0 ; ; ; ; -; Total registers ; 96 / 240 ( 40 % ) ; -; Total LABs ; 24 / 24 ( 100 % ) ; +; Total registers ; 95 / 240 ( 40 % ) ; +; Total LABs ; 23 / 24 ( 96 % ) ; ; Logic elements in carry chains ; 62 ; ; Virtual pins ; 0 ; ; I/O pins ; 68 / 80 ( 85 % ) ; @@ -179,12 +179,12 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin. ; UFM blocks ; 1 / 1 ( 100 % ) ; ; Global clocks ; 1 / 4 ( 25 % ) ; ; JTAGs ; 0 / 1 ( 0 % ) ; -; Average interconnect usage (total/H/V) ; 34% / 42% / 26% ; -; Peak interconnect usage (total/H/V) ; 34% / 42% / 26% ; -; Maximum fan-out ; 96 ; -; Highest non-global fan-out ; 31 ; -; Total fan-out ; 948 ; -; Average fan-out ; 3.12 ; +; Average interconnect usage (total/H/V) ; 24% / 25% / 23% ; +; Peak interconnect usage (total/H/V) ; 24% / 25% / 23% ; +; Maximum fan-out ; 95 ; +; Highest non-global fan-out ; 28 ; +; Total fan-out ; 856 ; +; Average fan-out ; 2.99 ; +---------------------------------------------+--------------------+ @@ -193,30 +193,30 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin. +---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+ ; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Location assigned by ; +---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+ -; C25M ; 14 ; 1 ; 1 ; 2 ; 0 ; 96 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; -; MISO ; 33 ; 1 ; 3 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; -; PHI0 ; 12 ; 1 ; 1 ; 3 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; -; RA[0] ; 30 ; 1 ; 3 ; 0 ; 3 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; -; RA[10] ; 16 ; 1 ; 1 ; 2 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; -; RA[11] ; 20 ; 1 ; 1 ; 1 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; -; RA[12] ; 1 ; 2 ; 2 ; 5 ; 3 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; -; RA[13] ; 97 ; 2 ; 3 ; 5 ; 3 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; -; RA[14] ; 36 ; 1 ; 4 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; -; RA[15] ; 95 ; 2 ; 3 ; 5 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; -; RA[1] ; 92 ; 2 ; 3 ; 5 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; -; RA[2] ; 35 ; 1 ; 3 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; -; RA[3] ; 96 ; 2 ; 3 ; 5 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; -; RA[4] ; 84 ; 2 ; 6 ; 5 ; 3 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; -; RA[5] ; 81 ; 2 ; 6 ; 5 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; -; RA[6] ; 82 ; 2 ; 6 ; 5 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; -; RA[7] ; 34 ; 1 ; 3 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; -; RA[8] ; 15 ; 1 ; 1 ; 2 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; -; RA[9] ; 17 ; 1 ; 1 ; 2 ; 3 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; -; nDEVSEL ; 77 ; 2 ; 7 ; 5 ; 2 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; +; C25M ; 14 ; 1 ; 1 ; 2 ; 0 ; 95 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; +; MISO ; 28 ; 1 ; 2 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; +; PHI0 ; 72 ; 2 ; 8 ; 4 ; 2 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; +; RA[0] ; 17 ; 1 ; 1 ; 2 ; 3 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; +; RA[10] ; 34 ; 1 ; 3 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; +; RA[11] ; 39 ; 1 ; 5 ; 0 ; 3 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; +; RA[12] ; 58 ; 2 ; 8 ; 2 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; +; RA[13] ; 57 ; 2 ; 8 ; 2 ; 3 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; +; RA[14] ; 61 ; 2 ; 8 ; 2 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; +; RA[15] ; 62 ; 2 ; 8 ; 2 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; +; RA[1] ; 38 ; 1 ; 4 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; +; RA[2] ; 16 ; 1 ; 1 ; 2 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; +; RA[3] ; 12 ; 1 ; 1 ; 3 ; 3 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; +; RA[4] ; 36 ; 1 ; 4 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; +; RA[5] ; 15 ; 1 ; 1 ; 2 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; +; RA[6] ; 91 ; 2 ; 4 ; 5 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; +; RA[7] ; 35 ; 1 ; 3 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; +; RA[8] ; 33 ; 1 ; 3 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; +; RA[9] ; 37 ; 1 ; 4 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; +; nDEVSEL ; 67 ; 2 ; 8 ; 3 ; 2 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; ; nIOSEL ; 71 ; 2 ; 8 ; 4 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; -; nIOSTRB ; 72 ; 2 ; 8 ; 4 ; 2 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; -; nRES ; 64 ; 2 ; 8 ; 3 ; 4 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; -; nWE ; 8 ; 1 ; 1 ; 3 ; 2 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; +; nIOSTRB ; 64 ; 2 ; 8 ; 3 ; 4 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; +; nRES ; 73 ; 2 ; 8 ; 4 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; +; nWE ; 74 ; 2 ; 8 ; 4 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; +---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+ @@ -225,34 +225,34 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin. +---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ ; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ; +---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ -; DQMH ; 75 ; 2 ; 7 ; 5 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; Fitter ; 10 pF ; - ; - ; -; DQML ; 76 ; 2 ; 7 ; 5 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; Fitter ; 10 pF ; - ; - ; -; FCK ; 29 ; 1 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; Fitter ; 10 pF ; - ; - ; -; MOSI ; 28 ; 1 ; 2 ; 0 ; 1 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; -; RAdir ; 78 ; 2 ; 7 ; 5 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; -; RCKE ; 66 ; 2 ; 8 ; 3 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; -; RDdir ; 100 ; 2 ; 2 ; 5 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; -; SA[0] ; 73 ; 2 ; 8 ; 4 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; -; SA[10] ; 62 ; 2 ; 8 ; 2 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; -; SA[11] ; 88 ; 2 ; 5 ; 5 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; -; SA[12] ; 70 ; 2 ; 8 ; 4 ; 4 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; -; SA[1] ; 21 ; 1 ; 1 ; 1 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; -; SA[2] ; 61 ; 2 ; 8 ; 2 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; -; SA[3] ; 39 ; 1 ; 5 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; -; SA[4] ; 74 ; 2 ; 8 ; 4 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; -; SA[5] ; 85 ; 2 ; 5 ; 5 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; -; SA[6] ; 83 ; 2 ; 6 ; 5 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; Fitter ; 10 pF ; - ; - ; -; SA[7] ; 19 ; 1 ; 1 ; 1 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; -; SA[8] ; 18 ; 1 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; -; SA[9] ; 67 ; 2 ; 8 ; 3 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; -; SBA[0] ; 43 ; 1 ; 6 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; -; SBA[1] ; 86 ; 2 ; 5 ; 5 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; -; nCAS ; 58 ; 2 ; 8 ; 2 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; -; nFCS ; 38 ; 1 ; 4 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; Fitter ; 10 pF ; - ; - ; -; nRAS ; 68 ; 2 ; 8 ; 3 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; -; nRCS ; 57 ; 2 ; 8 ; 2 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; Fitter ; 10 pF ; - ; - ; -; nRESout ; 37 ; 1 ; 4 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; -; nSWE ; 69 ; 2 ; 8 ; 3 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; DQMH ; 48 ; 1 ; 6 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; DQML ; 66 ; 2 ; 8 ; 3 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; FCK ; 30 ; 1 ; 3 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; Fitter ; 10 pF ; - ; - ; +; MOSI ; 21 ; 1 ; 1 ; 1 ; 3 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; RAdir ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; RCKE ; 70 ; 2 ; 8 ; 4 ; 4 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; RDdir ; 75 ; 2 ; 7 ; 5 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; SA[0] ; 1 ; 2 ; 2 ; 5 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; SA[10] ; 55 ; 2 ; 8 ; 1 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; SA[11] ; 42 ; 1 ; 5 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; SA[12] ; 44 ; 1 ; 6 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; SA[1] ; 100 ; 2 ; 2 ; 5 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; SA[2] ; 4 ; 1 ; 1 ; 4 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; SA[3] ; 88 ; 2 ; 5 ; 5 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; SA[4] ; 54 ; 2 ; 8 ; 1 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; SA[5] ; 77 ; 2 ; 7 ; 5 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; SA[6] ; 98 ; 2 ; 2 ; 5 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; SA[7] ; 81 ; 2 ; 6 ; 5 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; SA[8] ; 3 ; 1 ; 1 ; 4 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; SA[9] ; 52 ; 2 ; 8 ; 1 ; 4 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; SBA[0] ; 86 ; 2 ; 5 ; 5 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; SBA[1] ; 68 ; 2 ; 8 ; 3 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; nCAS ; 83 ; 2 ; 6 ; 5 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; nFCS ; 43 ; 1 ; 6 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; nRAS ; 69 ; 2 ; 8 ; 3 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; nRCS ; 84 ; 2 ; 6 ; 5 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; nRESout ; 19 ; 1 ; 1 ; 1 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; nSWE ; 82 ; 2 ; 6 ; 5 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ @@ -261,22 +261,22 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin. +-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ ; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ; +-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ -; RD[0] ; 2 ; 1 ; 1 ; 4 ; 0 ; 4 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; comb~2 (inverted) ; - ; -; RD[1] ; 7 ; 1 ; 1 ; 3 ; 1 ; 4 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; comb~2 (inverted) ; - ; -; RD[2] ; 98 ; 2 ; 2 ; 5 ; 0 ; 3 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; comb~2 (inverted) ; - ; -; RD[3] ; 3 ; 1 ; 1 ; 4 ; 1 ; 3 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; comb~2 (inverted) ; - ; -; RD[4] ; 5 ; 1 ; 1 ; 4 ; 3 ; 3 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; comb~2 (inverted) ; - ; -; RD[5] ; 99 ; 2 ; 2 ; 5 ; 1 ; 3 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; comb~2 (inverted) ; - ; -; RD[6] ; 4 ; 1 ; 1 ; 4 ; 2 ; 3 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; comb~2 (inverted) ; - ; -; RD[7] ; 6 ; 1 ; 1 ; 3 ; 0 ; 4 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; comb~2 (inverted) ; - ; -; SD[0] ; 42 ; 1 ; 5 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; SDOE ; - ; -; SD[1] ; 40 ; 1 ; 5 ; 0 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; SDOE ; - ; -; SD[2] ; 53 ; 2 ; 8 ; 1 ; 3 ; 0 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; SDOE ; - ; -; SD[3] ; 51 ; 1 ; 7 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; SDOE ; - ; -; SD[4] ; 41 ; 1 ; 5 ; 0 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; SDOE ; - ; -; SD[5] ; 52 ; 2 ; 8 ; 1 ; 4 ; 0 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; SDOE ; - ; -; SD[6] ; 27 ; 1 ; 2 ; 0 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; Fitter ; 10 pF ; SDOE ; - ; -; SD[7] ; 26 ; 1 ; 2 ; 0 ; 3 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; Fitter ; 10 pF ; SDOE ; - ; +; RD[0] ; 92 ; 2 ; 3 ; 5 ; 0 ; 3 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; comb~2 (inverted) ; - ; +; RD[1] ; 90 ; 2 ; 4 ; 5 ; 1 ; 3 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; comb~2 (inverted) ; - ; +; RD[2] ; 85 ; 2 ; 5 ; 5 ; 0 ; 3 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; comb~2 (inverted) ; - ; +; RD[3] ; 96 ; 2 ; 3 ; 5 ; 2 ; 3 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; comb~2 (inverted) ; - ; +; RD[4] ; 95 ; 2 ; 3 ; 5 ; 1 ; 3 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; comb~2 (inverted) ; - ; +; RD[5] ; 97 ; 2 ; 3 ; 5 ; 3 ; 3 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; comb~2 (inverted) ; - ; +; RD[6] ; 89 ; 2 ; 4 ; 5 ; 0 ; 3 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; comb~2 (inverted) ; - ; +; RD[7] ; 87 ; 2 ; 5 ; 5 ; 2 ; 4 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; comb~2 (inverted) ; - ; +; SD[0] ; 29 ; 1 ; 2 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; SDOE ; - ; +; SD[1] ; 8 ; 1 ; 1 ; 3 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; SDOE ; - ; +; SD[2] ; 27 ; 1 ; 2 ; 0 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; SDOE ; - ; +; SD[3] ; 26 ; 1 ; 2 ; 0 ; 3 ; 0 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; Fitter ; 10 pF ; SDOE ; - ; +; SD[4] ; 7 ; 1 ; 1 ; 3 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; SDOE ; - ; +; SD[5] ; 6 ; 1 ; 1 ; 3 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; SDOE ; - ; +; SD[6] ; 18 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; Fitter ; 10 pF ; SDOE ; - ; +; SD[7] ; 20 ; 1 ; 1 ; 1 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; Fitter ; 10 pF ; SDOE ; - ; +-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ @@ -285,8 +285,8 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin. +----------+------------------+---------------+--------------+ ; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; +----------+------------------+---------------+--------------+ -; 1 ; 33 / 38 ( 87 % ) ; 3.3V ; -- ; -; 2 ; 35 / 42 ( 83 % ) ; 3.3V ; -- ; +; 1 ; 31 / 38 ( 82 % ) ; 3.3V ; -- ; +; 2 ; 37 / 42 ( 88 % ) ; 3.3V ; -- ; +----------+------------------+---------------+--------------+ @@ -295,106 +295,106 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin. +----------+------------+----------+----------------+--------+--------------+-----------+------------+-----------------+----------+--------------+ ; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; +----------+------------+----------+----------------+--------+--------------+-----------+------------+-----------------+----------+--------------+ -; 1 ; 83 ; 2 ; RA[12] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; -; 2 ; 0 ; 1 ; RD[0] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 3 ; 1 ; 1 ; RD[3] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 4 ; 2 ; 1 ; RD[6] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 5 ; 3 ; 1 ; RD[4] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 6 ; 4 ; 1 ; RD[7] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 7 ; 5 ; 1 ; RD[1] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 8 ; 6 ; 1 ; nWE ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 1 ; 83 ; 2 ; SA[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 2 ; 0 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 3 ; 1 ; 1 ; SA[8] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 4 ; 2 ; 1 ; SA[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 5 ; 3 ; 1 ; RAdir ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 6 ; 4 ; 1 ; SD[5] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 7 ; 5 ; 1 ; SD[4] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 8 ; 6 ; 1 ; SD[1] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; ; 9 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; 10 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; ; 11 ; ; ; GNDINT ; gnd ; ; ; -- ; ; -- ; -- ; -; 12 ; 7 ; 1 ; PHI0 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 12 ; 7 ; 1 ; RA[3] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; ; 13 ; ; ; VCCINT ; power ; ; 2.5V/3.3V ; -- ; ; -- ; -- ; ; 14 ; 8 ; 1 ; C25M ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 15 ; 9 ; 1 ; RA[8] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 16 ; 10 ; 1 ; RA[10] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 17 ; 11 ; 1 ; RA[9] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 18 ; 12 ; 1 ; SA[8] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 19 ; 13 ; 1 ; SA[7] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 20 ; 14 ; 1 ; RA[11] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 21 ; 15 ; 1 ; SA[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 15 ; 9 ; 1 ; RA[5] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 16 ; 10 ; 1 ; RA[2] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 17 ; 11 ; 1 ; RA[0] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 18 ; 12 ; 1 ; SD[6] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 19 ; 13 ; 1 ; nRESout ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 20 ; 14 ; 1 ; SD[7] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 21 ; 15 ; 1 ; MOSI ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; ; 22 ; 16 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ; ; 23 ; 17 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ; ; 24 ; 18 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ; ; 25 ; 19 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ; -; 26 ; 20 ; 1 ; SD[7] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; -; 27 ; 21 ; 1 ; SD[6] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; -; 28 ; 22 ; 1 ; MOSI ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; -; 29 ; 23 ; 1 ; FCK ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; -; 30 ; 24 ; 1 ; RA[0] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 26 ; 20 ; 1 ; SD[3] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 27 ; 21 ; 1 ; SD[2] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 28 ; 22 ; 1 ; MISO ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 29 ; 23 ; 1 ; SD[0] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 30 ; 24 ; 1 ; FCK ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; ; 31 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; 32 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; -; 33 ; 25 ; 1 ; MISO ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; -; 34 ; 26 ; 1 ; RA[7] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; -; 35 ; 27 ; 1 ; RA[2] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; -; 36 ; 28 ; 1 ; RA[14] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; -; 37 ; 29 ; 1 ; nRESout ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; -; 38 ; 30 ; 1 ; nFCS ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; -; 39 ; 31 ; 1 ; SA[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; -; 40 ; 32 ; 1 ; SD[1] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; -; 41 ; 33 ; 1 ; SD[4] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; -; 42 ; 34 ; 1 ; SD[0] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; -; 43 ; 35 ; 1 ; SBA[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; -; 44 ; 36 ; 1 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 33 ; 25 ; 1 ; RA[8] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 34 ; 26 ; 1 ; RA[10] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 35 ; 27 ; 1 ; RA[7] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 36 ; 28 ; 1 ; RA[4] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 37 ; 29 ; 1 ; RA[9] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 38 ; 30 ; 1 ; RA[1] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 39 ; 31 ; 1 ; RA[11] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 40 ; 32 ; 1 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 41 ; 33 ; 1 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 42 ; 34 ; 1 ; SA[11] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 43 ; 35 ; 1 ; nFCS ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 44 ; 36 ; 1 ; SA[12] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; ; 45 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; 46 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; ; 47 ; 37 ; 1 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 48 ; 38 ; 1 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 48 ; 38 ; 1 ; DQMH ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; ; 49 ; 39 ; 1 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; 50 ; 40 ; 1 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 51 ; 41 ; 1 ; SD[3] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; -; 52 ; 42 ; 2 ; SD[5] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 53 ; 43 ; 2 ; SD[2] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 54 ; 44 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 55 ; 45 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 51 ; 41 ; 1 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 52 ; 42 ; 2 ; SA[9] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 53 ; 43 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 54 ; 44 ; 2 ; SA[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 55 ; 45 ; 2 ; SA[10] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; ; 56 ; 46 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 57 ; 47 ; 2 ; nRCS ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 58 ; 48 ; 2 ; nCAS ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 57 ; 47 ; 2 ; RA[13] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 58 ; 48 ; 2 ; RA[12] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; ; 59 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; 60 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; -; 61 ; 49 ; 2 ; SA[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 62 ; 50 ; 2 ; SA[10] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 61 ; 49 ; 2 ; RA[14] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 62 ; 50 ; 2 ; RA[15] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; ; 63 ; ; ; VCCINT ; power ; ; 2.5V/3.3V ; -- ; ; -- ; -- ; -; 64 ; 51 ; 2 ; nRES ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 64 ; 51 ; 2 ; nIOSTRB ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; ; 65 ; ; ; GNDINT ; gnd ; ; ; -- ; ; -- ; -- ; -; 66 ; 52 ; 2 ; RCKE ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 67 ; 53 ; 2 ; SA[9] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 68 ; 54 ; 2 ; nRAS ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 69 ; 55 ; 2 ; nSWE ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 70 ; 56 ; 2 ; SA[12] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 66 ; 52 ; 2 ; DQML ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 67 ; 53 ; 2 ; nDEVSEL ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 68 ; 54 ; 2 ; SBA[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 69 ; 55 ; 2 ; nRAS ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 70 ; 56 ; 2 ; RCKE ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; ; 71 ; 57 ; 2 ; nIOSEL ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 72 ; 58 ; 2 ; nIOSTRB ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 73 ; 59 ; 2 ; SA[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 74 ; 60 ; 2 ; SA[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 75 ; 61 ; 2 ; DQMH ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; -; 76 ; 62 ; 2 ; DQML ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; -; 77 ; 63 ; 2 ; nDEVSEL ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; -; 78 ; 64 ; 2 ; RAdir ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 72 ; 58 ; 2 ; PHI0 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 73 ; 59 ; 2 ; nRES ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 74 ; 60 ; 2 ; nWE ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 75 ; 61 ; 2 ; RDdir ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 76 ; 62 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 77 ; 63 ; 2 ; SA[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 78 ; 64 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; 79 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; ; 80 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 81 ; 65 ; 2 ; RA[5] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; -; 82 ; 66 ; 2 ; RA[6] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; -; 83 ; 67 ; 2 ; SA[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; -; 84 ; 68 ; 2 ; RA[4] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; -; 85 ; 69 ; 2 ; SA[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; -; 86 ; 70 ; 2 ; SBA[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; -; 87 ; 71 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 88 ; 72 ; 2 ; SA[11] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; -; 89 ; 73 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 90 ; 74 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 91 ; 75 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 92 ; 76 ; 2 ; RA[1] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 81 ; 65 ; 2 ; SA[7] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 82 ; 66 ; 2 ; nSWE ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 83 ; 67 ; 2 ; nCAS ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 84 ; 68 ; 2 ; nRCS ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 85 ; 69 ; 2 ; RD[2] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 86 ; 70 ; 2 ; SBA[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 87 ; 71 ; 2 ; RD[7] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 88 ; 72 ; 2 ; SA[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 89 ; 73 ; 2 ; RD[6] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 90 ; 74 ; 2 ; RD[1] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 91 ; 75 ; 2 ; RA[6] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 92 ; 76 ; 2 ; RD[0] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; ; 93 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; ; 94 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 95 ; 77 ; 2 ; RA[15] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; -; 96 ; 78 ; 2 ; RA[3] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; -; 97 ; 79 ; 2 ; RA[13] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; -; 98 ; 80 ; 2 ; RD[2] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; -; 99 ; 81 ; 2 ; RD[5] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; -; 100 ; 82 ; 2 ; RDdir ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 95 ; 77 ; 2 ; RD[4] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 96 ; 78 ; 2 ; RD[3] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 97 ; 79 ; 2 ; RD[5] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 98 ; 80 ; 2 ; SA[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 99 ; 81 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 100 ; 82 ; 2 ; SA[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +----------+------------+----------+----------------+--------+--------------+-----------+------------+-----------------+----------+--------------+ Note: Pin directions (input, output or bidir) are based on device operating in user mode. @@ -420,7 +420,7 @@ Note: User assignments will override these defaults. The user specified values a +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+ ; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ; +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+ -; |GR8RAM ; 235 (235) ; 96 ; 1 ; 68 ; 0 ; 139 (139) ; 4 (4) ; 92 (92) ; 62 (62) ; 18 (18) ; |GR8RAM ; work ; +; |GR8RAM ; 217 (217) ; 95 ; 1 ; 68 ; 0 ; 122 (122) ; 9 (9) ; 86 (86) ; 62 (62) ; 13 (13) ; |GR8RAM ; work ; ; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |GR8RAM|UFM:UFM_inst ; work ; ; |UFM_altufm_none_0ep:UFM_altufm_none_0ep_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |GR8RAM|UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component ; work ; +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+ @@ -438,22 +438,22 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; nIOSTRB ; Input ; (1) ; ; nIOSEL ; Input ; (1) ; ; C25M ; Input ; (0) ; -; RA[1] ; Input ; (1) ; -; RA[10] ; Input ; (1) ; -; RA[2] ; Input ; (1) ; -; RA[11] ; Input ; (1) ; -; RA[3] ; Input ; (1) ; -; RA[4] ; Input ; (1) ; -; RA[5] ; Input ; (1) ; -; RA[6] ; Input ; (1) ; -; RA[7] ; Input ; (1) ; -; RA[8] ; Input ; (1) ; -; RA[9] ; Input ; (1) ; ; RA[0] ; Input ; (1) ; +; RA[10] ; Input ; (1) ; +; RA[7] ; Input ; (1) ; +; RA[1] ; Input ; (1) ; +; RA[9] ; Input ; (1) ; +; RA[8] ; Input ; (1) ; +; RA[6] ; Input ; (1) ; +; RA[5] ; Input ; (1) ; +; RA[4] ; Input ; (1) ; +; RA[3] ; Input ; (1) ; +; RA[2] ; Input ; (1) ; ; RA[14] ; Input ; (1) ; ; RA[15] ; Input ; (1) ; ; RA[12] ; Input ; (1) ; ; RA[13] ; Input ; (1) ; +; RA[11] ; Input ; (1) ; ; nRES ; Input ; (1) ; ; MISO ; Input ; (1) ; ; nRESout ; Output ; -- ; @@ -508,18 +508,16 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +-------------+-------------+---------+---------------+--------+----------------------+------------------+ ; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; +-------------+-------------+---------+---------------+--------+----------------------+------------------+ -; ARCLK~8 ; LC_X7_Y1_N9 ; 2 ; Clock enable ; no ; -- ; -- ; -; Addr[19]~16 ; LC_X4_Y3_N1 ; 7 ; Clock enable ; no ; -- ; -- ; -; Addr[4]~4 ; LC_X4_Y3_N2 ; 8 ; Clock enable ; no ; -- ; -- ; -; Addr[8]~2 ; LC_X4_Y3_N7 ; 8 ; Clock enable ; no ; -- ; -- ; -; Bank[1]~1 ; LC_X2_Y3_N2 ; 2 ; Clock enable ; no ; -- ; -- ; -; C25M ; PIN_14 ; 96 ; Clock ; yes ; Global Clock ; GCLK1 ; -; DRCLK~3 ; LC_X7_Y1_N5 ; 2 ; Clock enable ; no ; -- ; -- ; -; MOSIOE ; LC_X3_Y1_N9 ; 3 ; Output enable ; no ; -- ; -- ; -; PSStart~1 ; LC_X7_Y3_N4 ; 16 ; Clock enable ; no ; -- ; -- ; -; SDOE ; LC_X2_Y1_N0 ; 8 ; Output enable ; no ; -- ; -- ; -; always17~0 ; LC_X2_Y1_N4 ; 2 ; Clock enable ; no ; -- ; -- ; -; nRESr ; LC_X7_Y3_N1 ; 31 ; Sync. clear ; no ; -- ; -- ; +; Addr[0]~8 ; LC_X3_Y2_N8 ; 8 ; Clock enable ; no ; -- ; -- ; +; Addr[13]~11 ; LC_X5_Y2_N2 ; 8 ; Clock enable ; no ; -- ; -- ; +; Addr[17]~7 ; LC_X5_Y2_N3 ; 7 ; Clock enable ; no ; -- ; -- ; +; C25M ; PIN_14 ; 95 ; Clock ; yes ; Global Clock ; GCLK1 ; +; MOSIOE ; LC_X6_Y2_N7 ; 4 ; Output enable ; no ; -- ; -- ; +; PSStart~1 ; LC_X7_Y4_N5 ; 16 ; Clock enable ; no ; -- ; -- ; +; SDOE ; LC_X2_Y1_N8 ; 8 ; Output enable ; no ; -- ; -- ; +; SS[0]~4 ; LC_X4_Y1_N1 ; 2 ; Clock enable ; no ; -- ; -- ; +; always18~0 ; LC_X2_Y1_N3 ; 2 ; Clock enable ; no ; -- ; -- ; +; nRESr ; LC_X7_Y4_N4 ; 28 ; Sync. clear ; no ; -- ; -- ; +-------------+-------------+---------+---------------+--------+----------------------+------------------+ @@ -528,403 +526,378 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +------+----------+---------+----------------------+------------------+ ; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; +------+----------+---------+----------------------+------------------+ -; C25M ; PIN_14 ; 96 ; Global Clock ; GCLK1 ; +; C25M ; PIN_14 ; 95 ; Global Clock ; GCLK1 ; +------+----------+---------+----------------------+------------------+ -+---------------------------------+ -; Non-Global High Fan-Out Signals ; -+-------------------+-------------+ -; Name ; Fan-Out ; -+-------------------+-------------+ -; nRESr ; 31 ; -; RAMSpecSEL~4 ; 19 ; -; Amux[1] ; 19 ; -; Amux[0] ; 18 ; -; Amux[2] ; 17 ; -; PSStart~1 ; 16 ; -; PS[1] ; 15 ; -; PS[0] ; 15 ; -; RAcur[0] ; 14 ; -; PS[2] ; 12 ; -; Addr[19]~10 ; 11 ; -; Addr[4]~3 ; 11 ; -; always10~0 ; 11 ; -; LS[1] ; 10 ; -; LS[4] ; 9 ; -; comb~2 ; 9 ; -; SDOE ; 8 ; -; Addr[4]~4 ; 8 ; -; Addr[8]~2 ; 8 ; -; LS[6] ; 8 ; -; LS[5] ; 8 ; -; nRESout~reg0 ; 8 ; -; Addr[19]~16 ; 7 ; -; LS[3] ; 7 ; -; RAMSpecSEL~1 ; 6 ; -; Equal5~0 ; 6 ; -; SetLoaded ; 5 ; -; Add1~112 ; 5 ; -; Add2~47 ; 5 ; -; nWEcur ; 5 ; -; Add1~57 ; 5 ; -; Add2~22 ; 5 ; -; Add1~42 ; 5 ; -; RAMSpecSEL~3 ; 5 ; -; Add1~2 ; 5 ; -; LS[8]~29 ; 5 ; -; LS[15] ; 5 ; -; LS[14] ; 5 ; -; LS[13] ; 5 ; -; LS[12] ; 5 ; -; LS[2] ; 5 ; -; LS[3]~1 ; 5 ; -; Equal43~1 ; 5 ; -; RD[7]~7 ; 4 ; -; RD[1]~1 ; 4 ; -; RD[0]~0 ; 4 ; -; Equal10~0 ; 4 ; -; Addr[22] ; 4 ; -; Addr[21] ; 4 ; -; Addr[20] ; 4 ; -; Addr[19] ; 4 ; -; Addr[18] ; 4 ; -; Addr[17] ; 4 ; -; Addr[16] ; 4 ; -; RAcur[1] ; 4 ; -; LS[13]~21 ; 4 ; -; LS[0] ; 4 ; -; Addr[7] ; 4 ; -; Addr[15] ; 4 ; -; RD[6]~6 ; 3 ; -; RD[5]~5 ; 3 ; -; RD[4]~4 ; 3 ; -; RD[3]~3 ; 3 ; -; RD[2]~2 ; 3 ; -; ARCLK~6 ; 3 ; -; MOSIOE ; 3 ; -; Mux0~0 ; 3 ; -; Add3~17 ; 3 ; -; Add2~57 ; 3 ; -; always10~1 ; 3 ; -; RAcur[2] ; 3 ; -; RAcur[3] ; 3 ; -; RACr ; 3 ; -; LS[10] ; 3 ; -; LS[9] ; 3 ; -; LS[8] ; 3 ; -; LS[7] ; 3 ; -; DRCLK~0 ; 3 ; -; ARCLK~0 ; 3 ; -; LS[11] ; 3 ; -; LS[17] ; 3 ; -; LS[16] ; 3 ; -; Addr[9] ; 3 ; -; Addr[8] ; 3 ; -; Addr[14] ; 3 ; -; Addr[13] ; 3 ; -; Addr[12] ; 3 ; -; Addr[11] ; 3 ; -; Addr[10] ; 3 ; -; REGEN ; 3 ; -; nIOSEL ; 2 ; -; nIOSTRB ; 2 ; -; nDEVSEL ; 2 ; -; nWE ; 2 ; -; PHI0 ; 2 ; -; always17~0 ; 2 ; -; ARCLK~8 ; 2 ; -; DRCLK~3 ; 2 ; -; DRCLK~2 ; 2 ; -; ARCLK~3 ; 2 ; -; MOSIout ; 2 ; -; FCKEN ; 2 ; -; Equal12~0 ; 2 ; -; FCS~0 ; 2 ; -; Equal10~1 ; 2 ; -; MOSIout~1 ; 2 ; -; ARCLK~2 ; 2 ; -; Mux0~4 ; 2 ; -; Mux0~3 ; 2 ; -; Mux2~0 ; 2 ; -; RefReqd ; 2 ; -; Add1~97 ; 2 ; -; Bank[1]~1 ; 2 ; -; DEVSELr ; 2 ; -; RAcur[7] ; 2 ; -; RAMSpecSEL~2 ; 2 ; -; ROMSpecRD ; 2 ; -; RAcur[10] ; 2 ; -; always9~3 ; 2 ; -; always9~0 ; 2 ; -; RAMSpecSEL~0 ; 2 ; -; IOSELr ; 2 ; -; Equal0~3 ; 2 ; -; Equal0~1 ; 2 ; -; FCS ; 2 ; -; RCKE~reg0 ; 2 ; -; DQML~1 ; 2 ; -; DQML~0 ; 2 ; -; Addr[0] ; 2 ; -; RAcur[9] ; 2 ; -; RAcur[8] ; 2 ; -; Addr[6] ; 2 ; -; Addr[5] ; 2 ; -; Addr[4] ; 2 ; -; Addr[3] ; 2 ; -; Addr[2] ; 2 ; -; Addr[1] ; 2 ; -; IOROMEN ; 2 ; -; MISO ; 1 ; -; nRES ; 1 ; -; RA[13] ; 1 ; -; RA[12] ; 1 ; -; RA[15] ; 1 ; -; RA[14] ; 1 ; -; RA[0] ; 1 ; -; RA[9] ; 1 ; -; RA[8] ; 1 ; -; RA[7] ; 1 ; -; RA[6] ; 1 ; -; RA[5] ; 1 ; -; RA[4] ; 1 ; -; RA[3] ; 1 ; -; RA[11] ; 1 ; -; RA[2] ; 1 ; -; RA[10] ; 1 ; -; RA[1] ; 1 ; -; ~GND ; 1 ; -; WRD[7] ; 1 ; -; WRD[6] ; 1 ; -; Equal37~0 ; 1 ; -; MOSIout~3 ; 1 ; -; MOSIout~2 ; 1 ; -; Equal13~0 ; 1 ; -; DEVSELr0 ; 1 ; -; nRESr0 ; 1 ; -; IOSTRBr0 ; 1 ; -; IOSELr0 ; 1 ; -; PHI0r0 ; 1 ; -; ARCLK~5 ; 1 ; -; ARCLK~4 ; 1 ; -; DRShift~0 ; 1 ; -; FCS~1 ; 1 ; -; MOSIout~0 ; 1 ; -; ARCLK~1 ; 1 ; -; Add1~110 ; 1 ; -; Mux2~1 ; 1 ; -; Equal5~1 ; 1 ; -; Mux0~2 ; 1 ; -; Mux0~1 ; 1 ; -; Add1~105 ; 1 ; -; Addr~29 ; 1 ; -; Add2~70 ; 1 ; -; Add3~30 ; 1 ; -; Add1~102COUT1_166 ; 1 ; -; Add1~102 ; 1 ; -; Add1~100 ; 1 ; -; Addr~27 ; 1 ; -; Add3~27COUT1_50 ; 1 ; -; Add3~27 ; 1 ; -; Add3~25 ; 1 ; -; Add2~67COUT1_108 ; 1 ; -; Add2~67 ; 1 ; -; Add2~65 ; 1 ; -; Add1~95 ; 1 ; -; Addr~25 ; 1 ; -; Add2~62COUT1_106 ; 1 ; -; Add2~62 ; 1 ; -; Add2~60 ; 1 ; -; Add3~22COUT1_48 ; 1 ; -; Add3~22 ; 1 ; -; Add3~20 ; 1 ; -; Add1~92COUT1_164 ; 1 ; -; Add1~92 ; 1 ; -; Add1~90 ; 1 ; -; Addr~23 ; 1 ; -; Add3~15 ; 1 ; -; Add2~55 ; 1 ; -; Add1~87COUT1_162 ; 1 ; -; Add1~87 ; 1 ; -; Add1~85 ; 1 ; -; Addr~21 ; 1 ; -; Add2~52COUT1_104 ; 1 ; -; Add2~52 ; 1 ; -; Add2~50 ; 1 ; -; Add3~12COUT1_46 ; 1 ; -; Add3~12 ; 1 ; -; Add3~10 ; 1 ; -; Add1~82COUT1_148 ; 1 ; -; Add1~82 ; 1 ; -; Add1~80 ; 1 ; -; Addr~20 ; 1 ; -; Add2~45 ; 1 ; -; Add1~77COUT1_160 ; 1 ; -; Add1~77 ; 1 ; -; Add1~75 ; 1 ; -; Addr~18 ; 1 ; -; Add3~7COUT1_44 ; 1 ; -; Add3~7 ; 1 ; -; Add3~5 ; 1 ; -; Add2~42COUT1_102 ; 1 ; -; Add2~42 ; 1 ; -; Add2~40 ; 1 ; -; Add1~72COUT1_146 ; 1 ; -; Add1~72 ; 1 ; -; Add1~70 ; 1 ; -; Addr~17 ; 1 ; -; Add2~37COUT1_88 ; 1 ; -; Add2~37 ; 1 ; -; Add2~35 ; 1 ; -; Addr[19]~15 ; 1 ; -; Addr[19]~14 ; 1 ; -; Addr[19]~13 ; 1 ; -; Add1~67COUT1_158 ; 1 ; -; Add1~67 ; 1 ; -; Add1~65 ; 1 ; -; Addr~11 ; 1 ; -; Add2~32COUT1_100 ; 1 ; -; Add2~32 ; 1 ; -; Add2~30 ; 1 ; -; Add3~2COUT1_42 ; 1 ; -; Add3~2 ; 1 ; -; Add3~0 ; 1 ; -; Add1~62COUT1_144 ; 1 ; -; Add1~62 ; 1 ; -; Add1~60 ; 1 ; -; Add1~55 ; 1 ; -; Addr~9 ; 1 ; -; Add2~27COUT1_98 ; 1 ; -; Add2~27 ; 1 ; -; Add2~25 ; 1 ; -; Add1~52COUT1_142 ; 1 ; -; Add1~52 ; 1 ; -; Add1~50 ; 1 ; -; Add1~47COUT1_156 ; 1 ; -; Add1~47 ; 1 ; -; Add1~45 ; 1 ; -; Addr~8 ; 1 ; -; Add2~20 ; 1 ; -; Add1~40 ; 1 ; -; Add1~37COUT1_140 ; 1 ; -; Add1~37 ; 1 ; -; Add1~35 ; 1 ; -; Add1~32COUT1_154 ; 1 ; -; Add1~32 ; 1 ; -; Add1~30 ; 1 ; -; Addr~7 ; 1 ; -; Add2~17COUT1_96 ; 1 ; -; Add2~17 ; 1 ; -; Add2~15 ; 1 ; -; Add1~27COUT1_138 ; 1 ; -; Add1~27 ; 1 ; -; Add1~25 ; 1 ; -; Add1~22COUT1_152 ; 1 ; -; Add1~22 ; 1 ; -; Add1~20 ; 1 ; -; Addr~6 ; 1 ; -; Add2~12COUT1_94 ; 1 ; -; Add2~12 ; 1 ; -; Add2~10 ; 1 ; -; Add1~17COUT1_136 ; 1 ; -; Add1~17 ; 1 ; -; Add1~15 ; 1 ; -; Add1~12COUT1_150 ; 1 ; -; Add1~12 ; 1 ; -; Add1~10 ; 1 ; -; Addr~5 ; 1 ; -; Add2~7COUT1_92 ; 1 ; -; Add2~7 ; 1 ; -; Add2~5 ; 1 ; -; Add1~7COUT1_134 ; 1 ; -; Add1~7 ; 1 ; -; Add1~5 ; 1 ; -; Addr[8]~1 ; 1 ; -; Add1~0 ; 1 ; -; Addr~0 ; 1 ; -; Add2~2COUT1_90 ; 1 ; -; Add2~2 ; 1 ; -; Add2~0 ; 1 ; -; PHI0r1 ; 1 ; -; PSStart~0 ; 1 ; -; RAcur[4] ; 1 ; -; always9~2 ; 1 ; -; always9~1 ; 1 ; -; Equal0~2 ; 1 ; -; LS[10]~33COUT1_64 ; 1 ; -; LS[10]~33 ; 1 ; -; LS[9]~31COUT1_62 ; 1 ; -; LS[9]~31 ; 1 ; -; LS[7]~27COUT1_60 ; 1 ; -; LS[7]~27 ; 1 ; -; LS[15]~25COUT1_72 ; 1 ; -; LS[15]~25 ; 1 ; -; LS[14]~23COUT1_70 ; 1 ; -; LS[14]~23 ; 1 ; -; LS[12]~19COUT1_68 ; 1 ; -; LS[12]~19 ; 1 ; -; LS[6]~17COUT1_58 ; 1 ; -; LS[6]~17 ; 1 ; -; LS[5]~15COUT1_56 ; 1 ; -; LS[5]~15 ; 1 ; -; LS[4]~13COUT1_54 ; 1 ; -; LS[4]~13 ; 1 ; -; LS[2]~11COUT1_52 ; 1 ; -; LS[2]~11 ; 1 ; -; Equal0~0 ; 1 ; -; LS[11]~9COUT1_66 ; 1 ; -; LS[11]~9 ; 1 ; -; LS[16]~5COUT1_74 ; 1 ; -; LS[16]~5 ; 1 ; -; LS[1]~3COUT1_50 ; 1 ; -; LS[1]~3 ; 1 ; -; ARShift ; 1 ; -; ARCLK ; 1 ; -; DRShift ; 1 ; -; DRCLK ; 1 ; -; FCK~reg0 ; 1 ; -; DQMH~0 ; 1 ; -; DQML~2 ; 1 ; -; nSWE~reg0 ; 1 ; -; nCAS~reg0 ; 1 ; -; nRAS~reg0 ; 1 ; -; nRCS~reg0 ; 1 ; -; SA~25 ; 1 ; -; SA~24 ; 1 ; -; SA~23 ; 1 ; -; SA~22 ; 1 ; -; SA~21 ; 1 ; -; SA~20 ; 1 ; -; SA~19 ; 1 ; -; SA~18 ; 1 ; -; SA~17 ; 1 ; -; SA~16 ; 1 ; -; SA~15 ; 1 ; -; RAcur[6] ; 1 ; -; SA~14 ; 1 ; -; SA~13 ; 1 ; -; RAcur[5] ; 1 ; -; SA~12 ; 1 ; -; SA~11 ; 1 ; -; SA~10 ; 1 ; -; SA~9 ; 1 ; -; Bank[1] ; 1 ; -; SA~8 ; 1 ; -; SA~7 ; 1 ; -; SA~6 ; 1 ; -; Bank[0] ; 1 ; -; SA~5 ; 1 ; -; SA~4 ; 1 ; -; RAcur[11] ; 1 ; -; SA~3 ; 1 ; -; SA~2 ; 1 ; -; SA~1 ; 1 ; -; SA~0 ; 1 ; -; Equal43~0 ; 1 ; -; PHI0r2 ; 1 ; -; comb~1 ; 1 ; -; comb~0 ; 1 ; -+-------------------+-------------+ ++-------------------------------------------------------------------------------------------------------+ +; Non-Global High Fan-Out Signals ; ++---------------------------------------------------------------------------------------------+---------+ +; Name ; Fan-Out ; ++---------------------------------------------------------------------------------------------+---------+ +; nRESr ; 28 ; +; RAMSpecSEL~2 ; 23 ; +; PSStart~1 ; 16 ; +; RAcur[0] ; 15 ; +; PS[1] ; 15 ; +; PS[0] ; 15 ; +; PS[2] ; 13 ; +; LS[1] ; 12 ; +; Addr[17]~1 ; 11 ; +; Addr[17]~0 ; 11 ; +; always10~0 ; 11 ; +; LS[3] ; 10 ; +; comb~2 ; 9 ; +; SDOE ; 8 ; +; Addr[13]~11 ; 8 ; +; Addr[0]~8 ; 8 ; +; LS[5] ; 8 ; +; LS[2] ; 8 ; +; nRESout~reg0 ; 8 ; +; Addr[17]~7 ; 7 ; +; LS[0] ; 7 ; +; SS[1] ; 6 ; +; Equal40~1 ; 6 ; +; LS[6] ; 6 ; +; LS[4] ; 6 ; +; Add2~67 ; 5 ; +; Add1~97 ; 5 ; +; Add1~47 ; 5 ; +; Add2~22 ; 5 ; +; Add1~22 ; 5 ; +; SS[0] ; 5 ; +; MOSIout~1 ; 5 ; +; Add1~7 ; 5 ; +; LS[8]~31 ; 5 ; +; LS[12] ; 5 ; +; LS[3]~1 ; 5 ; +; Amux[2] ; 5 ; +; RD[7]~7 ; 4 ; +; DRShift~0 ; 4 ; +; MOSIOE ; 4 ; +; nWEcur ; 4 ; +; Addr[22] ; 4 ; +; RAcur[1] ; 4 ; +; LS[15] ; 4 ; +; LS[14] ; 4 ; +; LS[13]~9 ; 4 ; +; LS[13] ; 4 ; +; Amux[1] ; 4 ; +; RD[6]~6 ; 3 ; +; RD[5]~5 ; 3 ; +; RD[4]~4 ; 3 ; +; RD[3]~3 ; 3 ; +; RD[2]~2 ; 3 ; +; RD[1]~1 ; 3 ; +; RD[0]~0 ; 3 ; +; Addr[16] ; 3 ; +; Addr[17] ; 3 ; +; Addr[18] ; 3 ; +; Addr[19] ; 3 ; +; Addr[20] ; 3 ; +; Add2~27 ; 3 ; +; Add3~17 ; 3 ; +; Addr[21] ; 3 ; +; Equal12~0 ; 3 ; +; Equal40~3 ; 3 ; +; Mux0~0 ; 3 ; +; always10~1 ; 3 ; +; Addr[15] ; 3 ; +; Addr[7] ; 3 ; +; RAMSpecSEL~0 ; 3 ; +; RACr ; 3 ; +; RAcur[2] ; 3 ; +; Equal5~0 ; 3 ; +; LS[8] ; 3 ; +; LS[11] ; 3 ; +; LS[10] ; 3 ; +; LS[9] ; 3 ; +; LS[16] ; 3 ; +; FCS~0 ; 3 ; +; LS[7] ; 3 ; +; LS[17] ; 3 ; +; REGEN ; 3 ; +; nIOSEL ; 2 ; +; nIOSTRB ; 2 ; +; nDEVSEL ; 2 ; +; nWE ; 2 ; +; PHI0 ; 2 ; +; Addr[8] ; 2 ; +; Addr[9] ; 2 ; +; Addr[10] ; 2 ; +; Addr[11] ; 2 ; +; Addr[12] ; 2 ; +; Addr[13] ; 2 ; +; Addr[14] ; 2 ; +; always18~0 ; 2 ; +; Add1~27 ; 2 ; +; SS[0]~4 ; 2 ; +; Equal41~1 ; 2 ; +; Equal41~0 ; 2 ; +; Equal40~4 ; 2 ; +; Equal36~0 ; 2 ; +; MOSIout ; 2 ; +; FCKEN ; 2 ; +; Equal11~0 ; 2 ; +; FCS~1 ; 2 ; +; Equal9~0 ; 2 ; +; Mux0~4 ; 2 ; +; Mux0~3 ; 2 ; +; Mux2~0 ; 2 ; +; RefReqd ; 2 ; +; Equal5~1 ; 2 ; +; RAcur[3] ; 2 ; +; RAMSpecSEL~1 ; 2 ; +; ROMSpecRD ; 2 ; +; always9~3 ; 2 ; +; RAcur[8] ; 2 ; +; RAcur[9] ; 2 ; +; RAcur[7] ; 2 ; +; IOSELr ; 2 ; +; Equal0~3 ; 2 ; +; Equal40~0 ; 2 ; +; FCS ; 2 ; +; RCKE~reg0 ; 2 ; +; DQML~1 ; 2 ; +; DQML~0 ; 2 ; +; Addr[0] ; 2 ; +; Amux[0] ; 2 ; +; IOROMEN ; 2 ; +; MISO ; 1 ; +; nRES ; 1 ; +; RA[11] ; 1 ; +; RA[13] ; 1 ; +; RA[12] ; 1 ; +; RA[15] ; 1 ; +; RA[14] ; 1 ; +; RA[2] ; 1 ; +; RA[3] ; 1 ; +; RA[4] ; 1 ; +; RA[5] ; 1 ; +; RA[6] ; 1 ; +; RA[8] ; 1 ; +; RA[9] ; 1 ; +; RA[1] ; 1 ; +; RA[7] ; 1 ; +; RA[10] ; 1 ; +; RA[0] ; 1 ; +; ~GND ; 1 ; +; Addr~30 ; 1 ; +; Addr~29 ; 1 ; +; Add1~112COUT1_146 ; 1 ; +; Add1~112 ; 1 ; +; Add1~110 ; 1 ; +; Add2~72COUT1_88 ; 1 ; +; Add2~72 ; 1 ; +; Add2~70 ; 1 ; +; Addr~28 ; 1 ; +; Addr[1] ; 1 ; +; Addr~26 ; 1 ; +; Add1~107COUT1_148 ; 1 ; +; Add1~107 ; 1 ; +; Add1~105 ; 1 ; +; Add2~65 ; 1 ; +; Addr~25 ; 1 ; +; Add1~102COUT1_134 ; 1 ; +; Add1~102 ; 1 ; +; Add1~100 ; 1 ; +; Addr[2] ; 1 ; +; Addr~23 ; 1 ; +; Add1~95 ; 1 ; +; Add2~62COUT1_90 ; 1 ; +; Add2~62 ; 1 ; +; Add2~60 ; 1 ; +; Addr~22 ; 1 ; +; Add1~92COUT1_136 ; 1 ; +; Add1~92 ; 1 ; +; Add1~90 ; 1 ; +; Addr[3] ; 1 ; +; Add1~87COUT1_158 ; 1 ; +; Add1~87 ; 1 ; +; Add1~85 ; 1 ; +; Add2~57COUT1_100 ; 1 ; +; Add2~57 ; 1 ; +; Add2~55 ; 1 ; +; Add3~32COUT1_42 ; 1 ; +; Add3~32 ; 1 ; +; Add3~30 ; 1 ; +; Addr~20 ; 1 ; +; Add1~82COUT1_150 ; 1 ; +; Add1~82 ; 1 ; +; Add1~80 ; 1 ; +; Add2~52COUT1_92 ; 1 ; +; Add2~52 ; 1 ; +; Add2~50 ; 1 ; +; Addr~19 ; 1 ; +; Add1~77COUT1_138 ; 1 ; +; Add1~77 ; 1 ; +; Add1~75 ; 1 ; +; Addr[4] ; 1 ; +; Add1~72COUT1_160 ; 1 ; +; Add1~72 ; 1 ; +; Add1~70 ; 1 ; +; Add2~47COUT1_102 ; 1 ; +; Add2~47 ; 1 ; +; Add2~45 ; 1 ; +; Add3~27COUT1_44 ; 1 ; +; Add3~27 ; 1 ; +; Add3~25 ; 1 ; +; Addr~17 ; 1 ; +; Add1~67COUT1_152 ; 1 ; +; Add1~67 ; 1 ; +; Add1~65 ; 1 ; +; Add2~42COUT1_94 ; 1 ; +; Add2~42 ; 1 ; +; Add2~40 ; 1 ; +; Addr~16 ; 1 ; +; Add1~62COUT1_140 ; 1 ; +; Add1~62 ; 1 ; +; Add1~60 ; 1 ; +; Addr[5] ; 1 ; +; Add1~57COUT1_162 ; 1 ; +; Add1~57 ; 1 ; +; Add1~55 ; 1 ; +; Add2~37COUT1_104 ; 1 ; +; Add2~37 ; 1 ; +; Add2~35 ; 1 ; +; Add3~22COUT1_46 ; 1 ; +; Add3~22 ; 1 ; +; Add3~20 ; 1 ; +; Addr~14 ; 1 ; +; Add1~52COUT1_154 ; 1 ; +; Add1~52 ; 1 ; +; Add1~50 ; 1 ; +; Add2~32COUT1_96 ; 1 ; +; Add2~32 ; 1 ; +; Add2~30 ; 1 ; +; Add1~45 ; 1 ; +; Addr[6] ; 1 ; +; Add1~42COUT1_164 ; 1 ; +; Add1~42 ; 1 ; +; Add1~40 ; 1 ; +; Add2~25 ; 1 ; +; Add3~15 ; 1 ; +; Addr~12 ; 1 ; +; Add1~37COUT1_156 ; 1 ; +; Add1~37 ; 1 ; +; Add1~35 ; 1 ; +; Add2~20 ; 1 ; +; Add1~32COUT1_142 ; 1 ; +; Add1~32 ; 1 ; +; Add1~30 ; 1 ; +; Add1~25 ; 1 ; +; Add2~17COUT1_106 ; 1 ; +; Add2~17 ; 1 ; +; Add2~15 ; 1 ; +; Add3~12COUT1_48 ; 1 ; +; Add3~12 ; 1 ; +; Add3~10 ; 1 ; +; SS[0]~3 ; 1 ; +; SS[0]~2 ; 1 ; +; Equal40~5 ; 1 ; +; SS[0]~1 ; 1 ; +; SS[0]~0 ; 1 ; +; WRD[7] ; 1 ; +; WRD[6] ; 1 ; +; MOSIOE~0 ; 1 ; +; MOSIout~4 ; 1 ; +; MOSIout~3 ; 1 ; +; MOSIout~2 ; 1 ; +; Equal12~1 ; 1 ; +; DEVSELr0 ; 1 ; +; Addr[13]~10 ; 1 ; +; Add1~20 ; 1 ; +; Addr~9 ; 1 ; +; Add2~12COUT1_98 ; 1 ; +; Add2~12 ; 1 ; +; Add2~10 ; 1 ; +; Add1~17COUT1_144 ; 1 ; +; Add1~17 ; 1 ; +; Add1~15 ; 1 ; +; Add1~12COUT1_166 ; 1 ; +; Add1~12 ; 1 ; +; Add1~10 ; 1 ; +; Add2~7COUT1_108 ; 1 ; +; Add2~7 ; 1 ; +; Add2~5 ; 1 ; +; Add3~7COUT1_50 ; 1 ; +; Add3~7 ; 1 ; +; Add3~5 ; 1 ; +; nRESr0 ; 1 ; +; IOSTRBr0 ; 1 ; +; IOSELr0 ; 1 ; +; PHI0r0 ; 1 ; +; DRShift~1 ; 1 ; +; FCS~2 ; 1 ; +; MOSIout~0 ; 1 ; +; Equal40~2 ; 1 ; +; Add1~5 ; 1 ; +; Mux2~1 ; 1 ; +; PHI0r1 ; 1 ; +; PSStart~0 ; 1 ; +; Mux0~2 ; 1 ; +; Mux0~1 ; 1 ; +; DEVSELr ; 1 ; +; Addr[17]~6 ; 1 ; +; Addr[17]~5 ; 1 ; +; Addr[17]~4 ; 1 ; +; Add1~0 ; 1 ; +; Addr~2 ; 1 ; +; Add2~0 ; 1 ; +; always9~4 ; 1 ; +; Add3~0 ; 1 ; +; always9~2 ; 1 ; +; always9~1 ; 1 ; +; RAcur[5] ; 1 ; +; RAcur[10] ; 1 ; +; always9~0 ; 1 ; +; Equal0~2 ; 1 ; +; LS[5]~33COUT1_56 ; 1 ; +; LS[5]~33 ; 1 ; +; Equal0~1 ; 1 ; +; LS[11]~29COUT1_66 ; 1 ; +; LS[11]~29 ; 1 ; +; LS[10]~27COUT1_64 ; 1 ; +; LS[10]~27 ; 1 ; +; LS[9]~25COUT1_62 ; 1 ; +; LS[9]~25 ; 1 ; +; LS[16]~23COUT1_74 ; 1 ; +; LS[16]~23 ; 1 ; +; LS[6]~21COUT1_58 ; 1 ; +; LS[6]~21 ; 1 ; +; LS[4]~19COUT1_54 ; 1 ; +; LS[4]~19 ; 1 ; +; Equal0~0 ; 1 ; +; LS[2]~17COUT1_52 ; 1 ; +; LS[2]~17 ; 1 ; +; LS[7]~15COUT1_60 ; 1 ; +; LS[7]~15 ; 1 ; +; LS[15]~13COUT1_72 ; 1 ; +; LS[15]~13 ; 1 ; +; LS[14]~11COUT1_70 ; 1 ; +; LS[14]~11 ; 1 ; +; LS[12]~7COUT1_68 ; 1 ; +; LS[12]~7 ; 1 ; +; LS[1]~3COUT1_50 ; 1 ; +; LS[1]~3 ; 1 ; +; ARShift ; 1 ; +; ARCLK ; 1 ; +; DRShift ; 1 ; +; DRCLK ; 1 ; +; FCK~reg0 ; 1 ; +; DQMH~0 ; 1 ; +; DQML~2 ; 1 ; +; nSWE~reg0 ; 1 ; +; nCAS~reg0 ; 1 ; +; nRAS~reg0 ; 1 ; +; nRCS~reg0 ; 1 ; +; Equal53~0 ; 1 ; +; Equal49~0 ; 1 ; +; PHI0r2 ; 1 ; +; comb~1 ; 1 ; +; comb~0 ; 1 ; +; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|wire_maxii_ufm_block1_drdout ; 1 ; ++---------------------------------------------------------------------------------------------+---------+ +--------------------------------------------------+ @@ -932,97 +905,92 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +-----------------------------+--------------------+ ; Other Routing Resource Type ; Usage ; +-----------------------------+--------------------+ -; C4s ; 171 / 784 ( 22 % ) ; -; Direct links ; 69 / 888 ( 8 % ) ; +; C4s ; 148 / 784 ( 19 % ) ; +; Direct links ; 67 / 888 ( 8 % ) ; ; Global clocks ; 1 / 4 ( 25 % ) ; ; LAB clocks ; 6 / 32 ( 19 % ) ; -; LUT chains ; 19 / 216 ( 9 % ) ; -; Local interconnects ; 400 / 888 ( 45 % ) ; -; R4s ; 245 / 704 ( 35 % ) ; +; LUT chains ; 22 / 216 ( 10 % ) ; +; Local interconnects ; 327 / 888 ( 37 % ) ; +; R4s ; 147 / 704 ( 21 % ) ; +-----------------------------+--------------------+ +---------------------------------------------------------------------------+ ; LAB Logic Elements ; +--------------------------------------------+------------------------------+ -; Number of Logic Elements (Average = 9.79) ; Number of LABs (Total = 24) ; +; Number of Logic Elements (Average = 9.43) ; Number of LABs (Total = 23) ; +--------------------------------------------+------------------------------+ ; 1 ; 0 ; ; 2 ; 0 ; ; 3 ; 0 ; -; 4 ; 0 ; +; 4 ; 1 ; ; 5 ; 0 ; ; 6 ; 0 ; ; 7 ; 1 ; -; 8 ; 0 ; +; 8 ; 1 ; ; 9 ; 2 ; -; 10 ; 21 ; +; 10 ; 18 ; +--------------------------------------------+------------------------------+ +-------------------------------------------------------------------+ ; LAB-wide Signals ; +------------------------------------+------------------------------+ -; LAB-wide Signals (Average = 1.79) ; Number of LABs (Total = 24) ; +; LAB-wide Signals (Average = 1.83) ; Number of LABs (Total = 23) ; +------------------------------------+------------------------------+ -; 1 Clock ; 22 ; -; 1 Clock enable ; 8 ; +; 1 Clock ; 21 ; +; 1 Clock enable ; 10 ; ; 1 Sync. clear ; 10 ; -; 2 Clock enables ; 3 ; +; 2 Clock enables ; 1 ; +------------------------------------+------------------------------+ -+-----------------------------------------------------------------------------+ -; LAB Signals Sourced ; -+----------------------------------------------+------------------------------+ -; Number of Signals Sourced (Average = 10.50) ; Number of LABs (Total = 24) ; -+----------------------------------------------+------------------------------+ -; 0 ; 0 ; -; 1 ; 0 ; -; 2 ; 0 ; -; 3 ; 0 ; -; 4 ; 0 ; -; 5 ; 0 ; -; 6 ; 0 ; -; 7 ; 1 ; -; 8 ; 0 ; -; 9 ; 2 ; -; 10 ; 17 ; -; 11 ; 0 ; -; 12 ; 0 ; -; 13 ; 1 ; -; 14 ; 2 ; -; 15 ; 0 ; -; 16 ; 1 ; -+----------------------------------------------+------------------------------+ ++----------------------------------------------------------------------------+ +; LAB Signals Sourced ; ++---------------------------------------------+------------------------------+ +; Number of Signals Sourced (Average = 9.83) ; Number of LABs (Total = 23) ; ++---------------------------------------------+------------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 1 ; +; 6 ; 0 ; +; 7 ; 1 ; +; 8 ; 1 ; +; 9 ; 2 ; +; 10 ; 15 ; +; 11 ; 1 ; +; 12 ; 0 ; +; 13 ; 1 ; +; 14 ; 1 ; ++---------------------------------------------+------------------------------+ +--------------------------------------------------------------------------------+ ; LAB Signals Sourced Out ; +-------------------------------------------------+------------------------------+ -; Number of Signals Sourced Out (Average = 7.63) ; Number of LABs (Total = 24) ; +; Number of Signals Sourced Out (Average = 7.17) ; Number of LABs (Total = 23) ; +-------------------------------------------------+------------------------------+ ; 0 ; 0 ; ; 1 ; 0 ; -; 2 ; 0 ; +; 2 ; 1 ; ; 3 ; 0 ; -; 4 ; 2 ; -; 5 ; 1 ; -; 6 ; 4 ; -; 7 ; 5 ; -; 8 ; 5 ; +; 4 ; 1 ; +; 5 ; 3 ; +; 6 ; 2 ; +; 7 ; 6 ; +; 8 ; 4 ; ; 9 ; 2 ; ; 10 ; 4 ; -; 11 ; 0 ; -; 12 ; 0 ; -; 13 ; 1 ; +-------------------------------------------------+------------------------------+ +-----------------------------------------------------------------------------+ ; LAB Distinct Inputs ; +----------------------------------------------+------------------------------+ -; Number of Distinct Inputs (Average = 15.25) ; Number of LABs (Total = 24) ; +; Number of Distinct Inputs (Average = 13.04) ; Number of LABs (Total = 23) ; +----------------------------------------------+------------------------------+ ; 0 ; 0 ; ; 1 ; 0 ; @@ -1030,22 +998,22 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; 3 ; 0 ; ; 4 ; 0 ; ; 5 ; 1 ; -; 6 ; 0 ; -; 7 ; 0 ; +; 6 ; 1 ; +; 7 ; 1 ; ; 8 ; 0 ; -; 9 ; 0 ; -; 10 ; 1 ; -; 11 ; 1 ; -; 12 ; 2 ; -; 13 ; 1 ; +; 9 ; 1 ; +; 10 ; 3 ; +; 11 ; 2 ; +; 12 ; 0 ; +; 13 ; 0 ; ; 14 ; 2 ; -; 15 ; 2 ; -; 16 ; 3 ; -; 17 ; 1 ; -; 18 ; 2 ; -; 19 ; 1 ; -; 20 ; 3 ; -; 21 ; 3 ; +; 15 ; 0 ; +; 16 ; 5 ; +; 17 ; 2 ; +; 18 ; 1 ; +; 19 ; 2 ; +; 20 ; 0 ; +; 21 ; 1 ; +----------------------------------------------+------------------------------+ @@ -1130,32 +1098,34 @@ Critical Warning (169085): No exact pin location assignment(s) for 68 pins of 68 Info (169086): Pin nIOSTRB not assigned to an exact location on the device Info (169086): Pin nIOSEL not assigned to an exact location on the device Info (169086): Pin C25M not assigned to an exact location on the device - Info (169086): Pin RA[1] not assigned to an exact location on the device - Info (169086): Pin RA[10] not assigned to an exact location on the device - Info (169086): Pin RA[2] not assigned to an exact location on the device - Info (169086): Pin RA[11] not assigned to an exact location on the device - Info (169086): Pin RA[3] not assigned to an exact location on the device - Info (169086): Pin RA[4] not assigned to an exact location on the device - Info (169086): Pin RA[5] not assigned to an exact location on the device - Info (169086): Pin RA[6] not assigned to an exact location on the device - Info (169086): Pin RA[7] not assigned to an exact location on the device - Info (169086): Pin RA[8] not assigned to an exact location on the device - Info (169086): Pin RA[9] not assigned to an exact location on the device Info (169086): Pin RA[0] not assigned to an exact location on the device + Info (169086): Pin RA[10] not assigned to an exact location on the device + Info (169086): Pin RA[7] not assigned to an exact location on the device + Info (169086): Pin RA[1] not assigned to an exact location on the device + Info (169086): Pin RA[9] not assigned to an exact location on the device + Info (169086): Pin RA[8] not assigned to an exact location on the device + Info (169086): Pin RA[6] not assigned to an exact location on the device + Info (169086): Pin RA[5] not assigned to an exact location on the device + Info (169086): Pin RA[4] not assigned to an exact location on the device + Info (169086): Pin RA[3] not assigned to an exact location on the device + Info (169086): Pin RA[2] not assigned to an exact location on the device Info (169086): Pin RA[14] not assigned to an exact location on the device Info (169086): Pin RA[15] not assigned to an exact location on the device Info (169086): Pin RA[12] not assigned to an exact location on the device Info (169086): Pin RA[13] not assigned to an exact location on the device + Info (169086): Pin RA[11] not assigned to an exact location on the device Info (169086): Pin nRES not assigned to an exact location on the device Info (169086): Pin MISO not assigned to an exact location on the device Critical Warning (332012): Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. Info (332144): No user constrained base clocks found in the design Info (332128): Timing requirements not specified -- optimizing circuit to achieve the following default global requirements Info (332127): Assuming a default timing requirement -Info (332111): Found 1 clocks +Info (332111): Found 3 clocks Info (332111): Period Clock Name Info (332111): ======== ============ + Info (332111): 1.000 ARCLK Info (332111): 1.000 C25M + Info (332111): 1.000 DRCLK Info (186079): Completed User Assigned Global Signals Promotion Operation Info (186215): Automatically promoted signal "C25M" to use Global clock in PIN 14 Info (186079): Completed Auto Global Promotion Operation @@ -1178,18 +1148,18 @@ Info (170191): Fitter placement operations beginning Info (170137): Fitter placement was successful Info (170192): Fitter placement operations ending: elapsed time is 00:00:03 Info (170193): Fitter routing operations beginning -Info (170195): Router estimated average interconnect usage is 27% of the available device resources - Info (170196): Router estimated peak interconnect usage is 27% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5 +Info (170195): Router estimated average interconnect usage is 19% of the available device resources + Info (170196): Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5 Info (170194): Fitter routing operations ending: elapsed time is 00:00:01 -Info (11888): Total time spent on timing analysis during the Fitter is 0.39 seconds. +Info (11888): Total time spent on timing analysis during the Fitter is 0.52 seconds. Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00 Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'. Info (144001): Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg Info: Quartus II 32-bit Fitter was successful. 0 errors, 4 warnings - Info: Peak virtual memory: 373 megabytes - Info: Processing ended: Fri Mar 19 07:33:11 2021 - Info: Elapsed time: 00:00:10 - Info: Total CPU time (on all processors): 00:00:09 + Info: Peak virtual memory: 376 megabytes + Info: Processing ended: Fri Mar 19 16:35:25 2021 + Info: Elapsed time: 00:00:09 + Info: Total CPU time (on all processors): 00:00:08 +----------------------------+ diff --git a/cpld/output_files/GR8RAM.fit.summary b/cpld/output_files/GR8RAM.fit.summary index c11276c..9e6df38 100755 --- a/cpld/output_files/GR8RAM.fit.summary +++ b/cpld/output_files/GR8RAM.fit.summary @@ -1,11 +1,11 @@ -Fitter Status : Successful - Fri Mar 19 07:33:10 2021 +Fitter Status : Successful - Fri Mar 19 16:35:25 2021 Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition Revision Name : GR8RAM Top-level Entity Name : GR8RAM Family : MAX II Device : EPM240T100C5 Timing Models : Final -Total logic elements : 235 / 240 ( 98 % ) +Total logic elements : 217 / 240 ( 90 % ) Total pins : 68 / 80 ( 85 % ) Total virtual pins : 0 UFM blocks : 1 / 1 ( 100 % ) diff --git a/cpld/output_files/GR8RAM.flow.rpt b/cpld/output_files/GR8RAM.flow.rpt index 4563710..d4a3c25 100755 --- a/cpld/output_files/GR8RAM.flow.rpt +++ b/cpld/output_files/GR8RAM.flow.rpt @@ -1,5 +1,5 @@ Flow report for GR8RAM -Fri Mar 19 07:33:22 2021 +Fri Mar 19 16:35:37 2021 Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition @@ -40,14 +40,14 @@ applicable agreement for further details. +-----------------------------------------------------------------------------+ ; Flow Summary ; +---------------------------+-------------------------------------------------+ -; Flow Status ; Successful - Fri Mar 19 07:33:15 2021 ; +; Flow Status ; Successful - Fri Mar 19 16:35:30 2021 ; ; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; ; Revision Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ; ; Family ; MAX II ; ; Device ; EPM240T100C5 ; ; Timing Models ; Final ; -; Total logic elements ; 235 / 240 ( 98 % ) ; +; Total logic elements ; 217 / 240 ( 90 % ) ; ; Total pins ; 68 / 80 ( 85 % ) ; ; Total virtual pins ; 0 ; ; UFM blocks ; 1 / 1 ( 100 % ) ; @@ -59,28 +59,37 @@ applicable agreement for further details. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 03/19/2021 07:32:56 ; +; Start date & time ; 03/19/2021 16:35:10 ; ; Main task ; Compilation ; ; Revision Name ; GR8RAM ; +-------------------+---------------------+ -+-------------------------------------------------------------------------------------------------------------------+ -; Flow Non-Default Global Settings ; -+---------------------------------------+--------------------------------+---------------+-------------+------------+ -; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; -+---------------------------------------+--------------------------------+---------------+-------------+------------+ -; COMPILER_SIGNATURE_ID ; 44085571633675.161615357603936 ; -- ; -- ; -- ; -; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ; -; IP_TOOL_NAME ; ALTUFM_NONE ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 13.0 ; -- ; -- ; -- ; -; MAXII_OPTIMIZATION_TECHNIQUE ; Area ; Balanced ; -- ; -- ; -; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; -; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; -; POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR ; 3.3V ; -- ; -- ; -- ; -; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; -; SYNTH_TIMING_DRIVEN_SYNTHESIS ; Off ; -- ; -- ; -- ; -+---------------------------------------+--------------------------------+---------------+-------------+------------+ ++-----------------------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++-------------------------------------------------+--------------------------------+---------------+-------------+------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++-------------------------------------------------+--------------------------------+---------------+-------------+------------+ +; ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ; On ; Off ; -- ; -- ; +; ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES ; Always ; Auto ; -- ; -- ; +; ALM_REGISTER_PACKING_EFFORT ; High ; Medium ; -- ; -- ; +; AUTO_RESOURCE_SHARING ; On ; Off ; -- ; -- ; +; COMPILER_SIGNATURE_ID ; 44085571633675.161618611002356 ; -- ; -- ; -- ; +; FINAL_PLACEMENT_OPTIMIZATION ; Always ; Automatically ; -- ; -- ; +; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ; +; IP_TOOL_NAME ; ALTUFM_NONE ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 13.0 ; -- ; -- ; -- ; +; MAXII_OPTIMIZATION_TECHNIQUE ; Area ; Balanced ; -- ; -- ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; PLACEMENT_EFFORT_MULTIPLIER ; 2.0 ; 1.0 ; -- ; -- ; +; POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR ; 3.3V ; -- ; -- ; -- ; +; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; +; REMOVE_REDUNDANT_LOGIC_CELLS ; On ; Off ; -- ; -- ; +; ROUTER_EFFORT_MULTIPLIER ; 2.0 ; 1.0 ; -- ; -- ; +; SAFE_STATE_MACHINE ; On ; Off ; -- ; -- ; +; SYNTH_TIMING_DRIVEN_SYNTHESIS ; Off ; -- ; -- ; -- ; ++-------------------------------------------------+--------------------------------+---------------+-------------+------------+ +-------------------------------------------------------------------------------------------------------------------------------+ @@ -88,11 +97,11 @@ applicable agreement for further details. +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:05 ; 1.0 ; 301 MB ; 00:00:05 ; -; Fitter ; 00:00:09 ; 1.3 ; 373 MB ; 00:00:08 ; +; Analysis & Synthesis ; 00:00:05 ; 1.0 ; 301 MB ; 00:00:04 ; +; Fitter ; 00:00:09 ; 1.5 ; 376 MB ; 00:00:08 ; ; Assembler ; 00:00:02 ; 1.0 ; 292 MB ; 00:00:02 ; -; TimeQuest Timing Analyzer ; 00:00:04 ; 1.0 ; 275 MB ; 00:00:05 ; -; Total ; 00:00:20 ; -- ; -- ; 00:00:20 ; +; TimeQuest Timing Analyzer ; 00:00:04 ; 1.0 ; 275 MB ; 00:00:04 ; +; Total ; 00:00:20 ; -- ; -- ; 00:00:18 ; +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ diff --git a/cpld/output_files/GR8RAM.jdi b/cpld/output_files/GR8RAM.jdi index c9b4840..723609f 100755 --- a/cpld/output_files/GR8RAM.jdi +++ b/cpld/output_files/GR8RAM.jdi @@ -1,6 +1,6 @@ - + diff --git a/cpld/output_files/GR8RAM.map.rpt b/cpld/output_files/GR8RAM.map.rpt index 8ee9a02..ea83aff 100755 --- a/cpld/output_files/GR8RAM.map.rpt +++ b/cpld/output_files/GR8RAM.map.rpt @@ -1,5 +1,5 @@ Analysis & Synthesis report for GR8RAM -Fri Mar 19 07:32:59 2021 +Fri Mar 19 16:35:14 2021 Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition @@ -47,12 +47,12 @@ applicable agreement for further details. +-------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +-----------------------------+-------------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Fri Mar 19 07:32:59 2021 ; +; Analysis & Synthesis Status ; Successful - Fri Mar 19 16:35:14 2021 ; ; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; ; Revision Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ; ; Family ; MAX II ; -; Total logic elements ; 260 ; +; Total logic elements ; 237 ; ; Total pins ; 68 ; ; Total virtual pins ; 0 ; ; UFM blocks ; 1 / 1 ( 100 % ) ; @@ -67,7 +67,12 @@ applicable agreement for further details. ; Device ; EPM240T100C5 ; ; ; Top-level entity name ; GR8RAM ; GR8RAM ; ; Family name ; MAX II ; Cyclone IV GX ; +; Safe State Machine ; On ; Off ; +; Remove Redundant Logic Cells ; On ; Off ; ; Optimization Technique ; Area ; Balanced ; +; Perform WYSIWYG Primitive Resynthesis ; On ; Off ; +; Allow Shift Register Merging across Hierarchies ; Always ; Auto ; +; Auto Resource Sharing ; On ; Off ; ; Use smart compilation ; Off ; Off ; ; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; ; Enable compact report table ; Off ; Off ; @@ -78,7 +83,6 @@ applicable agreement for further details. ; Verilog Version ; Verilog_2001 ; Verilog_2001 ; ; VHDL Version ; VHDL_1993 ; VHDL_1993 ; ; State Machine Processing ; Auto ; Auto ; -; Safe State Machine ; Off ; Off ; ; Extract Verilog State Machines ; On ; On ; ; Extract VHDL State Machines ; On ; On ; ; Ignore Verilog initial constructs ; Off ; Off ; @@ -89,7 +93,6 @@ applicable agreement for further details. ; Parallel Synthesis ; On ; On ; ; NOT Gate Push-Back ; On ; On ; ; Power-Up Don't Care ; On ; On ; -; Remove Redundant Logic Cells ; Off ; Off ; ; Remove Duplicate Registers ; On ; On ; ; Ignore CARRY Buffers ; Off ; Off ; ; Ignore CASCADE Buffers ; Off ; Off ; @@ -101,13 +104,10 @@ applicable agreement for further details. ; Carry Chain Length ; 70 ; 70 ; ; Auto Carry Chains ; On ; On ; ; Auto Open-Drain Pins ; On ; On ; -; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; ; Auto Shift Register Replacement ; Auto ; Auto ; -; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; ; Auto Clock Enable Replacement ; On ; On ; ; Allow Synchronous Control Signals ; On ; On ; ; Force Use of Synchronous Clear Signals ; Off ; Off ; -; Auto Resource Sharing ; Off ; Off ; ; Use LogicLock Constraints during Resource Balancing ; On ; On ; ; Ignore translate_off and synthesis_off directives ; Off ; Off ; ; Report Parameter Settings ; On ; On ; @@ -164,34 +164,34 @@ applicable agreement for further details. +---------------------------------------------+-------+ ; Resource ; Usage ; +---------------------------------------------+-------+ -; Total logic elements ; 260 ; -; -- Combinational with no register ; 164 ; +; Total logic elements ; 237 ; +; -- Combinational with no register ; 142 ; ; -- Register only ; 29 ; -; -- Combinational with a register ; 67 ; +; -- Combinational with a register ; 66 ; ; ; ; ; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 96 ; +; -- 4 input functions ; 80 ; ; -- 3 input functions ; 45 ; -; -- 2 input functions ; 80 ; -; -- 1 input functions ; 9 ; +; -- 2 input functions ; 71 ; +; -- 1 input functions ; 11 ; ; -- 0 input functions ; 1 ; ; ; ; ; Logic elements by mode ; ; -; -- normal mode ; 202 ; +; -- normal mode ; 179 ; ; -- arithmetic mode ; 58 ; ; -- qfbk mode ; 0 ; ; -- register cascade mode ; 0 ; ; -- synchronous clear/load mode ; 25 ; ; -- asynchronous clear/load mode ; 0 ; ; ; ; -; Total registers ; 96 ; +; Total registers ; 95 ; ; Total logic cells in carry chains ; 62 ; ; I/O pins ; 68 ; ; UFM blocks ; 1 ; ; Maximum fan-out node ; C25M ; -; Maximum fan-out ; 96 ; -; Total fan-out ; 933 ; -; Average fan-out ; 2.84 ; +; Maximum fan-out ; 95 ; +; Total fan-out ; 836 ; +; Average fan-out ; 2.73 ; +---------------------------------------------+-------+ @@ -200,7 +200,7 @@ applicable agreement for further details. +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+ ; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ; +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+ -; |GR8RAM ; 260 (260) ; 96 ; 1 ; 68 ; 0 ; 164 (164) ; 29 (29) ; 67 (67) ; 62 (62) ; 0 (0) ; |GR8RAM ; work ; +; |GR8RAM ; 237 (237) ; 95 ; 1 ; 68 ; 0 ; 142 (142) ; 29 (29) ; 66 (66) ; 62 (62) ; 0 (0) ; |GR8RAM ; work ; ; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |GR8RAM|UFM:UFM_inst ; work ; ; |UFM_altufm_none_0ep:UFM_altufm_none_0ep_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |GR8RAM|UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component ; work ; +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+ @@ -243,12 +243,12 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +----------------------------------------------+-------+ ; Statistic ; Value ; +----------------------------------------------+-------+ -; Total registers ; 96 ; +; Total registers ; 95 ; ; Number of registers using Synchronous Clear ; 25 ; ; Number of registers using Synchronous Load ; 0 ; ; Number of registers using Asynchronous Clear ; 0 ; ; Number of registers using Asynchronous Load ; 0 ; -; Number of registers using Clock Enable ; 45 ; +; Number of registers using Clock Enable ; 41 ; ; Number of registers using Preset ; 0 ; +----------------------------------------------+-------+ @@ -273,15 +273,11 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ ; 3:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; Yes ; |GR8RAM|PS[0] ; -; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |GR8RAM|Bank[1] ; -; 5:1 ; 8 bits ; 24 LEs ; 16 LEs ; 8 LEs ; Yes ; |GR8RAM|Addr[4] ; -; 7:1 ; 8 bits ; 32 LEs ; 16 LEs ; 16 LEs ; Yes ; |GR8RAM|Addr[8] ; -; 13:1 ; 2 bits ; 16 LEs ; 12 LEs ; 4 LEs ; Yes ; |GR8RAM|DRCLK ; -; 9:1 ; 8 bits ; 48 LEs ; 24 LEs ; 24 LEs ; Yes ; |GR8RAM|Addr[19] ; -; 8:1 ; 2 bits ; 10 LEs ; 6 LEs ; 4 LEs ; No ; |GR8RAM|SA ; -; 8:1 ; 5 bits ; 25 LEs ; 15 LEs ; 10 LEs ; No ; |GR8RAM|SA ; -; 8:1 ; 4 bits ; 20 LEs ; 12 LEs ; 8 LEs ; No ; |GR8RAM|SA ; -; 8:1 ; 2 bits ; 10 LEs ; 6 LEs ; 4 LEs ; No ; |GR8RAM|DQMH ; +; 5:1 ; 8 bits ; 24 LEs ; 16 LEs ; 8 LEs ; Yes ; |GR8RAM|Addr[0] ; +; 6:1 ; 2 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |GR8RAM|SS[0] ; +; 7:1 ; 8 bits ; 32 LEs ; 16 LEs ; 16 LEs ; Yes ; |GR8RAM|Addr[13] ; +; 9:1 ; 8 bits ; 48 LEs ; 24 LEs ; 24 LEs ; Yes ; |GR8RAM|Addr[17] ; +; 8:1 ; 2 bits ; 10 LEs ; 6 LEs ; 4 LEs ; No ; |GR8RAM|DQML ; +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ @@ -304,7 +300,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi Info: ******************************************************************* Info: Running Quartus II 32-bit Analysis & Synthesis Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - Info: Processing started: Fri Mar 19 07:32:54 2021 + Info: Processing started: Fri Mar 19 16:35:09 2021 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected Info (12021): Found 2 design units, including 2 entities, in source file ufm.v @@ -316,33 +312,48 @@ Warning (10236): Verilog HDL Implicit Net warning at gr8ram.v(223): created impl Warning (10236): Verilog HDL Implicit Net warning at gr8ram.v(226): created implicit net for "RTPB" Info (12127): Elaborating entity "GR8RAM" for the top level hierarchy Warning (10858): Verilog HDL warning at gr8ram.v(86): object RDout used but never assigned +Warning (10036): Verilog HDL or VHDL warning at gr8ram.v(118): object "Bank" assigned a value but never read Warning (10036): Verilog HDL or VHDL warning at gr8ram.v(228): object "UFMBr" assigned a value but never read Warning (10036): Verilog HDL or VHDL warning at gr8ram.v(230): object "RTPBr" assigned a value but never read -Warning (10036): Verilog HDL or VHDL warning at gr8ram.v(332): object "RefReady" assigned a value but never read +Warning (10036): Verilog HDL or VHDL warning at gr8ram.v(335): object "RefReady" assigned a value but never read Warning (10230): Verilog HDL assignment warning at gr8ram.v(24): truncated value with size 32 to match size of target (18) Warning (10230): Verilog HDL assignment warning at gr8ram.v(100): truncated value with size 32 to match size of target (24) Warning (10230): Verilog HDL assignment warning at gr8ram.v(104): truncated value with size 32 to match size of target (16) Warning (10230): Verilog HDL assignment warning at gr8ram.v(109): truncated value with size 32 to match size of target (8) -Warning (10230): Verilog HDL assignment warning at gr8ram.v(327): truncated value with size 32 to match size of target (3) +Warning (10230): Verilog HDL assignment warning at gr8ram.v(330): truncated value with size 32 to match size of target (3) Warning (10030): Net "RDout" at gr8ram.v(86) has no driver or initial value, using a default initial value '0' -Warning (10030): Net "WRD[5..0]" at gr8ram.v(312) has no driver or initial value, using a default initial value '0' +Warning (10030): Net "WRD[5..0]" at gr8ram.v(315) has no driver or initial value, using a default initial value '0' +Warning (10034): Output port "SA[11..0]" at gr8ram.v(347) has no driver Info (12128): Elaborating entity "UFM" for hierarchy "UFM:UFM_inst" Info (12128): Elaborating entity "UFM_altufm_none_0ep" for hierarchy "UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component" +Info (17026): Resynthesizing 0 WYSIWYG logic cells and I/Os using "area" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched Warning (13046): Tri-state node(s) do not directly drive top-level pin(s) Warning (13047): Converted the fan-out from the tri-state buffer "MOSI" to the node "WRD[6]" into an OR gate Warning (13024): Output pins are stuck at VCC or GND Warning (13410): Pin "RAdir" is stuck at VCC Warning (13410): Pin "SBA[0]" is stuck at GND -Info (21057): Implemented 329 device resources after synthesis - the final resource count might be different + Warning (13410): Pin "SA[0]" is stuck at GND + Warning (13410): Pin "SA[1]" is stuck at GND + Warning (13410): Pin "SA[2]" is stuck at GND + Warning (13410): Pin "SA[3]" is stuck at GND + Warning (13410): Pin "SA[4]" is stuck at GND + Warning (13410): Pin "SA[5]" is stuck at GND + Warning (13410): Pin "SA[6]" is stuck at GND + Warning (13410): Pin "SA[7]" is stuck at GND + Warning (13410): Pin "SA[8]" is stuck at GND + Warning (13410): Pin "SA[9]" is stuck at GND + Warning (13410): Pin "SA[10]" is stuck at GND + Warning (13410): Pin "SA[11]" is stuck at GND +Info (21057): Implemented 306 device resources after synthesis - the final resource count might be different Info (21058): Implemented 24 input pins Info (21059): Implemented 28 output pins Info (21060): Implemented 16 bidirectional pins - Info (21061): Implemented 260 logic cells + Info (21061): Implemented 237 logic cells Info (21070): Implemented 1 User Flash Memory blocks Info (144001): Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg -Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 19 warnings +Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 33 warnings Info: Peak virtual memory: 301 megabytes - Info: Processing ended: Fri Mar 19 07:32:59 2021 + Info: Processing ended: Fri Mar 19 16:35:14 2021 Info: Elapsed time: 00:00:05 Info: Total CPU time (on all processors): 00:00:05 diff --git a/cpld/output_files/GR8RAM.map.smsg b/cpld/output_files/GR8RAM.map.smsg index a19806b..a65a837 100755 --- a/cpld/output_files/GR8RAM.map.smsg +++ b/cpld/output_files/GR8RAM.map.smsg @@ -1,4 +1,4 @@ Warning (10463): Verilog HDL Declaration warning at UFM.v(72): "program" is SystemVerilog-2005 keyword Warning (10463): Verilog HDL Declaration warning at UFM.v(188): "program" is SystemVerilog-2005 keyword Warning (10273): Verilog HDL warning at gr8ram.v(85): extended using "x" or "z" -Warning (10273): Verilog HDL warning at gr8ram.v(311): extended using "x" or "z" +Warning (10273): Verilog HDL warning at gr8ram.v(314): extended using "x" or "z" diff --git a/cpld/output_files/GR8RAM.map.summary b/cpld/output_files/GR8RAM.map.summary index da0abaa..67c5a86 100755 --- a/cpld/output_files/GR8RAM.map.summary +++ b/cpld/output_files/GR8RAM.map.summary @@ -1,9 +1,9 @@ -Analysis & Synthesis Status : Successful - Fri Mar 19 07:32:59 2021 +Analysis & Synthesis Status : Successful - Fri Mar 19 16:35:14 2021 Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition Revision Name : GR8RAM Top-level Entity Name : GR8RAM Family : MAX II -Total logic elements : 260 +Total logic elements : 237 Total pins : 68 Total virtual pins : 0 UFM blocks : 1 / 1 ( 100 % ) diff --git a/cpld/output_files/GR8RAM.pin b/cpld/output_files/GR8RAM.pin index b748cdf..c508b09 100755 --- a/cpld/output_files/GR8RAM.pin +++ b/cpld/output_files/GR8RAM.pin @@ -62,103 +62,103 @@ CHIP "GR8RAM" ASSIGNED TO AN: EPM240T100C5 Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment ------------------------------------------------------------------------------------------------------------- -RA[12] : 1 : input : 3.3-V LVTTL : : 2 : N -RD[0] : 2 : bidir : 3.3-V LVTTL : : 1 : N -RD[3] : 3 : bidir : 3.3-V LVTTL : : 1 : N -RD[6] : 4 : bidir : 3.3-V LVTTL : : 1 : N -RD[4] : 5 : bidir : 3.3-V LVTTL : : 1 : N -RD[7] : 6 : bidir : 3.3-V LVTTL : : 1 : N -RD[1] : 7 : bidir : 3.3-V LVTTL : : 1 : N -nWE : 8 : input : 3.3-V LVTTL : : 1 : N +SA[0] : 1 : output : 3.3-V LVTTL : : 2 : N +GND* : 2 : : : : 1 : +SA[8] : 3 : output : 3.3-V LVTTL : : 1 : N +SA[2] : 4 : output : 3.3-V LVTTL : : 1 : N +RAdir : 5 : output : 3.3-V LVTTL : : 1 : N +SD[5] : 6 : bidir : 3.3-V LVTTL : : 1 : N +SD[4] : 7 : bidir : 3.3-V LVTTL : : 1 : N +SD[1] : 8 : bidir : 3.3-V LVTTL : : 1 : N VCCIO1 : 9 : power : : 3.3V : 1 : GNDIO : 10 : gnd : : : : GNDINT : 11 : gnd : : : : -PHI0 : 12 : input : 3.3-V LVTTL : : 1 : N +RA[3] : 12 : input : 3.3-V LVTTL : : 1 : N VCCINT : 13 : power : : 2.5V/3.3V : : C25M : 14 : input : 3.3-V LVTTL : : 1 : N -RA[8] : 15 : input : 3.3-V LVTTL : : 1 : N -RA[10] : 16 : input : 3.3-V LVTTL : : 1 : N -RA[9] : 17 : input : 3.3-V LVTTL : : 1 : N -SA[8] : 18 : output : 3.3-V LVTTL : : 1 : N -SA[7] : 19 : output : 3.3-V LVTTL : : 1 : N -RA[11] : 20 : input : 3.3-V LVTTL : : 1 : N -SA[1] : 21 : output : 3.3-V LVTTL : : 1 : N +RA[5] : 15 : input : 3.3-V LVTTL : : 1 : N +RA[2] : 16 : input : 3.3-V LVTTL : : 1 : N +RA[0] : 17 : input : 3.3-V LVTTL : : 1 : N +SD[6] : 18 : bidir : 3.3-V LVTTL : : 1 : N +nRESout : 19 : output : 3.3-V LVTTL : : 1 : N +SD[7] : 20 : bidir : 3.3-V LVTTL : : 1 : N +MOSI : 21 : output : 3.3-V LVTTL : : 1 : N TMS : 22 : input : : : 1 : TDI : 23 : input : : : 1 : TCK : 24 : input : : : 1 : TDO : 25 : output : : : 1 : -SD[7] : 26 : bidir : 3.3-V LVTTL : : 1 : N -SD[6] : 27 : bidir : 3.3-V LVTTL : : 1 : N -MOSI : 28 : output : 3.3-V LVTTL : : 1 : N -FCK : 29 : output : 3.3-V LVTTL : : 1 : N -RA[0] : 30 : input : 3.3-V LVTTL : : 1 : N +SD[3] : 26 : bidir : 3.3-V LVTTL : : 1 : N +SD[2] : 27 : bidir : 3.3-V LVTTL : : 1 : N +MISO : 28 : input : 3.3-V LVTTL : : 1 : N +SD[0] : 29 : bidir : 3.3-V LVTTL : : 1 : N +FCK : 30 : output : 3.3-V LVTTL : : 1 : N VCCIO1 : 31 : power : : 3.3V : 1 : GNDIO : 32 : gnd : : : : -MISO : 33 : input : 3.3-V LVTTL : : 1 : N -RA[7] : 34 : input : 3.3-V LVTTL : : 1 : N -RA[2] : 35 : input : 3.3-V LVTTL : : 1 : N -RA[14] : 36 : input : 3.3-V LVTTL : : 1 : N -nRESout : 37 : output : 3.3-V LVTTL : : 1 : N -nFCS : 38 : output : 3.3-V LVTTL : : 1 : N -SA[3] : 39 : output : 3.3-V LVTTL : : 1 : N -SD[1] : 40 : bidir : 3.3-V LVTTL : : 1 : N -SD[4] : 41 : bidir : 3.3-V LVTTL : : 1 : N -SD[0] : 42 : bidir : 3.3-V LVTTL : : 1 : N -SBA[0] : 43 : output : 3.3-V LVTTL : : 1 : N -GND* : 44 : : : : 1 : +RA[8] : 33 : input : 3.3-V LVTTL : : 1 : N +RA[10] : 34 : input : 3.3-V LVTTL : : 1 : N +RA[7] : 35 : input : 3.3-V LVTTL : : 1 : N +RA[4] : 36 : input : 3.3-V LVTTL : : 1 : N +RA[9] : 37 : input : 3.3-V LVTTL : : 1 : N +RA[1] : 38 : input : 3.3-V LVTTL : : 1 : N +RA[11] : 39 : input : 3.3-V LVTTL : : 1 : N +GND* : 40 : : : : 1 : +GND* : 41 : : : : 1 : +SA[11] : 42 : output : 3.3-V LVTTL : : 1 : N +nFCS : 43 : output : 3.3-V LVTTL : : 1 : N +SA[12] : 44 : output : 3.3-V LVTTL : : 1 : N VCCIO1 : 45 : power : : 3.3V : 1 : GNDIO : 46 : gnd : : : : GND* : 47 : : : : 1 : -GND* : 48 : : : : 1 : +DQMH : 48 : output : 3.3-V LVTTL : : 1 : N GND* : 49 : : : : 1 : GND* : 50 : : : : 1 : -SD[3] : 51 : bidir : 3.3-V LVTTL : : 1 : N -SD[5] : 52 : bidir : 3.3-V LVTTL : : 2 : N -SD[2] : 53 : bidir : 3.3-V LVTTL : : 2 : N -GND* : 54 : : : : 2 : -GND* : 55 : : : : 2 : +GND* : 51 : : : : 1 : +SA[9] : 52 : output : 3.3-V LVTTL : : 2 : N +GND* : 53 : : : : 2 : +SA[4] : 54 : output : 3.3-V LVTTL : : 2 : N +SA[10] : 55 : output : 3.3-V LVTTL : : 2 : N GND* : 56 : : : : 2 : -nRCS : 57 : output : 3.3-V LVTTL : : 2 : N -nCAS : 58 : output : 3.3-V LVTTL : : 2 : N +RA[13] : 57 : input : 3.3-V LVTTL : : 2 : N +RA[12] : 58 : input : 3.3-V LVTTL : : 2 : N VCCIO2 : 59 : power : : 3.3V : 2 : GNDIO : 60 : gnd : : : : -SA[2] : 61 : output : 3.3-V LVTTL : : 2 : N -SA[10] : 62 : output : 3.3-V LVTTL : : 2 : N +RA[14] : 61 : input : 3.3-V LVTTL : : 2 : N +RA[15] : 62 : input : 3.3-V LVTTL : : 2 : N VCCINT : 63 : power : : 2.5V/3.3V : : -nRES : 64 : input : 3.3-V LVTTL : : 2 : N +nIOSTRB : 64 : input : 3.3-V LVTTL : : 2 : N GNDINT : 65 : gnd : : : : -RCKE : 66 : output : 3.3-V LVTTL : : 2 : N -SA[9] : 67 : output : 3.3-V LVTTL : : 2 : N -nRAS : 68 : output : 3.3-V LVTTL : : 2 : N -nSWE : 69 : output : 3.3-V LVTTL : : 2 : N -SA[12] : 70 : output : 3.3-V LVTTL : : 2 : N +DQML : 66 : output : 3.3-V LVTTL : : 2 : N +nDEVSEL : 67 : input : 3.3-V LVTTL : : 2 : N +SBA[1] : 68 : output : 3.3-V LVTTL : : 2 : N +nRAS : 69 : output : 3.3-V LVTTL : : 2 : N +RCKE : 70 : output : 3.3-V LVTTL : : 2 : N nIOSEL : 71 : input : 3.3-V LVTTL : : 2 : N -nIOSTRB : 72 : input : 3.3-V LVTTL : : 2 : N -SA[0] : 73 : output : 3.3-V LVTTL : : 2 : N -SA[4] : 74 : output : 3.3-V LVTTL : : 2 : N -DQMH : 75 : output : 3.3-V LVTTL : : 2 : N -DQML : 76 : output : 3.3-V LVTTL : : 2 : N -nDEVSEL : 77 : input : 3.3-V LVTTL : : 2 : N -RAdir : 78 : output : 3.3-V LVTTL : : 2 : N +PHI0 : 72 : input : 3.3-V LVTTL : : 2 : N +nRES : 73 : input : 3.3-V LVTTL : : 2 : N +nWE : 74 : input : 3.3-V LVTTL : : 2 : N +RDdir : 75 : output : 3.3-V LVTTL : : 2 : N +GND* : 76 : : : : 2 : +SA[5] : 77 : output : 3.3-V LVTTL : : 2 : N +GND* : 78 : : : : 2 : GNDIO : 79 : gnd : : : : VCCIO2 : 80 : power : : 3.3V : 2 : -RA[5] : 81 : input : 3.3-V LVTTL : : 2 : N -RA[6] : 82 : input : 3.3-V LVTTL : : 2 : N -SA[6] : 83 : output : 3.3-V LVTTL : : 2 : N -RA[4] : 84 : input : 3.3-V LVTTL : : 2 : N -SA[5] : 85 : output : 3.3-V LVTTL : : 2 : N -SBA[1] : 86 : output : 3.3-V LVTTL : : 2 : N -GND* : 87 : : : : 2 : -SA[11] : 88 : output : 3.3-V LVTTL : : 2 : N -GND* : 89 : : : : 2 : -GND* : 90 : : : : 2 : -GND* : 91 : : : : 2 : -RA[1] : 92 : input : 3.3-V LVTTL : : 2 : N +SA[7] : 81 : output : 3.3-V LVTTL : : 2 : N +nSWE : 82 : output : 3.3-V LVTTL : : 2 : N +nCAS : 83 : output : 3.3-V LVTTL : : 2 : N +nRCS : 84 : output : 3.3-V LVTTL : : 2 : N +RD[2] : 85 : bidir : 3.3-V LVTTL : : 2 : N +SBA[0] : 86 : output : 3.3-V LVTTL : : 2 : N +RD[7] : 87 : bidir : 3.3-V LVTTL : : 2 : N +SA[3] : 88 : output : 3.3-V LVTTL : : 2 : N +RD[6] : 89 : bidir : 3.3-V LVTTL : : 2 : N +RD[1] : 90 : bidir : 3.3-V LVTTL : : 2 : N +RA[6] : 91 : input : 3.3-V LVTTL : : 2 : N +RD[0] : 92 : bidir : 3.3-V LVTTL : : 2 : N GNDIO : 93 : gnd : : : : VCCIO2 : 94 : power : : 3.3V : 2 : -RA[15] : 95 : input : 3.3-V LVTTL : : 2 : N -RA[3] : 96 : input : 3.3-V LVTTL : : 2 : N -RA[13] : 97 : input : 3.3-V LVTTL : : 2 : N -RD[2] : 98 : bidir : 3.3-V LVTTL : : 2 : N -RD[5] : 99 : bidir : 3.3-V LVTTL : : 2 : N -RDdir : 100 : output : 3.3-V LVTTL : : 2 : N +RD[4] : 95 : bidir : 3.3-V LVTTL : : 2 : N +RD[3] : 96 : bidir : 3.3-V LVTTL : : 2 : N +RD[5] : 97 : bidir : 3.3-V LVTTL : : 2 : N +SA[6] : 98 : output : 3.3-V LVTTL : : 2 : N +GND* : 99 : : : : 2 : +SA[1] : 100 : output : 3.3-V LVTTL : : 2 : N diff --git a/cpld/output_files/GR8RAM.pof b/cpld/output_files/GR8RAM.pof index 2934233..6b2b226 100755 Binary files a/cpld/output_files/GR8RAM.pof and b/cpld/output_files/GR8RAM.pof differ diff --git a/cpld/output_files/GR8RAM.sta.rpt b/cpld/output_files/GR8RAM.sta.rpt index 97bbf14..348d4dd 100755 --- a/cpld/output_files/GR8RAM.sta.rpt +++ b/cpld/output_files/GR8RAM.sta.rpt @@ -1,5 +1,5 @@ TimeQuest Timing Analyzer report for GR8RAM -Fri Mar 19 07:33:22 2021 +Fri Mar 19 16:35:38 2021 Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition @@ -16,25 +16,31 @@ Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit 8. Recovery Summary 9. Removal Summary 10. Minimum Pulse Width Summary - 11. Setup: 'C25M' - 12. Hold: 'C25M' - 13. Minimum Pulse Width: 'C25M' - 14. Setup Times - 15. Hold Times - 16. Clock to Output Times - 17. Minimum Clock to Output Times - 18. Propagation Delay - 19. Minimum Propagation Delay - 20. Output Enable Times - 21. Minimum Output Enable Times - 22. Output Disable Times - 23. Minimum Output Disable Times - 24. Setup Transfers - 25. Hold Transfers - 26. Report TCCS - 27. Report RSKM - 28. Unconstrained Paths - 29. TimeQuest Timing Analyzer Messages + 11. Setup: 'ARCLK' + 12. Setup: 'DRCLK' + 13. Setup: 'C25M' + 14. Hold: 'ARCLK' + 15. Hold: 'DRCLK' + 16. Hold: 'C25M' + 17. Minimum Pulse Width: 'ARCLK' + 18. Minimum Pulse Width: 'DRCLK' + 19. Minimum Pulse Width: 'C25M' + 20. Setup Times + 21. Hold Times + 22. Clock to Output Times + 23. Minimum Clock to Output Times + 24. Propagation Delay + 25. Minimum Propagation Delay + 26. Output Enable Times + 27. Minimum Output Enable Times + 28. Output Disable Times + 29. Minimum Output Disable Times + 30. Setup Transfers + 31. Hold Transfers + 32. Report TCCS + 33. Report RSKM + 34. Unconstrained Paths + 35. TimeQuest Timing Analyzer Messages @@ -87,13 +93,15 @@ applicable agreement for further details. +----------------------------+-------------+ -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Clocks ; -+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------+ -; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; -+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------+ -; C25M ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { C25M } ; -+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------+ ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clocks ; ++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+ +; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; ++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+ +; ARCLK ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { ARCLK } ; +; C25M ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { C25M } ; +; DRCLK ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { DRCLK } ; ++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+ +-------------------------------------------------+ @@ -101,27 +109,33 @@ applicable agreement for further details. +-----------+-----------------+------------+------+ ; Fmax ; Restricted Fmax ; Clock Name ; Note ; +-----------+-----------------+------------+------+ -; 95.18 MHz ; 95.18 MHz ; C25M ; ; +; 10.0 MHz ; 10.0 MHz ; ARCLK ; ; +; 10.0 MHz ; 10.0 MHz ; DRCLK ; ; +; 94.74 MHz ; 94.74 MHz ; C25M ; ; +-----------+-----------------+------------+------+ This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. -+--------------------------------+ -; Setup Summary ; -+-------+--------+---------------+ -; Clock ; Slack ; End Point TNS ; -+-------+--------+---------------+ -; C25M ; -9.506 ; -540.769 ; -+-------+--------+---------------+ ++---------------------------------+ +; Setup Summary ; ++-------+---------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-------+---------+---------------+ +; ARCLK ; -99.000 ; -99.000 ; +; DRCLK ; -99.000 ; -99.000 ; +; C25M ; -9.555 ; -547.115 ; ++-------+---------+---------------+ -+-------------------------------+ -; Hold Summary ; -+-------+-------+---------------+ -; Clock ; Slack ; End Point TNS ; -+-------+-------+---------------+ -; C25M ; 1.639 ; 0.000 ; -+-------+-------+---------------+ ++---------------------------------+ +; Hold Summary ; ++-------+---------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-------+---------+---------------+ +; ARCLK ; -16.276 ; -16.276 ; +; DRCLK ; -16.256 ; -16.256 ; +; C25M ; 1.377 ; 0.000 ; ++-------+---------+---------------+ -------------------- @@ -136,13 +150,35 @@ No paths to report. No paths to report. -+--------------------------------+ -; Minimum Pulse Width Summary ; -+-------+--------+---------------+ -; Clock ; Slack ; End Point TNS ; -+-------+--------+---------------+ -; C25M ; -2.289 ; -2.289 ; -+-------+--------+---------------+ ++---------------------------------+ +; Minimum Pulse Width Summary ; ++-------+---------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-------+---------+---------------+ +; ARCLK ; -29.500 ; -59.000 ; +; DRCLK ; -29.500 ; -59.000 ; +; C25M ; -2.289 ; -2.289 ; ++-------+---------+---------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Setup: 'ARCLK' ; ++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; -99.000 ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK ; ARCLK ; 1.000 ; 0.000 ; 80.000 ; +; -22.724 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C25M ; ARCLK ; 1.000 ; -2.195 ; 1.529 ; ++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Setup: 'DRCLK' ; ++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; -99.000 ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|wire_maxii_ufm_block1_drdout ; DRCLK ; DRCLK ; 1.000 ; 0.000 ; 80.000 ; +; -22.744 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|wire_maxii_ufm_block1_drdout ; C25M ; DRCLK ; 1.000 ; -2.195 ; 1.549 ; ++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +------------------------------------------------------------------------------------------------------+ @@ -150,217 +186,265 @@ No paths to report. +--------+-----------+-----------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+-----------+-----------+--------------+-------------+--------------+------------+------------+ -; -9.506 ; RAcur[2] ; Addr[11] ; C25M ; C25M ; 1.000 ; 0.000 ; 10.173 ; -; -9.506 ; RAcur[2] ; Addr[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 10.173 ; -; -9.506 ; RAcur[2] ; Addr[14] ; C25M ; C25M ; 1.000 ; 0.000 ; 10.173 ; -; -9.475 ; RAcur[8] ; Addr[20] ; C25M ; C25M ; 1.000 ; 0.000 ; 10.142 ; -; -9.425 ; RAcur[2] ; Addr[20] ; C25M ; C25M ; 1.000 ; 0.000 ; 10.092 ; -; -9.310 ; RAcur[11] ; Addr[20] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.977 ; -; -9.290 ; RAcur[8] ; Addr[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.957 ; -; -9.281 ; RAcur[0] ; Addr[11] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.948 ; -; -9.281 ; RAcur[0] ; Addr[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.948 ; -; -9.281 ; RAcur[0] ; Addr[14] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.948 ; -; -9.247 ; RAcur[8] ; Addr[11] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.914 ; -; -9.247 ; RAcur[8] ; Addr[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.914 ; -; -9.247 ; RAcur[8] ; Addr[14] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.914 ; -; -9.241 ; RAcur[0] ; nRCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.908 ; -; -9.240 ; RAcur[2] ; Addr[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.907 ; -; -9.207 ; RAcur[2] ; Addr[8] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.874 ; -; -9.207 ; RAcur[2] ; Addr[9] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.874 ; -; -9.207 ; RAcur[8] ; nRCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.874 ; -; -9.139 ; RAcur[2] ; Addr[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.806 ; -; -9.125 ; RAcur[11] ; Addr[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.792 ; -; -9.082 ; RAcur[11] ; Addr[11] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.749 ; -; -9.082 ; RAcur[11] ; Addr[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.749 ; -; -9.082 ; RAcur[11] ; Addr[14] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.749 ; -; -9.069 ; RAcur[2] ; Addr[13] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.736 ; -; -9.042 ; RAcur[11] ; nRCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.709 ; -; -9.038 ; RAcur[8] ; Addr[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.705 ; -; -9.008 ; RAcur[0] ; Addr[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.675 ; -; -9.008 ; RAcur[0] ; Addr[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.675 ; -; -9.008 ; RAcur[0] ; Addr[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.675 ; -; -9.007 ; RAcur[0] ; Addr[20] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.674 ; -; -8.982 ; RAcur[0] ; Addr[8] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.649 ; -; -8.982 ; RAcur[0] ; Addr[9] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.649 ; -; -8.978 ; RAcur[8] ; Addr[2] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.645 ; -; -8.978 ; RAcur[8] ; Addr[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.645 ; -; -8.974 ; RAcur[8] ; Addr[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.641 ; -; -8.974 ; RAcur[8] ; Addr[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.641 ; -; -8.974 ; RAcur[8] ; Addr[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.641 ; -; -8.948 ; RAcur[8] ; Addr[8] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.615 ; -; -8.948 ; RAcur[8] ; Addr[9] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.615 ; -; -8.928 ; RAcur[2] ; Addr[2] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.595 ; -; -8.928 ; RAcur[2] ; Addr[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.595 ; -; -8.910 ; RAcur[0] ; Addr[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.577 ; -; -8.873 ; RAcur[11] ; Addr[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.540 ; -; -8.844 ; RAcur[0] ; Addr[13] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.511 ; -; -8.843 ; RAcur[0] ; Addr[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.510 ; -; -8.838 ; RAcur[0] ; Addr[2] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.505 ; -; -8.819 ; RAcur[2] ; Addr[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.486 ; -; -8.813 ; RAcur[11] ; Addr[2] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.480 ; -; -8.813 ; RAcur[11] ; Addr[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.480 ; -; -8.810 ; RAcur[8] ; Addr[13] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.477 ; -; -8.809 ; RAcur[11] ; Addr[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.476 ; -; -8.809 ; RAcur[11] ; Addr[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.476 ; -; -8.809 ; RAcur[11] ; Addr[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.476 ; -; -8.789 ; RAcur[0] ; Addr[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.456 ; -; -8.783 ; RAcur[11] ; Addr[8] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.450 ; -; -8.783 ; RAcur[11] ; Addr[9] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.450 ; -; -8.781 ; RAcur[9] ; Addr[20] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.448 ; -; -8.771 ; RAcur[2] ; Addr[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.438 ; -; -8.750 ; RAcur[0] ; Addr[22] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.417 ; -; -8.716 ; RAcur[8] ; Addr[22] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.383 ; -; -8.649 ; nWEcur ; Addr[11] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.316 ; -; -8.649 ; nWEcur ; Addr[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.316 ; -; -8.649 ; nWEcur ; Addr[14] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.316 ; -; -8.645 ; RAcur[11] ; Addr[13] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.312 ; -; -8.623 ; RAcur[2] ; Addr[15] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.290 ; -; -8.596 ; RAcur[9] ; Addr[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.263 ; -; -8.592 ; RAcur[2] ; Addr[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.259 ; -; -8.587 ; RAcur[8] ; Addr[3] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.254 ; -; -8.587 ; RAcur[8] ; Addr[5] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.254 ; -; -8.568 ; nWEcur ; Addr[20] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.235 ; -; -8.553 ; RAcur[9] ; Addr[11] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.220 ; -; -8.553 ; RAcur[9] ; Addr[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.220 ; -; -8.553 ; RAcur[9] ; Addr[14] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.220 ; -; -8.551 ; RAcur[11] ; Addr[22] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.218 ; -; -8.541 ; RAcur[2] ; Addr[22] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.208 ; -; -8.540 ; RAcur[0] ; Addr[5] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.207 ; -; -8.539 ; RAcur[0] ; Addr[3] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.206 ; -; -8.537 ; RAcur[2] ; Addr[3] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.204 ; -; -8.537 ; RAcur[2] ; Addr[5] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.204 ; -; -8.518 ; RAcur[3] ; Addr[11] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.185 ; -; -8.518 ; RAcur[3] ; Addr[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.185 ; -; -8.518 ; RAcur[3] ; Addr[14] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.185 ; -; -8.513 ; RAcur[9] ; nRCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.180 ; -; -8.498 ; REGEN ; Addr[11] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.165 ; -; -8.498 ; REGEN ; Addr[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.165 ; -; -8.498 ; REGEN ; Addr[14] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.165 ; -; -8.478 ; RAcur[3] ; nRCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.145 ; -; -8.422 ; RAcur[1] ; Addr[11] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.089 ; -; -8.422 ; RAcur[1] ; Addr[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.089 ; -; -8.422 ; RAcur[1] ; Addr[14] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.089 ; -; -8.422 ; RAcur[11] ; Addr[3] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.089 ; -; -8.422 ; RAcur[11] ; Addr[5] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.089 ; -; -8.383 ; nWEcur ; Addr[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.050 ; -; -8.366 ; RAcur[0] ; nRAS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.033 ; -; -8.350 ; nWEcur ; Addr[8] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.017 ; -; -8.350 ; nWEcur ; Addr[9] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.017 ; -; -8.344 ; RAcur[9] ; Addr[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.011 ; -; -8.341 ; RAcur[1] ; Addr[20] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.008 ; -; -8.332 ; RAcur[8] ; nRAS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.999 ; -; -8.296 ; Addr[11] ; Addr[14] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.963 ; +; -9.555 ; RAcur[9] ; Addr[20] ; C25M ; C25M ; 1.000 ; 0.000 ; 10.222 ; +; -9.517 ; RAcur[9] ; Addr[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 10.184 ; +; -9.517 ; RAcur[9] ; Addr[11] ; C25M ; C25M ; 1.000 ; 0.000 ; 10.184 ; +; -9.517 ; RAcur[9] ; Addr[8] ; C25M ; C25M ; 1.000 ; 0.000 ; 10.184 ; +; -9.495 ; RAcur[9] ; Addr[22] ; C25M ; C25M ; 1.000 ; 0.000 ; 10.162 ; +; -9.495 ; RAcur[9] ; Addr[14] ; C25M ; C25M ; 1.000 ; 0.000 ; 10.162 ; +; -9.495 ; RAcur[9] ; Addr[13] ; C25M ; C25M ; 1.000 ; 0.000 ; 10.162 ; +; -9.495 ; RAcur[9] ; Addr[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 10.162 ; +; -9.495 ; RAcur[9] ; Addr[10] ; C25M ; C25M ; 1.000 ; 0.000 ; 10.162 ; +; -9.352 ; RAcur[10] ; Addr[20] ; C25M ; C25M ; 1.000 ; 0.000 ; 10.019 ; +; -9.333 ; RAcur[9] ; Addr[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 10.000 ; +; -9.314 ; RAcur[10] ; Addr[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.981 ; +; -9.314 ; RAcur[10] ; Addr[11] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.981 ; +; -9.314 ; RAcur[10] ; Addr[8] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.981 ; +; -9.292 ; RAcur[10] ; Addr[22] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.959 ; +; -9.292 ; RAcur[10] ; Addr[14] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.959 ; +; -9.292 ; RAcur[10] ; Addr[13] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.959 ; +; -9.292 ; RAcur[10] ; Addr[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.959 ; +; -9.292 ; RAcur[10] ; Addr[10] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.959 ; +; -9.246 ; RAcur[3] ; Addr[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.913 ; +; -9.246 ; RAcur[3] ; Addr[11] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.913 ; +; -9.246 ; RAcur[3] ; Addr[8] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.913 ; +; -9.224 ; RAcur[3] ; Addr[14] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.891 ; +; -9.224 ; RAcur[3] ; Addr[13] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.891 ; +; -9.224 ; RAcur[3] ; Addr[10] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.891 ; +; -9.185 ; RAcur[9] ; nRCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.852 ; +; -9.130 ; RAcur[10] ; Addr[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.797 ; +; -9.101 ; RAcur[9] ; Addr[5] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.768 ; +; -9.101 ; RAcur[9] ; Addr[4] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.768 ; +; -9.089 ; RAcur[9] ; Addr[7] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.756 ; +; -9.046 ; RAcur[9] ; Addr[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.713 ; +; -9.025 ; RAcur[9] ; Addr[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.692 ; +; -9.016 ; RAcur[3] ; Addr[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.683 ; +; -8.997 ; RAcur[9] ; Addr[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.664 ; +; -8.982 ; RAcur[10] ; nRCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.649 ; +; -8.898 ; RAcur[10] ; Addr[5] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.565 ; +; -8.898 ; RAcur[10] ; Addr[4] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.565 ; +; -8.886 ; RAcur[10] ; Addr[7] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.553 ; +; -8.869 ; RAcur[3] ; Addr[20] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.536 ; +; -8.847 ; RAcur[7] ; Addr[20] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.514 ; +; -8.843 ; RAcur[10] ; Addr[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.510 ; +; -8.822 ; RAcur[8] ; Addr[20] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.489 ; +; -8.822 ; RAcur[10] ; Addr[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.489 ; +; -8.809 ; RAcur[7] ; Addr[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.476 ; +; -8.809 ; RAcur[7] ; Addr[11] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.476 ; +; -8.809 ; RAcur[7] ; Addr[8] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.476 ; +; -8.794 ; RAcur[10] ; Addr[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.461 ; +; -8.787 ; RAcur[7] ; Addr[22] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.454 ; +; -8.787 ; RAcur[7] ; Addr[14] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.454 ; +; -8.787 ; RAcur[7] ; Addr[13] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.454 ; +; -8.787 ; RAcur[7] ; Addr[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.454 ; +; -8.787 ; RAcur[7] ; Addr[10] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.454 ; +; -8.784 ; RAcur[8] ; Addr[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.451 ; +; -8.784 ; RAcur[8] ; Addr[11] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.451 ; +; -8.784 ; RAcur[8] ; Addr[8] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.451 ; +; -8.776 ; RAcur[3] ; Addr[5] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.443 ; +; -8.776 ; RAcur[3] ; Addr[4] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.443 ; +; -8.764 ; RAcur[3] ; Addr[7] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.431 ; +; -8.762 ; RAcur[8] ; Addr[22] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.429 ; +; -8.762 ; RAcur[8] ; Addr[14] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.429 ; +; -8.762 ; RAcur[8] ; Addr[13] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.429 ; +; -8.762 ; RAcur[8] ; Addr[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.429 ; +; -8.762 ; RAcur[8] ; Addr[10] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.429 ; +; -8.727 ; RACr ; Addr[20] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.394 ; +; -8.709 ; LS[10] ; SS[1] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.376 ; +; -8.709 ; LS[10] ; SS[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.376 ; +; -8.708 ; RAcur[3] ; Addr[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.375 ; +; -8.702 ; RAcur[2] ; Addr[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.369 ; +; -8.702 ; RAcur[2] ; Addr[11] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.369 ; +; -8.702 ; RAcur[2] ; Addr[8] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.369 ; +; -8.696 ; RAcur[3] ; Addr[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.363 ; +; -8.689 ; RACr ; Addr[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.356 ; +; -8.689 ; RACr ; Addr[11] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.356 ; +; -8.689 ; RACr ; Addr[8] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.356 ; +; -8.686 ; RAcur[2] ; Addr[20] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.353 ; +; -8.680 ; RAcur[2] ; Addr[14] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.347 ; +; -8.680 ; RAcur[2] ; Addr[13] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.347 ; +; -8.680 ; RAcur[2] ; Addr[10] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.347 ; +; -8.667 ; RACr ; Addr[22] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.334 ; +; -8.667 ; RACr ; Addr[14] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.334 ; +; -8.667 ; RACr ; Addr[13] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.334 ; +; -8.667 ; RACr ; Addr[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.334 ; +; -8.667 ; RACr ; Addr[10] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.334 ; +; -8.657 ; LS[14] ; SS[1] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.324 ; +; -8.657 ; LS[14] ; SS[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.324 ; +; -8.626 ; RAcur[1] ; Addr[20] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.293 ; +; -8.626 ; RAcur[2] ; Addr[22] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.293 ; +; -8.626 ; RAcur[2] ; Addr[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.293 ; +; -8.625 ; RAcur[7] ; Addr[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.292 ; +; -8.600 ; RAcur[8] ; Addr[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.267 ; +; -8.566 ; RAcur[1] ; Addr[22] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.233 ; +; -8.566 ; RAcur[1] ; Addr[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.233 ; +; -8.550 ; Addr[15] ; Addr[20] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.217 ; +; -8.539 ; RAcur[3] ; Addr[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.206 ; +; -8.520 ; RAcur[3] ; Addr[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.187 ; +; -8.514 ; RAcur[9] ; nCAS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.181 ; +; -8.505 ; RACr ; Addr[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.172 ; +; -8.490 ; Addr[15] ; Addr[22] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.157 ; +; -8.490 ; Addr[15] ; Addr[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.157 ; +; -8.477 ; RAcur[7] ; nRCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.144 ; +--------+-----------+-----------+--------------+-------------+--------------+------------+------------+ ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Hold: 'ARCLK' ; ++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; -16.276 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C25M ; ARCLK ; 0.000 ; -2.195 ; 1.529 ; +; 60.000 ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK ; ARCLK ; 0.000 ; 0.000 ; 80.000 ; ++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Hold: 'DRCLK' ; ++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; -16.256 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|wire_maxii_ufm_block1_drdout ; C25M ; DRCLK ; 0.000 ; -2.195 ; 1.549 ; +; 60.000 ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|wire_maxii_ufm_block1_drdout ; DRCLK ; DRCLK ; 0.000 ; 0.000 ; 80.000 ; ++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + +-----------------------------------------------------------------------------------------------------------+ ; Hold: 'C25M' ; +-------+--------------+--------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +-------+--------------+--------------+--------------+-------------+--------------+------------+------------+ -; 1.639 ; RefReqd ; RefReqd ; C25M ; C25M ; 0.000 ; 0.000 ; 1.860 ; -; 1.649 ; LS[0] ; LS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.870 ; -; 1.658 ; LS[17] ; LS[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.879 ; -; 1.667 ; nRESout~reg0 ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 1.888 ; -; 1.715 ; PS[0] ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.936 ; -; 1.947 ; IOSELr ; REGEN ; C25M ; C25M ; 0.000 ; 0.000 ; 2.168 ; -; 1.947 ; nRESr0 ; nRESr ; C25M ; C25M ; -0.500 ; 0.000 ; 1.668 ; -; 1.989 ; PS[1] ; PS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.210 ; -; 2.015 ; PS[1] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.236 ; +; 1.377 ; PHI0r1 ; PHI0r2 ; C25M ; C25M ; 0.000 ; 0.000 ; 1.598 ; +; 1.646 ; DEVSELr ; nSWE~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 1.867 ; +; 1.649 ; LS[17] ; LS[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.870 ; +; 1.668 ; RefReqd ; RefReqd ; C25M ; C25M ; 0.000 ; 0.000 ; 1.889 ; +; 1.674 ; LS[0] ; LS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.895 ; +; 1.702 ; PS[2] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.923 ; +; 1.705 ; PS[2] ; RCKE~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 1.926 ; +; 1.709 ; PS[0] ; PS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.930 ; +; 1.711 ; PS[2] ; Amux[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.932 ; +; 1.889 ; nRESr0 ; nRESr ; C25M ; C25M ; -0.500 ; 0.000 ; 1.610 ; +; 1.893 ; PHI0r0 ; PHI0r1 ; C25M ; C25M ; -0.500 ; 0.000 ; 1.614 ; +; 1.922 ; IOSELr ; IOROMEN ; C25M ; C25M ; 0.000 ; 0.000 ; 2.143 ; +; 1.936 ; MOSIOE ; MOSIOE ; C25M ; C25M ; 0.000 ; 0.000 ; 2.157 ; +; 1.948 ; PS[1] ; PS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.169 ; ; 2.108 ; LS[6] ; LS[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.329 ; -; 2.112 ; MOSIout ; WRD[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.333 ; ; 2.116 ; LS[9] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.337 ; +; 2.117 ; LS[1] ; LS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; ; 2.117 ; LS[16] ; LS[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; -; 2.117 ; LS[11] ; LS[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; ; 2.117 ; LS[10] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; -; 2.117 ; MOSIOE ; MOSIOE ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; -; 2.126 ; LS[1] ; LS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ; -; 2.135 ; LS[8] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.356 ; -; 2.149 ; IOSELr ; IOROMEN ; C25M ; C25M ; 0.000 ; 0.000 ; 2.370 ; -; 2.158 ; PS[2] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.379 ; -; 2.164 ; IOSELr0 ; IOSELr ; C25M ; C25M ; -0.500 ; 0.000 ; 1.885 ; -; 2.172 ; PS[2] ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.393 ; -; 2.223 ; PHI0r1 ; PHI0r2 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.444 ; +; 2.117 ; LS[11] ; LS[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; +; 2.117 ; LS[8] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; +; 2.135 ; REGEN ; REGEN ; C25M ; C25M ; 0.000 ; 0.000 ; 2.356 ; +; 2.152 ; nRESout~reg0 ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.373 ; +; 2.154 ; LS[0] ; FCK~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.375 ; +; 2.161 ; nRESout~reg0 ; MOSIOE ; C25M ; C25M ; 0.000 ; 0.000 ; 2.382 ; +; 2.162 ; IOSELr0 ; IOSELr ; C25M ; C25M ; -0.500 ; 0.000 ; 1.883 ; +; 2.177 ; PS[1] ; nCAS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.398 ; +; 2.182 ; PS[0] ; nSWE~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.403 ; +; 2.221 ; LS[12] ; LS[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.442 ; ; 2.230 ; FCS ; FCS ; C25M ; C25M ; 0.000 ; 0.000 ; 2.451 ; -; 2.230 ; LS[4] ; LS[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.451 ; -; 2.231 ; LS[3] ; LS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; -; 2.231 ; LS[2] ; LS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; -; 2.231 ; LS[5] ; LS[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; ; 2.234 ; IOROMEN ; IOROMEN ; C25M ; C25M ; 0.000 ; 0.000 ; 2.455 ; -; 2.240 ; LS[7] ; LS[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.461 ; -; 2.241 ; LS[12] ; LS[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.462 ; -; 2.243 ; PS[0] ; Amux[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.464 ; -; 2.249 ; PS[0] ; RCKE~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.470 ; -; 2.249 ; LS[13] ; LS[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.470 ; -; 2.254 ; PS[0] ; nSWE~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.475 ; -; 2.260 ; LS[15] ; LS[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.481 ; +; 2.236 ; IOSELr ; REGEN ; C25M ; C25M ; 0.000 ; 0.000 ; 2.457 ; +; 2.239 ; LS[4] ; LS[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.460 ; +; 2.239 ; LS[5] ; LS[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.460 ; +; 2.248 ; LS[15] ; LS[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.469 ; +; 2.249 ; LS[7] ; LS[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.470 ; +; 2.250 ; LS[3] ; LS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.471 ; +; 2.251 ; LS[2] ; LS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.472 ; +; 2.261 ; LS[13] ; LS[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.482 ; ; 2.261 ; LS[14] ; LS[14] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.482 ; -; 2.295 ; PS[0] ; PS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.516 ; -; 2.308 ; PS[0] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.529 ; -; 2.321 ; MOSIOE ; WRD[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.542 ; -; 2.328 ; PS[1] ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.549 ; -; 2.381 ; nRESout~reg0 ; SDOE ; C25M ; C25M ; 0.000 ; 0.000 ; 2.602 ; -; 2.384 ; PHI0r1 ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.605 ; -; 2.386 ; nRESout~reg0 ; FCK~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.607 ; -; 2.555 ; LS[12] ; ARShift ; C25M ; C25M ; 0.000 ; 0.000 ; 2.776 ; -; 2.584 ; FCKEN ; FCK~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.805 ; -; 2.625 ; LS[0] ; FCK~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.846 ; -; 2.674 ; nRESout~reg0 ; MOSIOE ; C25M ; C25M ; 0.000 ; 0.000 ; 2.895 ; -; 2.713 ; SetLoaded ; DRShift ; C25M ; C25M ; 0.000 ; 0.000 ; 2.934 ; -; 2.715 ; PS[1] ; nCAS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.936 ; -; 2.718 ; PS[1] ; Amux[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.939 ; -; 2.723 ; PS[1] ; RCKE~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.944 ; -; 2.726 ; PS[1] ; nSWE~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.947 ; -; 2.752 ; LS[1] ; DRCLK ; C25M ; C25M ; 0.000 ; 0.000 ; 2.973 ; -; 2.765 ; PS[2] ; nSWE~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.986 ; -; 2.770 ; PS[2] ; RCKE~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.991 ; -; 2.773 ; PS[2] ; Amux[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.994 ; -; 2.888 ; PS[0] ; Amux[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.109 ; +; 2.442 ; PS[2] ; nSWE~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.663 ; +; 2.512 ; MOSIout ; WRD[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.733 ; +; 2.547 ; PHI0r1 ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.768 ; +; 2.581 ; DEVSELr ; nCAS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.802 ; +; 2.602 ; RACr ; Amux[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.823 ; +; 2.647 ; PS[2] ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.868 ; +; 2.647 ; PS[2] ; nRCS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.868 ; +; 2.736 ; PS[1] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.957 ; +; 2.738 ; PS[1] ; RCKE~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.959 ; +; 2.742 ; PS[1] ; Amux[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.963 ; +; 2.766 ; PS[0] ; nCAS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.987 ; +; 2.811 ; SS[1] ; DRShift ; C25M ; C25M ; 0.000 ; 0.000 ; 3.032 ; +; 2.811 ; SS[1] ; ARCLK ; C25M ; C25M ; 0.000 ; 0.000 ; 3.032 ; +; 2.811 ; SS[1] ; ARShift ; C25M ; C25M ; 0.000 ; 0.000 ; 3.032 ; +; 2.816 ; SS[1] ; DRCLK ; C25M ; C25M ; 0.000 ; 0.000 ; 3.037 ; +; 2.860 ; DEVSELr0 ; DEVSELr ; C25M ; C25M ; -0.500 ; 0.000 ; 2.581 ; +; 2.917 ; SS[0] ; ARCLK ; C25M ; C25M ; 0.000 ; 0.000 ; 3.138 ; +; 2.920 ; IOSTRBr0 ; IOSTRBr ; C25M ; C25M ; -0.500 ; 0.000 ; 2.641 ; +; 2.922 ; SS[0] ; DRShift ; C25M ; C25M ; 0.000 ; 0.000 ; 3.143 ; +; 2.927 ; SS[0] ; DRCLK ; C25M ; C25M ; 0.000 ; 0.000 ; 3.148 ; ; 2.940 ; LS[6] ; LS[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.161 ; ; 2.948 ; LS[9] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.169 ; -; 2.949 ; LS[11] ; LS[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; ; 2.949 ; LS[16] ; LS[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; +; 2.949 ; LS[11] ; LS[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; +; 2.949 ; LS[1] ; LS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; ; 2.949 ; LS[10] ; LS[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; -; 2.958 ; LS[1] ; LS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.179 ; -; 3.034 ; PS[2] ; Amux[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.255 ; ; 3.051 ; LS[6] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.272 ; +; 3.051 ; PS[2] ; nCAS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.272 ; ; 3.059 ; LS[9] ; LS[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.280 ; -; 3.060 ; REGEN ; REGEN ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ; +; 3.060 ; LS[1] ; LS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ; ; 3.060 ; LS[11] ; LS[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ; ; 3.060 ; LS[10] ; LS[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ; -; 3.069 ; LS[1] ; LS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.290 ; -; 3.112 ; DEVSELr0 ; DEVSELr ; C25M ; C25M ; -0.500 ; 0.000 ; 2.833 ; -; 3.128 ; Addr[5] ; Addr[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.349 ; -; 3.129 ; LS[12] ; ARCLK ; C25M ; C25M ; 0.000 ; 0.000 ; 3.350 ; -; 3.145 ; nRESout~reg0 ; FCKEN ; C25M ; C25M ; 0.000 ; 0.000 ; 3.366 ; -; 3.170 ; LS[4] ; LS[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.391 ; +; 3.075 ; LS[1] ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.296 ; +; 3.109 ; RACr ; nRAS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.330 ; +; 3.127 ; Addr[4] ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.348 ; +; 3.133 ; Addr[5] ; Addr[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.354 ; +; 3.161 ; LS[12] ; LS[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.382 ; ; 3.170 ; LS[9] ; LS[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.391 ; -; 3.171 ; LS[5] ; LS[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.392 ; ; 3.171 ; LS[10] ; LS[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.392 ; -; 3.171 ; LS[2] ; LS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.392 ; -; 3.180 ; LS[7] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.401 ; -; 3.181 ; LS[12] ; LS[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.402 ; -; 3.191 ; LS[15] ; ARShift ; C25M ; C25M ; 0.000 ; 0.000 ; 3.412 ; -; 3.192 ; PS[1] ; Amux[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.413 ; -; 3.195 ; PS[1] ; Amux[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.416 ; -; 3.200 ; LS[15] ; LS[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.421 ; -; 3.201 ; LS[0] ; LS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.422 ; +; 3.175 ; PS[2] ; Amux[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.396 ; +; 3.179 ; LS[5] ; LS[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.400 ; +; 3.179 ; LS[4] ; LS[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.400 ; +; 3.188 ; LS[15] ; LS[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.409 ; +; 3.189 ; LS[7] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.410 ; +; 3.191 ; LS[2] ; LS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.412 ; +; 3.200 ; PS[1] ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.421 ; ; 3.201 ; LS[14] ; LS[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.422 ; -; 3.219 ; LS[1] ; ARCLK ; C25M ; C25M ; 0.000 ; 0.000 ; 3.440 ; -; 3.229 ; SetLoaded ; ARShift ; C25M ; C25M ; 0.000 ; 0.000 ; 3.450 ; -; 3.267 ; LS[1] ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.488 ; -; 3.281 ; LS[4] ; LS[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.502 ; +; 3.203 ; PS[1] ; nSWE~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.424 ; +; 3.204 ; MOSIOE ; WRD[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.425 ; +; 3.217 ; FCKEN ; FCK~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.438 ; +; 3.224 ; LS[0] ; LS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.445 ; +; 3.241 ; IOSTRBr ; IOROMEN ; C25M ; C25M ; 0.000 ; 0.000 ; 3.462 ; +; 3.241 ; PS[1] ; nRCS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.462 ; +; 3.243 ; IOSTRBr ; REGEN ; C25M ; C25M ; 0.000 ; 0.000 ; 3.464 ; +; 3.252 ; DEVSELr ; nRCS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.473 ; +; 3.256 ; FCKEN ; FCKEN ; C25M ; C25M ; 0.000 ; 0.000 ; 3.477 ; +; 3.281 ; LS[1] ; MOSIout ; C25M ; C25M ; 0.000 ; 0.000 ; 3.502 ; +; 3.281 ; nRESr ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.502 ; ; 3.281 ; LS[9] ; LS[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.502 ; -; 3.282 ; LS[5] ; LS[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.503 ; -; 3.286 ; SetLoaded ; DRCLK ; C25M ; C25M ; 0.000 ; 0.000 ; 3.507 ; -; 3.290 ; LS[12] ; DRCLK ; C25M ; C25M ; 0.000 ; 0.000 ; 3.511 ; -; 3.306 ; nRESr ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.527 ; -; 3.311 ; LS[15] ; LS[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.532 ; -; 3.312 ; LS[14] ; LS[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.533 ; -; 3.324 ; LS[14] ; ARShift ; C25M ; C25M ; 0.000 ; 0.000 ; 3.545 ; +; 3.290 ; LS[5] ; LS[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.511 ; +-------+--------------+--------------+--------------+-------------+--------------+------------+------------+ ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Minimum Pulse Width: 'ARCLK' ; ++---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------------------+ +; -29.500 ; 0.500 ; 30.000 ; High Pulse Width ; ARCLK ; Rise ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; +; -29.500 ; 0.500 ; 30.000 ; Low Pulse Width ; ARCLK ; Rise ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; ARCLK ; Rise ; ARCLK|regout ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; ARCLK ; Rise ; ARCLK|regout ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; ARCLK ; Rise ; UFM_inst|UFM_altufm_none_0ep_component|maxii_ufm_block1|arclk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; ARCLK ; Rise ; UFM_inst|UFM_altufm_none_0ep_component|maxii_ufm_block1|arclk ; ++---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Minimum Pulse Width: 'DRCLK' ; ++---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------+ +; -29.500 ; 0.500 ; 30.000 ; High Pulse Width ; DRCLK ; Rise ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|wire_maxii_ufm_block1_drdout ; +; -29.500 ; 0.500 ; 30.000 ; Low Pulse Width ; DRCLK ; Rise ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|wire_maxii_ufm_block1_drdout ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; DRCLK ; Rise ; DRCLK|regout ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; DRCLK ; Rise ; DRCLK|regout ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; DRCLK ; Rise ; UFM_inst|UFM_altufm_none_0ep_component|maxii_ufm_block1|drclk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; DRCLK ; Rise ; UFM_inst|UFM_altufm_none_0ep_component|maxii_ufm_block1|drclk ; ++---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------+ + + +-------------------------------------------------------------------------------------------+ ; Minimum Pulse Width: 'C25M' ; +--------+--------------+----------------+------------------+-------+------------+----------+ @@ -423,10 +507,6 @@ No paths to report. ; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Amux[1] ; ; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Amux[2] ; ; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Amux[2] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Bank[0] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Bank[0] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Bank[1] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Bank[1] ; ; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; DEVSELr ; ; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; DEVSELr ; ; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Fall ; DEVSELr0 ; @@ -466,48 +546,52 @@ No paths to report. ; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[15] ; ; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[15] ; ; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[16] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[16] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[17] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[17] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[1] ; +--------+--------------+----------------+------------------+-------+------------+----------+ -+-----------------------------------------------------------------------+ -; Setup Times ; -+-----------+------------+-------+-------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-----------+------------+-------+-------+------------+-----------------+ -; MISO ; C25M ; 2.730 ; 2.730 ; Rise ; C25M ; -; RA[*] ; C25M ; 4.937 ; 4.937 ; Rise ; C25M ; -; RA[0] ; C25M ; 2.787 ; 2.787 ; Rise ; C25M ; -; RA[1] ; C25M ; 2.712 ; 2.712 ; Rise ; C25M ; -; RA[2] ; C25M ; 3.301 ; 3.301 ; Rise ; C25M ; -; RA[3] ; C25M ; 2.682 ; 2.682 ; Rise ; C25M ; -; RA[4] ; C25M ; 2.473 ; 2.473 ; Rise ; C25M ; -; RA[5] ; C25M ; 2.473 ; 2.473 ; Rise ; C25M ; -; RA[6] ; C25M ; 2.746 ; 2.746 ; Rise ; C25M ; -; RA[7] ; C25M ; 4.349 ; 4.349 ; Rise ; C25M ; -; RA[8] ; C25M ; 1.883 ; 1.883 ; Rise ; C25M ; -; RA[9] ; C25M ; 2.487 ; 2.487 ; Rise ; C25M ; -; RA[10] ; C25M ; 1.880 ; 1.880 ; Rise ; C25M ; -; RA[11] ; C25M ; 2.745 ; 2.745 ; Rise ; C25M ; -; RA[12] ; C25M ; 4.937 ; 4.937 ; Rise ; C25M ; -; RA[13] ; C25M ; 3.478 ; 3.478 ; Rise ; C25M ; -; RA[14] ; C25M ; 3.854 ; 3.854 ; Rise ; C25M ; -; RA[15] ; C25M ; 4.767 ; 4.767 ; Rise ; C25M ; -; RD[*] ; C25M ; 8.623 ; 8.623 ; Rise ; C25M ; -; RD[0] ; C25M ; 4.967 ; 4.967 ; Rise ; C25M ; -; RD[1] ; C25M ; 5.394 ; 5.394 ; Rise ; C25M ; -; RD[2] ; C25M ; 8.623 ; 8.623 ; Rise ; C25M ; -; RD[3] ; C25M ; 4.531 ; 4.531 ; Rise ; C25M ; -; RD[4] ; C25M ; 6.378 ; 6.378 ; Rise ; C25M ; -; RD[5] ; C25M ; 5.642 ; 5.642 ; Rise ; C25M ; -; RD[6] ; C25M ; 4.500 ; 4.500 ; Rise ; C25M ; -; RD[7] ; C25M ; 8.385 ; 8.385 ; Rise ; C25M ; -; nWE ; C25M ; 2.477 ; 2.477 ; Rise ; C25M ; -; PHI0 ; C25M ; 2.525 ; 2.525 ; Fall ; C25M ; -; nDEVSEL ; C25M ; 3.234 ; 3.234 ; Fall ; C25M ; -; nIOSEL ; C25M ; 2.372 ; 2.372 ; Fall ; C25M ; -; nIOSTRB ; C25M ; 3.449 ; 3.449 ; Fall ; C25M ; -; nRES ; C25M ; 2.075 ; 2.075 ; Fall ; C25M ; -+-----------+------------+-------+-------+------------+-----------------+ ++-------------------------------------------------------------------------+ +; Setup Times ; ++-----------+------------+--------+--------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+--------+--------+------------+-----------------+ +; MISO ; C25M ; 2.718 ; 2.718 ; Rise ; C25M ; +; RA[*] ; C25M ; 4.985 ; 4.985 ; Rise ; C25M ; +; RA[0] ; C25M ; 3.094 ; 3.094 ; Rise ; C25M ; +; RA[1] ; C25M ; 2.761 ; 2.761 ; Rise ; C25M ; +; RA[2] ; C25M ; 1.816 ; 1.816 ; Rise ; C25M ; +; RA[3] ; C25M ; 3.690 ; 3.690 ; Rise ; C25M ; +; RA[4] ; C25M ; 3.968 ; 3.968 ; Rise ; C25M ; +; RA[5] ; C25M ; 1.839 ; 1.839 ; Rise ; C25M ; +; RA[6] ; C25M ; 4.985 ; 4.985 ; Rise ; C25M ; +; RA[7] ; C25M ; 2.923 ; 2.923 ; Rise ; C25M ; +; RA[8] ; C25M ; 2.713 ; 2.713 ; Rise ; C25M ; +; RA[9] ; C25M ; 2.954 ; 2.954 ; Rise ; C25M ; +; RA[10] ; C25M ; 3.104 ; 3.104 ; Rise ; C25M ; +; RA[11] ; C25M ; 3.143 ; 3.143 ; Rise ; C25M ; +; RA[12] ; C25M ; 3.138 ; 3.138 ; Rise ; C25M ; +; RA[13] ; C25M ; 2.941 ; 2.941 ; Rise ; C25M ; +; RA[14] ; C25M ; 2.693 ; 2.693 ; Rise ; C25M ; +; RA[15] ; C25M ; 2.767 ; 2.767 ; Rise ; C25M ; +; RD[*] ; C25M ; 10.732 ; 10.732 ; Rise ; C25M ; +; RD[0] ; C25M ; 5.791 ; 5.791 ; Rise ; C25M ; +; RD[1] ; C25M ; 4.956 ; 4.956 ; Rise ; C25M ; +; RD[2] ; C25M ; 5.617 ; 5.617 ; Rise ; C25M ; +; RD[3] ; C25M ; 4.619 ; 4.619 ; Rise ; C25M ; +; RD[4] ; C25M ; 5.356 ; 5.356 ; Rise ; C25M ; +; RD[5] ; C25M ; 4.875 ; 4.875 ; Rise ; C25M ; +; RD[6] ; C25M ; 5.869 ; 5.869 ; Rise ; C25M ; +; RD[7] ; C25M ; 10.732 ; 10.732 ; Rise ; C25M ; +; nWE ; C25M ; 3.867 ; 3.867 ; Rise ; C25M ; +; PHI0 ; C25M ; 1.878 ; 1.878 ; Fall ; C25M ; +; nDEVSEL ; C25M ; 2.414 ; 2.414 ; Fall ; C25M ; +; nIOSEL ; C25M ; 3.080 ; 3.080 ; Fall ; C25M ; +; nIOSTRB ; C25M ; 2.094 ; 2.094 ; Fall ; C25M ; +; nRES ; C25M ; 2.086 ; 2.086 ; Fall ; C25M ; ++-----------+------------+--------+--------+------------+-----------------+ +-------------------------------------------------------------------------+ @@ -515,39 +599,39 @@ No paths to report. +-----------+------------+--------+--------+------------+-----------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+--------+--------+------------+-----------------+ -; MISO ; C25M ; -2.176 ; -2.176 ; Rise ; C25M ; -; RA[*] ; C25M ; -1.326 ; -1.326 ; Rise ; C25M ; -; RA[0] ; C25M ; -2.233 ; -2.233 ; Rise ; C25M ; -; RA[1] ; C25M ; -2.158 ; -2.158 ; Rise ; C25M ; -; RA[2] ; C25M ; -2.747 ; -2.747 ; Rise ; C25M ; -; RA[3] ; C25M ; -2.128 ; -2.128 ; Rise ; C25M ; -; RA[4] ; C25M ; -1.919 ; -1.919 ; Rise ; C25M ; -; RA[5] ; C25M ; -1.919 ; -1.919 ; Rise ; C25M ; -; RA[6] ; C25M ; -2.192 ; -2.192 ; Rise ; C25M ; -; RA[7] ; C25M ; -3.795 ; -3.795 ; Rise ; C25M ; -; RA[8] ; C25M ; -1.329 ; -1.329 ; Rise ; C25M ; -; RA[9] ; C25M ; -1.933 ; -1.933 ; Rise ; C25M ; -; RA[10] ; C25M ; -1.326 ; -1.326 ; Rise ; C25M ; -; RA[11] ; C25M ; -2.191 ; -2.191 ; Rise ; C25M ; -; RA[12] ; C25M ; -4.383 ; -4.383 ; Rise ; C25M ; -; RA[13] ; C25M ; -2.924 ; -2.924 ; Rise ; C25M ; -; RA[14] ; C25M ; -3.300 ; -3.300 ; Rise ; C25M ; -; RA[15] ; C25M ; -4.213 ; -4.213 ; Rise ; C25M ; -; RD[*] ; C25M ; -2.174 ; -2.174 ; Rise ; C25M ; -; RD[0] ; C25M ; -2.174 ; -2.174 ; Rise ; C25M ; -; RD[1] ; C25M ; -2.540 ; -2.540 ; Rise ; C25M ; -; RD[2] ; C25M ; -2.456 ; -2.456 ; Rise ; C25M ; -; RD[3] ; C25M ; -2.232 ; -2.232 ; Rise ; C25M ; -; RD[4] ; C25M ; -3.100 ; -3.100 ; Rise ; C25M ; -; RD[5] ; C25M ; -2.977 ; -2.977 ; Rise ; C25M ; -; RD[6] ; C25M ; -3.098 ; -3.098 ; Rise ; C25M ; -; RD[7] ; C25M ; -3.202 ; -3.202 ; Rise ; C25M ; -; nWE ; C25M ; -1.923 ; -1.923 ; Rise ; C25M ; -; PHI0 ; C25M ; -1.971 ; -1.971 ; Fall ; C25M ; -; nDEVSEL ; C25M ; -2.680 ; -2.680 ; Fall ; C25M ; -; nIOSEL ; C25M ; -1.818 ; -1.818 ; Fall ; C25M ; -; nIOSTRB ; C25M ; -2.895 ; -2.895 ; Fall ; C25M ; -; nRES ; C25M ; -1.521 ; -1.521 ; Fall ; C25M ; +; MISO ; C25M ; -2.164 ; -2.164 ; Rise ; C25M ; +; RA[*] ; C25M ; -1.262 ; -1.262 ; Rise ; C25M ; +; RA[0] ; C25M ; -2.540 ; -2.540 ; Rise ; C25M ; +; RA[1] ; C25M ; -2.207 ; -2.207 ; Rise ; C25M ; +; RA[2] ; C25M ; -1.262 ; -1.262 ; Rise ; C25M ; +; RA[3] ; C25M ; -3.136 ; -3.136 ; Rise ; C25M ; +; RA[4] ; C25M ; -3.414 ; -3.414 ; Rise ; C25M ; +; RA[5] ; C25M ; -1.285 ; -1.285 ; Rise ; C25M ; +; RA[6] ; C25M ; -4.431 ; -4.431 ; Rise ; C25M ; +; RA[7] ; C25M ; -2.369 ; -2.369 ; Rise ; C25M ; +; RA[8] ; C25M ; -2.159 ; -2.159 ; Rise ; C25M ; +; RA[9] ; C25M ; -2.400 ; -2.400 ; Rise ; C25M ; +; RA[10] ; C25M ; -2.550 ; -2.550 ; Rise ; C25M ; +; RA[11] ; C25M ; -2.589 ; -2.589 ; Rise ; C25M ; +; RA[12] ; C25M ; -2.584 ; -2.584 ; Rise ; C25M ; +; RA[13] ; C25M ; -2.387 ; -2.387 ; Rise ; C25M ; +; RA[14] ; C25M ; -2.139 ; -2.139 ; Rise ; C25M ; +; RA[15] ; C25M ; -2.213 ; -2.213 ; Rise ; C25M ; +; RD[*] ; C25M ; -2.496 ; -2.496 ; Rise ; C25M ; +; RD[0] ; C25M ; -2.763 ; -2.763 ; Rise ; C25M ; +; RD[1] ; C25M ; -2.496 ; -2.496 ; Rise ; C25M ; +; RD[2] ; C25M ; -3.534 ; -3.534 ; Rise ; C25M ; +; RD[3] ; C25M ; -3.040 ; -3.040 ; Rise ; C25M ; +; RD[4] ; C25M ; -2.714 ; -2.714 ; Rise ; C25M ; +; RD[5] ; C25M ; -3.205 ; -3.205 ; Rise ; C25M ; +; RD[6] ; C25M ; -3.000 ; -3.000 ; Rise ; C25M ; +; RD[7] ; C25M ; -3.257 ; -3.257 ; Rise ; C25M ; +; nWE ; C25M ; -3.313 ; -3.313 ; Rise ; C25M ; +; PHI0 ; C25M ; -1.324 ; -1.324 ; Fall ; C25M ; +; nDEVSEL ; C25M ; -1.860 ; -1.860 ; Fall ; C25M ; +; nIOSEL ; C25M ; -2.526 ; -2.526 ; Fall ; C25M ; +; nIOSTRB ; C25M ; -1.540 ; -1.540 ; Fall ; C25M ; +; nRES ; C25M ; -1.532 ; -1.532 ; Fall ; C25M ; +-----------+------------+--------+--------+------------+-----------------+ @@ -556,52 +640,40 @@ No paths to report. +-----------+------------+--------+--------+------------+-----------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+--------+--------+------------+-----------------+ -; DQMH ; C25M ; 12.172 ; 12.172 ; Rise ; C25M ; -; DQML ; C25M ; 12.191 ; 12.191 ; Rise ; C25M ; -; FCK ; C25M ; 6.853 ; 6.853 ; Rise ; C25M ; -; MOSI ; C25M ; 7.987 ; 7.987 ; Rise ; C25M ; -; RCKE ; C25M ; 7.918 ; 7.918 ; Rise ; C25M ; -; RD[*] ; C25M ; 13.512 ; 13.512 ; Rise ; C25M ; -; RD[0] ; C25M ; 13.512 ; 13.512 ; Rise ; C25M ; -; RD[1] ; C25M ; 12.527 ; 12.527 ; Rise ; C25M ; -; RD[2] ; C25M ; 13.043 ; 13.043 ; Rise ; C25M ; -; RD[3] ; C25M ; 13.512 ; 13.512 ; Rise ; C25M ; -; RD[4] ; C25M ; 13.512 ; 13.512 ; Rise ; C25M ; -; RD[5] ; C25M ; 13.043 ; 13.043 ; Rise ; C25M ; -; RD[6] ; C25M ; 13.512 ; 13.512 ; Rise ; C25M ; -; RD[7] ; C25M ; 12.527 ; 12.527 ; Rise ; C25M ; -; RDdir ; C25M ; 13.043 ; 13.043 ; Rise ; C25M ; -; SA[*] ; C25M ; 16.756 ; 16.756 ; Rise ; C25M ; -; SA[0] ; C25M ; 16.756 ; 16.756 ; Rise ; C25M ; -; SA[1] ; C25M ; 13.973 ; 13.973 ; Rise ; C25M ; -; SA[2] ; C25M ; 16.541 ; 16.541 ; Rise ; C25M ; -; SA[3] ; C25M ; 15.322 ; 15.322 ; Rise ; C25M ; -; SA[4] ; C25M ; 15.597 ; 15.597 ; Rise ; C25M ; -; SA[5] ; C25M ; 13.493 ; 13.493 ; Rise ; C25M ; -; SA[6] ; C25M ; 12.412 ; 12.412 ; Rise ; C25M ; -; SA[7] ; C25M ; 13.879 ; 13.879 ; Rise ; C25M ; -; SA[8] ; C25M ; 14.066 ; 14.066 ; Rise ; C25M ; -; SA[9] ; C25M ; 12.811 ; 12.811 ; Rise ; C25M ; -; SA[10] ; C25M ; 13.571 ; 13.571 ; Rise ; C25M ; -; SA[11] ; C25M ; 13.522 ; 13.522 ; Rise ; C25M ; -; SA[12] ; C25M ; 11.810 ; 11.810 ; Rise ; C25M ; -; SBA[*] ; C25M ; 11.477 ; 11.477 ; Rise ; C25M ; -; SBA[1] ; C25M ; 11.477 ; 11.477 ; Rise ; C25M ; -; SD[*] ; C25M ; 9.110 ; 9.110 ; Rise ; C25M ; -; SD[0] ; C25M ; 8.588 ; 8.588 ; Rise ; C25M ; -; SD[1] ; C25M ; 8.588 ; 8.588 ; Rise ; C25M ; -; SD[2] ; C25M ; 8.688 ; 8.688 ; Rise ; C25M ; -; SD[3] ; C25M ; 9.110 ; 9.110 ; Rise ; C25M ; -; SD[4] ; C25M ; 8.588 ; 8.588 ; Rise ; C25M ; -; SD[5] ; C25M ; 8.688 ; 8.688 ; Rise ; C25M ; -; SD[6] ; C25M ; 6.847 ; 6.847 ; Rise ; C25M ; -; SD[7] ; C25M ; 6.848 ; 6.848 ; Rise ; C25M ; -; nCAS ; C25M ; 8.531 ; 8.531 ; Rise ; C25M ; -; nFCS ; C25M ; 6.820 ; 6.820 ; Rise ; C25M ; -; nRAS ; C25M ; 8.122 ; 8.122 ; Rise ; C25M ; -; nRCS ; C25M ; 6.813 ; 6.813 ; Rise ; C25M ; -; nRESout ; C25M ; 9.088 ; 9.088 ; Rise ; C25M ; -; nSWE ; C25M ; 7.886 ; 7.886 ; Rise ; C25M ; +; DQMH ; C25M ; 14.543 ; 14.543 ; Rise ; C25M ; +; DQML ; C25M ; 14.323 ; 14.323 ; Rise ; C25M ; +; FCK ; C25M ; 6.814 ; 6.814 ; Rise ; C25M ; +; MOSI ; C25M ; 7.979 ; 7.979 ; Rise ; C25M ; +; RCKE ; C25M ; 7.479 ; 7.479 ; Rise ; C25M ; +; RD[*] ; C25M ; 12.638 ; 12.638 ; Rise ; C25M ; +; RD[0] ; C25M ; 12.638 ; 12.638 ; Rise ; C25M ; +; RD[1] ; C25M ; 12.638 ; 12.638 ; Rise ; C25M ; +; RD[2] ; C25M ; 12.608 ; 12.608 ; Rise ; C25M ; +; RD[3] ; C25M ; 12.638 ; 12.638 ; Rise ; C25M ; +; RD[4] ; C25M ; 12.638 ; 12.638 ; Rise ; C25M ; +; RD[5] ; C25M ; 12.638 ; 12.638 ; Rise ; C25M ; +; RD[6] ; C25M ; 12.638 ; 12.638 ; Rise ; C25M ; +; RD[7] ; C25M ; 12.608 ; 12.608 ; Rise ; C25M ; +; RDdir ; C25M ; 12.022 ; 12.022 ; Rise ; C25M ; +; SA[*] ; C25M ; 11.933 ; 11.933 ; Rise ; C25M ; +; SA[12] ; C25M ; 11.933 ; 11.933 ; Rise ; C25M ; +; SBA[*] ; C25M ; 10.649 ; 10.649 ; Rise ; C25M ; +; SBA[1] ; C25M ; 10.649 ; 10.649 ; Rise ; C25M ; +; SD[*] ; C25M ; 8.298 ; 8.298 ; Rise ; C25M ; +; SD[0] ; C25M ; 8.056 ; 8.056 ; Rise ; C25M ; +; SD[1] ; C25M ; 8.298 ; 8.298 ; Rise ; C25M ; +; SD[2] ; C25M ; 8.056 ; 8.056 ; Rise ; C25M ; +; SD[3] ; C25M ; 6.880 ; 6.880 ; Rise ; C25M ; +; SD[4] ; C25M ; 8.298 ; 8.298 ; Rise ; C25M ; +; SD[5] ; C25M ; 8.298 ; 8.298 ; Rise ; C25M ; +; SD[6] ; C25M ; 6.858 ; 6.858 ; Rise ; C25M ; +; SD[7] ; C25M ; 6.854 ; 6.854 ; Rise ; C25M ; +; nCAS ; C25M ; 7.921 ; 7.921 ; Rise ; C25M ; +; nFCS ; C25M ; 8.004 ; 8.004 ; Rise ; C25M ; +; nRAS ; C25M ; 8.131 ; 8.131 ; Rise ; C25M ; +; nRCS ; C25M ; 7.921 ; 7.921 ; Rise ; C25M ; +; nRESout ; C25M ; 8.754 ; 8.754 ; Rise ; C25M ; +; nSWE ; C25M ; 7.935 ; 7.935 ; Rise ; C25M ; +-----------+------------+--------+--------+------------+-----------------+ @@ -610,52 +682,40 @@ No paths to report. +-----------+------------+--------+--------+------------+-----------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+--------+--------+------------+-----------------+ -; DQMH ; C25M ; 9.531 ; 9.531 ; Rise ; C25M ; -; DQML ; C25M ; 9.550 ; 9.550 ; Rise ; C25M ; -; FCK ; C25M ; 6.853 ; 6.853 ; Rise ; C25M ; -; MOSI ; C25M ; 7.987 ; 7.987 ; Rise ; C25M ; -; RCKE ; C25M ; 7.918 ; 7.918 ; Rise ; C25M ; -; RD[*] ; C25M ; 9.051 ; 9.051 ; Rise ; C25M ; -; RD[0] ; C25M ; 10.036 ; 10.036 ; Rise ; C25M ; -; RD[1] ; C25M ; 9.051 ; 9.051 ; Rise ; C25M ; -; RD[2] ; C25M ; 9.567 ; 9.567 ; Rise ; C25M ; -; RD[3] ; C25M ; 10.036 ; 10.036 ; Rise ; C25M ; -; RD[4] ; C25M ; 10.036 ; 10.036 ; Rise ; C25M ; -; RD[5] ; C25M ; 9.567 ; 9.567 ; Rise ; C25M ; -; RD[6] ; C25M ; 10.036 ; 10.036 ; Rise ; C25M ; -; RD[7] ; C25M ; 9.051 ; 9.051 ; Rise ; C25M ; -; RDdir ; C25M ; 9.567 ; 9.567 ; Rise ; C25M ; -; SA[*] ; C25M ; 9.091 ; 9.091 ; Rise ; C25M ; -; SA[0] ; C25M ; 11.423 ; 11.423 ; Rise ; C25M ; -; SA[1] ; C25M ; 10.716 ; 10.716 ; Rise ; C25M ; -; SA[2] ; C25M ; 12.021 ; 12.021 ; Rise ; C25M ; -; SA[3] ; C25M ; 11.889 ; 11.889 ; Rise ; C25M ; -; SA[4] ; C25M ; 10.185 ; 10.185 ; Rise ; C25M ; -; SA[5] ; C25M ; 10.027 ; 10.027 ; Rise ; C25M ; -; SA[6] ; C25M ; 9.091 ; 9.091 ; Rise ; C25M ; -; SA[7] ; C25M ; 10.026 ; 10.026 ; Rise ; C25M ; -; SA[8] ; C25M ; 10.534 ; 10.534 ; Rise ; C25M ; -; SA[9] ; C25M ; 9.380 ; 9.380 ; Rise ; C25M ; -; SA[10] ; C25M ; 10.249 ; 10.249 ; Rise ; C25M ; -; SA[11] ; C25M ; 10.200 ; 10.200 ; Rise ; C25M ; -; SA[12] ; C25M ; 10.171 ; 10.171 ; Rise ; C25M ; -; SBA[*] ; C25M ; 10.707 ; 10.707 ; Rise ; C25M ; -; SBA[1] ; C25M ; 10.707 ; 10.707 ; Rise ; C25M ; -; SD[*] ; C25M ; 6.847 ; 6.847 ; Rise ; C25M ; -; SD[0] ; C25M ; 8.588 ; 8.588 ; Rise ; C25M ; -; SD[1] ; C25M ; 8.588 ; 8.588 ; Rise ; C25M ; -; SD[2] ; C25M ; 8.688 ; 8.688 ; Rise ; C25M ; -; SD[3] ; C25M ; 9.110 ; 9.110 ; Rise ; C25M ; -; SD[4] ; C25M ; 8.588 ; 8.588 ; Rise ; C25M ; -; SD[5] ; C25M ; 8.688 ; 8.688 ; Rise ; C25M ; -; SD[6] ; C25M ; 6.847 ; 6.847 ; Rise ; C25M ; -; SD[7] ; C25M ; 6.848 ; 6.848 ; Rise ; C25M ; -; nCAS ; C25M ; 8.531 ; 8.531 ; Rise ; C25M ; -; nFCS ; C25M ; 6.820 ; 6.820 ; Rise ; C25M ; -; nRAS ; C25M ; 8.122 ; 8.122 ; Rise ; C25M ; -; nRCS ; C25M ; 6.813 ; 6.813 ; Rise ; C25M ; -; nRESout ; C25M ; 9.088 ; 9.088 ; Rise ; C25M ; -; nSWE ; C25M ; 7.886 ; 7.886 ; Rise ; C25M ; +; DQMH ; C25M ; 10.913 ; 10.913 ; Rise ; C25M ; +; DQML ; C25M ; 10.693 ; 10.693 ; Rise ; C25M ; +; FCK ; C25M ; 6.814 ; 6.814 ; Rise ; C25M ; +; MOSI ; C25M ; 7.979 ; 7.979 ; Rise ; C25M ; +; RCKE ; C25M ; 7.479 ; 7.479 ; Rise ; C25M ; +; RD[*] ; C25M ; 8.939 ; 8.939 ; Rise ; C25M ; +; RD[0] ; C25M ; 8.969 ; 8.969 ; Rise ; C25M ; +; RD[1] ; C25M ; 8.969 ; 8.969 ; Rise ; C25M ; +; RD[2] ; C25M ; 8.939 ; 8.939 ; Rise ; C25M ; +; RD[3] ; C25M ; 8.969 ; 8.969 ; Rise ; C25M ; +; RD[4] ; C25M ; 8.969 ; 8.969 ; Rise ; C25M ; +; RD[5] ; C25M ; 8.969 ; 8.969 ; Rise ; C25M ; +; RD[6] ; C25M ; 8.969 ; 8.969 ; Rise ; C25M ; +; RD[7] ; C25M ; 8.939 ; 8.939 ; Rise ; C25M ; +; RDdir ; C25M ; 8.353 ; 8.353 ; Rise ; C25M ; +; SA[*] ; C25M ; 9.725 ; 9.725 ; Rise ; C25M ; +; SA[12] ; C25M ; 9.725 ; 9.725 ; Rise ; C25M ; +; SBA[*] ; C25M ; 10.149 ; 10.149 ; Rise ; C25M ; +; SBA[1] ; C25M ; 10.149 ; 10.149 ; Rise ; C25M ; +; SD[*] ; C25M ; 6.854 ; 6.854 ; Rise ; C25M ; +; SD[0] ; C25M ; 8.056 ; 8.056 ; Rise ; C25M ; +; SD[1] ; C25M ; 8.298 ; 8.298 ; Rise ; C25M ; +; SD[2] ; C25M ; 8.056 ; 8.056 ; Rise ; C25M ; +; SD[3] ; C25M ; 6.880 ; 6.880 ; Rise ; C25M ; +; SD[4] ; C25M ; 8.298 ; 8.298 ; Rise ; C25M ; +; SD[5] ; C25M ; 8.298 ; 8.298 ; Rise ; C25M ; +; SD[6] ; C25M ; 6.858 ; 6.858 ; Rise ; C25M ; +; SD[7] ; C25M ; 6.854 ; 6.854 ; Rise ; C25M ; +; nCAS ; C25M ; 7.921 ; 7.921 ; Rise ; C25M ; +; nFCS ; C25M ; 8.004 ; 8.004 ; Rise ; C25M ; +; nRAS ; C25M ; 8.131 ; 8.131 ; Rise ; C25M ; +; nRCS ; C25M ; 7.921 ; 7.921 ; Rise ; C25M ; +; nRESout ; C25M ; 8.754 ; 8.754 ; Rise ; C25M ; +; nSWE ; C25M ; 7.935 ; 7.935 ; Rise ; C25M ; +-----------+------------+--------+--------+------------+-----------------+ @@ -664,51 +724,51 @@ No paths to report. +------------+-------------+--------+----+----+--------+ ; Input Port ; Output Port ; RR ; RF ; FR ; FF ; +------------+-------------+--------+----+----+--------+ -; PHI0 ; RD[0] ; 14.757 ; ; ; 14.757 ; -; PHI0 ; RD[1] ; 13.772 ; ; ; 13.772 ; -; PHI0 ; RD[2] ; 14.288 ; ; ; 14.288 ; -; PHI0 ; RD[3] ; 14.757 ; ; ; 14.757 ; -; PHI0 ; RD[4] ; 14.757 ; ; ; 14.757 ; -; PHI0 ; RD[5] ; 14.288 ; ; ; 14.288 ; -; PHI0 ; RD[6] ; 14.757 ; ; ; 14.757 ; -; PHI0 ; RD[7] ; 13.772 ; ; ; 13.772 ; -; PHI0 ; RDdir ; 14.288 ; ; ; 14.288 ; -; nDEVSEL ; RD[0] ; 13.880 ; ; ; 13.880 ; -; nDEVSEL ; RD[1] ; 12.895 ; ; ; 12.895 ; -; nDEVSEL ; RD[2] ; 13.411 ; ; ; 13.411 ; -; nDEVSEL ; RD[3] ; 13.880 ; ; ; 13.880 ; -; nDEVSEL ; RD[4] ; 13.880 ; ; ; 13.880 ; -; nDEVSEL ; RD[5] ; 13.411 ; ; ; 13.411 ; -; nDEVSEL ; RD[6] ; 13.880 ; ; ; 13.880 ; -; nDEVSEL ; RD[7] ; 12.895 ; ; ; 12.895 ; -; nDEVSEL ; RDdir ; 13.411 ; ; ; 13.411 ; -; nIOSEL ; RD[0] ; 11.646 ; ; ; 11.646 ; -; nIOSEL ; RD[1] ; 10.661 ; ; ; 10.661 ; -; nIOSEL ; RD[2] ; 11.177 ; ; ; 11.177 ; -; nIOSEL ; RD[3] ; 11.646 ; ; ; 11.646 ; -; nIOSEL ; RD[4] ; 11.646 ; ; ; 11.646 ; -; nIOSEL ; RD[5] ; 11.177 ; ; ; 11.177 ; -; nIOSEL ; RD[6] ; 11.646 ; ; ; 11.646 ; -; nIOSEL ; RD[7] ; 10.661 ; ; ; 10.661 ; -; nIOSEL ; RDdir ; 11.177 ; ; ; 11.177 ; -; nIOSTRB ; RD[0] ; 12.844 ; ; ; 12.844 ; -; nIOSTRB ; RD[1] ; 11.859 ; ; ; 11.859 ; -; nIOSTRB ; RD[2] ; 12.375 ; ; ; 12.375 ; -; nIOSTRB ; RD[3] ; 12.844 ; ; ; 12.844 ; -; nIOSTRB ; RD[4] ; 12.844 ; ; ; 12.844 ; -; nIOSTRB ; RD[5] ; 12.375 ; ; ; 12.375 ; -; nIOSTRB ; RD[6] ; 12.844 ; ; ; 12.844 ; -; nIOSTRB ; RD[7] ; 11.859 ; ; ; 11.859 ; -; nIOSTRB ; RDdir ; 12.375 ; ; ; 12.375 ; -; nWE ; RD[0] ; 13.939 ; ; ; 13.939 ; -; nWE ; RD[1] ; 12.954 ; ; ; 12.954 ; -; nWE ; RD[2] ; 13.470 ; ; ; 13.470 ; -; nWE ; RD[3] ; 13.939 ; ; ; 13.939 ; -; nWE ; RD[4] ; 13.939 ; ; ; 13.939 ; -; nWE ; RD[5] ; 13.470 ; ; ; 13.470 ; -; nWE ; RD[6] ; 13.939 ; ; ; 13.939 ; -; nWE ; RD[7] ; 12.954 ; ; ; 12.954 ; -; nWE ; RDdir ; 13.470 ; ; ; 13.470 ; +; PHI0 ; RD[0] ; 10.726 ; ; ; 10.726 ; +; PHI0 ; RD[1] ; 10.726 ; ; ; 10.726 ; +; PHI0 ; RD[2] ; 10.696 ; ; ; 10.696 ; +; PHI0 ; RD[3] ; 10.726 ; ; ; 10.726 ; +; PHI0 ; RD[4] ; 10.726 ; ; ; 10.726 ; +; PHI0 ; RD[5] ; 10.726 ; ; ; 10.726 ; +; PHI0 ; RD[6] ; 10.726 ; ; ; 10.726 ; +; PHI0 ; RD[7] ; 10.696 ; ; ; 10.696 ; +; PHI0 ; RDdir ; 10.110 ; ; ; 10.110 ; +; nDEVSEL ; RD[0] ; 12.243 ; ; ; 12.243 ; +; nDEVSEL ; RD[1] ; 12.243 ; ; ; 12.243 ; +; nDEVSEL ; RD[2] ; 12.213 ; ; ; 12.213 ; +; nDEVSEL ; RD[3] ; 12.243 ; ; ; 12.243 ; +; nDEVSEL ; RD[4] ; 12.243 ; ; ; 12.243 ; +; nDEVSEL ; RD[5] ; 12.243 ; ; ; 12.243 ; +; nDEVSEL ; RD[6] ; 12.243 ; ; ; 12.243 ; +; nDEVSEL ; RD[7] ; 12.213 ; ; ; 12.213 ; +; nDEVSEL ; RDdir ; 11.627 ; ; ; 11.627 ; +; nIOSEL ; RD[0] ; 10.082 ; ; ; 10.082 ; +; nIOSEL ; RD[1] ; 10.082 ; ; ; 10.082 ; +; nIOSEL ; RD[2] ; 10.052 ; ; ; 10.052 ; +; nIOSEL ; RD[3] ; 10.082 ; ; ; 10.082 ; +; nIOSEL ; RD[4] ; 10.082 ; ; ; 10.082 ; +; nIOSEL ; RD[5] ; 10.082 ; ; ; 10.082 ; +; nIOSEL ; RD[6] ; 10.082 ; ; ; 10.082 ; +; nIOSEL ; RD[7] ; 10.052 ; ; ; 10.052 ; +; nIOSEL ; RDdir ; 9.466 ; ; ; 9.466 ; +; nIOSTRB ; RD[0] ; 11.819 ; ; ; 11.819 ; +; nIOSTRB ; RD[1] ; 11.819 ; ; ; 11.819 ; +; nIOSTRB ; RD[2] ; 11.789 ; ; ; 11.789 ; +; nIOSTRB ; RD[3] ; 11.819 ; ; ; 11.819 ; +; nIOSTRB ; RD[4] ; 11.819 ; ; ; 11.819 ; +; nIOSTRB ; RD[5] ; 11.819 ; ; ; 11.819 ; +; nIOSTRB ; RD[6] ; 11.819 ; ; ; 11.819 ; +; nIOSTRB ; RD[7] ; 11.789 ; ; ; 11.789 ; +; nIOSTRB ; RDdir ; 11.203 ; ; ; 11.203 ; +; nWE ; RD[0] ; 10.429 ; ; ; 10.429 ; +; nWE ; RD[1] ; 10.429 ; ; ; 10.429 ; +; nWE ; RD[2] ; 10.399 ; ; ; 10.399 ; +; nWE ; RD[3] ; 10.429 ; ; ; 10.429 ; +; nWE ; RD[4] ; 10.429 ; ; ; 10.429 ; +; nWE ; RD[5] ; 10.429 ; ; ; 10.429 ; +; nWE ; RD[6] ; 10.429 ; ; ; 10.429 ; +; nWE ; RD[7] ; 10.399 ; ; ; 10.399 ; +; nWE ; RDdir ; 9.813 ; ; ; 9.813 ; +------------+-------------+--------+----+----+--------+ @@ -717,51 +777,51 @@ No paths to report. +------------+-------------+--------+----+----+--------+ ; Input Port ; Output Port ; RR ; RF ; FR ; FF ; +------------+-------------+--------+----+----+--------+ -; PHI0 ; RD[0] ; 14.757 ; ; ; 14.757 ; -; PHI0 ; RD[1] ; 13.772 ; ; ; 13.772 ; -; PHI0 ; RD[2] ; 14.288 ; ; ; 14.288 ; -; PHI0 ; RD[3] ; 14.757 ; ; ; 14.757 ; -; PHI0 ; RD[4] ; 14.757 ; ; ; 14.757 ; -; PHI0 ; RD[5] ; 14.288 ; ; ; 14.288 ; -; PHI0 ; RD[6] ; 14.757 ; ; ; 14.757 ; -; PHI0 ; RD[7] ; 13.772 ; ; ; 13.772 ; -; PHI0 ; RDdir ; 14.288 ; ; ; 14.288 ; -; nDEVSEL ; RD[0] ; 13.880 ; ; ; 13.880 ; -; nDEVSEL ; RD[1] ; 12.895 ; ; ; 12.895 ; -; nDEVSEL ; RD[2] ; 13.411 ; ; ; 13.411 ; -; nDEVSEL ; RD[3] ; 13.880 ; ; ; 13.880 ; -; nDEVSEL ; RD[4] ; 13.880 ; ; ; 13.880 ; -; nDEVSEL ; RD[5] ; 13.411 ; ; ; 13.411 ; -; nDEVSEL ; RD[6] ; 13.880 ; ; ; 13.880 ; -; nDEVSEL ; RD[7] ; 12.895 ; ; ; 12.895 ; -; nDEVSEL ; RDdir ; 13.411 ; ; ; 13.411 ; -; nIOSEL ; RD[0] ; 11.646 ; ; ; 11.646 ; -; nIOSEL ; RD[1] ; 10.661 ; ; ; 10.661 ; -; nIOSEL ; RD[2] ; 11.177 ; ; ; 11.177 ; -; nIOSEL ; RD[3] ; 11.646 ; ; ; 11.646 ; -; nIOSEL ; RD[4] ; 11.646 ; ; ; 11.646 ; -; nIOSEL ; RD[5] ; 11.177 ; ; ; 11.177 ; -; nIOSEL ; RD[6] ; 11.646 ; ; ; 11.646 ; -; nIOSEL ; RD[7] ; 10.661 ; ; ; 10.661 ; -; nIOSEL ; RDdir ; 11.177 ; ; ; 11.177 ; -; nIOSTRB ; RD[0] ; 12.844 ; ; ; 12.844 ; -; nIOSTRB ; RD[1] ; 11.859 ; ; ; 11.859 ; -; nIOSTRB ; RD[2] ; 12.375 ; ; ; 12.375 ; -; nIOSTRB ; RD[3] ; 12.844 ; ; ; 12.844 ; -; nIOSTRB ; RD[4] ; 12.844 ; ; ; 12.844 ; -; nIOSTRB ; RD[5] ; 12.375 ; ; ; 12.375 ; -; nIOSTRB ; RD[6] ; 12.844 ; ; ; 12.844 ; -; nIOSTRB ; RD[7] ; 11.859 ; ; ; 11.859 ; -; nIOSTRB ; RDdir ; 12.375 ; ; ; 12.375 ; -; nWE ; RD[0] ; 13.939 ; ; ; 13.939 ; -; nWE ; RD[1] ; 12.954 ; ; ; 12.954 ; -; nWE ; RD[2] ; 13.470 ; ; ; 13.470 ; -; nWE ; RD[3] ; 13.939 ; ; ; 13.939 ; -; nWE ; RD[4] ; 13.939 ; ; ; 13.939 ; -; nWE ; RD[5] ; 13.470 ; ; ; 13.470 ; -; nWE ; RD[6] ; 13.939 ; ; ; 13.939 ; -; nWE ; RD[7] ; 12.954 ; ; ; 12.954 ; -; nWE ; RDdir ; 13.470 ; ; ; 13.470 ; +; PHI0 ; RD[0] ; 10.726 ; ; ; 10.726 ; +; PHI0 ; RD[1] ; 10.726 ; ; ; 10.726 ; +; PHI0 ; RD[2] ; 10.696 ; ; ; 10.696 ; +; PHI0 ; RD[3] ; 10.726 ; ; ; 10.726 ; +; PHI0 ; RD[4] ; 10.726 ; ; ; 10.726 ; +; PHI0 ; RD[5] ; 10.726 ; ; ; 10.726 ; +; PHI0 ; RD[6] ; 10.726 ; ; ; 10.726 ; +; PHI0 ; RD[7] ; 10.696 ; ; ; 10.696 ; +; PHI0 ; RDdir ; 10.110 ; ; ; 10.110 ; +; nDEVSEL ; RD[0] ; 12.243 ; ; ; 12.243 ; +; nDEVSEL ; RD[1] ; 12.243 ; ; ; 12.243 ; +; nDEVSEL ; RD[2] ; 12.213 ; ; ; 12.213 ; +; nDEVSEL ; RD[3] ; 12.243 ; ; ; 12.243 ; +; nDEVSEL ; RD[4] ; 12.243 ; ; ; 12.243 ; +; nDEVSEL ; RD[5] ; 12.243 ; ; ; 12.243 ; +; nDEVSEL ; RD[6] ; 12.243 ; ; ; 12.243 ; +; nDEVSEL ; RD[7] ; 12.213 ; ; ; 12.213 ; +; nDEVSEL ; RDdir ; 11.627 ; ; ; 11.627 ; +; nIOSEL ; RD[0] ; 10.082 ; ; ; 10.082 ; +; nIOSEL ; RD[1] ; 10.082 ; ; ; 10.082 ; +; nIOSEL ; RD[2] ; 10.052 ; ; ; 10.052 ; +; nIOSEL ; RD[3] ; 10.082 ; ; ; 10.082 ; +; nIOSEL ; RD[4] ; 10.082 ; ; ; 10.082 ; +; nIOSEL ; RD[5] ; 10.082 ; ; ; 10.082 ; +; nIOSEL ; RD[6] ; 10.082 ; ; ; 10.082 ; +; nIOSEL ; RD[7] ; 10.052 ; ; ; 10.052 ; +; nIOSEL ; RDdir ; 9.466 ; ; ; 9.466 ; +; nIOSTRB ; RD[0] ; 11.819 ; ; ; 11.819 ; +; nIOSTRB ; RD[1] ; 11.819 ; ; ; 11.819 ; +; nIOSTRB ; RD[2] ; 11.789 ; ; ; 11.789 ; +; nIOSTRB ; RD[3] ; 11.819 ; ; ; 11.819 ; +; nIOSTRB ; RD[4] ; 11.819 ; ; ; 11.819 ; +; nIOSTRB ; RD[5] ; 11.819 ; ; ; 11.819 ; +; nIOSTRB ; RD[6] ; 11.819 ; ; ; 11.819 ; +; nIOSTRB ; RD[7] ; 11.789 ; ; ; 11.789 ; +; nIOSTRB ; RDdir ; 11.203 ; ; ; 11.203 ; +; nWE ; RD[0] ; 10.429 ; ; ; 10.429 ; +; nWE ; RD[1] ; 10.429 ; ; ; 10.429 ; +; nWE ; RD[2] ; 10.399 ; ; ; 10.399 ; +; nWE ; RD[3] ; 10.429 ; ; ; 10.429 ; +; nWE ; RD[4] ; 10.429 ; ; ; 10.429 ; +; nWE ; RD[5] ; 10.429 ; ; ; 10.429 ; +; nWE ; RD[6] ; 10.429 ; ; ; 10.429 ; +; nWE ; RD[7] ; 10.399 ; ; ; 10.399 ; +; nWE ; RDdir ; 9.813 ; ; ; 9.813 ; +------------+-------------+--------+----+----+--------+ @@ -770,10 +830,10 @@ No paths to report. +-----------+------------+-------+------+------------+-----------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+-------+------+------------+-----------------+ -; MOSI ; C25M ; 6.777 ; ; Rise ; C25M ; -; SD[*] ; C25M ; 6.957 ; ; Rise ; C25M ; -; SD[6] ; C25M ; 6.957 ; ; Rise ; C25M ; -; SD[7] ; C25M ; 6.957 ; ; Rise ; C25M ; +; MOSI ; C25M ; 7.526 ; ; Rise ; C25M ; +; SD[*] ; C25M ; 6.349 ; ; Rise ; C25M ; +; SD[6] ; C25M ; 6.349 ; ; Rise ; C25M ; +; SD[7] ; C25M ; 6.349 ; ; Rise ; C25M ; +-----------+------------+-------+------+------------+-----------------+ @@ -782,10 +842,10 @@ No paths to report. +-----------+------------+-------+------+------------+-----------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+-------+------+------------+-----------------+ -; MOSI ; C25M ; 6.777 ; ; Rise ; C25M ; -; SD[*] ; C25M ; 6.957 ; ; Rise ; C25M ; -; SD[6] ; C25M ; 6.957 ; ; Rise ; C25M ; -; SD[7] ; C25M ; 6.957 ; ; Rise ; C25M ; +; MOSI ; C25M ; 7.526 ; ; Rise ; C25M ; +; SD[*] ; C25M ; 6.349 ; ; Rise ; C25M ; +; SD[6] ; C25M ; 6.349 ; ; Rise ; C25M ; +; SD[7] ; C25M ; 6.349 ; ; Rise ; C25M ; +-----------+------------+-------+------+------------+-----------------+ @@ -794,10 +854,10 @@ No paths to report. +-----------+------------+-----------+-----------+------------+-----------------+ ; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; +-----------+------------+-----------+-----------+------------+-----------------+ -; MOSI ; C25M ; 6.777 ; ; Rise ; C25M ; -; SD[*] ; C25M ; 6.957 ; ; Rise ; C25M ; -; SD[6] ; C25M ; 6.957 ; ; Rise ; C25M ; -; SD[7] ; C25M ; 6.957 ; ; Rise ; C25M ; +; MOSI ; C25M ; 7.526 ; ; Rise ; C25M ; +; SD[*] ; C25M ; 6.349 ; ; Rise ; C25M ; +; SD[6] ; C25M ; 6.349 ; ; Rise ; C25M ; +; SD[7] ; C25M ; 6.349 ; ; Rise ; C25M ; +-----------+------------+-----------+-----------+------------+-----------------+ @@ -806,10 +866,10 @@ No paths to report. +-----------+------------+-----------+-----------+------------+-----------------+ ; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; +-----------+------------+-----------+-----------+------------+-----------------+ -; MOSI ; C25M ; 6.777 ; ; Rise ; C25M ; -; SD[*] ; C25M ; 6.957 ; ; Rise ; C25M ; -; SD[6] ; C25M ; 6.957 ; ; Rise ; C25M ; -; SD[7] ; C25M ; 6.957 ; ; Rise ; C25M ; +; MOSI ; C25M ; 7.526 ; ; Rise ; C25M ; +; SD[*] ; C25M ; 6.349 ; ; Rise ; C25M ; +; SD[6] ; C25M ; 6.349 ; ; Rise ; C25M ; +; SD[7] ; C25M ; 6.349 ; ; Rise ; C25M ; +-----------+------------+-----------+-----------+------------+-----------------+ @@ -818,7 +878,12 @@ No paths to report. +------------+----------+----------+----------+----------+----------+ ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; +------------+----------+----------+----------+----------+----------+ -; C25M ; C25M ; 2664 ; 5 ; 0 ; 0 ; +; ARCLK ; ARCLK ; 1 ; 0 ; 0 ; 0 ; +; C25M ; ARCLK ; 1 ; 0 ; 0 ; 0 ; +; C25M ; C25M ; 2727 ; 5 ; 0 ; 0 ; +; DRCLK ; C25M ; 2 ; 0 ; 0 ; 0 ; +; C25M ; DRCLK ; 1 ; 0 ; 0 ; 0 ; +; DRCLK ; DRCLK ; 1 ; 0 ; 0 ; 0 ; +------------+----------+----------+----------+----------+----------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. @@ -828,7 +893,12 @@ Entries labeled "false path" only account for clock-to-clock false paths and not +------------+----------+----------+----------+----------+----------+ ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; +------------+----------+----------+----------+----------+----------+ -; C25M ; C25M ; 2664 ; 5 ; 0 ; 0 ; +; ARCLK ; ARCLK ; 1 ; 0 ; 0 ; 0 ; +; C25M ; ARCLK ; 1 ; 0 ; 0 ; 0 ; +; C25M ; C25M ; 2727 ; 5 ; 0 ; 0 ; +; DRCLK ; C25M ; 2 ; 0 ; 0 ; 0 ; +; C25M ; DRCLK ; 1 ; 0 ; 0 ; 0 ; +; DRCLK ; DRCLK ; 1 ; 0 ; 0 ; 0 ; +------------+----------+----------+----------+----------+----------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. @@ -853,9 +923,9 @@ No dedicated SERDES Receiver circuitry present in device or used in design ; Illegal Clocks ; 0 ; 0 ; ; Unconstrained Clocks ; 0 ; 0 ; ; Unconstrained Input Ports ; 31 ; 31 ; -; Unconstrained Input Port Paths ; 107 ; 107 ; -; Unconstrained Output Ports ; 42 ; 42 ; -; Unconstrained Output Port Paths ; 181 ; 181 ; +; Unconstrained Input Port Paths ; 105 ; 105 ; +; Unconstrained Output Ports ; 30 ; 30 ; +; Unconstrained Output Port Paths ; 110 ; 110 ; +---------------------------------+-------+------+ @@ -865,7 +935,7 @@ No dedicated SERDES Receiver circuitry present in device or used in design Info: ******************************************************************* Info: Running Quartus II 32-bit TimeQuest Timing Analyzer Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - Info: Processing started: Fri Mar 19 07:33:17 2021 + Info: Processing started: Fri Mar 19 16:35:33 2021 Info: Command: quartus_sta GR8RAM -c GR8RAM Info: qsta_default_script.tcl version: #1 Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected @@ -876,30 +946,38 @@ Info (306005): Delay annotation completed successfully Critical Warning (332012): Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" Info (332105): Deriving Clocks + Info (332105): create_clock -period 1.000 -name DRCLK DRCLK + Info (332105): create_clock -period 1.000 -name ARCLK ARCLK Info (332105): create_clock -period 1.000 -name C25M C25M Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON Critical Warning (332148): Timing requirements not met -Info (332146): Worst-case setup slack is -9.506 +Info (332146): Worst-case setup slack is -99.000 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== - Info (332119): -9.506 -540.769 C25M -Info (332146): Worst-case hold slack is 1.639 + Info (332119): -99.000 -99.000 ARCLK + Info (332119): -99.000 -99.000 DRCLK + Info (332119): -9.555 -547.115 C25M +Info (332146): Worst-case hold slack is -16.276 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== - Info (332119): 1.639 0.000 C25M + Info (332119): -16.276 -16.276 ARCLK + Info (332119): -16.256 -16.256 DRCLK + Info (332119): 1.377 0.000 C25M Info (332140): No Recovery paths to report Info (332140): No Removal paths to report -Info (332146): Worst-case minimum pulse width slack is -2.289 +Info (332146): Worst-case minimum pulse width slack is -29.500 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== + Info (332119): -29.500 -59.000 ARCLK + Info (332119): -29.500 -59.000 DRCLK Info (332119): -2.289 -2.289 C25M Info (332001): The selected device family is not supported by the report_metastability command. Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings Info: Peak virtual memory: 275 megabytes - Info: Processing ended: Fri Mar 19 07:33:22 2021 + Info: Processing ended: Fri Mar 19 16:35:38 2021 Info: Elapsed time: 00:00:05 - Info: Total CPU time (on all processors): 00:00:05 + Info: Total CPU time (on all processors): 00:00:04 diff --git a/cpld/output_files/GR8RAM.sta.summary b/cpld/output_files/GR8RAM.sta.summary index 1567b0c..0e8de0b 100755 --- a/cpld/output_files/GR8RAM.sta.summary +++ b/cpld/output_files/GR8RAM.sta.summary @@ -2,14 +2,38 @@ TimeQuest Timing Analyzer Summary ------------------------------------------------------------ +Type : Setup 'ARCLK' +Slack : -99.000 +TNS : -99.000 + +Type : Setup 'DRCLK' +Slack : -99.000 +TNS : -99.000 + Type : Setup 'C25M' -Slack : -9.506 -TNS : -540.769 +Slack : -9.555 +TNS : -547.115 + +Type : Hold 'ARCLK' +Slack : -16.276 +TNS : -16.276 + +Type : Hold 'DRCLK' +Slack : -16.256 +TNS : -16.256 Type : Hold 'C25M' -Slack : 1.639 +Slack : 1.377 TNS : 0.000 +Type : Minimum Pulse Width 'ARCLK' +Slack : -29.500 +TNS : -59.000 + +Type : Minimum Pulse Width 'DRCLK' +Slack : -29.500 +TNS : -59.000 + Type : Minimum Pulse Width 'C25M' Slack : -2.289 TNS : -2.289