From 764b09ba6a085204c7c71ce2db86253b1facdbae Mon Sep 17 00:00:00 2001 From: Zane Kaminski Date: Sun, 16 Feb 2020 22:03:57 -0500 Subject: [PATCH] Comments, no actual changes to CPLD verilog --- cpld/GR8RAM.v | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/cpld/GR8RAM.v b/cpld/GR8RAM.v index 3899c78..8fcc1be 100755 --- a/cpld/GR8RAM.v +++ b/cpld/GR8RAM.v @@ -140,13 +140,14 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode, end end + /* DEVSEL register and IOSTRB ROM enable */ always @(posedge C7M, negedge nRES) begin if (~nRES) begin REGEN <= 0; IOROMEN <= 0; end else begin // Enable registers at end of S4 when IOSEL accessed (Cn00-CnFF). - if (S==4 & ~nIOSEL) REGEN <= 1; + if (S==4 & ~nIOSEL) REGEN <= 1'b1; // Enable IOSTRB ROM when accessing CnXX in IOSEL ROM. if (S==4 & ~nIOSEL) IOROMEN <= 1'b1;