From 862aeacf1dc41b742652d499bc05ff20ee4daa58 Mon Sep 17 00:00:00 2001 From: Zane Kaminski Date: Sat, 8 May 2021 10:16:39 -0400 Subject: [PATCH] Update Initialization Sequence --- Documentation/Initialization Sequence | 148 ++------------------------ 1 file changed, 11 insertions(+), 137 deletions(-) diff --git a/Documentation/Initialization Sequence b/Documentation/Initialization Sequence index 84abe2d..345e443 100644 --- a/Documentation/Initialization Sequence +++ b/Documentation/Initialization Sequence @@ -1,139 +1,13 @@ Init sequence -Init State SDRAM Flash IS Other --------------------------------------------------------------------------------- -$00000-$0FFBF Nothing Nothing 0 -$00000 NOP CKE /CS hi, CLK lo -... -$0FF90 NOP CKE /CS hi, CLK lo InitActv <= ~BODf -.... -$0FFA0 NOP CKE /CS lo, CLK lo -... -$0FFAF NOP CKE /CS lo, CLK lo - -$0FFB0-$0FFBF Init: Precharge Send read cmd ($03) 1 -$0FFB0 NOP CKE CLK lo, MOSI 0 (b7) -$0FFB1 NOP CKE CLK hi -$0FFB2 NOP CKE CLK lo, MOSI 0 (b6) -$0FFB3 PC all CLK hi -$0FFB4 NOP CKE CLK lo, MOSI 0 (b5) -$0FFB5 NOP CKE CLK hi -$0FFB6 NOP CKE CLK lo, MOSI 0 (b4) -$0FFB7 NOP CKE CLK hi -$0FFB8 NOP CKE CLK lo, MOSI 0 (b3) -$0FFB9 NOP CKE CLK hi -$0FFBA NOP CKE CLK lo, MOSI 0 (b2) -$0FFBB Load mode CLK hi -$0FFBC NOP CKE CLK lo, MOSI 1 (b1) -$0FFBD NOP CKE CLK hi -$0FFBE NOP CKE CLK lo, MOSI 1 (b0) -$0FFBF NOP CKE CLK hi - -$0FFC0-$0FFEF Init: mode & ref Send address ($000000) 2 -$0FFC0 NOP CKE CLK lo, MOSI 0 (b23) -$0FFC1 NOP CKE CLK hi -$0FFC2 NOP CKE CLK lo, MOSI 0 (b22) -$0FFC3 AREF CLK hi -$0FFC4 NOP CKE CLK lo, MOSI Firmware[1] (b21) -$0FFC5 NOP CKE CLK hi -$0FFC6 NOP CKE CLK lo, MOSI Firmware[0] (b20) -$0FFC7 NOP CKE CLK hi -$0FFC8 NOP CKE CLK lo, MOSI 0 (b19) -$0FFC9 NOP CKE CLK hi -$0FFCA NOP CKE CLK lo, MOSI 0 (b18) -$0FFCB AREF CLK hi -$0FFCC NOP CKE CLK lo, MOSI 0 (b17) -$0FFCD NOP CKE CLK hi -$0FFCE NOP CKE CLK lo, MOSI 0 (b16) -$0FFCF NOP CKE CLK hi -$0FFD0 NOP CKE CLK lo, MOSI 0 (b15) -$0FFD1 NOP CKE CLK hi -$0FFD2 NOP CKE CLK lo, MOSI 0 (b14) -$0FFD3 AREF CLK hi -$0FFD4 NOP CKE CLK lo, MOSI 0 (b13) -$0FFD5 NOP CKE CLK hi -$0FFD6 NOP CKE CLK lo, MOSI 0 (b12) -$0FFD7 NOP CKE CLK hi -$0FFD8 NOP CKE CLK lo, MOSI 0 (b11) -$0FFD9 NOP CKE CLK hi -$0FFDA NOP CKE CLK lo, MOSI 0 (b10) -$0FFDB AREF CLK hi -$0FFDC NOP CKE CLK lo, MOSI 0 (b9) -$0FFDD NOP CKE CLK hi -$0FFDE NOP CKE CLK lo, MOSI 0 (b8) -$0FFDF NOP CKE CLK hi -$0FFE0 NOP CKE CLK lo, MOSI 0 (b7) -$0FFE1 NOP CKE CLK hi -$0FFE2 NOP CKE CLK lo, MOSI 0 (b6) -$0FFE3 AREF CLK hi -$0FFE4 NOP CKE CLK lo, MOSI 0 (b5) -$0FFE5 NOP CKE CLK hi -$0FFE6 NOP CKE CLK lo, MOSI 0 (b4) -$0FFE7 NOP CKE CLK hi -$0FFE8 NOP CKE CLK lo, MOSI 0 (b3) -$0FFE9 NOP CKE CLK hi -$0FFEA NOP CKE CLK lo, MOSI 0 (b2) -$0FFEB AREF CLK hi -$0FFEC NOP CKE CLK lo, MOSI 0 (b1) -$0FFED NOP CKE CLK hi -$0FFEE NOP CKE CLK lo, MOSI 0 (b0) -$0FFEF NOP CKE CLK hi - -$0FFF0-$0FFFF Init: mode & ref 8 dummy clocks 2 -$0FFF0 NOP CKE CLK lo, MOSIOE 0 -$0FFF1 NOP CKE CLK hi -$0FFF2 NOP CKE CLK lo -$0FFF3 AREF CLK hi -$0FFF4 NOP CKE CLK lo -$0FFF5 NOP CKE CLK hi -$0FFF6 NOP CKE CLK lo -$0FFF7 NOP CKE CLK hi -$0FFF8 NOP CKE CLK lo -$0FFF9 NOP CKE CLK hi -$0FFFA NOP CKE CLK lo -$0FFFB AREF CLK hi -$0FFFC NOP CKE CLK lo -$0FFFD NOP CKE CLK hi -$0FFFE NOP CKE CLK lo -$0FFFF NOP CKE CLK hi - -$10000-$2FFFF Write ROM data Shift in read data 3 -$10000 NOP CKE CLK lo -$10001 NOP CKE CLK hi, get b7:6 of $000000 -$10002 NOP CKE CLK lo -$10003 AREF CLK hi, get b5:4 of $000000 -$10004 NOP CKE CLK lo -$10005 ACT CLK hi, get b3:2 of $000000 -$10006 NOP CKE CLK lo -$10007 WR AP CLK hi, get b1:0 of $000000 -$10008 NOP CKE CLK lo -$10009 NOP CKE CLK hi, get b7:6 of $000001 -$1000A NOP CKE CLK lo -$1000B AREF CLK hi, get b5:4 of $000001 -$1000C NOP CKE CLK lo -$1000D ACT CLK hi, get b3:2 of $000001 -$1000E NOP CKE CLK lo -$1000F WR AP CLK hi, get b1:0 of $000001 -... -$2FFF0 NOP CKE CLK lo -$2FFF1 NOP CKE CLK hi, get b7:6 of $003FFE -$2FFF2 NOP CKE CLK lo -$2FFF3 AREF CLK hi, get b5:4 of $003FFE -$2FFF4 NOP CKE CLK lo -$2FFF5 ACT CLK hi, get b3:2 of $003FFE -$2FFF6 NOP CKE CLK lo -$2FFF7 WR AP CLK hi, get b1:0 of $003FFE -$2FFF8 NOP CKE CLK lo -$2FFF9 NOP CKE CLK hi, get b7:6 of $003FFF -$2FFFA NOP CKE CLK lo -$2FFFB AREF CLK hi, get b5:4 of $003FFF -$2FFFC NOP CKE CLK lo -$2FFFD ACT CLK hi, get b3:2 of $003FFF -$2FFFE NOP CKE CLK lo -$2FFFF WR AP CLK hi, get b1:0 of $003FFF - -$30000 NOP CKE CLK lo, /CS hi 3 -$30001 NOP CKE CLK lo, /CS hi 3 -$30002 NOP CKE CLK lo, /CS hi 3 SDRAMActv <= InitActv && ~InitInterrupted - - +LS SDRAM Flash IS +------------------------------------------------------------------- +$0000-$1FCE Nothing Nothing 0 +$1FCF Init: Precharge Nothing 1 +$1FD0-$1FFA Init: AREF Pause SPI Select 4 +$1FFB Init: AREF Pause Dual Read (0x3B) 5 +$1FFC Init: AREF Pause A[23:16] (0) 5 +$1FFD Init: AREF Pause A[15:08] (FW in 14:13) 5 +$1FFE Init: AREF Pause A[07:00] (0) 5 +$1FFF Init: AREF Pause Dummy 5 +$2000-$3FFF Init: Write ROM Shift MISO into WRD 6