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https://github.com/garrettsworkshop/GR8RAM.git
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Some power improvements
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@ -1,7 +1,7 @@
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module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
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INTin, INTout, DMAin, DMAout,
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nNMIout, nIRQout, nRDYout, nINHout, RWout, nDMAout,
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RA, nWE, RD, RAdir, RDdir, nIOSEL, nDEVSEL, nIOSTRB,
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GNDout1, GNDout2, nIRQout, RWout, nDMAout,
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RA, PU, nWE, RD, RAdir, RDdir, nIOSEL, nDEVSEL, nIOSTRB,
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SBA, SA, nRCS, nRAS, nCAS, nSWE, DQML, DQMH, RCKE, SD,
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nFCS, FCK, MISO, MOSI);
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@ -19,7 +19,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
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/* Firmware select */
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input [1:0] SetFW;
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wire [1:0] SetROM = ~SetFW[1:0];
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wire SetENRestore = SetROM[1:0]==1'b11;
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wire SetENRestore = SetROM[1:0]==2'b11;
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wire SetEN24bit = SetROM[1];
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/* State counter from PHI0 rising edge */
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@ -53,12 +53,13 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
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input nIOSEL, nDEVSEL, nIOSTRB;
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/* Apple address bus */
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input [15:0] RA; reg CXXXr;
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input [15:0] RA;
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input nWE;
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always @(posedge PHI0) CXXXr <= RA[15:12]==4'hC;
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input PU;
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wire RA4 = RA[4] && PU;
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/* Apple select signals */
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wire RAMExists = (!SetEN24bit || !Addr[23]);
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wire RAMExists = !SetEN24bit || !Addr[23] ;
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wire BankSEL = REGEN && !nDEVSEL && RA[3:0]==4'hF;
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wire SPITX1SEL = REGEN && !nDEVSEL && RA[3:0]==4'hD;
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wire SPITX0SEL = REGEN && !nDEVSEL && RA[3:0]==4'hC;
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@ -66,7 +67,24 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
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wire AddrHSEL = REGEN && !nDEVSEL && RA[3:0]==4'h2;
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wire AddrMSEL = REGEN && !nDEVSEL && RA[3:0]==4'h1;
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wire AddrLSEL = REGEN && !nDEVSEL && RA[3:0]==4'h0;
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/* Slot number detect */
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reg SlotKnown = 0;
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reg [2:0] Slot;
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always @(negedge PHI0) begin
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if (!nIOSEL) begin
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SlotKnown <= 1;
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Slot <= RA[10:8];
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end
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end
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/* RAM/ROM speculative select */
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wire RAMSpecSEL = RA[15:8]==8'hC0 && RA[7] && RA[3:0]==4'h3 && REGEN;
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wire IOSELSpecSEL = RA[15:12]==4'hC && !RA[11] && (RA[10:8]==Slot[2:0] || !SlotKnown);
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wire IOSTRBSpecSEL = RA[15:12]==4'hC && RA[11] && IOROMEN;
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wire RAMROMSpecSEL = RAMSpecSEL || IOSELSpecSEL || IOSTRBSpecSEL;
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reg RAMROMSpecSELr; always @(posedge PHI0) RAMROMSpecSELr <= RAMROMSpecSEL;
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/* IOROMEN control */
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reg IOROMEN = 0;
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wire IOROMRES = !nIOSTRB && RA[10:0]==11'h7FF;
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@ -97,9 +115,6 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
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always @(posedge C25M, negedge nRESr) begin
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if (!nRESr) begin
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Addr[23:0] <= 24'h000000;
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AddrIncL <= 0;
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AddrIncM <= 0;
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AddrIncH <= 0;
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end else begin
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if (PS==8 && RAMSEL) AddrIncL <= 1;
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else AddrIncL <= 0;
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@ -331,7 +346,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
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always @(posedge C25M) begin
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case (PS[3:0])
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0: begin // NOP CKE / NOP CKD
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RCKE <= PSStart && (IS==6 || (IS==7 && CXXXr));
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RCKE <= PSStart && (IS==6 || (IS==7 && RAMROMSpecSELr));
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nRCS <= 1;
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nRAS <= 1;
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nCAS <= 1;
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@ -462,7 +477,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
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DQMH <= !Addr[0];
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end else begin
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SBA[1:0] <= 2'b10;
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SA[12:0] <= { 4'b0011, RA[9:1]};
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SA[12:0] <= { 4'b0011, RA[9:5], RA4, RA[3:1]};
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DQML <= RA[0];
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DQMH <= !RA[0];
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end
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@ -550,9 +565,10 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
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/* Unused Pins */
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output RAdir = 1;
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output nDMAout = 1;
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output nNMIout = 1;
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output nINHout = 1;
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output nRDYout = 1;
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output nIRQout = 1;
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output RWout = 1;
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/* Grounds next to PU */
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output GNDout1 = 0;
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output GNDout2 = 0;
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endmodule
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