Apple-2-HW/GR8RAM
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Some power improvements

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This commit is contained in:
Zane Kaminski 2023-04-14 03:58:43 -04:00
parent d0ece610cc
commit 95a87fef83
1 changed files with 31 additions and 15 deletions
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46
cpld/GR8RAM.v
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@ -1,7 +1,7 @@
module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
INTin, INTout, DMAin, DMAout, INTin, INTout, DMAin, DMAout,
nNMIout, nIRQout, nRDYout, nINHout, RWout, nDMAout, GNDout1, GNDout2, nIRQout, RWout, nDMAout,
RA, nWE, RD, RAdir, RDdir, nIOSEL, nDEVSEL, nIOSTRB, RA, PU, nWE, RD, RAdir, RDdir, nIOSEL, nDEVSEL, nIOSTRB,
SBA, SA, nRCS, nRAS, nCAS, nSWE, DQML, DQMH, RCKE, SD, SBA, SA, nRCS, nRAS, nCAS, nSWE, DQML, DQMH, RCKE, SD,
nFCS, FCK, MISO, MOSI); nFCS, FCK, MISO, MOSI);
@ -19,7 +19,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
/* Firmware select */ /* Firmware select */
input [1:0] SetFW; input [1:0] SetFW;
wire [1:0] SetROM = ~SetFW[1:0]; wire [1:0] SetROM = ~SetFW[1:0];
wire SetENRestore = SetROM[1:0]==1'b11; wire SetENRestore = SetROM[1:0]==2'b11;
wire SetEN24bit = SetROM[1]; wire SetEN24bit = SetROM[1];
/* State counter from PHI0 rising edge */ /* State counter from PHI0 rising edge */
@ -53,12 +53,13 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
input nIOSEL, nDEVSEL, nIOSTRB; input nIOSEL, nDEVSEL, nIOSTRB;
/* Apple address bus */ /* Apple address bus */
input [15:0] RA; reg CXXXr; input [15:0] RA;
input nWE; input nWE;
always @(posedge PHI0) CXXXr <= RA[15:12]==4'hC; input PU;
wire RA4 = RA[4] && PU;
/* Apple select signals */ /* Apple select signals */
wire RAMExists = (!SetEN24bit || !Addr[23]); wire RAMExists = !SetEN24bit || !Addr[23] ;
wire BankSEL = REGEN && !nDEVSEL && RA[3:0]==4'hF; wire BankSEL = REGEN && !nDEVSEL && RA[3:0]==4'hF;
wire SPITX1SEL = REGEN && !nDEVSEL && RA[3:0]==4'hD; wire SPITX1SEL = REGEN && !nDEVSEL && RA[3:0]==4'hD;
wire SPITX0SEL = REGEN && !nDEVSEL && RA[3:0]==4'hC; wire SPITX0SEL = REGEN && !nDEVSEL && RA[3:0]==4'hC;
@ -66,7 +67,24 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
wire AddrHSEL = REGEN && !nDEVSEL && RA[3:0]==4'h2; wire AddrHSEL = REGEN && !nDEVSEL && RA[3:0]==4'h2;
wire AddrMSEL = REGEN && !nDEVSEL && RA[3:0]==4'h1; wire AddrMSEL = REGEN && !nDEVSEL && RA[3:0]==4'h1;
wire AddrLSEL = REGEN && !nDEVSEL && RA[3:0]==4'h0; wire AddrLSEL = REGEN && !nDEVSEL && RA[3:0]==4'h0;
/* Slot number detect */
reg SlotKnown = 0;
reg [2:0] Slot;
always @(negedge PHI0) begin
if (!nIOSEL) begin
SlotKnown <= 1;
Slot <= RA[10:8];
end
end
/* RAM/ROM speculative select */
wire RAMSpecSEL = RA[15:8]==8'hC0 && RA[7] && RA[3:0]==4'h3 && REGEN;
wire IOSELSpecSEL = RA[15:12]==4'hC && !RA[11] && (RA[10:8]==Slot[2:0] || !SlotKnown);
wire IOSTRBSpecSEL = RA[15:12]==4'hC && RA[11] && IOROMEN;
wire RAMROMSpecSEL = RAMSpecSEL || IOSELSpecSEL || IOSTRBSpecSEL;
reg RAMROMSpecSELr; always @(posedge PHI0) RAMROMSpecSELr <= RAMROMSpecSEL;
/* IOROMEN control */ /* IOROMEN control */
reg IOROMEN = 0; reg IOROMEN = 0;
wire IOROMRES = !nIOSTRB && RA[10:0]==11'h7FF; wire IOROMRES = !nIOSTRB && RA[10:0]==11'h7FF;
@ -97,9 +115,6 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
always @(posedge C25M, negedge nRESr) begin always @(posedge C25M, negedge nRESr) begin
if (!nRESr) begin if (!nRESr) begin
Addr[23:0] <= 24'h000000; Addr[23:0] <= 24'h000000;
AddrIncL <= 0;
AddrIncM <= 0;
AddrIncH <= 0;
end else begin end else begin
if (PS==8 && RAMSEL) AddrIncL <= 1; if (PS==8 && RAMSEL) AddrIncL <= 1;
else AddrIncL <= 0; else AddrIncL <= 0;
@ -331,7 +346,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
always @(posedge C25M) begin always @(posedge C25M) begin
case (PS[3:0]) case (PS[3:0])
0: begin // NOP CKE / NOP CKD 0: begin // NOP CKE / NOP CKD
RCKE <= PSStart && (IS==6 || (IS==7 && CXXXr)); RCKE <= PSStart && (IS==6 || (IS==7 && RAMROMSpecSELr));
nRCS <= 1; nRCS <= 1;
nRAS <= 1; nRAS <= 1;
nCAS <= 1; nCAS <= 1;
@ -462,7 +477,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
DQMH <= !Addr[0]; DQMH <= !Addr[0];
end else begin end else begin
SBA[1:0] <= 2'b10; SBA[1:0] <= 2'b10;
SA[12:0] <= { 4'b0011, RA[9:1]}; SA[12:0] <= { 4'b0011, RA[9:5], RA4, RA[3:1]};
DQML <= RA[0]; DQML <= RA[0];
DQMH <= !RA[0]; DQMH <= !RA[0];
end end
@ -550,9 +565,10 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
/* Unused Pins */ /* Unused Pins */
output RAdir = 1; output RAdir = 1;
output nDMAout = 1; output nDMAout = 1;
output nNMIout = 1;
output nINHout = 1;
output nRDYout = 1;
output nIRQout = 1; output nIRQout = 1;
output RWout = 1; output RWout = 1;
/* Grounds next to PU */
output GNDout1 = 0;
output GNDout2 = 0;
endmodule endmodule