diff --git a/cpld/output_files/GR8RAM.asm.rpt b/cpld/output_files/GR8RAM.asm.rpt index 7533478..f2642bc 100644 --- a/cpld/output_files/GR8RAM.asm.rpt +++ b/cpld/output_files/GR8RAM.asm.rpt @@ -1,6 +1,6 @@ Assembler report for GR8RAM -Tue Feb 28 11:21:26 2023 -Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition +Fri Feb 16 20:46:17 2024 +Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition --------------------- @@ -10,7 +10,7 @@ Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition 2. Assembler Summary 3. Assembler Settings 4. Assembler Generated Files - 5. Assembler Device Options: /Repos2/GR8RAM/cpld2/output_files/GR8RAM.pof + 5. Assembler Device Options: /Repos/GR8RAM/cpld/output_files/GR8RAM.pof 6. Assembler Messages @@ -18,7 +18,7 @@ Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition ---------------- ; Legal Notice ; ---------------- -Copyright (C) 2022 Intel Corporation. All rights reserved. +Copyright (C) 2019 Intel Corporation. All rights reserved. Your use of Intel Corporation's design tools, logic functions and other software and tools, and any partner logic functions, and any output files from any of the foregoing @@ -38,7 +38,7 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Tue Feb 28 11:21:26 2023 ; +; Assembler Status ; Successful - Fri Feb 16 20:46:17 2024 ; ; Revision Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ; ; Family ; MAX II ; @@ -53,23 +53,23 @@ https://fpgasoftware.intel.com/eula. +--------+---------+---------------+ -+----------------------------------------------+ -; Assembler Generated Files ; -+----------------------------------------------+ -; File Name ; -+----------------------------------------------+ -; /Repos2/GR8RAM/cpld2/output_files/GR8RAM.pof ; -+----------------------------------------------+ ++--------------------------------------------+ +; Assembler Generated Files ; ++--------------------------------------------+ +; File Name ; ++--------------------------------------------+ +; /Repos/GR8RAM/cpld/output_files/GR8RAM.pof ; ++--------------------------------------------+ -+------------------------------------------------------------------------+ -; Assembler Device Options: /Repos2/GR8RAM/cpld2/output_files/GR8RAM.pof ; -+----------------+-------------------------------------------------------+ -; Option ; Setting ; -+----------------+-------------------------------------------------------+ -; JTAG usercode ; 0x00163AA4 ; -; Checksum ; 0x00163E9C ; -+----------------+-------------------------------------------------------+ ++----------------------------------------------------------------------+ +; Assembler Device Options: /Repos/GR8RAM/cpld/output_files/GR8RAM.pof ; ++----------------+-----------------------------------------------------+ +; Option ; Setting ; ++----------------+-----------------------------------------------------+ +; JTAG usercode ; 0x00163AA4 ; +; Checksum ; 0x00163E9C ; ++----------------+-----------------------------------------------------+ +--------------------+ @@ -77,15 +77,15 @@ https://fpgasoftware.intel.com/eula. +--------------------+ Info: ******************************************************************* Info: Running Quartus Prime Assembler - Info: Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition - Info: Processing started: Tue Feb 28 11:21:25 2023 + Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition + Info: Processing started: Fri Feb 16 20:46:16 2024 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (115031): Writing out detailed assembly data for power analysis Info (115030): Assembler is generating device programming files Info: Quartus Prime Assembler was successful. 0 errors, 1 warning - Info: Peak virtual memory: 13100 megabytes - Info: Processing ended: Tue Feb 28 11:21:26 2023 + Info: Peak virtual memory: 13096 megabytes + Info: Processing ended: Fri Feb 16 20:46:17 2024 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 diff --git a/cpld/output_files/GR8RAM.done b/cpld/output_files/GR8RAM.done index 381b13b..f733ffc 100644 --- a/cpld/output_files/GR8RAM.done +++ b/cpld/output_files/GR8RAM.done @@ -1 +1 @@ -Tue Feb 28 11:21:32 2023 +Fri Feb 16 20:46:20 2024 diff --git a/cpld/output_files/GR8RAM.fit.rpt b/cpld/output_files/GR8RAM.fit.rpt index 95c0b85..ca69b5b 100644 --- a/cpld/output_files/GR8RAM.fit.rpt +++ b/cpld/output_files/GR8RAM.fit.rpt @@ -1,6 +1,6 @@ Fitter report for GR8RAM -Tue Feb 28 11:21:23 2023 -Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition +Fri Feb 16 20:46:15 2024 +Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition --------------------- @@ -38,7 +38,7 @@ Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition ---------------- ; Legal Notice ; ---------------- -Copyright (C) 2022 Intel Corporation. All rights reserved. +Copyright (C) 2019 Intel Corporation. All rights reserved. Your use of Intel Corporation's design tools, logic functions and other software and tools, and any partner logic functions, and any output files from any of the foregoing @@ -55,21 +55,21 @@ https://fpgasoftware.intel.com/eula. -+------------------------------------------------------------------------+ -; Fitter Summary ; -+-----------------------+------------------------------------------------+ -; Fitter Status ; Successful - Tue Feb 28 11:21:23 2023 ; -; Quartus Prime Version ; 22.1std.0 Build 915 10/25/2022 SC Lite Edition ; -; Revision Name ; GR8RAM ; -; Top-level Entity Name ; GR8RAM ; -; Family ; MAX II ; -; Device ; EPM240T100C5 ; -; Timing Models ; Final ; -; Total logic elements ; 233 / 240 ( 97 % ) ; -; Total pins ; 80 / 80 ( 100 % ) ; -; Total virtual pins ; 0 ; -; UFM blocks ; 0 / 1 ( 0 % ) ; -+-----------------------+------------------------------------------------+ ++---------------------------------------------------------------------+ +; Fitter Summary ; ++-----------------------+---------------------------------------------+ +; Fitter Status ; Successful - Fri Feb 16 20:46:15 2024 ; +; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; +; Revision Name ; GR8RAM ; +; Top-level Entity Name ; GR8RAM ; +; Family ; MAX II ; +; Device ; EPM240T100C5 ; +; Timing Models ; Final ; +; Total logic elements ; 233 / 240 ( 97 % ) ; +; Total pins ; 80 / 80 ( 100 % ) ; +; Total virtual pins ; 0 ; +; UFM blocks ; 0 / 1 ( 0 % ) ; ++-----------------------+---------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------+ @@ -134,15 +134,15 @@ https://fpgasoftware.intel.com/eula. ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; -; Processor 2 ; 0.7% ; -; Processors 3-4 ; 0.5% ; +; Processor 2 ; 1.0% ; +; Processors 3-4 ; 0.7% ; +----------------------------+-------------+ +--------------+ ; Pin-Out File ; +--------------+ -The pin-out file can be found in /Repos2/GR8RAM/cpld2/output_files/GR8RAM.pin. +The pin-out file can be found in /Repos/GR8RAM/cpld/output_files/GR8RAM.pin. +---------------------------------------------------------------------+ @@ -741,13 +741,13 @@ Info (332111): Found 2 clocks Info (332111): 40.000 C25M Info (332111): 978.000 PHI0 Info (186079): Completed User Assigned Global Signals Promotion Operation -Info (186215): Automatically promoted signal "C25M" to use Global clock in PIN 64 File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 9 -Info (186216): Automatically promoted some destinations of signal "PHI0" to use Global clock File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 9 +Info (186215): Automatically promoted signal "C25M" to use Global clock in PIN 64 File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 9 +Info (186216): Automatically promoted some destinations of signal "PHI0" to use Global clock File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 9 Info (186217): Destination "comb~0" may be non-global or may not use global clock - Info (186217): Destination "PHI0r1" may be non-global or may not use global clock File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 10 -Info (186228): Pin "PHI0" drives global clock, but is not placed in a dedicated clock pin position File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 9 -Info (186216): Automatically promoted some destinations of signal "nRESr" to use Global clock File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 16 - Info (186217): Destination "IOROMEN" may be non-global or may not use global clock File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 94 + Info (186217): Destination "PHI0r1" may be non-global or may not use global clock File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 10 +Info (186228): Pin "PHI0" drives global clock, but is not placed in a dedicated clock pin position File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 9 +Info (186216): Automatically promoted some destinations of signal "nRESr" to use Global clock File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 16 + Info (186217): Destination "IOROMEN" may be non-global or may not use global clock File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 94 Info (186079): Completed Auto Global Promotion Operation Info (176234): Starting register packing Info (186468): Started processing fast register assignments @@ -760,13 +760,13 @@ Info (176215): I/O bank details before I/O pin placement Info (176214): Statistics of I/O banks Info (176213): I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 38 total pin(s) used -- 0 pins available Info (176213): I/O bank number 2 does not use VREF pins and has 3.3V VCCIO pins. 41 total pin(s) used -- 1 pins available -Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01 +Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00 Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family. Info (170189): Fitter placement preparation operations beginning Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 Info (170191): Fitter placement operations beginning Info (170137): Fitter placement was successful -Info (170192): Fitter placement operations ending: elapsed time is 00:00:01 +Info (170192): Fitter placement operations ending: elapsed time is 00:00:00 Info (170193): Fitter routing operations beginning Info (170195): Router estimated average interconnect usage is 30% of the available device resources Info (170196): Router estimated peak interconnect usage is 30% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5 @@ -774,20 +774,20 @@ Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were Info (170201): Optimizations that may affect the design's routability were skipped Info (170200): Optimizations that may affect the design's timing were skipped Info (170194): Fitter routing operations ending: elapsed time is 00:00:00 -Info (11888): Total time spent on timing analysis during the Fitter is 0.27 seconds. +Info (11888): Total time spent on timing analysis during the Fitter is 0.16 seconds. Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00 Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'. -Info (144001): Generated suppressed messages file /Repos2/GR8RAM/cpld2/output_files/GR8RAM.fit.smsg +Info (144001): Generated suppressed messages file /Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg Info: Quartus Prime Fitter was successful. 0 errors, 4 warnings - Info: Peak virtual memory: 13746 megabytes - Info: Processing ended: Tue Feb 28 11:21:23 2023 - Info: Elapsed time: 00:00:06 - Info: Total CPU time (on all processors): 00:00:05 + Info: Peak virtual memory: 13772 megabytes + Info: Processing ended: Fri Feb 16 20:46:15 2024 + Info: Elapsed time: 00:00:03 + Info: Total CPU time (on all processors): 00:00:03 +----------------------------+ ; Fitter Suppressed Messages ; +----------------------------+ -The suppressed messages can be found in /Repos2/GR8RAM/cpld2/output_files/GR8RAM.fit.smsg. +The suppressed messages can be found in /Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg. diff --git a/cpld/output_files/GR8RAM.fit.summary b/cpld/output_files/GR8RAM.fit.summary index 615a84b..2985690 100644 --- a/cpld/output_files/GR8RAM.fit.summary +++ b/cpld/output_files/GR8RAM.fit.summary @@ -1,5 +1,5 @@ -Fitter Status : Successful - Tue Feb 28 11:21:23 2023 -Quartus Prime Version : 22.1std.0 Build 915 10/25/2022 SC Lite Edition +Fitter Status : Successful - Fri Feb 16 20:46:15 2024 +Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition Revision Name : GR8RAM Top-level Entity Name : GR8RAM Family : MAX II diff --git a/cpld/output_files/GR8RAM.flow.rpt b/cpld/output_files/GR8RAM.flow.rpt index cb3a8d0..82db817 100644 --- a/cpld/output_files/GR8RAM.flow.rpt +++ b/cpld/output_files/GR8RAM.flow.rpt @@ -1,6 +1,6 @@ Flow report for GR8RAM -Tue Feb 28 11:21:31 2023 -Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition +Fri Feb 16 20:46:19 2024 +Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition --------------------- @@ -21,7 +21,7 @@ Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition ---------------- ; Legal Notice ; ---------------- -Copyright (C) 2022 Intel Corporation. All rights reserved. +Copyright (C) 2019 Intel Corporation. All rights reserved. Your use of Intel Corporation's design tools, logic functions and other software and tools, and any partner logic functions, and any output files from any of the foregoing @@ -38,21 +38,21 @@ https://fpgasoftware.intel.com/eula. -+------------------------------------------------------------------------+ -; Flow Summary ; -+-----------------------+------------------------------------------------+ -; Flow Status ; Successful - Tue Feb 28 11:21:31 2023 ; -; Quartus Prime Version ; 22.1std.0 Build 915 10/25/2022 SC Lite Edition ; -; Revision Name ; GR8RAM ; -; Top-level Entity Name ; GR8RAM ; -; Family ; MAX II ; -; Device ; EPM240T100C5 ; -; Timing Models ; Final ; -; Total logic elements ; 233 / 240 ( 97 % ) ; -; Total pins ; 80 / 80 ( 100 % ) ; -; Total virtual pins ; 0 ; -; UFM blocks ; 0 / 1 ( 0 % ) ; -+-----------------------+------------------------------------------------+ ++---------------------------------------------------------------------+ +; Flow Summary ; ++-----------------------+---------------------------------------------+ +; Flow Status ; Successful - Fri Feb 16 20:46:17 2024 ; +; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; +; Revision Name ; GR8RAM ; +; Top-level Entity Name ; GR8RAM ; +; Family ; MAX II ; +; Device ; EPM240T100C5 ; +; Timing Models ; Final ; +; Total logic elements ; 233 / 240 ( 97 % ) ; +; Total pins ; 80 / 80 ( 100 % ) ; +; Total virtual pins ; 0 ; +; UFM blocks ; 0 / 1 ( 0 % ) ; ++-----------------------+---------------------------------------------+ +-----------------------------------------+ @@ -60,33 +60,25 @@ https://fpgasoftware.intel.com/eula. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 02/28/2023 11:20:54 ; +; Start date & time ; 02/16/2024 20:45:52 ; ; Main task ; Compilation ; ; Revision Name ; GR8RAM ; +-------------------+---------------------+ -+--------------------------------------------------------------------------------------------------------------------------------------------------+ -; Flow Non-Default Global Settings ; -+---------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ -; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; -+---------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ -; COMPILER_SIGNATURE_ID ; 121381084694.167760125411500 ; -- ; -- ; -- ; -; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ; -; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ; -; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ; -; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_symbol ; -; EDA_NETLIST_WRITER_OUTPUT_DIR ; simulation/questa ; -- ; -- ; eda_simulation ; -; EDA_OUTPUT_DATA_FORMAT ; Verilog Hdl ; -- ; -- ; eda_simulation ; -; EDA_SIMULATION_TOOL ; Questa Intel FPGA (Verilog) ; ; -- ; -- ; -; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ; -; IOBANK_VCCIO ; -- (Not supported for targeted family) ; -- ; -- ; 1 ; -; IOBANK_VCCIO ; -- (Not supported for targeted family) ; -- ; -- ; 2 ; -; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; -; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; -; POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR ; 3.3V ; -- ; -- ; -- ; -; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; -+---------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ ++---------------------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++---------------------------------------+----------------------------------------+---------------+-------------+------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++---------------------------------------+----------------------------------------+---------------+-------------+------------+ +; COMPILER_SIGNATURE_ID ; 121380219419.170813435209448 ; -- ; -- ; -- ; +; IOBANK_VCCIO ; -- (Not supported for targeted family) ; -- ; -- ; 1 ; +; IOBANK_VCCIO ; -- (Not supported for targeted family) ; -- ; -- ; 2 ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR ; 3.3V ; -- ; -- ; -- ; +; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; ++---------------------------------------+----------------------------------------+---------------+-------------+------------+ +--------------------------------------------------------------------------------------------------------------------------+ @@ -94,12 +86,11 @@ https://fpgasoftware.intel.com/eula. +----------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:23 ; 1.0 ; 13114 MB ; 00:00:48 ; -; Fitter ; 00:00:06 ; 1.0 ; 13746 MB ; 00:00:05 ; -; Assembler ; 00:00:01 ; 1.0 ; 13099 MB ; 00:00:01 ; -; Timing Analyzer ; 00:00:02 ; 1.0 ; 13081 MB ; 00:00:01 ; -; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 13024 MB ; 00:00:01 ; -; Total ; 00:00:33 ; -- ; -- ; 00:00:56 ; +; Analysis & Synthesis ; 00:00:19 ; 1.0 ; 13145 MB ; 00:00:41 ; +; Fitter ; 00:00:03 ; 1.0 ; 13772 MB ; 00:00:03 ; +; Assembler ; 00:00:01 ; 1.0 ; 13092 MB ; 00:00:01 ; +; Timing Analyzer ; 00:00:01 ; 1.0 ; 13094 MB ; 00:00:01 ; +; Total ; 00:00:24 ; -- ; -- ; 00:00:46 ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ @@ -112,7 +103,6 @@ https://fpgasoftware.intel.com/eula. ; Fitter ; ZaneMacWin11 ; Windows 10 ; 10.0 ; x86_64 ; ; Assembler ; ZaneMacWin11 ; Windows 10 ; 10.0 ; x86_64 ; ; Timing Analyzer ; ZaneMacWin11 ; Windows 10 ; 10.0 ; x86_64 ; -; EDA Netlist Writer ; ZaneMacWin11 ; Windows 10 ; 10.0 ; x86_64 ; +----------------------+------------------+------------+------------+----------------+ @@ -123,7 +113,6 @@ quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM quartus_sta GR8RAM -c GR8RAM -quartus_eda --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM diff --git a/cpld/output_files/GR8RAM.jdi b/cpld/output_files/GR8RAM.jdi index b6cbf71..cd3ac0c 100644 --- a/cpld/output_files/GR8RAM.jdi +++ b/cpld/output_files/GR8RAM.jdi @@ -1,6 +1,6 @@ - + diff --git a/cpld/output_files/GR8RAM.map.rpt b/cpld/output_files/GR8RAM.map.rpt index 0dbf265..ccf51e4 100644 --- a/cpld/output_files/GR8RAM.map.rpt +++ b/cpld/output_files/GR8RAM.map.rpt @@ -1,6 +1,6 @@ Analysis & Synthesis report for GR8RAM -Tue Feb 28 11:21:16 2023 -Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition +Fri Feb 16 20:46:11 2024 +Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition --------------------- @@ -26,7 +26,7 @@ Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition ---------------- ; Legal Notice ; ---------------- -Copyright (C) 2022 Intel Corporation. All rights reserved. +Copyright (C) 2019 Intel Corporation. All rights reserved. Your use of Intel Corporation's design tools, logic functions and other software and tools, and any partner logic functions, and any output files from any of the foregoing @@ -43,19 +43,19 @@ https://fpgasoftware.intel.com/eula. -+------------------------------------------------------------------------------+ -; Analysis & Synthesis Summary ; -+-----------------------------+------------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Tue Feb 28 11:21:16 2023 ; -; Quartus Prime Version ; 22.1std.0 Build 915 10/25/2022 SC Lite Edition ; -; Revision Name ; GR8RAM ; -; Top-level Entity Name ; GR8RAM ; -; Family ; MAX II ; -; Total logic elements ; 253 ; -; Total pins ; 80 ; -; Total virtual pins ; 0 ; -; UFM blocks ; 0 / 1 ( 0 % ) ; -+-----------------------------+------------------------------------------------+ ++---------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++-----------------------------+---------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Fri Feb 16 20:46:11 2024 ; +; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; +; Revision Name ; GR8RAM ; +; Top-level Entity Name ; GR8RAM ; +; Family ; MAX II ; +; Total logic elements ; 253 ; +; Total pins ; 80 ; +; Total virtual pins ; 0 ; +; UFM blocks ; 0 / 1 ( 0 % ) ; ++-----------------------------+---------------------------------------------+ +------------------------------------------------------------------------------------------------------------+ @@ -145,13 +145,13 @@ https://fpgasoftware.intel.com/eula. +----------------------------+-------------+ -+-----------------------------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Source Files Read ; -+----------------------------------+-----------------+------------------------------+-------------------------------------------+---------+ -; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; -+----------------------------------+-----------------+------------------------------+-------------------------------------------+---------+ -; gr8ram.v ; yes ; Auto-Found Verilog HDL File ; //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v ; ; -+----------------------------------+-----------------+------------------------------+-------------------------------------------+---------+ ++-------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+------------------------+---------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------+-----------------+------------------------+---------------------------------------+---------+ +; GR8RAM.v ; yes ; User Verilog HDL File ; //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v ; ; ++----------------------------------+-----------------+------------------------+---------------------------------------+---------+ +-----------------------------------------------------+ @@ -279,44 +279,44 @@ Encoding Type: One-Hot +-------------------------------+ Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis - Info: Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition - Info: Processing started: Tue Feb 28 11:20:53 2023 + Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition + Info: Processing started: Fri Feb 16 20:45:52 2024 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected -Warning (12125): Using design file gr8ram.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project - Info (12023): Found entity 1: GR8RAM File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 1 +Info (12021): Found 1 design units, including 1 entities, in source file gr8ram.v + Info (12023): Found entity 1: GR8RAM File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 1 Info (12127): Elaborating entity "GR8RAM" for the top level hierarchy -Warning (10230): Verilog HDL assignment warning at gr8ram.v(42): truncated value with size 32 to match size of target (4) File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 42 -Warning (10230): Verilog HDL assignment warning at gr8ram.v(47): truncated value with size 32 to match size of target (14) File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 47 -Warning (10230): Verilog HDL assignment warning at gr8ram.v(134): truncated value with size 32 to match size of target (8) File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 134 -Warning (10230): Verilog HDL assignment warning at gr8ram.v(142): truncated value with size 32 to match size of target (8) File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 142 -Warning (10230): Verilog HDL assignment warning at gr8ram.v(149): truncated value with size 32 to match size of target (8) File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 149 +Warning (10230): Verilog HDL assignment warning at GR8RAM.v(42): truncated value with size 32 to match size of target (4) File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 42 +Warning (10230): Verilog HDL assignment warning at GR8RAM.v(47): truncated value with size 32 to match size of target (14) File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 47 +Warning (10230): Verilog HDL assignment warning at GR8RAM.v(134): truncated value with size 32 to match size of target (8) File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 134 +Warning (10230): Verilog HDL assignment warning at GR8RAM.v(142): truncated value with size 32 to match size of target (8) File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 142 +Warning (10230): Verilog HDL assignment warning at GR8RAM.v(149): truncated value with size 32 to match size of target (8) File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 149 Warning (13024): Output pins are stuck at VCC or GND - Warning (13410): Pin "nNMIout" is stuck at VCC File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 563 - Warning (13410): Pin "nIRQout" is stuck at VCC File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 566 - Warning (13410): Pin "nRDYout" is stuck at VCC File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 565 - Warning (13410): Pin "nINHout" is stuck at VCC File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 564 - Warning (13410): Pin "RWout" is stuck at VCC File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 567 - Warning (13410): Pin "nDMAout" is stuck at VCC File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 562 - Warning (13410): Pin "RAdir" is stuck at VCC File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 561 + Warning (13410): Pin "nNMIout" is stuck at VCC File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 563 + Warning (13410): Pin "nIRQout" is stuck at VCC File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 566 + Warning (13410): Pin "nRDYout" is stuck at VCC File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 565 + Warning (13410): Pin "nINHout" is stuck at VCC File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 564 + Warning (13410): Pin "RWout" is stuck at VCC File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 567 + Warning (13410): Pin "nDMAout" is stuck at VCC File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 562 + Warning (13410): Pin "RAdir" is stuck at VCC File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 561 Info (17049): 3 registers lost all their fanouts during netlist optimizations. Info (21057): Implemented 333 device resources after synthesis - the final resource count might be different Info (21058): Implemented 28 input pins Info (21059): Implemented 35 output pins Info (21060): Implemented 17 bidirectional pins Info (21061): Implemented 253 logic cells -Info (144001): Generated suppressed messages file /Repos2/GR8RAM/cpld2/output_files/GR8RAM.map.smsg -Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 15 warnings - Info: Peak virtual memory: 13114 megabytes - Info: Processing ended: Tue Feb 28 11:21:16 2023 - Info: Elapsed time: 00:00:23 - Info: Total CPU time (on all processors): 00:00:48 +Info (144001): Generated suppressed messages file /Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg +Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 14 warnings + Info: Peak virtual memory: 13145 megabytes + Info: Processing ended: Fri Feb 16 20:46:11 2024 + Info: Elapsed time: 00:00:19 + Info: Total CPU time (on all processors): 00:00:41 +------------------------------------------+ ; Analysis & Synthesis Suppressed Messages ; +------------------------------------------+ -The suppressed messages can be found in /Repos2/GR8RAM/cpld2/output_files/GR8RAM.map.smsg. +The suppressed messages can be found in /Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg. diff --git a/cpld/output_files/GR8RAM.map.smsg b/cpld/output_files/GR8RAM.map.smsg index 45e0f77..bb83fda 100644 --- a/cpld/output_files/GR8RAM.map.smsg +++ b/cpld/output_files/GR8RAM.map.smsg @@ -1,2 +1,2 @@ -Warning (10273): Verilog HDL warning at gr8ram.v(110): extended using "x" or "z" File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 110 -Warning (10273): Verilog HDL warning at gr8ram.v(286): extended using "x" or "z" File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 286 +Warning (10273): Verilog HDL warning at GR8RAM.v(110): extended using "x" or "z" File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 110 +Warning (10273): Verilog HDL warning at GR8RAM.v(286): extended using "x" or "z" File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 286 diff --git a/cpld/output_files/GR8RAM.map.summary b/cpld/output_files/GR8RAM.map.summary index 6a8e211..736b3f6 100644 --- a/cpld/output_files/GR8RAM.map.summary +++ b/cpld/output_files/GR8RAM.map.summary @@ -1,5 +1,5 @@ -Analysis & Synthesis Status : Successful - Tue Feb 28 11:21:16 2023 -Quartus Prime Version : 22.1std.0 Build 915 10/25/2022 SC Lite Edition +Analysis & Synthesis Status : Successful - Fri Feb 16 20:46:11 2024 +Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition Revision Name : GR8RAM Top-level Entity Name : GR8RAM Family : MAX II diff --git a/cpld/output_files/GR8RAM.pin b/cpld/output_files/GR8RAM.pin index 33a0c06..be7c22e 100644 --- a/cpld/output_files/GR8RAM.pin +++ b/cpld/output_files/GR8RAM.pin @@ -1,4 +1,4 @@ - -- Copyright (C) 2022 Intel Corporation. All rights reserved. + -- Copyright (C) 2019 Intel Corporation. All rights reserved. -- Your use of Intel Corporation's design tools, logic functions -- and other software and tools, and any partner logic -- functions, and any output files from any of the foregoing @@ -58,7 +58,7 @@ -- Pin directions (input, output or bidir) are based on device operating in user mode. --------------------------------------------------------------------------------- -Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition +Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition CHIP "GR8RAM" ASSIGNED TO AN: EPM240T100C5 Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment diff --git a/cpld/output_files/GR8RAM.pof b/cpld/output_files/GR8RAM.pof index c90017c..78fa46a 100644 Binary files a/cpld/output_files/GR8RAM.pof and b/cpld/output_files/GR8RAM.pof differ diff --git a/cpld/output_files/GR8RAM.sta.rpt b/cpld/output_files/GR8RAM.sta.rpt index 26f6da6..78369cc 100644 --- a/cpld/output_files/GR8RAM.sta.rpt +++ b/cpld/output_files/GR8RAM.sta.rpt @@ -1,6 +1,6 @@ Timing Analyzer report for GR8RAM -Tue Feb 28 11:21:29 2023 -Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition +Fri Feb 16 20:46:19 2024 +Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition --------------------- @@ -40,7 +40,7 @@ Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition ---------------- ; Legal Notice ; ---------------- -Copyright (C) 2022 Intel Corporation. All rights reserved. +Copyright (C) 2019 Intel Corporation. All rights reserved. Your use of Intel Corporation's design tools, logic functions and other software and tools, and any partner logic functions, and any output files from any of the foregoing @@ -57,18 +57,18 @@ https://fpgasoftware.intel.com/eula. -+--------------------------------------------------------------------------------+ -; Timing Analyzer Summary ; -+-----------------------+--------------------------------------------------------+ -; Quartus Prime Version ; Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition ; -; Timing Analyzer ; Legacy Timing Analyzer ; -; Revision Name ; GR8RAM ; -; Device Family ; MAX II ; -; Device Name ; EPM240T100C5 ; -; Timing Models ; Final ; -; Delay Model ; Slow Model ; -; Rise/Fall Delays ; Unavailable ; -+-----------------------+--------------------------------------------------------+ ++-----------------------------------------------------------------------------+ +; Timing Analyzer Summary ; ++-----------------------+-----------------------------------------------------+ +; Quartus Prime Version ; Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; +; Timing Analyzer ; Legacy Timing Analyzer ; +; Revision Name ; GR8RAM ; +; Device Family ; MAX II ; +; Device Name ; EPM240T100C5 ; +; Timing Models ; Final ; +; Delay Model ; Slow Model ; +; Rise/Fall Delays ; Unavailable ; ++-----------------------+-----------------------------------------------------+ +------------------------------------------+ @@ -80,10 +80,11 @@ https://fpgasoftware.intel.com/eula. ; Maximum allowed ; 4 ; ; ; ; ; Average used ; 1.00 ; -; Maximum used ; 1 ; +; Maximum used ; 2 ; ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; +; Processor 2 ; 0.2% ; +----------------------------+-------------+ @@ -92,7 +93,7 @@ https://fpgasoftware.intel.com/eula. +---------------+--------+--------------------------+ ; SDC File Path ; Status ; Read at ; +---------------+--------+--------------------------+ -; GR8RAM.sdc ; OK ; Tue Feb 28 11:21:29 2023 ; +; GR8RAM.sdc ; OK ; Fri Feb 16 20:46:19 2024 ; +---------------+--------+--------------------------+ @@ -745,8 +746,8 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi +--------------------------+ Info: ******************************************************************* Info: Running Quartus Prime Timing Analyzer - Info: Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition - Info: Processing started: Tue Feb 28 11:21:27 2023 + Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition + Info: Processing started: Fri Feb 16 20:46:18 2024 Info: Command: quartus_sta GR8RAM -c GR8RAM Info: qsta_default_script.tcl version: #1 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. @@ -783,9 +784,9 @@ Info (332001): The selected device family is not supported by the report_metasta Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements Info: Quartus Prime Timing Analyzer was successful. 0 errors, 1 warning - Info: Peak virtual memory: 13081 megabytes - Info: Processing ended: Tue Feb 28 11:21:29 2023 - Info: Elapsed time: 00:00:02 + Info: Peak virtual memory: 13094 megabytes + Info: Processing ended: Fri Feb 16 20:46:19 2024 + Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01