From a2eecf44751efbc680bb7fa40c28e488d0e0af3d Mon Sep 17 00:00:00 2001 From: Zane Kaminski Date: Sun, 26 Jan 2020 15:13:37 -0500 Subject: [PATCH] Separated CSDBEN --- Docs.sch | 144 +++++++++++++++++++++++++------------------------- cpld/GR8RAM.v | 41 ++++++++------ 2 files changed, 97 insertions(+), 88 deletions(-) diff --git a/Docs.sch b/Docs.sch index 3f0dae6..e2b1103 100644 --- a/Docs.sch +++ b/Docs.sch @@ -38,8 +38,6 @@ Wire Wire Line 6100 1100 6100 1000 Wire Wire Line 5800 1100 6100 1100 -Wire Wire Line - 6100 1550 6150 1450 Wire Wire Line 6100 1400 6150 1300 Wire Wire Line @@ -126,7 +124,7 @@ Text Notes 3300 1100 0 40 ~ 0 S3 Text Notes 800 1250 2 50 ~ 0 PHI0 -Text Notes 3850 850 0 100 ~ 0 +Text Notes 3500 850 0 100 ~ 0 6502 CPU Access (long) Text Notes 800 1400 2 50 ~ 0 PHI1 @@ -238,10 +236,6 @@ Wire Wire Line 1600 1750 900 1750 Wire Wire Line 900 1850 1600 1850 -Wire Wire Line - 1650 1750 6400 1750 -Wire Wire Line - 6450 1750 10400 1750 Wire Wire Line 6450 1850 10400 1850 Text Notes 800 2000 2 50 ~ 0 @@ -300,8 +294,6 @@ Wire Wire Line 6400 1900 6450 1950 Wire Wire Line 6150 1300 8200 1300 -Wire Wire Line - 1650 1850 6400 1850 Wire Wire Line 1600 1900 900 1900 Wire Wire Line @@ -316,14 +308,10 @@ Wire Wire Line 3850 1450 3900 1550 Wire Wire Line 6350 1550 6400 1450 -Wire Bus Line - 6100 1550 6100 2250 Wire Wire Line 1350 1450 3400 1450 Wire Bus Line 7900 950 7900 2200 -Wire Bus Line - 8500 950 8500 2200 Wire Bus Line 9100 950 9100 2200 Wire Bus Line @@ -333,13 +321,9 @@ Wire Bus Line Wire Bus Line 6700 950 6700 2200 Wire Bus Line - 6100 850 6100 1550 -Wire Bus Line - 5500 950 5500 2200 + 5500 850 5500 2250 Wire Bus Line 3700 950 3700 2200 -Wire Bus Line - 4300 950 4300 2200 Wire Bus Line 4900 950 4900 2200 Wire Bus Line @@ -355,23 +339,17 @@ Wire Wire Line Wire Bus Line 3400 850 3400 2250 Wire Wire Line - 3400 1700 3450 1600 + 3400 1600 1350 1600 Wire Wire Line - 6600 1600 6650 1700 + 1350 1600 1300 1700 Wire Wire Line - 6150 1600 6200 1700 + 900 1700 1300 1700 Wire Wire Line - 3400 1700 1350 1700 + 8200 1600 8250 1700 Wire Wire Line - 1350 1700 1300 1600 + 10350 1600 10400 1600 Wire Wire Line - 900 1600 1300 1600 -Wire Wire Line - 8200 1700 8250 1600 -Wire Wire Line - 10350 1700 10400 1700 -Wire Wire Line - 10300 1600 10350 1700 + 10300 1700 10350 1600 Wire Wire Line 5200 1000 5200 1100 Wire Wire Line @@ -390,10 +368,6 @@ Wire Wire Line 4800 2000 4750 1950 Wire Wire Line 4800 1900 4750 1950 -Wire Wire Line - 3450 1600 6600 1600 -Wire Wire Line - 6200 1700 8200 1700 Wire Wire Line 10000 1000 10000 1100 Wire Wire Line @@ -598,22 +572,12 @@ Wire Wire Line 8250 1400 10300 1400 Wire Wire Line 8650 1450 8700 1550 -Wire Bus Line - 8200 850 8200 2250 -Wire Wire Line - 6150 1450 8650 1450 -Wire Wire Line - 3450 1550 6350 1550 -Wire Bus Line - 10300 1600 10300 2250 Wire Wire Line 8200 1450 8250 1550 Wire Wire Line 8250 1550 10300 1550 Wire Wire Line 10300 1550 10400 1550 -Wire Bus Line - 10300 850 10300 1600 Wire Wire Line 6150 2500 7000 2500 Wire Wire Line @@ -784,38 +748,74 @@ Wire Wire Line 3500 1450 3550 1550 Wire Wire Line 3450 1450 3500 1550 -Wire Wire Line - 6300 1550 6350 1450 -Wire Wire Line - 6250 1550 6300 1450 -Wire Wire Line - 6150 1550 6200 1450 -Wire Wire Line - 6200 1550 6250 1450 Wire Wire Line 10350 1450 10400 1450 Wire Wire Line 10350 1550 10400 1450 Wire Wire Line - 10350 1600 10400 1700 -Wire Wire Line - 8250 1600 10400 1600 -Wire Wire Line - 6550 1600 6600 1700 -Wire Wire Line - 6500 1600 6550 1700 -Wire Wire Line - 6450 1600 6500 1700 -Wire Wire Line - 6400 1600 6450 1700 -Wire Wire Line - 6350 1600 6400 1700 -Wire Wire Line - 6250 1600 6300 1700 -Wire Wire Line - 6200 1600 6250 1700 -Wire Wire Line - 6300 1600 6350 1700 + 10350 1700 10400 1600 Text Notes 800 1700 2 50 ~ 0 -PHI0d +PHI1d +Wire Wire Line + 6200 1550 6250 1450 +Wire Wire Line + 6150 1550 6200 1450 +Wire Wire Line + 6250 1550 6300 1450 +Wire Wire Line + 6300 1550 6350 1450 +Wire Bus Line + 6100 850 6100 1550 +Wire Bus Line + 6100 1550 6100 2250 +Wire Bus Line + 8500 950 8500 2200 +Wire Bus Line + 8200 850 8200 2250 +Wire Wire Line + 3450 1550 6350 1550 +Wire Wire Line + 6150 1450 8650 1450 +Wire Wire Line + 6100 1550 6150 1450 +Wire Bus Line + 4300 950 4300 2200 +Wire Wire Line + 1650 1850 6400 1850 +Wire Wire Line + 6300 1700 6350 1600 +Wire Wire Line + 6350 1700 6400 1600 +Wire Wire Line + 6400 1700 6450 1600 +Wire Wire Line + 6500 1700 6550 1600 +Wire Wire Line + 6550 1700 6600 1600 +Wire Wire Line + 6150 1700 6200 1600 +Wire Wire Line + 6600 1700 6650 1600 +Wire Wire Line + 6450 1750 10400 1750 +Wire Wire Line + 1650 1750 6400 1750 +Wire Wire Line + 3400 1600 3450 1700 +Wire Bus Line + 10300 1700 10300 2250 +Wire Bus Line + 10300 850 10300 1700 +Wire Wire Line + 6200 1700 6250 1600 +Wire Wire Line + 6250 1700 6300 1600 +Wire Wire Line + 3450 1700 6600 1700 +Wire Wire Line + 6450 1700 6500 1600 +Wire Wire Line + 6200 1600 8200 1600 +Wire Wire Line + 8250 1700 10400 1700 $EndSCHEMATC diff --git a/cpld/GR8RAM.v b/cpld/GR8RAM.v index 4576d77..98f849f 100755 --- a/cpld/GR8RAM.v +++ b/cpld/GR8RAM.v @@ -8,8 +8,7 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode, input nRES, nMode; // Reset, mode /* PHI1 Delay */ - wire [8:0] PHI1b; - wire PHI1; + wire [8:0] PHI1b; wire PHI1; LCELL PHI1b0_MC (.in(PHI1in), .out(PHI1b[0])); LCELL PHI1b1_MC (.in(PHI1b[0]), .out(PHI1b[1])); LCELL PHI1b2_MC (.in(PHI1b[1]), .out(PHI1b[2])); @@ -48,10 +47,10 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode, /* Data Bus Routing */ // DRAM/ROM data bus - wire RDOE = CSDBEN & ~nWE; + wire RDOE = DBEN & ~nWE; inout [7:0] RD = RDOE ? D[7:0] : 8'bZ; // Apple II data bus - wire DOE = CSDBEN & nWE & + wire DOE = DBEN & nWE & ((~nDEVSEL & REGEN) | ~nIOSEL | (~nIOSTRB & IOROMEN)); wire [7:0] Dout = (nDEVSEL | RAMSELA) ? RD[7:0] : AddrHSELA ? {Addr[23:16]} : @@ -63,9 +62,9 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode, output nINH = 1'bZ; /* DRAM and ROM Control Signals */ - output nRCS = ~((~nIOSEL | (~nIOSTRB & IOROMEN)) & CSDBEN); // ROM chip select + output nRCS = ~((~nIOSEL | (~nIOSTRB & IOROMEN)) & CSDBEN & nRES); // ROM chip select output nROE = ~nWE; // need this for flash ROM - output nRWE = nWE | (nDEVSEL & nIOSEL & nIOSTRB); // for ROM & DRAM + output reg nRWE; // for ROM & DRAM output nRAS = ~(RASr | RASf); output nCAS0 = ~(CAS0f | (CASr & RAMSEL & ~Addr[22])); // DRAM CAS bank 0 output nCAS1 = ~(CAS1f | (CASr & RAMSEL & Addr[22])); // DRAM CAS bank 1 @@ -80,6 +79,7 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode, /* CAS rising/falling edge components */ reg CASr = 0, CAS0f = 0, CAS1f = 0; reg RASr = 0, RASf = 0; + reg ASel = 0; // DRAM address multiplexer select /* State Counters */ reg PHI1reg = 0; // Saved PHI1 at last rising clock edge @@ -90,9 +90,10 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode, /* Misc. */ reg REGEN = 0; // Register enable reg IOROMEN = 0; // IOSTRB ROM enable - reg CSDBEN = 0; // ROM CS, data bus driver gating - reg ASel = 0; // DRAM address multiplexer select - reg FullIOEN = 0; + reg FullIOEN = 0; // Set to enable full IOROM space + reg DBEN = 0; // data bus driver gating + reg RDCSEN = 0; // ROM CS enable for reads + reg WRCSEN = 0; // ROM CS gating for writes // Apple II Bus Compatibiltiy Rules: // Synchronize to PHI0 or PHI1. (PHI1 here) @@ -105,7 +106,7 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode, // Can sample /IOSTRB at same times as /IOSEL, plus: // 1st rising edge of C7M in PHI0 (S3) - always @(posedge C7M, negedge nRES) begin + always @(posedge C7M) begin // Synchronize state counter to S1 when just entering PHI1 PHI1reg <= PHI1; // Save old PHI1 if (~PHI1) PHI0seen <= 1; // PHI0seen set in PHI0 @@ -119,10 +120,15 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode, // Only drive Apple II data bus after state 4 to avoid bus fight. // Thus we wait 1.5 7M cycles (210 ns) into PHI0 before driving. // Same for driving the ROM/SRAM data bus (RD). - // Similarly, only select the ROM chip starting at the end of S4. - // This provides address setup time for write operations and - // minimizes power consumption. - CSDBEN <= S==4 | S==5 | S==6 | S==7; + DBEN <= S==4 | S==5 | S==6 | S==7; + + // Similarly, only select the ROM chip starting at + // the end of S4 for reads and the end of S5 for writes. + // This ensures that write data is valid for + // the entire time that the ROM is selected, + // and minimizes power consumption for reads. + RDCSEN <= S==4 | S==5 | S==6 | S==7; + WRCSEN <= S==5 | S==6 | S==7; end always @(posedge C7M, negedge nRES) begin @@ -183,7 +189,7 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode, end /* DRAM RAS/CAS */ - always @(posedge C7M, negedge nRES) begin + always @(posedge C7M) begin RASr <= (S==1 & Ref==0) | // Refresh (S==4 & RAMSEL & nWE) | // Read: Early RAS (S==5 & RAMSEL & ~nWE); // Write: Late RAS @@ -195,7 +201,10 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode, // Read: long, early CAS, gated later by RAMSEL CASr <= (RAMSEL & ~nWE & (S==5 | S==6 | S==7)); end - always @(negedge C7M, negedge nRES) begin + always @(negedge C7M) begin + if (S==0 | S==1) nRWE <= 1; + if (S==3) nRWE <= nWE; + RASf <= (S==4 & RAMSEL & nWE) | // Read: Early RAS (S==5 & RAMSEL & ~nWE); // Write: Late RAS