From a4f29ea751f0f227881907f96deeb5c91cc32747 Mon Sep 17 00:00:00 2001 From: Zane Kaminski Date: Wed, 26 Feb 2020 02:13:35 -0500 Subject: [PATCH] Removed SetWR and FullIOEN --- cpld/GR8RAM.v | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/cpld/GR8RAM.v b/cpld/GR8RAM.v index 8fcc1be..3144de9 100755 --- a/cpld/GR8RAM.v +++ b/cpld/GR8RAM.v @@ -27,8 +27,7 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode, input nWE; // 6502 R/W output [10:0] RA; // DRAM/ROM address assign RA[10:8] = CASel ? Addr[21:19] : Addr[10:8]; - assign RA[7:0] = (~nIOSTRB & FullIOEN) ? Bank+1 : - (~nIOSTRB & ~FullIOEN) ? {7'b0000001, Bank[0]} : + assign RA[7:0] = ~nIOSTRB ? Bank+1 : (~CASel & nIOSEL & nIOSTRB) ? Addr[18:11] : (CASel & nIOSEL & nIOSTRB) ? Addr[7:0] : 8'h00; @@ -40,7 +39,6 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode, wire AddrMSELA = A[3:0]==4'h1; wire AddrLSELA = A[3:0]==4'h0; LCELL BankWR_MC (.in(BankSELA & ~nWE & ~nDEVSEL & REGEN), .out(BankWR)); wire BankWR; - LCELL SetWR_MC (.in(SetSELA & ~nWE & ~nDEVSEL & REGEN), .out(SetWR)); wire SetWR; LCELL RAMSEL_MC (.in(RAMSELA & ~nDEVSEL & REGEN), .out(RAMSEL)); wire RAMSEL; LCELL AddrHWR_MC (.in(AddrHSELA & ~nWE & ~nDEVSEL & REGEN), .out(AddrHWR)); wire AddrHWR; LCELL AddrMWR_MC (.in(AddrMSELA & ~nWE & ~nDEVSEL & REGEN), .out(AddrMWR)); wire AddrMWR; @@ -92,7 +90,6 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode, /* Misc. */ reg REGEN = 0; // Register enable reg IOROMEN = 0; // IOSTRB ROM enable - reg FullIOEN = 0; // Set to enable full I/O ROM space reg DBEN = 0; // Data bus driver gating reg CSEN = 0; // ROM CS enable gating @@ -184,7 +181,6 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode, // Set register in middle of S6 if accessed. if (S==6) begin if (BankWR) Bank[7:0] <= D[7:0]; // Bank - if (SetWR) FullIOEN <= D[7:0] == 8'hE5; IncAddrL <= RAMSEL; IncAddrM <= AddrLWR & Addr[7] & ~D[7];