mirror of
https://github.com/garrettsworkshop/GR8RAM.git
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Merge branch 'dev' of https://github.com/garrettsworkshop/GR8RAM into dev
This commit is contained in:
Zane Kaminski
commit
abfe1cc597
1
.gitignore
vendored
1
.gitignore
vendored
@ -26,3 +26,4 @@ fp-info-cache
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cpld/db/GR8RAM.db_info
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cpld/db/GR8RAM.tmw_info
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cpld/GR8RAM.qws
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Documentation/~$4205AManual.docx
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BIN
Documentation/FrontIsomTransparent.png
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Documentation/FrontIsomTransparent.png
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Documentation/GW4205AManual.pdf
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Documentation/GW4205AManual.pdf
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@ -1,139 +1,13 @@
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Init sequence
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Init State SDRAM Flash IS Other
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--------------------------------------------------------------------------------
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$00000-$0FFBF Nothing Nothing 0
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$00000 NOP CKE /CS hi, CLK lo
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...
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$0FF90 NOP CKE /CS hi, CLK lo InitActv <= ~BODf
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....
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$0FFA0 NOP CKE /CS lo, CLK lo
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...
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$0FFAF NOP CKE /CS lo, CLK lo
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$0FFB0-$0FFBF Init: Precharge Send read cmd ($03) 1
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$0FFB0 NOP CKE CLK lo, MOSI 0 (b7)
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$0FFB1 NOP CKE CLK hi
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$0FFB2 NOP CKE CLK lo, MOSI 0 (b6)
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$0FFB3 PC all CLK hi
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$0FFB4 NOP CKE CLK lo, MOSI 0 (b5)
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$0FFB5 NOP CKE CLK hi
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$0FFB6 NOP CKE CLK lo, MOSI 0 (b4)
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$0FFB7 NOP CKE CLK hi
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$0FFB8 NOP CKE CLK lo, MOSI 0 (b3)
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$0FFB9 NOP CKE CLK hi
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$0FFBA NOP CKE CLK lo, MOSI 0 (b2)
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$0FFBB Load mode CLK hi
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$0FFBC NOP CKE CLK lo, MOSI 1 (b1)
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$0FFBD NOP CKE CLK hi
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$0FFBE NOP CKE CLK lo, MOSI 1 (b0)
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$0FFBF NOP CKE CLK hi
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$0FFC0-$0FFEF Init: mode & ref Send address ($000000) 2
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$0FFC0 NOP CKE CLK lo, MOSI 0 (b23)
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$0FFC1 NOP CKE CLK hi
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$0FFC2 NOP CKE CLK lo, MOSI 0 (b22)
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$0FFC3 AREF CLK hi
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$0FFC4 NOP CKE CLK lo, MOSI Firmware[1] (b21)
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$0FFC5 NOP CKE CLK hi
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$0FFC6 NOP CKE CLK lo, MOSI Firmware[0] (b20)
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$0FFC7 NOP CKE CLK hi
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$0FFC8 NOP CKE CLK lo, MOSI 0 (b19)
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$0FFC9 NOP CKE CLK hi
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$0FFCA NOP CKE CLK lo, MOSI 0 (b18)
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$0FFCB AREF CLK hi
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$0FFCC NOP CKE CLK lo, MOSI 0 (b17)
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$0FFCD NOP CKE CLK hi
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$0FFCE NOP CKE CLK lo, MOSI 0 (b16)
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$0FFCF NOP CKE CLK hi
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$0FFD0 NOP CKE CLK lo, MOSI 0 (b15)
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$0FFD1 NOP CKE CLK hi
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$0FFD2 NOP CKE CLK lo, MOSI 0 (b14)
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$0FFD3 AREF CLK hi
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$0FFD4 NOP CKE CLK lo, MOSI 0 (b13)
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$0FFD5 NOP CKE CLK hi
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$0FFD6 NOP CKE CLK lo, MOSI 0 (b12)
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$0FFD7 NOP CKE CLK hi
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$0FFD8 NOP CKE CLK lo, MOSI 0 (b11)
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$0FFD9 NOP CKE CLK hi
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$0FFDA NOP CKE CLK lo, MOSI 0 (b10)
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$0FFDB AREF CLK hi
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$0FFDC NOP CKE CLK lo, MOSI 0 (b9)
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$0FFDD NOP CKE CLK hi
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$0FFDE NOP CKE CLK lo, MOSI 0 (b8)
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$0FFDF NOP CKE CLK hi
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$0FFE0 NOP CKE CLK lo, MOSI 0 (b7)
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$0FFE1 NOP CKE CLK hi
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$0FFE2 NOP CKE CLK lo, MOSI 0 (b6)
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$0FFE3 AREF CLK hi
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$0FFE4 NOP CKE CLK lo, MOSI 0 (b5)
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$0FFE5 NOP CKE CLK hi
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$0FFE6 NOP CKE CLK lo, MOSI 0 (b4)
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$0FFE7 NOP CKE CLK hi
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$0FFE8 NOP CKE CLK lo, MOSI 0 (b3)
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$0FFE9 NOP CKE CLK hi
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$0FFEA NOP CKE CLK lo, MOSI 0 (b2)
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$0FFEB AREF CLK hi
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$0FFEC NOP CKE CLK lo, MOSI 0 (b1)
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$0FFED NOP CKE CLK hi
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$0FFEE NOP CKE CLK lo, MOSI 0 (b0)
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$0FFEF NOP CKE CLK hi
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$0FFF0-$0FFFF Init: mode & ref 8 dummy clocks 2
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$0FFF0 NOP CKE CLK lo, MOSIOE 0
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$0FFF1 NOP CKE CLK hi
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$0FFF2 NOP CKE CLK lo
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$0FFF3 AREF CLK hi
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$0FFF4 NOP CKE CLK lo
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$0FFF5 NOP CKE CLK hi
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$0FFF6 NOP CKE CLK lo
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$0FFF7 NOP CKE CLK hi
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$0FFF8 NOP CKE CLK lo
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$0FFF9 NOP CKE CLK hi
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$0FFFA NOP CKE CLK lo
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$0FFFB AREF CLK hi
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$0FFFC NOP CKE CLK lo
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$0FFFD NOP CKE CLK hi
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$0FFFE NOP CKE CLK lo
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$0FFFF NOP CKE CLK hi
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$10000-$2FFFF Write ROM data Shift in read data 3
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$10000 NOP CKE CLK lo
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$10001 NOP CKE CLK hi, get b7:6 of $000000
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$10002 NOP CKE CLK lo
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$10003 AREF CLK hi, get b5:4 of $000000
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$10004 NOP CKE CLK lo
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$10005 ACT CLK hi, get b3:2 of $000000
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$10006 NOP CKE CLK lo
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$10007 WR AP CLK hi, get b1:0 of $000000
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$10008 NOP CKE CLK lo
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$10009 NOP CKE CLK hi, get b7:6 of $000001
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$1000A NOP CKE CLK lo
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$1000B AREF CLK hi, get b5:4 of $000001
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$1000C NOP CKE CLK lo
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$1000D ACT CLK hi, get b3:2 of $000001
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$1000E NOP CKE CLK lo
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$1000F WR AP CLK hi, get b1:0 of $000001
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...
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$2FFF0 NOP CKE CLK lo
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$2FFF1 NOP CKE CLK hi, get b7:6 of $003FFE
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$2FFF2 NOP CKE CLK lo
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$2FFF3 AREF CLK hi, get b5:4 of $003FFE
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$2FFF4 NOP CKE CLK lo
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$2FFF5 ACT CLK hi, get b3:2 of $003FFE
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$2FFF6 NOP CKE CLK lo
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$2FFF7 WR AP CLK hi, get b1:0 of $003FFE
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$2FFF8 NOP CKE CLK lo
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$2FFF9 NOP CKE CLK hi, get b7:6 of $003FFF
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$2FFFA NOP CKE CLK lo
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$2FFFB AREF CLK hi, get b5:4 of $003FFF
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$2FFFC NOP CKE CLK lo
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$2FFFD ACT CLK hi, get b3:2 of $003FFF
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$2FFFE NOP CKE CLK lo
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$2FFFF WR AP CLK hi, get b1:0 of $003FFF
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$30000 NOP CKE CLK lo, /CS hi 3
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$30001 NOP CKE CLK lo, /CS hi 3
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$30002 NOP CKE CLK lo, /CS hi 3 SDRAMActv <= InitActv && ~InitInterrupted
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LS SDRAM Flash IS
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-------------------------------------------------------------------
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$0000-$1FCE Nothing Nothing 0
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$1FCF Init: Precharge Nothing 1
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$1FD0-$1FFA Init: AREF Pause SPI Select 4
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$1FFB Init: AREF Pause Dual Read (0x3B) 5
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$1FFC Init: AREF Pause A[23:16] (0) 5
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$1FFD Init: AREF Pause A[15:08] (FW in 14:13) 5
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$1FFE Init: AREF Pause A[07:00] (0) 5
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$1FFF Init: AREF Pause Dummy 5
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$2000-$3FFF Init: Write ROM Shift MISO into WRD 6
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@ -13,21 +13,20 @@ GR8RAM/LibraryCard Slinky RAM memory map
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0 00 0000 | |
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-----------------------------
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Firmware area map (N=$0000, $2000, $4000, $6000)
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-----------------------------
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N+1FFF | |
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1 00 1FFF | |
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.... | IOSTRB bank 1 (2 kB) |
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N+1800 | |
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1 00 1800 | |
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-----------------------------
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N+17FF | |
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1 00 17FF | |
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.... | IOSEL bank 1 (2 kB) |
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N+1000 | |
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1 00 1000 | |
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-----------------------------
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N+0FFF | |
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1 00 0FFF | |
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.... | IOSTRB bank 0 (2 kB) |
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N+0800 | |
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1 00 0800 | |
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-----------------------------
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N+07FF | |
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1 00 07FF | |
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.... | IOSEL bank 0 (2 kB) |
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N+0000 | |
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1 00 0000 | |
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-----------------------------
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