diff --git a/cpld/GR8RAM.qpf b/cpld/GR8RAM.qpf old mode 100755 new mode 100644 index 01ef89f..c72b9e0 --- a/cpld/GR8RAM.qpf +++ b/cpld/GR8RAM.qpf @@ -1,29 +1,30 @@ # -------------------------------------------------------------------------- # # -# Copyright (C) 1991-2013 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic +# Copyright (C) 2022 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic # functions, and any output files from any of the foregoing # (including device programming or simulation files), and any # associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. # # -------------------------------------------------------------------------- # # -# Quartus II 32-bit -# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition -# Date created = 13:41:40 March 15, 2021 +# Quartus Prime +# Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition +# Date created = 11:15:44 February 28, 2023 # # -------------------------------------------------------------------------- # -QUARTUS_VERSION = "13.0" -DATE = "13:41:40 March 15, 2021" +QUARTUS_VERSION = "22.1" +DATE = "11:15:44 February 28, 2023" # Revisions diff --git a/cpld/GR8RAM.qsf b/cpld/GR8RAM.qsf old mode 100755 new mode 100644 index a55b9a9..e2e3f88 --- a/cpld/GR8RAM.qsf +++ b/cpld/GR8RAM.qsf @@ -39,8 +39,8 @@ set_global_assignment -name FAMILY "MAX II" set_global_assignment -name DEVICE EPM240T100C5 set_global_assignment -name TOP_LEVEL_ENTITY GR8RAM -set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" -set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:41:40 MARCH 15, 2021" +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 22.1STD.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:15:44 FEBRUARY 28, 2023" set_global_assignment -name LAST_QUARTUS_VERSION "22.1std.0 Lite Edition" set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 @@ -50,29 +50,14 @@ set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100 set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 5 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1" set_global_assignment -name POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR 3.3V -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF -set_global_assignment -name FITTER_EFFORT "STANDARD FIT" -set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE AREA -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF -set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON -set_global_assignment -name SAFE_STATE_MACHINE OFF -set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON -set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES ALWAYS -set_global_assignment -name AUTO_RESOURCE_SHARING ON -set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 2.0 -set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 2.0 -set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS -set_global_assignment -name ALM_REGISTER_PACKING_EFFORT HIGH -set_global_assignment -name MUX_RESTRUCTURE ON -set_global_assignment -name STATE_MACHINE_PROCESSING "MINIMAL BITS" -set_global_assignment -name SYNTHESIS_SEED 123 -set_global_assignment -name SEED 235 -set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII "MINIMIZE AREA" -set_global_assignment -name ROUTER_REGISTER_DUPLICATION OFF -set_global_assignment -name VERILOG_FILE GR8RAM.v -set_location_assignment PIN_1 -to RA[4] +set_global_assignment -name EDA_SIMULATION_TOOL "Questa Intel FPGA (Verilog)" +set_global_assignment -name EDA_NETLIST_WRITER_OUTPUT_DIR simulation/questa -section_id eda_simulation +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan set_location_assignment PIN_2 -to RA[5] set_location_assignment PIN_3 -to RA[6] set_location_assignment PIN_4 -to RA[3] diff --git a/cpld/GR8RAM.sdc b/cpld/GR8RAM.sdc old mode 100755 new mode 100644 diff --git a/cpld/GR8RAM_assignment_defaults.qdf b/cpld/GR8RAM_assignment_defaults.qdf deleted file mode 100644 index 31a43a3..0000000 --- a/cpld/GR8RAM_assignment_defaults.qdf +++ /dev/null @@ -1,806 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 2022 Intel Corporation. All rights reserved. -# Your use of Intel Corporation's design tools, logic functions -# and other software and tools, and any partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Intel Program License -# Subscription Agreement, the Intel Quartus Prime License Agreement, -# the Intel FPGA IP License Agreement, or other applicable license -# agreement, including, without limitation, that your use is for -# the sole purpose of programming logic devices manufactured by -# Intel and sold by Intel or its authorized distributors. Please -# refer to the applicable agreement for further details, at -# https://fpgasoftware.intel.com/eula. -# -# -------------------------------------------------------------------------- # -# -# Quartus Prime -# Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition -# Date created = 11:10:33 February 28, 2023 -# -# -------------------------------------------------------------------------- # -# -# Note: -# -# 1) Do not modify this file. This file was generated -# automatically by the Quartus Prime software and is used -# to preserve global assignments across Quartus Prime versions. -# -# -------------------------------------------------------------------------- # - -set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off -set_global_assignment -name IP_COMPONENT_INTERNAL Off -set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On -set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off -set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off -set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db -set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off -set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off -set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off -set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off -set_global_assignment -name HC_OUTPUT_DIR hc_output -set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off -set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off -set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On -set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off -set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings" -set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On -set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On -set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off -set_global_assignment -name REVISION_TYPE Base -family "Arria V" -set_global_assignment -name REVISION_TYPE Base -family "Stratix V" -set_global_assignment -name REVISION_TYPE Base -family "Arria V GZ" -set_global_assignment -name REVISION_TYPE Base -family "Cyclone V" -set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle" -set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On -set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On -set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On -set_global_assignment -name DO_COMBINED_ANALYSIS Off -set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off -set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off -set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off -set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off -set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On -set_global_assignment -name TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On -set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V" -set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone 10 LP" -set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "MAX 10" -set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix IV" -set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV E" -set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria 10" -set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX V" -set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix V" -set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V GZ" -set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX II" -set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GX" -set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GZ" -set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV GX" -set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone V" -set_global_assignment -name TIMING_ANALYZER_DO_REPORT_TIMING Off -set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V" -set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone 10 LP" -set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "MAX 10" -set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV" -set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E" -set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria 10" -set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V" -set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V" -set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ" -set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II" -set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX" -set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ" -set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX" -set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V" -set_global_assignment -name TIMING_ANALYZER_REPORT_NUM_WORST_CASE_TIMING_PATHS 100 -set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V" -set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone 10 LP" -set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "MAX 10" -set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV E" -set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix IV" -set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria 10" -set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX V" -set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix V" -set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V GZ" -set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX II" -set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GX" -set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GZ" -set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV GX" -set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone V" -set_global_assignment -name OPTIMIZATION_MODE Balanced -set_global_assignment -name ALLOW_REGISTER_MERGING On -set_global_assignment -name ALLOW_REGISTER_DUPLICATION On -set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V" -set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Cyclone 10 LP" -set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX 10" -set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix IV" -set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV E" -set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Arria 10" -set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX V" -set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix V" -set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V GZ" -set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX II" -set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GX" -set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GZ" -set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV GX" -set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone V" -set_global_assignment -name MUX_RESTRUCTURE Auto -set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off -set_global_assignment -name ENABLE_IP_DEBUG Off -set_global_assignment -name SAVE_DISK_SPACE On -set_global_assignment -name OCP_HW_EVAL -value OFF -set_global_assignment -name DEVICE_FILTER_PACKAGE Any -set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any -set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any -set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" -set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001 -set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993 -set_global_assignment -name FAMILY -value "Cyclone V" -set_global_assignment -name TRUE_WYSIWYG_FLOW Off -set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off -set_global_assignment -name STATE_MACHINE_PROCESSING Auto -set_global_assignment -name SAFE_STATE_MACHINE Off -set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On -set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On -set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off -set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000 -set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250 -set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On -set_global_assignment -name PARALLEL_SYNTHESIS On -set_global_assignment -name DSP_BLOCK_BALANCING Auto -set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)" -set_global_assignment -name NOT_GATE_PUSH_BACK On -set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On -set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off -set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On -set_global_assignment -name IGNORE_CARRY_BUFFERS Off -set_global_assignment -name IGNORE_CASCADE_BUFFERS Off -set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off -set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off -set_global_assignment -name IGNORE_LCELL_BUFFERS Off -set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO -set_global_assignment -name IGNORE_SOFT_BUFFERS On -set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off -set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off -set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On -set_global_assignment -name AUTO_GLOBAL_OE_MAX On -set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On -set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off -set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut -set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced -set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced -set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced -set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced -set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced -set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced -set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed -set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced -set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area -set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area -set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area -set_global_assignment -name ALLOW_XOR_GATE_USAGE On -set_global_assignment -name AUTO_LCELL_INSERTION On -set_global_assignment -name CARRY_CHAIN_LENGTH 48 -set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32 -set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32 -set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48 -set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70 -set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70 -set_global_assignment -name CASCADE_CHAIN_LENGTH 2 -set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16 -set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4 -set_global_assignment -name AUTO_CARRY_CHAINS On -set_global_assignment -name AUTO_CASCADE_CHAINS On -set_global_assignment -name AUTO_PARALLEL_EXPANDERS On -set_global_assignment -name AUTO_OPEN_DRAIN_PINS On -set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off -set_global_assignment -name AUTO_ROM_RECOGNITION On -set_global_assignment -name AUTO_RAM_RECOGNITION On -set_global_assignment -name AUTO_DSP_RECOGNITION On -set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto -set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto -set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On -set_global_assignment -name STRICT_RAM_RECOGNITION Off -set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On -set_global_assignment -name FORCE_SYNCH_CLEAR Off -set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On -set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off -set_global_assignment -name AUTO_RESOURCE_SHARING Off -set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off -set_global_assignment -name MAX7000_FANIN_PER_CELL 100 -set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On -set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)" -set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)" -set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)" -set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off -set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone 10 LP" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX" -set_global_assignment -name REPORT_PARAMETER_SETTINGS On -set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On -set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On -set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone 10 LP" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V" -set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation" -set_global_assignment -name HDL_MESSAGE_LEVEL Level2 -set_global_assignment -name USE_HIGH_SPEED_ADDER Auto -set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100 -set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000 -set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000 -set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off -set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000 -set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100 -set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On -set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off -set_global_assignment -name BLOCK_DESIGN_NAMING Auto -set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off -set_global_assignment -name SYNTHESIS_EFFORT Auto -set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On -set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off -set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium -set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone 10 LP" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX" -set_global_assignment -name MAX_LABS "-1 (Unlimited)" -set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On -set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)" -set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On -set_global_assignment -name PRPOF_ID Off -set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off -set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On -set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On -set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off -set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off -set_global_assignment -name AUTO_MERGE_PLLS On -set_global_assignment -name IGNORE_MODE_FOR_MERGE Off -set_global_assignment -name TXPMA_SLEW_RATE Low -set_global_assignment -name ADCE_ENABLED Auto -set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal -set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off -set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0 -set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0 -set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0 -set_global_assignment -name PHYSICAL_SYNTHESIS Off -set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off -set_global_assignment -name DEVICE AUTO -set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off -set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off -set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On -set_global_assignment -name ENABLE_NCEO_OUTPUT Off -set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin" -set_global_assignment -name STRATIXIII_UPDATE_MODE Standard -set_global_assignment -name STRATIX_UPDATE_MODE Standard -set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image" -set_global_assignment -name CVP_MODE Off -set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V" -set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10" -set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V" -set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ" -set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V" -set_global_assignment -name VID_OPERATION_MODE "PMBus Slave" -set_global_assignment -name USE_CONF_DONE AUTO -set_global_assignment -name USE_PWRMGT_SCL AUTO -set_global_assignment -name USE_PWRMGT_SDA AUTO -set_global_assignment -name USE_PWRMGT_ALERT AUTO -set_global_assignment -name USE_INIT_DONE AUTO -set_global_assignment -name USE_CVP_CONFDONE AUTO -set_global_assignment -name USE_SEU_ERROR AUTO -set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration" -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial" -set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial" -set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial" -set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name USER_START_UP_CLOCK Off -set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off -set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off -set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On -set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On -set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC -set_global_assignment -name ENABLE_VREFA_PIN Off -set_global_assignment -name ENABLE_VREFB_PIN Off -set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off -set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off -set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off -set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off -set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground" -set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off -set_global_assignment -name INIT_DONE_OPEN_DRAIN On -set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated" -set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated" -set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated" -set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin" -set_global_assignment -name ENABLE_CONFIGURATION_PINS On -set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off -set_global_assignment -name ENABLE_NCE_PIN Off -set_global_assignment -name ENABLE_BOOT_SEL_PIN On -set_global_assignment -name CRC_ERROR_CHECKING Off -set_global_assignment -name INTERNAL_SCRUBBING Off -set_global_assignment -name PR_ERROR_OPEN_DRAIN On -set_global_assignment -name PR_READY_OPEN_DRAIN On -set_global_assignment -name ENABLE_CVP_CONFDONE Off -set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On -set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone 10 LP" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone 10 LP" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V" -set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On -set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto -set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care -set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV" -set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10" -set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V" -set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ" -set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0 -set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On -set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation" -set_global_assignment -name OPTIMIZE_SSN Off -set_global_assignment -name OPTIMIZE_TIMING "Normal compilation" -set_global_assignment -name ECO_OPTIMIZE_TIMING Off -set_global_assignment -name ECO_REGENERATE_REPORT Off -set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal -set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off -set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically -set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically -set_global_assignment -name SEED 1 -set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF -set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off -set_global_assignment -name SLOW_SLEW_RATE Off -set_global_assignment -name PCI_IO Off -set_global_assignment -name TURBO_BIT On -set_global_assignment -name WEAK_PULL_UP_RESISTOR Off -set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off -set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off -set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On -set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto -set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto -set_global_assignment -name NORMAL_LCELL_INSERT On -set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone 10 LP" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX" -set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V" -set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF -set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off -set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off -set_global_assignment -name AUTO_TURBO_BIT ON -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off -set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off -set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off -set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off -set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On -set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off -set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off -set_global_assignment -name FITTER_EFFORT "Auto Fit" -set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns -set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal -set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto -set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto -set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off -set_global_assignment -name AUTO_GLOBAL_CLOCK On -set_global_assignment -name AUTO_GLOBAL_OE On -set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On -set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic -set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off -set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off -set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off -set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off -set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off -set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off -set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off -set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off -set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off -set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off -set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off -set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off -set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off -set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off -set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off -set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up" -set_global_assignment -name ENABLE_HOLD_BACK_OFF On -set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto -set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off -set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto -set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On -set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On -set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone 10 LP" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V" -set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)" -set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)" -set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)" -set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)" -set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10" -set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V" -set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V" -set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX" -set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ" -set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V" -set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX" -set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off -set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On -set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off -set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off -set_global_assignment -name PR_DONE_OPEN_DRAIN On -set_global_assignment -name NCEO_OPEN_DRAIN On -set_global_assignment -name ENABLE_CRC_ERROR_PIN Off -set_global_assignment -name ENABLE_PR_PINS Off -set_global_assignment -name RESERVE_PR_PINS Off -set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off -set_global_assignment -name PR_PINS_OPEN_DRAIN Off -set_global_assignment -name CLAMPING_DIODE Off -set_global_assignment -name TRI_STATE_SPI_PINS Off -set_global_assignment -name UNUSED_TSD_PINS_GND Off -set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off -set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off -set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium -set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V" -set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV" -set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10" -set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V" -set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ" -set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V" -set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0 -set_global_assignment -name SEU_FIT_REPORT Off -set_global_assignment -name HYPER_RETIMER Off -family "Arria 10" -set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1" -set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto -set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto -set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On -set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On -set_global_assignment -name EDA_SIMULATION_TOOL "" -set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" -set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "" -set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "" -set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "" -set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "" -set_global_assignment -name EDA_BOARD_DESIGN_TOOL "" -set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "" -set_global_assignment -name EDA_RESYNTHESIS_TOOL "" -set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On -set_global_assignment -name COMPRESSION_MODE Off -set_global_assignment -name CLOCK_SOURCE Internal -set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz" -set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1 -set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On -set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off -set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On -set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF -set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F -set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off -set_global_assignment -name USE_CHECKSUM_AS_USERCODE On -set_global_assignment -name SECURITY_BIT Off -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone 10 LP" -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10" -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E" -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV" -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V" -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II" -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX" -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ" -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX" -set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto -set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto -set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130" -set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000 -set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000 -set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000 -set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000 -set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000 -set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000 -set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000 -set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000 -set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery" -set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0 -set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0 -set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0 -set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto -set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto -set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto -set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto -set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto -set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto -set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off -set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On -set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off -set_global_assignment -name GENERATE_TTF_FILE Off -set_global_assignment -name GENERATE_RBF_FILE Off -set_global_assignment -name GENERATE_HEX_FILE Off -set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0 -set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up -set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal" -set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off -set_global_assignment -name AUTO_RESTART_CONFIGURATION On -set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off -set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off -set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On -set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V" -set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone 10 LP" -set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10" -set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E" -set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10" -set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V" -set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ" -set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX" -set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX" -set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V" -set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF -set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off -set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off -set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off -set_global_assignment -name POR_SCHEME "Instant ON" -set_global_assignment -name EN_USER_IO_WEAK_PULLUP On -set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On -set_global_assignment -name POF_VERIFY_PROTECT Off -set_global_assignment -name ENABLE_SPI_MODE_CHECK Off -set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On -set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off -set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0 -set_global_assignment -name GENERATE_PMSF_FILES On -set_global_assignment -name START_TIME 0ns -set_global_assignment -name SIMULATION_MODE TIMING -set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off -set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On -set_global_assignment -name SETUP_HOLD_DETECTION Off -set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -set_global_assignment -name CHECK_OUTPUTS Off -set_global_assignment -name SIMULATION_COVERAGE On -set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On -set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On -set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On -set_global_assignment -name GLITCH_DETECTION Off -set_global_assignment -name GLITCH_INTERVAL 1ns -set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off -set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On -set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off -set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On -set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE -set_global_assignment -name SIMULATION_NETLIST_VIEWER Off -set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT -set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT -set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off -set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO -set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO -set_global_assignment -name DRC_TOP_FANOUT 50 -set_global_assignment -name DRC_FANOUT_EXCEEDING 30 -set_global_assignment -name DRC_GATED_CLOCK_FEED 30 -set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY -set_global_assignment -name ENABLE_DRC_SETTINGS Off -set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25 -set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10 -set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30 -set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2 -set_global_assignment -name MERGE_HEX_FILE Off -set_global_assignment -name GENERATE_SVF_FILE Off -set_global_assignment -name GENERATE_ISC_FILE Off -set_global_assignment -name GENERATE_JAM_FILE Off -set_global_assignment -name GENERATE_JBC_FILE Off -set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On -set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off -set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off -set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off -set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off -set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On -set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off -set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state" -set_global_assignment -name HPS_EARLY_IO_RELEASE Off -set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off -set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off -set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5% -set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5% -set_global_assignment -name POWER_USE_PVA On -set_global_assignment -name POWER_USE_INPUT_FILE "No File" -set_global_assignment -name POWER_USE_INPUT_FILES Off -set_global_assignment -name POWER_VCD_FILTER_GLITCHES On -set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off -set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off -set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL -set_global_assignment -name POWER_AUTO_COMPUTE_TJ On -set_global_assignment -name POWER_TJ_VALUE 25 -set_global_assignment -name POWER_USE_TA_VALUE 25 -set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off -set_global_assignment -name POWER_BOARD_TEMPERATURE 25 -set_global_assignment -name POWER_HPS_ENABLE Off -set_global_assignment -name POWER_HPS_PROC_FREQ 0.0 -set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off -set_global_assignment -name IGNORE_PARTITIONS Off -set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off -set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On -set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End" -set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On -set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On -set_global_assignment -name RTLV_GROUP_RELATED_NODES On -set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off -set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off -set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On -set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On -set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On -set_global_assignment -name EQC_BBOX_MERGE On -set_global_assignment -name EQC_LVDS_MERGE On -set_global_assignment -name EQC_RAM_UNMERGING On -set_global_assignment -name EQC_DFF_SS_EMULATION On -set_global_assignment -name EQC_RAM_REGISTER_UNPACK On -set_global_assignment -name EQC_MAC_REGISTER_UNPACK On -set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On -set_global_assignment -name EQC_STRUCTURE_MATCHING On -set_global_assignment -name EQC_AUTO_BREAK_CONE On -set_global_assignment -name EQC_POWER_UP_COMPARE Off -set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On -set_global_assignment -name EQC_AUTO_INVERSION On -set_global_assignment -name EQC_AUTO_TERMINATE On -set_global_assignment -name EQC_SUB_CONE_REPORT Off -set_global_assignment -name EQC_RENAMING_RULES On -set_global_assignment -name EQC_PARAMETER_CHECK On -set_global_assignment -name EQC_AUTO_PORTSWAP On -set_global_assignment -name EQC_DETECT_DONT_CARES On -set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off -set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ? -set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ? -set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ? -set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ? -set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ? -set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ? -set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ? -set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ? -set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ? -set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ? -set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "" -section_id ? -set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ? -set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ? -set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ? -set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ? -set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ? -set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ? -set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ? -set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ? -set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ? -set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ? -set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ? -set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ? -set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ? -set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST On -section_id ? -set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ? -set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ? -set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ? -set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ? -set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ? -set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ? -set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ? -set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ? -set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ? -set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR Off -section_id ? -set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ? -set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ? -set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ? -set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ? -set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ? -set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -section_id ? -set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ? -set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ? -set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ? -set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ? -set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ? -set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ? -set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ? -set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ? -set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ? -set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ? -set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ? -set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ? -set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ? -set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ? -set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ? -set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ? -set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ? -set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ? -set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ? -set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ? -set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ? -set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ? -set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ? -set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ? diff --git a/cpld/UFM.qip b/cpld/UFM.qip deleted file mode 100755 index e2d8458..0000000 --- a/cpld/UFM.qip +++ /dev/null @@ -1,3 +0,0 @@ -set_global_assignment -name IP_TOOL_NAME "ALTUFM_NONE" -set_global_assignment -name IP_TOOL_VERSION "13.0" -set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "UFM.v"] diff --git a/cpld/db/.cmp.kpt b/cpld/db/.cmp.kpt new file mode 100644 index 0000000..eaedafd Binary files /dev/null and b/cpld/db/.cmp.kpt differ diff --git a/cpld/db/GR8RAM.(0).cnf.cdb b/cpld/db/GR8RAM.(0).cnf.cdb new file mode 100644 index 0000000..2b5b869 Binary files /dev/null and b/cpld/db/GR8RAM.(0).cnf.cdb differ diff --git a/cpld/db/GR8RAM.(0).cnf.hdb b/cpld/db/GR8RAM.(0).cnf.hdb new file mode 100644 index 0000000..8144461 Binary files /dev/null and b/cpld/db/GR8RAM.(0).cnf.hdb differ diff --git a/cpld/db/GR8RAM.asm.qmsg b/cpld/db/GR8RAM.asm.qmsg new file mode 100644 index 0000000..1a146da --- /dev/null +++ b/cpld/db/GR8RAM.asm.qmsg @@ -0,0 +1,7 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1677601285636 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition " "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1677601285638 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 28 11:21:25 2023 " "Processing started: Tue Feb 28 11:21:25 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1677601285638 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1677601285638 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1677601285639 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1677601285947 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1677601286047 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1677601286058 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13100 " "Peak virtual memory: 13100 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1677601286355 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 28 11:21:26 2023 " "Processing ended: Tue Feb 28 11:21:26 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1677601286355 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1677601286355 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1677601286355 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1677601286355 ""} diff --git a/cpld/db/GR8RAM.asm.rdb b/cpld/db/GR8RAM.asm.rdb new file mode 100644 index 0000000..33b1b52 Binary files /dev/null and b/cpld/db/GR8RAM.asm.rdb differ diff --git a/cpld/db/GR8RAM.asm_labs.ddb b/cpld/db/GR8RAM.asm_labs.ddb new file mode 100644 index 0000000..5fb602f Binary files /dev/null and b/cpld/db/GR8RAM.asm_labs.ddb differ diff --git a/cpld/db/GR8RAM.cmp.cdb b/cpld/db/GR8RAM.cmp.cdb new file mode 100644 index 0000000..db20137 Binary files /dev/null and b/cpld/db/GR8RAM.cmp.cdb differ diff --git a/cpld/db/GR8RAM.cmp.hdb b/cpld/db/GR8RAM.cmp.hdb new file mode 100644 index 0000000..d568531 Binary files /dev/null and b/cpld/db/GR8RAM.cmp.hdb differ diff --git a/cpld/db/GR8RAM.cmp.idb b/cpld/db/GR8RAM.cmp.idb new file mode 100644 index 0000000..608e6ab Binary files /dev/null and b/cpld/db/GR8RAM.cmp.idb differ diff --git a/cpld/db/GR8RAM.cmp.logdb b/cpld/db/GR8RAM.cmp.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/cpld/db/GR8RAM.cmp.logdb @@ -0,0 +1 @@ +v1 diff --git a/cpld/db/GR8RAM.cmp.rdb b/cpld/db/GR8RAM.cmp.rdb new file mode 100644 index 0000000..efc33c3 Binary files /dev/null and b/cpld/db/GR8RAM.cmp.rdb differ diff --git a/cpld/db/GR8RAM.cmp0.ddb b/cpld/db/GR8RAM.cmp0.ddb new file mode 100644 index 0000000..8628242 Binary files /dev/null and b/cpld/db/GR8RAM.cmp0.ddb differ diff --git a/cpld/db/GR8RAM.eda.qmsg b/cpld/db/GR8RAM.eda.qmsg new file mode 100644 index 0000000..cdd2c87 --- /dev/null +++ b/cpld/db/GR8RAM.eda.qmsg @@ -0,0 +1,6 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1677601290645 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition " "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1677601290647 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 28 11:21:30 2023 " "Processing started: Tue Feb 28 11:21:30 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1677601290647 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1677601290647 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_eda --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1677601290647 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1677601291072 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "GR8RAM.vo /Repos2/GR8RAM/cpld2/simulation/questa/ simulation " "Generated file GR8RAM.vo in folder \"/Repos2/GR8RAM/cpld2/simulation/questa/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1677601291254 ""} +{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13024 " "Peak virtual memory: 13024 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1677601291299 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 28 11:21:31 2023 " "Processing ended: Tue Feb 28 11:21:31 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1677601291299 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1677601291299 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1677601291299 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1677601291299 ""} diff --git a/cpld/db/GR8RAM.fit.qmsg b/cpld/db/GR8RAM.fit.qmsg new file mode 100644 index 0000000..efe5afc --- /dev/null +++ b/cpld/db/GR8RAM.fit.qmsg @@ -0,0 +1,44 @@ +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1677601279685 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1677601279686 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1677601279701 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1677601279826 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1677601279827 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1677601280022 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1677601280063 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1677601280624 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1677601280624 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1677601280624 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1677601280624 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1677601280624 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1677601280624 ""} +{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "1 80 " "No exact pin location assignment(s) for 1 pins of 80 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1677601280753 ""} +{ "Info" "ISTA_SDC_FOUND" "GR8RAM.sdc " "Reading SDC File: 'GR8RAM.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1677601280874 ""} +{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1677601280923 ""} +{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1677601280925 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1677601280925 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 40.000 C25M " " 40.000 C25M" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1677601280925 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 978.000 PHI0 " " 978.000 PHI0" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1677601280925 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1677601280925 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1677601280945 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1677601280946 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1677601280959 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" { } { { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 9 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1677601280992 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI0 Global clock " "Automatically promoted some destinations of signal \"PHI0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~0 " "Destination \"comb~0\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1677601280992 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI0r1 " "Destination \"PHI0r1\" may be non-global or may not use global clock" { } { { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 10 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1677601280992 ""} } { { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 9 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1677601280992 ""} +{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI0 " "Pin \"PHI0\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/22.1std/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/22.1std/quartus/bin64/pin_planner.ppl" { PHI0 } } } { "c:/intelfpga_lite/22.1std/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/22.1std/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PHI0" } } } } { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 9 -1 0 } } { "temporary_test_loc" "" { Generic "//mac/iCloud/Repos2/GR8RAM/cpld2/" { { 0 { 0 ""} 0 418 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1677601280992 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nRESr Global clock " "Automatically promoted some destinations of signal \"nRESr\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "IOROMEN " "Destination \"IOROMEN\" may be non-global or may not use global clock" { } { { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 94 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1677601280993 ""} } { { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 16 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1677601280993 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1677601280994 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1677601281004 ""} +{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1677601281114 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1677601281203 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1677601281204 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1677601281205 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1677601281205 ""} +{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "1 unused 3.3V 1 0 0 " "Number of I/O pins in group: 1 (unused VREF, 3.3V VCCIO, 1 input, 0 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "I/O standards used: 3.3-V LVTTL." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Design Software" 0 -1 1677601281234 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Design Software" 0 -1 1677601281234 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1677601281234 ""} +{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.3V 38 0 " "I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 38 total pin(s) used -- 0 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1677601281236 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use 3.3V 41 1 " "I/O bank number 2 does not use VREF pins and has 3.3V VCCIO pins. 41 total pin(s) used -- 1 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1677601281236 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Design Software" 0 -1 1677601281236 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1677601281236 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1677601281325 ""} +{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1677601281341 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1677601281559 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1677601281888 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1677601281913 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1677601282469 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1677601282469 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1677601282537 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "30 " "Router estimated average interconnect usage is 30% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "30 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 30% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "//mac/iCloud/Repos2/GR8RAM/cpld2/" { { 1 { 0 "Router estimated peak interconnect usage is 30% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 12 { 0 ""} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1677601282887 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1677601282887 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1677601282982 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1677601282982 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1677601282982 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1677601282986 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.27 " "Total time spent on timing analysis during the Fitter is 0.27 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1677601283019 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1677601283056 ""} +{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1677601283164 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/Repos2/GR8RAM/cpld2/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file /Repos2/GR8RAM/cpld2/output_files/GR8RAM.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1677601283280 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13746 " "Peak virtual memory: 13746 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1677601283368 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 28 11:21:23 2023 " "Processing ended: Tue Feb 28 11:21:23 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1677601283368 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1677601283368 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1677601283368 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1677601283368 ""} diff --git a/cpld/db/GR8RAM.hier_info b/cpld/db/GR8RAM.hier_info new file mode 100644 index 0000000..554e4da --- /dev/null +++ b/cpld/db/GR8RAM.hier_info @@ -0,0 +1,220 @@ +|GR8RAM +C25M => SA[0]~reg0.CLK +C25M => SA[1]~reg0.CLK +C25M => SA[2]~reg0.CLK +C25M => SA[3]~reg0.CLK +C25M => SA[4]~reg0.CLK +C25M => SA[5]~reg0.CLK +C25M => SA[6]~reg0.CLK +C25M => SA[7]~reg0.CLK +C25M => SA[8]~reg0.CLK +C25M => SA[9]~reg0.CLK +C25M => SA[10]~reg0.CLK +C25M => SA[11]~reg0.CLK +C25M => SA[12]~reg0.CLK +C25M => SBA[0]~reg0.CLK +C25M => SBA[1]~reg0.CLK +C25M => DQMH~reg0.CLK +C25M => DQML~reg0.CLK +C25M => SDOE.CLK +C25M => nSWE~reg0.CLK +C25M => nCAS~reg0.CLK +C25M => nRAS~reg0.CLK +C25M => nRCS~reg0.CLK +C25M => RCKE~reg0.CLK +C25M => WRD[0].CLK +C25M => WRD[1].CLK +C25M => WRD[2].CLK +C25M => WRD[3].CLK +C25M => WRD[4].CLK +C25M => WRD[5].CLK +C25M => WRD[6].CLK +C25M => WRD[7].CLK +C25M => MOSIout.CLK +C25M => FCKOE.CLK +C25M => MOSIOE.CLK +C25M => FCS.CLK +C25M => FCKout.CLK +C25M => Bank.CLK +C25M => AddrIncH.CLK +C25M => AddrIncM.CLK +C25M => AddrIncL.CLK +C25M => Addr[0].CLK +C25M => Addr[1].CLK +C25M => Addr[2].CLK +C25M => Addr[3].CLK +C25M => Addr[4].CLK +C25M => Addr[5].CLK +C25M => Addr[6].CLK +C25M => Addr[7].CLK +C25M => Addr[8].CLK +C25M => Addr[9].CLK +C25M => Addr[10].CLK +C25M => Addr[11].CLK +C25M => Addr[12].CLK +C25M => Addr[13].CLK +C25M => Addr[14].CLK +C25M => Addr[15].CLK +C25M => Addr[16].CLK +C25M => Addr[17].CLK +C25M => Addr[18].CLK +C25M => Addr[19].CLK +C25M => Addr[20].CLK +C25M => Addr[21].CLK +C25M => Addr[22].CLK +C25M => Addr[23].CLK +C25M => IOROMEN.CLK +C25M => nIOSTRBr.CLK +C25M => REGEN.CLK +C25M => nRESout~reg0.CLK +C25M => LS[0].CLK +C25M => LS[1].CLK +C25M => LS[2].CLK +C25M => LS[3].CLK +C25M => LS[4].CLK +C25M => LS[5].CLK +C25M => LS[6].CLK +C25M => LS[7].CLK +C25M => LS[8].CLK +C25M => LS[9].CLK +C25M => LS[10].CLK +C25M => LS[11].CLK +C25M => LS[12].CLK +C25M => LS[13].CLK +C25M => PS[0].CLK +C25M => PS[1].CLK +C25M => PS[2].CLK +C25M => PS[3].CLK +C25M => SetFWr[0].CLK +C25M => SetFWr[1].CLK +C25M => SetFWLoaded.CLK +C25M => nRESr.CLK +C25M => nRESf[0].CLK +C25M => nRESf[1].CLK +C25M => nRESf[2].CLK +C25M => nRESf[3].CLK +C25M => PHI0r2.CLK +C25M => PHI0r1.CLK +C25M => IS~7.DATAIN +C25M => RDD[0].CLK +C25M => RDD[1].CLK +C25M => RDD[2].CLK +C25M => RDD[3].CLK +C25M => RDD[4].CLK +C25M => RDD[5].CLK +C25M => RDD[6].CLK +C25M => RDD[7].CLK +PHI0 => comb.IN1 +PHI0 => nWEr.CLK +PHI0 => RAr[0].CLK +PHI0 => RAr[1].CLK +PHI0 => RAr[2].CLK +PHI0 => RAr[3].CLK +PHI0 => RAr[4].CLK +PHI0 => RAr[5].CLK +PHI0 => RAr[6].CLK +PHI0 => RAr[7].CLK +PHI0 => RAr[8].CLK +PHI0 => RAr[9].CLK +PHI0 => RAr[10].CLK +PHI0 => RAr[11].CLK +PHI0 => CXXXr.CLK +PHI0 => PHI0r1.DATAIN +nRES => nRESf[0].DATAIN +nRESout <= nRESout~reg0.DB_MAX_OUTPUT_PORT_TYPE +SetFW[0] => SetFWr[0].DATAIN +SetFW[1] => SetFWr[1].DATAIN +INTin => INTout.DATAIN +INTout <= INTin.DB_MAX_OUTPUT_PORT_TYPE +DMAin => DMAout.DATAIN +DMAout <= DMAin.DB_MAX_OUTPUT_PORT_TYPE +nNMIout <= +nIRQout <= +nRDYout <= +nINHout <= +RWout <= +nDMAout <= +RA[0] => RAr[0].DATAIN +RA[0] => Equal16.IN10 +RA[1] => RAr[1].DATAIN +RA[1] => Equal16.IN9 +RA[2] => RAr[2].DATAIN +RA[2] => Equal16.IN8 +RA[3] => RAr[3].DATAIN +RA[3] => Equal16.IN7 +RA[4] => RAr[4].DATAIN +RA[4] => Equal16.IN6 +RA[5] => RAr[5].DATAIN +RA[5] => Equal16.IN5 +RA[6] => RAr[6].DATAIN +RA[6] => Equal16.IN4 +RA[7] => RAr[7].DATAIN +RA[7] => Equal16.IN3 +RA[8] => RAr[8].DATAIN +RA[8] => Equal16.IN2 +RA[9] => RAr[9].DATAIN +RA[9] => Equal16.IN1 +RA[10] => RAr[10].DATAIN +RA[10] => Equal16.IN0 +RA[11] => RAr[11].DATAIN +RA[12] => Equal8.IN1 +RA[13] => Equal8.IN0 +RA[14] => Equal8.IN3 +RA[15] => Equal8.IN2 +nWE => comb.IN1 +nWE => nWEr.DATAIN +RD[0] <> RD[0] +RD[1] <> RD[1] +RD[2] <> RD[2] +RD[3] <> RD[3] +RD[4] <> RD[4] +RD[5] <> RD[5] +RD[6] <> RD[6] +RD[7] <> RD[7] +RAdir <= +RDdir <= comb.DB_MAX_OUTPUT_PORT_TYPE +nIOSEL => comb.IN0 +nIOSEL => always7.IN1 +nDEVSEL => comb.IN1 +nDEVSEL => RAMSEL.IN1 +nDEVSEL => comb.IN1 +nDEVSEL => RAMRegSEL.IN1 +nIOSTRB => nIOSTRBr.DATAIN +nIOSTRB => comb.IN1 +nIOSTRB => comb.IN1 +SBA[0] <= SBA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +SBA[1] <= SBA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +SA[0] <= SA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +SA[1] <= SA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +SA[2] <= SA[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +SA[3] <= SA[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +SA[4] <= SA[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +SA[5] <= SA[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +SA[6] <= SA[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +SA[7] <= SA[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +SA[8] <= SA[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +SA[9] <= SA[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +SA[10] <= SA[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +SA[11] <= SA[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +SA[12] <= SA[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +nRCS <= nRCS~reg0.DB_MAX_OUTPUT_PORT_TYPE +nRAS <= nRAS~reg0.DB_MAX_OUTPUT_PORT_TYPE +nCAS <= nCAS~reg0.DB_MAX_OUTPUT_PORT_TYPE +nSWE <= nSWE~reg0.DB_MAX_OUTPUT_PORT_TYPE +DQML <= DQML~reg0.DB_MAX_OUTPUT_PORT_TYPE +DQMH <= DQMH~reg0.DB_MAX_OUTPUT_PORT_TYPE +RCKE <= RCKE~reg0.DB_MAX_OUTPUT_PORT_TYPE +SD[0] <> SD[0] +SD[1] <> SD[1] +SD[2] <> SD[2] +SD[3] <> SD[3] +SD[4] <> SD[4] +SD[5] <> SD[5] +SD[6] <> SD[6] +SD[7] <> SD[7] +nFCS <= nFCS.DB_MAX_OUTPUT_PORT_TYPE +FCK <= FCK.DB_MAX_OUTPUT_PORT_TYPE +MISO => WRD.DATAB +MOSI <> MOSI + + diff --git a/cpld/db/GR8RAM.hif b/cpld/db/GR8RAM.hif new file mode 100644 index 0000000..078099c Binary files /dev/null and b/cpld/db/GR8RAM.hif differ diff --git a/cpld/db/GR8RAM.lpc.html b/cpld/db/GR8RAM.lpc.html new file mode 100644 index 0000000..fbc5ab5 --- /dev/null +++ b/cpld/db/GR8RAM.lpc.html @@ -0,0 +1,18 @@ + + + + + + + + + + + + + + + + + +
HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
diff --git a/cpld/db/GR8RAM.lpc.rdb b/cpld/db/GR8RAM.lpc.rdb new file mode 100644 index 0000000..d6f342b Binary files /dev/null and b/cpld/db/GR8RAM.lpc.rdb differ diff --git a/cpld/db/GR8RAM.lpc.txt b/cpld/db/GR8RAM.lpc.txt new file mode 100644 index 0000000..a463804 --- /dev/null +++ b/cpld/db/GR8RAM.lpc.txt @@ -0,0 +1,5 @@ ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Legal Partition Candidates ; ++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; ++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ diff --git a/cpld/db/GR8RAM.map.cdb b/cpld/db/GR8RAM.map.cdb new file mode 100644 index 0000000..174f702 Binary files /dev/null and b/cpld/db/GR8RAM.map.cdb differ diff --git a/cpld/db/GR8RAM.map.hdb b/cpld/db/GR8RAM.map.hdb new file mode 100644 index 0000000..ec0d4a9 Binary files /dev/null and b/cpld/db/GR8RAM.map.hdb differ diff --git a/cpld/db/GR8RAM.map.logdb b/cpld/db/GR8RAM.map.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/cpld/db/GR8RAM.map.logdb @@ -0,0 +1 @@ +v1 diff --git a/cpld/db/GR8RAM.map.qmsg b/cpld/db/GR8RAM.map.qmsg new file mode 100644 index 0000000..42130c6 --- /dev/null +++ b/cpld/db/GR8RAM.map.qmsg @@ -0,0 +1,19 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1677601254100 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition " "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1677601254102 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 28 11:20:53 2023 " "Processing started: Tue Feb 28 11:20:53 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1677601254102 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1677601254102 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1677601254103 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1677601254505 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1677601254505 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "gr8ram.v(110) " "Verilog HDL warning at gr8ram.v(110): extended using \"x\" or \"z\"" { } { { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 110 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1677601274977 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "gr8ram.v(286) " "Verilog HDL warning at gr8ram.v(286): extended using \"x\" or \"z\"" { } { { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 286 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1677601274981 ""} +{ "Warning" "WSGN_SEARCH_FILE" "gr8ram.v 1 1 " "Using design file gr8ram.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1677601274993 ""} } { } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1677601274993 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1677601275007 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 gr8ram.v(42) " "Verilog HDL assignment warning at gr8ram.v(42): truncated value with size 32 to match size of target (4)" { } { { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 42 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1677601275027 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 gr8ram.v(47) " "Verilog HDL assignment warning at gr8ram.v(47): truncated value with size 32 to match size of target (14)" { } { { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 47 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1677601275028 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 gr8ram.v(134) " "Verilog HDL assignment warning at gr8ram.v(134): truncated value with size 32 to match size of target (8)" { } { { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 134 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1677601275033 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 gr8ram.v(142) " "Verilog HDL assignment warning at gr8ram.v(142): truncated value with size 32 to match size of target (8)" { } { { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 142 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1677601275033 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 gr8ram.v(149) " "Verilog HDL assignment warning at gr8ram.v(149): truncated value with size 32 to match size of target (8)" { } { { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 149 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1677601275034 "|GR8RAM"} +{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "nNMIout VCC " "Pin \"nNMIout\" is stuck at VCC" { } { { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 563 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1677601275953 "|GR8RAM|nNMIout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nIRQout VCC " "Pin \"nIRQout\" is stuck at VCC" { } { { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 566 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1677601275953 "|GR8RAM|nIRQout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nRDYout VCC " "Pin \"nRDYout\" is stuck at VCC" { } { { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 565 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1677601275953 "|GR8RAM|nRDYout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nINHout VCC " "Pin \"nINHout\" is stuck at VCC" { } { { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 564 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1677601275953 "|GR8RAM|nINHout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RWout VCC " "Pin \"RWout\" is stuck at VCC" { } { { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 567 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1677601275953 "|GR8RAM|RWout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nDMAout VCC " "Pin \"nDMAout\" is stuck at VCC" { } { { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 562 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1677601275953 "|GR8RAM|nDMAout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "gr8ram.v" "" { Text "//mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v" 561 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1677601275953 "|GR8RAM|RAdir"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1677601275953 ""} +{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "3 " "3 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1677601276221 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "333 " "Implemented 333 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "28 " "Implemented 28 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1677601276250 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1677601276250 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Design Software" 0 -1 1677601276250 ""} { "Info" "ICUT_CUT_TM_LCELLS" "253 " "Implemented 253 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1677601276250 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1677601276250 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/Repos2/GR8RAM/cpld2/output_files/GR8RAM.map.smsg " "Generated suppressed messages file /Repos2/GR8RAM/cpld2/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1677601276457 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 15 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 15 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13114 " "Peak virtual memory: 13114 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1677601276495 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 28 11:21:16 2023 " "Processing ended: Tue Feb 28 11:21:16 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1677601276495 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:23 " "Elapsed time: 00:00:23" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1677601276495 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:48 " "Total CPU time (on all processors): 00:00:48" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1677601276495 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1677601276495 ""} diff --git a/cpld/db/GR8RAM.map.rdb b/cpld/db/GR8RAM.map.rdb new file mode 100644 index 0000000..e85039e Binary files /dev/null and b/cpld/db/GR8RAM.map.rdb differ diff --git a/cpld/db/GR8RAM.pre_map.hdb b/cpld/db/GR8RAM.pre_map.hdb new file mode 100644 index 0000000..e21c913 Binary files /dev/null and b/cpld/db/GR8RAM.pre_map.hdb differ diff --git a/cpld/db/GR8RAM.root_partition.map.reg_db.cdb b/cpld/db/GR8RAM.root_partition.map.reg_db.cdb new file mode 100644 index 0000000..01ff862 Binary files /dev/null and b/cpld/db/GR8RAM.root_partition.map.reg_db.cdb differ diff --git a/cpld/db/GR8RAM.routing.rdb b/cpld/db/GR8RAM.routing.rdb new file mode 100644 index 0000000..c2bcb55 Binary files /dev/null and b/cpld/db/GR8RAM.routing.rdb differ diff --git a/cpld/db/GR8RAM.rtlv.hdb b/cpld/db/GR8RAM.rtlv.hdb new file mode 100644 index 0000000..95ea829 Binary files /dev/null and b/cpld/db/GR8RAM.rtlv.hdb differ diff --git a/cpld/db/GR8RAM.rtlv_sg.cdb b/cpld/db/GR8RAM.rtlv_sg.cdb new file mode 100644 index 0000000..fb019a1 Binary files /dev/null and b/cpld/db/GR8RAM.rtlv_sg.cdb differ diff --git a/cpld/db/GR8RAM.rtlv_sg_swap.cdb b/cpld/db/GR8RAM.rtlv_sg_swap.cdb new file mode 100644 index 0000000..e6db90d Binary files /dev/null and b/cpld/db/GR8RAM.rtlv_sg_swap.cdb differ diff --git a/cpld2/db/GR8RAM.sld_design_entry.sci b/cpld/db/GR8RAM.sld_design_entry_dsc.sci similarity index 100% rename from cpld2/db/GR8RAM.sld_design_entry.sci rename to cpld/db/GR8RAM.sld_design_entry_dsc.sci diff --git a/cpld/db/GR8RAM.smart_action.txt b/cpld/db/GR8RAM.smart_action.txt new file mode 100644 index 0000000..c8e8a13 --- /dev/null +++ b/cpld/db/GR8RAM.smart_action.txt @@ -0,0 +1 @@ +DONE diff --git a/cpld/db/GR8RAM.smp_dump.txt b/cpld/db/GR8RAM.smp_dump.txt new file mode 100644 index 0000000..30f490a --- /dev/null +++ b/cpld/db/GR8RAM.smp_dump.txt @@ -0,0 +1,9 @@ + +State Machine - |GR8RAM|IS +Name IS.111 IS.110 IS.101 IS.100 IS.001 IS.000 +IS.000 0 0 0 0 0 0 +IS.001 0 0 0 0 1 1 +IS.100 0 0 0 1 0 1 +IS.101 0 0 1 0 0 1 +IS.110 0 1 0 0 0 1 +IS.111 1 0 0 0 0 1 diff --git a/cpld/db/GR8RAM.sta.qmsg b/cpld/db/GR8RAM.sta.qmsg new file mode 100644 index 0000000..34439db --- /dev/null +++ b/cpld/db/GR8RAM.sta.qmsg @@ -0,0 +1,22 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1677601288128 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition " "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1677601288129 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 28 11:21:27 2023 " "Processing started: Tue Feb 28 11:21:27 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1677601288129 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1677601288129 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1677601288130 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1677601288250 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1677601288411 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1677601288411 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1677601288455 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1677601288455 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1677601288513 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1677601288921 ""} +{ "Info" "ISTA_SDC_FOUND" "GR8RAM.sdc " "Reading SDC File: 'GR8RAM.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Timing Analyzer" 0 -1 1677601289007 ""} +{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1677601289045 ""} +{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1677601289084 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup 10.278 " "Worst-case setup slack is 10.278" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1677601289092 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1677601289092 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 10.278 0.000 C25M " " 10.278 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1677601289092 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1677601289092 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.376 " "Worst-case hold slack is 1.376" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1677601289097 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1677601289097 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.376 0.000 C25M " " 1.376 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1677601289097 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1677601289097 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 33.311 " "Worst-case recovery slack is 33.311" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1677601289104 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1677601289104 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 33.311 0.000 C25M " " 33.311 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1677601289104 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1677601289104 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "removal 6.135 " "Worst-case removal slack is 6.135" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1677601289109 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1677601289109 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 6.135 0.000 C25M " " 6.135 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1677601289109 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1677601289109 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 19.734 " "Worst-case minimum pulse width slack is 19.734" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1677601289113 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1677601289113 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.734 0.000 C25M " " 19.734 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1677601289113 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 488.734 0.000 PHI0 " " 488.734 0.000 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1677601289113 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1677601289113 ""} +{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Timing Analyzer" 0 -1 1677601289175 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1677601289198 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1677601289201 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1 Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13081 " "Peak virtual memory: 13081 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1677601289276 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 28 11:21:29 2023 " "Processing ended: Tue Feb 28 11:21:29 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1677601289276 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1677601289276 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1677601289276 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1677601289276 ""} diff --git a/cpld/db/GR8RAM.sta.rdb b/cpld/db/GR8RAM.sta.rdb new file mode 100644 index 0000000..4e3f7be Binary files /dev/null and b/cpld/db/GR8RAM.sta.rdb differ diff --git a/cpld/db/GR8RAM.sta_cmp.5_slow.tdb b/cpld/db/GR8RAM.sta_cmp.5_slow.tdb new file mode 100644 index 0000000..a8f7d62 Binary files /dev/null and b/cpld/db/GR8RAM.sta_cmp.5_slow.tdb differ diff --git a/cpld/db/GR8RAM.tis_db_list.ddb b/cpld/db/GR8RAM.tis_db_list.ddb new file mode 100644 index 0000000..b9ea6cb Binary files /dev/null and b/cpld/db/GR8RAM.tis_db_list.ddb differ diff --git a/cpld/db/GR8RAM.vpr.ammdb b/cpld/db/GR8RAM.vpr.ammdb new file mode 100644 index 0000000..27436c4 Binary files /dev/null and b/cpld/db/GR8RAM.vpr.ammdb differ diff --git a/cpld/db/logic_util_heursitic.dat b/cpld/db/logic_util_heursitic.dat deleted file mode 100755 index a673eab..0000000 Binary files a/cpld/db/logic_util_heursitic.dat and /dev/null differ diff --git a/cpld/db/prev_cmp_GR8RAM.qmsg b/cpld/db/prev_cmp_GR8RAM.qmsg deleted file mode 100755 index a48d744..0000000 --- a/cpld/db/prev_cmp_GR8RAM.qmsg +++ /dev/null @@ -1,91 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1619049425619 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1619049425619 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 21 19:57:05 2021 " "Processing started: Wed Apr 21 19:57:05 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1619049425619 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1619049425619 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1619049425635 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1619049427276 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(110) " "Verilog HDL warning at GR8RAM.v(110): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 110 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1619049427432 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(286) " "Verilog HDL warning at GR8RAM.v(286): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 286 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1619049427432 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1619049427448 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1619049427448 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1619049427557 ""} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(42) " "Verilog HDL assignment warning at GR8RAM.v(42): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 42 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1619049427557 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(47) " "Verilog HDL assignment warning at GR8RAM.v(47): truncated value with size 32 to match size of target (14)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 47 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1619049427557 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(134) " "Verilog HDL assignment warning at GR8RAM.v(134): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 134 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1619049427573 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(142) " "Verilog HDL assignment warning at GR8RAM.v(142): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 142 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1619049427573 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(149) " "Verilog HDL assignment warning at GR8RAM.v(149): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 149 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1619049427589 "|GR8RAM"} -{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 -1 1619049429167 ""} -{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "nNMIout VCC " "Pin \"nNMIout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 563 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1619049429543 "|GR8RAM|nNMIout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nIRQout VCC " "Pin \"nIRQout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 566 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1619049429543 "|GR8RAM|nIRQout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nRDYout VCC " "Pin \"nRDYout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 565 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1619049429543 "|GR8RAM|nRDYout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nINHout VCC " "Pin \"nINHout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 564 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1619049429543 "|GR8RAM|nINHout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RWout VCC " "Pin \"RWout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 567 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1619049429543 "|GR8RAM|RWout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nDMAout VCC " "Pin \"nDMAout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 562 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1619049429543 "|GR8RAM|nDMAout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 561 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1619049429543 "|GR8RAM|RAdir"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1619049429543 ""} -{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1619049430027 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "337 " "Implemented 337 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "28 " "Implemented 28 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1619049430074 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1619049430074 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1619049430074 ""} { "Info" "ICUT_CUT_TM_LCELLS" "257 " "Implemented 257 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1619049430074 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1619049430074 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1619049430324 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 13 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 13 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "301 " "Peak virtual memory: 301 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1619049430496 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 21 19:57:10 2021 " "Processing ended: Wed Apr 21 19:57:10 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1619049430496 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1619049430496 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1619049430496 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1619049430496 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1619049433591 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 32-bit " "Running Quartus II 32-bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1619049433606 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 21 19:57:12 2021 " "Processing started: Wed Apr 21 19:57:12 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1619049433606 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1619049433606 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1619049433606 ""} -{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1619049433810 ""} -{ "Info" "0" "" "Project = GR8RAM" { } { } 0 0 "Project = GR8RAM" 0 0 "Fitter" 0 0 1619049433810 ""} -{ "Info" "0" "" "Revision = GR8RAM" { } { } 0 0 "Revision = GR8RAM" 0 0 "Fitter" 0 0 1619049433810 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1619049434576 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1619049434607 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1619049435513 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1619049435513 ""} -{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1619049435826 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1619049435873 ""} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1619049436217 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1619049436217 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1619049436217 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1619049436217 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1619049436217 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1619049436217 ""} -{ "Info" "ISTA_SDC_FOUND" "GR8RAM.sdc " "Reading SDC File: 'GR8RAM.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1619049436389 ""} -{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1619049436436 ""} -{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1619049436451 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1619049436451 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 40.000 C25M " " 40.000 C25M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1619049436451 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 978.000 PHI0 " " 978.000 PHI0" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1619049436451 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1619049436451 ""} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1619049436451 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1619049436451 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1619049436467 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1619049436514 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI0 Global clock " "Automatically promoted some destinations of signal \"PHI0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~0 " "Destination \"comb~0\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1619049436514 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI0r1 " "Destination \"PHI0r1\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1619049436514 ""} } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1619049436514 ""} -{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI0 " "Pin \"PHI0\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI0 } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "PHI0" } } } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 419 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1619049436514 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nRESr Global clock " "Automatically promoted some destinations of signal \"nRESr\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "IOROMEN " "Destination \"IOROMEN\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 94 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1619049436514 ""} } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 16 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1619049436514 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1619049436514 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1619049436529 ""} -{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1619049436592 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1619049436654 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1619049436670 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1619049436670 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1619049436670 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619049436701 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1619049436967 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619049437342 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1619049437373 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1619049438593 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619049438593 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1619049438686 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "34 " "Router estimated average interconnect usage is 34% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "34 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1619049439186 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1619049439186 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619049439702 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.56 " "Total time spent on timing analysis during the Fitter is 0.56 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1619049439718 ""} -{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619049439718 ""} -{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1619049439765 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1619049440124 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "383 " "Peak virtual memory: 383 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1619049440312 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 21 19:57:20 2021 " "Processing ended: Wed Apr 21 19:57:20 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1619049440312 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1619049440312 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1619049440312 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1619049440312 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1619049443282 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1619049443297 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 21 19:57:22 2021 " "Processing started: Wed Apr 21 19:57:22 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1619049443297 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1619049443297 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1619049443297 ""} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1619049444797 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1619049444985 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "293 " "Peak virtual memory: 293 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1619049446001 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 21 19:57:26 2021 " "Processing ended: Wed Apr 21 19:57:26 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1619049446001 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1619049446001 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1619049446001 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1619049446001 ""} -{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1619049446923 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1619049449251 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1619049449267 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 21 19:57:27 2021 " "Processing started: Wed Apr 21 19:57:27 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1619049449267 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1619049449267 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1619049449267 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1619049449455 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1619049450502 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1619049450705 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1619049450705 ""} -{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1619049450877 ""} -{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1619049451408 ""} -{ "Info" "ISTA_SDC_FOUND" "GR8RAM.sdc " "Reading SDC File: 'GR8RAM.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1619049451564 ""} -{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1619049451627 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup 12.419 " "Worst-case setup slack is 12.419" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451721 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451721 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 12.419 0.000 C25M " " 12.419 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451721 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1619049451721 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.393 " "Worst-case hold slack is 1.393" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451721 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451721 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.393 0.000 C25M " " 1.393 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451721 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1619049451721 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 33.300 " "Worst-case recovery slack is 33.300" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451736 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451736 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 33.300 0.000 C25M " " 33.300 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451736 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1619049451736 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "removal 6.146 " "Worst-case removal slack is 6.146" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451736 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451736 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 6.146 0.000 C25M " " 6.146 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451736 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1619049451736 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 19.734 " "Worst-case minimum pulse width slack is 19.734" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451752 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451752 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.734 0.000 C25M " " 19.734 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451752 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 488.734 0.000 PHI0 " " 488.734 0.000 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451752 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1619049451752 ""} -{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1619049451861 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1619049451924 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1619049451939 ""} -{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "278 " "Peak virtual memory: 278 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1619049452143 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 21 19:57:32 2021 " "Processing ended: Wed Apr 21 19:57:32 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1619049452143 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1619049452143 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1619049452143 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1619049452143 ""} -{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 15 s " "Quartus II Full Compilation was successful. 0 errors, 15 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1619049453283 ""} diff --git a/cpld/greybox_tmp/cbx_args.txt b/cpld/greybox_tmp/cbx_args.txt deleted file mode 100755 index 88ae65d..0000000 --- a/cpld/greybox_tmp/cbx_args.txt +++ /dev/null @@ -1,25 +0,0 @@ -ERASE_TIME=500000000 -INTENDED_DEVICE_FAMILY="MAX II" -LPM_FILE=UNUSED -LPM_HINT=UNUSED -LPM_TYPE=altufm_none -OSC_FREQUENCY=180000 -PORT_ARCLKENA=PORT_UNUSED -PORT_DRCLKENA=PORT_UNUSED -PROGRAM_TIME=1600000 -WIDTH_UFM_ADDRESS=9 -DEVICE_FAMILY="MAX II" -CBX_AUTO_BLACKBOX=ALL -arclk -ardin -arshft -busy -drclk -drdin -drdout -drshft -erase -osc -oscena -program -rtpbusy diff --git a/cpld/incremental_db/README b/cpld/incremental_db/README old mode 100755 new mode 100644 diff --git a/cpld/incremental_db/compiled_partitions/GR8RAM.db_info b/cpld/incremental_db/compiled_partitions/GR8RAM.db_info index e7990f0..842bd19 100644 --- a/cpld/incremental_db/compiled_partitions/GR8RAM.db_info +++ b/cpld/incremental_db/compiled_partitions/GR8RAM.db_info @@ -1,3 +1,3 @@ Quartus_Version = Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition Version_Index = 553882368 -Creation_Time = Tue Feb 28 11:10:33 2023 +Creation_Time = Tue Feb 28 11:21:15 2023 diff --git a/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt b/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt old mode 100755 new mode 100644 index c535fa4..10b8f14 Binary files a/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt and b/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt differ diff --git a/cpld/output_files/GR8RAM.asm.rpt b/cpld/output_files/GR8RAM.asm.rpt old mode 100755 new mode 100644 index 37daa67..7533478 --- a/cpld/output_files/GR8RAM.asm.rpt +++ b/cpld/output_files/GR8RAM.asm.rpt @@ -1,6 +1,6 @@ Assembler report for GR8RAM -Tue Sep 14 01:35:32 2021 -Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +Tue Feb 28 11:21:26 2023 +Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition --------------------- @@ -10,7 +10,7 @@ Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit 2. Assembler Summary 3. Assembler Settings 4. Assembler Generated Files - 5. Assembler Device Options: C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.pof + 5. Assembler Device Options: /Repos2/GR8RAM/cpld2/output_files/GR8RAM.pof 6. Assembler Messages @@ -18,26 +18,27 @@ Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit ---------------- ; Legal Notice ; ---------------- -Copyright (C) 1991-2013 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic +Copyright (C) 2022 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Tue Sep 14 01:35:32 2021 ; +; Assembler Status ; Successful - Tue Feb 28 11:21:26 2023 ; ; Revision Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ; ; Family ; MAX II ; @@ -45,69 +46,46 @@ applicable agreement for further details. +-----------------------+---------------------------------------+ -+---------------------------------------------------------------------------------------------------------+ -; Assembler Settings ; -+-----------------------------------------------------------------------------+-----------+---------------+ -; Option ; Setting ; Default Value ; -+-----------------------------------------------------------------------------+-----------+---------------+ -; Use smart compilation ; Off ; Off ; -; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; -; Enable compact report table ; Off ; Off ; -; Compression mode ; Off ; Off ; -; Clock source for configuration device ; Internal ; Internal ; -; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ; -; Divide clock frequency by ; 1 ; 1 ; -; Auto user code ; On ; On ; -; Security bit ; Off ; Off ; -; Use configuration device ; On ; On ; -; Configuration device ; Auto ; Auto ; -; Configuration device auto user code ; Off ; Off ; -; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ; -; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ; -; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ; -; Hexadecimal Output File start address ; 0 ; 0 ; -; Hexadecimal Output File count direction ; Up ; Up ; -; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ; -; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ; -; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ; -; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ; -; In-System Programming Default Clamp State ; Tri-state ; Tri-state ; -+-----------------------------------------------------------------------------+-----------+---------------+ ++----------------------------------+ +; Assembler Settings ; ++--------+---------+---------------+ +; Option ; Setting ; Default Value ; ++--------+---------+---------------+ -+-------------------------------------------------------------------+ -; Assembler Generated Files ; -+-------------------------------------------------------------------+ -; File Name ; -+-------------------------------------------------------------------+ -; C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.pof ; -+-------------------------------------------------------------------+ ++----------------------------------------------+ +; Assembler Generated Files ; ++----------------------------------------------+ +; File Name ; ++----------------------------------------------+ +; /Repos2/GR8RAM/cpld2/output_files/GR8RAM.pof ; ++----------------------------------------------+ -+---------------------------------------------------------------------------------------------+ -; Assembler Device Options: C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.pof ; -+----------------+----------------------------------------------------------------------------+ -; Option ; Setting ; -+----------------+----------------------------------------------------------------------------+ -; Device ; EPM240T100C5 ; -; JTAG usercode ; 0x00161CF0 ; -; Checksum ; 0x001620E8 ; -+----------------+----------------------------------------------------------------------------+ ++------------------------------------------------------------------------+ +; Assembler Device Options: /Repos2/GR8RAM/cpld2/output_files/GR8RAM.pof ; ++----------------+-------------------------------------------------------+ +; Option ; Setting ; ++----------------+-------------------------------------------------------+ +; JTAG usercode ; 0x00163AA4 ; +; Checksum ; 0x00163E9C ; ++----------------+-------------------------------------------------------+ +--------------------+ ; Assembler Messages ; +--------------------+ Info: ******************************************************************* -Info: Running Quartus II 64-Bit Assembler - Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - Info: Processing started: Tue Sep 14 01:35:31 2021 +Info: Running Quartus Prime Assembler + Info: Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition + Info: Processing started: Tue Feb 28 11:21:25 2023 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (115031): Writing out detailed assembly data for power analysis Info (115030): Assembler is generating device programming files -Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 381 megabytes - Info: Processing ended: Tue Sep 14 01:35:32 2021 +Info: Quartus Prime Assembler was successful. 0 errors, 1 warning + Info: Peak virtual memory: 13100 megabytes + Info: Processing ended: Tue Feb 28 11:21:26 2023 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 diff --git a/cpld/output_files/GR8RAM.cdf b/cpld/output_files/GR8RAM.cdf index c83d408..07b57a1 100644 --- a/cpld/output_files/GR8RAM.cdf +++ b/cpld/output_files/GR8RAM.cdf @@ -4,7 +4,7 @@ JedecChain; DefaultMfr(6E); P ActionCode(Cfg) - Device PartName(EPM240T100) Path("//Mac/iCloud/Repos2/GR8RAM/cpld/output_files/") File("GR8RAM.pof") MfrSpec(OpMask(1) SEC_Device(EPM240T100) Child_OpMask(2 3 3)); + Device PartName(EPM240T100) Path("//mac/iCloud/Repos2/GR8RAM/cpld2/output_files/") File("GR8RAM.pof") MfrSpec(OpMask(1) SEC_Device(EPM240T100) Child_OpMask(2 3 3)); ChainEnd; diff --git a/cpld/output_files/GR8RAM.done b/cpld/output_files/GR8RAM.done old mode 100755 new mode 100644 index 3f077ca..381b13b --- a/cpld/output_files/GR8RAM.done +++ b/cpld/output_files/GR8RAM.done @@ -1 +1 @@ -Tue Sep 14 01:35:34 2021 +Tue Feb 28 11:21:32 2023 diff --git a/cpld/output_files/GR8RAM.eda.rpt b/cpld/output_files/GR8RAM.eda.rpt new file mode 100644 index 0000000..9c146b0 --- /dev/null +++ b/cpld/output_files/GR8RAM.eda.rpt @@ -0,0 +1,94 @@ +EDA Netlist Writer report for GR8RAM +Tue Feb 28 11:21:31 2023 +Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. EDA Netlist Writer Summary + 3. Simulation Settings + 4. Simulation Generated Files + 5. EDA Netlist Writer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2022 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++-------------------------------------------------------------------+ +; EDA Netlist Writer Summary ; ++---------------------------+---------------------------------------+ +; EDA Netlist Writer Status ; Successful - Tue Feb 28 11:21:31 2023 ; +; Revision Name ; GR8RAM ; +; Top-level Entity Name ; GR8RAM ; +; Family ; MAX II ; +; Simulation Files Creation ; Successful ; ++---------------------------+---------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Simulation Settings ; ++---------------------------------------------------------------------------------------------------+-----------------------------+ +; Option ; Setting ; ++---------------------------------------------------------------------------------------------------+-----------------------------+ +; Tool Name ; Questa Intel FPGA (Verilog) ; +; Generate functional simulation netlist ; On ; +; Truncate long hierarchy paths ; Off ; +; Map illegal HDL characters ; Off ; +; Flatten buses into individual nodes ; Off ; +; Maintain hierarchy ; Off ; +; Bring out device-wide set/reset signals as ports ; Off ; +; Enable glitch filtering ; Off ; +; Do not write top level VHDL entity ; Off ; +; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ; +; Architecture name in VHDL output netlist ; structure ; +; Generate third-party EDA tool command script for RTL functional simulation ; Off ; +; Generate third-party EDA tool command script for gate-level simulation ; Off ; ++---------------------------------------------------------------------------------------------------+-----------------------------+ + + ++--------------------------------------------------+ +; Simulation Generated Files ; ++--------------------------------------------------+ +; Generated Files ; ++--------------------------------------------------+ +; /Repos2/GR8RAM/cpld2/simulation/questa/GR8RAM.vo ; ++--------------------------------------------------+ + + ++-----------------------------+ +; EDA Netlist Writer Messages ; ++-----------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime EDA Netlist Writer + Info: Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition + Info: Processing started: Tue Feb 28 11:21:30 2023 +Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (204019): Generated file GR8RAM.vo in folder "/Repos2/GR8RAM/cpld2/simulation/questa/" for EDA simulation tool +Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning + Info: Peak virtual memory: 13024 megabytes + Info: Processing ended: Tue Feb 28 11:21:31 2023 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:01 + + diff --git a/cpld/output_files/GR8RAM.fit.rpt b/cpld/output_files/GR8RAM.fit.rpt old mode 100755 new mode 100644 index 60461ed..95c0b85 --- a/cpld/output_files/GR8RAM.fit.rpt +++ b/cpld/output_files/GR8RAM.fit.rpt @@ -1,6 +1,6 @@ Fitter report for GR8RAM -Tue Sep 14 01:35:30 2021 -Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +Tue Feb 28 11:21:23 2023 +Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition --------------------- @@ -18,12 +18,12 @@ Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit 10. I/O Bank Usage 11. All Package Pins 12. Output Pin Default Load For Reported TCO - 13. Fitter Resource Utilization by Entity - 14. Delay Chain Summary - 15. Control Signals - 16. Global & Other Fast Signals - 17. Non-Global High Fan-Out Signals - 18. Other Routing Usage Summary + 13. I/O Assignment Warnings + 14. Fitter Resource Utilization by Entity + 15. Delay Chain Summary + 16. Control Signals + 17. Global & Other Fast Signals + 18. Routing Usage Summary 19. LAB Logic Elements 20. LAB-wide Signals 21. LAB Signals Sourced @@ -38,184 +38,196 @@ Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit ---------------- ; Legal Notice ; ---------------- -Copyright (C) 1991-2013 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic +Copyright (C) 2022 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. -+-----------------------------------------------------------------------------+ -; Fitter Summary ; -+---------------------------+-------------------------------------------------+ -; Fitter Status ; Successful - Tue Sep 14 01:35:30 2021 ; -; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; -; Revision Name ; GR8RAM ; -; Top-level Entity Name ; GR8RAM ; -; Family ; MAX II ; -; Device ; EPM240T100C5 ; -; Timing Models ; Final ; -; Total logic elements ; 234 / 240 ( 98 % ) ; -; Total pins ; 80 / 80 ( 100 % ) ; -; Total virtual pins ; 0 ; -; UFM blocks ; 0 / 1 ( 0 % ) ; -+---------------------------+-------------------------------------------------+ ++------------------------------------------------------------------------+ +; Fitter Summary ; ++-----------------------+------------------------------------------------+ +; Fitter Status ; Successful - Tue Feb 28 11:21:23 2023 ; +; Quartus Prime Version ; 22.1std.0 Build 915 10/25/2022 SC Lite Edition ; +; Revision Name ; GR8RAM ; +; Top-level Entity Name ; GR8RAM ; +; Family ; MAX II ; +; Device ; EPM240T100C5 ; +; Timing Models ; Final ; +; Total logic elements ; 233 / 240 ( 97 % ) ; +; Total pins ; 80 / 80 ( 100 % ) ; +; Total virtual pins ; 0 ; +; UFM blocks ; 0 / 1 ( 0 % ) ; ++-----------------------+------------------------------------------------+ -+----------------------------------------------------------------------------------------------------------------------------------------------+ -; Fitter Settings ; -+----------------------------------------------------------------------------+--------------------------------+--------------------------------+ -; Option ; Setting ; Default Value ; -+----------------------------------------------------------------------------+--------------------------------+--------------------------------+ -; Device ; EPM240T100C5 ; ; -; Minimum Core Junction Temperature ; 0 ; ; -; Maximum Core Junction Temperature ; 85 ; ; -; Placement Effort Multiplier ; 2.0 ; 1.0 ; -; Router Effort Multiplier ; 2.0 ; 1.0 ; -; Fit Attempts to Skip ; 0 ; 0.0 ; -; Device I/O Standard ; 3.3-V LVTTL ; ; -; Final Placement Optimizations ; Always ; Automatically ; -; Fitter Initial Placement Seed ; 235 ; 1 ; -; Fitter Effort ; Standard Fit ; Auto Fit ; -; Auto Register Duplication ; Off ; Auto ; -; Use smart compilation ; Off ; Off ; -; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; -; Enable compact report table ; Off ; Off ; -; Router Timing Optimization Level ; Normal ; Normal ; -; Always Enable Input Buffers ; Off ; Off ; -; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ; -; Optimize Multi-Corner Timing ; Off ; Off ; -; Guarantee I/O Paths Have Zero Hold Time at Fast Corner ; On ; On ; -; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; -; Optimize Timing ; Normal compilation ; Normal compilation ; -; Optimize Timing for ECOs ; Off ; Off ; -; Regenerate full fit report during ECO compiles ; Off ; Off ; -; Optimize IOC Register Placement for Timing ; Normal ; Normal ; -; Limit to One Fitting Attempt ; Off ; Off ; -; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; -; Slow Slew Rate ; Off ; Off ; -; PCI I/O ; Off ; Off ; -; Weak Pull-Up Resistor ; Off ; Off ; -; Enable Bus-Hold Circuitry ; Off ; Off ; -; Auto Delay Chains ; On ; On ; -; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ; -; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; -; Perform Register Duplication for Performance ; Off ; Off ; -; Perform Register Retiming for Performance ; Off ; Off ; -; Perform Asynchronous Signal Pipelining ; Off ; Off ; -; Physical Synthesis Effort Level ; Normal ; Normal ; -; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ; -; Auto Global Clock ; On ; On ; -; Auto Global Register Control Signals ; On ; On ; -; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; -+----------------------------------------------------------------------------+--------------------------------+--------------------------------+ ++--------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++--------------------------------------------------------------------+--------------------------------+--------------------------------+ +; Option ; Setting ; Default Value ; ++--------------------------------------------------------------------+--------------------------------+--------------------------------+ +; Device ; EPM240T100C5 ; ; +; Minimum Core Junction Temperature ; 0 ; ; +; Maximum Core Junction Temperature ; 85 ; ; +; Fit Attempts to Skip ; 0 ; 0.0 ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Router Effort Multiplier ; 1.0 ; 1.0 ; +; Always Enable Input Buffers ; Off ; Off ; +; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ; +; Optimize Multi-Corner Timing ; Off ; Off ; +; Guarantee I/O Paths Have Zero Hold Time at Fast Corner ; On ; On ; +; Power Optimization During Fitting ; Normal compilation ; Normal compilation ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; Normal ; Normal ; +; Limit to One Fitting Attempt ; Off ; Off ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; Periphery to Core Placement and Routing Optimization ; Off ; Off ; +; Slow Slew Rate ; Off ; Off ; +; PCI I/O ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Delay Chains ; On ; On ; +; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; +; Perform Register Duplication for Performance ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Physical Synthesis Effort Level ; Normal ; Normal ; +; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ; +; Auto Register Duplication ; Auto ; Auto ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; ++--------------------------------------------------------------------+--------------------------------+--------------------------------+ -Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. -+-------------------------------------+ -; Parallel Compilation ; -+----------------------------+--------+ -; Processors ; Number ; -+----------------------------+--------+ -; Number detected on machine ; 12 ; -; Maximum allowed ; 1 ; -+----------------------------+--------+ ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.02 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processor 2 ; 0.7% ; +; Processors 3-4 ; 0.5% ; ++----------------------------+-------------+ +--------------+ ; Pin-Out File ; +--------------+ -The pin-out file can be found in C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.pin. +The pin-out file can be found in /Repos2/GR8RAM/cpld2/output_files/GR8RAM.pin. -+------------------------------------------------------------------+ -; Fitter Resource Usage Summary ; -+---------------------------------------------+--------------------+ -; Resource ; Usage ; -+---------------------------------------------+--------------------+ -; Total logic elements ; 234 / 240 ( 98 % ) ; -; -- Combinational with no register ; 113 ; -; -- Register only ; 1 ; -; -- Combinational with a register ; 120 ; -; ; ; -; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 126 ; -; -- 3 input functions ; 41 ; -; -- 2 input functions ; 65 ; -; -- 1 input functions ; 0 ; -; -- 0 input functions ; 1 ; -; ; ; -; Logic elements by mode ; ; -; -- normal mode ; 201 ; -; -- arithmetic mode ; 33 ; -; -- qfbk mode ; 18 ; -; -- register cascade mode ; 0 ; -; -- synchronous clear/load mode ; 67 ; -; -- asynchronous clear/load mode ; 29 ; -; ; ; -; Total registers ; 121 / 240 ( 50 % ) ; -; Total LABs ; 24 / 24 ( 100 % ) ; -; Logic elements in carry chains ; 37 ; -; Virtual pins ; 0 ; -; I/O pins ; 80 / 80 ( 100 % ) ; -; -- Clock pins ; 4 / 4 ( 100 % ) ; -; ; ; -; Global signals ; 3 ; -; UFM blocks ; 0 / 1 ( 0 % ) ; -; Global clocks ; 3 / 4 ( 75 % ) ; -; JTAGs ; 0 / 1 ( 0 % ) ; -; Average interconnect usage (total/H/V) ; 40% / 44% / 37% ; -; Peak interconnect usage (total/H/V) ; 40% / 44% / 37% ; -; Maximum fan-out ; 107 ; -; Highest non-global fan-out ; 47 ; -; Total fan-out ; 1091 ; -; Average fan-out ; 3.47 ; -+---------------------------------------------+--------------------+ ++---------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++---------------------------------------------+-----------------------+ +; Resource ; Usage ; ++---------------------------------------------+-----------------------+ +; Total logic elements ; 233 / 240 ( 97 % ) ; +; -- Combinational with no register ; 109 ; +; -- Register only ; 6 ; +; -- Combinational with a register ; 118 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 124 ; +; -- 3 input functions ; 30 ; +; -- 2 input functions ; 71 ; +; -- 1 input functions ; 0 ; +; -- 0 input functions ; 2 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 200 ; +; -- arithmetic mode ; 33 ; +; -- qfbk mode ; 18 ; +; -- register cascade mode ; 0 ; +; -- synchronous clear/load mode ; 68 ; +; -- asynchronous clear/load mode ; 29 ; +; ; ; +; Total registers ; 124 / 240 ( 52 % ) ; +; Total LABs ; 24 / 24 ( 100 % ) ; +; Logic elements in carry chains ; 37 ; +; Virtual pins ; 0 ; +; I/O pins ; 80 / 80 ( 100 % ) ; +; -- Clock pins ; 4 / 4 ( 100 % ) ; +; ; ; +; UFM blocks ; 0 / 1 ( 0 % ) ; +; ; ; +; -- Total Fixed Point DSP Blocks ; 0 ; +; -- Total Floating Point DSP Blocks ; 0 ; +; ; ; +; Global signals ; 3 ; +; -- Global clocks ; 3 / 4 ( 75 % ) ; +; JTAGs ; 0 / 1 ( 0 % ) ; +; Average interconnect usage (total/H/V) ; 34.1% / 35.6% / 32.6% ; +; Peak interconnect usage (total/H/V) ; 34.1% / 35.6% / 32.6% ; +; Maximum fan-out ; 110 ; +; Highest non-global fan-out ; 53 ; +; Total fan-out ; 1071 ; +; Average fan-out ; 3.42 ; ++---------------------------------------------+-----------------------+ -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Input Pins ; -+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+----------------------------+----------------------+ -; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Location assigned by ; -+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+----------------------------+----------------------+ -; C25M ; 64 ; 2 ; 8 ; 3 ; 4 ; 107 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; DMAin ; 48 ; 1 ; 6 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; INTin ; 49 ; 1 ; 7 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; MISO ; 16 ; 1 ; 1 ; 2 ; 2 ; 1 ; 0 ; no ; no ; yes ; Off ; 3.3-V LVTTL ; User ; -; PHI0 ; 41 ; 1 ; 5 ; 0 ; 1 ; 16 ; 0 ; yes ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; -; RA[0] ; 100 ; 2 ; 2 ; 5 ; 2 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; RA[10] ; 14 ; 1 ; 1 ; 2 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; RA[11] ; 34 ; 1 ; 3 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; RA[12] ; 35 ; 1 ; 3 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; RA[13] ; 36 ; 1 ; 4 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; RA[14] ; 37 ; 1 ; 4 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; RA[15] ; 38 ; 1 ; 4 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; RA[1] ; 98 ; 2 ; 2 ; 5 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; RA[2] ; 97 ; 2 ; 3 ; 5 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; RA[3] ; 4 ; 1 ; 1 ; 4 ; 2 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; RA[4] ; 1 ; 2 ; 2 ; 5 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; RA[5] ; 2 ; 1 ; 1 ; 4 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; RA[6] ; 3 ; 1 ; 1 ; 4 ; 1 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; RA[7] ; 6 ; 1 ; 1 ; 3 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; RA[8] ; 7 ; 1 ; 1 ; 3 ; 1 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; RA[9] ; 8 ; 1 ; 1 ; 3 ; 2 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; SetFW[0] ; 96 ; 2 ; 3 ; 5 ; 2 ; 1 ; 0 ; no ; no ; no ; On ; 3.3V Schmitt Trigger Input ; User ; -; SetFW[1] ; 95 ; 2 ; 3 ; 5 ; 1 ; 1 ; 0 ; no ; no ; no ; On ; 3.3V Schmitt Trigger Input ; User ; -; nDEVSEL ; 40 ; 1 ; 5 ; 0 ; 2 ; 4 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; -; nIOSEL ; 39 ; 1 ; 5 ; 0 ; 3 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; -; nIOSTRB ; 42 ; 1 ; 5 ; 0 ; 0 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; -; nRES ; 44 ; 1 ; 6 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; -; nWE ; 43 ; 1 ; 6 ; 0 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; -+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+----------------------------+----------------------+ ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+----------------------------+----------------------+----------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Location assigned by ; Slow Slew Rate ; ++----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+----------------------------+----------------------+----------------+ +; C25M ; 64 ; 2 ; 8 ; 3 ; 4 ; 110 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; +; DMAin ; 48 ; 1 ; 6 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; +; INTin ; 49 ; 1 ; 7 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; +; MISO ; 16 ; 1 ; 1 ; 2 ; 2 ; 1 ; 0 ; no ; no ; yes ; Off ; 3.3-V LVTTL ; User ; no ; +; PHI0 ; 41 ; 1 ; 5 ; 0 ; 1 ; 16 ; 0 ; yes ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; no ; +; RA[0] ; 100 ; 2 ; 2 ; 5 ; 2 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; +; RA[10] ; 14 ; 1 ; 1 ; 2 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; +; RA[11] ; 34 ; 1 ; 3 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; +; RA[12] ; 35 ; 1 ; 3 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; +; RA[13] ; 36 ; 1 ; 4 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; +; RA[14] ; 37 ; 1 ; 4 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; +; RA[15] ; 38 ; 1 ; 4 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; +; RA[1] ; 98 ; 2 ; 2 ; 5 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; +; RA[2] ; 97 ; 2 ; 3 ; 5 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; +; RA[3] ; 4 ; 1 ; 1 ; 4 ; 2 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; +; RA[4] ; 1 ; 2 ; 2 ; 5 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; no ; +; RA[5] ; 2 ; 1 ; 1 ; 4 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; +; RA[6] ; 3 ; 1 ; 1 ; 4 ; 1 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; +; RA[7] ; 6 ; 1 ; 1 ; 3 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; +; RA[8] ; 7 ; 1 ; 1 ; 3 ; 1 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; +; RA[9] ; 8 ; 1 ; 1 ; 3 ; 2 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; +; SetFW[0] ; 96 ; 2 ; 3 ; 5 ; 2 ; 1 ; 0 ; no ; no ; no ; On ; 3.3V Schmitt Trigger Input ; User ; no ; +; SetFW[1] ; 95 ; 2 ; 3 ; 5 ; 1 ; 1 ; 0 ; no ; no ; no ; On ; 3.3V Schmitt Trigger Input ; User ; no ; +; nDEVSEL ; 40 ; 1 ; 5 ; 0 ; 2 ; 4 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; no ; +; nIOSEL ; 39 ; 1 ; 5 ; 0 ; 3 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; no ; +; nIOSTRB ; 42 ; 1 ; 5 ; 0 ; 0 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; no ; +; nRES ; 44 ; 1 ; 6 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; no ; +; nWE ; 43 ; 1 ; 6 ; 0 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; no ; ++----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+----------------------------+----------------------+----------------+ +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ @@ -232,31 +244,31 @@ The pin-out file can be found in C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/outpu ; RCKE ; 66 ; 2 ; 8 ; 3 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; ; RDdir ; 17 ; 1 ; 1 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; ; RWout ; 33 ; 1 ; 3 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; -; SA[0] ; 75 ; 2 ; 7 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; yes ; User ; 10 pF ; - ; - ; +; SA[0] ; 75 ; 2 ; 7 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; ; SA[10] ; 73 ; 2 ; 8 ; 4 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; -; SA[11] ; 70 ; 2 ; 8 ; 4 ; 4 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; -; SA[12] ; 68 ; 2 ; 8 ; 3 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; +; SA[11] ; 70 ; 2 ; 8 ; 4 ; 4 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; yes ; User ; 10 pF ; - ; - ; +; SA[12] ; 68 ; 2 ; 8 ; 3 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; yes ; User ; 10 pF ; - ; - ; ; SA[1] ; 81 ; 2 ; 6 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; ; SA[2] ; 82 ; 2 ; 6 ; 5 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; ; SA[3] ; 84 ; 2 ; 6 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; ; SA[4] ; 76 ; 2 ; 7 ; 5 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; -; SA[5] ; 83 ; 2 ; 6 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; +; SA[5] ; 83 ; 2 ; 6 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; yes ; User ; 10 pF ; - ; - ; ; SA[6] ; 77 ; 2 ; 7 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; ; SA[7] ; 78 ; 2 ; 7 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; ; SA[8] ; 74 ; 2 ; 8 ; 4 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; ; SA[9] ; 72 ; 2 ; 8 ; 4 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; ; SBA[0] ; 69 ; 2 ; 8 ; 3 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; ; SBA[1] ; 71 ; 2 ; 8 ; 4 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; -; nCAS ; 61 ; 2 ; 8 ; 2 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; +; nCAS ; 61 ; 2 ; 8 ; 2 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; yes ; User ; 10 pF ; - ; - ; ; nDMAout ; 21 ; 1 ; 1 ; 1 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; -; nFCS ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; yes ; no ; no ; yes ; no ; On ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; +; nFCS ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; yes ; no ; no ; yes ; no ; On ; 3.3-V LVTTL ; 8mA ; yes ; User ; 10 pF ; - ; - ; ; nINHout ; 27 ; 1 ; 2 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; ; nIRQout ; 29 ; 1 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; ; nNMIout ; 26 ; 1 ; 2 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; ; nRAS ; 62 ; 2 ; 8 ; 2 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; yes ; User ; 10 pF ; - ; - ; ; nRCS ; 67 ; 2 ; 8 ; 3 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; ; nRDYout ; 28 ; 1 ; 2 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; -; nRESout ; 30 ; 1 ; 3 ; 0 ; 3 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; +; nRESout ; 30 ; 1 ; 3 ; 0 ; 3 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; yes ; User ; 10 pF ; - ; - ; ; nSWE ; 58 ; 2 ; 8 ; 2 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; +---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ @@ -275,14 +287,14 @@ The pin-out file can be found in C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/outpu ; RD[5] ; 91 ; 2 ; 4 ; 5 ; 2 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ; ; RD[6] ; 92 ; 2 ; 3 ; 5 ; 0 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ; ; RD[7] ; 99 ; 2 ; 2 ; 5 ; 1 ; 6 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ; -; SD[0] ; 50 ; 1 ; 7 ; 0 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; +; SD[0] ; 50 ; 1 ; 7 ; 0 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; SDOE ; - ; ; SD[1] ; 47 ; 1 ; 6 ; 0 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; -; SD[2] ; 56 ; 2 ; 8 ; 1 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; -; SD[3] ; 55 ; 2 ; 8 ; 1 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; -; SD[4] ; 51 ; 1 ; 7 ; 0 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; -; SD[5] ; 52 ; 2 ; 8 ; 1 ; 4 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; -; SD[6] ; 53 ; 2 ; 8 ; 1 ; 3 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; -; SD[7] ; 54 ; 2 ; 8 ; 1 ; 2 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; +; SD[2] ; 56 ; 2 ; 8 ; 1 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; SDOE ; - ; +; SD[3] ; 55 ; 2 ; 8 ; 1 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; SDOE ; - ; +; SD[4] ; 51 ; 1 ; 7 ; 0 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; SDOE ; - ; +; SD[5] ; 52 ; 2 ; 8 ; 1 ; 4 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; SDOE ; - ; +; SD[6] ; 53 ; 2 ; 8 ; 1 ; 3 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; SDOE ; - ; +; SD[7] ; 54 ; 2 ; 8 ; 1 ; 2 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; SDOE ; - ; +-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ @@ -301,7 +313,7 @@ The pin-out file can be found in C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/outpu +----------+------------+----------+----------------+--------+----------------------------+-----------+------------+-----------------+----------+--------------+ ; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; +----------+------------+----------+----------------+--------+----------------------------+-----------+------------+-----------------+----------+--------------+ -; 1 ; 83 ; 2 ; RA[4] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 1 ; 83 ; 2 ; RA[4] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; ; 2 ; 0 ; 1 ; RA[5] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; ; 3 ; 1 ; 1 ; RA[6] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; ; 4 ; 2 ; 1 ; RA[3] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; @@ -421,13 +433,22 @@ Note: Pin directions (input, output or bidir) are based on device operating in u Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables. -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Fitter Resource Utilization by Entity ; -+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+ -; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ; -+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+ -; |GR8RAM ; 234 (234) ; 121 ; 0 ; 80 ; 0 ; 113 (113) ; 1 (1) ; 120 (120) ; 37 (37) ; 22 (22) ; |GR8RAM ; work ; -+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+ ++----------------------------------------+ +; I/O Assignment Warnings ; ++----------+-----------------------------+ +; Pin Name ; Reason ; ++----------+-----------------------------+ +; RA[4] ; Missing location assignment ; ++----------+-----------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ; ++----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+ +; |GR8RAM ; 233 (233) ; 124 ; 0 ; 80 ; 0 ; 109 (109) ; 6 (6) ; 118 (118) ; 37 (37) ; 18 (18) ; |GR8RAM ; GR8RAM ; work ; ++----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. @@ -436,34 +457,6 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +----------+----------+---------------+ ; Name ; Pin Type ; Pad to Core 0 ; +----------+----------+---------------+ -; INTin ; Input ; (1) ; -; DMAin ; Input ; (1) ; -; PHI0 ; Input ; (0) ; -; nWE ; Input ; (1) ; -; RA[0] ; Input ; (1) ; -; RA[1] ; Input ; (1) ; -; RA[2] ; Input ; (1) ; -; RA[3] ; Input ; (1) ; -; RA[4] ; Input ; (1) ; -; RA[5] ; Input ; (1) ; -; RA[6] ; Input ; (1) ; -; RA[7] ; Input ; (1) ; -; RA[8] ; Input ; (1) ; -; RA[9] ; Input ; (1) ; -; RA[10] ; Input ; (1) ; -; nIOSTRB ; Input ; (1) ; -; nIOSEL ; Input ; (1) ; -; nDEVSEL ; Input ; (1) ; -; C25M ; Input ; (0) ; -; RA[11] ; Input ; (1) ; -; RA[14] ; Input ; (1) ; -; RA[15] ; Input ; (1) ; -; RA[12] ; Input ; (1) ; -; RA[13] ; Input ; (1) ; -; SetFW[1] ; Input ; (1) ; -; SetFW[0] ; Input ; (1) ; -; nRES ; Input ; (1) ; -; MISO ; Input ; (1) ; ; nRESout ; Output ; -- ; ; INTout ; Output ; -- ; ; DMAout ; Output ; -- ; @@ -516,6 +509,34 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; SD[6] ; Bidir ; (1) ; ; SD[7] ; Bidir ; (1) ; ; MOSI ; Bidir ; (1) ; +; INTin ; Input ; (1) ; +; DMAin ; Input ; (1) ; +; PHI0 ; Input ; (0) ; +; nWE ; Input ; (1) ; +; RA[0] ; Input ; (1) ; +; RA[1] ; Input ; (1) ; +; RA[2] ; Input ; (1) ; +; RA[3] ; Input ; (1) ; +; RA[4] ; Input ; (1) ; +; RA[5] ; Input ; (1) ; +; RA[6] ; Input ; (1) ; +; RA[7] ; Input ; (1) ; +; RA[8] ; Input ; (1) ; +; RA[9] ; Input ; (1) ; +; RA[10] ; Input ; (1) ; +; nIOSTRB ; Input ; (1) ; +; nIOSEL ; Input ; (1) ; +; nDEVSEL ; Input ; (1) ; +; C25M ; Input ; (0) ; +; RA[11] ; Input ; (1) ; +; RA[14] ; Input ; (1) ; +; RA[15] ; Input ; (1) ; +; RA[12] ; Input ; (1) ; +; RA[13] ; Input ; (1) ; +; SetFW[1] ; Input ; (1) ; +; SetFW[0] ; Input ; (1) ; +; nRES ; Input ; (1) ; +; MISO ; Input ; (1) ; +----------+----------+---------------+ @@ -524,21 +545,22 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +-------------+-------------+---------+---------------------------------------+--------+----------------------+------------------+ ; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; +-------------+-------------+---------+---------------------------------------+--------+----------------------+------------------+ -; C25M ; PIN_64 ; 107 ; Clock ; yes ; Global Clock ; GCLK3 ; -; Equal20~0 ; LC_X7_Y2_N8 ; 8 ; Clock enable ; no ; -- ; -- ; -; Equal2~1 ; LC_X3_Y2_N5 ; 19 ; Clock enable ; no ; -- ; -- ; -; FCKOE ; LC_X2_Y2_N8 ; 2 ; Output enable ; no ; -- ; -- ; -; MOSIOE ; LC_X2_Y2_N4 ; 1 ; Output enable ; no ; -- ; -- ; +; C25M ; PIN_64 ; 110 ; Clock ; yes ; Global Clock ; GCLK3 ; +; Equal20~0 ; LC_X2_Y4_N5 ; 8 ; Clock enable ; no ; -- ; -- ; +; Equal2~1 ; LC_X2_Y1_N5 ; 16 ; Clock enable ; no ; -- ; -- ; +; FCKOE ; LC_X3_Y1_N1 ; 2 ; Output enable ; no ; -- ; -- ; +; IS~19 ; LC_X2_Y2_N7 ; 5 ; Clock enable ; no ; -- ; -- ; +; MOSIOE ; LC_X2_Y2_N8 ; 1 ; Output enable ; no ; -- ; -- ; ; PHI0 ; PIN_41 ; 16 ; Clock ; yes ; Global Clock ; GCLK2 ; -; PS[0] ; LC_X3_Y2_N8 ; 46 ; Clock enable, Sync. clear, Sync. load ; no ; -- ; -- ; -; PS[2] ; LC_X3_Y2_N9 ; 27 ; Sync. clear, Sync. load ; no ; -- ; -- ; -; SDOE ; LC_X4_Y2_N1 ; 8 ; Output enable ; no ; -- ; -- ; -; SetFWLoaded ; LC_X7_Y3_N6 ; 2 ; Clock enable ; no ; -- ; -- ; -; always9~2 ; LC_X4_Y4_N9 ; 8 ; Sync. load ; no ; -- ; -- ; -; always9~3 ; LC_X4_Y4_N8 ; 9 ; Sync. load ; no ; -- ; -- ; -; always9~4 ; LC_X5_Y4_N8 ; 9 ; Sync. load ; no ; -- ; -- ; -; comb~2 ; LC_X3_Y3_N9 ; 9 ; Output enable ; no ; -- ; -- ; -; nRESr ; LC_X7_Y3_N2 ; 30 ; Async. clear, Sync. clear ; yes ; Global Clock ; GCLK1 ; +; PS[0] ; LC_X6_Y1_N1 ; 52 ; Clock enable, Sync. clear, Sync. load ; no ; -- ; -- ; +; PS[2] ; LC_X2_Y1_N2 ; 27 ; Sync. clear, Sync. load ; no ; -- ; -- ; +; SDOE ; LC_X5_Y1_N4 ; 8 ; Output enable ; no ; -- ; -- ; +; SetFWLoaded ; LC_X4_Y2_N8 ; 2 ; Clock enable ; no ; -- ; -- ; +; always9~2 ; LC_X7_Y3_N6 ; 8 ; Sync. load ; no ; -- ; -- ; +; always9~3 ; LC_X7_Y3_N7 ; 9 ; Sync. load ; no ; -- ; -- ; +; always9~4 ; LC_X6_Y3_N9 ; 9 ; Sync. load ; no ; -- ; -- ; +; comb~2 ; LC_X4_Y1_N8 ; 9 ; Output enable ; no ; -- ; -- ; +; nRESr ; LC_X3_Y1_N7 ; 30 ; Async. clear, Sync. clear ; yes ; Global Clock ; GCLK1 ; +-------------+-------------+---------+---------------------------------------+--------+----------------------+------------------+ @@ -547,397 +569,31 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +-------+-------------+---------+----------------------+------------------+ ; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; +-------+-------------+---------+----------------------+------------------+ -; C25M ; PIN_64 ; 107 ; Global Clock ; GCLK3 ; +; C25M ; PIN_64 ; 110 ; Global Clock ; GCLK3 ; ; PHI0 ; PIN_41 ; 16 ; Global Clock ; GCLK2 ; -; nRESr ; LC_X7_Y3_N2 ; 30 ; Global Clock ; GCLK1 ; +; nRESr ; LC_X3_Y1_N7 ; 30 ; Global Clock ; GCLK1 ; +-------+-------------+---------+----------------------+------------------+ -+---------------------------------+ -; Non-Global High Fan-Out Signals ; -+---------------------+-----------+ -; Name ; Fan-Out ; -+---------------------+-----------+ -; PS[0] ; 47 ; -; PS[1] ; 33 ; -; PS[3] ; 29 ; -; PS[2] ; 27 ; -; IS.state_bit_0 ; 20 ; -; Equal2~1 ; 19 ; -; IS.state_bit_1 ; 17 ; -; IS.110~0 ; 16 ; -; RAMSpecSEL~0 ; 16 ; -; LS[0] ; 13 ; -; RDD[1]~23 ; 9 ; -; always9~4 ; 9 ; -; always9~3 ; 9 ; -; comb~2 ; 9 ; -; RDD[1]~22 ; 8 ; -; Equal20~0 ; 8 ; -; SDOE ; 8 ; -; always9~2 ; 8 ; -; IS.state_bit_2 ; 8 ; -; LS[2] ; 8 ; -; RAr[0] ; 8 ; -; SA[1]~6 ; 7 ; -; SetFWr[1] ; 7 ; -; RAr[1] ; 7 ; -; RD[7]~7 ; 6 ; -; SA[3]~9 ; 6 ; -; SA[3]~8 ; 6 ; -; SA[3]~7 ; 6 ; -; LS[1] ; 6 ; -; Equal19~0 ; 6 ; -; RD[0]~0 ; 5 ; -; RDD[4]~12 ; 5 ; -; Addr[0] ; 5 ; -; LS[6]~17 ; 5 ; -; SA[1]~5 ; 5 ; -; LS[1]~3 ; 5 ; -; Mux14~2 ; 5 ; -; Addr[23] ; 5 ; -; always9~0 ; 5 ; -; RAMRegSpecSEL~0 ; 5 ; -; RD[6]~6 ; 4 ; -; RD[5]~5 ; 4 ; -; RD[4]~4 ; 4 ; -; RD[3]~3 ; 4 ; -; RD[2]~2 ; 4 ; -; RD[1]~1 ; 4 ; -; nDEVSEL ; 4 ; -; RDD[4]~13 ; 4 ; -; always9~1 ; 4 ; -; LS[13] ; 4 ; -; Equal3~2 ; 4 ; -; nRCS~1 ; 4 ; -; Addr[9] ; 4 ; -; Addr[8] ; 4 ; -; Addr[7] ; 4 ; -; Addr[6] ; 4 ; -; Addr[15] ; 4 ; -; Addr[5] ; 4 ; -; LS[5] ; 4 ; -; Addr[14] ; 4 ; -; Addr[4] ; 4 ; -; LS[4] ; 4 ; -; Addr[13] ; 4 ; -; Addr[3] ; 4 ; -; RAr[3] ; 4 ; -; Addr[12] ; 4 ; -; Addr[2] ; 4 ; -; Addr[11] ; 4 ; -; Addr[1] ; 4 ; -; Addr[10] ; 4 ; -; RAr[2] ; 4 ; -; nIOSEL ; 3 ; -; nIOSTRB ; 3 ; -; SA[1]~15 ; 3 ; -; WRD[5] ; 3 ; -; WRD[4] ; 3 ; -; WRD[3] ; 3 ; -; WRD[2] ; 3 ; -; WRD[1] ; 3 ; -; WRD[0] ; 3 ; -; Equal4~0 ; 3 ; -; Equal5~0 ; 3 ; -; Equal3~3 ; 3 ; -; IS.111~0 ; 3 ; -; nWEr ; 3 ; -; Addr[22] ; 3 ; -; Addr[21] ; 3 ; -; Addr[20]~41 ; 3 ; -; Addr[20] ; 3 ; -; SA~10 ; 3 ; -; Equal1~0 ; 3 ; -; Addr[19] ; 3 ; -; LS[9] ; 3 ; -; Addr[18] ; 3 ; -; LS[8] ; 3 ; -; Addr[17] ; 3 ; -; LS[7] ; 3 ; -; Addr[16] ; 3 ; -; LS[6] ; 3 ; -; Addr[4]~17 ; 3 ; -; LS[3] ; 3 ; -; LS[12] ; 3 ; -; Addr[12]~11 ; 3 ; -; LS[11] ; 3 ; -; SA[1]~3 ; 3 ; -; LS[10] ; 3 ; -; SA[1]~2 ; 3 ; -; IOROMEN ; 3 ; -; RA[10] ; 2 ; -; RA[9] ; 2 ; -; RA[8] ; 2 ; -; RA[7] ; 2 ; -; RA[6] ; 2 ; -; RA[5] ; 2 ; -; RA[4] ; 2 ; -; RA[3] ; 2 ; -; RA[2] ; 2 ; -; RA[1] ; 2 ; -; RA[0] ; 2 ; -; nWE ; 2 ; -; WRD[7] ; 2 ; -; WRD[6] ; 2 ; -; AddrIncL ; 2 ; -; AddrIncM ; 2 ; -; SetFWLoaded ; 2 ; -; IS.state_bit_1~3 ; 2 ; -; IS.state_bit_1~0 ; 2 ; -; Equal5~1 ; 2 ; -; FCKOE ; 2 ; -; PS~0 ; 2 ; -; Equal1~1 ; 2 ; -; DQMH~0 ; 2 ; -; Mux12~1 ; 2 ; -; nRCS~5 ; 2 ; -; nRCS~4 ; 2 ; -; nRCS~2 ; 2 ; -; RAr[9] ; 2 ; -; Bank ; 2 ; -; RAr[11] ; 2 ; -; LS[11]~5 ; 2 ; -; SA[1]~4 ; 2 ; -; RAr[10] ; 2 ; -; nRESf[2] ; 2 ; -; nRESf[1] ; 2 ; -; nRESf[0] ; 2 ; -; RAMRegSpecSEL ; 2 ; -; CXXXr ; 2 ; -; REGEN ; 2 ; -; RAr[8] ; 2 ; -; Equal9~0 ; 2 ; -; RAr[7] ; 2 ; -; always8~0 ; 2 ; -; nRESout~reg0 ; 2 ; -; MOSI~0 ; 1 ; -; SD[7]~7 ; 1 ; -; SD[6]~6 ; 1 ; -; SD[5]~5 ; 1 ; -; SD[4]~4 ; 1 ; -; SD[3]~3 ; 1 ; -; SD[2]~2 ; 1 ; -; SD[1]~1 ; 1 ; -; SD[0]~0 ; 1 ; -; MISO ; 1 ; -; nRES ; 1 ; -; SetFW[0] ; 1 ; -; SetFW[1] ; 1 ; -; RA[13] ; 1 ; -; RA[12] ; 1 ; -; RA[15] ; 1 ; -; RA[14] ; 1 ; -; RA[11] ; 1 ; -; DMAin ; 1 ; -; INTin ; 1 ; -; Mux2~3 ; 1 ; -; SetFWr[0] ; 1 ; -; Mux2~2 ; 1 ; -; Mux2~1 ; 1 ; -; Mux2~0 ; 1 ; -; SA[1]~14 ; 1 ; -; RDD~20 ; 1 ; -; RDD~18 ; 1 ; -; RDD~16 ; 1 ; -; RDD~14 ; 1 ; -; RDD~10 ; 1 ; -; RDD~8 ; 1 ; -; RDD~6 ; 1 ; -; RDD~4 ; 1 ; -; AddrIncM~2 ; 1 ; -; AddrIncM~1 ; 1 ; -; AddrIncM~0 ; 1 ; -; AddrIncH~2 ; 1 ; -; AddrIncH~1 ; 1 ; -; AddrIncH~0 ; 1 ; -; MOSIout ; 1 ; -; RDD[7] ; 1 ; -; RDD[6] ; 1 ; -; RDD[5] ; 1 ; -; RDD[4] ; 1 ; -; RDD[3] ; 1 ; -; RDD[2] ; 1 ; -; RDD[1] ; 1 ; -; RDD[0] ; 1 ; -; MOSIOE ; 1 ; -; IS.101~0 ; 1 ; -; IS.state_bit_2~1 ; 1 ; -; IS.state_bit_2~0 ; 1 ; -; Equal3~4 ; 1 ; -; AddrIncH ; 1 ; -; IS.state_bit_1~2 ; 1 ; -; IS.state_bit_1~1 ; 1 ; -; IS.state_bit_0~5 ; 1 ; -; IS.state_bit_0~4 ; 1 ; -; Equal6~0 ; 1 ; -; Equal3~1 ; 1 ; -; Equal3~0 ; 1 ; -; FCKout ; 1 ; -; FCS ; 1 ; -; Equal2~0 ; 1 ; -; Mux11~3 ; 1 ; -; Mux11~2 ; 1 ; -; Mux11~1 ; 1 ; -; PHI0r1 ; 1 ; -; Mux11~0 ; 1 ; -; Selector2~0 ; 1 ; -; Selector1~0 ; 1 ; -; Addr[0]~47COUT1_92 ; 1 ; -; Addr[0]~47 ; 1 ; -; Selector0~0 ; 1 ; -; Mux12~2 ; 1 ; -; nRCS~3 ; 1 ; -; Mux12~0 ; 1 ; -; IS.000~0 ; 1 ; -; nRCS~0 ; 1 ; -; Addr[22]~45COUT1_78 ; 1 ; -; Addr[22]~45 ; 1 ; -; Addr[21]~43COUT1_76 ; 1 ; -; Addr[21]~43 ; 1 ; -; Mux15~1 ; 1 ; -; Mux15~0 ; 1 ; -; Addr[19]~39COUT1_74 ; 1 ; -; Addr[19]~39 ; 1 ; -; Mux16~2 ; 1 ; -; Addr[9]~37COUT1_82 ; 1 ; -; Addr[9]~37 ; 1 ; -; LS[9]~23COUT1_50 ; 1 ; -; LS[9]~23 ; 1 ; -; Mux16~1 ; 1 ; -; Mux16~0 ; 1 ; -; Addr[18]~35COUT1_72 ; 1 ; -; Addr[18]~35 ; 1 ; -; Mux17~2 ; 1 ; -; Addr[8]~33COUT1_80 ; 1 ; -; Addr[8]~33 ; 1 ; -; LS[8]~21COUT1_48 ; 1 ; -; LS[8]~21 ; 1 ; -; Mux17~1 ; 1 ; -; Mux17~0 ; 1 ; -; Addr[17]~31COUT1_70 ; 1 ; -; Addr[17]~31 ; 1 ; -; Mux18~2 ; 1 ; -; LS[7]~19COUT1_46 ; 1 ; -; LS[7]~19 ; 1 ; -; Mux18~1 ; 1 ; -; Mux18~0 ; 1 ; -; Addr[16]~27COUT1_68 ; 1 ; -; Addr[16]~27 ; 1 ; -; Mux19~3 ; 1 ; -; Mux19~2 ; 1 ; -; Addr[6]~25COUT1_102 ; 1 ; -; Addr[6]~25 ; 1 ; -; RAr[6] ; 1 ; -; Mux19~1 ; 1 ; -; Mux19~0 ; 1 ; -; Mux20~2 ; 1 ; -; Addr[5]~21COUT1_100 ; 1 ; -; Addr[5]~21 ; 1 ; -; LS[5]~15COUT1_44 ; 1 ; -; LS[5]~15 ; 1 ; -; Mux20~1 ; 1 ; -; Mux20~0 ; 1 ; -; Addr[14]~19COUT1_90 ; 1 ; -; Addr[14]~19 ; 1 ; -; Mux21~2 ; 1 ; -; LS[4]~13COUT1_42 ; 1 ; -; LS[4]~13 ; 1 ; -; RAr[4] ; 1 ; -; Mux21~1 ; 1 ; -; Mux21~0 ; 1 ; -; Addr[13]~15COUT1_88 ; 1 ; -; Addr[13]~15 ; 1 ; -; Addr[3]~13COUT1_98 ; 1 ; -; Addr[3]~13 ; 1 ; -; Mux22~3 ; 1 ; -; LS[3]~11COUT1_40 ; 1 ; -; LS[3]~11 ; 1 ; -; Mux22~2 ; 1 ; -; Mux22~1 ; 1 ; -; Mux22~0 ; 1 ; -; LS[12]~9COUT1_54 ; 1 ; -; LS[12]~9 ; 1 ; -; Addr[2]~9COUT1_96 ; 1 ; -; Addr[2]~9 ; 1 ; -; Mux23~3 ; 1 ; -; LS[2]~7COUT1_38 ; 1 ; -; LS[2]~7 ; 1 ; -; Mux23~2 ; 1 ; -; Mux23~1 ; 1 ; -; nRESf[3] ; 1 ; -; Mux23~0 ; 1 ; -; Addr[11]~7COUT1_86 ; 1 ; -; Addr[11]~7 ; 1 ; -; Addr[1]~5COUT1_94 ; 1 ; -; Addr[1]~5 ; 1 ; -; Mux24~3 ; 1 ; -; Mux24~2 ; 1 ; -; Mux24~1 ; 1 ; -; Mux24~0 ; 1 ; -; LS[10]~1COUT1_52 ; 1 ; -; LS[10]~1 ; 1 ; -; Addr[10]~3COUT1_84 ; 1 ; -; Addr[10]~3 ; 1 ; -; Mux13~0 ; 1 ; -; Mux14~3 ; 1 ; -; Mux14~1 ; 1 ; -; Mux14~0 ; 1 ; -; always8~4 ; 1 ; -; RAr[5] ; 1 ; -; always8~3 ; 1 ; -; always8~2 ; 1 ; -; always8~1 ; 1 ; -; RCKE~reg0 ; 1 ; -; DQMH~reg0 ; 1 ; -; DQML~reg0 ; 1 ; -; nSWE~reg0 ; 1 ; -; nCAS~reg0 ; 1 ; -; nRAS~reg0 ; 1 ; -; nRCS~reg0 ; 1 ; -; SA[12]~reg0 ; 1 ; -; SA[11]~reg0 ; 1 ; -; SA[10]~reg0 ; 1 ; -; SA[9]~reg0 ; 1 ; -; SA[8]~reg0 ; 1 ; -; SA[7]~reg0 ; 1 ; -; SA[6]~reg0 ; 1 ; -; SA[5]~reg0 ; 1 ; -; SA[4]~reg0 ; 1 ; -; SA[3]~reg0 ; 1 ; -; SA[2]~reg0 ; 1 ; -; SA[1]~reg0 ; 1 ; -; SA[0]~reg0 ; 1 ; -; SBA[1]~reg0 ; 1 ; -; SBA[0]~reg0 ; 1 ; -; comb~1 ; 1 ; -; Equal16~2 ; 1 ; -; Equal16~1 ; 1 ; -; Equal16~0 ; 1 ; -; PHI0r2 ; 1 ; -; comb~0 ; 1 ; -+---------------------+-----------+ - - -+--------------------------------------------------+ -; Other Routing Usage Summary ; -+-----------------------------+--------------------+ -; Other Routing Resource Type ; Usage ; -+-----------------------------+--------------------+ -; C4s ; 226 / 784 ( 29 % ) ; -; Direct links ; 67 / 888 ( 8 % ) ; -; Global clocks ; 3 / 4 ( 75 % ) ; -; LAB clocks ; 14 / 32 ( 44 % ) ; -; LUT chains ; 24 / 216 ( 11 % ) ; -; Local interconnects ; 434 / 888 ( 49 % ) ; -; R4s ; 255 / 704 ( 36 % ) ; -+-----------------------------+--------------------+ ++--------------------------------------------+ +; Routing Usage Summary ; ++-----------------------+--------------------+ +; Routing Resource Type ; Usage ; ++-----------------------+--------------------+ +; C4s ; 211 / 784 ( 27 % ) ; +; Direct links ; 50 / 888 ( 6 % ) ; +; Global clocks ; 3 / 4 ( 75 % ) ; +; LAB clocks ; 13 / 32 ( 41 % ) ; +; LUT chains ; 8 / 216 ( 4 % ) ; +; Local interconnects ; 379 / 888 ( 43 % ) ; +; R4s ; 199 / 704 ( 28 % ) ; ++-----------------------+--------------------+ +---------------------------------------------------------------------------+ ; LAB Logic Elements ; +--------------------------------------------+------------------------------+ -; Number of Logic Elements (Average = 9.75) ; Number of LABs (Total = 24) ; +; Number of Logic Elements (Average = 9.71) ; Number of LABs (Total = 24) ; +--------------------------------------------+------------------------------+ ; 1 ; 0 ; ; 2 ; 0 ; @@ -947,8 +603,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; 6 ; 0 ; ; 7 ; 1 ; ; 8 ; 1 ; -; 9 ; 1 ; -; 10 ; 21 ; +; 9 ; 2 ; +; 10 ; 20 ; +--------------------------------------------+------------------------------+ @@ -957,19 +613,19 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +------------------------------------+------------------------------+ ; LAB-wide Signals (Average = 1.71) ; Number of LABs (Total = 24) ; +------------------------------------+------------------------------+ -; 1 Async. clear ; 3 ; -; 1 Clock ; 19 ; +; 1 Async. clear ; 5 ; +; 1 Clock ; 21 ; ; 1 Clock enable ; 5 ; -; 1 Sync. clear ; 6 ; +; 1 Sync. clear ; 4 ; ; 1 Sync. load ; 3 ; -; 2 Clocks ; 5 ; +; 2 Clocks ; 3 ; +------------------------------------+------------------------------+ +-----------------------------------------------------------------------------+ ; LAB Signals Sourced ; +----------------------------------------------+------------------------------+ -; Number of Signals Sourced (Average = 10.67) ; Number of LABs (Total = 24) ; +; Number of Signals Sourced (Average = 10.50) ; Number of LABs (Total = 24) ; +----------------------------------------------+------------------------------+ ; 0 ; 0 ; ; 1 ; 0 ; @@ -979,70 +635,70 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; 5 ; 0 ; ; 6 ; 0 ; ; 7 ; 1 ; -; 8 ; 0 ; +; 8 ; 1 ; ; 9 ; 1 ; -; 10 ; 16 ; -; 11 ; 2 ; -; 12 ; 0 ; +; 10 ; 15 ; +; 11 ; 0 ; +; 12 ; 3 ; ; 13 ; 1 ; ; 14 ; 1 ; ; 15 ; 1 ; -; 16 ; 1 ; +----------------------------------------------+------------------------------+ +--------------------------------------------------------------------------------+ ; LAB Signals Sourced Out ; +-------------------------------------------------+------------------------------+ -; Number of Signals Sourced Out (Average = 7.54) ; Number of LABs (Total = 24) ; +; Number of Signals Sourced Out (Average = 7.42) ; Number of LABs (Total = 24) ; +-------------------------------------------------+------------------------------+ ; 0 ; 0 ; ; 1 ; 0 ; -; 2 ; 1 ; -; 3 ; 0 ; -; 4 ; 0 ; +; 2 ; 0 ; +; 3 ; 1 ; +; 4 ; 2 ; ; 5 ; 4 ; -; 6 ; 2 ; -; 7 ; 4 ; -; 8 ; 4 ; -; 9 ; 4 ; -; 10 ; 4 ; -; 11 ; 1 ; +; 6 ; 4 ; +; 7 ; 2 ; +; 8 ; 2 ; +; 9 ; 1 ; +; 10 ; 6 ; +; 11 ; 0 ; +; 12 ; 2 ; +-------------------------------------------------+------------------------------+ +-----------------------------------------------------------------------------+ ; LAB Distinct Inputs ; +----------------------------------------------+------------------------------+ -; Number of Distinct Inputs (Average = 16.08) ; Number of LABs (Total = 24) ; +; Number of Distinct Inputs (Average = 14.13) ; Number of LABs (Total = 24) ; +----------------------------------------------+------------------------------+ ; 0 ; 0 ; ; 1 ; 0 ; ; 2 ; 0 ; ; 3 ; 0 ; ; 4 ; 0 ; -; 5 ; 0 ; -; 6 ; 1 ; +; 5 ; 2 ; +; 6 ; 2 ; ; 7 ; 0 ; ; 8 ; 1 ; ; 9 ; 1 ; -; 10 ; 3 ; -; 11 ; 0 ; -; 12 ; 1 ; -; 13 ; 2 ; -; 14 ; 0 ; +; 10 ; 2 ; +; 11 ; 1 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 4 ; ; 15 ; 3 ; ; 16 ; 1 ; ; 17 ; 1 ; -; 18 ; 2 ; -; 19 ; 1 ; -; 20 ; 2 ; +; 18 ; 1 ; +; 19 ; 0 ; +; 20 ; 1 ; ; 21 ; 0 ; -; 22 ; 2 ; +; 22 ; 1 ; ; 23 ; 0 ; -; 24 ; 0 ; -; 25 ; 0 ; -; 26 ; 3 ; +; 24 ; 1 ; +; 25 ; 1 ; +; 26 ; 1 ; +----------------------------------------------+------------------------------+ @@ -1057,18 +713,18 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; Enable INIT_DONE output ; Off ; ; Configuration scheme ; Passive Serial ; ; Reserve all unused pins ; As output driving ground ; -; Base pin-out file on sameframe device ; Off ; +----------------------------------------------+--------------------------+ +-----------------+ ; Fitter Messages ; +-----------------+ -Warning (20028): Parallel compilation is not licensed and has been disabled +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected Info (119006): Selected device EPM240T100C5 for design "GR8RAM" Info (21077): Low junction temperature is 0 degrees C Info (21077): High junction temperature is 85 degrees C -Info (171004): Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance +Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices Info (176445): Device EPM240T100I5 is compatible @@ -1076,6 +732,7 @@ Info (176444): Device migration not selected. If you intend to use device migrat Info (176445): Device EPM570T100C5 is compatible Info (176445): Device EPM570T100I5 is compatible Info (176445): Device EPM570T100A5 is compatible +Critical Warning (169085): No exact pin location assignment(s) for 1 pins of 80 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report. Info (332104): Reading SDC File: 'GR8RAM.sdc' Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements Info (332111): Found 2 clocks @@ -1084,42 +741,53 @@ Info (332111): Found 2 clocks Info (332111): 40.000 C25M Info (332111): 978.000 PHI0 Info (186079): Completed User Assigned Global Signals Promotion Operation -Info (186215): Automatically promoted signal "C25M" to use Global clock in PIN 64 -Info (186216): Automatically promoted some destinations of signal "PHI0" to use Global clock +Info (186215): Automatically promoted signal "C25M" to use Global clock in PIN 64 File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 9 +Info (186216): Automatically promoted some destinations of signal "PHI0" to use Global clock File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 9 Info (186217): Destination "comb~0" may be non-global or may not use global clock - Info (186217): Destination "PHI0r1" may be non-global or may not use global clock -Info (186228): Pin "PHI0" drives global clock, but is not placed in a dedicated clock pin position -Info (186216): Automatically promoted some destinations of signal "nRESr" to use Global clock - Info (186217): Destination "IOROMEN" may be non-global or may not use global clock + Info (186217): Destination "PHI0r1" may be non-global or may not use global clock File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 10 +Info (186228): Pin "PHI0" drives global clock, but is not placed in a dedicated clock pin position File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 9 +Info (186216): Automatically promoted some destinations of signal "nRESr" to use Global clock File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 16 + Info (186217): Destination "IOROMEN" may be non-global or may not use global clock File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 94 Info (186079): Completed Auto Global Promotion Operation Info (176234): Starting register packing Info (186468): Started processing fast register assignments Info (186469): Finished processing fast register assignments Info (176235): Finished register packing +Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement + Info (176211): Number of I/O pins in group: 1 (unused VREF, 3.3V VCCIO, 1 input, 0 output, 0 bidirectional) + Info (176212): I/O standards used: 3.3-V LVTTL. +Info (176215): I/O bank details before I/O pin placement + Info (176214): Statistics of I/O banks + Info (176213): I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 38 total pin(s) used -- 0 pins available + Info (176213): I/O bank number 2 does not use VREF pins and has 3.3V VCCIO pins. 41 total pin(s) used -- 1 pins available Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01 +Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family. Info (170189): Fitter placement preparation operations beginning Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 Info (170191): Fitter placement operations beginning Info (170137): Fitter placement was successful Info (170192): Fitter placement operations ending: elapsed time is 00:00:01 Info (170193): Fitter routing operations beginning -Info (170195): Router estimated average interconnect usage is 34% of the available device resources - Info (170196): Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5 +Info (170195): Router estimated average interconnect usage is 30% of the available device resources + Info (170196): Router estimated peak interconnect usage is 30% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5 +Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info (170201): Optimizations that may affect the design's routability were skipped + Info (170200): Optimizations that may affect the design's timing were skipped Info (170194): Fitter routing operations ending: elapsed time is 00:00:00 Info (11888): Total time spent on timing analysis during the Fitter is 0.27 seconds. Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00 Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'. -Info (144001): Generated suppressed messages file C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.fit.smsg -Info: Quartus II 64-Bit Fitter was successful. 0 errors, 3 warnings - Info: Peak virtual memory: 544 megabytes - Info: Processing ended: Tue Sep 14 01:35:30 2021 - Info: Elapsed time: 00:00:02 - Info: Total CPU time (on all processors): 00:00:03 +Info (144001): Generated suppressed messages file /Repos2/GR8RAM/cpld2/output_files/GR8RAM.fit.smsg +Info: Quartus Prime Fitter was successful. 0 errors, 4 warnings + Info: Peak virtual memory: 13746 megabytes + Info: Processing ended: Tue Feb 28 11:21:23 2023 + Info: Elapsed time: 00:00:06 + Info: Total CPU time (on all processors): 00:00:05 +----------------------------+ ; Fitter Suppressed Messages ; +----------------------------+ -The suppressed messages can be found in C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.fit.smsg. +The suppressed messages can be found in /Repos2/GR8RAM/cpld2/output_files/GR8RAM.fit.smsg. diff --git a/cpld/output_files/GR8RAM.fit.smsg b/cpld/output_files/GR8RAM.fit.smsg old mode 100755 new mode 100644 diff --git a/cpld/output_files/GR8RAM.fit.summary b/cpld/output_files/GR8RAM.fit.summary old mode 100755 new mode 100644 index 5d9e773..615a84b --- a/cpld/output_files/GR8RAM.fit.summary +++ b/cpld/output_files/GR8RAM.fit.summary @@ -1,11 +1,11 @@ -Fitter Status : Successful - Tue Sep 14 01:35:30 2021 -Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition +Fitter Status : Successful - Tue Feb 28 11:21:23 2023 +Quartus Prime Version : 22.1std.0 Build 915 10/25/2022 SC Lite Edition Revision Name : GR8RAM Top-level Entity Name : GR8RAM Family : MAX II Device : EPM240T100C5 Timing Models : Final -Total logic elements : 234 / 240 ( 98 % ) +Total logic elements : 233 / 240 ( 97 % ) Total pins : 80 / 80 ( 100 % ) Total virtual pins : 0 UFM blocks : 0 / 1 ( 0 % ) diff --git a/cpld/output_files/GR8RAM.flow.rpt b/cpld/output_files/GR8RAM.flow.rpt old mode 100755 new mode 100644 index e7cc3c2..cb3a8d0 --- a/cpld/output_files/GR8RAM.flow.rpt +++ b/cpld/output_files/GR8RAM.flow.rpt @@ -1,6 +1,6 @@ Flow report for GR8RAM -Tue Sep 14 01:35:34 2021 -Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +Tue Feb 28 11:21:31 2023 +Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition --------------------- @@ -21,37 +21,38 @@ Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit ---------------- ; Legal Notice ; ---------------- -Copyright (C) 1991-2013 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic +Copyright (C) 2022 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. -+-----------------------------------------------------------------------------+ -; Flow Summary ; -+---------------------------+-------------------------------------------------+ -; Flow Status ; Successful - Tue Sep 14 01:35:32 2021 ; -; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; -; Revision Name ; GR8RAM ; -; Top-level Entity Name ; GR8RAM ; -; Family ; MAX II ; -; Device ; EPM240T100C5 ; -; Timing Models ; Final ; -; Total logic elements ; 234 / 240 ( 98 % ) ; -; Total pins ; 80 / 80 ( 100 % ) ; -; Total virtual pins ; 0 ; -; UFM blocks ; 0 / 1 ( 0 % ) ; -+---------------------------+-------------------------------------------------+ ++------------------------------------------------------------------------+ +; Flow Summary ; ++-----------------------+------------------------------------------------+ +; Flow Status ; Successful - Tue Feb 28 11:21:31 2023 ; +; Quartus Prime Version ; 22.1std.0 Build 915 10/25/2022 SC Lite Edition ; +; Revision Name ; GR8RAM ; +; Top-level Entity Name ; GR8RAM ; +; Family ; MAX II ; +; Device ; EPM240T100C5 ; +; Timing Models ; Final ; +; Total logic elements ; 233 / 240 ( 97 % ) ; +; Total pins ; 80 / 80 ( 100 % ) ; +; Total virtual pins ; 0 ; +; UFM blocks ; 0 / 1 ( 0 % ) ; ++-----------------------+------------------------------------------------+ +-----------------------------------------+ @@ -59,67 +60,60 @@ applicable agreement for further details. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 09/14/2021 01:35:26 ; +; Start date & time ; 02/28/2023 11:20:54 ; ; Main task ; Compilation ; ; Revision Name ; GR8RAM ; +-------------------+---------------------+ -+---------------------------------------------------------------------------------------------------------------------------+ -; Flow Non-Default Global Settings ; -+-------------------------------------------------+------------------------------+---------------+-------------+------------+ -; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; -+-------------------------------------------------+------------------------------+---------------+-------------+------------+ -; ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ; On ; Off ; -- ; -- ; -; ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES ; Always ; Auto ; -- ; -- ; -; ALM_REGISTER_PACKING_EFFORT ; High ; Medium ; -- ; -- ; -; AUTO_PACKED_REGISTERS_MAXII ; Minimize Area ; Auto ; -- ; -- ; -; AUTO_RESOURCE_SHARING ; On ; Off ; -- ; -- ; -; COMPILER_SIGNATURE_ID ; 962837114763.163159772501756 ; -- ; -- ; -- ; -; FINAL_PLACEMENT_OPTIMIZATION ; Always ; Automatically ; -- ; -- ; -; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ; -; IOBANK_VCCIO ; 3.3V ; -- ; -- ; 1 ; -; IOBANK_VCCIO ; 3.3V ; -- ; -- ; 2 ; -; MAXII_OPTIMIZATION_TECHNIQUE ; Area ; Balanced ; -- ; -- ; -; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; -; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; -; MUX_RESTRUCTURE ; On ; Auto ; -- ; -- ; -; PLACEMENT_EFFORT_MULTIPLIER ; 2.0 ; 1.0 ; -- ; -- ; -; POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR ; 3.3V ; -- ; -- ; -- ; -; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; -; REMOVE_REDUNDANT_LOGIC_CELLS ; On ; Off ; -- ; -- ; -; ROUTER_EFFORT_MULTIPLIER ; 2.0 ; 1.0 ; -- ; -- ; -; ROUTER_REGISTER_DUPLICATION ; Off ; Auto ; -- ; -- ; -; SEED ; 235 ; 1 ; -- ; -- ; -; STATE_MACHINE_PROCESSING ; Minimal Bits ; Auto ; -- ; -- ; -; SYNTHESIS_SEED ; 123 ; 1 ; -- ; -- ; -; SYNTH_TIMING_DRIVEN_SYNTHESIS ; Off ; -- ; -- ; -- ; -+-------------------------------------------------+------------------------------+---------------+-------------+------------+ ++--------------------------------------------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++---------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++---------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ +; COMPILER_SIGNATURE_ID ; 121381084694.167760125411500 ; -- ; -- ; -- ; +; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ; +; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ; +; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ; +; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_symbol ; +; EDA_NETLIST_WRITER_OUTPUT_DIR ; simulation/questa ; -- ; -- ; eda_simulation ; +; EDA_OUTPUT_DATA_FORMAT ; Verilog Hdl ; -- ; -- ; eda_simulation ; +; EDA_SIMULATION_TOOL ; Questa Intel FPGA (Verilog) ; ; -- ; -- ; +; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ; +; IOBANK_VCCIO ; -- (Not supported for targeted family) ; -- ; -- ; 1 ; +; IOBANK_VCCIO ; -- (Not supported for targeted family) ; -- ; -- ; 2 ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR ; 3.3V ; -- ; -- ; -- ; +; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; ++---------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ -+-------------------------------------------------------------------------------------------------------------------------------+ -; Flow Elapsed Time ; -+---------------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; -+---------------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:02 ; 1.0 ; 422 MB ; 00:00:01 ; -; Fitter ; 00:00:02 ; 1.0 ; 544 MB ; 00:00:02 ; -; Assembler ; 00:00:01 ; 1.0 ; 381 MB ; 00:00:01 ; -; TimeQuest Timing Analyzer ; 00:00:02 ; 1.0 ; 374 MB ; 00:00:01 ; -; Total ; 00:00:07 ; -- ; -- ; 00:00:05 ; -+---------------------------+--------------+-------------------------+---------------------+------------------------------------+ ++--------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:23 ; 1.0 ; 13114 MB ; 00:00:48 ; +; Fitter ; 00:00:06 ; 1.0 ; 13746 MB ; 00:00:05 ; +; Assembler ; 00:00:01 ; 1.0 ; 13099 MB ; 00:00:01 ; +; Timing Analyzer ; 00:00:02 ; 1.0 ; 13081 MB ; 00:00:01 ; +; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 13024 MB ; 00:00:01 ; +; Total ; 00:00:33 ; -- ; -- ; 00:00:56 ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ -+----------------------------------------------------------------------------------------+ -; Flow OS Summary ; -+---------------------------+------------------+-----------+------------+----------------+ -; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; -+---------------------------+------------------+-----------+------------+----------------+ -; Analysis & Synthesis ; Dog-PC ; Windows 7 ; 6.1 ; x86_64 ; -; Fitter ; Dog-PC ; Windows 7 ; 6.1 ; x86_64 ; -; Assembler ; Dog-PC ; Windows 7 ; 6.1 ; x86_64 ; -; TimeQuest Timing Analyzer ; Dog-PC ; Windows 7 ; 6.1 ; x86_64 ; -+---------------------------+------------------+-----------+------------+----------------+ ++------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++----------------------+------------------+------------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++----------------------+------------------+------------+------------+----------------+ +; Analysis & Synthesis ; ZaneMacWin11 ; Windows 10 ; 10.0 ; x86_64 ; +; Fitter ; ZaneMacWin11 ; Windows 10 ; 10.0 ; x86_64 ; +; Assembler ; ZaneMacWin11 ; Windows 10 ; 10.0 ; x86_64 ; +; Timing Analyzer ; ZaneMacWin11 ; Windows 10 ; 10.0 ; x86_64 ; +; EDA Netlist Writer ; ZaneMacWin11 ; Windows 10 ; 10.0 ; x86_64 ; ++----------------------+------------------+------------+------------+----------------+ ------------ @@ -129,6 +123,7 @@ quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM quartus_sta GR8RAM -c GR8RAM +quartus_eda --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM diff --git a/cpld/output_files/GR8RAM.jdi b/cpld/output_files/GR8RAM.jdi old mode 100755 new mode 100644 index 1b5d781..b6cbf71 --- a/cpld/output_files/GR8RAM.jdi +++ b/cpld/output_files/GR8RAM.jdi @@ -1,6 +1,6 @@ - + diff --git a/cpld/output_files/GR8RAM.map.rpt b/cpld/output_files/GR8RAM.map.rpt old mode 100755 new mode 100644 index 766c357..0dbf265 --- a/cpld/output_files/GR8RAM.map.rpt +++ b/cpld/output_files/GR8RAM.map.rpt @@ -1,6 +1,6 @@ Analysis & Synthesis report for GR8RAM -Tue Sep 14 01:35:27 2021 -Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +Tue Feb 28 11:21:16 2023 +Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition --------------------- @@ -26,128 +26,132 @@ Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit ---------------- ; Legal Notice ; ---------------- -Copyright (C) 1991-2013 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic +Copyright (C) 2022 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. -+-------------------------------------------------------------------------------+ -; Analysis & Synthesis Summary ; -+-----------------------------+-------------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Tue Sep 14 01:35:27 2021 ; -; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; -; Revision Name ; GR8RAM ; -; Top-level Entity Name ; GR8RAM ; -; Family ; MAX II ; -; Total logic elements ; 257 ; -; Total pins ; 80 ; -; Total virtual pins ; 0 ; -; UFM blocks ; 0 / 1 ( 0 % ) ; -+-----------------------------+-------------------------------------------------+ ++------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++-----------------------------+------------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Tue Feb 28 11:21:16 2023 ; +; Quartus Prime Version ; 22.1std.0 Build 915 10/25/2022 SC Lite Edition ; +; Revision Name ; GR8RAM ; +; Top-level Entity Name ; GR8RAM ; +; Family ; MAX II ; +; Total logic elements ; 253 ; +; Total pins ; 80 ; +; Total virtual pins ; 0 ; +; UFM blocks ; 0 / 1 ( 0 % ) ; ++-----------------------------+------------------------------------------------+ -+----------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Settings ; -+----------------------------------------------------------------------------+--------------------+--------------------+ -; Option ; Setting ; Default Value ; -+----------------------------------------------------------------------------+--------------------+--------------------+ -; Device ; EPM240T100C5 ; ; -; Top-level entity name ; GR8RAM ; GR8RAM ; -; Family name ; MAX II ; Cyclone IV GX ; -; Restructure Multiplexers ; On ; Auto ; -; State Machine Processing ; Minimal Bits ; Auto ; -; Remove Redundant Logic Cells ; On ; Off ; -; Optimization Technique ; Area ; Balanced ; -; Perform WYSIWYG Primitive Resynthesis ; On ; Off ; -; Allow Shift Register Merging across Hierarchies ; Always ; Auto ; -; Auto Resource Sharing ; On ; Off ; -; Synthesis Seed ; 123 ; 1 ; -; Use smart compilation ; Off ; Off ; -; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; -; Enable compact report table ; Off ; Off ; -; Create Debugging Nodes for IP Cores ; Off ; Off ; -; Preserve fewer node names ; On ; On ; -; Disable OpenCore Plus hardware evaluation ; Off ; Off ; -; Verilog Version ; Verilog_2001 ; Verilog_2001 ; -; VHDL Version ; VHDL_1993 ; VHDL_1993 ; -; Safe State Machine ; Off ; Off ; -; Extract Verilog State Machines ; On ; On ; -; Extract VHDL State Machines ; On ; On ; -; Ignore Verilog initial constructs ; Off ; Off ; -; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; -; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; -; Add Pass-Through Logic to Inferred RAMs ; On ; On ; -; Infer RAMs from Raw Logic ; On ; On ; -; Parallel Synthesis ; On ; On ; -; NOT Gate Push-Back ; On ; On ; -; Power-Up Don't Care ; On ; On ; -; Remove Duplicate Registers ; On ; On ; -; Ignore CARRY Buffers ; Off ; Off ; -; Ignore CASCADE Buffers ; Off ; Off ; -; Ignore GLOBAL Buffers ; Off ; Off ; -; Ignore ROW GLOBAL Buffers ; Off ; Off ; -; Ignore LCELL Buffers ; Off ; Off ; -; Ignore SOFT Buffers ; On ; On ; -; Limit AHDL Integers to 32 Bits ; Off ; Off ; -; Carry Chain Length ; 70 ; 70 ; -; Auto Carry Chains ; On ; On ; -; Auto Open-Drain Pins ; On ; On ; -; Auto Shift Register Replacement ; Auto ; Auto ; -; Auto Clock Enable Replacement ; On ; On ; -; Allow Synchronous Control Signals ; On ; On ; -; Force Use of Synchronous Clear Signals ; Off ; Off ; -; Use LogicLock Constraints during Resource Balancing ; On ; On ; -; Ignore translate_off and synthesis_off directives ; Off ; Off ; -; Report Parameter Settings ; On ; On ; -; Report Source Assignments ; On ; On ; -; Report Connectivity Checks ; On ; On ; -; Ignore Maximum Fan-Out Assignments ; Off ; Off ; -; Synchronization Register Chain Length ; 2 ; 2 ; -; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; -; HDL message level ; Level2 ; Level2 ; -; Suppress Register Optimization Related Messages ; Off ; Off ; -; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; -; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; -; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; -; Clock MUX Protection ; On ; On ; -; Block Design Naming ; Auto ; Auto ; -; Synthesis Effort ; Auto ; Auto ; -; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; -; Pre-Mapping Resynthesis Optimization ; Off ; Off ; -; Analysis & Synthesis Message Level ; Medium ; Medium ; -; Disable Register Merging Across Hierarchies ; Auto ; Auto ; -+----------------------------------------------------------------------------+--------------------+--------------------+ ++------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++------------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++------------------------------------------------------------------+--------------------+--------------------+ +; Device ; EPM240T100C5 ; ; +; Top-level entity name ; GR8RAM ; GR8RAM ; +; Family name ; MAX II ; Cyclone V ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; Intel FPGA IP Evaluation Mode ; Enable ; Enable ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL_1993 ; VHDL_1993 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Infer RAMs from Raw Logic ; On ; On ; +; Parallel Synthesis ; On ; On ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Report Parameter Settings ; On ; On ; +; Report Source Assignments ; On ; On ; +; Report Connectivity Checks ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 2 ; 2 ; +; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Block Design Naming ; Auto ; Auto ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; +; Disable Register Merging Across Hierarchies ; Auto ; Auto ; ++------------------------------------------------------------------+--------------------+--------------------+ -Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. -+-------------------------------------+ -; Parallel Compilation ; -+----------------------------+--------+ -; Processors ; Number ; -+----------------------------+--------+ -; Number detected on machine ; 12 ; -; Maximum allowed ; 1 ; -+----------------------------+--------+ ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 1 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; ++----------------------------+-------------+ -+--------------------------------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Source Files Read ; -+----------------------------------+-----------------+------------------------+----------------------------------------------------+---------+ -; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; -+----------------------------------+-----------------+------------------------+----------------------------------------------------+---------+ -; GR8RAM.v ; yes ; User Verilog HDL File ; C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v ; ; -+----------------------------------+-----------------+------------------------+----------------------------------------------------+---------+ ++-----------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+------------------------------+-------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------+-----------------+------------------------------+-------------------------------------------+---------+ +; gr8ram.v ; yes ; Auto-Found Verilog HDL File ; //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v ; ; ++----------------------------------+-----------------+------------------------------+-------------------------------------------+---------+ +-----------------------------------------------------+ @@ -155,59 +159,59 @@ Parallel compilation was disabled, but you have multiple processors available. E +---------------------------------------------+-------+ ; Resource ; Usage ; +---------------------------------------------+-------+ -; Total logic elements ; 257 ; -; -- Combinational with no register ; 136 ; -; -- Register only ; 24 ; -; -- Combinational with a register ; 97 ; +; Total logic elements ; 253 ; +; -- Combinational with no register ; 129 ; +; -- Register only ; 26 ; +; -- Combinational with a register ; 98 ; ; ; ; ; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 126 ; -; -- 3 input functions ; 41 ; -; -- 2 input functions ; 65 ; +; -- 4 input functions ; 124 ; +; -- 3 input functions ; 30 ; +; -- 2 input functions ; 71 ; ; -- 1 input functions ; 0 ; -; -- 0 input functions ; 1 ; +; -- 0 input functions ; 2 ; ; ; ; ; Logic elements by mode ; ; -; -- normal mode ; 224 ; +; -- normal mode ; 220 ; ; -- arithmetic mode ; 33 ; ; -- qfbk mode ; 0 ; ; -- register cascade mode ; 0 ; ; -- synchronous clear/load mode ; 45 ; ; -- asynchronous clear/load mode ; 29 ; ; ; ; -; Total registers ; 121 ; +; Total registers ; 124 ; ; Total logic cells in carry chains ; 37 ; ; I/O pins ; 80 ; ; Maximum fan-out node ; C25M ; -; Maximum fan-out ; 107 ; -; Total fan-out ; 1095 ; -; Average fan-out ; 3.25 ; +; Maximum fan-out ; 110 ; +; Total fan-out ; 1076 ; +; Average fan-out ; 3.23 ; +---------------------------------------------+-------+ -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Resource Utilization by Entity ; -+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+ -; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ; -+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+ -; |GR8RAM ; 257 (257) ; 121 ; 0 ; 80 ; 0 ; 136 (136) ; 24 (24) ; 97 (97) ; 37 (37) ; 0 (0) ; |GR8RAM ; work ; -+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+ ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ; ++----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+ +; |GR8RAM ; 253 (253) ; 124 ; 0 ; 80 ; 0 ; 129 (129) ; 26 (26) ; 98 (98) ; 37 (37) ; 0 (0) ; |GR8RAM ; GR8RAM ; work ; ++----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. -Encoding Type: Minimal Bits -+-----------------------------------------------------------+ -; State Machine - |GR8RAM|IS ; -+--------+----------------+----------------+----------------+ -; Name ; IS.state_bit_2 ; IS.state_bit_1 ; IS.state_bit_0 ; -+--------+----------------+----------------+----------------+ -; IS.000 ; 0 ; 0 ; 0 ; -; IS.001 ; 0 ; 0 ; 1 ; -; IS.100 ; 1 ; 0 ; 0 ; -; IS.101 ; 1 ; 0 ; 1 ; -; IS.110 ; 0 ; 1 ; 0 ; -; IS.111 ; 0 ; 1 ; 1 ; -+--------+----------------+----------------+----------------+ +Encoding Type: One-Hot ++--------------------------------------------------------------+ +; State Machine - |GR8RAM|IS ; ++--------+--------+--------+--------+--------+--------+--------+ +; Name ; IS.111 ; IS.110 ; IS.101 ; IS.100 ; IS.001 ; IS.000 ; ++--------+--------+--------+--------+--------+--------+--------+ +; IS.000 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; IS.001 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ; +; IS.100 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ; +; IS.101 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ; +; IS.110 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ; +; IS.111 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ; ++--------+--------+--------+--------+--------+--------+--------+ +------------------------------------------------------------+ @@ -215,8 +219,10 @@ Encoding Type: Minimal Bits +---------------------------------------+--------------------+ ; Register name ; Reason for Removal ; +---------------------------------------+--------------------+ +; IS~8 ; Lost fanout ; +; IS~9 ; Lost fanout ; ; IS~10 ; Lost fanout ; -; Total Number of Removed Registers = 1 ; ; +; Total Number of Removed Registers = 3 ; ; +---------------------------------------+--------------------+ @@ -225,12 +231,12 @@ Encoding Type: Minimal Bits +----------------------------------------------+-------+ ; Statistic ; Value ; +----------------------------------------------+-------+ -; Total registers ; 121 ; +; Total registers ; 124 ; ; Number of registers using Synchronous Clear ; 12 ; ; Number of registers using Synchronous Load ; 33 ; ; Number of registers using Asynchronous Clear ; 29 ; ; Number of registers using Asynchronous Load ; 0 ; -; Number of registers using Clock Enable ; 24 ; +; Number of registers using Clock Enable ; 29 ; ; Number of registers using Preset ; 0 ; +----------------------------------------------+-------+ @@ -264,7 +270,7 @@ Encoding Type: Minimal Bits ; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |GR8RAM|RDD[1] ; ; 5:1 ; 4 bits ; 12 LEs ; 8 LEs ; 4 LEs ; Yes ; |GR8RAM|RDD[4] ; ; 18:1 ; 2 bits ; 24 LEs ; 8 LEs ; 16 LEs ; Yes ; |GR8RAM|DQMH~reg0 ; -; 8:1 ; 5 bits ; 25 LEs ; 20 LEs ; 5 LEs ; No ; |GR8RAM|IS ; +; 7:1 ; 5 bits ; 20 LEs ; 20 LEs ; 0 LEs ; No ; |GR8RAM|IS ; +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ @@ -272,45 +278,45 @@ Encoding Type: Minimal Bits ; Analysis & Synthesis Messages ; +-------------------------------+ Info: ******************************************************************* -Info: Running Quartus II 64-Bit Analysis & Synthesis - Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - Info: Processing started: Tue Sep 14 01:35:25 2021 +Info: Running Quartus Prime Analysis & Synthesis + Info: Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition + Info: Processing started: Tue Feb 28 11:20:53 2023 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM -Warning (20028): Parallel compilation is not licensed and has been disabled -Info (12021): Found 1 design units, including 1 entities, in source file gr8ram.v - Info (12023): Found entity 1: GR8RAM +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected +Warning (12125): Using design file gr8ram.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project + Info (12023): Found entity 1: GR8RAM File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 1 Info (12127): Elaborating entity "GR8RAM" for the top level hierarchy -Warning (10230): Verilog HDL assignment warning at GR8RAM.v(42): truncated value with size 32 to match size of target (4) -Warning (10230): Verilog HDL assignment warning at GR8RAM.v(47): truncated value with size 32 to match size of target (14) -Warning (10230): Verilog HDL assignment warning at GR8RAM.v(134): truncated value with size 32 to match size of target (8) -Warning (10230): Verilog HDL assignment warning at GR8RAM.v(142): truncated value with size 32 to match size of target (8) -Warning (10230): Verilog HDL assignment warning at GR8RAM.v(149): truncated value with size 32 to match size of target (8) -Info (17026): Resynthesizing 0 WYSIWYG logic cells and I/Os using "area" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched +Warning (10230): Verilog HDL assignment warning at gr8ram.v(42): truncated value with size 32 to match size of target (4) File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 42 +Warning (10230): Verilog HDL assignment warning at gr8ram.v(47): truncated value with size 32 to match size of target (14) File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 47 +Warning (10230): Verilog HDL assignment warning at gr8ram.v(134): truncated value with size 32 to match size of target (8) File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 134 +Warning (10230): Verilog HDL assignment warning at gr8ram.v(142): truncated value with size 32 to match size of target (8) File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 142 +Warning (10230): Verilog HDL assignment warning at gr8ram.v(149): truncated value with size 32 to match size of target (8) File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 149 Warning (13024): Output pins are stuck at VCC or GND - Warning (13410): Pin "nNMIout" is stuck at VCC - Warning (13410): Pin "nIRQout" is stuck at VCC - Warning (13410): Pin "nRDYout" is stuck at VCC - Warning (13410): Pin "nINHout" is stuck at VCC - Warning (13410): Pin "RWout" is stuck at VCC - Warning (13410): Pin "nDMAout" is stuck at VCC - Warning (13410): Pin "RAdir" is stuck at VCC -Info (17049): 1 registers lost all their fanouts during netlist optimizations. -Info (21057): Implemented 337 device resources after synthesis - the final resource count might be different + Warning (13410): Pin "nNMIout" is stuck at VCC File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 563 + Warning (13410): Pin "nIRQout" is stuck at VCC File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 566 + Warning (13410): Pin "nRDYout" is stuck at VCC File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 565 + Warning (13410): Pin "nINHout" is stuck at VCC File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 564 + Warning (13410): Pin "RWout" is stuck at VCC File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 567 + Warning (13410): Pin "nDMAout" is stuck at VCC File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 562 + Warning (13410): Pin "RAdir" is stuck at VCC File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 561 +Info (17049): 3 registers lost all their fanouts during netlist optimizations. +Info (21057): Implemented 333 device resources after synthesis - the final resource count might be different Info (21058): Implemented 28 input pins Info (21059): Implemented 35 output pins Info (21060): Implemented 17 bidirectional pins - Info (21061): Implemented 257 logic cells -Info (144001): Generated suppressed messages file C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg -Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 14 warnings - Info: Peak virtual memory: 422 megabytes - Info: Processing ended: Tue Sep 14 01:35:27 2021 - Info: Elapsed time: 00:00:02 - Info: Total CPU time (on all processors): 00:00:01 + Info (21061): Implemented 253 logic cells +Info (144001): Generated suppressed messages file /Repos2/GR8RAM/cpld2/output_files/GR8RAM.map.smsg +Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 15 warnings + Info: Peak virtual memory: 13114 megabytes + Info: Processing ended: Tue Feb 28 11:21:16 2023 + Info: Elapsed time: 00:00:23 + Info: Total CPU time (on all processors): 00:00:48 +------------------------------------------+ ; Analysis & Synthesis Suppressed Messages ; +------------------------------------------+ -The suppressed messages can be found in C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg. +The suppressed messages can be found in /Repos2/GR8RAM/cpld2/output_files/GR8RAM.map.smsg. diff --git a/cpld/output_files/GR8RAM.map.smsg b/cpld/output_files/GR8RAM.map.smsg old mode 100755 new mode 100644 index 91314af..45e0f77 --- a/cpld/output_files/GR8RAM.map.smsg +++ b/cpld/output_files/GR8RAM.map.smsg @@ -1,2 +1,2 @@ -Warning (10273): Verilog HDL warning at GR8RAM.v(110): extended using "x" or "z" -Warning (10273): Verilog HDL warning at GR8RAM.v(286): extended using "x" or "z" +Warning (10273): Verilog HDL warning at gr8ram.v(110): extended using "x" or "z" File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 110 +Warning (10273): Verilog HDL warning at gr8ram.v(286): extended using "x" or "z" File: //mac/iCloud/Repos2/GR8RAM/cpld2/gr8ram.v Line: 286 diff --git a/cpld/output_files/GR8RAM.map.summary b/cpld/output_files/GR8RAM.map.summary old mode 100755 new mode 100644 index 6277dc1..6a8e211 --- a/cpld/output_files/GR8RAM.map.summary +++ b/cpld/output_files/GR8RAM.map.summary @@ -1,9 +1,9 @@ -Analysis & Synthesis Status : Successful - Tue Sep 14 01:35:27 2021 -Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition +Analysis & Synthesis Status : Successful - Tue Feb 28 11:21:16 2023 +Quartus Prime Version : 22.1std.0 Build 915 10/25/2022 SC Lite Edition Revision Name : GR8RAM Top-level Entity Name : GR8RAM Family : MAX II -Total logic elements : 257 +Total logic elements : 253 Total pins : 80 Total virtual pins : 0 UFM blocks : 0 / 1 ( 0 % ) diff --git a/cpld/output_files/GR8RAM.pin b/cpld/output_files/GR8RAM.pin old mode 100755 new mode 100644 index c0079bd..33a0c06 --- a/cpld/output_files/GR8RAM.pin +++ b/cpld/output_files/GR8RAM.pin @@ -1,21 +1,22 @@ - -- Copyright (C) 1991-2013 Altera Corporation - -- Your use of Altera Corporation's design tools, logic functions - -- and other software and tools, and its AMPP partner logic + -- Copyright (C) 2022 Intel Corporation. All rights reserved. + -- Your use of Intel Corporation's design tools, logic functions + -- and other software and tools, and any partner logic -- functions, and any output files from any of the foregoing -- (including device programming or simulation files), and any -- associated documentation or information are expressly subject - -- to the terms and conditions of the Altera Program License - -- Subscription Agreement, Altera MegaCore Function License - -- Agreement, or other applicable license agreement, including, - -- without limitation, that your use is for the sole purpose of - -- programming logic devices manufactured by Altera and sold by - -- Altera or its authorized distributors. Please refer to the - -- applicable agreement for further details. + -- to the terms and conditions of the Intel Program License + -- Subscription Agreement, the Intel Quartus Prime License Agreement, + -- the Intel FPGA IP License Agreement, or other applicable license + -- agreement, including, without limitation, that your use is for + -- the sole purpose of programming logic devices manufactured by + -- Intel and sold by Intel or its authorized distributors. Please + -- refer to the applicable agreement for further details, at + -- https://fpgasoftware.intel.com/eula. -- - -- This is a Quartus II output file. It is for reporting purposes only, and is - -- not intended for use as a Quartus II input file. This file cannot be used - -- to make Quartus II pin assignments - for instructions on how to make pin - -- assignments, please see Quartus II help. + -- This is a Quartus Prime output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus Prime input file. This file cannot be used + -- to make Quartus Prime pin assignments - for instructions on how to make pin + -- assignments, please see Quartus Prime help. --------------------------------------------------------------------------------- @@ -26,24 +27,24 @@ -- VCCINT : Dedicated power pin, which MUST be connected to VCC (2.5V/3.3V). -- VCCIO : Dedicated power pin, which MUST be connected to VCC -- of its bank. - -- Bank 1: 3.3V - -- Bank 2: 3.3V + -- Bank 1: 3.3V + -- Bank 2: 3.3V -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. - -- It can also be used to report unused dedicated pins. The connection - -- on the board for unused dedicated pins depends on whether this will - -- be used in a future design. One example is device migration. When - -- using device migration, refer to the device pin-tables. If it is a - -- GND pin in the pin table or if it will not be used in a future design - -- for another purpose the it MUST be connected to GND. If it is an unused - -- dedicated pin, then it can be connected to a valid signal on the board - -- (low, high, or toggling) if that signal is required for a different - -- revision of the design. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. - -- This pin should be connected to GND. It may also be connected to a - -- valid signal on the board (low, high, or toggling) if that signal - -- is required for a different revision of the design. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND - -- or leave it unconnected. + -- or leave it unconnected. -- RESERVED : Unused I/O pin, which MUST be left unconnected. -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. @@ -57,12 +58,12 @@ -- Pin directions (input, output or bidir) are based on device operating in user mode. --------------------------------------------------------------------------------- -Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition CHIP "GR8RAM" ASSIGNED TO AN: EPM240T100C5 Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment ------------------------------------------------------------------------------------------------------------- -RA[4] : 1 : input : 3.3-V LVTTL : : 2 : Y +RA[4] : 1 : input : 3.3-V LVTTL : : 2 : N RA[5] : 2 : input : 3.3-V LVTTL : : 1 : Y RA[6] : 3 : input : 3.3-V LVTTL : : 1 : Y RA[3] : 4 : input : 3.3-V LVTTL : : 1 : Y diff --git a/cpld/output_files/GR8RAM.pof b/cpld/output_files/GR8RAM.pof old mode 100755 new mode 100644 index f433911..c90017c Binary files a/cpld/output_files/GR8RAM.pof and b/cpld/output_files/GR8RAM.pof differ diff --git a/cpld/output_files/GR8RAM.sld b/cpld/output_files/GR8RAM.sld new file mode 100644 index 0000000..f7d3ed7 --- /dev/null +++ b/cpld/output_files/GR8RAM.sld @@ -0,0 +1 @@ + diff --git a/cpld/output_files/GR8RAM.sta.rpt b/cpld/output_files/GR8RAM.sta.rpt old mode 100755 new mode 100644 index 07fc1a7..26f6da6 --- a/cpld/output_files/GR8RAM.sta.rpt +++ b/cpld/output_files/GR8RAM.sta.rpt @@ -1,13 +1,13 @@ -TimeQuest Timing Analyzer report for GR8RAM -Tue Sep 14 01:35:34 2021 -Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +Timing Analyzer report for GR8RAM +Tue Feb 28 11:21:29 2023 +Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition --------------------- ; Table of Contents ; --------------------- 1. Legal Notice - 2. TimeQuest Timing Analyzer Summary + 2. Timing Analyzer Summary 3. Parallel Compilation 4. SDC File List 5. Clocks @@ -21,70 +21,70 @@ Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit 13. Hold: 'C25M' 14. Recovery: 'C25M' 15. Removal: 'C25M' - 16. Minimum Pulse Width: 'C25M' - 17. Minimum Pulse Width: 'PHI0' - 18. Setup Times - 19. Hold Times - 20. Clock to Output Times - 21. Minimum Clock to Output Times - 22. Propagation Delay - 23. Minimum Propagation Delay - 24. Output Enable Times - 25. Minimum Output Enable Times - 26. Output Disable Times - 27. Minimum Output Disable Times - 28. Setup Transfers - 29. Hold Transfers - 30. Recovery Transfers - 31. Removal Transfers - 32. Report TCCS - 33. Report RSKM - 34. Unconstrained Paths - 35. TimeQuest Timing Analyzer Messages + 16. Setup Transfers + 17. Hold Transfers + 18. Recovery Transfers + 19. Removal Transfers + 20. Report TCCS + 21. Report RSKM + 22. Unconstrained Paths Summary + 23. Clock Status Summary + 24. Unconstrained Input Ports + 25. Unconstrained Output Ports + 26. Unconstrained Input Ports + 27. Unconstrained Output Ports + 28. Timing Analyzer Messages ---------------- ; Legal Notice ; ---------------- -Copyright (C) 1991-2013 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic +Copyright (C) 2022 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. -+----------------------------------------------------------------------------------------+ -; TimeQuest Timing Analyzer Summary ; -+--------------------+-------------------------------------------------------------------+ -; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ; -; Revision Name ; GR8RAM ; -; Device Family ; MAX II ; -; Device Name ; EPM240T100C5 ; -; Timing Models ; Final ; -; Delay Model ; Slow Model ; -; Rise/Fall Delays ; Unavailable ; -+--------------------+-------------------------------------------------------------------+ ++--------------------------------------------------------------------------------+ +; Timing Analyzer Summary ; ++-----------------------+--------------------------------------------------------+ +; Quartus Prime Version ; Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition ; +; Timing Analyzer ; Legacy Timing Analyzer ; +; Revision Name ; GR8RAM ; +; Device Family ; MAX II ; +; Device Name ; EPM240T100C5 ; +; Timing Models ; Final ; +; Delay Model ; Slow Model ; +; Rise/Fall Delays ; Unavailable ; ++-----------------------+--------------------------------------------------------+ -Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. -+-------------------------------------+ -; Parallel Compilation ; -+----------------------------+--------+ -; Processors ; Number ; -+----------------------------+--------+ -; Number detected on machine ; 12 ; -; Maximum allowed ; 1 ; -+----------------------------+--------+ ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 1 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; ++----------------------------+-------------+ +---------------------------------------------------+ @@ -92,7 +92,7 @@ Parallel compilation was disabled, but you have multiple processors available. E +---------------+--------+--------------------------+ ; SDC File Path ; Status ; Read at ; +---------------+--------+--------------------------+ -; GR8RAM.sdc ; OK ; Tue Sep 14 01:35:33 2021 ; +; GR8RAM.sdc ; OK ; Tue Feb 28 11:21:29 2023 ; +---------------+--------+--------------------------+ @@ -111,7 +111,7 @@ Parallel compilation was disabled, but you have multiple processors available. E +-----------+-----------------+------------+------+ ; Fmax ; Restricted Fmax ; Clock Name ; Note ; +-----------+-----------------+------------+------+ -; 65.95 MHz ; 65.95 MHz ; C25M ; ; +; 51.43 MHz ; 51.43 MHz ; C25M ; ; +-----------+-----------------+------------+------+ This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. @@ -121,7 +121,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +-------+--------+---------------+ -; C25M ; 12.419 ; 0.000 ; +; C25M ; 10.278 ; 0.000 ; +-------+--------+---------------+ @@ -130,7 +130,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +-------+-------+---------------+ -; C25M ; 1.393 ; 0.000 ; +; C25M ; 1.376 ; 0.000 ; +-------+-------+---------------+ @@ -139,7 +139,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +-------+--------+---------------+ -; C25M ; 33.300 ; 0.000 ; +; C25M ; 33.311 ; 0.000 ; +-------+--------+---------------+ @@ -148,7 +148,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +-------+-------+---------------+ -; C25M ; 6.146 ; 0.000 ; +; C25M ; 6.135 ; 0.000 ; +-------+-------+---------------+ @@ -162,220 +162,220 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+---------+---------------+ -+----------------------------------------------------------------------------------------------------------------+ -; Setup: 'C25M' ; -+--------+----------------+----------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+--------+----------------+----------------+--------------+-------------+--------------+------------+------------+ -; 12.419 ; REGEN ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.248 ; -; 12.825 ; REGEN ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.842 ; -; 12.826 ; REGEN ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.841 ; -; 12.830 ; REGEN ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.837 ; -; 12.861 ; REGEN ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.806 ; -; 12.948 ; Addr[7] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.719 ; -; 13.317 ; REGEN ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.350 ; -; 13.332 ; PS[2] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.335 ; -; 13.332 ; PS[2] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.335 ; -; 13.485 ; REGEN ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.182 ; -; 13.494 ; REGEN ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.173 ; -; 13.610 ; PS[1] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.057 ; -; 13.610 ; PS[1] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.057 ; -; 13.611 ; PS[3] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.056 ; -; 13.611 ; PS[3] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.056 ; -; 13.692 ; Addr[14] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.975 ; -; 13.794 ; Addr[15] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.873 ; -; 13.950 ; Addr[10] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.717 ; -; 13.955 ; PS[2] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.712 ; -; 13.958 ; Addr[12] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.709 ; -; 13.965 ; Addr[4] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.702 ; -; 14.046 ; PS[0] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.621 ; -; 14.046 ; PS[0] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.621 ; -; 14.233 ; PS[1] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.434 ; -; 14.234 ; PS[3] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.433 ; -; 14.257 ; Addr[13] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.410 ; -; 14.387 ; PS[2] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.280 ; -; 14.387 ; PS[2] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.280 ; -; 14.387 ; PS[2] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.280 ; -; 14.387 ; PS[2] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.280 ; -; 14.387 ; PS[2] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.280 ; -; 14.407 ; Addr[11] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.260 ; -; 14.442 ; Addr[6] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.225 ; -; 14.448 ; Addr[5] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.219 ; -; 14.638 ; Addr[19] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.029 ; -; 14.650 ; Addr[3] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.017 ; -; 14.665 ; PS[1] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.002 ; -; 14.665 ; PS[1] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.002 ; -; 14.665 ; PS[1] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.002 ; -; 14.665 ; PS[1] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.002 ; -; 14.665 ; PS[1] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.002 ; -; 14.666 ; PS[3] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.001 ; -; 14.666 ; PS[3] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.001 ; -; 14.666 ; PS[3] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.001 ; -; 14.666 ; PS[3] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.001 ; -; 14.666 ; PS[3] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.001 ; -; 14.669 ; PS[0] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.998 ; -; 14.690 ; Addr[22] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.977 ; -; 14.700 ; Addr[16] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.967 ; -; 14.800 ; SetFWr[1] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.867 ; -; 14.801 ; SetFWr[1] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.866 ; -; 14.805 ; SetFWr[1] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.862 ; -; 14.871 ; Addr[9] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.796 ; -; 14.878 ; Addr[8] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.789 ; -; 15.101 ; PS[0] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.566 ; -; 15.101 ; PS[0] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.566 ; -; 15.101 ; PS[0] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.566 ; -; 15.101 ; PS[0] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.566 ; -; 15.101 ; PS[0] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.566 ; -; 15.384 ; Addr[21] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.283 ; -; 15.456 ; Addr[2] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.211 ; -; 15.469 ; Addr[20] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.198 ; -; 15.505 ; Addr[23] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.162 ; -; 15.510 ; SetFWr[1] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.157 ; -; 15.817 ; Addr[18] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.850 ; -; 15.897 ; Addr[17] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.770 ; -; 16.230 ; Addr[1] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.437 ; -; 16.377 ; Addr[0] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.290 ; -; 25.936 ; REGEN ; SA[1]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 13.731 ; -; 26.182 ; REGEN ; SA[0]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 13.485 ; -; 26.524 ; REGEN ; SA[2]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 13.143 ; -; 26.906 ; Addr[23] ; SA[1]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 12.761 ; -; 27.133 ; REGEN ; RCKE~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 12.534 ; -; 27.152 ; Addr[23] ; SA[0]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 12.515 ; -; 27.487 ; REGEN ; SA[8]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 12.180 ; -; 27.494 ; Addr[23] ; SA[2]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 12.173 ; -; 27.513 ; IS.state_bit_1 ; SA[1]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 12.154 ; -; 27.759 ; IS.state_bit_1 ; SA[0]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.908 ; -; 27.761 ; REGEN ; SA[5]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.906 ; -; 27.882 ; IS.state_bit_0 ; SA[1]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.785 ; -; 27.915 ; REGEN ; SA[4]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.752 ; -; 28.015 ; IS.state_bit_1 ; RCKE~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.652 ; -; 28.101 ; IS.state_bit_1 ; SA[2]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.566 ; -; 28.103 ; Addr[23] ; RCKE~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.564 ; -; 28.107 ; PS[1] ; SA[1]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.560 ; -; 28.128 ; IS.state_bit_0 ; SA[0]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.539 ; -; 28.154 ; REGEN ; SA[6]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.513 ; -; 28.192 ; IS.state_bit_0 ; RCKE~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.475 ; -; 28.245 ; PS[1] ; SA[2]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.422 ; -; 28.350 ; REGEN ; nRCS~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.317 ; -; 28.456 ; PS[0] ; SA[1]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.211 ; -; 28.457 ; Addr[23] ; SA[8]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.210 ; -; 28.470 ; IS.state_bit_0 ; SA[2]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.197 ; -; 28.515 ; REGEN ; SA[3]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.152 ; -; 28.594 ; PS[0] ; SA[2]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.073 ; -; 28.638 ; SetFWr[0] ; SA[1]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.029 ; -; 28.731 ; Addr[23] ; SA[5]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.936 ; -; 28.806 ; LS[10] ; IS.state_bit_0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.861 ; -; 28.812 ; REGEN ; SA[7]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.855 ; -; 28.884 ; SetFWr[0] ; SA[0]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.783 ; -+--------+----------------+----------------+--------------+-------------+--------------+------------+------------+ ++-------------------------------------------------------------------------------------------------------+ +; Setup: 'C25M' ; ++--------+-----------+------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+-----------+------------+--------------+-------------+--------------+------------+------------+ +; 10.278 ; REGEN ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 9.389 ; +; 10.285 ; REGEN ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 9.382 ; +; 10.289 ; REGEN ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 9.378 ; +; 10.642 ; REGEN ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 9.025 ; +; 11.085 ; REGEN ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 8.582 ; +; 11.357 ; REGEN ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 8.310 ; +; 11.401 ; REGEN ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 8.266 ; +; 11.402 ; REGEN ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 8.265 ; +; 12.395 ; PS[0] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.272 ; +; 12.395 ; PS[0] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.272 ; +; 12.395 ; PS[0] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.272 ; +; 12.395 ; PS[0] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.272 ; +; 12.440 ; PS[0] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.227 ; +; 12.440 ; PS[0] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.227 ; +; 12.440 ; PS[0] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.227 ; +; 12.440 ; PS[0] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.227 ; +; 12.450 ; PS[3] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.217 ; +; 12.450 ; PS[3] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.217 ; +; 12.450 ; PS[3] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.217 ; +; 12.450 ; PS[3] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.217 ; +; 12.495 ; PS[3] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.172 ; +; 12.495 ; PS[3] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.172 ; +; 12.495 ; PS[3] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.172 ; +; 12.495 ; PS[3] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.172 ; +; 12.804 ; PS[2] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.863 ; +; 12.804 ; PS[2] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.863 ; +; 12.804 ; PS[2] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.863 ; +; 12.804 ; PS[2] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.863 ; +; 12.849 ; PS[2] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.818 ; +; 12.849 ; PS[2] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.818 ; +; 12.849 ; PS[2] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.818 ; +; 12.849 ; PS[2] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.818 ; +; 13.331 ; Addr[12] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.336 ; +; 13.753 ; PS[1] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.914 ; +; 13.753 ; PS[1] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.914 ; +; 13.753 ; PS[1] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.914 ; +; 13.753 ; PS[1] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.914 ; +; 13.798 ; PS[1] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.869 ; +; 13.798 ; PS[1] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.869 ; +; 13.798 ; PS[1] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.869 ; +; 13.798 ; PS[1] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.869 ; +; 13.971 ; Addr[11] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.696 ; +; 14.103 ; Addr[7] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.564 ; +; 14.314 ; Addr[15] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.353 ; +; 14.675 ; Addr[14] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.992 ; +; 14.748 ; Addr[8] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.919 ; +; 14.753 ; Addr[9] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.914 ; +; 14.779 ; SetFWr[1] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.888 ; +; 14.780 ; SetFWr[1] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.887 ; +; 14.785 ; SetFWr[1] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.882 ; +; 14.975 ; Addr[4] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.692 ; +; 15.251 ; SetFWr[1] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.416 ; +; 15.322 ; Addr[10] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.345 ; +; 15.387 ; Addr[21] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.280 ; +; 15.489 ; Addr[6] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.178 ; +; 15.612 ; Addr[17] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.055 ; +; 15.651 ; Addr[13] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.016 ; +; 15.653 ; Addr[19] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.014 ; +; 15.700 ; Addr[5] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.967 ; +; 15.911 ; Addr[16] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.756 ; +; 16.065 ; Addr[22] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.602 ; +; 16.103 ; Addr[18] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.564 ; +; 16.349 ; Addr[23] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.318 ; +; 16.647 ; Addr[0] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.020 ; +; 16.656 ; Addr[3] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.011 ; +; 16.711 ; Addr[1] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 2.956 ; +; 16.777 ; Addr[20] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 2.890 ; +; 17.105 ; Addr[2] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 2.562 ; +; 22.720 ; Addr[23] ; SA[0]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 16.947 ; +; 23.632 ; Addr[23] ; SA[2]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 16.035 ; +; 23.717 ; REGEN ; SA[0]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 15.950 ; +; 23.986 ; SetFWr[0] ; SA[0]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 15.681 ; +; 24.629 ; REGEN ; SA[2]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 15.038 ; +; 24.898 ; SetFWr[0] ; SA[2]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 14.769 ; +; 25.067 ; SetFWr[1] ; SA[0]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 14.600 ; +; 25.201 ; PS[1] ; SA[0]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 14.466 ; +; 25.277 ; Addr[23] ; SA[1]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 14.390 ; +; 25.323 ; PS[1] ; SA[2]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 14.344 ; +; 25.783 ; Addr[23] ; SA[4]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 13.884 ; +; 25.876 ; Addr[23] ; RCKE~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 13.791 ; +; 25.979 ; SetFWr[1] ; SA[2]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 13.688 ; +; 26.015 ; Addr[23] ; SA[8]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 13.652 ; +; 26.018 ; Addr[23] ; SA[3]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 13.649 ; +; 26.117 ; Addr[23] ; SA[5]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 13.550 ; +; 26.222 ; PS[1] ; Addr[10] ; C25M ; C25M ; 40.000 ; 0.000 ; 13.445 ; +; 26.222 ; PS[1] ; Addr[11] ; C25M ; C25M ; 40.000 ; 0.000 ; 13.445 ; +; 26.222 ; PS[1] ; Addr[12] ; C25M ; C25M ; 40.000 ; 0.000 ; 13.445 ; +; 26.222 ; PS[1] ; Addr[13] ; C25M ; C25M ; 40.000 ; 0.000 ; 13.445 ; +; 26.222 ; PS[1] ; Addr[14] ; C25M ; C25M ; 40.000 ; 0.000 ; 13.445 ; +; 26.222 ; PS[1] ; Addr[15] ; C25M ; C25M ; 40.000 ; 0.000 ; 13.445 ; +; 26.222 ; PS[1] ; Addr[8] ; C25M ; C25M ; 40.000 ; 0.000 ; 13.445 ; +; 26.222 ; PS[1] ; Addr[9] ; C25M ; C25M ; 40.000 ; 0.000 ; 13.445 ; +; 26.274 ; REGEN ; SA[1]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 13.393 ; +; 26.312 ; Addr[23] ; SA[6]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 13.355 ; +; 26.361 ; LS[7] ; IS.000 ; C25M ; C25M ; 40.000 ; 0.000 ; 13.306 ; +; 26.498 ; PS[0] ; SA[0]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 13.169 ; +; 26.543 ; SetFWr[0] ; SA[1]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 13.124 ; +; 26.596 ; Addr[23] ; SA[7]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 13.071 ; +; 26.722 ; PS[0] ; Addr[10] ; C25M ; C25M ; 40.000 ; 0.000 ; 12.945 ; +; 26.722 ; PS[0] ; Addr[11] ; C25M ; C25M ; 40.000 ; 0.000 ; 12.945 ; ++--------+-----------+------------+--------------+-------------+--------------+------------+------------+ -+---------------------------------------------------------------------------------------------------------------+ -; Hold: 'C25M' ; -+-------+----------------+----------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+-------+----------------+----------------+--------------+-------------+--------------+------------+------------+ -; 1.393 ; WRD[0] ; WRD[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.614 ; -; 1.400 ; PHI0r1 ; PHI0r2 ; C25M ; C25M ; 0.000 ; 0.000 ; 1.621 ; -; 1.411 ; WRD[7] ; WRD[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.632 ; -; 1.413 ; nRESf[1] ; nRESf[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.634 ; -; 1.418 ; WRD[4] ; WRD[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.639 ; -; 1.418 ; WRD[5] ; WRD[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.639 ; -; 1.420 ; WRD[1] ; WRD[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.641 ; -; 1.421 ; WRD[2] ; WRD[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.642 ; -; 1.645 ; WRD[3] ; WRD[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.866 ; -; 1.649 ; nRESout~reg0 ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 1.870 ; -; 1.661 ; REGEN ; REGEN ; C25M ; C25M ; 0.000 ; 0.000 ; 1.882 ; -; 1.695 ; PS[2] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.916 ; -; 1.734 ; PS[0] ; PS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.955 ; -; 1.778 ; WRD[3] ; WRD[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.999 ; -; 1.840 ; nRESf[2] ; nRESf[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.061 ; -; 1.930 ; Addr[15] ; AddrIncH ; C25M ; C25M ; 0.000 ; 0.000 ; 2.151 ; -; 1.939 ; Addr[7] ; AddrIncM ; C25M ; C25M ; 0.000 ; 0.000 ; 2.160 ; -; 1.944 ; nRESf[1] ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 2.165 ; -; 1.958 ; PS[3] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.179 ; -; 1.994 ; PS[1] ; PS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.215 ; -; 2.003 ; PS[1] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.224 ; -; 2.063 ; LS[13] ; LS[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.284 ; -; 2.117 ; Addr[10] ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; -; 2.117 ; Addr[1] ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; -; 2.117 ; Addr[2] ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; -; 2.117 ; Addr[9] ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; -; 2.125 ; Addr[16] ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.346 ; -; 2.125 ; Addr[8] ; Addr[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.346 ; -; 2.126 ; Addr[23] ; Addr[23] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ; -; 2.126 ; Addr[17] ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ; -; 2.127 ; LS[6] ; LS[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.348 ; -; 2.127 ; Addr[18] ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.348 ; -; 2.133 ; Addr[0] ; Addr[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.354 ; -; 2.133 ; LS[7] ; LS[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.354 ; -; 2.135 ; LS[0] ; LS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.356 ; -; 2.137 ; Addr[15] ; Addr[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.358 ; -; 2.138 ; LS[0] ; LS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.359 ; -; 2.145 ; IOROMEN ; IOROMEN ; C25M ; C25M ; 0.000 ; 0.000 ; 2.366 ; -; 2.145 ; Addr[7] ; Addr[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.366 ; -; 2.151 ; LS[8] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.372 ; -; 2.153 ; LS[9] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.374 ; -; 2.160 ; LS[4] ; LS[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.381 ; -; 2.160 ; WRD[5] ; WRD[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.381 ; -; 2.161 ; WRD[4] ; WRD[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.382 ; -; 2.166 ; PS[2] ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.387 ; -; 2.169 ; PS[2] ; MOSIout ; C25M ; C25M ; 0.000 ; 0.000 ; 2.390 ; -; 2.222 ; Addr[19] ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.443 ; -; 2.230 ; Addr[5] ; Addr[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.451 ; -; 2.230 ; Addr[21] ; Addr[21] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.451 ; -; 2.230 ; PS[0] ; FCKout ; C25M ; C25M ; 0.000 ; 0.000 ; 2.451 ; -; 2.231 ; Addr[3] ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; -; 2.231 ; Addr[4] ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; -; 2.231 ; Addr[6] ; Addr[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; -; 2.231 ; Addr[20] ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; -; 2.231 ; Addr[22] ; Addr[22] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; -; 2.232 ; Addr[11] ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.453 ; -; 2.240 ; LS[1] ; LS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.461 ; -; 2.240 ; LS[3] ; LS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.461 ; -; 2.242 ; LS[10] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.463 ; -; 2.248 ; LS[12] ; LS[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.469 ; -; 2.249 ; Addr[12] ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.470 ; -; 2.250 ; LS[11] ; LS[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.471 ; -; 2.251 ; LS[5] ; LS[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.472 ; -; 2.252 ; LS[2] ; LS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.473 ; -; 2.260 ; Addr[13] ; Addr[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.481 ; -; 2.261 ; WRD[2] ; WRD[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.482 ; -; 2.262 ; Addr[14] ; Addr[14] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.483 ; -; 2.264 ; WRD[1] ; WRD[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.485 ; -; 2.310 ; PS[0] ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.531 ; -; 2.312 ; PS[0] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.533 ; -; 2.317 ; Bank ; Bank ; C25M ; C25M ; 0.000 ; 0.000 ; 2.538 ; -; 2.319 ; IS.state_bit_0 ; IS.state_bit_0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.540 ; -; 2.333 ; IS.state_bit_0 ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.554 ; -; 2.345 ; PS[0] ; MOSIout ; C25M ; C25M ; 0.000 ; 0.000 ; 2.566 ; -; 2.448 ; WRD[6] ; WRD[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.669 ; -; 2.521 ; nRESf[3] ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 2.742 ; -; 2.531 ; IS.state_bit_1 ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.752 ; -; 2.660 ; PS[1] ; nCAS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.881 ; -; 2.673 ; nRESf[2] ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 2.894 ; -; 2.708 ; PS[2] ; nCAS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.929 ; -; 2.709 ; PS[0] ; nSWE~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.930 ; -; 2.753 ; IS.state_bit_1 ; IS.state_bit_0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.974 ; -; 2.782 ; PS[0] ; nCAS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.003 ; -; 2.829 ; PS[0] ; nRAS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.050 ; -; 2.949 ; Addr[9] ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; -; 2.949 ; Addr[10] ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; -; 2.949 ; Addr[1] ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; -; 2.949 ; Addr[2] ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; -; 2.957 ; Addr[16] ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.178 ; -; 2.957 ; Addr[8] ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.178 ; -; 2.958 ; Addr[17] ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.179 ; -; 2.959 ; Addr[18] ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.180 ; -; 2.965 ; Addr[0] ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.186 ; -; 2.965 ; LS[7] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.186 ; -; 2.983 ; LS[8] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.204 ; -; 2.985 ; LS[9] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.206 ; -; 2.992 ; LS[4] ; LS[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.213 ; -; 3.034 ; Addr[0] ; DQMH~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.255 ; -; 3.060 ; Addr[10] ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ; -; 3.060 ; Addr[2] ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ; -+-------+----------------+----------------+--------------+-------------+--------------+------------+------------+ ++-----------------------------------------------------------------------------------------------------------+ +; Hold: 'C25M' ; ++-------+--------------+--------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+--------------+--------------+--------------+-------------+--------------+------------+------------+ +; 1.376 ; PHI0r1 ; PHI0r2 ; C25M ; C25M ; 0.000 ; 0.000 ; 1.597 ; +; 1.412 ; nRESf[1] ; nRESf[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.633 ; +; 1.412 ; WRD[7] ; WRD[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.633 ; +; 1.419 ; WRD[4] ; WRD[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.640 ; +; 1.420 ; WRD[0] ; WRD[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.641 ; +; 1.426 ; nRESf[2] ; nRESf[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.647 ; +; 1.429 ; nRESf[0] ; nRESf[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.650 ; +; 1.646 ; WRD[2] ; WRD[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.867 ; +; 1.649 ; nRESout~reg0 ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 1.870 ; +; 1.652 ; WRD[5] ; WRD[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.873 ; +; 1.653 ; WRD[3] ; WRD[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.874 ; +; 1.661 ; Bank ; Bank ; C25M ; C25M ; 0.000 ; 0.000 ; 1.882 ; +; 1.664 ; Addr[19] ; SA[9]~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 1.885 ; +; 1.670 ; IS.000 ; FCKOE ; C25M ; C25M ; 0.000 ; 0.000 ; 1.891 ; +; 1.675 ; LS[0] ; LS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.896 ; +; 1.719 ; PS[0] ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.940 ; +; 1.720 ; PS[2] ; MOSIout ; C25M ; C25M ; 0.000 ; 0.000 ; 1.941 ; +; 1.793 ; WRD[2] ; WRD[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.014 ; +; 1.794 ; WRD[3] ; WRD[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.015 ; +; 1.806 ; WRD[6] ; WRD[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.027 ; +; 1.809 ; IS.101 ; MOSIOE ; C25M ; C25M ; 0.000 ; 0.000 ; 2.030 ; +; 1.846 ; WRD[1] ; WRD[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.067 ; +; 1.942 ; Addr[21] ; SA[11]~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.163 ; +; 1.948 ; nRESf[2] ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 2.169 ; +; 2.048 ; nRESf[1] ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 2.269 ; +; 2.063 ; LS[13] ; LS[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.284 ; +; 2.082 ; Addr[15] ; AddrIncH ; C25M ; C25M ; 0.000 ; 0.000 ; 2.303 ; +; 2.107 ; LS[7] ; LS[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.328 ; +; 2.115 ; Addr[0] ; DQML~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.336 ; +; 2.116 ; Addr[0] ; Addr[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.337 ; +; 2.116 ; Addr[16] ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.337 ; +; 2.117 ; Addr[23] ; Addr[23] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; +; 2.117 ; Addr[10] ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; +; 2.117 ; Addr[7] ; Addr[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; +; 2.117 ; Addr[17] ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; +; 2.117 ; Addr[18] ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; +; 2.117 ; Addr[9] ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; +; 2.125 ; Addr[8] ; Addr[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.346 ; +; 2.126 ; Addr[1] ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ; +; 2.126 ; Addr[15] ; Addr[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ; +; 2.127 ; Addr[2] ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.348 ; +; 2.128 ; nRESf[3] ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 2.349 ; +; 2.137 ; IS.111 ; IS.111 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.358 ; +; 2.144 ; LS[4] ; LS[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.365 ; +; 2.145 ; LS[6] ; LS[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.366 ; +; 2.149 ; REGEN ; REGEN ; C25M ; C25M ; 0.000 ; 0.000 ; 2.370 ; +; 2.150 ; LS[0] ; LS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.371 ; +; 2.151 ; LS[8] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.372 ; +; 2.153 ; LS[9] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.374 ; +; 2.185 ; PS[2] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.406 ; +; 2.188 ; PS[2] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.409 ; +; 2.232 ; Addr[11] ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.453 ; +; 2.232 ; Addr[3] ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.453 ; +; 2.232 ; Addr[19] ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.453 ; +; 2.239 ; Addr[22] ; Addr[22] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.460 ; +; 2.240 ; Addr[20] ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.461 ; +; 2.241 ; PS[0] ; RCKE~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.462 ; +; 2.242 ; LS[10] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.463 ; +; 2.249 ; Addr[12] ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.470 ; +; 2.249 ; Addr[21] ; Addr[21] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.470 ; +; 2.250 ; Addr[4] ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.471 ; +; 2.250 ; Addr[5] ; Addr[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.471 ; +; 2.251 ; LS[5] ; LS[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.472 ; +; 2.252 ; PS[1] ; PS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.473 ; +; 2.259 ; LS[11] ; LS[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.480 ; +; 2.261 ; Addr[13] ; Addr[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.482 ; +; 2.261 ; Addr[14] ; Addr[14] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.482 ; +; 2.263 ; WRD[5] ; WRD[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.484 ; +; 2.264 ; nRESf[0] ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 2.485 ; +; 2.264 ; WRD[4] ; WRD[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.485 ; +; 2.267 ; WRD[0] ; WRD[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.488 ; +; 2.270 ; LS[2] ; LS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.491 ; +; 2.271 ; LS[12] ; LS[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.492 ; +; 2.272 ; SetFWLoaded ; SetFWr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.493 ; +; 2.272 ; LS[3] ; LS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.493 ; +; 2.272 ; SetFWLoaded ; SetFWr[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.493 ; +; 2.274 ; LS[1] ; LS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.495 ; +; 2.276 ; IOROMEN ; IOROMEN ; C25M ; C25M ; 0.000 ; 0.000 ; 2.497 ; +; 2.287 ; PS[3] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.508 ; +; 2.573 ; Addr[6] ; Addr[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.794 ; +; 2.686 ; WRD[1] ; WRD[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.907 ; +; 2.690 ; Addr[0] ; DQMH~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.911 ; +; 2.902 ; PS[0] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.123 ; +; 2.906 ; PS[0] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.127 ; +; 2.939 ; LS[7] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.160 ; +; 2.948 ; Addr[0] ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.169 ; +; 2.948 ; Addr[16] ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.169 ; +; 2.949 ; Addr[9] ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; +; 2.949 ; Addr[10] ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; +; 2.949 ; Addr[17] ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; +; 2.949 ; Addr[18] ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; +; 2.957 ; Addr[8] ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.178 ; +; 2.958 ; Addr[1] ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.179 ; +; 2.959 ; Addr[2] ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.180 ; +; 2.976 ; LS[4] ; LS[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.197 ; +; 2.983 ; LS[8] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.204 ; +; 2.985 ; LS[9] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.206 ; +; 3.001 ; PHI0r1 ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.222 ; +; 3.050 ; LS[7] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.271 ; +; 3.059 ; Addr[16] ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.280 ; ++-------+--------------+--------------+--------------+-------------+--------------+------------+------------+ +-----------------------------------------------------------------------------------------------------+ @@ -383,35 +383,35 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +--------+-----------+----------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+-----------+----------+--------------+-------------+--------------+------------+------------+ -; 33.300 ; nRESr ; Addr[0] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.367 ; -; 33.300 ; nRESr ; REGEN ; C25M ; C25M ; 40.000 ; 0.000 ; 6.367 ; -; 33.300 ; nRESr ; Addr[23] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.367 ; -; 33.300 ; nRESr ; Addr[10] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.367 ; -; 33.300 ; nRESr ; Addr[1] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.367 ; -; 33.300 ; nRESr ; Addr[11] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.367 ; -; 33.300 ; nRESr ; Addr[2] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.367 ; -; 33.300 ; nRESr ; Addr[12] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.367 ; -; 33.300 ; nRESr ; Bank ; C25M ; C25M ; 40.000 ; 0.000 ; 6.367 ; -; 33.300 ; nRESr ; Addr[3] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.367 ; -; 33.300 ; nRESr ; Addr[13] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.367 ; -; 33.300 ; nRESr ; Addr[4] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.367 ; -; 33.300 ; nRESr ; Addr[14] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.367 ; -; 33.300 ; nRESr ; Addr[5] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.367 ; -; 33.300 ; nRESr ; Addr[15] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.367 ; -; 33.300 ; nRESr ; Addr[6] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.367 ; -; 33.300 ; nRESr ; Addr[16] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.367 ; -; 33.300 ; nRESr ; Addr[7] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.367 ; -; 33.300 ; nRESr ; Addr[17] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.367 ; -; 33.300 ; nRESr ; Addr[8] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.367 ; -; 33.300 ; nRESr ; Addr[18] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.367 ; -; 33.300 ; nRESr ; Addr[9] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.367 ; -; 33.300 ; nRESr ; Addr[19] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.367 ; -; 33.300 ; nRESr ; Addr[20] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.367 ; -; 33.300 ; nRESr ; Addr[21] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.367 ; -; 33.300 ; nRESr ; Addr[22] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.367 ; -; 33.300 ; nRESr ; AddrIncH ; C25M ; C25M ; 40.000 ; 0.000 ; 6.367 ; -; 33.300 ; nRESr ; AddrIncM ; C25M ; C25M ; 40.000 ; 0.000 ; 6.367 ; -; 33.300 ; nRESr ; AddrIncL ; C25M ; C25M ; 40.000 ; 0.000 ; 6.367 ; +; 33.311 ; nRESr ; Addr[0] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ; +; 33.311 ; nRESr ; REGEN ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ; +; 33.311 ; nRESr ; Addr[23] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ; +; 33.311 ; nRESr ; Addr[10] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ; +; 33.311 ; nRESr ; Addr[1] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ; +; 33.311 ; nRESr ; Addr[11] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ; +; 33.311 ; nRESr ; Addr[2] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ; +; 33.311 ; nRESr ; Addr[12] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ; +; 33.311 ; nRESr ; Bank ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ; +; 33.311 ; nRESr ; Addr[3] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ; +; 33.311 ; nRESr ; Addr[13] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ; +; 33.311 ; nRESr ; Addr[4] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ; +; 33.311 ; nRESr ; Addr[14] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ; +; 33.311 ; nRESr ; Addr[5] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ; +; 33.311 ; nRESr ; Addr[15] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ; +; 33.311 ; nRESr ; Addr[6] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ; +; 33.311 ; nRESr ; Addr[16] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ; +; 33.311 ; nRESr ; Addr[7] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ; +; 33.311 ; nRESr ; Addr[17] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ; +; 33.311 ; nRESr ; Addr[8] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ; +; 33.311 ; nRESr ; Addr[18] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ; +; 33.311 ; nRESr ; Addr[9] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ; +; 33.311 ; nRESr ; Addr[19] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ; +; 33.311 ; nRESr ; Addr[20] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ; +; 33.311 ; nRESr ; Addr[21] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ; +; 33.311 ; nRESr ; Addr[22] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ; +; 33.311 ; nRESr ; AddrIncH ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ; +; 33.311 ; nRESr ; AddrIncM ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ; +; 33.311 ; nRESr ; AddrIncL ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ; +--------+-----------+----------+--------------+-------------+--------------+------------+------------+ @@ -420,917 +420,44 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+-----------+----------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +-------+-----------+----------+--------------+-------------+--------------+------------+------------+ -; 6.146 ; nRESr ; Addr[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.367 ; -; 6.146 ; nRESr ; REGEN ; C25M ; C25M ; 0.000 ; 0.000 ; 6.367 ; -; 6.146 ; nRESr ; Addr[23] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.367 ; -; 6.146 ; nRESr ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.367 ; -; 6.146 ; nRESr ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.367 ; -; 6.146 ; nRESr ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.367 ; -; 6.146 ; nRESr ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.367 ; -; 6.146 ; nRESr ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.367 ; -; 6.146 ; nRESr ; Bank ; C25M ; C25M ; 0.000 ; 0.000 ; 6.367 ; -; 6.146 ; nRESr ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.367 ; -; 6.146 ; nRESr ; Addr[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.367 ; -; 6.146 ; nRESr ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.367 ; -; 6.146 ; nRESr ; Addr[14] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.367 ; -; 6.146 ; nRESr ; Addr[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.367 ; -; 6.146 ; nRESr ; Addr[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.367 ; -; 6.146 ; nRESr ; Addr[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.367 ; -; 6.146 ; nRESr ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.367 ; -; 6.146 ; nRESr ; Addr[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.367 ; -; 6.146 ; nRESr ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.367 ; -; 6.146 ; nRESr ; Addr[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.367 ; -; 6.146 ; nRESr ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.367 ; -; 6.146 ; nRESr ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.367 ; -; 6.146 ; nRESr ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.367 ; -; 6.146 ; nRESr ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.367 ; -; 6.146 ; nRESr ; Addr[21] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.367 ; -; 6.146 ; nRESr ; Addr[22] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.367 ; -; 6.146 ; nRESr ; AddrIncH ; C25M ; C25M ; 0.000 ; 0.000 ; 6.367 ; -; 6.146 ; nRESr ; AddrIncM ; C25M ; C25M ; 0.000 ; 0.000 ; 6.367 ; -; 6.146 ; nRESr ; AddrIncL ; C25M ; C25M ; 0.000 ; 0.000 ; 6.367 ; +; 6.135 ; nRESr ; Addr[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ; +; 6.135 ; nRESr ; REGEN ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ; +; 6.135 ; nRESr ; Addr[23] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ; +; 6.135 ; nRESr ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ; +; 6.135 ; nRESr ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ; +; 6.135 ; nRESr ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ; +; 6.135 ; nRESr ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ; +; 6.135 ; nRESr ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ; +; 6.135 ; nRESr ; Bank ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ; +; 6.135 ; nRESr ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ; +; 6.135 ; nRESr ; Addr[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ; +; 6.135 ; nRESr ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ; +; 6.135 ; nRESr ; Addr[14] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ; +; 6.135 ; nRESr ; Addr[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ; +; 6.135 ; nRESr ; Addr[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ; +; 6.135 ; nRESr ; Addr[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ; +; 6.135 ; nRESr ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ; +; 6.135 ; nRESr ; Addr[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ; +; 6.135 ; nRESr ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ; +; 6.135 ; nRESr ; Addr[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ; +; 6.135 ; nRESr ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ; +; 6.135 ; nRESr ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ; +; 6.135 ; nRESr ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ; +; 6.135 ; nRESr ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ; +; 6.135 ; nRESr ; Addr[21] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ; +; 6.135 ; nRESr ; Addr[22] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ; +; 6.135 ; nRESr ; AddrIncH ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ; +; 6.135 ; nRESr ; AddrIncM ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ; +; 6.135 ; nRESr ; AddrIncL ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ; +-------+-----------+----------+--------------+-------------+--------------+------------+------------+ -+-------------------------------------------------------------------------------------------------+ -; Minimum Pulse Width: 'C25M' ; -+--------+--------------+----------------+------------------+-------+------------+----------------+ -; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; -+--------+--------------+----------------+------------------+-------+------------+----------------+ -; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; AddrIncH ; -; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; AddrIncH ; -; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; AddrIncL ; -; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; AddrIncL ; -; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; AddrIncM ; -; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; AddrIncM ; -; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[0] ; -; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[0] ; -; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[10] ; -; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[10] ; -; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[11] ; -; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[11] ; -; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[12] ; -; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[12] ; -; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[13] ; -; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[13] ; -; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[14] ; -; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[14] ; -; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[15] ; -; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[15] ; -; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[16] ; -; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[16] ; -; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[17] ; -; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[17] ; -; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[18] ; -; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[18] ; -; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[19] ; -; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[19] ; -; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[1] ; -; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[1] ; -; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[20] ; -; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[20] ; -; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[21] ; -; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[21] ; -; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[22] ; -; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[22] ; -; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[23] ; -; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[23] ; -; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[2] ; -; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[2] ; -; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[3] ; -; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[3] ; -; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[4] ; -; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[4] ; -; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[5] ; -; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[5] ; -; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[6] ; -; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[6] ; -; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[7] ; -; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[7] ; -; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[8] ; -; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[8] ; -; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[9] ; -; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[9] ; -; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Bank ; -; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Bank ; -; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; DQMH~reg0 ; -; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; DQMH~reg0 ; -; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; DQML~reg0 ; -; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; DQML~reg0 ; -; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; FCKOE ; -; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; FCKOE ; -; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; FCKout ; -; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; FCKout ; -; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; FCS ; -; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; FCS ; -; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; IOROMEN ; -; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; IOROMEN ; -; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; IS.state_bit_0 ; -; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; IS.state_bit_0 ; -; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; IS.state_bit_1 ; -; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; IS.state_bit_1 ; -; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; IS.state_bit_2 ; -; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; IS.state_bit_2 ; -; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[0] ; -; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[0] ; -; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[10] ; -; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[10] ; -; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[11] ; -; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[11] ; -; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[12] ; -; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[12] ; -; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[13] ; -; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[13] ; -; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[1] ; -; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[1] ; -; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[2] ; -; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[2] ; -; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[3] ; -; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[3] ; -; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[4] ; -; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[4] ; -; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[5] ; -; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[5] ; -; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[6] ; -; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[6] ; -; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[7] ; -; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[7] ; -; 19.734 ; 20.000 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[8] ; -; 19.734 ; 20.000 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[8] ; -+--------+--------------+----------------+------------------+-------+------------+----------------+ - - -+------------------------------------------------------------------------------------------------+ -; Minimum Pulse Width: 'PHI0' ; -+---------+--------------+----------------+------------------+-------+------------+--------------+ -; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; -+---------+--------------+----------------+------------------+-------+------------+--------------+ -; 488.734 ; 489.000 ; 0.266 ; High Pulse Width ; PHI0 ; Rise ; CXXXr ; -; 488.734 ; 489.000 ; 0.266 ; Low Pulse Width ; PHI0 ; Rise ; CXXXr ; -; 488.734 ; 489.000 ; 0.266 ; High Pulse Width ; PHI0 ; Rise ; RAr[0] ; -; 488.734 ; 489.000 ; 0.266 ; Low Pulse Width ; PHI0 ; Rise ; RAr[0] ; -; 488.734 ; 489.000 ; 0.266 ; High Pulse Width ; PHI0 ; Rise ; RAr[10] ; -; 488.734 ; 489.000 ; 0.266 ; Low Pulse Width ; PHI0 ; Rise ; RAr[10] ; -; 488.734 ; 489.000 ; 0.266 ; High Pulse Width ; PHI0 ; Rise ; RAr[11] ; -; 488.734 ; 489.000 ; 0.266 ; Low Pulse Width ; PHI0 ; Rise ; RAr[11] ; -; 488.734 ; 489.000 ; 0.266 ; High Pulse Width ; PHI0 ; Rise ; RAr[1] ; -; 488.734 ; 489.000 ; 0.266 ; Low Pulse Width ; PHI0 ; Rise ; RAr[1] ; -; 488.734 ; 489.000 ; 0.266 ; High Pulse Width ; PHI0 ; Rise ; RAr[2] ; -; 488.734 ; 489.000 ; 0.266 ; Low Pulse Width ; PHI0 ; Rise ; RAr[2] ; -; 488.734 ; 489.000 ; 0.266 ; High Pulse Width ; PHI0 ; Rise ; RAr[3] ; -; 488.734 ; 489.000 ; 0.266 ; Low Pulse Width ; PHI0 ; Rise ; RAr[3] ; -; 488.734 ; 489.000 ; 0.266 ; High Pulse Width ; PHI0 ; Rise ; RAr[4] ; -; 488.734 ; 489.000 ; 0.266 ; Low Pulse Width ; PHI0 ; Rise ; RAr[4] ; -; 488.734 ; 489.000 ; 0.266 ; High Pulse Width ; PHI0 ; Rise ; RAr[5] ; -; 488.734 ; 489.000 ; 0.266 ; Low Pulse Width ; PHI0 ; Rise ; RAr[5] ; -; 488.734 ; 489.000 ; 0.266 ; High Pulse Width ; PHI0 ; Rise ; RAr[6] ; -; 488.734 ; 489.000 ; 0.266 ; Low Pulse Width ; PHI0 ; Rise ; RAr[6] ; -; 488.734 ; 489.000 ; 0.266 ; High Pulse Width ; PHI0 ; Rise ; RAr[7] ; -; 488.734 ; 489.000 ; 0.266 ; Low Pulse Width ; PHI0 ; Rise ; RAr[7] ; -; 488.734 ; 489.000 ; 0.266 ; High Pulse Width ; PHI0 ; Rise ; RAr[8] ; -; 488.734 ; 489.000 ; 0.266 ; Low Pulse Width ; PHI0 ; Rise ; RAr[8] ; -; 488.734 ; 489.000 ; 0.266 ; High Pulse Width ; PHI0 ; Rise ; RAr[9] ; -; 488.734 ; 489.000 ; 0.266 ; Low Pulse Width ; PHI0 ; Rise ; RAr[9] ; -; 488.734 ; 489.000 ; 0.266 ; High Pulse Width ; PHI0 ; Rise ; nWEr ; -; 488.734 ; 489.000 ; 0.266 ; Low Pulse Width ; PHI0 ; Rise ; nWEr ; -; 489.000 ; 489.000 ; 0.000 ; High Pulse Width ; PHI0 ; Rise ; CXXXr|clk ; -; 489.000 ; 489.000 ; 0.000 ; Low Pulse Width ; PHI0 ; Rise ; CXXXr|clk ; -; 489.000 ; 489.000 ; 0.000 ; High Pulse Width ; PHI0 ; Rise ; PHI0|combout ; -; 489.000 ; 489.000 ; 0.000 ; Low Pulse Width ; PHI0 ; Rise ; PHI0|combout ; -; 489.000 ; 489.000 ; 0.000 ; High Pulse Width ; PHI0 ; Rise ; RAr[0]|clk ; -; 489.000 ; 489.000 ; 0.000 ; Low Pulse Width ; PHI0 ; Rise ; RAr[0]|clk ; -; 489.000 ; 489.000 ; 0.000 ; High Pulse Width ; PHI0 ; Rise ; RAr[10]|clk ; -; 489.000 ; 489.000 ; 0.000 ; Low Pulse Width ; PHI0 ; Rise ; RAr[10]|clk ; -; 489.000 ; 489.000 ; 0.000 ; High Pulse Width ; PHI0 ; Rise ; RAr[11]|clk ; -; 489.000 ; 489.000 ; 0.000 ; Low Pulse Width ; PHI0 ; Rise ; RAr[11]|clk ; -; 489.000 ; 489.000 ; 0.000 ; High Pulse Width ; PHI0 ; Rise ; RAr[1]|clk ; -; 489.000 ; 489.000 ; 0.000 ; Low Pulse Width ; PHI0 ; Rise ; RAr[1]|clk ; -; 489.000 ; 489.000 ; 0.000 ; High Pulse Width ; PHI0 ; Rise ; RAr[2]|clk ; -; 489.000 ; 489.000 ; 0.000 ; Low Pulse Width ; PHI0 ; Rise ; RAr[2]|clk ; -; 489.000 ; 489.000 ; 0.000 ; High Pulse Width ; PHI0 ; Rise ; RAr[3]|clk ; -; 489.000 ; 489.000 ; 0.000 ; Low Pulse Width ; PHI0 ; Rise ; RAr[3]|clk ; -; 489.000 ; 489.000 ; 0.000 ; High Pulse Width ; PHI0 ; Rise ; RAr[4]|clk ; -; 489.000 ; 489.000 ; 0.000 ; Low Pulse Width ; PHI0 ; Rise ; RAr[4]|clk ; -; 489.000 ; 489.000 ; 0.000 ; High Pulse Width ; PHI0 ; Rise ; RAr[5]|clk ; -; 489.000 ; 489.000 ; 0.000 ; Low Pulse Width ; PHI0 ; Rise ; RAr[5]|clk ; -; 489.000 ; 489.000 ; 0.000 ; High Pulse Width ; PHI0 ; Rise ; RAr[6]|clk ; -; 489.000 ; 489.000 ; 0.000 ; Low Pulse Width ; PHI0 ; Rise ; RAr[6]|clk ; -; 489.000 ; 489.000 ; 0.000 ; High Pulse Width ; PHI0 ; Rise ; RAr[7]|clk ; -; 489.000 ; 489.000 ; 0.000 ; Low Pulse Width ; PHI0 ; Rise ; RAr[7]|clk ; -; 489.000 ; 489.000 ; 0.000 ; High Pulse Width ; PHI0 ; Rise ; RAr[8]|clk ; -; 489.000 ; 489.000 ; 0.000 ; Low Pulse Width ; PHI0 ; Rise ; RAr[8]|clk ; -; 489.000 ; 489.000 ; 0.000 ; High Pulse Width ; PHI0 ; Rise ; RAr[9]|clk ; -; 489.000 ; 489.000 ; 0.000 ; Low Pulse Width ; PHI0 ; Rise ; RAr[9]|clk ; -; 489.000 ; 489.000 ; 0.000 ; High Pulse Width ; PHI0 ; Rise ; nWEr|clk ; -; 489.000 ; 489.000 ; 0.000 ; Low Pulse Width ; PHI0 ; Rise ; nWEr|clk ; -; 974.000 ; 978.000 ; 4.000 ; Port Rate ; PHI0 ; Rise ; PHI0 ; -+---------+--------------+----------------+------------------+-------+------------+--------------+ - - -+-------------------------------------------------------------------------+ -; Setup Times ; -+-----------+------------+--------+--------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-----------+------------+--------+--------+------------+-----------------+ -; MISO ; C25M ; 4.863 ; 4.863 ; Rise ; C25M ; -; MOSI ; C25M ; 3.316 ; 3.316 ; Rise ; C25M ; -; RD[*] ; C25M ; 6.278 ; 6.278 ; Rise ; C25M ; -; RD[0] ; C25M ; 4.055 ; 4.055 ; Rise ; C25M ; -; RD[1] ; C25M ; 3.822 ; 3.822 ; Rise ; C25M ; -; RD[2] ; C25M ; 3.312 ; 3.312 ; Rise ; C25M ; -; RD[3] ; C25M ; 3.974 ; 3.974 ; Rise ; C25M ; -; RD[4] ; C25M ; 3.441 ; 3.441 ; Rise ; C25M ; -; RD[5] ; C25M ; 3.969 ; 3.969 ; Rise ; C25M ; -; RD[6] ; C25M ; 6.278 ; 6.278 ; Rise ; C25M ; -; RD[7] ; C25M ; 4.093 ; 4.093 ; Rise ; C25M ; -; SetFW[*] ; C25M ; 4.149 ; 4.149 ; Rise ; C25M ; -; SetFW[0] ; C25M ; 4.149 ; 4.149 ; Rise ; C25M ; -; SetFW[1] ; C25M ; 3.738 ; 3.738 ; Rise ; C25M ; -; nDEVSEL ; C25M ; 9.957 ; 9.957 ; Rise ; C25M ; -; nIOSEL ; C25M ; 4.637 ; 4.637 ; Rise ; C25M ; -; nIOSTRB ; C25M ; 5.052 ; 5.052 ; Rise ; C25M ; -; nRES ; C25M ; 3.763 ; 3.763 ; Rise ; C25M ; -; SD[*] ; C25M ; 5.269 ; 5.269 ; Fall ; C25M ; -; SD[0] ; C25M ; 4.676 ; 4.676 ; Fall ; C25M ; -; SD[1] ; C25M ; 4.064 ; 4.064 ; Fall ; C25M ; -; SD[2] ; C25M ; 3.916 ; 3.916 ; Fall ; C25M ; -; SD[3] ; C25M ; 5.158 ; 5.158 ; Fall ; C25M ; -; SD[4] ; C25M ; 3.719 ; 3.719 ; Fall ; C25M ; -; SD[5] ; C25M ; 3.149 ; 3.149 ; Fall ; C25M ; -; SD[6] ; C25M ; 3.295 ; 3.295 ; Fall ; C25M ; -; SD[7] ; C25M ; 5.269 ; 5.269 ; Fall ; C25M ; -; RA[*] ; PHI0 ; 0.892 ; 0.892 ; Rise ; PHI0 ; -; RA[0] ; PHI0 ; 0.414 ; 0.414 ; Rise ; PHI0 ; -; RA[1] ; PHI0 ; 0.713 ; 0.713 ; Rise ; PHI0 ; -; RA[2] ; PHI0 ; 0.008 ; 0.008 ; Rise ; PHI0 ; -; RA[3] ; PHI0 ; 0.464 ; 0.464 ; Rise ; PHI0 ; -; RA[4] ; PHI0 ; -0.520 ; -0.520 ; Rise ; PHI0 ; -; RA[5] ; PHI0 ; 0.727 ; 0.727 ; Rise ; PHI0 ; -; RA[6] ; PHI0 ; -0.603 ; -0.603 ; Rise ; PHI0 ; -; RA[7] ; PHI0 ; -0.772 ; -0.772 ; Rise ; PHI0 ; -; RA[8] ; PHI0 ; -1.522 ; -1.522 ; Rise ; PHI0 ; -; RA[9] ; PHI0 ; -1.478 ; -1.478 ; Rise ; PHI0 ; -; RA[10] ; PHI0 ; 0.892 ; 0.892 ; Rise ; PHI0 ; -; RA[11] ; PHI0 ; -0.105 ; -0.105 ; Rise ; PHI0 ; -; RA[12] ; PHI0 ; -0.073 ; -0.073 ; Rise ; PHI0 ; -; RA[13] ; PHI0 ; -0.133 ; -0.133 ; Rise ; PHI0 ; -; RA[14] ; PHI0 ; -0.434 ; -0.434 ; Rise ; PHI0 ; -; RA[15] ; PHI0 ; 0.054 ; 0.054 ; Rise ; PHI0 ; -; nWE ; PHI0 ; 1.076 ; 1.076 ; Rise ; PHI0 ; -+-----------+------------+--------+--------+------------+-----------------+ - - -+-------------------------------------------------------------------------+ -; Hold Times ; -+-----------+------------+--------+--------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-----------+------------+--------+--------+------------+-----------------+ -; MISO ; C25M ; -4.309 ; -4.309 ; Rise ; C25M ; -; MOSI ; C25M ; -2.762 ; -2.762 ; Rise ; C25M ; -; RD[*] ; C25M ; -1.878 ; -1.878 ; Rise ; C25M ; -; RD[0] ; C25M ; -2.106 ; -2.106 ; Rise ; C25M ; -; RD[1] ; C25M ; -2.899 ; -2.899 ; Rise ; C25M ; -; RD[2] ; C25M ; -1.911 ; -1.911 ; Rise ; C25M ; -; RD[3] ; C25M ; -2.031 ; -2.031 ; Rise ; C25M ; -; RD[4] ; C25M ; -2.065 ; -2.065 ; Rise ; C25M ; -; RD[5] ; C25M ; -1.878 ; -1.878 ; Rise ; C25M ; -; RD[6] ; C25M ; -2.052 ; -2.052 ; Rise ; C25M ; -; RD[7] ; C25M ; -1.899 ; -1.899 ; Rise ; C25M ; -; SetFW[*] ; C25M ; -3.184 ; -3.184 ; Rise ; C25M ; -; SetFW[0] ; C25M ; -3.595 ; -3.595 ; Rise ; C25M ; -; SetFW[1] ; C25M ; -3.184 ; -3.184 ; Rise ; C25M ; -; nDEVSEL ; C25M ; -4.698 ; -4.698 ; Rise ; C25M ; -; nIOSEL ; C25M ; -4.076 ; -4.076 ; Rise ; C25M ; -; nIOSTRB ; C25M ; -3.232 ; -3.232 ; Rise ; C25M ; -; nRES ; C25M ; -3.209 ; -3.209 ; Rise ; C25M ; -; SD[*] ; C25M ; -2.595 ; -2.595 ; Fall ; C25M ; -; SD[0] ; C25M ; -4.122 ; -4.122 ; Fall ; C25M ; -; SD[1] ; C25M ; -3.510 ; -3.510 ; Fall ; C25M ; -; SD[2] ; C25M ; -3.362 ; -3.362 ; Fall ; C25M ; -; SD[3] ; C25M ; -4.604 ; -4.604 ; Fall ; C25M ; -; SD[4] ; C25M ; -3.165 ; -3.165 ; Fall ; C25M ; -; SD[5] ; C25M ; -2.595 ; -2.595 ; Fall ; C25M ; -; SD[6] ; C25M ; -2.741 ; -2.741 ; Fall ; C25M ; -; SD[7] ; C25M ; -4.715 ; -4.715 ; Fall ; C25M ; -; RA[*] ; PHI0 ; 2.076 ; 2.076 ; Rise ; PHI0 ; -; RA[0] ; PHI0 ; 0.140 ; 0.140 ; Rise ; PHI0 ; -; RA[1] ; PHI0 ; -0.159 ; -0.159 ; Rise ; PHI0 ; -; RA[2] ; PHI0 ; 0.546 ; 0.546 ; Rise ; PHI0 ; -; RA[3] ; PHI0 ; 0.090 ; 0.090 ; Rise ; PHI0 ; -; RA[4] ; PHI0 ; 1.074 ; 1.074 ; Rise ; PHI0 ; -; RA[5] ; PHI0 ; -0.173 ; -0.173 ; Rise ; PHI0 ; -; RA[6] ; PHI0 ; 1.157 ; 1.157 ; Rise ; PHI0 ; -; RA[7] ; PHI0 ; 1.326 ; 1.326 ; Rise ; PHI0 ; -; RA[8] ; PHI0 ; 2.076 ; 2.076 ; Rise ; PHI0 ; -; RA[9] ; PHI0 ; 2.032 ; 2.032 ; Rise ; PHI0 ; -; RA[10] ; PHI0 ; -0.338 ; -0.338 ; Rise ; PHI0 ; -; RA[11] ; PHI0 ; 0.659 ; 0.659 ; Rise ; PHI0 ; -; RA[12] ; PHI0 ; 0.627 ; 0.627 ; Rise ; PHI0 ; -; RA[13] ; PHI0 ; 0.687 ; 0.687 ; Rise ; PHI0 ; -; RA[14] ; PHI0 ; 0.988 ; 0.988 ; Rise ; PHI0 ; -; RA[15] ; PHI0 ; 0.500 ; 0.500 ; Rise ; PHI0 ; -; nWE ; PHI0 ; -0.522 ; -0.522 ; Rise ; PHI0 ; -+-----------+------------+--------+--------+------------+-----------------+ - - -+-------------------------------------------------------------------------+ -; Clock to Output Times ; -+-----------+------------+--------+--------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-----------+------------+--------+--------+------------+-----------------+ -; DQMH ; C25M ; 17.381 ; 17.381 ; Rise ; C25M ; -; DQML ; C25M ; 17.650 ; 17.650 ; Rise ; C25M ; -; FCK ; C25M ; 17.362 ; 17.362 ; Rise ; C25M ; -; MOSI ; C25M ; 17.251 ; 17.251 ; Rise ; C25M ; -; RCKE ; C25M ; 17.169 ; 17.169 ; Rise ; C25M ; -; RDdir ; C25M ; 23.995 ; 23.995 ; Rise ; C25M ; -; SA[*] ; C25M ; 18.571 ; 18.571 ; Rise ; C25M ; -; SA[0] ; C25M ; 15.989 ; 15.989 ; Rise ; C25M ; -; SA[1] ; C25M ; 17.051 ; 17.051 ; Rise ; C25M ; -; SA[2] ; C25M ; 17.460 ; 17.460 ; Rise ; C25M ; -; SA[3] ; C25M ; 18.571 ; 18.571 ; Rise ; C25M ; -; SA[4] ; C25M ; 17.861 ; 17.861 ; Rise ; C25M ; -; SA[5] ; C25M ; 17.846 ; 17.846 ; Rise ; C25M ; -; SA[6] ; C25M ; 17.924 ; 17.924 ; Rise ; C25M ; -; SA[7] ; C25M ; 17.771 ; 17.771 ; Rise ; C25M ; -; SA[8] ; C25M ; 17.826 ; 17.826 ; Rise ; C25M ; -; SA[9] ; C25M ; 17.029 ; 17.029 ; Rise ; C25M ; -; SA[10] ; C25M ; 17.820 ; 17.820 ; Rise ; C25M ; -; SA[11] ; C25M ; 17.097 ; 17.097 ; Rise ; C25M ; -; SA[12] ; C25M ; 18.520 ; 18.520 ; Rise ; C25M ; -; SBA[*] ; C25M ; 18.530 ; 18.530 ; Rise ; C25M ; -; SBA[0] ; C25M ; 17.892 ; 17.892 ; Rise ; C25M ; -; SBA[1] ; C25M ; 18.530 ; 18.530 ; Rise ; C25M ; -; SD[*] ; C25M ; 17.061 ; 17.061 ; Rise ; C25M ; -; SD[0] ; C25M ; 17.061 ; 17.061 ; Rise ; C25M ; -; SD[1] ; C25M ; 15.918 ; 15.918 ; Rise ; C25M ; -; SD[2] ; C25M ; 16.402 ; 16.402 ; Rise ; C25M ; -; SD[3] ; C25M ; 16.297 ; 16.297 ; Rise ; C25M ; -; SD[4] ; C25M ; 15.834 ; 15.834 ; Rise ; C25M ; -; SD[5] ; C25M ; 16.821 ; 16.821 ; Rise ; C25M ; -; SD[6] ; C25M ; 16.477 ; 16.477 ; Rise ; C25M ; -; SD[7] ; C25M ; 16.328 ; 16.328 ; Rise ; C25M ; -; nCAS ; C25M ; 17.133 ; 17.133 ; Rise ; C25M ; -; nFCS ; C25M ; 17.510 ; 17.510 ; Rise ; C25M ; -; nRAS ; C25M ; 15.968 ; 15.968 ; Rise ; C25M ; -; nRCS ; C25M ; 17.139 ; 17.139 ; Rise ; C25M ; -; nRESout ; C25M ; 17.067 ; 17.067 ; Rise ; C25M ; -; nSWE ; C25M ; 17.830 ; 17.830 ; Rise ; C25M ; -; RD[*] ; C25M ; 10.221 ; 10.221 ; Fall ; C25M ; -; RD[0] ; C25M ; 8.885 ; 8.885 ; Fall ; C25M ; -; RD[1] ; C25M ; 9.048 ; 9.048 ; Fall ; C25M ; -; RD[2] ; C25M ; 9.448 ; 9.448 ; Fall ; C25M ; -; RD[3] ; C25M ; 9.926 ; 9.926 ; Fall ; C25M ; -; RD[4] ; C25M ; 9.443 ; 9.443 ; Fall ; C25M ; -; RD[5] ; C25M ; 10.114 ; 10.114 ; Fall ; C25M ; -; RD[6] ; C25M ; 9.651 ; 9.651 ; Fall ; C25M ; -; RD[7] ; C25M ; 10.221 ; 10.221 ; Fall ; C25M ; -; RDdir ; PHI0 ; 21.935 ; 21.935 ; Rise ; PHI0 ; -; RDdir ; PHI0 ; 21.935 ; 21.935 ; Fall ; PHI0 ; -+-----------+------------+--------+--------+------------+-----------------+ - - -+-------------------------------------------------------------------------+ -; Minimum Clock to Output Times ; -+-----------+------------+--------+--------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-----------+------------+--------+--------+------------+-----------------+ -; DQMH ; C25M ; 17.381 ; 17.381 ; Rise ; C25M ; -; DQML ; C25M ; 17.650 ; 17.650 ; Rise ; C25M ; -; FCK ; C25M ; 17.362 ; 17.362 ; Rise ; C25M ; -; MOSI ; C25M ; 17.251 ; 17.251 ; Rise ; C25M ; -; RCKE ; C25M ; 17.169 ; 17.169 ; Rise ; C25M ; -; RDdir ; C25M ; 20.487 ; 20.487 ; Rise ; C25M ; -; SA[*] ; C25M ; 15.989 ; 15.989 ; Rise ; C25M ; -; SA[0] ; C25M ; 15.989 ; 15.989 ; Rise ; C25M ; -; SA[1] ; C25M ; 17.051 ; 17.051 ; Rise ; C25M ; -; SA[2] ; C25M ; 17.460 ; 17.460 ; Rise ; C25M ; -; SA[3] ; C25M ; 18.571 ; 18.571 ; Rise ; C25M ; -; SA[4] ; C25M ; 17.861 ; 17.861 ; Rise ; C25M ; -; SA[5] ; C25M ; 17.846 ; 17.846 ; Rise ; C25M ; -; SA[6] ; C25M ; 17.924 ; 17.924 ; Rise ; C25M ; -; SA[7] ; C25M ; 17.771 ; 17.771 ; Rise ; C25M ; -; SA[8] ; C25M ; 17.826 ; 17.826 ; Rise ; C25M ; -; SA[9] ; C25M ; 17.029 ; 17.029 ; Rise ; C25M ; -; SA[10] ; C25M ; 17.820 ; 17.820 ; Rise ; C25M ; -; SA[11] ; C25M ; 17.097 ; 17.097 ; Rise ; C25M ; -; SA[12] ; C25M ; 18.520 ; 18.520 ; Rise ; C25M ; -; SBA[*] ; C25M ; 17.892 ; 17.892 ; Rise ; C25M ; -; SBA[0] ; C25M ; 17.892 ; 17.892 ; Rise ; C25M ; -; SBA[1] ; C25M ; 18.530 ; 18.530 ; Rise ; C25M ; -; SD[*] ; C25M ; 15.834 ; 15.834 ; Rise ; C25M ; -; SD[0] ; C25M ; 17.061 ; 17.061 ; Rise ; C25M ; -; SD[1] ; C25M ; 15.918 ; 15.918 ; Rise ; C25M ; -; SD[2] ; C25M ; 16.402 ; 16.402 ; Rise ; C25M ; -; SD[3] ; C25M ; 16.297 ; 16.297 ; Rise ; C25M ; -; SD[4] ; C25M ; 15.834 ; 15.834 ; Rise ; C25M ; -; SD[5] ; C25M ; 16.821 ; 16.821 ; Rise ; C25M ; -; SD[6] ; C25M ; 16.477 ; 16.477 ; Rise ; C25M ; -; SD[7] ; C25M ; 16.328 ; 16.328 ; Rise ; C25M ; -; nCAS ; C25M ; 17.133 ; 17.133 ; Rise ; C25M ; -; nFCS ; C25M ; 17.510 ; 17.510 ; Rise ; C25M ; -; nRAS ; C25M ; 15.968 ; 15.968 ; Rise ; C25M ; -; nRCS ; C25M ; 17.139 ; 17.139 ; Rise ; C25M ; -; nRESout ; C25M ; 17.067 ; 17.067 ; Rise ; C25M ; -; nSWE ; C25M ; 17.830 ; 17.830 ; Rise ; C25M ; -; RD[*] ; C25M ; 8.885 ; 8.885 ; Fall ; C25M ; -; RD[0] ; C25M ; 8.885 ; 8.885 ; Fall ; C25M ; -; RD[1] ; C25M ; 9.048 ; 9.048 ; Fall ; C25M ; -; RD[2] ; C25M ; 9.448 ; 9.448 ; Fall ; C25M ; -; RD[3] ; C25M ; 9.926 ; 9.926 ; Fall ; C25M ; -; RD[4] ; C25M ; 9.443 ; 9.443 ; Fall ; C25M ; -; RD[5] ; C25M ; 10.114 ; 10.114 ; Fall ; C25M ; -; RD[6] ; C25M ; 9.651 ; 9.651 ; Fall ; C25M ; -; RD[7] ; C25M ; 10.221 ; 10.221 ; Fall ; C25M ; -; RDdir ; PHI0 ; 21.935 ; 21.935 ; Rise ; PHI0 ; -; RDdir ; PHI0 ; 21.935 ; 21.935 ; Fall ; PHI0 ; -+-----------+------------+--------+--------+------------+-----------------+ - - -+------------------------------------------------------+ -; Propagation Delay ; -+------------+-------------+--------+----+----+--------+ -; Input Port ; Output Port ; RR ; RF ; FR ; FF ; -+------------+-------------+--------+----+----+--------+ -; DMAin ; DMAout ; 8.665 ; ; ; 8.665 ; -; INTin ; INTout ; 8.862 ; ; ; 8.862 ; -; RA[0] ; RD[0] ; 13.610 ; ; ; 13.610 ; -; RA[0] ; RD[1] ; 13.610 ; ; ; 13.610 ; -; RA[0] ; RD[2] ; 13.610 ; ; ; 13.610 ; -; RA[0] ; RD[3] ; 13.610 ; ; ; 13.610 ; -; RA[0] ; RD[4] ; 13.610 ; ; ; 13.610 ; -; RA[0] ; RD[5] ; 13.610 ; ; ; 13.610 ; -; RA[0] ; RD[6] ; 13.565 ; ; ; 13.565 ; -; RA[0] ; RD[7] ; 13.565 ; ; ; 13.565 ; -; RA[0] ; RDdir ; 23.870 ; ; ; 23.870 ; -; RA[1] ; RD[0] ; 12.760 ; ; ; 12.760 ; -; RA[1] ; RD[1] ; 12.760 ; ; ; 12.760 ; -; RA[1] ; RD[2] ; 12.760 ; ; ; 12.760 ; -; RA[1] ; RD[3] ; 12.760 ; ; ; 12.760 ; -; RA[1] ; RD[4] ; 12.760 ; ; ; 12.760 ; -; RA[1] ; RD[5] ; 12.760 ; ; ; 12.760 ; -; RA[1] ; RD[6] ; 12.715 ; ; ; 12.715 ; -; RA[1] ; RD[7] ; 12.715 ; ; ; 12.715 ; -; RA[1] ; RDdir ; 23.020 ; ; ; 23.020 ; -; RA[2] ; RD[0] ; 13.252 ; ; ; 13.252 ; -; RA[2] ; RD[1] ; 13.252 ; ; ; 13.252 ; -; RA[2] ; RD[2] ; 13.252 ; ; ; 13.252 ; -; RA[2] ; RD[3] ; 13.252 ; ; ; 13.252 ; -; RA[2] ; RD[4] ; 13.252 ; ; ; 13.252 ; -; RA[2] ; RD[5] ; 13.252 ; ; ; 13.252 ; -; RA[2] ; RD[6] ; 13.207 ; ; ; 13.207 ; -; RA[2] ; RD[7] ; 13.207 ; ; ; 13.207 ; -; RA[2] ; RDdir ; 23.512 ; ; ; 23.512 ; -; RA[3] ; RD[0] ; 13.532 ; ; ; 13.532 ; -; RA[3] ; RD[1] ; 13.532 ; ; ; 13.532 ; -; RA[3] ; RD[2] ; 13.532 ; ; ; 13.532 ; -; RA[3] ; RD[3] ; 13.532 ; ; ; 13.532 ; -; RA[3] ; RD[4] ; 13.532 ; ; ; 13.532 ; -; RA[3] ; RD[5] ; 13.532 ; ; ; 13.532 ; -; RA[3] ; RD[6] ; 13.487 ; ; ; 13.487 ; -; RA[3] ; RD[7] ; 13.487 ; ; ; 13.487 ; -; RA[3] ; RDdir ; 23.792 ; ; ; 23.792 ; -; RA[4] ; RD[0] ; 13.442 ; ; ; 13.442 ; -; RA[4] ; RD[1] ; 13.442 ; ; ; 13.442 ; -; RA[4] ; RD[2] ; 13.442 ; ; ; 13.442 ; -; RA[4] ; RD[3] ; 13.442 ; ; ; 13.442 ; -; RA[4] ; RD[4] ; 13.442 ; ; ; 13.442 ; -; RA[4] ; RD[5] ; 13.442 ; ; ; 13.442 ; -; RA[4] ; RD[6] ; 13.397 ; ; ; 13.397 ; -; RA[4] ; RD[7] ; 13.397 ; ; ; 13.397 ; -; RA[4] ; RDdir ; 23.702 ; ; ; 23.702 ; -; RA[5] ; RD[0] ; 13.393 ; ; ; 13.393 ; -; RA[5] ; RD[1] ; 13.393 ; ; ; 13.393 ; -; RA[5] ; RD[2] ; 13.393 ; ; ; 13.393 ; -; RA[5] ; RD[3] ; 13.393 ; ; ; 13.393 ; -; RA[5] ; RD[4] ; 13.393 ; ; ; 13.393 ; -; RA[5] ; RD[5] ; 13.393 ; ; ; 13.393 ; -; RA[5] ; RD[6] ; 13.348 ; ; ; 13.348 ; -; RA[5] ; RD[7] ; 13.348 ; ; ; 13.348 ; -; RA[5] ; RDdir ; 23.653 ; ; ; 23.653 ; -; RA[6] ; RD[0] ; 13.690 ; ; ; 13.690 ; -; RA[6] ; RD[1] ; 13.690 ; ; ; 13.690 ; -; RA[6] ; RD[2] ; 13.690 ; ; ; 13.690 ; -; RA[6] ; RD[3] ; 13.690 ; ; ; 13.690 ; -; RA[6] ; RD[4] ; 13.690 ; ; ; 13.690 ; -; RA[6] ; RD[5] ; 13.690 ; ; ; 13.690 ; -; RA[6] ; RD[6] ; 13.645 ; ; ; 13.645 ; -; RA[6] ; RD[7] ; 13.645 ; ; ; 13.645 ; -; RA[6] ; RDdir ; 23.950 ; ; ; 23.950 ; -; RA[7] ; RD[0] ; 12.122 ; ; ; 12.122 ; -; RA[7] ; RD[1] ; 12.122 ; ; ; 12.122 ; -; RA[7] ; RD[2] ; 12.122 ; ; ; 12.122 ; -; RA[7] ; RD[3] ; 12.122 ; ; ; 12.122 ; -; RA[7] ; RD[4] ; 12.122 ; ; ; 12.122 ; -; RA[7] ; RD[5] ; 12.122 ; ; ; 12.122 ; -; RA[7] ; RD[6] ; 12.077 ; ; ; 12.077 ; -; RA[7] ; RD[7] ; 12.077 ; ; ; 12.077 ; -; RA[7] ; RDdir ; 22.382 ; ; ; 22.382 ; -; RA[8] ; RD[0] ; 11.505 ; ; ; 11.505 ; -; RA[8] ; RD[1] ; 11.505 ; ; ; 11.505 ; -; RA[8] ; RD[2] ; 11.505 ; ; ; 11.505 ; -; RA[8] ; RD[3] ; 11.505 ; ; ; 11.505 ; -; RA[8] ; RD[4] ; 11.505 ; ; ; 11.505 ; -; RA[8] ; RD[5] ; 11.505 ; ; ; 11.505 ; -; RA[8] ; RD[6] ; 11.460 ; ; ; 11.460 ; -; RA[8] ; RD[7] ; 11.460 ; ; ; 11.460 ; -; RA[8] ; RDdir ; 21.765 ; ; ; 21.765 ; -; RA[9] ; RD[0] ; 11.899 ; ; ; 11.899 ; -; RA[9] ; RD[1] ; 11.899 ; ; ; 11.899 ; -; RA[9] ; RD[2] ; 11.899 ; ; ; 11.899 ; -; RA[9] ; RD[3] ; 11.899 ; ; ; 11.899 ; -; RA[9] ; RD[4] ; 11.899 ; ; ; 11.899 ; -; RA[9] ; RD[5] ; 11.899 ; ; ; 11.899 ; -; RA[9] ; RD[6] ; 11.854 ; ; ; 11.854 ; -; RA[9] ; RD[7] ; 11.854 ; ; ; 11.854 ; -; RA[9] ; RDdir ; 22.159 ; ; ; 22.159 ; -; RA[10] ; RD[0] ; 13.038 ; ; ; 13.038 ; -; RA[10] ; RD[1] ; 13.038 ; ; ; 13.038 ; -; RA[10] ; RD[2] ; 13.038 ; ; ; 13.038 ; -; RA[10] ; RD[3] ; 13.038 ; ; ; 13.038 ; -; RA[10] ; RD[4] ; 13.038 ; ; ; 13.038 ; -; RA[10] ; RD[5] ; 13.038 ; ; ; 13.038 ; -; RA[10] ; RD[6] ; 12.993 ; ; ; 12.993 ; -; RA[10] ; RD[7] ; 12.993 ; ; ; 12.993 ; -; RA[10] ; RDdir ; 23.298 ; ; ; 23.298 ; -; nDEVSEL ; RD[0] ; 11.136 ; ; ; 11.136 ; -; nDEVSEL ; RD[1] ; 11.136 ; ; ; 11.136 ; -; nDEVSEL ; RD[2] ; 11.136 ; ; ; 11.136 ; -; nDEVSEL ; RD[3] ; 11.136 ; ; ; 11.136 ; -; nDEVSEL ; RD[4] ; 11.136 ; ; ; 11.136 ; -; nDEVSEL ; RD[5] ; 11.136 ; ; ; 11.136 ; -; nDEVSEL ; RD[6] ; 11.091 ; ; ; 11.091 ; -; nDEVSEL ; RD[7] ; 11.091 ; ; ; 11.091 ; -; nDEVSEL ; RDdir ; 21.396 ; ; ; 21.396 ; -; nIOSEL ; RD[0] ; 11.071 ; ; ; 11.071 ; -; nIOSEL ; RD[1] ; 11.071 ; ; ; 11.071 ; -; nIOSEL ; RD[2] ; 11.071 ; ; ; 11.071 ; -; nIOSEL ; RD[3] ; 11.071 ; ; ; 11.071 ; -; nIOSEL ; RD[4] ; 11.071 ; ; ; 11.071 ; -; nIOSEL ; RD[5] ; 11.071 ; ; ; 11.071 ; -; nIOSEL ; RD[6] ; 11.026 ; ; ; 11.026 ; -; nIOSEL ; RD[7] ; 11.026 ; ; ; 11.026 ; -; nIOSEL ; RDdir ; 21.331 ; ; ; 21.331 ; -; nIOSTRB ; RD[0] ; 12.415 ; ; ; 12.415 ; -; nIOSTRB ; RD[1] ; 12.415 ; ; ; 12.415 ; -; nIOSTRB ; RD[2] ; 12.415 ; ; ; 12.415 ; -; nIOSTRB ; RD[3] ; 12.415 ; ; ; 12.415 ; -; nIOSTRB ; RD[4] ; 12.415 ; ; ; 12.415 ; -; nIOSTRB ; RD[5] ; 12.415 ; ; ; 12.415 ; -; nIOSTRB ; RD[6] ; 12.370 ; ; ; 12.370 ; -; nIOSTRB ; RD[7] ; 12.370 ; ; ; 12.370 ; -; nIOSTRB ; RDdir ; 22.675 ; ; ; 22.675 ; -; nWE ; RD[0] ; 13.158 ; ; ; 13.158 ; -; nWE ; RD[1] ; 13.158 ; ; ; 13.158 ; -; nWE ; RD[2] ; 13.158 ; ; ; 13.158 ; -; nWE ; RD[3] ; 13.158 ; ; ; 13.158 ; -; nWE ; RD[4] ; 13.158 ; ; ; 13.158 ; -; nWE ; RD[5] ; 13.158 ; ; ; 13.158 ; -; nWE ; RD[6] ; 13.113 ; ; ; 13.113 ; -; nWE ; RD[7] ; 13.113 ; ; ; 13.113 ; -; nWE ; RDdir ; 23.418 ; ; ; 23.418 ; -+------------+-------------+--------+----+----+--------+ - - -+------------------------------------------------------+ -; Minimum Propagation Delay ; -+------------+-------------+--------+----+----+--------+ -; Input Port ; Output Port ; RR ; RF ; FR ; FF ; -+------------+-------------+--------+----+----+--------+ -; DMAin ; DMAout ; 8.665 ; ; ; 8.665 ; -; INTin ; INTout ; 8.862 ; ; ; 8.862 ; -; RA[0] ; RD[0] ; 13.610 ; ; ; 13.610 ; -; RA[0] ; RD[1] ; 13.610 ; ; ; 13.610 ; -; RA[0] ; RD[2] ; 13.610 ; ; ; 13.610 ; -; RA[0] ; RD[3] ; 13.610 ; ; ; 13.610 ; -; RA[0] ; RD[4] ; 13.610 ; ; ; 13.610 ; -; RA[0] ; RD[5] ; 13.610 ; ; ; 13.610 ; -; RA[0] ; RD[6] ; 13.565 ; ; ; 13.565 ; -; RA[0] ; RD[7] ; 13.565 ; ; ; 13.565 ; -; RA[0] ; RDdir ; 23.870 ; ; ; 23.870 ; -; RA[1] ; RD[0] ; 12.760 ; ; ; 12.760 ; -; RA[1] ; RD[1] ; 12.760 ; ; ; 12.760 ; -; RA[1] ; RD[2] ; 12.760 ; ; ; 12.760 ; -; RA[1] ; RD[3] ; 12.760 ; ; ; 12.760 ; -; RA[1] ; RD[4] ; 12.760 ; ; ; 12.760 ; -; RA[1] ; RD[5] ; 12.760 ; ; ; 12.760 ; -; RA[1] ; RD[6] ; 12.715 ; ; ; 12.715 ; -; RA[1] ; RD[7] ; 12.715 ; ; ; 12.715 ; -; RA[1] ; RDdir ; 23.020 ; ; ; 23.020 ; -; RA[2] ; RD[0] ; 13.252 ; ; ; 13.252 ; -; RA[2] ; RD[1] ; 13.252 ; ; ; 13.252 ; -; RA[2] ; RD[2] ; 13.252 ; ; ; 13.252 ; -; RA[2] ; RD[3] ; 13.252 ; ; ; 13.252 ; -; RA[2] ; RD[4] ; 13.252 ; ; ; 13.252 ; -; RA[2] ; RD[5] ; 13.252 ; ; ; 13.252 ; -; RA[2] ; RD[6] ; 13.207 ; ; ; 13.207 ; -; RA[2] ; RD[7] ; 13.207 ; ; ; 13.207 ; -; RA[2] ; RDdir ; 23.512 ; ; ; 23.512 ; -; RA[3] ; RD[0] ; 13.532 ; ; ; 13.532 ; -; RA[3] ; RD[1] ; 13.532 ; ; ; 13.532 ; -; RA[3] ; RD[2] ; 13.532 ; ; ; 13.532 ; -; RA[3] ; RD[3] ; 13.532 ; ; ; 13.532 ; -; RA[3] ; RD[4] ; 13.532 ; ; ; 13.532 ; -; RA[3] ; RD[5] ; 13.532 ; ; ; 13.532 ; -; RA[3] ; RD[6] ; 13.487 ; ; ; 13.487 ; -; RA[3] ; RD[7] ; 13.487 ; ; ; 13.487 ; -; RA[3] ; RDdir ; 23.792 ; ; ; 23.792 ; -; RA[4] ; RD[0] ; 13.442 ; ; ; 13.442 ; -; RA[4] ; RD[1] ; 13.442 ; ; ; 13.442 ; -; RA[4] ; RD[2] ; 13.442 ; ; ; 13.442 ; -; RA[4] ; RD[3] ; 13.442 ; ; ; 13.442 ; -; RA[4] ; RD[4] ; 13.442 ; ; ; 13.442 ; -; RA[4] ; RD[5] ; 13.442 ; ; ; 13.442 ; -; RA[4] ; RD[6] ; 13.397 ; ; ; 13.397 ; -; RA[4] ; RD[7] ; 13.397 ; ; ; 13.397 ; -; RA[4] ; RDdir ; 23.702 ; ; ; 23.702 ; -; RA[5] ; RD[0] ; 13.393 ; ; ; 13.393 ; -; RA[5] ; RD[1] ; 13.393 ; ; ; 13.393 ; -; RA[5] ; RD[2] ; 13.393 ; ; ; 13.393 ; -; RA[5] ; RD[3] ; 13.393 ; ; ; 13.393 ; -; RA[5] ; RD[4] ; 13.393 ; ; ; 13.393 ; -; RA[5] ; RD[5] ; 13.393 ; ; ; 13.393 ; -; RA[5] ; RD[6] ; 13.348 ; ; ; 13.348 ; -; RA[5] ; RD[7] ; 13.348 ; ; ; 13.348 ; -; RA[5] ; RDdir ; 23.653 ; ; ; 23.653 ; -; RA[6] ; RD[0] ; 13.690 ; ; ; 13.690 ; -; RA[6] ; RD[1] ; 13.690 ; ; ; 13.690 ; -; RA[6] ; RD[2] ; 13.690 ; ; ; 13.690 ; -; RA[6] ; RD[3] ; 13.690 ; ; ; 13.690 ; -; RA[6] ; RD[4] ; 13.690 ; ; ; 13.690 ; -; RA[6] ; RD[5] ; 13.690 ; ; ; 13.690 ; -; RA[6] ; RD[6] ; 13.645 ; ; ; 13.645 ; -; RA[6] ; RD[7] ; 13.645 ; ; ; 13.645 ; -; RA[6] ; RDdir ; 23.950 ; ; ; 23.950 ; -; RA[7] ; RD[0] ; 12.122 ; ; ; 12.122 ; -; RA[7] ; RD[1] ; 12.122 ; ; ; 12.122 ; -; RA[7] ; RD[2] ; 12.122 ; ; ; 12.122 ; -; RA[7] ; RD[3] ; 12.122 ; ; ; 12.122 ; -; RA[7] ; RD[4] ; 12.122 ; ; ; 12.122 ; -; RA[7] ; RD[5] ; 12.122 ; ; ; 12.122 ; -; RA[7] ; RD[6] ; 12.077 ; ; ; 12.077 ; -; RA[7] ; RD[7] ; 12.077 ; ; ; 12.077 ; -; RA[7] ; RDdir ; 22.382 ; ; ; 22.382 ; -; RA[8] ; RD[0] ; 11.505 ; ; ; 11.505 ; -; RA[8] ; RD[1] ; 11.505 ; ; ; 11.505 ; -; RA[8] ; RD[2] ; 11.505 ; ; ; 11.505 ; -; RA[8] ; RD[3] ; 11.505 ; ; ; 11.505 ; -; RA[8] ; RD[4] ; 11.505 ; ; ; 11.505 ; -; RA[8] ; RD[5] ; 11.505 ; ; ; 11.505 ; -; RA[8] ; RD[6] ; 11.460 ; ; ; 11.460 ; -; RA[8] ; RD[7] ; 11.460 ; ; ; 11.460 ; -; RA[8] ; RDdir ; 21.765 ; ; ; 21.765 ; -; RA[9] ; RD[0] ; 11.899 ; ; ; 11.899 ; -; RA[9] ; RD[1] ; 11.899 ; ; ; 11.899 ; -; RA[9] ; RD[2] ; 11.899 ; ; ; 11.899 ; -; RA[9] ; RD[3] ; 11.899 ; ; ; 11.899 ; -; RA[9] ; RD[4] ; 11.899 ; ; ; 11.899 ; -; RA[9] ; RD[5] ; 11.899 ; ; ; 11.899 ; -; RA[9] ; RD[6] ; 11.854 ; ; ; 11.854 ; -; RA[9] ; RD[7] ; 11.854 ; ; ; 11.854 ; -; RA[9] ; RDdir ; 22.159 ; ; ; 22.159 ; -; RA[10] ; RD[0] ; 13.038 ; ; ; 13.038 ; -; RA[10] ; RD[1] ; 13.038 ; ; ; 13.038 ; -; RA[10] ; RD[2] ; 13.038 ; ; ; 13.038 ; -; RA[10] ; RD[3] ; 13.038 ; ; ; 13.038 ; -; RA[10] ; RD[4] ; 13.038 ; ; ; 13.038 ; -; RA[10] ; RD[5] ; 13.038 ; ; ; 13.038 ; -; RA[10] ; RD[6] ; 12.993 ; ; ; 12.993 ; -; RA[10] ; RD[7] ; 12.993 ; ; ; 12.993 ; -; RA[10] ; RDdir ; 23.298 ; ; ; 23.298 ; -; nDEVSEL ; RD[0] ; 11.136 ; ; ; 11.136 ; -; nDEVSEL ; RD[1] ; 11.136 ; ; ; 11.136 ; -; nDEVSEL ; RD[2] ; 11.136 ; ; ; 11.136 ; -; nDEVSEL ; RD[3] ; 11.136 ; ; ; 11.136 ; -; nDEVSEL ; RD[4] ; 11.136 ; ; ; 11.136 ; -; nDEVSEL ; RD[5] ; 11.136 ; ; ; 11.136 ; -; nDEVSEL ; RD[6] ; 11.091 ; ; ; 11.091 ; -; nDEVSEL ; RD[7] ; 11.091 ; ; ; 11.091 ; -; nDEVSEL ; RDdir ; 21.396 ; ; ; 21.396 ; -; nIOSEL ; RD[0] ; 11.071 ; ; ; 11.071 ; -; nIOSEL ; RD[1] ; 11.071 ; ; ; 11.071 ; -; nIOSEL ; RD[2] ; 11.071 ; ; ; 11.071 ; -; nIOSEL ; RD[3] ; 11.071 ; ; ; 11.071 ; -; nIOSEL ; RD[4] ; 11.071 ; ; ; 11.071 ; -; nIOSEL ; RD[5] ; 11.071 ; ; ; 11.071 ; -; nIOSEL ; RD[6] ; 11.026 ; ; ; 11.026 ; -; nIOSEL ; RD[7] ; 11.026 ; ; ; 11.026 ; -; nIOSEL ; RDdir ; 21.331 ; ; ; 21.331 ; -; nIOSTRB ; RD[0] ; 12.415 ; ; ; 12.415 ; -; nIOSTRB ; RD[1] ; 12.415 ; ; ; 12.415 ; -; nIOSTRB ; RD[2] ; 12.415 ; ; ; 12.415 ; -; nIOSTRB ; RD[3] ; 12.415 ; ; ; 12.415 ; -; nIOSTRB ; RD[4] ; 12.415 ; ; ; 12.415 ; -; nIOSTRB ; RD[5] ; 12.415 ; ; ; 12.415 ; -; nIOSTRB ; RD[6] ; 12.370 ; ; ; 12.370 ; -; nIOSTRB ; RD[7] ; 12.370 ; ; ; 12.370 ; -; nIOSTRB ; RDdir ; 22.675 ; ; ; 22.675 ; -; nWE ; RD[0] ; 13.158 ; ; ; 13.158 ; -; nWE ; RD[1] ; 13.158 ; ; ; 13.158 ; -; nWE ; RD[2] ; 13.158 ; ; ; 13.158 ; -; nWE ; RD[3] ; 13.158 ; ; ; 13.158 ; -; nWE ; RD[4] ; 13.158 ; ; ; 13.158 ; -; nWE ; RD[5] ; 13.158 ; ; ; 13.158 ; -; nWE ; RD[6] ; 13.113 ; ; ; 13.113 ; -; nWE ; RD[7] ; 13.113 ; ; ; 13.113 ; -; nWE ; RDdir ; 23.418 ; ; ; 23.418 ; -+------------+-------------+--------+----+----+--------+ - - -+-----------------------------------------------------------------------+ -; Output Enable Times ; -+-----------+------------+--------+------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-----------+------------+--------+------+------------+-----------------+ -; FCK ; C25M ; 15.951 ; ; Rise ; C25M ; -; MOSI ; C25M ; 15.242 ; ; Rise ; C25M ; -; RD[*] ; C25M ; 13.690 ; ; Rise ; C25M ; -; RD[0] ; C25M ; 13.735 ; ; Rise ; C25M ; -; RD[1] ; C25M ; 13.735 ; ; Rise ; C25M ; -; RD[2] ; C25M ; 13.735 ; ; Rise ; C25M ; -; RD[3] ; C25M ; 13.735 ; ; Rise ; C25M ; -; RD[4] ; C25M ; 13.735 ; ; Rise ; C25M ; -; RD[5] ; C25M ; 13.735 ; ; Rise ; C25M ; -; RD[6] ; C25M ; 13.690 ; ; Rise ; C25M ; -; RD[7] ; C25M ; 13.690 ; ; Rise ; C25M ; -; SD[*] ; C25M ; 13.373 ; ; Rise ; C25M ; -; SD[0] ; C25M ; 13.829 ; ; Rise ; C25M ; -; SD[1] ; C25M ; 13.829 ; ; Rise ; C25M ; -; SD[2] ; C25M ; 13.373 ; ; Rise ; C25M ; -; SD[3] ; C25M ; 13.373 ; ; Rise ; C25M ; -; SD[4] ; C25M ; 13.829 ; ; Rise ; C25M ; -; SD[5] ; C25M ; 13.373 ; ; Rise ; C25M ; -; SD[6] ; C25M ; 13.373 ; ; Rise ; C25M ; -; SD[7] ; C25M ; 13.373 ; ; Rise ; C25M ; -; nFCS ; C25M ; 15.969 ; ; Rise ; C25M ; -; RD[*] ; PHI0 ; 11.630 ; ; Rise ; PHI0 ; -; RD[0] ; PHI0 ; 11.675 ; ; Rise ; PHI0 ; -; RD[1] ; PHI0 ; 11.675 ; ; Rise ; PHI0 ; -; RD[2] ; PHI0 ; 11.675 ; ; Rise ; PHI0 ; -; RD[3] ; PHI0 ; 11.675 ; ; Rise ; PHI0 ; -; RD[4] ; PHI0 ; 11.675 ; ; Rise ; PHI0 ; -; RD[5] ; PHI0 ; 11.675 ; ; Rise ; PHI0 ; -; RD[6] ; PHI0 ; 11.630 ; ; Rise ; PHI0 ; -; RD[7] ; PHI0 ; 11.630 ; ; Rise ; PHI0 ; -; RD[*] ; PHI0 ; 11.630 ; ; Fall ; PHI0 ; -; RD[0] ; PHI0 ; 11.675 ; ; Fall ; PHI0 ; -; RD[1] ; PHI0 ; 11.675 ; ; Fall ; PHI0 ; -; RD[2] ; PHI0 ; 11.675 ; ; Fall ; PHI0 ; -; RD[3] ; PHI0 ; 11.675 ; ; Fall ; PHI0 ; -; RD[4] ; PHI0 ; 11.675 ; ; Fall ; PHI0 ; -; RD[5] ; PHI0 ; 11.675 ; ; Fall ; PHI0 ; -; RD[6] ; PHI0 ; 11.630 ; ; Fall ; PHI0 ; -; RD[7] ; PHI0 ; 11.630 ; ; Fall ; PHI0 ; -+-----------+------------+--------+------+------------+-----------------+ - - -+-----------------------------------------------------------------------+ -; Minimum Output Enable Times ; -+-----------+------------+--------+------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-----------+------------+--------+------+------------+-----------------+ -; FCK ; C25M ; 15.951 ; ; Rise ; C25M ; -; MOSI ; C25M ; 15.242 ; ; Rise ; C25M ; -; RD[*] ; C25M ; 10.182 ; ; Rise ; C25M ; -; RD[0] ; C25M ; 10.227 ; ; Rise ; C25M ; -; RD[1] ; C25M ; 10.227 ; ; Rise ; C25M ; -; RD[2] ; C25M ; 10.227 ; ; Rise ; C25M ; -; RD[3] ; C25M ; 10.227 ; ; Rise ; C25M ; -; RD[4] ; C25M ; 10.227 ; ; Rise ; C25M ; -; RD[5] ; C25M ; 10.227 ; ; Rise ; C25M ; -; RD[6] ; C25M ; 10.182 ; ; Rise ; C25M ; -; RD[7] ; C25M ; 10.182 ; ; Rise ; C25M ; -; SD[*] ; C25M ; 13.373 ; ; Rise ; C25M ; -; SD[0] ; C25M ; 13.829 ; ; Rise ; C25M ; -; SD[1] ; C25M ; 13.829 ; ; Rise ; C25M ; -; SD[2] ; C25M ; 13.373 ; ; Rise ; C25M ; -; SD[3] ; C25M ; 13.373 ; ; Rise ; C25M ; -; SD[4] ; C25M ; 13.829 ; ; Rise ; C25M ; -; SD[5] ; C25M ; 13.373 ; ; Rise ; C25M ; -; SD[6] ; C25M ; 13.373 ; ; Rise ; C25M ; -; SD[7] ; C25M ; 13.373 ; ; Rise ; C25M ; -; nFCS ; C25M ; 15.969 ; ; Rise ; C25M ; -; RD[*] ; PHI0 ; 11.630 ; ; Rise ; PHI0 ; -; RD[0] ; PHI0 ; 11.675 ; ; Rise ; PHI0 ; -; RD[1] ; PHI0 ; 11.675 ; ; Rise ; PHI0 ; -; RD[2] ; PHI0 ; 11.675 ; ; Rise ; PHI0 ; -; RD[3] ; PHI0 ; 11.675 ; ; Rise ; PHI0 ; -; RD[4] ; PHI0 ; 11.675 ; ; Rise ; PHI0 ; -; RD[5] ; PHI0 ; 11.675 ; ; Rise ; PHI0 ; -; RD[6] ; PHI0 ; 11.630 ; ; Rise ; PHI0 ; -; RD[7] ; PHI0 ; 11.630 ; ; Rise ; PHI0 ; -; RD[*] ; PHI0 ; 11.630 ; ; Fall ; PHI0 ; -; RD[0] ; PHI0 ; 11.675 ; ; Fall ; PHI0 ; -; RD[1] ; PHI0 ; 11.675 ; ; Fall ; PHI0 ; -; RD[2] ; PHI0 ; 11.675 ; ; Fall ; PHI0 ; -; RD[3] ; PHI0 ; 11.675 ; ; Fall ; PHI0 ; -; RD[4] ; PHI0 ; 11.675 ; ; Fall ; PHI0 ; -; RD[5] ; PHI0 ; 11.675 ; ; Fall ; PHI0 ; -; RD[6] ; PHI0 ; 11.630 ; ; Fall ; PHI0 ; -; RD[7] ; PHI0 ; 11.630 ; ; Fall ; PHI0 ; -+-----------+------------+--------+------+------------+-----------------+ - - -+-------------------------------------------------------------------------------+ -; Output Disable Times ; -+-----------+------------+-----------+-----------+------------+-----------------+ -; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; -+-----------+------------+-----------+-----------+------------+-----------------+ -; FCK ; C25M ; 15.951 ; ; Rise ; C25M ; -; MOSI ; C25M ; 15.242 ; ; Rise ; C25M ; -; RD[*] ; C25M ; 13.690 ; ; Rise ; C25M ; -; RD[0] ; C25M ; 13.735 ; ; Rise ; C25M ; -; RD[1] ; C25M ; 13.735 ; ; Rise ; C25M ; -; RD[2] ; C25M ; 13.735 ; ; Rise ; C25M ; -; RD[3] ; C25M ; 13.735 ; ; Rise ; C25M ; -; RD[4] ; C25M ; 13.735 ; ; Rise ; C25M ; -; RD[5] ; C25M ; 13.735 ; ; Rise ; C25M ; -; RD[6] ; C25M ; 13.690 ; ; Rise ; C25M ; -; RD[7] ; C25M ; 13.690 ; ; Rise ; C25M ; -; SD[*] ; C25M ; 13.373 ; ; Rise ; C25M ; -; SD[0] ; C25M ; 13.829 ; ; Rise ; C25M ; -; SD[1] ; C25M ; 13.829 ; ; Rise ; C25M ; -; SD[2] ; C25M ; 13.373 ; ; Rise ; C25M ; -; SD[3] ; C25M ; 13.373 ; ; Rise ; C25M ; -; SD[4] ; C25M ; 13.829 ; ; Rise ; C25M ; -; SD[5] ; C25M ; 13.373 ; ; Rise ; C25M ; -; SD[6] ; C25M ; 13.373 ; ; Rise ; C25M ; -; SD[7] ; C25M ; 13.373 ; ; Rise ; C25M ; -; nFCS ; C25M ; 15.969 ; ; Rise ; C25M ; -; RD[*] ; PHI0 ; 11.630 ; ; Rise ; PHI0 ; -; RD[0] ; PHI0 ; 11.675 ; ; Rise ; PHI0 ; -; RD[1] ; PHI0 ; 11.675 ; ; Rise ; PHI0 ; -; RD[2] ; PHI0 ; 11.675 ; ; Rise ; PHI0 ; -; RD[3] ; PHI0 ; 11.675 ; ; Rise ; PHI0 ; -; RD[4] ; PHI0 ; 11.675 ; ; Rise ; PHI0 ; -; RD[5] ; PHI0 ; 11.675 ; ; Rise ; PHI0 ; -; RD[6] ; PHI0 ; 11.630 ; ; Rise ; PHI0 ; -; RD[7] ; PHI0 ; 11.630 ; ; Rise ; PHI0 ; -; RD[*] ; PHI0 ; 11.630 ; ; Fall ; PHI0 ; -; RD[0] ; PHI0 ; 11.675 ; ; Fall ; PHI0 ; -; RD[1] ; PHI0 ; 11.675 ; ; Fall ; PHI0 ; -; RD[2] ; PHI0 ; 11.675 ; ; Fall ; PHI0 ; -; RD[3] ; PHI0 ; 11.675 ; ; Fall ; PHI0 ; -; RD[4] ; PHI0 ; 11.675 ; ; Fall ; PHI0 ; -; RD[5] ; PHI0 ; 11.675 ; ; Fall ; PHI0 ; -; RD[6] ; PHI0 ; 11.630 ; ; Fall ; PHI0 ; -; RD[7] ; PHI0 ; 11.630 ; ; Fall ; PHI0 ; -+-----------+------------+-----------+-----------+------------+-----------------+ - - -+-------------------------------------------------------------------------------+ -; Minimum Output Disable Times ; -+-----------+------------+-----------+-----------+------------+-----------------+ -; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; -+-----------+------------+-----------+-----------+------------+-----------------+ -; FCK ; C25M ; 15.951 ; ; Rise ; C25M ; -; MOSI ; C25M ; 15.242 ; ; Rise ; C25M ; -; RD[*] ; C25M ; 10.182 ; ; Rise ; C25M ; -; RD[0] ; C25M ; 10.227 ; ; Rise ; C25M ; -; RD[1] ; C25M ; 10.227 ; ; Rise ; C25M ; -; RD[2] ; C25M ; 10.227 ; ; Rise ; C25M ; -; RD[3] ; C25M ; 10.227 ; ; Rise ; C25M ; -; RD[4] ; C25M ; 10.227 ; ; Rise ; C25M ; -; RD[5] ; C25M ; 10.227 ; ; Rise ; C25M ; -; RD[6] ; C25M ; 10.182 ; ; Rise ; C25M ; -; RD[7] ; C25M ; 10.182 ; ; Rise ; C25M ; -; SD[*] ; C25M ; 13.373 ; ; Rise ; C25M ; -; SD[0] ; C25M ; 13.829 ; ; Rise ; C25M ; -; SD[1] ; C25M ; 13.829 ; ; Rise ; C25M ; -; SD[2] ; C25M ; 13.373 ; ; Rise ; C25M ; -; SD[3] ; C25M ; 13.373 ; ; Rise ; C25M ; -; SD[4] ; C25M ; 13.829 ; ; Rise ; C25M ; -; SD[5] ; C25M ; 13.373 ; ; Rise ; C25M ; -; SD[6] ; C25M ; 13.373 ; ; Rise ; C25M ; -; SD[7] ; C25M ; 13.373 ; ; Rise ; C25M ; -; nFCS ; C25M ; 15.969 ; ; Rise ; C25M ; -; RD[*] ; PHI0 ; 11.630 ; ; Rise ; PHI0 ; -; RD[0] ; PHI0 ; 11.675 ; ; Rise ; PHI0 ; -; RD[1] ; PHI0 ; 11.675 ; ; Rise ; PHI0 ; -; RD[2] ; PHI0 ; 11.675 ; ; Rise ; PHI0 ; -; RD[3] ; PHI0 ; 11.675 ; ; Rise ; PHI0 ; -; RD[4] ; PHI0 ; 11.675 ; ; Rise ; PHI0 ; -; RD[5] ; PHI0 ; 11.675 ; ; Rise ; PHI0 ; -; RD[6] ; PHI0 ; 11.630 ; ; Rise ; PHI0 ; -; RD[7] ; PHI0 ; 11.630 ; ; Rise ; PHI0 ; -; RD[*] ; PHI0 ; 11.630 ; ; Fall ; PHI0 ; -; RD[0] ; PHI0 ; 11.675 ; ; Fall ; PHI0 ; -; RD[1] ; PHI0 ; 11.675 ; ; Fall ; PHI0 ; -; RD[2] ; PHI0 ; 11.675 ; ; Fall ; PHI0 ; -; RD[3] ; PHI0 ; 11.675 ; ; Fall ; PHI0 ; -; RD[4] ; PHI0 ; 11.675 ; ; Fall ; PHI0 ; -; RD[5] ; PHI0 ; 11.675 ; ; Fall ; PHI0 ; -; RD[6] ; PHI0 ; 11.630 ; ; Fall ; PHI0 ; -; RD[7] ; PHI0 ; 11.630 ; ; Fall ; PHI0 ; -+-----------+------------+-----------+-----------+------------+-----------------+ - - +-------------------------------------------------------------------------+ ; Setup Transfers ; +------------+----------+------------+------------+------------+----------+ ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; +------------+----------+------------+------------+------------+----------+ -; C25M ; C25M ; 1526 ; 0 ; 88 ; 0 ; +; C25M ; C25M ; 1520 ; 0 ; 88 ; 0 ; ; PHI0 ; C25M ; false path ; false path ; false path ; 0 ; +------------+----------+------------+------------+------------+----------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. @@ -1341,7 +468,7 @@ Entries labeled "false path" only account for clock-to-clock false paths and not +------------+----------+------------+------------+------------+----------+ ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; +------------+----------+------------+------------+------------+----------+ -; C25M ; C25M ; 1526 ; 0 ; 88 ; 0 ; +; C25M ; C25M ; 1520 ; 0 ; 88 ; 0 ; ; PHI0 ; C25M ; false path ; false path ; false path ; 0 ; +------------+----------+------------+------------+------------+----------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. @@ -1376,11 +503,11 @@ No dedicated SERDES Transmitter circuitry present in device or used in design --------------- ; Report RSKM ; --------------- -No dedicated SERDES Receiver circuitry present in device or used in design +No non-DPA dedicated SERDES Receiver circuitry present in device or used in design +------------------------------------------------+ -; Unconstrained Paths ; +; Unconstrained Paths Summary ; +---------------------------------+-------+------+ ; Property ; Setup ; Hold ; +---------------------------------+-------+------+ @@ -1393,49 +520,271 @@ No dedicated SERDES Receiver circuitry present in device or used in design +---------------------------------+-------+------+ -+------------------------------------+ -; TimeQuest Timing Analyzer Messages ; -+------------------------------------+ ++-------------------------------------+ +; Clock Status Summary ; ++--------+-------+------+-------------+ +; Target ; Clock ; Type ; Status ; ++--------+-------+------+-------------+ +; C25M ; C25M ; Base ; Constrained ; +; PHI0 ; PHI0 ; Base ; Constrained ; ++--------+-------+------+-------------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; DMAin ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; INTin ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; MISO ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; MOSI ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; PHI0 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[9] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[10] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[11] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[12] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[13] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[14] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[15] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SD[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SD[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SD[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SD[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SD[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SD[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SD[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SD[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SetFW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SetFW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nDEVSEL ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nIOSEL ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nIOSTRB ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nRES ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nWE ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; DMAout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; DQMH ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; DQML ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; FCK ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; INTout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; MOSI ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RCKE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RDdir ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SA[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SA[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SA[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SA[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SA[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SA[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SA[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SA[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SA[8] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SA[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SA[10] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SA[11] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SA[12] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SBA[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SBA[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SD[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SD[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SD[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SD[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SD[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SD[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SD[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SD[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nCAS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nFCS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nRAS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nRCS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nRESout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nSWE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; DMAin ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; INTin ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; MISO ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; MOSI ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; PHI0 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[9] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[10] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[11] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[12] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[13] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[14] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[15] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SD[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SD[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SD[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SD[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SD[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SD[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SD[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SD[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SetFW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SetFW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nDEVSEL ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nIOSEL ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nIOSTRB ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nRES ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nWE ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; DMAout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; DQMH ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; DQML ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; FCK ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; INTout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; MOSI ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RCKE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RDdir ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SA[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SA[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SA[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SA[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SA[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SA[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SA[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SA[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SA[8] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SA[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SA[10] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SA[11] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SA[12] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SBA[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SBA[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SD[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SD[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SD[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SD[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SD[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SD[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SD[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SD[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nCAS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nFCS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nRAS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nRCS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nRESout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nSWE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++--------------------------+ +; Timing Analyzer Messages ; ++--------------------------+ Info: ******************************************************************* -Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer - Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - Info: Processing started: Tue Sep 14 01:35:32 2021 +Info: Running Quartus Prime Timing Analyzer + Info: Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition + Info: Processing started: Tue Feb 28 11:21:27 2023 Info: Command: quartus_sta GR8RAM -c GR8RAM Info: qsta_default_script.tcl version: #1 -Warning (20028): Parallel compilation is not licensed and has been disabled +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected Info (21077): Low junction temperature is 0 degrees C Info (21077): High junction temperature is 85 degrees C -Info (306004): Started post-fitting delay annotation -Info (306005): Delay annotation completed successfully +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully Info (332104): Reading SDC File: 'GR8RAM.sdc' -Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON -Info (332146): Worst-case setup slack is 12.419 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= ============= ===================== - Info (332119): 12.419 0.000 C25M -Info (332146): Worst-case hold slack is 1.393 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= ============= ===================== - Info (332119): 1.393 0.000 C25M -Info (332146): Worst-case recovery slack is 33.300 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= ============= ===================== - Info (332119): 33.300 0.000 C25M -Info (332146): Worst-case removal slack is 6.146 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= ============= ===================== - Info (332119): 6.146 0.000 C25M +Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON +Info: Can't run Report Timing Closure Recommendations. The current device family is not supported. +Info (332146): Worst-case setup slack is 10.278 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 10.278 0.000 C25M +Info (332146): Worst-case hold slack is 1.376 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 1.376 0.000 C25M +Info (332146): Worst-case recovery slack is 33.311 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 33.311 0.000 C25M +Info (332146): Worst-case removal slack is 6.135 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 6.135 0.000 C25M Info (332146): Worst-case minimum pulse width slack is 19.734 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= ============= ===================== - Info (332119): 19.734 0.000 C25M - Info (332119): 488.734 0.000 PHI0 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 19.734 0.000 C25M + Info (332119): 488.734 0.000 PHI0 Info (332001): The selected device family is not supported by the report_metastability command. Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements -Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 1 warning - Info: Peak virtual memory: 374 megabytes - Info: Processing ended: Tue Sep 14 01:35:34 2021 +Info: Quartus Prime Timing Analyzer was successful. 0 errors, 1 warning + Info: Peak virtual memory: 13081 megabytes + Info: Processing ended: Tue Feb 28 11:21:29 2023 Info: Elapsed time: 00:00:02 Info: Total CPU time (on all processors): 00:00:01 diff --git a/cpld/output_files/GR8RAM.sta.summary b/cpld/output_files/GR8RAM.sta.summary old mode 100755 new mode 100644 index d814531..2f7497e --- a/cpld/output_files/GR8RAM.sta.summary +++ b/cpld/output_files/GR8RAM.sta.summary @@ -1,21 +1,21 @@ ------------------------------------------------------------ -TimeQuest Timing Analyzer Summary +Timing Analyzer Summary ------------------------------------------------------------ Type : Setup 'C25M' -Slack : 12.419 +Slack : 10.278 TNS : 0.000 Type : Hold 'C25M' -Slack : 1.393 +Slack : 1.376 TNS : 0.000 Type : Recovery 'C25M' -Slack : 33.300 +Slack : 33.311 TNS : 0.000 Type : Removal 'C25M' -Slack : 6.146 +Slack : 6.135 TNS : 0.000 Type : Minimum Pulse Width 'C25M' diff --git a/cpld/output_files/GR8RAM.svf b/cpld/output_files/GR8RAM.svf index 74a77b5..432de55 100644 --- a/cpld/output_files/GR8RAM.svf +++ b/cpld/output_files/GR8RAM.svf @@ -15,11 +15,11 @@ ! !Quartus Prime SVF converter 22.1 ! -!Device #1: EPM240 - //Mac/iCloud/Repos2/GR8RAM/cpld/output_files/GR8RAM.pof Sat Feb 25 09:32:41 2023 +!Device #1: EPM240 - //mac/iCloud/Repos2/GR8RAM/cpld2/output_files/GR8RAM.pof Tue Feb 28 11:21:26 2023 ! -!NOTE "USERCODE" "00161CF0"; +!NOTE "USERCODE" "00163AA4"; ! -!NOTE "CHECKSUM" "001620E8"; +!NOTE "CHECKSUM" "00163E9C"; ! ! ! @@ -129,7 +129,7 @@ SDR 16 TDI (BFF7); RUNTEST 100 TCK; SDR 16 TDI (FFFF); RUNTEST 100 TCK; -SDR 16 TDI (7FFF); +SDR 16 TDI (7FFB); RUNTEST 100 TCK; SDR 16 TDI (FFFF); RUNTEST 100 TCK; @@ -153,7 +153,7 @@ SDR 16 TDI (BFFF); RUNTEST 100 TCK; SDR 16 TDI (FFFF); RUNTEST 100 TCK; -SDR 16 TDI (67FF); +SDR 16 TDI (77FF); RUNTEST 100 TCK; SDR 16 TDI (FFFF); RUNTEST 100 TCK; @@ -161,25 +161,25 @@ SDR 16 TDI (BFFF); RUNTEST 100 TCK; SDR 16 TDI (C666); RUNTEST 100 TCK; -SDR 16 TDI (6FF9); +SDR 16 TDI (6FFB); RUNTEST 100 TCK; SDR 16 TDI (FF7F); RUNTEST 100 TCK; SDR 16 TDI (BC66); RUNTEST 100 TCK; -SDR 16 TDI (67FE); +SDR 16 TDI (67F6); RUNTEST 100 TCK; SDR 16 TDI (733F); RUNTEST 100 TCK; SDR 16 TDI (FF19); RUNTEST 100 TCK; -SDR 16 TDI (BD3F); +SDR 16 TDI (AF3F); RUNTEST 100 TCK; -SDR 16 TDI (ECCF); +SDR 16 TDI (E4CF); RUNTEST 100 TCK; SDR 16 TDI (7FFF); RUNTEST 100 TCK; -SDR 16 TDI (7FFF); +SDR 16 TDI (FF7F); RUNTEST 100 TCK; SDR 16 TDI (BFCC); RUNTEST 100 TCK; @@ -199,439 +199,39 @@ SDR 16 TDI (FFFF); RUNTEST 100 TCK; SDR 16 TDI (BFFF); RUNTEST 100 TCK; -SDR 16 TDI (FFF7); +SDR 16 TDI (FFFF); RUNTEST 100 TCK; -SDR 16 TDI (77BF); +SDR 16 TDI (77DF); RUNTEST 100 TCK; SDR 16 TDI (EFFF); RUNTEST 100 TCK; -SDR 16 TDI (B7FF); -RUNTEST 100 TCK; -SDR 16 TDI (F7FF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FF7F); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (6FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFB); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (77FF); -RUNTEST 100 TCK; -SDR 16 TDI (FBFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFEF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FDF); -RUNTEST 100 TCK; -SDR 16 TDI (EFFF); -RUNTEST 100 TCK; -SDR 16 TDI (ADFF); -RUNTEST 100 TCK; -SDR 16 TDI (EFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFE); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FEF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFA); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (EEFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FF7F); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFE); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFE); -RUNTEST 100 TCK; -SDR 16 TDI (F7FF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (CFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFBF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7DFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFBF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFE); -RUNTEST 100 TCK; -SDR 16 TDI (FFFE); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FF7F); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (DFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (777F); -RUNTEST 100 TCK; -SDR 16 TDI (EFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BF7F); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7BFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFE); -RUNTEST 100 TCK; -SDR 16 TDI (6FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FF7F); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFE); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7F7F); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7DFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (6FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (F7FF); -RUNTEST 100 TCK; -SDR 16 TDI (77FF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFDF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (77FF); -RUNTEST 100 TCK; -SDR 16 TDI (FF7F); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BEFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (77F7); -RUNTEST 100 TCK; -SDR 16 TDI (FFFE); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FBFF); -RUNTEST 100 TCK; -SDR 16 TDI (76FF); -RUNTEST 100 TCK; -SDR 16 TDI (ABFD); -RUNTEST 100 TCK; -SDR 16 TDI (BBBF); -RUNTEST 100 TCK; -SDR 16 TDI (FFDA); -RUNTEST 100 TCK; -SDR 16 TDI (7DFE); -RUNTEST 100 TCK; -SDR 16 TDI (FFBF); -RUNTEST 100 TCK; -SDR 16 TDI (BFEF); -RUNTEST 100 TCK; -SDR 16 TDI (FEFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FDFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (7F7F); -RUNTEST 100 TCK; -SDR 16 TDI (BFEF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFE); -RUNTEST 100 TCK; -SDR 16 TDI (7FF5); -RUNTEST 100 TCK; -SDR 16 TDI (EF5F); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (DBFF); -RUNTEST 100 TCK; -SDR 16 TDI (7B7B); -RUNTEST 100 TCK; -SDR 16 TDI (EFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BDFE); -RUNTEST 100 TCK; -SDR 16 TDI (DDFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFF7); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFB); -RUNTEST 100 TCK; -SDR 16 TDI (EF7E); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FF7); -RUNTEST 100 TCK; -SDR 16 TDI (EFFD); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FCCD); -RUNTEST 100 TCK; -SDR 16 TDI (7BFD); -RUNTEST 100 TCK; -SDR 16 TDI (FF7F); -RUNTEST 100 TCK; -SDR 16 TDI (BDFF); -RUNTEST 100 TCK; -SDR 16 TDI (7DFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FDFF); -RUNTEST 100 TCK; -SDR 16 TDI (6FF7); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFEF); -RUNTEST 100 TCK; -SDR 16 TDI (77FD); -RUNTEST 100 TCK; -SDR 16 TDI (76FB); -RUNTEST 100 TCK; -SDR 16 TDI (D7AF); -RUNTEST 100 TCK; -SDR 16 TDI (BDDF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (6DBB); -RUNTEST 100 TCK; -SDR 16 TDI (EFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFF7); -RUNTEST 100 TCK; -SDR 16 TDI (BEFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (F7EF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FB7); -RUNTEST 100 TCK; -SDR 16 TDI (BAFB); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7BBF); -RUNTEST 100 TCK; -SDR 16 TDI (FF7F); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFBF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (EEFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFD); -RUNTEST 100 TCK; -SDR 16 TDI (EFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (EDFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FEF); -RUNTEST 100 TCK; -SDR 16 TDI (AFFD); -RUNTEST 100 TCK; -SDR 16 TDI (BFDF); -RUNTEST 100 TCK; -SDR 16 TDI (FFF7); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFE); -RUNTEST 100 TCK; -SDR 16 TDI (B7FF); -RUNTEST 100 TCK; -SDR 16 TDI (BEEF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFB); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; SDR 16 TDI (BBFF); RUNTEST 100 TCK; -SDR 16 TDI (FF7F); +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFE); +RUNTEST 100 TCK; +SDR 16 TDI (6FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FEF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFF5); RUNTEST 100 TCK; SDR 16 TDI (7FFF); RUNTEST 100 TCK; @@ -639,29 +239,45 @@ SDR 16 TDI (FFFF); RUNTEST 100 TCK; SDR 16 TDI (BFFF); RUNTEST 100 TCK; -SDR 16 TDI (DFFF); +SDR 16 TDI (FFFF); RUNTEST 100 TCK; SDR 16 TDI (7FFF); RUNTEST 100 TCK; -SDR 16 TDI (F7FD); +SDR 16 TDI (FFFF); RUNTEST 100 TCK; -SDR 16 TDI (B7BF); +SDR 16 TDI (BFFF); RUNTEST 100 TCK; -SDR 16 TDI (FFFB); +SDR 16 TDI (FFFF); RUNTEST 100 TCK; -SDR 16 TDI (6CDF); +SDR 16 TDI (6FFF); RUNTEST 100 TCK; -SDR 16 TDI (DFFD); +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (EFFF); RUNTEST 100 TCK; SDR 16 TDI (AFFF); RUNTEST 100 TCK; -SDR 16 TDI (FFDF); +SDR 16 TDI (FFFF); RUNTEST 100 TCK; SDR 16 TDI (7FFF); RUNTEST 100 TCK; SDR 16 TDI (FFFF); RUNTEST 100 TCK; -SDR 16 TDI (BFFD); +SDR 16 TDI (BFFF); RUNTEST 100 TCK; SDR 16 TDI (FFFF); RUNTEST 100 TCK; @@ -671,1631 +287,71 @@ SDR 16 TDI (FFFF); RUNTEST 100 TCK; SDR 16 TDI (BFFF); RUNTEST 100 TCK; -SDR 16 TDI (F9EF); +SDR 16 TDI (BFFF); RUNTEST 100 TCK; SDR 16 TDI (7FFF); RUNTEST 100 TCK; -SDR 16 TDI (3FD7); -RUNTEST 100 TCK; -SDR 16 TDI (BDEB); -RUNTEST 100 TCK; SDR 16 TDI (FFFF); RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (EF7F); -RUNTEST 100 TCK; SDR 16 TDI (BFFF); RUNTEST 100 TCK; -SDR 16 TDI (FF77); +SDR 16 TDI (FFFF); RUNTEST 100 TCK; -SDR 16 TDI (7FF7); +SDR 16 TDI (6FDF); RUNTEST 100 TCK; SDR 16 TDI (EEFF); RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (F77F); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (B55F); -RUNTEST 100 TCK; -SDR 16 TDI (FEBF); -RUNTEST 100 TCK; -SDR 16 TDI (6FEF); -RUNTEST 100 TCK; -SDR 16 TDI (FF7F); -RUNTEST 100 TCK; -SDR 16 TDI (B6FF); -RUNTEST 100 TCK; -SDR 16 TDI (FBFB); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFF6); -RUNTEST 100 TCK; -SDR 16 TDI (ADDF); -RUNTEST 100 TCK; -SDR 16 TDI (FB7C); -RUNTEST 100 TCK; -SDR 16 TDI (7FBF); -RUNTEST 100 TCK; -SDR 16 TDI (FDFF); -RUNTEST 100 TCK; -SDR 16 TDI (BDDF); -RUNTEST 100 TCK; -SDR 16 TDI (3775); -RUNTEST 100 TCK; -SDR 16 TDI (69FF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFD); -RUNTEST 100 TCK; -SDR 16 TDI (7FFE); -RUNTEST 100 TCK; -SDR 16 TDI (FBCC); -RUNTEST 100 TCK; -SDR 16 TDI (BF7F); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (773F); -RUNTEST 100 TCK; -SDR 16 TDI (FF7F); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFEF); -RUNTEST 100 TCK; -SDR 16 TDI (7FE7); -RUNTEST 100 TCK; -SDR 16 TDI (DFAF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7DFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (B55F); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (F7DD); -RUNTEST 100 TCK; -SDR 16 TDI (BFF7); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FF6); -RUNTEST 100 TCK; -SDR 16 TDI (FFDF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFDF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFE); -RUNTEST 100 TCK; -SDR 16 TDI (F7FF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFD); -RUNTEST 100 TCK; -SDR 16 TDI (FF75); -RUNTEST 100 TCK; -SDR 16 TDI (69FF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BAAF); -RUNTEST 100 TCK; -SDR 16 TDI (FEFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FEF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFE); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFE); -RUNTEST 100 TCK; -SDR 16 TDI (7FFD); -RUNTEST 100 TCK; -SDR 16 TDI (FFB9); -RUNTEST 100 TCK; -SDR 16 TDI (BDDF); -RUNTEST 100 TCK; -SDR 16 TDI (FBBA); -RUNTEST 100 TCK; -SDR 16 TDI (7DBB); -RUNTEST 100 TCK; -SDR 16 TDI (7FBF); -RUNTEST 100 TCK; -SDR 16 TDI (BBBF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7DFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFE); -RUNTEST 100 TCK; -SDR 16 TDI (6FFF); -RUNTEST 100 TCK; -SDR 16 TDI (D3F7); -RUNTEST 100 TCK; -SDR 16 TDI (B97F); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FAF); -RUNTEST 100 TCK; -SDR 16 TDI (FFEF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFF7); -RUNTEST 100 TCK; -SDR 16 TDI (7BFF); -RUNTEST 100 TCK; -SDR 16 TDI (EDEF); -RUNTEST 100 TCK; -SDR 16 TDI (BF77); -RUNTEST 100 TCK; -SDR 16 TDI (75FF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFBF); -RUNTEST 100 TCK; -SDR 16 TDI (7BFC); -RUNTEST 100 TCK; -SDR 16 TDI (FF7F); -RUNTEST 100 TCK; -SDR 16 TDI (BFFB); -RUNTEST 100 TCK; -SDR 16 TDI (77F9); -RUNTEST 100 TCK; -SDR 16 TDI (77FB); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FEF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FF7C); -RUNTEST 100 TCK; -SDR 16 TDI (6DF7); -RUNTEST 100 TCK; -SDR 16 TDI (3E9F); -RUNTEST 100 TCK; -SDR 16 TDI (BC7F); -RUNTEST 100 TCK; -SDR 16 TDI (33FD); -RUNTEST 100 TCK; -SDR 16 TDI (6FCA); -RUNTEST 100 TCK; -SDR 16 TDI (FFB6); -RUNTEST 100 TCK; -SDR 16 TDI (AFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FF21); -RUNTEST 100 TCK; -SDR 16 TDI (7DE7); -RUNTEST 100 TCK; -SDR 16 TDI (8FBF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BBBF); -RUNTEST 100 TCK; -SDR 16 TDI (FCFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FEF); -RUNTEST 100 TCK; -SDR 16 TDI (FBE3); -RUNTEST 100 TCK; -SDR 16 TDI (BFBB); -RUNTEST 100 TCK; -SDR 16 TDI (FFF7); -RUNTEST 100 TCK; -SDR 16 TDI (7F37); -RUNTEST 100 TCK; -SDR 16 TDI (FF4B); -RUNTEST 100 TCK; -SDR 16 TDI (B99F); -RUNTEST 100 TCK; -SDR 16 TDI (F9DE); -RUNTEST 100 TCK; -SDR 16 TDI (779B); -RUNTEST 100 TCK; -SDR 16 TDI (786F); -RUNTEST 100 TCK; -SDR 16 TDI (BDDC); -RUNTEST 100 TCK; -SDR 16 TDI (727F); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFBF); -RUNTEST 100 TCK; -SDR 16 TDI (77FC); -RUNTEST 100 TCK; -SDR 16 TDI (E57C); -RUNTEST 100 TCK; -SDR 16 TDI (A3F7); -RUNTEST 100 TCK; -SDR 16 TDI (FFFA); -RUNTEST 100 TCK; -SDR 16 TDI (77FD); -RUNTEST 100 TCK; -SDR 16 TDI (7FFD); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (6F7D); -RUNTEST 100 TCK; -SDR 16 TDI (FFDF); -RUNTEST 100 TCK; -SDR 16 TDI (BAAF); -RUNTEST 100 TCK; -SDR 16 TDI (8FFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (B66F); -RUNTEST 100 TCK; -SDR 16 TDI (FCFC); -RUNTEST 100 TCK; -SDR 16 TDI (67DE); -RUNTEST 100 TCK; -SDR 16 TDI (1FFA); -RUNTEST 100 TCK; -SDR 16 TDI (A000); -RUNTEST 100 TCK; -SDR 16 TDI (FFE0); -RUNTEST 100 TCK; -SDR 16 TDI (7882); -RUNTEST 100 TCK; -SDR 16 TDI (1F0F); -RUNTEST 100 TCK; -SDR 16 TDI (A61F); -RUNTEST 100 TCK; -SDR 16 TDI (7FE7); -RUNTEST 100 TCK; -SDR 16 TDI (7245); -RUNTEST 100 TCK; -SDR 16 TDI (A8EF); -RUNTEST 100 TCK; -SDR 16 TDI (B781); -RUNTEST 100 TCK; -SDR 16 TDI (80F5); -RUNTEST 100 TCK; -SDR 16 TDI (69FF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BEDF); -RUNTEST 100 TCK; -SDR 16 TDI (FC3C); -RUNTEST 100 TCK; -SDR 16 TDI (67A0); -RUNTEST 100 TCK; -SDR 16 TDI (1BA2); -RUNTEST 100 TCK; -SDR 16 TDI (A000); -RUNTEST 100 TCK; -SDR 16 TDI (FFD0); -RUNTEST 100 TCK; -SDR 16 TDI (7800); -RUNTEST 100 TCK; -SDR 16 TDI (1F0F); -RUNTEST 100 TCK; -SDR 16 TDI (A01E); -RUNTEST 100 TCK; -SDR 16 TDI (F9F6); -RUNTEST 100 TCK; -SDR 16 TDI (6280); -RUNTEST 100 TCK; -SDR 16 TDI (A8CF); -RUNTEST 100 TCK; -SDR 16 TDI (AF81); -RUNTEST 100 TCK; -SDR 16 TDI (907F); -RUNTEST 100 TCK; -SDR 16 TDI (7DFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (B77F); -RUNTEST 100 TCK; -SDR 16 TDI (FDFC); -RUNTEST 100 TCK; -SDR 16 TDI (67E7); -RUNTEST 100 TCK; -SDR 16 TDI (1FFB); -RUNTEST 100 TCK; -SDR 16 TDI (A230); -RUNTEST 100 TCK; -SDR 16 TDI (33F0); -RUNTEST 100 TCK; -SDR 16 TDI (6001); -RUNTEST 100 TCK; -SDR 16 TDI (9F0F); -RUNTEST 100 TCK; -SDR 16 TDI (BF9F); -RUNTEST 100 TCK; -SDR 16 TDI (FFE7); -RUNTEST 100 TCK; -SDR 16 TDI (7253); -RUNTEST 100 TCK; -SDR 16 TDI (00DF); -RUNTEST 100 TCK; -SDR 16 TDI (BF09); -RUNTEST 100 TCK; -SDR 16 TDI (80F5); -RUNTEST 100 TCK; -SDR 16 TDI (6BFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BDFF); -RUNTEST 100 TCK; -SDR 16 TDI (FDBE); -RUNTEST 100 TCK; -SDR 16 TDI (67E1); -RUNTEST 100 TCK; -SDR 16 TDI (01C2); -RUNTEST 100 TCK; -SDR 16 TDI (A030); -RUNTEST 100 TCK; -SDR 16 TDI (33F4); -RUNTEST 100 TCK; -SDR 16 TDI (6001); -RUNTEST 100 TCK; -SDR 16 TDI (9F7E); -RUNTEST 100 TCK; -SDR 16 TDI (BF9F); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (6290); -RUNTEST 100 TCK; -SDR 16 TDI (80DF); -RUNTEST 100 TCK; -SDR 16 TDI (BF09); -RUNTEST 100 TCK; -SDR 16 TDI (007F); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BAA7); -RUNTEST 100 TCK; -SDR 16 TDI (3332); -RUNTEST 100 TCK; -SDR 16 TDI (61E6); -RUNTEST 100 TCK; -SDR 16 TDI (EE6F); -RUNTEST 100 TCK; -SDR 16 TDI (A318); -RUNTEST 100 TCK; -SDR 16 TDI (11F2); -RUNTEST 100 TCK; -SDR 16 TDI (6144); -RUNTEST 100 TCK; -SDR 16 TDI (3CEC); -RUNTEST 100 TCK; -SDR 16 TDI (BDCF); -RUNTEST 100 TCK; -SDR 16 TDI (9BB8); -RUNTEST 100 TCK; -SDR 16 TDI (73C9); -RUNTEST 100 TCK; -SDR 16 TDI (CCE7); -RUNTEST 100 TCK; -SDR 16 TDI (B89C); -RUNTEST 100 TCK; -SDR 16 TDI (98FF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7777); -RUNTEST 100 TCK; -SDR 16 TDI (6952); -RUNTEST 100 TCK; -SDR 16 TDI (6767); -RUNTEST 100 TCK; -SDR 16 TDI (B773); -RUNTEST 100 TCK; -SDR 16 TDI (22A1); -RUNTEST 100 TCK; -SDR 16 TDI (6627); -RUNTEST 100 TCK; -SDR 16 TDI (7DCD); -RUNTEST 100 TCK; -SDR 16 TDI (B985); -RUNTEST 100 TCK; -SDR 16 TDI (599D); -RUNTEST 100 TCK; -SDR 16 TDI (79DD); -RUNTEST 100 TCK; -SDR 16 TDI (DDC2); -RUNTEST 100 TCK; -SDR 16 TDI (B5DD); -RUNTEST 100 TCK; -SDR 16 TDI (DDFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BEF7); -RUNTEST 100 TCK; -SDR 16 TDI (FFBF); -RUNTEST 100 TCK; -SDR 16 TDI (77CF); -RUNTEST 100 TCK; -SDR 16 TDI (FEFD); -RUNTEST 100 TCK; -SDR 16 TDI (BF99); -RUNTEST 100 TCK; -SDR 16 TDI (DFEE); -RUNTEST 100 TCK; -SDR 16 TDI (7DDD); -RUNTEST 100 TCK; -SDR 16 TDI (FFFE); -RUNTEST 100 TCK; -SDR 16 TDI (BFDF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (EEFF); -RUNTEST 100 TCK; -SDR 16 TDI (B3BB); -RUNTEST 100 TCK; -SDR 16 TDI (BBFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FF7); -RUNTEST 100 TCK; -SDR 16 TDI (FFFB); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (EBFA); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFF7); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FF7F); -RUNTEST 100 TCK; -SDR 16 TDI (7BFF); -RUNTEST 100 TCK; -SDR 16 TDI (BF7F); -RUNTEST 100 TCK; -SDR 16 TDI (BEFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFD7); -RUNTEST 100 TCK; -SDR 16 TDI (5FFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (F7F7); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7D7D); -RUNTEST 100 TCK; -SDR 16 TDI (DDFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FBFB); -RUNTEST 100 TCK; -SDR 16 TDI (6DFF); -RUNTEST 100 TCK; -SDR 16 TDI (FDFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFBF); -RUNTEST 100 TCK; -SDR 16 TDI (DBFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (EFEF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (D7FD); -RUNTEST 100 TCK; -SDR 16 TDI (7FFD); -RUNTEST 100 TCK; -SDR 16 TDI (DFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFE); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FEFF); -RUNTEST 100 TCK; -SDR 16 TDI (BEFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7DFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BBBF); -RUNTEST 100 TCK; -SDR 16 TDI (EFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FF7); -RUNTEST 100 TCK; -SDR 16 TDI (FFFD); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFB); -RUNTEST 100 TCK; -SDR 16 TDI (7D7F); -RUNTEST 100 TCK; -SDR 16 TDI (FDFB); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FF7F); -RUNTEST 100 TCK; -SDR 16 TDI (77FF); -RUNTEST 100 TCK; -SDR 16 TDI (BFBF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7DFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BEFB); -RUNTEST 100 TCK; -SDR 16 TDI (7FE7); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (7F7F); -RUNTEST 100 TCK; -SDR 16 TDI (BFBF); -RUNTEST 100 TCK; -SDR 16 TDI (F7FB); -RUNTEST 100 TCK; -SDR 16 TDI (737F); -RUNTEST 100 TCK; -SDR 16 TDI (DBFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFBF); -RUNTEST 100 TCK; -SDR 16 TDI (FDF6); -RUNTEST 100 TCK; -SDR 16 TDI (7DFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFDF); -RUNTEST 100 TCK; -SDR 16 TDI (7EFF); -RUNTEST 100 TCK; -SDR 16 TDI (77FF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFD); -RUNTEST 100 TCK; -SDR 16 TDI (F7FF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (F7DC); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FF7); -RUNTEST 100 TCK; -SDR 16 TDI (EFAF); -RUNTEST 100 TCK; -SDR 16 TDI (BCFF); -RUNTEST 100 TCK; -SDR 16 TDI (DFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7B7E); -RUNTEST 100 TCK; -SDR 16 TDI (DFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FDFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BF5D); -RUNTEST 100 TCK; -SDR 16 TDI (FEFF); -RUNTEST 100 TCK; -SDR 16 TDI (77FF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFD); -RUNTEST 100 TCK; -SDR 16 TDI (BF7F); -RUNTEST 100 TCK; -SDR 16 TDI (F7FF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFDF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (DEFF); -RUNTEST 100 TCK; -SDR 16 TDI (6BF9); -RUNTEST 100 TCK; -SDR 16 TDI (FBBF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BBDB); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (6EBF); -RUNTEST 100 TCK; -SDR 16 TDI (AFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFB); -RUNTEST 100 TCK; -SDR 16 TDI (6B77); -RUNTEST 100 TCK; -SDR 16 TDI (B77F); -RUNTEST 100 TCK; -SDR 16 TDI (BB5F); -RUNTEST 100 TCK; -SDR 16 TDI (FBF7); -RUNTEST 100 TCK; -SDR 16 TDI (7D7F); -RUNTEST 100 TCK; -SDR 16 TDI (DFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFDF); -RUNTEST 100 TCK; -SDR 16 TDI (FAFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BEFF); -RUNTEST 100 TCK; -SDR 16 TDI (FAFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFC); -RUNTEST 100 TCK; -SDR 16 TDI (BEFE); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FF7); -RUNTEST 100 TCK; -SDR 16 TDI (DFFD); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFB7); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFF7); -RUNTEST 100 TCK; -SDR 16 TDI (EFFB); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFEF); -RUNTEST 100 TCK; -SDR 16 TDI (7FEF); -RUNTEST 100 TCK; -SDR 16 TDI (7BFF); -RUNTEST 100 TCK; -SDR 16 TDI (BF77); -RUNTEST 100 TCK; -SDR 16 TDI (FFF7); -RUNTEST 100 TCK; -SDR 16 TDI (7CBD); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BBFF); -RUNTEST 100 TCK; -SDR 16 TDI (FEFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (F7FF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FDFE); -RUNTEST 100 TCK; -SDR 16 TDI (B96F); -RUNTEST 100 TCK; -SDR 16 TDI (FFFB); -RUNTEST 100 TCK; -SDR 16 TDI (7D75); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFF7); -RUNTEST 100 TCK; -SDR 16 TDI (7FFA); -RUNTEST 100 TCK; -SDR 16 TDI (FEFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFBB); -RUNTEST 100 TCK; -SDR 16 TDI (F37F); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BDFF); -RUNTEST 100 TCK; -SDR 16 TDI (FEDF); -RUNTEST 100 TCK; -SDR 16 TDI (77FE); -RUNTEST 100 TCK; -SDR 16 TDI (FFFD); -RUNTEST 100 TCK; -SDR 16 TDI (BFF9); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FBF); -RUNTEST 100 TCK; -SDR 16 TDI (5FFE); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFBF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFF7); -RUNTEST 100 TCK; -SDR 16 TDI (FFFB); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (B55F); -RUNTEST 100 TCK; -SDR 16 TDI (F7BF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFB); -RUNTEST 100 TCK; -SDR 16 TDI (EFEF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7BFD); -RUNTEST 100 TCK; -SDR 16 TDI (7BFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FDF); -RUNTEST 100 TCK; -SDR 16 TDI (BFBF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7DF4); -RUNTEST 100 TCK; -SDR 16 TDI (79FF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFD); -RUNTEST 100 TCK; -SDR 16 TDI (7FFE); -RUNTEST 100 TCK; -SDR 16 TDI (7FFE); -RUNTEST 100 TCK; -SDR 16 TDI (BF3A); -RUNTEST 100 TCK; -SDR 16 TDI (BBFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FF7); -RUNTEST 100 TCK; -SDR 16 TDI (BEFB); -RUNTEST 100 TCK; -SDR 16 TDI (ADFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFBB); -RUNTEST 100 TCK; -SDR 16 TDI (77D9); -RUNTEST 100 TCK; -SDR 16 TDI (7BBF); -RUNTEST 100 TCK; -SDR 16 TDI (BEF3); -RUNTEST 100 TCK; -SDR 16 TDI (EEFF); -RUNTEST 100 TCK; -SDR 16 TDI (7DFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (B55E); -RUNTEST 100 TCK; -SDR 16 TDI (FFF7); -RUNTEST 100 TCK; -SDR 16 TDI (6FEF); -RUNTEST 100 TCK; -SDR 16 TDI (FBFE); -RUNTEST 100 TCK; -SDR 16 TDI (BD9B); -RUNTEST 100 TCK; -SDR 16 TDI (FFF7); -RUNTEST 100 TCK; -SDR 16 TDI (777F); -RUNTEST 100 TCK; -SDR 16 TDI (FFFE); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FBFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (DDDF); -RUNTEST 100 TCK; -SDR 16 TDI (BD5F); -RUNTEST 100 TCK; -SDR 16 TDI (DF75); -RUNTEST 100 TCK; -SDR 16 TDI (69FF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (AAAF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7DEB); -RUNTEST 100 TCK; -SDR 16 TDI (DFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFB7); -RUNTEST 100 TCK; -SDR 16 TDI (FBFF); -RUNTEST 100 TCK; -SDR 16 TDI (6FF6); -RUNTEST 100 TCK; -SDR 16 TDI (DDFF); -RUNTEST 100 TCK; -SDR 16 TDI (ADFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFDF); -RUNTEST 100 TCK; -SDR 16 TDI (7EFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFEF); -RUNTEST 100 TCK; -SDR 16 TDI (6FFF); -RUNTEST 100 TCK; -SDR 16 TDI (7DFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (EEFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (DFFE); -RUNTEST 100 TCK; -SDR 16 TDI (7CFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFDB); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BEFF); -RUNTEST 100 TCK; -SDR 16 TDI (775B); -RUNTEST 100 TCK; -SDR 16 TDI (DFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFDF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFEF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFE); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (B6FF); -RUNTEST 100 TCK; -SDR 16 TDI (6FFB); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFD); -RUNTEST 100 TCK; -SDR 16 TDI (6CFB); -RUNTEST 100 TCK; -SDR 16 TDI (7DBF); -RUNTEST 100 TCK; -SDR 16 TDI (FEFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFD); -RUNTEST 100 TCK; -SDR 16 TDI (6DED); -RUNTEST 100 TCK; -SDR 16 TDI (F37F); -RUNTEST 100 TCK; -SDR 16 TDI (A77F); -RUNTEST 100 TCK; -SDR 16 TDI (CFFE); -RUNTEST 100 TCK; -SDR 16 TDI (7F76); -RUNTEST 100 TCK; -SDR 16 TDI (BFF3); -RUNTEST 100 TCK; -SDR 16 TDI (B7FD); -RUNTEST 100 TCK; -SDR 16 TDI (3AFB); -RUNTEST 100 TCK; -SDR 16 TDI (7717); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFF5); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BEEC); -RUNTEST 100 TCK; -SDR 16 TDI (FE5F); -RUNTEST 100 TCK; -SDR 16 TDI (7FFA); -RUNTEST 100 TCK; -SDR 16 TDI (7FFC); -RUNTEST 100 TCK; -SDR 16 TDI (B8BF); -RUNTEST 100 TCK; -SDR 16 TDI (77FB); -RUNTEST 100 TCK; -SDR 16 TDI (62EF); -RUNTEST 100 TCK; -SDR 16 TDI (FFCF); -RUNTEST 100 TCK; -SDR 16 TDI (ADBF); -RUNTEST 100 TCK; -SDR 16 TDI (FDFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FEB); -RUNTEST 100 TCK; -SDR 16 TDI (D45F); -RUNTEST 100 TCK; -SDR 16 TDI (BE5F); -RUNTEST 100 TCK; -SDR 16 TDI (566A); -RUNTEST 100 TCK; -SDR 16 TDI (77FF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (67F7); -RUNTEST 100 TCK; -SDR 16 TDI (7FF7); -RUNTEST 100 TCK; -SDR 16 TDI (9FD7); -RUNTEST 100 TCK; -SDR 16 TDI (BFE3); -RUNTEST 100 TCK; -SDR 16 TDI (BBF5); -RUNTEST 100 TCK; -SDR 16 TDI (7DFF); -RUNTEST 100 TCK; -SDR 16 TDI (5CFD); -RUNTEST 100 TCK; -SDR 16 TDI (BBFF); -RUNTEST 100 TCK; -SDR 16 TDI (D71D); -RUNTEST 100 TCK; -SDR 16 TDI (78FD); -RUNTEST 100 TCK; -SDR 16 TDI (AFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BDAE); -RUNTEST 100 TCK; -SDR 16 TDI (EDFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (B99D); -RUNTEST 100 TCK; -SDR 16 TDI (69FC); -RUNTEST 100 TCK; -SDR 16 TDI (67C0); -RUNTEST 100 TCK; -SDR 16 TDI (0B9E); -RUNTEST 100 TCK; -SDR 16 TDI (B4A0); -RUNTEST 100 TCK; -SDR 16 TDI (03EE); -RUNTEST 100 TCK; -SDR 16 TDI (7580); -RUNTEST 100 TCK; -SDR 16 TDI (1302); -RUNTEST 100 TCK; -SDR 16 TDI (A01E); -RUNTEST 100 TCK; -SDR 16 TDI (1819); -RUNTEST 100 TCK; -SDR 16 TDI (70AF); -RUNTEST 100 TCK; -SDR 16 TDI (FC0F); -RUNTEST 100 TCK; -SDR 16 TDI (B079); -RUNTEST 100 TCK; -SDR 16 TDI (87F5); -RUNTEST 100 TCK; -SDR 16 TDI (6BFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (ABFE); -RUNTEST 100 TCK; -SDR 16 TDI (E9C3); -RUNTEST 100 TCK; -SDR 16 TDI (67A0); -RUNTEST 100 TCK; -SDR 16 TDI (0BE0); -RUNTEST 100 TCK; -SDR 16 TDI (A0A0); -RUNTEST 100 TCK; -SDR 16 TDI (03D0); -RUNTEST 100 TCK; -SDR 16 TDI (7580); -RUNTEST 100 TCK; -SDR 16 TDI (1302); -RUNTEST 100 TCK; -SDR 16 TDI (B41B); -RUNTEST 100 TCK; -SDR 16 TDI (9F99); -RUNTEST 100 TCK; -SDR 16 TDI (70AB); -RUNTEST 100 TCK; -SDR 16 TDI (0C0F); -RUNTEST 100 TCK; -SDR 16 TDI (AAA9); -RUNTEST 100 TCK; -SDR 16 TDI (D07F); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BD5D); -RUNTEST 100 TCK; -SDR 16 TDI (9283); -RUNTEST 100 TCK; -SDR 16 TDI (7FF0); -RUNTEST 100 TCK; -SDR 16 TDI (2C60); -RUNTEST 100 TCK; -SDR 16 TDI (AA40); -RUNTEST 100 TCK; -SDR 16 TDI (E3FF); -RUNTEST 100 TCK; -SDR 16 TDI (6C06); -RUNTEST 100 TCK; -SDR 16 TDI (30C7); -RUNTEST 100 TCK; -SDR 16 TDI (A47F); -RUNTEST 100 TCK; -SDR 16 TDI (E066); -RUNTEST 100 TCK; -SDR 16 TDI (610F); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (B86C); -RUNTEST 100 TCK; -SDR 16 TDI (84F5); -RUNTEST 100 TCK; -SDR 16 TDI (6BFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFE); -RUNTEST 100 TCK; -SDR 16 TDI (D2B0); -RUNTEST 100 TCK; -SDR 16 TDI (67F6); -RUNTEST 100 TCK; -SDR 16 TDI (0D86); -RUNTEST 100 TCK; -SDR 16 TDI (A040); -RUNTEST 100 TCK; -SDR 16 TDI (C3F0); -RUNTEST 100 TCK; -SDR 16 TDI (7C06); -RUNTEST 100 TCK; -SDR 16 TDI (10C1); -RUNTEST 100 TCK; -SDR 16 TDI (A07F); -RUNTEST 100 TCK; -SDR 16 TDI (9DE6); -RUNTEST 100 TCK; -SDR 16 TDI (6083); -RUNTEST 100 TCK; -SDR 16 TDI (3C0F); -RUNTEST 100 TCK; -SDR 16 TDI (BCC8); -RUNTEST 100 TCK; -SDR 16 TDI (07FF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BAA7); -RUNTEST 100 TCK; -SDR 16 TDI (BBBB); -RUNTEST 100 TCK; -SDR 16 TDI (71EE); -RUNTEST 100 TCK; -SDR 16 TDI (2EEF); -RUNTEST 100 TCK; -SDR 16 TDI (B219); -RUNTEST 100 TCK; -SDR 16 TDI (31F1); -RUNTEST 100 TCK; -SDR 16 TDI (6286); -RUNTEST 100 TCK; -SDR 16 TDI (38CF); -RUNTEST 100 TCK; -SDR 16 TDI (B9AF); -RUNTEST 100 TCK; -SDR 16 TDI (9999); -RUNTEST 100 TCK; -SDR 16 TDI (71CF); -RUNTEST 100 TCK; -SDR 16 TDI (CEC7); -RUNTEST 100 TCK; -SDR 16 TDI (BA9C); -RUNTEST 100 TCK; -SDR 16 TDI (9BFE); -RUNTEST 100 TCK; -SDR 16 TDI (77FF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFF7); -RUNTEST 100 TCK; -SDR 16 TDI (1111); -RUNTEST 100 TCK; -SDR 16 TDI (6167); -RUNTEST 100 TCK; -SDR 16 TDI (6445); -RUNTEST 100 TCK; -SDR 16 TDI (B763); -RUNTEST 100 TCK; -SDR 16 TDI (36A9); -RUNTEST 100 TCK; -SDR 16 TDI (7677); -RUNTEST 100 TCK; -SDR 16 TDI (79DC); -RUNTEST 100 TCK; -SDR 16 TDI (BBA5); -RUNTEST 100 TCK; -SDR 16 TDI (19D9); -RUNTEST 100 TCK; -SDR 16 TDI (79DC); -RUNTEST 100 TCK; -SDR 16 TDI (DC9A); -RUNTEST 100 TCK; -SDR 16 TDI (B1CD); -RUNTEST 100 TCK; -SDR 16 TDI (D9FF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFD); -RUNTEST 100 TCK; -SDR 16 TDI (DDDD); -RUNTEST 100 TCK; -SDR 16 TDI (7FDF); -RUNTEST 100 TCK; -SDR 16 TDI (FDDD); -RUNTEST 100 TCK; -SDR 16 TDI (BBDD); -RUNTEST 100 TCK; -SDR 16 TDI (BBEF); -RUNTEST 100 TCK; -SDR 16 TDI (7FCF); -RUNTEST 100 TCK; -SDR 16 TDI (FEF7); -RUNTEST 100 TCK; -SDR 16 TDI (BFC7); -RUNTEST 100 TCK; -SDR 16 TDI (7FBF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (EFEF); -RUNTEST 100 TCK; -SDR 16 TDI (B77F); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (EFFF); -RUNTEST 100 TCK; -SDR 16 TDI (6FEF); -RUNTEST 100 TCK; -SDR 16 TDI (FDF7); -RUNTEST 100 TCK; -SDR 16 TDI (BF77); -RUNTEST 100 TCK; -SDR 16 TDI (EBFA); -RUNTEST 100 TCK; -SDR 16 TDI (7FEE); -RUNTEST 100 TCK; -SDR 16 TDI (DF7F); -RUNTEST 100 TCK; -SDR 16 TDI (BEBF); -RUNTEST 100 TCK; -SDR 16 TDI (F7DF); -RUNTEST 100 TCK; -SDR 16 TDI (6DFB); -RUNTEST 100 TCK; -SDR 16 TDI (FEDF); -RUNTEST 100 TCK; -SDR 16 TDI (BD7F); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FD7F); -RUNTEST 100 TCK; -SDR 16 TDI (7FFE); -RUNTEST 100 TCK; -SDR 16 TDI (FF3F); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (77FF); -RUNTEST 100 TCK; -SDR 16 TDI (FFF7); -RUNTEST 100 TCK; -SDR 16 TDI (BBFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7BFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (F7DF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (DD7F); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FB7F); -RUNTEST 100 TCK; -SDR 16 TDI (BFF7); -RUNTEST 100 TCK; -SDR 16 TDI (BBFD); -RUNTEST 100 TCK; -SDR 16 TDI (7FFE); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BBBF); -RUNTEST 100 TCK; -SDR 16 TDI (EFDF); -RUNTEST 100 TCK; -SDR 16 TDI (6BF7); -RUNTEST 100 TCK; -SDR 16 TDI (FFDF); -RUNTEST 100 TCK; -SDR 16 TDI (BEFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFBF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (77F7); -RUNTEST 100 TCK; -SDR 16 TDI (FFEF); -RUNTEST 100 TCK; -SDR 16 TDI (BF7F); -RUNTEST 100 TCK; -SDR 16 TDI (EFFB); -RUNTEST 100 TCK; -SDR 16 TDI (77EF); -RUNTEST 100 TCK; -SDR 16 TDI (FF77); -RUNTEST 100 TCK; -SDR 16 TDI (BEFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7EFF); -RUNTEST 100 TCK; -SDR 16 TDI (FDFF); -RUNTEST 100 TCK; SDR 16 TDI (BDFF); RUNTEST 100 TCK; SDR 16 TDI (F7FF); RUNTEST 100 TCK; SDR 16 TDI (7FFF); RUNTEST 100 TCK; -SDR 16 TDI (FFFF); +SDR 16 TDI (BF7F); RUNTEST 100 TCK; -SDR 16 TDI (BBBF); +SDR 16 TDI (BFFF); RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (DFFB); -RUNTEST 100 TCK; -SDR 16 TDI (BFBF); -RUNTEST 100 TCK; -SDR 16 TDI (F7FF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFB); -RUNTEST 100 TCK; -SDR 16 TDI (DBED); -RUNTEST 100 TCK; -SDR 16 TDI (BD3F); -RUNTEST 100 TCK; -SDR 16 TDI (FEF7); -RUNTEST 100 TCK; -SDR 16 TDI (66FF); -RUNTEST 100 TCK; -SDR 16 TDI (FFEF); -RUNTEST 100 TCK; -SDR 16 TDI (BFF7); -RUNTEST 100 TCK; -SDR 16 TDI (FFFB); +SDR 16 TDI (FFFE); RUNTEST 100 TCK; SDR 16 TDI (7FFF); RUNTEST 100 TCK; SDR 16 TDI (FFFF); RUNTEST 100 TCK; -SDR 16 TDI (BFFE); +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FBFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); RUNTEST 100 TCK; SDR 16 TDI (FFFF); RUNTEST 100 TCK; -SDR 16 TDI (7FF3); -RUNTEST 100 TCK; -SDR 16 TDI (F7FE); -RUNTEST 100 TCK; -SDR 16 TDI (BBDE); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FF7); -RUNTEST 100 TCK; -SDR 16 TDI (EF7F); -RUNTEST 100 TCK; SDR 16 TDI (BFFF); RUNTEST 100 TCK; SDR 16 TDI (FFFF); RUNTEST 100 TCK; -SDR 16 TDI (7FB7); +SDR 16 TDI (7FBF); RUNTEST 100 TCK; -SDR 16 TDI (EFBF); +SDR 16 TDI (EFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BF7F); +RUNTEST 100 TCK; +SDR 16 TDI (FFBF); +RUNTEST 100 TCK; +SDR 16 TDI (7FBF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BBFB); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); RUNTEST 100 TCK; SDR 16 TDI (BFFF); RUNTEST 100 TCK; -SDR 16 TDI (BFFF); +SDR 16 TDI (FFFF); RUNTEST 100 TCK; SDR 16 TDI (7FFF); RUNTEST 100 TCK; @@ -2303,671 +359,79 @@ SDR 16 TDI (FFFF); RUNTEST 100 TCK; SDR 16 TDI (BDF7); RUNTEST 100 TCK; -SDR 16 TDI (7EEB); +SDR 16 TDI (FFFF); RUNTEST 100 TCK; -SDR 16 TDI (77FF); +SDR 16 TDI (7DFF); RUNTEST 100 TCK; -SDR 16 TDI (FFBF); -RUNTEST 100 TCK; -SDR 16 TDI (B77D); +SDR 16 TDI (EBFF); RUNTEST 100 TCK; SDR 16 TDI (BFFF); RUNTEST 100 TCK; -SDR 16 TDI (6EFE); -RUNTEST 100 TCK; -SDR 16 TDI (DF5F); -RUNTEST 100 TCK; -SDR 16 TDI (BEFF); -RUNTEST 100 TCK; -SDR 16 TDI (BBFB); -RUNTEST 100 TCK; -SDR 16 TDI (7BFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BBFF); -RUNTEST 100 TCK; -SDR 16 TDI (FBF7); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFD); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FEB); -RUNTEST 100 TCK; -SDR 16 TDI (D7FB); -RUNTEST 100 TCK; -SDR 16 TDI (AFDF); -RUNTEST 100 TCK; -SDR 16 TDI (F7FF); -RUNTEST 100 TCK; -SDR 16 TDI (7FF3); -RUNTEST 100 TCK; -SDR 16 TDI (F7FD); -RUNTEST 100 TCK; -SDR 16 TDI (BDDF); -RUNTEST 100 TCK; -SDR 16 TDI (FF76); -RUNTEST 100 TCK; -SDR 16 TDI (7D7B); -RUNTEST 100 TCK; -SDR 16 TDI (EF5F); -RUNTEST 100 TCK; -SDR 16 TDI (BFEF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BAFF); -RUNTEST 100 TCK; -SDR 16 TDI (F9FF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (BF7B); -RUNTEST 100 TCK; -SDR 16 TDI (BFFB); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7BDD); -RUNTEST 100 TCK; -SDR 16 TDI (F7FB); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FF6F); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (AFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFDF); -RUNTEST 100 TCK; -SDR 16 TDI (7FEF); -RUNTEST 100 TCK; -SDR 16 TDI (7FEF); -RUNTEST 100 TCK; -SDR 16 TDI (BEFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFF7); -RUNTEST 100 TCK; -SDR 16 TDI (6FFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFD); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFBE); -RUNTEST 100 TCK; -SDR 16 TDI (7FDF); -RUNTEST 100 TCK; -SDR 16 TDI (FBFF); -RUNTEST 100 TCK; -SDR 16 TDI (BBEF); -RUNTEST 100 TCK; -SDR 16 TDI (7EFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (B7FF); -RUNTEST 100 TCK; -SDR 16 TDI (F7FF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BDBF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7EFF); -RUNTEST 100 TCK; -SDR 16 TDI (77FF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FB7B); -RUNTEST 100 TCK; -SDR 16 TDI (6FFE); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BDBF); -RUNTEST 100 TCK; -SDR 16 TDI (737F); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BEFF); -RUNTEST 100 TCK; -SDR 16 TDI (FEEF); -RUNTEST 100 TCK; -SDR 16 TDI (77FE); -RUNTEST 100 TCK; -SDR 16 TDI (DEEB); -RUNTEST 100 TCK; -SDR 16 TDI (BFF7); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (6BBB); -RUNTEST 100 TCK; -SDR 16 TDI (FFFA); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFAF); -RUNTEST 100 TCK; -SDR 16 TDI (7FEF); -RUNTEST 100 TCK; -SDR 16 TDI (FBFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFF7); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (B7FF); -RUNTEST 100 TCK; -SDR 16 TDI (77FF); -RUNTEST 100 TCK; -SDR 16 TDI (EFF7); -RUNTEST 100 TCK; -SDR 16 TDI (BF7F); -RUNTEST 100 TCK; -SDR 16 TDI (77FF); -RUNTEST 100 TCK; -SDR 16 TDI (7DD5); -RUNTEST 100 TCK; -SDR 16 TDI (F7FF); -RUNTEST 100 TCK; -SDR 16 TDI (B7DF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFD); -RUNTEST 100 TCK; -SDR 16 TDI (7EF7); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFEF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFD); -RUNTEST 100 TCK; -SDR 16 TDI (7BFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BB7F); -RUNTEST 100 TCK; -SDR 16 TDI (FFFE); -RUNTEST 100 TCK; -SDR 16 TDI (7FFD); -RUNTEST 100 TCK; -SDR 16 TDI (DF3B); -RUNTEST 100 TCK; -SDR 16 TDI (B5FF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFE); -RUNTEST 100 TCK; -SDR 16 TDI (777F); -RUNTEST 100 TCK; -SDR 16 TDI (5FEF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFE); -RUNTEST 100 TCK; -SDR 16 TDI (F7FF); -RUNTEST 100 TCK; -SDR 16 TDI (6B7F); -RUNTEST 100 TCK; -SDR 16 TDI (FF5F); -RUNTEST 100 TCK; -SDR 16 TDI (BFBF); -RUNTEST 100 TCK; -SDR 16 TDI (F5FF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (B7BE); -RUNTEST 100 TCK; -SDR 16 TDI (FF7B); -RUNTEST 100 TCK; -SDR 16 TDI (7FF7); -RUNTEST 100 TCK; -SDR 16 TDI (7BFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFF7); -RUNTEST 100 TCK; -SDR 16 TDI (FFFB); -RUNTEST 100 TCK; -SDR 16 TDI (7FDB); -RUNTEST 100 TCK; -SDR 16 TDI (BFFD); -RUNTEST 100 TCK; -SDR 16 TDI (AFFF); -RUNTEST 100 TCK; -SDR 16 TDI (CBDE); -RUNTEST 100 TCK; -SDR 16 TDI (7DEB); -RUNTEST 100 TCK; -SDR 16 TDI (EFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BCFB); -RUNTEST 100 TCK; -SDR 16 TDI (BF7D); -RUNTEST 100 TCK; -SDR 16 TDI (7BFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (AFFB); -RUNTEST 100 TCK; -SDR 16 TDI (DFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FDDE); -RUNTEST 100 TCK; -SDR 16 TDI (BD3F); -RUNTEST 100 TCK; -SDR 16 TDI (FFEF); -RUNTEST 100 TCK; -SDR 16 TDI (7FEE); -RUNTEST 100 TCK; -SDR 16 TDI (FFEB); -RUNTEST 100 TCK; -SDR 16 TDI (BBDB); -RUNTEST 100 TCK; -SDR 16 TDI (BFFB); -RUNTEST 100 TCK; -SDR 16 TDI (77FF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (EEFF); -RUNTEST 100 TCK; -SDR 16 TDI (7DFD); -RUNTEST 100 TCK; -SDR 16 TDI (DFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BDDD); -RUNTEST 100 TCK; -SDR 16 TDI (FFFD); -RUNTEST 100 TCK; -SDR 16 TDI (6B7F); -RUNTEST 100 TCK; -SDR 16 TDI (FBF7); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FD7D); -RUNTEST 100 TCK; -SDR 16 TDI (7B7F); -RUNTEST 100 TCK; -SDR 16 TDI (7F7F); -RUNTEST 100 TCK; -SDR 16 TDI (BFEF); -RUNTEST 100 TCK; -SDR 16 TDI (EDFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFE); -RUNTEST 100 TCK; -SDR 16 TDI (FFEF); -RUNTEST 100 TCK; -SDR 16 TDI (7FF7); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (AFBE); -RUNTEST 100 TCK; -SDR 16 TDI (EFF7); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BF7F); -RUNTEST 100 TCK; -SDR 16 TDI (FF5F); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (EEFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7F7F); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFD); -RUNTEST 100 TCK; -SDR 16 TDI (FFF5); -RUNTEST 100 TCK; -SDR 16 TDI (7DE0); -RUNTEST 100 TCK; -SDR 16 TDI (13F6); -RUNTEST 100 TCK; -SDR 16 TDI (AEFD); -RUNTEST 100 TCK; -SDR 16 TDI (4FFF); -RUNTEST 100 TCK; -SDR 16 TDI (6C97); -RUNTEST 100 TCK; -SDR 16 TDI (B3EF); -RUNTEST 100 TCK; -SDR 16 TDI (A77F); -RUNTEST 100 TCK; -SDR 16 TDI (F9F9); -RUNTEST 100 TCK; -SDR 16 TDI (7676); -RUNTEST 100 TCK; -SDR 16 TDI (FE6F); -RUNTEST 100 TCK; -SDR 16 TDI (BBE9); -RUNTEST 100 TCK; -SDR 16 TDI (33FF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BDFE); -RUNTEST 100 TCK; -SDR 16 TDI (FEDF); -RUNTEST 100 TCK; -SDR 16 TDI (6FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFD); -RUNTEST 100 TCK; -SDR 16 TDI (B5F2); -RUNTEST 100 TCK; -SDR 16 TDI (FFFC); -RUNTEST 100 TCK; -SDR 16 TDI (7F7B); -RUNTEST 100 TCK; -SDR 16 TDI (DEDA); -RUNTEST 100 TCK; -SDR 16 TDI (BCFF); -RUNTEST 100 TCK; -SDR 16 TDI (F7EF); -RUNTEST 100 TCK; -SDR 16 TDI (7FCF); -RUNTEST 100 TCK; -SDR 16 TDI (DFFB); -RUNTEST 100 TCK; -SDR 16 TDI (BFF7); -RUNTEST 100 TCK; -SDR 16 TDI (CD6A); -RUNTEST 100 TCK; -SDR 16 TDI (77FF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (677F); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FF5F); -RUNTEST 100 TCK; -SDR 16 TDI (BF2F); -RUNTEST 100 TCK; -SDR 16 TDI (F7F3); -RUNTEST 100 TCK; -SDR 16 TDI (73FD); -RUNTEST 100 TCK; -SDR 16 TDI (7FFD); -RUNTEST 100 TCK; -SDR 16 TDI (BF9E); -RUNTEST 100 TCK; -SDR 16 TDI (CE1E); -RUNTEST 100 TCK; -SDR 16 TDI (69BB); -RUNTEST 100 TCK; -SDR 16 TDI (2F9F); -RUNTEST 100 TCK; -SDR 16 TDI (BC9F); -RUNTEST 100 TCK; SDR 16 TDI (FEFF); RUNTEST 100 TCK; SDR 16 TDI (7FFF); RUNTEST 100 TCK; SDR 16 TDI (FFFF); RUNTEST 100 TCK; -SDR 16 TDI (BBAD); +SDR 16 TDI (BFFF); RUNTEST 100 TCK; -SDR 16 TDI (69FC); +SDR 16 TDI (FFFE); RUNTEST 100 TCK; -SDR 16 TDI (67C2); -RUNTEST 100 TCK; -SDR 16 TDI (0B9E); -RUNTEST 100 TCK; -SDR 16 TDI (A130); -RUNTEST 100 TCK; -SDR 16 TDI (EFEF); -RUNTEST 100 TCK; -SDR 16 TDI (7404); -RUNTEST 100 TCK; -SDR 16 TDI (BC00); -RUNTEST 100 TCK; -SDR 16 TDI (B17F); -RUNTEST 100 TCK; -SDR 16 TDI (0100); -RUNTEST 100 TCK; -SDR 16 TDI (6888); -RUNTEST 100 TCK; -SDR 16 TDI (5C1F); -RUNTEST 100 TCK; -SDR 16 TDI (B768); -RUNTEST 100 TCK; -SDR 16 TDI (0075); -RUNTEST 100 TCK; -SDR 16 TDI (6BFF); +SDR 16 TDI (6FFF); RUNTEST 100 TCK; SDR 16 TDI (FFFF); RUNTEST 100 TCK; -SDR 16 TDI (BF5E); +SDR 16 TDI (BFFF); RUNTEST 100 TCK; -SDR 16 TDI (E9C3); -RUNTEST 100 TCK; -SDR 16 TDI (67A0); -RUNTEST 100 TCK; -SDR 16 TDI (0BE0); -RUNTEST 100 TCK; -SDR 16 TDI (A3F0); -RUNTEST 100 TCK; -SDR 16 TDI (8FDE); -RUNTEST 100 TCK; -SDR 16 TDI (78A7); -RUNTEST 100 TCK; -SDR 16 TDI (BA00); -RUNTEST 100 TCK; -SDR 16 TDI (A11E); -RUNTEST 100 TCK; -SDR 16 TDI (8002); -RUNTEST 100 TCK; -SDR 16 TDI (6000); -RUNTEST 100 TCK; -SDR 16 TDI (5C2F); -RUNTEST 100 TCK; -SDR 16 TDI (AF08); -RUNTEST 100 TCK; -SDR 16 TDI (10FF); +SDR 16 TDI (F7FF); RUNTEST 100 TCK; SDR 16 TDI (7FFF); RUNTEST 100 TCK; SDR 16 TDI (FFFF); RUNTEST 100 TCK; -SDR 16 TDI (B5FD); -RUNTEST 100 TCK; -SDR 16 TDI (9283); -RUNTEST 100 TCK; -SDR 16 TDI (7FE0); -RUNTEST 100 TCK; -SDR 16 TDI (4C61); -RUNTEST 100 TCK; -SDR 16 TDI (A538); -RUNTEST 100 TCK; -SDR 16 TDI (EFF3); -RUNTEST 100 TCK; -SDR 16 TDI (6066); -RUNTEST 100 TCK; -SDR 16 TDI (1CC8); -RUNTEST 100 TCK; -SDR 16 TDI (B19F); -RUNTEST 100 TCK; -SDR 16 TDI (C208); -RUNTEST 100 TCK; -SDR 16 TDI (6078); -RUNTEST 100 TCK; -SDR 16 TDI (BC6F); -RUNTEST 100 TCK; -SDR 16 TDI (BF99); -RUNTEST 100 TCK; -SDR 16 TDI (F875); -RUNTEST 100 TCK; -SDR 16 TDI (6BFF); +SDR 16 TDI (BFFF); RUNTEST 100 TCK; SDR 16 TDI (FFFF); RUNTEST 100 TCK; -SDR 16 TDI (BDFE); +SDR 16 TDI (7DDF); RUNTEST 100 TCK; -SDR 16 TDI (D2B0); +SDR 16 TDI (FFFF); RUNTEST 100 TCK; -SDR 16 TDI (67E0); +SDR 16 TDI (BFFF); RUNTEST 100 TCK; -SDR 16 TDI (0D86); +SDR 16 TDI (FFFF); RUNTEST 100 TCK; -SDR 16 TDI (A338); +SDR 16 TDI (7FBF); RUNTEST 100 TCK; -SDR 16 TDI (2FFC); +SDR 16 TDI (FFFF); RUNTEST 100 TCK; -SDR 16 TDI (6126); +SDR 16 TDI (BDFF); RUNTEST 100 TCK; -SDR 16 TDI (19C8); +SDR 16 TDI (FFFF); RUNTEST 100 TCK; -SDR 16 TDI (A19F); +SDR 16 TDI (6FFF); RUNTEST 100 TCK; -SDR 16 TDI (E00A); +SDR 16 TDI (FFFF); RUNTEST 100 TCK; -SDR 16 TDI (70F0); +SDR 16 TDI (BFFF); RUNTEST 100 TCK; -SDR 16 TDI (9C1F); -RUNTEST 100 TCK; -SDR 16 TDI (BF98); -RUNTEST 100 TCK; -SDR 16 TDI (787F); +SDR 16 TDI (FFFF); RUNTEST 100 TCK; SDR 16 TDI (7FFF); RUNTEST 100 TCK; SDR 16 TDI (FFFF); RUNTEST 100 TCK; -SDR 16 TDI (BA3F); -RUNTEST 100 TCK; -SDR 16 TDI (BBBB); -RUNTEST 100 TCK; -SDR 16 TDI (71E6); -RUNTEST 100 TCK; -SDR 16 TDI (6EEF); -RUNTEST 100 TCK; -SDR 16 TDI (B333); -RUNTEST 100 TCK; -SDR 16 TDI (75F3); -RUNTEST 100 TCK; -SDR 16 TDI (6E7F); -RUNTEST 100 TCK; -SDR 16 TDI (7EE8); -RUNTEST 100 TCK; -SDR 16 TDI (B9CF); -RUNTEST 100 TCK; -SDR 16 TDI (D98B); -RUNTEST 100 TCK; -SDR 16 TDI (71E8); -RUNTEST 100 TCK; -SDR 16 TDI (8E83); -RUNTEST 100 TCK; -SDR 16 TDI (B998); -RUNTEST 100 TCK; -SDR 16 TDI (89FA); -RUNTEST 100 TCK; -SDR 16 TDI (77FF); +SDR 16 TDI (BEF7); RUNTEST 100 TCK; SDR 16 TDI (FFFF); RUNTEST 100 TCK; -SDR 16 TDI (BD7F); +SDR 16 TDI (7FFF); RUNTEST 100 TCK; -SDR 16 TDI (1111); +SDR 16 TDI (FFFF); RUNTEST 100 TCK; -SDR 16 TDI (6177); +SDR 16 TDI (BF7F); RUNTEST 100 TCK; -SDR 16 TDI (2445); -RUNTEST 100 TCK; -SDR 16 TDI (B777); -RUNTEST 100 TCK; -SDR 16 TDI (74AB); -RUNTEST 100 TCK; -SDR 16 TDI (6767); -RUNTEST 100 TCK; -SDR 16 TDI (7CCD); -RUNTEST 100 TCK; -SDR 16 TDI (BB85); -RUNTEST 100 TCK; -SDR 16 TDI (5DD9); -RUNTEST 100 TCK; -SDR 16 TDI (7BCD); -RUNTEST 100 TCK; -SDR 16 TDI (DCD2); -RUNTEST 100 TCK; -SDR 16 TDI (B5DD); -RUNTEST 100 TCK; -SDR 16 TDI (D9FF); +SDR 16 TDI (FFDF); RUNTEST 100 TCK; SDR 16 TDI (7FFF); RUNTEST 100 TCK; @@ -2975,27 +439,771 @@ SDR 16 TDI (FFFF); RUNTEST 100 TCK; SDR 16 TDI (BFFD); RUNTEST 100 TCK; -SDR 16 TDI (DDDD); +SDR 16 TDI (FFFE); RUNTEST 100 TCK; -SDR 16 TDI (7FCF); +SDR 16 TDI (7FFF); RUNTEST 100 TCK; -SDR 16 TDI (FDDD); +SDR 16 TDI (FFFF); RUNTEST 100 TCK; -SDR 16 TDI (BBBB); +SDR 16 TDI (BFFF); RUNTEST 100 TCK; -SDR 16 TDI (FFE7); +SDR 16 TDI (FFF7); RUNTEST 100 TCK; -SDR 16 TDI (7EFF); +SDR 16 TDI (7FFF); RUNTEST 100 TCK; -SDR 16 TDI (F7FF); +SDR 16 TDI (FFFF); RUNTEST 100 TCK; -SDR 16 TDI (BCEF); +SDR 16 TDI (BFDF); RUNTEST 100 TCK; -SDR 16 TDI (3FFF); +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFB); +RUNTEST 100 TCK; +SDR 16 TDI (EFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFBF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (DFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); RUNTEST 100 TCK; SDR 16 TDI (77FF); RUNTEST 100 TCK; -SDR 16 TDI (E7FF); +SDR 16 TDI (FF7E); +RUNTEST 100 TCK; +SDR 16 TDI (BF7F); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (A7FF); +RUNTEST 100 TCK; +SDR 16 TDI (B7FF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7B7B); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BDF7); +RUNTEST 100 TCK; +SDR 16 TDI (DDFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFE); +RUNTEST 100 TCK; +SDR 16 TDI (FEFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FEE); +RUNTEST 100 TCK; +SDR 16 TDI (FFFB); +RUNTEST 100 TCK; +SDR 16 TDI (BBFE); +RUNTEST 100 TCK; +SDR 16 TDI (FFF7); +RUNTEST 100 TCK; +SDR 16 TDI (6FBF); +RUNTEST 100 TCK; +SDR 16 TDI (E7AF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (AFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7DFF); +RUNTEST 100 TCK; +SDR 16 TDI (DFBF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (DFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFB); +RUNTEST 100 TCK; +SDR 16 TDI (6FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FF7F); +RUNTEST 100 TCK; +SDR 16 TDI (AFAF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFD); +RUNTEST 100 TCK; +SDR 16 TDI (DFFF); +RUNTEST 100 TCK; +SDR 16 TDI (AFBF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (77B7); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BBEF); +RUNTEST 100 TCK; +SDR 16 TDI (FBFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7F7F); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BDFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (EFFB); +RUNTEST 100 TCK; +SDR 16 TDI (BDFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFE); +RUNTEST 100 TCK; +SDR 16 TDI (7DFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFB); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFE); +RUNTEST 100 TCK; +SDR 16 TDI (EFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FEF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFD); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFF7); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (DFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FEFF); +RUNTEST 100 TCK; +SDR 16 TDI (BBFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFD); +RUNTEST 100 TCK; +SDR 16 TDI (DFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFD); +RUNTEST 100 TCK; +SDR 16 TDI (BDFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFF7); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (DFBF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (6FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BBFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FBF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (EFFB); +RUNTEST 100 TCK; +SDR 16 TDI (BBFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7DFF); +RUNTEST 100 TCK; +SDR 16 TDI (BEFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFD); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (B55F); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (6FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BBFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (F9AA); +RUNTEST 100 TCK; +SDR 16 TDI (B3FF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFA); +RUNTEST 100 TCK; +SDR 16 TDI (75FF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BBBF); +RUNTEST 100 TCK; +SDR 16 TDI (FFF5); +RUNTEST 100 TCK; +SDR 16 TDI (69FF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FDFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFD); +RUNTEST 100 TCK; +SDR 16 TDI (FFBF); +RUNTEST 100 TCK; +SDR 16 TDI (AF6B); +RUNTEST 100 TCK; +SDR 16 TDI (EF7F); +RUNTEST 100 TCK; +SDR 16 TDI (7FFB); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFBF); +RUNTEST 100 TCK; +SDR 16 TDI (B7EF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFEF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7DFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (B55F); +RUNTEST 100 TCK; +SDR 16 TDI (FF7F); +RUNTEST 100 TCK; +SDR 16 TDI (7FF7); +RUNTEST 100 TCK; +SDR 16 TDI (FF77); +RUNTEST 100 TCK; +SDR 16 TDI (AFDF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FBF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFD); +RUNTEST 100 TCK; +SDR 16 TDI (FDBF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (DDFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFD); +RUNTEST 100 TCK; +SDR 16 TDI (DDF5); +RUNTEST 100 TCK; +SDR 16 TDI (69FF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BAAF); +RUNTEST 100 TCK; +SDR 16 TDI (FDFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFD); +RUNTEST 100 TCK; +SDR 16 TDI (FFDD); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFBB); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFE); +RUNTEST 100 TCK; +SDR 16 TDI (7DFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFBF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7DFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFBB); +RUNTEST 100 TCK; +SDR 16 TDI (EFFD); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFDD); +RUNTEST 100 TCK; +SDR 16 TDI (BFDF); +RUNTEST 100 TCK; +SDR 16 TDI (CFEF); +RUNTEST 100 TCK; +SDR 16 TDI (7BFF); +RUNTEST 100 TCK; +SDR 16 TDI (BBAF); +RUNTEST 100 TCK; +SDR 16 TDI (BDFE); +RUNTEST 100 TCK; +SDR 16 TDI (FEFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFD); +RUNTEST 100 TCK; +SDR 16 TDI (7F7F); +RUNTEST 100 TCK; +SDR 16 TDI (77FF); +RUNTEST 100 TCK; +SDR 16 TDI (3F73); +RUNTEST 100 TCK; +SDR 16 TDI (BBFE); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7BFF); +RUNTEST 100 TCK; +SDR 16 TDI (FDFF); +RUNTEST 100 TCK; +SDR 16 TDI (BBFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFBF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (D9BD); +RUNTEST 100 TCK; +SDR 16 TDI (AFFC); +RUNTEST 100 TCK; +SDR 16 TDI (ECFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FCFF); +RUNTEST 100 TCK; +SDR 16 TDI (77FD); +RUNTEST 100 TCK; +SDR 16 TDI (FF13); +RUNTEST 100 TCK; +SDR 16 TDI (AB5B); +RUNTEST 100 TCK; +SDR 16 TDI (9F7D); +RUNTEST 100 TCK; +SDR 16 TDI (7FBF); +RUNTEST 100 TCK; +SDR 16 TDI (F4DD); +RUNTEST 100 TCK; +SDR 16 TDI (A99F); +RUNTEST 100 TCK; +SDR 16 TDI (E7F7); +RUNTEST 100 TCK; +SDR 16 TDI (6BFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFBF); +RUNTEST 100 TCK; +SDR 16 TDI (BDDF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (B9BF); +RUNTEST 100 TCK; +SDR 16 TDI (BF3F); +RUNTEST 100 TCK; +SDR 16 TDI (6FF2); +RUNTEST 100 TCK; +SDR 16 TDI (FEEE); +RUNTEST 100 TCK; +SDR 16 TDI (BFEF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (DFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FD8F); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (B3EF); +RUNTEST 100 TCK; +SDR 16 TDI (BBFE); +RUNTEST 100 TCK; +SDR 16 TDI (767F); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFD); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (DFFD); +RUNTEST 100 TCK; +SDR 16 TDI (B7B5); +RUNTEST 100 TCK; +SDR 16 TDI (6FFF); +RUNTEST 100 TCK; +SDR 16 TDI (7DFD); +RUNTEST 100 TCK; +SDR 16 TDI (FF22); +RUNTEST 100 TCK; +SDR 16 TDI (BFFB); +RUNTEST 100 TCK; +SDR 16 TDI (9FFC); +RUNTEST 100 TCK; +SDR 16 TDI (74FF); +RUNTEST 100 TCK; +SDR 16 TDI (CC5E); +RUNTEST 100 TCK; +SDR 16 TDI (B7B9); +RUNTEST 100 TCK; +SDR 16 TDI (D9FF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (B76C); +RUNTEST 100 TCK; +SDR 16 TDI (FEFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FDF); +RUNTEST 100 TCK; +SDR 16 TDI (9E80); +RUNTEST 100 TCK; +SDR 16 TDI (A700); +RUNTEST 100 TCK; +SDR 16 TDI (1BE9); +RUNTEST 100 TCK; +SDR 16 TDI (78B9); +RUNTEST 100 TCK; +SDR 16 TDI (F00F); +RUNTEST 100 TCK; +SDR 16 TDI (A1FF); +RUNTEST 100 TCK; +SDR 16 TDI (2800); +RUNTEST 100 TCK; +SDR 16 TDI (60FF); +RUNTEST 100 TCK; +SDR 16 TDI (AF8F); +RUNTEST 100 TCK; +SDR 16 TDI (A004); +RUNTEST 100 TCK; +SDR 16 TDI (7875); +RUNTEST 100 TCK; +SDR 16 TDI (69FF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BEDC); +RUNTEST 100 TCK; +SDR 16 TDI (3FFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FAA); +RUNTEST 100 TCK; +SDR 16 TDI (7EA0); +RUNTEST 100 TCK; +SDR 16 TDI (A300); +RUNTEST 100 TCK; +SDR 16 TDI (23F9); +RUNTEST 100 TCK; +SDR 16 TDI (7EBE); +RUNTEST 100 TCK; +SDR 16 TDI (102D); +RUNTEST 100 TCK; +SDR 16 TDI (A1FF); +RUNTEST 100 TCK; +SDR 16 TDI (A858); +RUNTEST 100 TCK; +SDR 16 TDI (60FF); +RUNTEST 100 TCK; +SDR 16 TDI (A08D); +RUNTEST 100 TCK; +SDR 16 TDI (B800); +RUNTEST 100 TCK; +SDR 16 TDI (007F); +RUNTEST 100 TCK; +SDR 16 TDI (7DFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (B77C); +RUNTEST 100 TCK; +SDR 16 TDI (FCFC); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (9E00); +RUNTEST 100 TCK; +SDR 16 TDI (A0E3); +RUNTEST 100 TCK; +SDR 16 TDI (17FE); +RUNTEST 100 TCK; +SDR 16 TDI (6646); +RUNTEST 100 TCK; +SDR 16 TDI (1C06); +RUNTEST 100 TCK; +SDR 16 TDI (A19F); +RUNTEST 100 TCK; +SDR 16 TDI (D804); +RUNTEST 100 TCK; +SDR 16 TDI (78FF); +RUNTEST 100 TCK; +SDR 16 TDI (57BF); +RUNTEST 100 TCK; +SDR 16 TDI (B998); +RUNTEST 100 TCK; +SDR 16 TDI (00F5); +RUNTEST 100 TCK; +SDR 16 TDI (6BFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFEC); +RUNTEST 100 TCK; +SDR 16 TDI (3CFC); +RUNTEST 100 TCK; +SDR 16 TDI (7FFE); +RUNTEST 100 TCK; +SDR 16 TDI (7E04); +RUNTEST 100 TCK; +SDR 16 TDI (A0C0); +RUNTEST 100 TCK; +SDR 16 TDI (23FE); +RUNTEST 100 TCK; +SDR 16 TDI (7858); +RUNTEST 100 TCK; +SDR 16 TDI (700F); +RUNTEST 100 TCK; +SDR 16 TDI (B99F); +RUNTEST 100 TCK; +SDR 16 TDI (C878); +RUNTEST 100 TCK; +SDR 16 TDI (60FF); +RUNTEST 100 TCK; +SDR 16 TDI (588F); +RUNTEST 100 TCK; +SDR 16 TDI (B998); +RUNTEST 100 TCK; +SDR 16 TDI (787F); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (B8AF); +RUNTEST 100 TCK; +SDR 16 TDI (33B3); +RUNTEST 100 TCK; +SDR 16 TDI (63EE); +RUNTEST 100 TCK; +SDR 16 TDI (E6E7); +RUNTEST 100 TCK; +SDR 16 TDI (A323); +RUNTEST 100 TCK; +SDR 16 TDI (39F7); +RUNTEST 100 TCK; +SDR 16 TDI (6EEE); +RUNTEST 100 TCK; +SDR 16 TDI (FEEC); +RUNTEST 100 TCK; +SDR 16 TDI (BD8F); +RUNTEST 100 TCK; +SDR 16 TDI (9989); +RUNTEST 100 TCK; +SDR 16 TDI (77CC); +RUNTEST 100 TCK; +SDR 16 TDI (CCE7); +RUNTEST 100 TCK; +SDR 16 TDI (B999); +RUNTEST 100 TCK; +SDR 16 TDI (99FF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BEFE); +RUNTEST 100 TCK; +SDR 16 TDI (7737); +RUNTEST 100 TCK; +SDR 16 TDI (6946); +RUNTEST 100 TCK; +SDR 16 TDI (7673); +RUNTEST 100 TCK; +SDR 16 TDI (B736); +RUNTEST 100 TCK; +SDR 16 TDI (70A2); +RUNTEST 100 TCK; +SDR 16 TDI (6444); +RUNTEST 100 TCK; +SDR 16 TDI (5CCD); +RUNTEST 100 TCK; +SDR 16 TDI (B9B5); +RUNTEST 100 TCK; +SDR 16 TDI (19DD); +RUNTEST 100 TCK; +SDR 16 TDI (73DD); +RUNTEST 100 TCK; +SDR 16 TDI (CCC2); +RUNTEST 100 TCK; +SDR 16 TDI (B5DC); +RUNTEST 100 TCK; +SDR 16 TDI (DCFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFEF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (77DF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFEF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FEFE); +RUNTEST 100 TCK; +SDR 16 TDI (BDDF); +RUNTEST 100 TCK; +SDR 16 TDI (7F3B); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FF73); RUNTEST 100 TCK; SDR 16 TDI (B3BF); RUNTEST 100 TCK; @@ -3007,27 +1215,11 @@ SDR 16 TDI (FFFF); RUNTEST 100 TCK; SDR 16 TDI (BFFF); RUNTEST 100 TCK; -SDR 16 TDI (BF7D); +SDR 16 TDI (FDF7); RUNTEST 100 TCK; -SDR 16 TDI (7FEF); +SDR 16 TDI (7FFF); RUNTEST 100 TCK; -SDR 16 TDI (FDFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFE); -RUNTEST 100 TCK; -SDR 16 TDI (DFFF); -RUNTEST 100 TCK; -SDR 16 TDI (6DFF); -RUNTEST 100 TCK; -SDR 16 TDI (F7DB); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (CDDB); -RUNTEST 100 TCK; -SDR 16 TDI (7F67); -RUNTEST 100 TCK; -SDR 16 TDI (DBFF); +SDR 16 TDI (FFFF); RUNTEST 100 TCK; SDR 16 TDI (BEFF); RUNTEST 100 TCK; @@ -3035,1887 +1227,527 @@ SDR 16 TDI (FFFF); RUNTEST 100 TCK; SDR 16 TDI (7FFF); RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BDFF); -RUNTEST 100 TCK; -SDR 16 TDI (EFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFB); -RUNTEST 100 TCK; -SDR 16 TDI (F77B); -RUNTEST 100 TCK; -SDR 16 TDI (B5DF); -RUNTEST 100 TCK; -SDR 16 TDI (FFF6); -RUNTEST 100 TCK; -SDR 16 TDI (7FDE); -RUNTEST 100 TCK; -SDR 16 TDI (FDFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFDF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7BFD); -RUNTEST 100 TCK; -SDR 16 TDI (FF6F); -RUNTEST 100 TCK; -SDR 16 TDI (BDDF); -RUNTEST 100 TCK; -SDR 16 TDI (FDFD); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (B5DD); -RUNTEST 100 TCK; -SDR 16 TDI (EFFF); -RUNTEST 100 TCK; -SDR 16 TDI (73BF); -RUNTEST 100 TCK; -SDR 16 TDI (F7FF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (DBFF); -RUNTEST 100 TCK; -SDR 16 TDI (7F7E); -RUNTEST 100 TCK; -SDR 16 TDI (FF7F); -RUNTEST 100 TCK; -SDR 16 TDI (BBFF); -RUNTEST 100 TCK; -SDR 16 TDI (FDFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BBFF); -RUNTEST 100 TCK; -SDR 16 TDI (FF7E); -RUNTEST 100 TCK; -SDR 16 TDI (7FF7); -RUNTEST 100 TCK; -SDR 16 TDI (F57F); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFE); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FDE7); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (EFDB); -RUNTEST 100 TCK; -SDR 16 TDI (7BE7); -RUNTEST 100 TCK; -SDR 16 TDI (D7FF); -RUNTEST 100 TCK; -SDR 16 TDI (BEDF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFB); -RUNTEST 100 TCK; -SDR 16 TDI (F7FB); -RUNTEST 100 TCK; -SDR 16 TDI (7FFB); -RUNTEST 100 TCK; -SDR 16 TDI (FFDF); -RUNTEST 100 TCK; -SDR 16 TDI (B77F); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFB); -RUNTEST 100 TCK; -SDR 16 TDI (FF7F); -RUNTEST 100 TCK; -SDR 16 TDI (BDFF); -RUNTEST 100 TCK; -SDR 16 TDI (DD37); -RUNTEST 100 TCK; -SDR 16 TDI (7DF5); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFDF); -RUNTEST 100 TCK; -SDR 16 TDI (7FEF); -RUNTEST 100 TCK; -SDR 16 TDI (77FF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFD); -RUNTEST 100 TCK; -SDR 16 TDI (7DEF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFB); -RUNTEST 100 TCK; -SDR 16 TDI (FBFB); -RUNTEST 100 TCK; -SDR 16 TDI (7F3F); -RUNTEST 100 TCK; -SDR 16 TDI (AFF7); -RUNTEST 100 TCK; -SDR 16 TDI (B7FF); -RUNTEST 100 TCK; -SDR 16 TDI (F7FF); -RUNTEST 100 TCK; -SDR 16 TDI (6FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFBF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (DFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFDD); -RUNTEST 100 TCK; -SDR 16 TDI (77D7); -RUNTEST 100 TCK; -SDR 16 TDI (77FD); -RUNTEST 100 TCK; -SDR 16 TDI (EFDF); -RUNTEST 100 TCK; -SDR 16 TDI (AFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (6BEF); -RUNTEST 100 TCK; -SDR 16 TDI (FBFF); -RUNTEST 100 TCK; -SDR 16 TDI (AFDF); -RUNTEST 100 TCK; -SDR 16 TDI (FFF3); -RUNTEST 100 TCK; -SDR 16 TDI (67FF); -RUNTEST 100 TCK; -SDR 16 TDI (FEEF); -RUNTEST 100 TCK; -SDR 16 TDI (BFEF); -RUNTEST 100 TCK; -SDR 16 TDI (DBFD); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FDFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (B7B7); -RUNTEST 100 TCK; -SDR 16 TDI (FBF7); -RUNTEST 100 TCK; -SDR 16 TDI (7EDB); -RUNTEST 100 TCK; -SDR 16 TDI (DF77); -RUNTEST 100 TCK; -SDR 16 TDI (BDFF); -RUNTEST 100 TCK; -SDR 16 TDI (CB5F); -RUNTEST 100 TCK; -SDR 16 TDI (7EF5); -RUNTEST 100 TCK; -SDR 16 TDI (FFBF); -RUNTEST 100 TCK; -SDR 16 TDI (BFBF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BDFF); -RUNTEST 100 TCK; -SDR 16 TDI (F9FB); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FBFF); -RUNTEST 100 TCK; -SDR 16 TDI (BA7F); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (6DEC); -RUNTEST 100 TCK; -SDR 16 TDI (EDE7); -RUNTEST 100 TCK; -SDR 16 TDI (B5FF); -RUNTEST 100 TCK; -SDR 16 TDI (FBFB); -RUNTEST 100 TCK; -SDR 16 TDI (7B9F); -RUNTEST 100 TCK; -SDR 16 TDI (7BFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFF6); -RUNTEST 100 TCK; -SDR 16 TDI (FF7F); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BF7F); -RUNTEST 100 TCK; -SDR 16 TDI (FFBF); -RUNTEST 100 TCK; -SDR 16 TDI (7FEE); -RUNTEST 100 TCK; -SDR 16 TDI (BEFD); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFF7); -RUNTEST 100 TCK; -SDR 16 TDI (7F7F); -RUNTEST 100 TCK; -SDR 16 TDI (BB7F); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BF77); -RUNTEST 100 TCK; -SDR 16 TDI (6EF7); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BBBF); -RUNTEST 100 TCK; -SDR 16 TDI (EFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BDFF); -RUNTEST 100 TCK; -SDR 16 TDI (F7FF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FF7F); -RUNTEST 100 TCK; -SDR 16 TDI (B7EF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7DF7); -RUNTEST 100 TCK; -SDR 16 TDI (FFFE); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFB7); -RUNTEST 100 TCK; -SDR 16 TDI (7BF6); -RUNTEST 100 TCK; -SDR 16 TDI (EFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFB); -RUNTEST 100 TCK; -SDR 16 TDI (B7FF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BF7F); -RUNTEST 100 TCK; -SDR 16 TDI (FEBB); -RUNTEST 100 TCK; -SDR 16 TDI (77FE); -RUNTEST 100 TCK; -SDR 16 TDI (DBFB); -RUNTEST 100 TCK; -SDR 16 TDI (BD7F); -RUNTEST 100 TCK; -SDR 16 TDI (FBFF); -RUNTEST 100 TCK; -SDR 16 TDI (6EFB); -RUNTEST 100 TCK; -SDR 16 TDI (55AB); -RUNTEST 100 TCK; -SDR 16 TDI (B3FF); -RUNTEST 100 TCK; -SDR 16 TDI (FB7A); -RUNTEST 100 TCK; -SDR 16 TDI (7D6F); -RUNTEST 100 TCK; -SDR 16 TDI (77FF); -RUNTEST 100 TCK; -SDR 16 TDI (BFB6); -RUNTEST 100 TCK; -SDR 16 TDI (FF7F); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BDAD); -RUNTEST 100 TCK; -SDR 16 TDI (F7FF); -RUNTEST 100 TCK; -SDR 16 TDI (6FFE); -RUNTEST 100 TCK; -SDR 16 TDI (EFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFD9); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7DFC); -RUNTEST 100 TCK; -SDR 16 TDI (FFB9); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFBF); -RUNTEST 100 TCK; -SDR 16 TDI (6E77); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFB); -RUNTEST 100 TCK; -SDR 16 TDI (BEF5); -RUNTEST 100 TCK; -SDR 16 TDI (6BFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BBFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFE); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FF33); -RUNTEST 100 TCK; -SDR 16 TDI (B5FF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFD); -RUNTEST 100 TCK; -SDR 16 TDI (7EDF); -RUNTEST 100 TCK; -SDR 16 TDI (B5FF); -RUNTEST 100 TCK; -SDR 16 TDI (BBBF); -RUNTEST 100 TCK; -SDR 16 TDI (F5FF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFE); -RUNTEST 100 TCK; -SDR 16 TDI (7EDF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7DFF); -RUNTEST 100 TCK; -SDR 16 TDI (7DFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (B65E); -RUNTEST 100 TCK; -SDR 16 TDI (FF7B); -RUNTEST 100 TCK; -SDR 16 TDI (7FEF); -RUNTEST 100 TCK; -SDR 16 TDI (FBFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (E7FA); -RUNTEST 100 TCK; -SDR 16 TDI (73AF); -RUNTEST 100 TCK; -SDR 16 TDI (FFDF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFB); -RUNTEST 100 TCK; -SDR 16 TDI (3FFD); -RUNTEST 100 TCK; -SDR 16 TDI (7BEB); -RUNTEST 100 TCK; -SDR 16 TDI (6BFF); -RUNTEST 100 TCK; -SDR 16 TDI (BDDF); -RUNTEST 100 TCK; -SDR 16 TDI (F7F5); -RUNTEST 100 TCK; -SDR 16 TDI (6BFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFB); -RUNTEST 100 TCK; -SDR 16 TDI (DFFF); -RUNTEST 100 TCK; -SDR 16 TDI (AFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFDF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (B76B); -RUNTEST 100 TCK; -SDR 16 TDI (BF7F); -RUNTEST 100 TCK; -SDR 16 TDI (FEFE); -RUNTEST 100 TCK; -SDR 16 TDI (757F); -RUNTEST 100 TCK; -SDR 16 TDI (DFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFF3); -RUNTEST 100 TCK; -SDR 16 TDI (7B6A); -RUNTEST 100 TCK; -SDR 16 TDI (75FF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (EEFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (B99D); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7775); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (AFFF); -RUNTEST 100 TCK; -SDR 16 TDI (F7DF); -RUNTEST 100 TCK; -SDR 16 TDI (7FEF); -RUNTEST 100 TCK; -SDR 16 TDI (FD6F); -RUNTEST 100 TCK; -SDR 16 TDI (AEFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFEF); -RUNTEST 100 TCK; -SDR 16 TDI (7DED); -RUNTEST 100 TCK; -SDR 16 TDI (DFFF); -RUNTEST 100 TCK; -SDR 16 TDI (AFFB); -RUNTEST 100 TCK; -SDR 16 TDI (5BFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (7EFF); -RUNTEST 100 TCK; -SDR 16 TDI (AABF); -RUNTEST 100 TCK; -SDR 16 TDI (FCFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (F7BF); -RUNTEST 100 TCK; -SDR 16 TDI (BF7F); -RUNTEST 100 TCK; -SDR 16 TDI (EFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FF75); -RUNTEST 100 TCK; -SDR 16 TDI (6DEC); -RUNTEST 100 TCK; -SDR 16 TDI (B3F6); -RUNTEST 100 TCK; -SDR 16 TDI (A7D3); -RUNTEST 100 TCK; -SDR 16 TDI (AFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FB1); -RUNTEST 100 TCK; -SDR 16 TDI (93C1); -RUNTEST 100 TCK; -SDR 16 TDI (BFFE); -RUNTEST 100 TCK; -SDR 16 TDI (FF3E); -RUNTEST 100 TCK; -SDR 16 TDI (73C3); -RUNTEST 100 TCK; -SDR 16 TDI (3FBF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFE); -RUNTEST 100 TCK; -SDR 16 TDI (5BFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (B3FC); -RUNTEST 100 TCK; -SDR 16 TDI (7EDF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFD); -RUNTEST 100 TCK; -SDR 16 TDI (BFEF); -RUNTEST 100 TCK; -SDR 16 TDI (D7FC); -RUNTEST 100 TCK; -SDR 16 TDI (73FF); -RUNTEST 100 TCK; -SDR 16 TDI (FC3F); -RUNTEST 100 TCK; -SDR 16 TDI (BEFF); -RUNTEST 100 TCK; -SDR 16 TDI (E6FD); -RUNTEST 100 TCK; -SDR 16 TDI (7EFD); -RUNTEST 100 TCK; -SDR 16 TDI (E6EF); -RUNTEST 100 TCK; -SDR 16 TDI (BCE9); -RUNTEST 100 TCK; -SDR 16 TDI (BCEA); -RUNTEST 100 TCK; -SDR 16 TDI (77FF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (E7FF); -RUNTEST 100 TCK; -SDR 16 TDI (7FF3); -RUNTEST 100 TCK; -SDR 16 TDI (5F5F); -RUNTEST 100 TCK; -SDR 16 TDI (B8BC); -RUNTEST 100 TCK; -SDR 16 TDI (FBEB); -RUNTEST 100 TCK; -SDR 16 TDI (6C4E); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (A11B); -RUNTEST 100 TCK; -SDR 16 TDI (D9DF); -RUNTEST 100 TCK; -SDR 16 TDI (6D3F); -RUNTEST 100 TCK; -SDR 16 TDI (D95F); -RUNTEST 100 TCK; -SDR 16 TDI (B75F); -RUNTEST 100 TCK; -SDR 16 TDI (E77F); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BE5D); -RUNTEST 100 TCK; -SDR 16 TDI (69FC); -RUNTEST 100 TCK; -SDR 16 TDI (67C0); -RUNTEST 100 TCK; -SDR 16 TDI (0B9E); -RUNTEST 100 TCK; -SDR 16 TDI (A320); -RUNTEST 100 TCK; -SDR 16 TDI (03C0); -RUNTEST 100 TCK; -SDR 16 TDI (60A2); -RUNTEST 100 TCK; -SDR 16 TDI (5E39); -RUNTEST 100 TCK; -SDR 16 TDI (B997); -RUNTEST 100 TCK; -SDR 16 TDI (6084); -RUNTEST 100 TCK; -SDR 16 TDI (7CB5); -RUNTEST 100 TCK; -SDR 16 TDI (F48F); -RUNTEST 100 TCK; -SDR 16 TDI (A49F); -RUNTEST 100 TCK; -SDR 16 TDI (E3F5); -RUNTEST 100 TCK; -SDR 16 TDI (6BFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BAFE); -RUNTEST 100 TCK; -SDR 16 TDI (E9C3); -RUNTEST 100 TCK; -SDR 16 TDI (67A0); -RUNTEST 100 TCK; -SDR 16 TDI (0BE0); -RUNTEST 100 TCK; -SDR 16 TDI (A382); -RUNTEST 100 TCK; -SDR 16 TDI (03D0); -RUNTEST 100 TCK; -SDR 16 TDI (62E0); -RUNTEST 100 TCK; -SDR 16 TDI (1201); -RUNTEST 100 TCK; -SDR 16 TDI (A01F); -RUNTEST 100 TCK; -SDR 16 TDI (8884); -RUNTEST 100 TCK; -SDR 16 TDI (6080); -RUNTEST 100 TCK; -SDR 16 TDI (F43F); -RUNTEST 100 TCK; -SDR 16 TDI (AC1E); -RUNTEST 100 TCK; -SDR 16 TDI (897F); -RUNTEST 100 TCK; -SDR 16 TDI (7DFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BF6D); -RUNTEST 100 TCK; -SDR 16 TDI (9283); -RUNTEST 100 TCK; -SDR 16 TDI (7FF0); -RUNTEST 100 TCK; -SDR 16 TDI (0C61); -RUNTEST 100 TCK; -SDR 16 TDI (A32C); -RUNTEST 100 TCK; -SDR 16 TDI (23F9); -RUNTEST 100 TCK; -SDR 16 TDI (6000); -RUNTEST 100 TCK; -SDR 16 TDI (7CDB); -RUNTEST 100 TCK; -SDR 16 TDI (B77F); -RUNTEST 100 TCK; -SDR 16 TDI (E7E6); -RUNTEST 100 TCK; -SDR 16 TDI (7BCF); -RUNTEST 100 TCK; -SDR 16 TDI (0F8F); -RUNTEST 100 TCK; -SDR 16 TDI (BEBF); -RUNTEST 100 TCK; -SDR 16 TDI (F975); -RUNTEST 100 TCK; -SDR 16 TDI (6BFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFDE); -RUNTEST 100 TCK; -SDR 16 TDI (D2B0); -RUNTEST 100 TCK; -SDR 16 TDI (67F6); -RUNTEST 100 TCK; -SDR 16 TDI (4D86); -RUNTEST 100 TCK; -SDR 16 TDI (A37E); -RUNTEST 100 TCK; -SDR 16 TDI (33F0); -RUNTEST 100 TCK; -SDR 16 TDI (6000); -RUNTEST 100 TCK; -SDR 16 TDI (7CD3); -RUNTEST 100 TCK; -SDR 16 TDI (B77F); -RUNTEST 100 TCK; -SDR 16 TDI (EE66); -RUNTEST 100 TCK; -SDR 16 TDI (6BC9); -RUNTEST 100 TCK; -SDR 16 TDI (49FF); -RUNTEST 100 TCK; -SDR 16 TDI (BE3C); -RUNTEST 100 TCK; -SDR 16 TDI (897F); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BE27); -RUNTEST 100 TCK; -SDR 16 TDI (BBBB); -RUNTEST 100 TCK; -SDR 16 TDI (71EE); -RUNTEST 100 TCK; -SDR 16 TDI (6EEF); -RUNTEST 100 TCK; -SDR 16 TDI (A3BB); -RUNTEST 100 TCK; -SDR 16 TDI (B1F3); -RUNTEST 100 TCK; -SDR 16 TDI (66E6); -RUNTEST 100 TCK; -SDR 16 TDI (7CCF); -RUNTEST 100 TCK; -SDR 16 TDI (B98F); -RUNTEST 100 TCK; -SDR 16 TDI (D99F); -RUNTEST 100 TCK; -SDR 16 TDI (73EE); -RUNTEST 100 TCK; -SDR 16 TDI (8EC7); -RUNTEST 100 TCK; -SDR 16 TDI (BDD9); -RUNTEST 100 TCK; -SDR 16 TDI (99EB); -RUNTEST 100 TCK; -SDR 16 TDI (77FF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BF77); -RUNTEST 100 TCK; -SDR 16 TDI (1111); -RUNTEST 100 TCK; -SDR 16 TDI (6167); -RUNTEST 100 TCK; -SDR 16 TDI (6445); -RUNTEST 100 TCK; -SDR 16 TDI (A777); -RUNTEST 100 TCK; -SDR 16 TDI (74A9); -RUNTEST 100 TCK; -SDR 16 TDI (7277); -RUNTEST 100 TCK; -SDR 16 TDI (3CDC); -RUNTEST 100 TCK; -SDR 16 TDI (BB25); -RUNTEST 100 TCK; -SDR 16 TDI (1DD9); -RUNTEST 100 TCK; -SDR 16 TDI (7BCC); -RUNTEST 100 TCK; -SDR 16 TDI (DC92); -RUNTEST 100 TCK; -SDR 16 TDI (B5CC); -RUNTEST 100 TCK; -SDR 16 TDI (DDFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFDD); -RUNTEST 100 TCK; -SDR 16 TDI (DDDD); -RUNTEST 100 TCK; -SDR 16 TDI (7FDE); -RUNTEST 100 TCK; -SDR 16 TDI (FDDD); -RUNTEST 100 TCK; -SDR 16 TDI (BBFF); -RUNTEST 100 TCK; -SDR 16 TDI (F8FF); -RUNTEST 100 TCK; -SDR 16 TDI (6FCE); -RUNTEST 100 TCK; -SDR 16 TDI (F7FF); -RUNTEST 100 TCK; -SDR 16 TDI (BDEF); -RUNTEST 100 TCK; -SDR 16 TDI (77BF); -RUNTEST 100 TCK; -SDR 16 TDI (7F77); -RUNTEST 100 TCK; -SDR 16 TDI (E7F7); -RUNTEST 100 TCK; -SDR 16 TDI (B3BB); -RUNTEST 100 TCK; -SDR 16 TDI (BBFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BAEE); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (BEDF); -RUNTEST 100 TCK; -SDR 16 TDI (B7EF); -RUNTEST 100 TCK; -SDR 16 TDI (F7FF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FEFF); -RUNTEST 100 TCK; -SDR 16 TDI (BBFF); -RUNTEST 100 TCK; -SDR 16 TDI (DF6D); -RUNTEST 100 TCK; -SDR 16 TDI (6B5F); -RUNTEST 100 TCK; -SDR 16 TDI (DFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BBDE); -RUNTEST 100 TCK; -SDR 16 TDI (EFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FF77); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (F7FD); -RUNTEST 100 TCK; -SDR 16 TDI (BE7D); -RUNTEST 100 TCK; -SDR 16 TDI (EFFB); -RUNTEST 100 TCK; -SDR 16 TDI (76EB); -RUNTEST 100 TCK; -SDR 16 TDI (F7DE); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (EBDF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFB); -RUNTEST 100 TCK; -SDR 16 TDI (BBDF); -RUNTEST 100 TCK; -SDR 16 TDI (BF7B); -RUNTEST 100 TCK; -SDR 16 TDI (BDFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (AFFF); -RUNTEST 100 TCK; -SDR 16 TDI (76E5); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFD); -RUNTEST 100 TCK; -SDR 16 TDI (B7DE); -RUNTEST 100 TCK; -SDR 16 TDI (FFF7); -RUNTEST 100 TCK; -SDR 16 TDI (77FF); -RUNTEST 100 TCK; -SDR 16 TDI (FFDF); -RUNTEST 100 TCK; -SDR 16 TDI (BBFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFF5); -RUNTEST 100 TCK; -SDR 16 TDI (7FEF); -RUNTEST 100 TCK; -SDR 16 TDI (EFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BEFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (AFAB); -RUNTEST 100 TCK; -SDR 16 TDI (FFBF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (D6BF); -RUNTEST 100 TCK; -SDR 16 TDI (BF7F); -RUNTEST 100 TCK; -SDR 16 TDI (F7FF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FAFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (DF5E); -RUNTEST 100 TCK; -SDR 16 TDI (7B7F); -RUNTEST 100 TCK; -SDR 16 TDI (FFDF); -RUNTEST 100 TCK; -SDR 16 TDI (BDDE); -RUNTEST 100 TCK; -SDR 16 TDI (F5FB); -RUNTEST 100 TCK; -SDR 16 TDI (7DFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFD); -RUNTEST 100 TCK; -SDR 16 TDI (FEF7); -RUNTEST 100 TCK; -SDR 16 TDI (7FF3); -RUNTEST 100 TCK; -SDR 16 TDI (FECD); -RUNTEST 100 TCK; -SDR 16 TDI (BEFF); -RUNTEST 100 TCK; -SDR 16 TDI (EFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7EF7); -RUNTEST 100 TCK; -SDR 16 TDI (7DFF); -RUNTEST 100 TCK; -SDR 16 TDI (BDFF); -RUNTEST 100 TCK; -SDR 16 TDI (CF77); -RUNTEST 100 TCK; -SDR 16 TDI (777F); -RUNTEST 100 TCK; -SDR 16 TDI (FF7F); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FEFB); -RUNTEST 100 TCK; -SDR 16 TDI (77FF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FBEF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (AFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FBFB); -RUNTEST 100 TCK; -SDR 16 TDI (75BF); -RUNTEST 100 TCK; -SDR 16 TDI (AB7F); -RUNTEST 100 TCK; -SDR 16 TDI (BFBF); -RUNTEST 100 TCK; -SDR 16 TDI (FDFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FF7); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BDFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFD); -RUNTEST 100 TCK; -SDR 16 TDI (B7DF); -RUNTEST 100 TCK; -SDR 16 TDI (77FD); -RUNTEST 100 TCK; -SDR 16 TDI (EFFD); -RUNTEST 100 TCK; -SDR 16 TDI (BBFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFD); -RUNTEST 100 TCK; -SDR 16 TDI (7FFB); -RUNTEST 100 TCK; -SDR 16 TDI (677E); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FF7F); -RUNTEST 100 TCK; -SDR 16 TDI (7F7F); -RUNTEST 100 TCK; -SDR 16 TDI (EEFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFEF); -RUNTEST 100 TCK; -SDR 16 TDI (FF7F); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; SDR 16 TDI (FDF7); RUNTEST 100 TCK; -SDR 16 TDI (7FEF); -RUNTEST 100 TCK; -SDR 16 TDI (FF37); -RUNTEST 100 TCK; -SDR 16 TDI (ADFF); -RUNTEST 100 TCK; -SDR 16 TDI (EBF7); -RUNTEST 100 TCK; -SDR 16 TDI (6ACF); -RUNTEST 100 TCK; -SDR 16 TDI (DDFF); -RUNTEST 100 TCK; -SDR 16 TDI (BDDF); -RUNTEST 100 TCK; -SDR 16 TDI (ADF7); -RUNTEST 100 TCK; -SDR 16 TDI (77FB); -RUNTEST 100 TCK; -SDR 16 TDI (FFBF); -RUNTEST 100 TCK; SDR 16 TDI (BFFF); RUNTEST 100 TCK; -SDR 16 TDI (BBFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFDD); -RUNTEST 100 TCK; -SDR 16 TDI (B77F); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (75BF); -RUNTEST 100 TCK; -SDR 16 TDI (B7DF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (6FDE); -RUNTEST 100 TCK; -SDR 16 TDI (DE6F); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FBBF); -RUNTEST 100 TCK; -SDR 16 TDI (79BF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (B7FF); -RUNTEST 100 TCK; -SDR 16 TDI (EDD7); -RUNTEST 100 TCK; -SDR 16 TDI (7FEF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (AEBE); -RUNTEST 100 TCK; -SDR 16 TDI (FFF7); -RUNTEST 100 TCK; -SDR 16 TDI (7FF3); -RUNTEST 100 TCK; -SDR 16 TDI (F7FF); -RUNTEST 100 TCK; -SDR 16 TDI (BDFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFF3); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BBFF); -RUNTEST 100 TCK; -SDR 16 TDI (5FFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFDF); -RUNTEST 100 TCK; -SDR 16 TDI (D757); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (F4EF); -RUNTEST 100 TCK; -SDR 16 TDI (BF7B); -RUNTEST 100 TCK; -SDR 16 TDI (7FFB); -RUNTEST 100 TCK; -SDR 16 TDI (77DF); -RUNTEST 100 TCK; -SDR 16 TDI (D77B); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (DFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7EFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BBFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (B7FE); -RUNTEST 100 TCK; -SDR 16 TDI (7EFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (5FBE); -RUNTEST 100 TCK; -SDR 16 TDI (B6DE); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FF5); -RUNTEST 100 TCK; -SDR 16 TDI (7DEF); -RUNTEST 100 TCK; -SDR 16 TDI (BDFF); -RUNTEST 100 TCK; -SDR 16 TDI (FDAD); -RUNTEST 100 TCK; -SDR 16 TDI (77BF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (5FFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (AE5F); -RUNTEST 100 TCK; -SDR 16 TDI (EBF7); -RUNTEST 100 TCK; -SDR 16 TDI (7FFE); -RUNTEST 100 TCK; -SDR 16 TDI (DFDB); -RUNTEST 100 TCK; -SDR 16 TDI (BAB7); -RUNTEST 100 TCK; -SDR 16 TDI (FFFE); -RUNTEST 100 TCK; -SDR 16 TDI (7FDF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (ABDF); -RUNTEST 100 TCK; -SDR 16 TDI (FFDE); -RUNTEST 100 TCK; -SDR 16 TDI (7FFE); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFF5); -RUNTEST 100 TCK; -SDR 16 TDI (6BFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (ABFD); -RUNTEST 100 TCK; SDR 16 TDI (FFDF); RUNTEST 100 TCK; -SDR 16 TDI (77FB); -RUNTEST 100 TCK; -SDR 16 TDI (FAEF); -RUNTEST 100 TCK; -SDR 16 TDI (AFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FF7F); -RUNTEST 100 TCK; -SDR 16 TDI (7F77); -RUNTEST 100 TCK; -SDR 16 TDI (FFF9); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BB77); -RUNTEST 100 TCK; -SDR 16 TDI (7ADB); -RUNTEST 100 TCK; -SDR 16 TDI (FFBF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (EEFF); -RUNTEST 100 TCK; -SDR 16 TDI (7DFF); +SDR 16 TDI (6F7D); RUNTEST 100 TCK; SDR 16 TDI (FFFF); RUNTEST 100 TCK; -SDR 16 TDI (AF5F); +SDR 16 TDI (BCFF); RUNTEST 100 TCK; -SDR 16 TDI (9FAE); +SDR 16 TDI (FFFF); RUNTEST 100 TCK; -SDR 16 TDI (7FF7); +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFF7); +RUNTEST 100 TCK; +SDR 16 TDI (FF7F); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); RUNTEST 100 TCK; SDR 16 TDI (EFFF); RUNTEST 100 TCK; SDR 16 TDI (BFFF); RUNTEST 100 TCK; -SDR 16 TDI (F7FB); +SDR 16 TDI (FFFF); RUNTEST 100 TCK; -SDR 16 TDI (77BB); +SDR 16 TDI (6FEB); RUNTEST 100 TCK; -SDR 16 TDI (FEDF); +SDR 16 TDI (DBFF); RUNTEST 100 TCK; SDR 16 TDI (BFFF); RUNTEST 100 TCK; -SDR 16 TDI (FF7D); +SDR 16 TDI (FFFD); RUNTEST 100 TCK; SDR 16 TDI (7FFB); RUNTEST 100 TCK; -SDR 16 TDI (EEFE); +SDR 16 TDI (FFFF); RUNTEST 100 TCK; SDR 16 TDI (BFFE); RUNTEST 100 TCK; -SDR 16 TDI (FFF5); -RUNTEST 100 TCK; -SDR 16 TDI (6BFF); -RUNTEST 100 TCK; SDR 16 TDI (FFFF); RUNTEST 100 TCK; -SDR 16 TDI (A5FE); -RUNTEST 100 TCK; -SDR 16 TDI (FE7F); -RUNTEST 100 TCK; SDR 16 TDI (7FFF); RUNTEST 100 TCK; -SDR 16 TDI (FFFD); -RUNTEST 100 TCK; -SDR 16 TDI (AE7F); -RUNTEST 100 TCK; -SDR 16 TDI (EFF6); -RUNTEST 100 TCK; -SDR 16 TDI (7B6F); -RUNTEST 100 TCK; -SDR 16 TDI (BFDD); -RUNTEST 100 TCK; -SDR 16 TDI (BF7D); -RUNTEST 100 TCK; -SDR 16 TDI (F5FF); -RUNTEST 100 TCK; -SDR 16 TDI (7F7F); -RUNTEST 100 TCK; -SDR 16 TDI (FEFF); -RUNTEST 100 TCK; -SDR 16 TDI (B7FF); -RUNTEST 100 TCK; -SDR 16 TDI (FFEA); -RUNTEST 100 TCK; -SDR 16 TDI (75FF); -RUNTEST 100 TCK; SDR 16 TDI (FFFF); RUNTEST 100 TCK; SDR 16 TDI (BFFF); RUNTEST 100 TCK; -SDR 16 TDI (BFF7); -RUNTEST 100 TCK; -SDR 16 TDI (6BFD); -RUNTEST 100 TCK; -SDR 16 TDI (FD57); -RUNTEST 100 TCK; -SDR 16 TDI (9FEF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (77FF); -RUNTEST 100 TCK; -SDR 16 TDI (FA77); -RUNTEST 100 TCK; -SDR 16 TDI (B7FF); -RUNTEST 100 TCK; -SDR 16 TDI (FFAA); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFBF); -RUNTEST 100 TCK; -SDR 16 TDI (BEFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); +SDR 16 TDI (FDB7); RUNTEST 100 TCK; SDR 16 TDI (7FFF); RUNTEST 100 TCK; SDR 16 TDI (FFFF); RUNTEST 100 TCK; -SDR 16 TDI (9FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FEFD); -RUNTEST 100 TCK; -SDR 16 TDI (7FF7); -RUNTEST 100 TCK; -SDR 16 TDI (F7FF); -RUNTEST 100 TCK; -SDR 16 TDI (B7E7); -RUNTEST 100 TCK; -SDR 16 TDI (D7FF); -RUNTEST 100 TCK; -SDR 16 TDI (7BFB); -RUNTEST 100 TCK; -SDR 16 TDI (DB7F); -RUNTEST 100 TCK; -SDR 16 TDI (BEDF); -RUNTEST 100 TCK; -SDR 16 TDI (B7FF); -RUNTEST 100 TCK; -SDR 16 TDI (7F5E); -RUNTEST 100 TCK; -SDR 16 TDI (FBFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFEF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (5FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (9FFF); -RUNTEST 100 TCK; -SDR 16 TDI (BD25); -RUNTEST 100 TCK; -SDR 16 TDI (4DEF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFD); -RUNTEST 100 TCK; -SDR 16 TDI (BA5B); -RUNTEST 100 TCK; -SDR 16 TDI (E7F5); -RUNTEST 100 TCK; -SDR 16 TDI (7D5B); -RUNTEST 100 TCK; -SDR 16 TDI (F5FF); -RUNTEST 100 TCK; -SDR 16 TDI (9E9D); -RUNTEST 100 TCK; -SDR 16 TDI (9FD7); -RUNTEST 100 TCK; -SDR 16 TDI (7FFA); -RUNTEST 100 TCK; -SDR 16 TDI (DE7D); -RUNTEST 100 TCK; -SDR 16 TDI (BEFE); +SDR 16 TDI (BDFF); RUNTEST 100 TCK; SDR 16 TDI (FFFF); RUNTEST 100 TCK; SDR 16 TDI (7FFF); RUNTEST 100 TCK; -SDR 16 TDI (FFFF); +SDR 16 TDI (DEF7); RUNTEST 100 TCK; -SDR 16 TDI (B5FC); -RUNTEST 100 TCK; -SDR 16 TDI (67FA); -RUNTEST 100 TCK; -SDR 16 TDI (77F9); -RUNTEST 100 TCK; -SDR 16 TDI (4AE3); -RUNTEST 100 TCK; -SDR 16 TDI (ADF7); -RUNTEST 100 TCK; -SDR 16 TDI (DF7F); -RUNTEST 100 TCK; -SDR 16 TDI (56EF); -RUNTEST 100 TCK; -SDR 16 TDI (7E82); -RUNTEST 100 TCK; -SDR 16 TDI (9BFF); -RUNTEST 100 TCK; -SDR 16 TDI (F0EB); -RUNTEST 100 TCK; -SDR 16 TDI (5B97); -RUNTEST 100 TCK; -SDR 16 TDI (BFBF); -RUNTEST 100 TCK; -SDR 16 TDI (B7FF); -RUNTEST 100 TCK; -SDR 16 TDI (FF7B); -RUNTEST 100 TCK; -SDR 16 TDI (57FF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (9FFF); -RUNTEST 100 TCK; -SDR 16 TDI (DEDF); -RUNTEST 100 TCK; -SDR 16 TDI (7FF7); -RUNTEST 100 TCK; -SDR 16 TDI (F51E); -RUNTEST 100 TCK; -SDR 16 TDI (B7AF); -RUNTEST 100 TCK; -SDR 16 TDI (FBFA); -RUNTEST 100 TCK; -SDR 16 TDI (6BB5); -RUNTEST 100 TCK; -SDR 16 TDI (9B7D); -RUNTEST 100 TCK; -SDR 16 TDI (A77F); -RUNTEST 100 TCK; -SDR 16 TDI (EF3C); -RUNTEST 100 TCK; -SDR 16 TDI (4E6D); -RUNTEST 100 TCK; -SDR 16 TDI (F5FF); -RUNTEST 100 TCK; -SDR 16 TDI (BFF7); -RUNTEST 100 TCK; -SDR 16 TDI (F7FF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (8F5F); -RUNTEST 100 TCK; -SDR 16 TDI (002E); -RUNTEST 100 TCK; -SDR 16 TDI (5FCF); -RUNTEST 100 TCK; -SDR 16 TDI (EFBA); -RUNTEST 100 TCK; -SDR 16 TDI (A36B); -RUNTEST 100 TCK; -SDR 16 TDI (F7EC); -RUNTEST 100 TCK; -SDR 16 TDI (602B); -RUNTEST 100 TCK; -SDR 16 TDI (9970); -RUNTEST 100 TCK; -SDR 16 TDI (8A77); -RUNTEST 100 TCK; -SDR 16 TDI (084C); -RUNTEST 100 TCK; -SDR 16 TDI (7041); -RUNTEST 100 TCK; -SDR 16 TDI (A06F); -RUNTEST 100 TCK; -SDR 16 TDI (A4E2); -RUNTEST 100 TCK; -SDR 16 TDI (E7EC); -RUNTEST 100 TCK; -SDR 16 TDI (7BFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (A7FE); -RUNTEST 100 TCK; -SDR 16 TDI (8022); -RUNTEST 100 TCK; -SDR 16 TDI (47A5); -RUNTEST 100 TCK; -SDR 16 TDI (E422); -RUNTEST 100 TCK; -SDR 16 TDI (AB2B); -RUNTEST 100 TCK; -SDR 16 TDI (F2F0); -RUNTEST 100 TCK; -SDR 16 TDI (6A0B); -RUNTEST 100 TCK; -SDR 16 TDI (91F4); -RUNTEST 100 TCK; -SDR 16 TDI (881B); -RUNTEST 100 TCK; -SDR 16 TDI (8944); -RUNTEST 100 TCK; -SDR 16 TDI (4040); -RUNTEST 100 TCK; -SDR 16 TDI (A08F); -RUNTEST 100 TCK; -SDR 16 TDI (BCFA); -RUNTEST 100 TCK; -SDR 16 TDI (F86F); -RUNTEST 100 TCK; -SDR 16 TDI (6FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (9D5F); -RUNTEST 100 TCK; -SDR 16 TDI (022E); -RUNTEST 100 TCK; -SDR 16 TDI (7FF7); -RUNTEST 100 TCK; -SDR 16 TDI (F7BA); -RUNTEST 100 TCK; -SDR 16 TDI (A28F); -RUNTEST 100 TCK; -SDR 16 TDI (EBFB); -RUNTEST 100 TCK; -SDR 16 TDI (6410); -RUNTEST 100 TCK; -SDR 16 TDI (1EB0); -RUNTEST 100 TCK; -SDR 16 TDI (AFBF); -RUNTEST 100 TCK; -SDR 16 TDI (F86B); -RUNTEST 100 TCK; -SDR 16 TDI (7040); -RUNTEST 100 TCK; -SDR 16 TDI (6C5F); -RUNTEST 100 TCK; -SDR 16 TDI (9F19); -RUNTEST 100 TCK; -SDR 16 TDI (187D); -RUNTEST 100 TCK; -SDR 16 TDI (7BFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BBFE); -RUNTEST 100 TCK; -SDR 16 TDI (6422); -RUNTEST 100 TCK; -SDR 16 TDI (67E4); -RUNTEST 100 TCK; -SDR 16 TDI (0422); -RUNTEST 100 TCK; -SDR 16 TDI (A203); -RUNTEST 100 TCK; -SDR 16 TDI (E3FB); -RUNTEST 100 TCK; -SDR 16 TDI (7213); -RUNTEST 100 TCK; -SDR 16 TDI (36F0); -RUNTEST 100 TCK; -SDR 16 TDI (8BBF); -RUNTEST 100 TCK; -SDR 16 TDI (E063); -RUNTEST 100 TCK; -SDR 16 TDI (6FD0); -RUNTEST 100 TCK; -SDR 16 TDI (608F); -RUNTEST 100 TCK; -SDR 16 TDI (BF61); -RUNTEST 100 TCK; -SDR 16 TDI (61BF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFDF); -RUNTEST 100 TCK; -SDR 16 TDI (BA3B); -RUNTEST 100 TCK; -SDR 16 TDI (71EE); -RUNTEST 100 TCK; -SDR 16 TDI (EEEF); -RUNTEST 100 TCK; -SDR 16 TDI (A123); -RUNTEST 100 TCK; -SDR 16 TDI (11F3); -RUNTEST 100 TCK; -SDR 16 TDI (484D); -RUNTEST 100 TCK; -SDR 16 TDI (3888); -RUNTEST 100 TCK; -SDR 16 TDI (938F); -RUNTEST 100 TCK; -SDR 16 TDI (B888); -RUNTEST 100 TCK; -SDR 16 TDI (50CC); -RUNTEST 100 TCK; -SDR 16 TDI (CCE7); -RUNTEST 100 TCK; -SDR 16 TDI (BBBB); -RUNTEST 100 TCK; -SDR 16 TDI (BBEA); -RUNTEST 100 TCK; -SDR 16 TDI (67FF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (97FF); -RUNTEST 100 TCK; -SDR 16 TDI (3373); -RUNTEST 100 TCK; -SDR 16 TDI (6146); -RUNTEST 100 TCK; -SDR 16 TDI (6667); -RUNTEST 100 TCK; -SDR 16 TDI (B737); -RUNTEST 100 TCK; -SDR 16 TDI (72A9); -RUNTEST 100 TCK; -SDR 16 TDI (6623); -RUNTEST 100 TCK; -SDR 16 TDI (7DD9); -RUNTEST 100 TCK; -SDR 16 TDI (BBB5); -RUNTEST 100 TCK; -SDR 16 TDI (1CDD); -RUNTEST 100 TCK; -SDR 16 TDI (73C9); -RUNTEST 100 TCK; -SDR 16 TDI (C9C2); -RUNTEST 100 TCK; -SDR 16 TDI (9111); -RUNTEST 100 TCK; -SDR 16 TDI (117F); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFDD); +SDR 16 TDI (BFFF); RUNTEST 100 TCK; SDR 16 TDI (FFDD); RUNTEST 100 TCK; -SDR 16 TDI (7FDD); -RUNTEST 100 TCK; -SDR 16 TDI (FDDD); -RUNTEST 100 TCK; -SDR 16 TDI (BDBF); -RUNTEST 100 TCK; -SDR 16 TDI (DFEF); -RUNTEST 100 TCK; -SDR 16 TDI (7CDD); -RUNTEST 100 TCK; -SDR 16 TDI (FFEE); -RUNTEST 100 TCK; -SDR 16 TDI (9FDF); -RUNTEST 100 TCK; -SDR 16 TDI (7BFF); -RUNTEST 100 TCK; -SDR 16 TDI (7E7F); -RUNTEST 100 TCK; -SDR 16 TDI (FFF7); -RUNTEST 100 TCK; -SDR 16 TDI (B7FF); -RUNTEST 100 TCK; -SDR 16 TDI (FFBF); -RUNTEST 100 TCK; -SDR 16 TDI (6FFF); +SDR 16 TDI (7FFE); RUNTEST 100 TCK; SDR 16 TDI (FFFF); RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (A7F7); -RUNTEST 100 TCK; -SDR 16 TDI (7FF7); -RUNTEST 100 TCK; -SDR 16 TDI (EEEF); -RUNTEST 100 TCK; -SDR 16 TDI (95E7); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (7DFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFB5); -RUNTEST 100 TCK; -SDR 16 TDI (6FF5); -RUNTEST 100 TCK; -SDR 16 TDI (BF7F); -RUNTEST 100 TCK; -SDR 16 TDI (BF7C); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (9FFE); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFD); -RUNTEST 100 TCK; -SDR 16 TDI (BFBE); -RUNTEST 100 TCK; -SDR 16 TDI (7BF6); -RUNTEST 100 TCK; -SDR 16 TDI (74D5); -RUNTEST 100 TCK; -SDR 16 TDI (FF9F); -RUNTEST 100 TCK; -SDR 16 TDI (B2BF); -RUNTEST 100 TCK; -SDR 16 TDI (D2FF); -RUNTEST 100 TCK; -SDR 16 TDI (5F7F); -RUNTEST 100 TCK; -SDR 16 TDI (F7FF); -RUNTEST 100 TCK; -SDR 16 TDI (9FBF); -RUNTEST 100 TCK; -SDR 16 TDI (ADDF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (8FFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FF7); -RUNTEST 100 TCK; -SDR 16 TDI (5FEF); -RUNTEST 100 TCK; -SDR 16 TDI (F7F5); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFD); -RUNTEST 100 TCK; -SDR 16 TDI (77DD); -RUNTEST 100 TCK; -SDR 16 TDI (FEFF); -RUNTEST 100 TCK; -SDR 16 TDI (9F7F); -RUNTEST 100 TCK; -SDR 16 TDI (DFDD); -RUNTEST 100 TCK; -SDR 16 TDI (6FF7); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; SDR 16 TDI (BEFF); RUNTEST 100 TCK; -SDR 16 TDI (FDFF); +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7DFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BBAF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); RUNTEST 100 TCK; SDR 16 TDI (7FFF); RUNTEST 100 TCK; SDR 16 TDI (FFFF); RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFE); +RUNTEST 100 TCK; +SDR 16 TDI (7F7F); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BBFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7DFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFD); +RUNTEST 100 TCK; +SDR 16 TDI (FBFB); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFD); +RUNTEST 100 TCK; +SDR 16 TDI (AFBF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FF7F); +RUNTEST 100 TCK; +SDR 16 TDI (BB7F); +RUNTEST 100 TCK; +SDR 16 TDI (FDFF); +RUNTEST 100 TCK; +SDR 16 TDI (7DFF); +RUNTEST 100 TCK; +SDR 16 TDI (FDFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FAFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FBE); +RUNTEST 100 TCK; +SDR 16 TDI (6FF3); +RUNTEST 100 TCK; +SDR 16 TDI (6FFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFE7); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (7F7D); +RUNTEST 100 TCK; +SDR 16 TDI (CFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFBF); +RUNTEST 100 TCK; +SDR 16 TDI (DFFD); +RUNTEST 100 TCK; +SDR 16 TDI (7FFA); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFBF); +RUNTEST 100 TCK; +SDR 16 TDI (DFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFF7); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FEFF); +RUNTEST 100 TCK; +SDR 16 TDI (BB77); +RUNTEST 100 TCK; +SDR 16 TDI (FBF7); +RUNTEST 100 TCK; +SDR 16 TDI (6F6F); +RUNTEST 100 TCK; +SDR 16 TDI (CF7F); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (DFBD); +RUNTEST 100 TCK; +SDR 16 TDI (7FFD); +RUNTEST 100 TCK; +SDR 16 TDI (EFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFDF); +RUNTEST 100 TCK; +SDR 16 TDI (DFF7); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFD); +RUNTEST 100 TCK; +SDR 16 TDI (FB75); +RUNTEST 100 TCK; +SDR 16 TDI (6FEB); +RUNTEST 100 TCK; +SDR 16 TDI (77FA); +RUNTEST 100 TCK; +SDR 16 TDI (BFEF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFD); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BB3F); +RUNTEST 100 TCK; +SDR 16 TDI (FDFF); +RUNTEST 100 TCK; +SDR 16 TDI (7DFB); +RUNTEST 100 TCK; +SDR 16 TDI (FDFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FD7F); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (6BB7); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BEFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFF7); +RUNTEST 100 TCK; +SDR 16 TDI (ABFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFEF); +RUNTEST 100 TCK; +SDR 16 TDI (DDFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BEBF); +RUNTEST 100 TCK; +SDR 16 TDI (FDEF); +RUNTEST 100 TCK; +SDR 16 TDI (7FEF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFF7); +RUNTEST 100 TCK; +SDR 16 TDI (7FFE); +RUNTEST 100 TCK; +SDR 16 TDI (F5FD); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (DDF7); +RUNTEST 100 TCK; +SDR 16 TDI (7BFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BBFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BDFF); +RUNTEST 100 TCK; +SDR 16 TDI (DDF7); +RUNTEST 100 TCK; +SDR 16 TDI (7FF7); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (BDFB); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFB); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFE); +RUNTEST 100 TCK; +SDR 16 TDI (7BFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BBF7); +RUNTEST 100 TCK; +SDR 16 TDI (EDFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFBF); +RUNTEST 100 TCK; +SDR 16 TDI (7B9F); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (7AFA); +RUNTEST 100 TCK; +SDR 16 TDI (ADFF); +RUNTEST 100 TCK; +SDR 16 TDI (FDEF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (B55F); +RUNTEST 100 TCK; +SDR 16 TDI (9FB7); +RUNTEST 100 TCK; +SDR 16 TDI (7FFA); +RUNTEST 100 TCK; +SDR 16 TDI (EECD); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FEAE); +RUNTEST 100 TCK; +SDR 16 TDI (BFDF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFDF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFF5); +RUNTEST 100 TCK; +SDR 16 TDI (69FF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (F7FF); +RUNTEST 100 TCK; +SDR 16 TDI (6FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FBFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (EFF7); +RUNTEST 100 TCK; +SDR 16 TDI (6EFF); +RUNTEST 100 TCK; +SDR 16 TDI (BBFF); +RUNTEST 100 TCK; +SDR 16 TDI (BBFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFDE); +RUNTEST 100 TCK; +SDR 16 TDI (77FF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BBFA); +RUNTEST 100 TCK; +SDR 16 TDI (BBFF); +RUNTEST 100 TCK; +SDR 16 TDI (7DFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (B55F); +RUNTEST 100 TCK; +SDR 16 TDI (DFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FF7); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; SDR 16 TDI (AFFF); RUNTEST 100 TCK; -SDR 16 TDI (D7FF); +SDR 16 TDI (FFFF); RUNTEST 100 TCK; -SDR 16 TDI (7FFF); +SDR 16 TDI (7FDF); RUNTEST 100 TCK; -SDR 16 TDI (FEFF); +SDR 16 TDI (FF7F); RUNTEST 100 TCK; -SDR 16 TDI (99D7); +SDR 16 TDI (BEFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFC); +RUNTEST 100 TCK; +SDR 16 TDI (7FFE); +RUNTEST 100 TCK; +SDR 16 TDI (FDFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFBF); +RUNTEST 100 TCK; +SDR 16 TDI (FFF5); +RUNTEST 100 TCK; +SDR 16 TDI (69FF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (AAAD); +RUNTEST 100 TCK; +SDR 16 TDI (7BF7); +RUNTEST 100 TCK; +SDR 16 TDI (6FFD); +RUNTEST 100 TCK; +SDR 16 TDI (DFDD); RUNTEST 100 TCK; SDR 16 TDI (BFFF); RUNTEST 100 TCK; -SDR 16 TDI (7DEE); +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7DFF); RUNTEST 100 TCK; SDR 16 TDI (FFDF); RUNTEST 100 TCK; -SDR 16 TDI (BDDF); +SDR 16 TDI (BFBF); RUNTEST 100 TCK; -SDR 16 TDI (EFF7); +SDR 16 TDI (FF6F); RUNTEST 100 TCK; -SDR 16 TDI (7F7D); +SDR 16 TDI (7FFF); RUNTEST 100 TCK; -SDR 16 TDI (FBBF); +SDR 16 TDI (F7FF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7DFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FBFF); +RUNTEST 100 TCK; +SDR 16 TDI (BEEF); +RUNTEST 100 TCK; +SDR 16 TDI (FFF5); +RUNTEST 100 TCK; +SDR 16 TDI (6FF7); +RUNTEST 100 TCK; +SDR 16 TDI (F9FF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFB); +RUNTEST 100 TCK; +SDR 16 TDI (7FFE); +RUNTEST 100 TCK; +SDR 16 TDI (FEFD); RUNTEST 100 TCK; SDR 16 TDI (BFFC); RUNTEST 100 TCK; @@ -4925,543 +1757,1279 @@ SDR 16 TDI (7FFF); RUNTEST 100 TCK; SDR 16 TDI (FFFF); RUNTEST 100 TCK; -SDR 16 TDI (9FFF); +SDR 16 TDI (BFFD); RUNTEST 100 TCK; -SDR 16 TDI (FEFF); +SDR 16 TDI (FFBF); RUNTEST 100 TCK; -SDR 16 TDI (5FFD); +SDR 16 TDI (7FF7); RUNTEST 100 TCK; -SDR 16 TDI (FF5F); +SDR 16 TDI (5777); RUNTEST 100 TCK; -SDR 16 TDI (BFFF); +SDR 16 TDI (BFFE); +RUNTEST 100 TCK; +SDR 16 TDI (FFBD); RUNTEST 100 TCK; SDR 16 TDI (7FFF); RUNTEST 100 TCK; -SDR 16 TDI (7FDD); +SDR 16 TDI (FFFD); +RUNTEST 100 TCK; +SDR 16 TDI (B37F); +RUNTEST 100 TCK; +SDR 16 TDI (DDCF); +RUNTEST 100 TCK; +SDR 16 TDI (7BFF); RUNTEST 100 TCK; SDR 16 TDI (FBFF); RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FD6F); -RUNTEST 100 TCK; -SDR 16 TDI (6EFF); -RUNTEST 100 TCK; -SDR 16 TDI (DFFF); -RUNTEST 100 TCK; -SDR 16 TDI (9BEE); -RUNTEST 100 TCK; -SDR 16 TDI (FBFB); -RUNTEST 100 TCK; -SDR 16 TDI (57FF); +SDR 16 TDI (BFBF); RUNTEST 100 TCK; SDR 16 TDI (FFFF); RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFEF); -RUNTEST 100 TCK; SDR 16 TDI (7FFF); RUNTEST 100 TCK; SDR 16 TDI (FFFF); RUNTEST 100 TCK; -SDR 16 TDI (BBFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFF7); -RUNTEST 100 TCK; -SDR 16 TDI (5F77); -RUNTEST 100 TCK; -SDR 16 TDI (AF7D); -RUNTEST 100 TCK; -SDR 16 TDI (9F7F); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7BF9); -RUNTEST 100 TCK; -SDR 16 TDI (FB5F); -RUNTEST 100 TCK; -SDR 16 TDI (9FFF); +SDR 16 TDI (BFFF); RUNTEST 100 TCK; SDR 16 TDI (BFFF); RUNTEST 100 TCK; -SDR 16 TDI (5FFF); +SDR 16 TDI (7FEE); RUNTEST 100 TCK; -SDR 16 TDI (FFFF); +SDR 16 TDI (D4ED); RUNTEST 100 TCK; SDR 16 TDI (BFFF); RUNTEST 100 TCK; -SDR 16 TDI (BBDF); +SDR 16 TDI (DFFB); RUNTEST 100 TCK; -SDR 16 TDI (57EC); +SDR 16 TDI (6BFF); RUNTEST 100 TCK; -SDR 16 TDI (EF7F); +SDR 16 TDI (F5BF); RUNTEST 100 TCK; -SDR 16 TDI (9FFB); +SDR 16 TDI (AFFF); RUNTEST 100 TCK; -SDR 16 TDI (FFFB); +SDR 16 TDI (FEFE); RUNTEST 100 TCK; -SDR 16 TDI (7FFE); +SDR 16 TDI (6FFD); RUNTEST 100 TCK; -SDR 16 TDI (EFFF); +SDR 16 TDI (F5FE); RUNTEST 100 TCK; -SDR 16 TDI (9EFF); -RUNTEST 100 TCK; -SDR 16 TDI (FF7F); -RUNTEST 100 TCK; -SDR 16 TDI (4FFF); -RUNTEST 100 TCK; -SDR 16 TDI (D7FF); -RUNTEST 100 TCK; -SDR 16 TDI (BDF7); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); +SDR 16 TDI (BF9E); RUNTEST 100 TCK; SDR 16 TDI (5FFF); RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; SDR 16 TDI (FFFF); RUNTEST 100 TCK; -SDR 16 TDI (9FFF); +SDR 16 TDI (BEEF); +RUNTEST 100 TCK; +SDR 16 TDI (EF3F); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (EBDF); +RUNTEST 100 TCK; +SDR 16 TDI (AFED); +RUNTEST 100 TCK; +SDR 16 TDI (FFF6); +RUNTEST 100 TCK; +SDR 16 TDI (773F); +RUNTEST 100 TCK; +SDR 16 TDI (DBCE); +RUNTEST 100 TCK; +SDR 16 TDI (B8BF); +RUNTEST 100 TCK; +SDR 16 TDI (9BF3); +RUNTEST 100 TCK; +SDR 16 TDI (77FE); +RUNTEST 100 TCK; +SDR 16 TDI (FEDF); +RUNTEST 100 TCK; +SDR 16 TDI (BDFD); +RUNTEST 100 TCK; +SDR 16 TDI (FFEA); +RUNTEST 100 TCK; +SDR 16 TDI (77FF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFC); +RUNTEST 100 TCK; +SDR 16 TDI (53F3); +RUNTEST 100 TCK; +SDR 16 TDI (67F1); +RUNTEST 100 TCK; +SDR 16 TDI (3F33); +RUNTEST 100 TCK; +SDR 16 TDI (BEFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFBD); +RUNTEST 100 TCK; +SDR 16 TDI (7FEF); +RUNTEST 100 TCK; +SDR 16 TDI (FE7D); +RUNTEST 100 TCK; +SDR 16 TDI (BF5F); +RUNTEST 100 TCK; +SDR 16 TDI (FF8D); +RUNTEST 100 TCK; +SDR 16 TDI (7BFF); +RUNTEST 100 TCK; +SDR 16 TDI (FBFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFB); RUNTEST 100 TCK; SDR 16 TDI (FDFF); RUNTEST 100 TCK; SDR 16 TDI (7FFF); RUNTEST 100 TCK; -SDR 16 TDI (FFBF); +SDR 16 TDI (FFFF); RUNTEST 100 TCK; -SDR 16 TDI (9BFF); +SDR 16 TDI (B59C); RUNTEST 100 TCK; -SDR 16 TDI (7FFF); +SDR 16 TDI (000F); RUNTEST 100 TCK; -SDR 16 TDI (5ED3); +SDR 16 TDI (7FC0); RUNTEST 100 TCK; -SDR 16 TDI (D77D); +SDR 16 TDI (0200); RUNTEST 100 TCK; -SDR 16 TDI (BFFF); +SDR 16 TDI (BE9F); RUNTEST 100 TCK; -SDR 16 TDI (FDF7); +SDR 16 TDI (C3E0); RUNTEST 100 TCK; -SDR 16 TDI (59F6); +SDR 16 TDI (6019); RUNTEST 100 TCK; -SDR 16 TDI (FF9F); +SDR 16 TDI (F803); RUNTEST 100 TCK; -SDR 16 TDI (9FFF); +SDR 16 TDI (BF5F); RUNTEST 100 TCK; -SDR 16 TDI (3BFF); +SDR 16 TDI (0098); +RUNTEST 100 TCK; +SDR 16 TDI (60FC); +RUNTEST 100 TCK; +SDR 16 TDI (F00F); +RUNTEST 100 TCK; +SDR 16 TDI (B01F); +RUNTEST 100 TCK; +SDR 16 TDI (8075); +RUNTEST 100 TCK; +SDR 16 TDI (6BFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (AFFC); +RUNTEST 100 TCK; +SDR 16 TDI (000F); +RUNTEST 100 TCK; +SDR 16 TDI (7FA0); +RUNTEST 100 TCK; +SDR 16 TDI (0000); +RUNTEST 100 TCK; +SDR 16 TDI (BE9C); +RUNTEST 100 TCK; +SDR 16 TDI (3370); +RUNTEST 100 TCK; +SDR 16 TDI (6018); +RUNTEST 100 TCK; +SDR 16 TDI (1003); +RUNTEST 100 TCK; +SDR 16 TDI (A7DE); +RUNTEST 100 TCK; +SDR 16 TDI (80B8); +RUNTEST 100 TCK; +SDR 16 TDI (60FC); +RUNTEST 100 TCK; +SDR 16 TDI (FC0D); +RUNTEST 100 TCK; +SDR 16 TDI (B81B); +RUNTEST 100 TCK; +SDR 16 TDI (807F); RUNTEST 100 TCK; SDR 16 TDI (7FFF); RUNTEST 100 TCK; SDR 16 TDI (FFFF); RUNTEST 100 TCK; -SDR 16 TDI (9FF7); +SDR 16 TDI (B95C); RUNTEST 100 TCK; -SDR 16 TDI (BDDF); +SDR 16 TDI (2303); RUNTEST 100 TCK; -SDR 16 TDI (5FFF); +SDR 16 TDI (67F1); RUNTEST 100 TCK; -SDR 16 TDI (D7D7); +SDR 16 TDI (0111); RUNTEST 100 TCK; -SDR 16 TDI (BAFF); +SDR 16 TDI (A928); RUNTEST 100 TCK; -SDR 16 TDI (FFFF); +SDR 16 TDI (3FF1); RUNTEST 100 TCK; -SDR 16 TDI (5FAD); +SDR 16 TDI (6326); RUNTEST 100 TCK; -SDR 16 TDI (FB7F); +SDR 16 TDI (1080); RUNTEST 100 TCK; -SDR 16 TDI (9FFF); +SDR 16 TDI (BF3F); RUNTEST 100 TCK; -SDR 16 TDI (FDFE); +SDR 16 TDI (E098); RUNTEST 100 TCK; -SDR 16 TDI (77FF); +SDR 16 TDI (6CFF); RUNTEST 100 TCK; -SDR 16 TDI (FFFF); +SDR 16 TDI (F90F); RUNTEST 100 TCK; -SDR 16 TDI (9FFF); +SDR 16 TDI (B87F); RUNTEST 100 TCK; -SDR 16 TDI (FBAF); +SDR 16 TDI (8075); RUNTEST 100 TCK; -SDR 16 TDI (5FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (5FEF); -RUNTEST 100 TCK; -SDR 16 TDI (FBFF); -RUNTEST 100 TCK; -SDR 16 TDI (9FBE); -RUNTEST 100 TCK; -SDR 16 TDI (FFFB); -RUNTEST 100 TCK; -SDR 16 TDI (7FFE); -RUNTEST 100 TCK; -SDR 16 TDI (FFFB); -RUNTEST 100 TCK; -SDR 16 TDI (93FF); -RUNTEST 100 TCK; -SDR 16 TDI (BF77); -RUNTEST 100 TCK; -SDR 16 TDI (5EFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BBFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (5FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (9FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFBF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFF7); -RUNTEST 100 TCK; -SDR 16 TDI (8FFD); -RUNTEST 100 TCK; -SDR 16 TDI (FFF7); -RUNTEST 100 TCK; -SDR 16 TDI (5EDD); -RUNTEST 100 TCK; -SDR 16 TDI (BE66); -RUNTEST 100 TCK; -SDR 16 TDI (BBFF); -RUNTEST 100 TCK; -SDR 16 TDI (BDBB); -RUNTEST 100 TCK; -SDR 16 TDI (6FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FEFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFBF); -RUNTEST 100 TCK; -SDR 16 TDI (ADFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (9FFB); -RUNTEST 100 TCK; -SDR 16 TDI (7EEF); -RUNTEST 100 TCK; -SDR 16 TDI (5FFF); -RUNTEST 100 TCK; -SDR 16 TDI (ABBF); -RUNTEST 100 TCK; -SDR 16 TDI (B5BF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FEE); -RUNTEST 100 TCK; -SDR 16 TDI (FBFF); -RUNTEST 100 TCK; -SDR 16 TDI (B7FF); -RUNTEST 100 TCK; -SDR 16 TDI (FF6F); -RUNTEST 100 TCK; -SDR 16 TDI (79FF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (9FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFB7); -RUNTEST 100 TCK; -SDR 16 TDI (5FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (AB5F); -RUNTEST 100 TCK; -SDR 16 TDI (B7FD); -RUNTEST 100 TCK; -SDR 16 TDI (77FF); -RUNTEST 100 TCK; -SDR 16 TDI (AFF6); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (7EFF); -RUNTEST 100 TCK; -SDR 16 TDI (BB9F); -RUNTEST 100 TCK; -SDR 16 TDI (97FF); -RUNTEST 100 TCK; -SDR 16 TDI (FFDD); -RUNTEST 100 TCK; -SDR 16 TDI (5FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFD); -RUNTEST 100 TCK; -SDR 16 TDI (7BFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (AEFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFBF); -RUNTEST 100 TCK; -SDR 16 TDI (7FB6); -RUNTEST 100 TCK; -SDR 16 TDI (FBFF); -RUNTEST 100 TCK; -SDR 16 TDI (979F); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (57FF); -RUNTEST 100 TCK; -SDR 16 TDI (FDF5); -RUNTEST 100 TCK; -SDR 16 TDI (BDDF); -RUNTEST 100 TCK; -SDR 16 TDI (BD7F); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFBF); -RUNTEST 100 TCK; -SDR 16 TDI (BBBF); -RUNTEST 100 TCK; -SDR 16 TDI (7EFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (8A5F); -RUNTEST 100 TCK; -SDR 16 TDI (DFFF); -RUNTEST 100 TCK; -SDR 16 TDI (5FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FF7D); -RUNTEST 100 TCK; -SDR 16 TDI (BFFB); -RUNTEST 100 TCK; -SDR 16 TDI (DBF7); -RUNTEST 100 TCK; -SDR 16 TDI (7DFE); -RUNTEST 100 TCK; -SDR 16 TDI (FF7F); -RUNTEST 100 TCK; -SDR 16 TDI (AEFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFEF); -RUNTEST 100 TCK; -SDR 16 TDI (7FBF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (9FFA); -RUNTEST 100 TCK; -SDR 16 TDI (FFFD); -RUNTEST 100 TCK; -SDR 16 TDI (5BFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (AFFD); -RUNTEST 100 TCK; -SDR 16 TDI (FD7F); -RUNTEST 100 TCK; -SDR 16 TDI (7FEF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFDF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFD); -RUNTEST 100 TCK; -SDR 16 TDI (6EFF); -RUNTEST 100 TCK; -SDR 16 TDI (F5FB); -RUNTEST 100 TCK; -SDR 16 TDI (9DFF); -RUNTEST 100 TCK; -SDR 16 TDI (F6FD); -RUNTEST 100 TCK; -SDR 16 TDI (57FF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFB); -RUNTEST 100 TCK; -SDR 16 TDI (FFFB); -RUNTEST 100 TCK; -SDR 16 TDI (77FF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FD7); -RUNTEST 100 TCK; -SDR 16 TDI (7FFE); -RUNTEST 100 TCK; -SDR 16 TDI (BBDF); -RUNTEST 100 TCK; -SDR 16 TDI (9DF6); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (5FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFD); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (DDFF); -RUNTEST 100 TCK; -SDR 16 TDI (6EFB); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BAEF); -RUNTEST 100 TCK; -SDR 16 TDI (DFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (9FFF); -RUNTEST 100 TCK; -SDR 16 TDI (D5DF); -RUNTEST 100 TCK; -SDR 16 TDI (5FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FF35); -RUNTEST 100 TCK; -SDR 16 TDI (96BD); -RUNTEST 100 TCK; -SDR 16 TDI (EBFD); -RUNTEST 100 TCK; -SDR 16 TDI (5DDF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (BEBD); -RUNTEST 100 TCK; -SDR 16 TDI (F7EF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FBFE); -RUNTEST 100 TCK; -SDR 16 TDI (BEFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (9BFF); -RUNTEST 100 TCK; -SDR 16 TDI (B72F); -RUNTEST 100 TCK; -SDR 16 TDI (4FEF); -RUNTEST 100 TCK; -SDR 16 TDI (9256); -RUNTEST 100 TCK; -SDR 16 TDI (B3DE); -RUNTEST 100 TCK; -SDR 16 TDI (DBFA); -RUNTEST 100 TCK; -SDR 16 TDI (6AFE); -RUNTEST 100 TCK; -SDR 16 TDI (FEB2); -RUNTEST 100 TCK; -SDR 16 TDI (AFFD); -RUNTEST 100 TCK; -SDR 16 TDI (F0D3); -RUNTEST 100 TCK; -SDR 16 TDI (7DFF); -RUNTEST 100 TCK; -SDR 16 TDI (FF7F); -RUNTEST 100 TCK; -SDR 16 TDI (9DED); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (5FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BDFF); -RUNTEST 100 TCK; -SDR 16 TDI (7DDD); -RUNTEST 100 TCK; -SDR 16 TDI (7FB7); -RUNTEST 100 TCK; -SDR 16 TDI (FDBF); -RUNTEST 100 TCK; -SDR 16 TDI (BE6D); -RUNTEST 100 TCK; -SDR 16 TDI (A7FD); -RUNTEST 100 TCK; -SDR 16 TDI (77FF); -RUNTEST 100 TCK; -SDR 16 TDI (DB5D); -RUNTEST 100 TCK; -SDR 16 TDI (97DF); -RUNTEST 100 TCK; -SDR 16 TDI (BF7F); -RUNTEST 100 TCK; -SDR 16 TDI (57BF); -RUNTEST 100 TCK; -SDR 16 TDI (B7FF); -RUNTEST 100 TCK; -SDR 16 TDI (BB5E); -RUNTEST 100 TCK; -SDR 16 TDI (FF7F); -RUNTEST 100 TCK; -SDR 16 TDI (7BFF); +SDR 16 TDI (6BFF); RUNTEST 100 TCK; SDR 16 TDI (FFFF); RUNTEST 100 TCK; SDR 16 TDI (BFFE); RUNTEST 100 TCK; -SDR 16 TDI (CAFB); +SDR 16 TDI (0303); RUNTEST 100 TCK; -SDR 16 TDI (7FFE); +SDR 16 TDI (67E0); RUNTEST 100 TCK; -SDR 16 TDI (7FE9); +SDR 16 TDI (0001); RUNTEST 100 TCK; -SDR 16 TDI (9DB3); +SDR 16 TDI (A92B); +RUNTEST 100 TCK; +SDR 16 TDI (03F0); +RUNTEST 100 TCK; +SDR 16 TDI (6326); +RUNTEST 100 TCK; +SDR 16 TDI (7000); +RUNTEST 100 TCK; +SDR 16 TDI (BE9F); +RUNTEST 100 TCK; +SDR 16 TDI (E0C2); +RUNTEST 100 TCK; +SDR 16 TDI (6CFF); +RUNTEST 100 TCK; +SDR 16 TDI (FC0F); +RUNTEST 100 TCK; +SDR 16 TDI (B87F); +RUNTEST 100 TCK; +SDR 16 TDI (807F); RUNTEST 100 TCK; SDR 16 TDI (7FFF); RUNTEST 100 TCK; -SDR 16 TDI (5D5F); +SDR 16 TDI (FFFF); RUNTEST 100 TCK; -SDR 16 TDI (75FF); +SDR 16 TDI (BAAE); RUNTEST 100 TCK; -SDR 16 TDI (B83F); +SDR 16 TDI (3181); RUNTEST 100 TCK; -SDR 16 TDI (CFEC); +SDR 16 TDI (63E2); +RUNTEST 100 TCK; +SDR 16 TDI (6023); +RUNTEST 100 TCK; +SDR 16 TDI (BBBB); +RUNTEST 100 TCK; +SDR 16 TDI (B9F3); +RUNTEST 100 TCK; +SDR 16 TDI (662E); +RUNTEST 100 TCK; +SDR 16 TDI (F682); +RUNTEST 100 TCK; +SDR 16 TDI (B8CF); +RUNTEST 100 TCK; +SDR 16 TDI (98B2); +RUNTEST 100 TCK; +SDR 16 TDI (63CC); +RUNTEST 100 TCK; +SDR 16 TDI (ECC7); +RUNTEST 100 TCK; +SDR 16 TDI (B999); +RUNTEST 100 TCK; +SDR 16 TDI (99FE); +RUNTEST 100 TCK; +SDR 16 TDI (77FF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (6732); +RUNTEST 100 TCK; +SDR 16 TDI (6557); +RUNTEST 100 TCK; +SDR 16 TDI (2776); +RUNTEST 100 TCK; +SDR 16 TDI (B111); +RUNTEST 100 TCK; +SDR 16 TDI (10AB); +RUNTEST 100 TCK; +SDR 16 TDI (7364); +RUNTEST 100 TCK; +SDR 16 TDI (58DC); +RUNTEST 100 TCK; +SDR 16 TDI (B315); +RUNTEST 100 TCK; +SDR 16 TDI (4D89); +RUNTEST 100 TCK; +SDR 16 TDI (79DC); +RUNTEST 100 TCK; +SDR 16 TDI (C9CA); +RUNTEST 100 TCK; +SDR 16 TDI (B199); +RUNTEST 100 TCK; +SDR 16 TDI (99FF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FD9D); +RUNTEST 100 TCK; +SDR 16 TDI (7FDF); +RUNTEST 100 TCK; +SDR 16 TDI (FDFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFE7); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (F7F7); +RUNTEST 100 TCK; +SDR 16 TDI (BCFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FF7); +RUNTEST 100 TCK; +SDR 16 TDI (6FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FF7F); +RUNTEST 100 TCK; +SDR 16 TDI (B77F); +RUNTEST 100 TCK; +SDR 16 TDI (F77F); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7BFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FF7); +RUNTEST 100 TCK; +SDR 16 TDI (F6FF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (DFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFBF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7F7B); +RUNTEST 100 TCK; +SDR 16 TDI (DFDF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (B7DF); +RUNTEST 100 TCK; +SDR 16 TDI (FDF7); +RUNTEST 100 TCK; +SDR 16 TDI (6FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (BBE9); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFD); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FDFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFEF); +RUNTEST 100 TCK; +SDR 16 TDI (FFDF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FDFB); +RUNTEST 100 TCK; +SDR 16 TDI (77FF); +RUNTEST 100 TCK; +SDR 16 TDI (EFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFD); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFD); +RUNTEST 100 TCK; +SDR 16 TDI (7F7B); +RUNTEST 100 TCK; +SDR 16 TDI (FEDF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFBB); +RUNTEST 100 TCK; +SDR 16 TDI (BBFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FF7); +RUNTEST 100 TCK; +SDR 16 TDI (FEFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (EFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFBF); +RUNTEST 100 TCK; +SDR 16 TDI (DFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (EFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFD); +RUNTEST 100 TCK; +SDR 16 TDI (FFEF); +RUNTEST 100 TCK; +SDR 16 TDI (6FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFD); +RUNTEST 100 TCK; +SDR 16 TDI (A7DF); +RUNTEST 100 TCK; +SDR 16 TDI (7FF9); +RUNTEST 100 TCK; +SDR 16 TDI (77EF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (69FF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BDFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FEF7); +RUNTEST 100 TCK; +SDR 16 TDI (7FEF); +RUNTEST 100 TCK; +SDR 16 TDI (FF3F); +RUNTEST 100 TCK; +SDR 16 TDI (BDFF); +RUNTEST 100 TCK; +SDR 16 TDI (F7FF); RUNTEST 100 TCK; SDR 16 TDI (7FFB); RUNTEST 100 TCK; +SDR 16 TDI (EFB7); +RUNTEST 100 TCK; +SDR 16 TDI (BDBF); +RUNTEST 100 TCK; +SDR 16 TDI (DFEF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFEF); +RUNTEST 100 TCK; +SDR 16 TDI (BFDF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFD7); +RUNTEST 100 TCK; +SDR 16 TDI (FDFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (EFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFDA); +RUNTEST 100 TCK; +SDR 16 TDI (EFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FB7); +RUNTEST 100 TCK; +SDR 16 TDI (FEFE); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (DFBF); +RUNTEST 100 TCK; +SDR 16 TDI (7BFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFDF); +RUNTEST 100 TCK; +SDR 16 TDI (BDDF); +RUNTEST 100 TCK; +SDR 16 TDI (FFF7); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFE); +RUNTEST 100 TCK; +SDR 16 TDI (FFD7); +RUNTEST 100 TCK; +SDR 16 TDI (77EF); +RUNTEST 100 TCK; +SDR 16 TDI (FF5A); +RUNTEST 100 TCK; +SDR 16 TDI (BAFF); +RUNTEST 100 TCK; +SDR 16 TDI (B7F9); +RUNTEST 100 TCK; +SDR 16 TDI (6FFD); +RUNTEST 100 TCK; +SDR 16 TDI (DF77); +RUNTEST 100 TCK; +SDR 16 TDI (BDBF); +RUNTEST 100 TCK; +SDR 16 TDI (FFF6); +RUNTEST 100 TCK; +SDR 16 TDI (7DFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (E6FF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (A5FB); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (77FB); +RUNTEST 100 TCK; +SDR 16 TDI (F5E6); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FD7D); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (DDFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFA); +RUNTEST 100 TCK; +SDR 16 TDI (AFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFD); +RUNTEST 100 TCK; +SDR 16 TDI (FFA7); +RUNTEST 100 TCK; +SDR 16 TDI (7FEF); +RUNTEST 100 TCK; +SDR 16 TDI (EDBB); +RUNTEST 100 TCK; +SDR 16 TDI (BF5E); +RUNTEST 100 TCK; +SDR 16 TDI (7FFB); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (DFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7BE7); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BBB7); +RUNTEST 100 TCK; +SDR 16 TDI (FDFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFD7); +RUNTEST 100 TCK; +SDR 16 TDI (7FFE); +RUNTEST 100 TCK; +SDR 16 TDI (FEEE); +RUNTEST 100 TCK; +SDR 16 TDI (BDDF); +RUNTEST 100 TCK; +SDR 16 TDI (7FF7); +RUNTEST 100 TCK; +SDR 16 TDI (7EFD); +RUNTEST 100 TCK; +SDR 16 TDI (D7F7); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BDFD); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BDFF); +RUNTEST 100 TCK; +SDR 16 TDI (F7FF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFD); +RUNTEST 100 TCK; +SDR 16 TDI (D5BF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (CBBB); +RUNTEST 100 TCK; +SDR 16 TDI (B776); +RUNTEST 100 TCK; +SDR 16 TDI (FBFF); +RUNTEST 100 TCK; +SDR 16 TDI (6FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FDEE); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FF7F); +RUNTEST 100 TCK; +SDR 16 TDI (77E7); +RUNTEST 100 TCK; +SDR 16 TDI (DEEF); +RUNTEST 100 TCK; +SDR 16 TDI (BFCB); +RUNTEST 100 TCK; +SDR 16 TDI (5DFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFE); +RUNTEST 100 TCK; +SDR 16 TDI (FBBF); +RUNTEST 100 TCK; +SDR 16 TDI (7FB7); +RUNTEST 100 TCK; +SDR 16 TDI (EEAD); +RUNTEST 100 TCK; +SDR 16 TDI (BBEF); +RUNTEST 100 TCK; +SDR 16 TDI (FFF6); +RUNTEST 100 TCK; +SDR 16 TDI (7FFC); +RUNTEST 100 TCK; +SDR 16 TDI (DEF7); +RUNTEST 100 TCK; +SDR 16 TDI (BDFF); +RUNTEST 100 TCK; +SDR 16 TDI (DFB5); +RUNTEST 100 TCK; +SDR 16 TDI (77FB); +RUNTEST 100 TCK; +SDR 16 TDI (FDFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFBD); +RUNTEST 100 TCK; +SDR 16 TDI (DFFD); +RUNTEST 100 TCK; +SDR 16 TDI (7BFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BBBF); +RUNTEST 100 TCK; +SDR 16 TDI (6FE5); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; SDR 16 TDI (FFFE); RUNTEST 100 TCK; -SDR 16 TDI (BEFB); +SDR 16 TDI (BDBF); +RUNTEST 100 TCK; +SDR 16 TDI (EFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7F2F); +RUNTEST 100 TCK; +SDR 16 TDI (FFDE); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FDD); +RUNTEST 100 TCK; +SDR 16 TDI (ABBF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (F3FF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFBF); +RUNTEST 100 TCK; +SDR 16 TDI (EFFD); +RUNTEST 100 TCK; +SDR 16 TDI (77FE); +RUNTEST 100 TCK; +SDR 16 TDI (FFDF); +RUNTEST 100 TCK; +SDR 16 TDI (BEF7); +RUNTEST 100 TCK; +SDR 16 TDI (77FF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (BBBB); +RUNTEST 100 TCK; +SDR 16 TDI (B7BF); +RUNTEST 100 TCK; +SDR 16 TDI (F7FE); +RUNTEST 100 TCK; +SDR 16 TDI (7DBF); +RUNTEST 100 TCK; +SDR 16 TDI (F7AF); +RUNTEST 100 TCK; +SDR 16 TDI (AFFE); +RUNTEST 100 TCK; +SDR 16 TDI (F6FD); +RUNTEST 100 TCK; +SDR 16 TDI (7BFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (B7FF); +RUNTEST 100 TCK; +SDR 16 TDI (F5E7); +RUNTEST 100 TCK; +SDR 16 TDI (6FFC); +RUNTEST 100 TCK; +SDR 16 TDI (DFFD); +RUNTEST 100 TCK; +SDR 16 TDI (BFBD); +RUNTEST 100 TCK; +SDR 16 TDI (7FFB); +RUNTEST 100 TCK; +SDR 16 TDI (7B33); +RUNTEST 100 TCK; +SDR 16 TDI (FFDF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFF3); +RUNTEST 100 TCK; +SDR 16 TDI (7FDF); +RUNTEST 100 TCK; +SDR 16 TDI (EDDF); +RUNTEST 100 TCK; +SDR 16 TDI (BFB7); +RUNTEST 100 TCK; +SDR 16 TDI (FFFB); +RUNTEST 100 TCK; +SDR 16 TDI (77FF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFD); +RUNTEST 100 TCK; +SDR 16 TDI (7F7F); +RUNTEST 100 TCK; +SDR 16 TDI (7FEF); +RUNTEST 100 TCK; +SDR 16 TDI (F577); +RUNTEST 100 TCK; +SDR 16 TDI (BFDF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFE); +RUNTEST 100 TCK; +SDR 16 TDI (7FFE); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BF3F); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (BB7D); +RUNTEST 100 TCK; +SDR 16 TDI (FDFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FDFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFB); +RUNTEST 100 TCK; +SDR 16 TDI (DDFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFF6); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (77FF); +RUNTEST 100 TCK; +SDR 16 TDI (F5BE); +RUNTEST 100 TCK; +SDR 16 TDI (BAFD); +RUNTEST 100 TCK; +SDR 16 TDI (FFBF); +RUNTEST 100 TCK; +SDR 16 TDI (7AFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFEE); +RUNTEST 100 TCK; +SDR 16 TDI (DF7F); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BDB7); +RUNTEST 100 TCK; +SDR 16 TDI (7FFC); +RUNTEST 100 TCK; +SDR 16 TDI (FA29); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (7E44); +RUNTEST 100 TCK; +SDR 16 TDI (7EFF); +RUNTEST 100 TCK; +SDR 16 TDI (BE1D); +RUNTEST 100 TCK; +SDR 16 TDI (CFCA); +RUNTEST 100 TCK; +SDR 16 TDI (77FF); +RUNTEST 100 TCK; +SDR 16 TDI (761F); +RUNTEST 100 TCK; +SDR 16 TDI (BFBB); +RUNTEST 100 TCK; +SDR 16 TDI (5FFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (56FE); +RUNTEST 100 TCK; +SDR 16 TDI (7FAF); +RUNTEST 100 TCK; +SDR 16 TDI (4FFF); +RUNTEST 100 TCK; +SDR 16 TDI (B616); +RUNTEST 100 TCK; +SDR 16 TDI (D7F4); +RUNTEST 100 TCK; +SDR 16 TDI (6FBB); +RUNTEST 100 TCK; +SDR 16 TDI (B727); +RUNTEST 100 TCK; +SDR 16 TDI (BDFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFF7); +RUNTEST 100 TCK; +SDR 16 TDI (7E9D); +RUNTEST 100 TCK; +SDR 16 TDI (BDFF); +RUNTEST 100 TCK; +SDR 16 TDI (BBF5); +RUNTEST 100 TCK; +SDR 16 TDI (EE6A); +RUNTEST 100 TCK; +SDR 16 TDI (77FF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFC); +RUNTEST 100 TCK; +SDR 16 TDI (EB49); +RUNTEST 100 TCK; +SDR 16 TDI (67F3); +RUNTEST 100 TCK; +SDR 16 TDI (B5D6); +RUNTEST 100 TCK; +SDR 16 TDI (BDE9); +RUNTEST 100 TCK; +SDR 16 TDI (BFFB); +RUNTEST 100 TCK; +SDR 16 TDI (7BFF); +RUNTEST 100 TCK; +SDR 16 TDI (D9D8); +RUNTEST 100 TCK; +SDR 16 TDI (B3FF); +RUNTEST 100 TCK; +SDR 16 TDI (FFBD); +RUNTEST 100 TCK; +SDR 16 TDI (79E7); +RUNTEST 100 TCK; +SDR 16 TDI (CBEF); +RUNTEST 100 TCK; +SDR 16 TDI (AECE); +RUNTEST 100 TCK; +SDR 16 TDI (B1FF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (B9AE); +RUNTEST 100 TCK; +SDR 16 TDI (F238); +RUNTEST 100 TCK; +SDR 16 TDI (7FD3); +RUNTEST 100 TCK; +SDR 16 TDI (4B82); +RUNTEST 100 TCK; +SDR 16 TDI (A001); +RUNTEST 100 TCK; +SDR 16 TDI (7FE7); +RUNTEST 100 TCK; +SDR 16 TDI (6200); +RUNTEST 100 TCK; +SDR 16 TDI (3E81); +RUNTEST 100 TCK; +SDR 16 TDI (A61F); +RUNTEST 100 TCK; +SDR 16 TDI (07E7); +RUNTEST 100 TCK; +SDR 16 TDI (78A0); +RUNTEST 100 TCK; +SDR 16 TDI (075F); +RUNTEST 100 TCK; +SDR 16 TDI (B118); +RUNTEST 100 TCK; +SDR 16 TDI (8075); +RUNTEST 100 TCK; +SDR 16 TDI (6BFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (B6AC); +RUNTEST 100 TCK; +SDR 16 TDI (0A00); +RUNTEST 100 TCK; +SDR 16 TDI (67A2); +RUNTEST 100 TCK; +SDR 16 TDI (0022); +RUNTEST 100 TCK; +SDR 16 TDI (A100); +RUNTEST 100 TCK; +SDR 16 TDI (43DC); +RUNTEST 100 TCK; +SDR 16 TDI (6200); +RUNTEST 100 TCK; +SDR 16 TDI (1A58); +RUNTEST 100 TCK; +SDR 16 TDI (A613); +RUNTEST 100 TCK; +SDR 16 TDI (8787); +RUNTEST 100 TCK; +SDR 16 TDI (74A0); +RUNTEST 100 TCK; +SDR 16 TDI (000F); +RUNTEST 100 TCK; +SDR 16 TDI (A918); +RUNTEST 100 TCK; +SDR 16 TDI (007F); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFE); +RUNTEST 100 TCK; +SDR 16 TDI (FFF7); +RUNTEST 100 TCK; +SDR 16 TDI (6FEF); +RUNTEST 100 TCK; +SDR 16 TDI (6FFE); +RUNTEST 100 TCK; +SDR 16 TDI (A023); +RUNTEST 100 TCK; +SDR 16 TDI (83F8); +RUNTEST 100 TCK; +SDR 16 TDI (6222); +RUNTEST 100 TCK; +SDR 16 TDI (19E2); +RUNTEST 100 TCK; +SDR 16 TDI (AF1F); +RUNTEST 100 TCK; +SDR 16 TDI (CFE7); +RUNTEST 100 TCK; +SDR 16 TDI (66B0); +RUNTEST 100 TCK; +SDR 16 TDI (C06F); +RUNTEST 100 TCK; +SDR 16 TDI (B918); +RUNTEST 100 TCK; +SDR 16 TDI (20F5); +RUNTEST 100 TCK; +SDR 16 TDI (6BFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BF7B); +RUNTEST 100 TCK; +SDR 16 TDI (04CF); +RUNTEST 100 TCK; +SDR 16 TDI (6FE7); +RUNTEST 100 TCK; +SDR 16 TDI (6E39); +RUNTEST 100 TCK; +SDR 16 TDI (BC02); +RUNTEST 100 TCK; +SDR 16 TDI (83FC); +RUNTEST 100 TCK; +SDR 16 TDI (6200); +RUNTEST 100 TCK; +SDR 16 TDI (1960); +RUNTEST 100 TCK; +SDR 16 TDI (AE1F); +RUNTEST 100 TCK; +SDR 16 TDI (CF8F); +RUNTEST 100 TCK; +SDR 16 TDI (68BF); +RUNTEST 100 TCK; +SDR 16 TDI (402F); +RUNTEST 100 TCK; +SDR 16 TDI (B910); +RUNTEST 100 TCK; +SDR 16 TDI (007F); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (B89F); +RUNTEST 100 TCK; +SDR 16 TDI (3B3B); +RUNTEST 100 TCK; +SDR 16 TDI (73EE); +RUNTEST 100 TCK; +SDR 16 TDI (E666); +RUNTEST 100 TCK; +SDR 16 TDI (AA23); +RUNTEST 100 TCK; +SDR 16 TDI (19F4); +RUNTEST 100 TCK; +SDR 16 TDI (6626); +RUNTEST 100 TCK; +SDR 16 TDI (DCCC); +RUNTEST 100 TCK; +SDR 16 TDI (B18F); +RUNTEST 100 TCK; +SDR 16 TDI (99A3); +RUNTEST 100 TCK; +SDR 16 TDI (61E8); +RUNTEST 100 TCK; +SDR 16 TDI (CCE7); +RUNTEST 100 TCK; +SDR 16 TDI (B899); +RUNTEST 100 TCK; +SDR 16 TDI (98FA); +RUNTEST 100 TCK; +SDR 16 TDI (77FF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFB); +RUNTEST 100 TCK; +SDR 16 TDI (7373); +RUNTEST 100 TCK; +SDR 16 TDI (6146); +RUNTEST 100 TCK; +SDR 16 TDI (7777); +RUNTEST 100 TCK; +SDR 16 TDI (B376); +RUNTEST 100 TCK; +SDR 16 TDI (72A3); +RUNTEST 100 TCK; +SDR 16 TDI (7736); +RUNTEST 100 TCK; +SDR 16 TDI (3999); +RUNTEST 100 TCK; +SDR 16 TDI (BB35); +RUNTEST 100 TCK; +SDR 16 TDI (5998); +RUNTEST 100 TCK; +SDR 16 TDI (7BDD); +RUNTEST 100 TCK; +SDR 16 TDI (DDC2); +RUNTEST 100 TCK; +SDR 16 TDI (B5CD); +RUNTEST 100 TCK; +SDR 16 TDI (9DFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BD6F); +RUNTEST 100 TCK; +SDR 16 TDI (9F9D); +RUNTEST 100 TCK; +SDR 16 TDI (7BDD); +RUNTEST 100 TCK; +SDR 16 TDI (CEEE); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (DBFE); +RUNTEST 100 TCK; +SDR 16 TDI (6FFF); +RUNTEST 100 TCK; +SDR 16 TDI (DEFF); +RUNTEST 100 TCK; +SDR 16 TDI (BDFF); +RUNTEST 100 TCK; +SDR 16 TDI (3FF7); +RUNTEST 100 TCK; +SDR 16 TDI (6FFF); +RUNTEST 100 TCK; +SDR 16 TDI (EE73); +RUNTEST 100 TCK; +SDR 16 TDI (BFFB); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (E7F5); +RUNTEST 100 TCK; +SDR 16 TDI (6FFF); +RUNTEST 100 TCK; +SDR 16 TDI (7F7B); +RUNTEST 100 TCK; +SDR 16 TDI (AD9F); +RUNTEST 100 TCK; +SDR 16 TDI (FBFF); +RUNTEST 100 TCK; +SDR 16 TDI (7DFC); +RUNTEST 100 TCK; +SDR 16 TDI (F7BF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FDDB); +RUNTEST 100 TCK; +SDR 16 TDI (7F7F); +RUNTEST 100 TCK; +SDR 16 TDI (EFEF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); RUNTEST 100 TCK; SDR 16 TDI (3FFF); RUNTEST 100 TCK; @@ -5469,609 +3037,33 @@ SDR 16 TDI (7FFF); RUNTEST 100 TCK; SDR 16 TDI (FFFF); RUNTEST 100 TCK; -SDR 16 TDI (875C); -RUNTEST 100 TCK; -SDR 16 TDI (B834); -RUNTEST 100 TCK; -SDR 16 TDI (47D8); -RUNTEST 100 TCK; -SDR 16 TDI (807B); -RUNTEST 100 TCK; -SDR 16 TDI (B23E); -RUNTEST 100 TCK; -SDR 16 TDI (23ED); -RUNTEST 100 TCK; -SDR 16 TDI (6FFE); -RUNTEST 100 TCK; -SDR 16 TDI (7B3A); -RUNTEST 100 TCK; -SDR 16 TDI (B997); -RUNTEST 100 TCK; -SDR 16 TDI (192C); -RUNTEST 100 TCK; -SDR 16 TDI (617A); -RUNTEST 100 TCK; -SDR 16 TDI (7F0F); -RUNTEST 100 TCK; -SDR 16 TDI (9000); -RUNTEST 100 TCK; -SDR 16 TDI (67EA); -RUNTEST 100 TCK; -SDR 16 TDI (5FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (AEFC); -RUNTEST 100 TCK; -SDR 16 TDI (9420); -RUNTEST 100 TCK; -SDR 16 TDI (67B8); -RUNTEST 100 TCK; -SDR 16 TDI (821E); -RUNTEST 100 TCK; -SDR 16 TDI (A0F8); -RUNTEST 100 TCK; -SDR 16 TDI (0FD3); -RUNTEST 100 TCK; -SDR 16 TDI (667E); -RUNTEST 100 TCK; -SDR 16 TDI (1814); -RUNTEST 100 TCK; -SDR 16 TDI (999B); -RUNTEST 100 TCK; -SDR 16 TDI (980C); -RUNTEST 100 TCK; -SDR 16 TDI (417A); -RUNTEST 100 TCK; -SDR 16 TDI (70CD); -RUNTEST 100 TCK; -SDR 16 TDI (B800); -RUNTEST 100 TCK; -SDR 16 TDI (607F); -RUNTEST 100 TCK; -SDR 16 TDI (6FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (B75F); -RUNTEST 100 TCK; -SDR 16 TDI (763B); -RUNTEST 100 TCK; -SDR 16 TDI (7FE0); -RUNTEST 100 TCK; -SDR 16 TDI (109B); -RUNTEST 100 TCK; -SDR 16 TDI (923C); -RUNTEST 100 TCK; -SDR 16 TDI (2FF1); -RUNTEST 100 TCK; -SDR 16 TDI (47FE); -RUNTEST 100 TCK; -SDR 16 TDI (7CB0); -RUNTEST 100 TCK; -SDR 16 TDI (BBBF); -RUNTEST 100 TCK; -SDR 16 TDI (D86E); -RUNTEST 100 TCK; -SDR 16 TDI (61A4); -RUNTEST 100 TCK; -SDR 16 TDI (A0FF); -RUNTEST 100 TCK; -SDR 16 TDI (B8C0); -RUNTEST 100 TCK; -SDR 16 TDI (986B); -RUNTEST 100 TCK; -SDR 16 TDI (77FF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; SDR 16 TDI (BFFF); RUNTEST 100 TCK; -SDR 16 TDI (7C20); +SDR 16 TDI (7EEF); RUNTEST 100 TCK; -SDR 16 TDI (67E1); +SDR 16 TDI (7FF7); RUNTEST 100 TCK; -SDR 16 TDI (328C); +SDR 16 TDI (F7FF); RUNTEST 100 TCK; -SDR 16 TDI (A3FC); -RUNTEST 100 TCK; -SDR 16 TDI (0FF3); -RUNTEST 100 TCK; -SDR 16 TDI (467E); -RUNTEST 100 TCK; -SDR 16 TDI (1CA0); -RUNTEST 100 TCK; -SDR 16 TDI (A23F); -RUNTEST 100 TCK; -SDR 16 TDI (C02E); -RUNTEST 100 TCK; -SDR 16 TDI (61A4); -RUNTEST 100 TCK; -SDR 16 TDI (AC0F); -RUNTEST 100 TCK; -SDR 16 TDI (9840); -RUNTEST 100 TCK; -SDR 16 TDI (19FE); -RUNTEST 100 TCK; -SDR 16 TDI (5FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFD7); -RUNTEST 100 TCK; -SDR 16 TDI (B23B); -RUNTEST 100 TCK; -SDR 16 TDI (63E6); -RUNTEST 100 TCK; -SDR 16 TDI (FE67); -RUNTEST 100 TCK; -SDR 16 TDI (B330); -RUNTEST 100 TCK; -SDR 16 TDI (B1FE); -RUNTEST 100 TCK; -SDR 16 TDI (6666); -RUNTEST 100 TCK; -SDR 16 TDI (7CFC); -RUNTEST 100 TCK; -SDR 16 TDI (9DCF); -RUNTEST 100 TCK; -SDR 16 TDI (B9F9); -RUNTEST 100 TCK; -SDR 16 TDI (51EE); -RUNTEST 100 TCK; -SDR 16 TDI (EEE7); -RUNTEST 100 TCK; -SDR 16 TDI (B9C9); -RUNTEST 100 TCK; -SDR 16 TDI (BBFA); -RUNTEST 100 TCK; -SDR 16 TDI (77FF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFDF); -RUNTEST 100 TCK; -SDR 16 TDI (3773); -RUNTEST 100 TCK; -SDR 16 TDI (6956); -RUNTEST 100 TCK; -SDR 16 TDI (6777); -RUNTEST 100 TCK; -SDR 16 TDI (9273); -RUNTEST 100 TCK; -SDR 16 TDI (26A1); -RUNTEST 100 TCK; -SDR 16 TDI (5626); -RUNTEST 100 TCK; -SDR 16 TDI (7DCC); -RUNTEST 100 TCK; -SDR 16 TDI (B985); -RUNTEST 100 TCK; -SDR 16 TDI (1C9D); -RUNTEST 100 TCK; -SDR 16 TDI (7B44); -RUNTEST 100 TCK; -SDR 16 TDI (4442); -RUNTEST 100 TCK; -SDR 16 TDI (B5CD); -RUNTEST 100 TCK; -SDR 16 TDI (917F); +SDR 16 TDI (B7F7); RUNTEST 100 TCK; SDR 16 TDI (7FFF); RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (9FF9); -RUNTEST 100 TCK; -SDR 16 TDI (FBDF); -RUNTEST 100 TCK; -SDR 16 TDI (53CF); +SDR 16 TDI (7FF7); RUNTEST 100 TCK; SDR 16 TDI (FEEE); RUNTEST 100 TCK; -SDR 16 TDI (BBFD); -RUNTEST 100 TCK; -SDR 16 TDI (FFEE); -RUNTEST 100 TCK; -SDR 16 TDI (6FDE); -RUNTEST 100 TCK; -SDR 16 TDI (DFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7BFB); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; SDR 16 TDI (B3FF); RUNTEST 100 TCK; -SDR 16 TDI (FFFE); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (7DFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFD); -RUNTEST 100 TCK; -SDR 16 TDI (7BF7); -RUNTEST 100 TCK; -SDR 16 TDI (7E6D); -RUNTEST 100 TCK; -SDR 16 TDI (BEDF); -RUNTEST 100 TCK; -SDR 16 TDI (FEFB); -RUNTEST 100 TCK; -SDR 16 TDI (7B7F); -RUNTEST 100 TCK; -SDR 16 TDI (F7FF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFE); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7577); -RUNTEST 100 TCK; -SDR 16 TDI (6FFD); -RUNTEST 100 TCK; -SDR 16 TDI (F7FF); -RUNTEST 100 TCK; -SDR 16 TDI (B7DD); -RUNTEST 100 TCK; -SDR 16 TDI (FFFB); -RUNTEST 100 TCK; -SDR 16 TDI (777D); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BBFF); -RUNTEST 100 TCK; -SDR 16 TDI (D5D7); -RUNTEST 100 TCK; -SDR 16 TDI (6FFB); -RUNTEST 100 TCK; -SDR 16 TDI (BF7F); -RUNTEST 100 TCK; -SDR 16 TDI (BFF7); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7BFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (AFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FF7); -RUNTEST 100 TCK; -SDR 16 TDI (6FFB); -RUNTEST 100 TCK; -SDR 16 TDI (7BFF); -RUNTEST 100 TCK; -SDR 16 TDI (B7FD); -RUNTEST 100 TCK; -SDR 16 TDI (FFF7); -RUNTEST 100 TCK; -SDR 16 TDI (77FD); -RUNTEST 100 TCK; -SDR 16 TDI (FFAF); -RUNTEST 100 TCK; -SDR 16 TDI (BFBF); -RUNTEST 100 TCK; -SDR 16 TDI (AD77); -RUNTEST 100 TCK; -SDR 16 TDI (7FBF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (AFFF); -RUNTEST 100 TCK; -SDR 16 TDI (F57F); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (F7FF); -RUNTEST 100 TCK; -SDR 16 TDI (BFDF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFD); -RUNTEST 100 TCK; -SDR 16 TDI (7D76); -RUNTEST 100 TCK; -SDR 16 TDI (FDFD); -RUNTEST 100 TCK; -SDR 16 TDI (BB7F); -RUNTEST 100 TCK; -SDR 16 TDI (FFDA); -RUNTEST 100 TCK; -SDR 16 TDI (77FF); -RUNTEST 100 TCK; -SDR 16 TDI (FBBF); -RUNTEST 100 TCK; -SDR 16 TDI (BFF7); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BDFB); -RUNTEST 100 TCK; -SDR 16 TDI (7FFB); -RUNTEST 100 TCK; -SDR 16 TDI (FF5E); -RUNTEST 100 TCK; -SDR 16 TDI (B5DF); -RUNTEST 100 TCK; -SDR 16 TDI (D7FF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFB); -RUNTEST 100 TCK; -SDR 16 TDI (F9BE); -RUNTEST 100 TCK; -SDR 16 TDI (BD3F); -RUNTEST 100 TCK; -SDR 16 TDI (FEF3); -RUNTEST 100 TCK; -SDR 16 TDI (7EF7); -RUNTEST 100 TCK; -SDR 16 TDI (FEFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFEF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFDF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (EFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFA); -RUNTEST 100 TCK; -SDR 16 TDI (5DFF); -RUNTEST 100 TCK; -SDR 16 TDI (EFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FDFF); -RUNTEST 100 TCK; -SDR 16 TDI (77FF); -RUNTEST 100 TCK; -SDR 16 TDI (DFBF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFE); -RUNTEST 100 TCK; -SDR 16 TDI (FBFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (5FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFBF); -RUNTEST 100 TCK; -SDR 16 TDI (AADF); -RUNTEST 100 TCK; -SDR 16 TDI (FFF6); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (EA7E); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FB7B); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (DDFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFF7); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FEDB); -RUNTEST 100 TCK; -SDR 16 TDI (7FFB); -RUNTEST 100 TCK; -SDR 16 TDI (FF7F); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (D7FF); -RUNTEST 100 TCK; -SDR 16 TDI (7BFD); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BB5F); -RUNTEST 100 TCK; -SDR 16 TDI (FFEF); -RUNTEST 100 TCK; -SDR 16 TDI (5DFB); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFF6); -RUNTEST 100 TCK; -SDR 16 TDI (77EF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (F7FB); -RUNTEST 100 TCK; -SDR 16 TDI (5FDF); -RUNTEST 100 TCK; -SDR 16 TDI (EFFB); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (F7FF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFE); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (BF7F); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (5FFD); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (77FF); -RUNTEST 100 TCK; -SDR 16 TDI (EFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FF7); -RUNTEST 100 TCK; -SDR 16 TDI (FFEF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (DFFF); -RUNTEST 100 TCK; -SDR 16 TDI (5FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FF5); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFB); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (DFFF); -RUNTEST 100 TCK; -SDR 16 TDI (5FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFDF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFF9); -RUNTEST 100 TCK; -SDR 16 TDI (77FF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FBFF); -RUNTEST 100 TCK; -SDR 16 TDI (4FBF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFB); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (F7FF); -RUNTEST 100 TCK; -SDR 16 TDI (7FF9); -RUNTEST 100 TCK; -SDR 16 TDI (7FFF); -RUNTEST 100 TCK; SDR 16 TDI (BEFF); RUNTEST 100 TCK; -SDR 16 TDI (DFFF); +SDR 16 TDI (7FDD); +RUNTEST 100 TCK; +SDR 16 TDI (BDFF); +RUNTEST 100 TCK; +SDR 16 TDI (BDBF); +RUNTEST 100 TCK; +SDR 16 TDI (FFDF); RUNTEST 100 TCK; SDR 16 TDI (7FFF); RUNTEST 100 TCK; @@ -6079,47 +3071,319 @@ SDR 16 TDI (FFFF); RUNTEST 100 TCK; SDR 16 TDI (BFFF); RUNTEST 100 TCK; -SDR 16 TDI (FFEE); +SDR 16 TDI (7FFD); RUNTEST 100 TCK; -SDR 16 TDI (5FFF); +SDR 16 TDI (6FFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFD); +RUNTEST 100 TCK; +SDR 16 TDI (B7DF); +RUNTEST 100 TCK; +SDR 16 TDI (77FF); +RUNTEST 100 TCK; +SDR 16 TDI (7BF4); +RUNTEST 100 TCK; +SDR 16 TDI (FF7F); +RUNTEST 100 TCK; +SDR 16 TDI (BBFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFDF); +RUNTEST 100 TCK; +SDR 16 TDI (7FED); +RUNTEST 100 TCK; +SDR 16 TDI (DDFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BBBF); +RUNTEST 100 TCK; +SDR 16 TDI (D7FB); +RUNTEST 100 TCK; +SDR 16 TDI (7FEF); +RUNTEST 100 TCK; +SDR 16 TDI (F6FE); +RUNTEST 100 TCK; +SDR 16 TDI (BD77); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (F7FF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FDFD); +RUNTEST 100 TCK; +SDR 16 TDI (7F7F); +RUNTEST 100 TCK; +SDR 16 TDI (FFDF); +RUNTEST 100 TCK; +SDR 16 TDI (BDFF); +RUNTEST 100 TCK; +SDR 16 TDI (3FFB); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BAFF); +RUNTEST 100 TCK; +SDR 16 TDI (FDFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFDA); +RUNTEST 100 TCK; +SDR 16 TDI (BDBF); +RUNTEST 100 TCK; +SDR 16 TDI (FBFF); +RUNTEST 100 TCK; +SDR 16 TDI (7DFF); +RUNTEST 100 TCK; +SDR 16 TDI (DFFD); +RUNTEST 100 TCK; +SDR 16 TDI (BD7F); +RUNTEST 100 TCK; +SDR 16 TDI (DEF7); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FE7F); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFBB); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); RUNTEST 100 TCK; SDR 16 TDI (FFFF); RUNTEST 100 TCK; SDR 16 TDI (BFFD); RUNTEST 100 TCK; -SDR 16 TDI (EFFD); +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFB); +RUNTEST 100 TCK; +SDR 16 TDI (FFF7); +RUNTEST 100 TCK; +SDR 16 TDI (BFF5); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FDD); +RUNTEST 100 TCK; +SDR 16 TDI (E7DF); +RUNTEST 100 TCK; +SDR 16 TDI (BFBF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7EF5); +RUNTEST 100 TCK; +SDR 16 TDI (DFDF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFE); +RUNTEST 100 TCK; +SDR 16 TDI (FEFF); RUNTEST 100 TCK; SDR 16 TDI (7FFF); RUNTEST 100 TCK; SDR 16 TDI (FFFF); RUNTEST 100 TCK; +SDR 16 TDI (BFFD); +RUNTEST 100 TCK; +SDR 16 TDI (E9FB); +RUNTEST 100 TCK; +SDR 16 TDI (7FEC); +RUNTEST 100 TCK; +SDR 16 TDI (FFDE); +RUNTEST 100 TCK; +SDR 16 TDI (BF77); +RUNTEST 100 TCK; +SDR 16 TDI (E7F7); +RUNTEST 100 TCK; +SDR 16 TDI (7CCC); +RUNTEST 100 TCK; +SDR 16 TDI (FF9D); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FF3B); +RUNTEST 100 TCK; +SDR 16 TDI (7EFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FB77); +RUNTEST 100 TCK; +SDR 16 TDI (7BFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFEB); +RUNTEST 100 TCK; +SDR 16 TDI (BDFE); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; SDR 16 TDI (B7FF); RUNTEST 100 TCK; -SDR 16 TDI (EFFF); +SDR 16 TDI (BD3F); +RUNTEST 100 TCK; +SDR 16 TDI (DFF7); +RUNTEST 100 TCK; +SDR 16 TDI (7FF9); +RUNTEST 100 TCK; +SDR 16 TDI (ED9F); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); RUNTEST 100 TCK; SDR 16 TDI (7FFF); RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); +SDR 16 TDI (7FFF); RUNTEST 100 TCK; SDR 16 TDI (FFFF); RUNTEST 100 TCK; -SDR 16 TDI (5FFF); +SDR 16 TDI (BDFF); +RUNTEST 100 TCK; +SDR 16 TDI (DFAF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFDB); +RUNTEST 100 TCK; +SDR 16 TDI (BAF6); RUNTEST 100 TCK; SDR 16 TDI (FFFF); RUNTEST 100 TCK; +SDR 16 TDI (7B3F); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FBFB); +RUNTEST 100 TCK; +SDR 16 TDI (7D7E); +RUNTEST 100 TCK; +SDR 16 TDI (EFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (AF7F); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BF7E); +RUNTEST 100 TCK; +SDR 16 TDI (76F7); +RUNTEST 100 TCK; +SDR 16 TDI (7FEE); +RUNTEST 100 TCK; +SDR 16 TDI (BCFE); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FF7); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (7F57); +RUNTEST 100 TCK; +SDR 16 TDI (BBFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFF7); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BBF7); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFD); +RUNTEST 100 TCK; +SDR 16 TDI (F7DF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FD7F); +RUNTEST 100 TCK; +SDR 16 TDI (B7BF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FEF); +RUNTEST 100 TCK; +SDR 16 TDI (FF5F); +RUNTEST 100 TCK; SDR 16 TDI (BFFF); RUNTEST 100 TCK; SDR 16 TDI (FDFF); RUNTEST 100 TCK; -SDR 16 TDI (7FFD); +SDR 16 TDI (7EFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BDBF); +RUNTEST 100 TCK; +SDR 16 TDI (DBFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BE7F); +RUNTEST 100 TCK; +SDR 16 TDI (AEB7); +RUNTEST 100 TCK; +SDR 16 TDI (7FFE); +RUNTEST 100 TCK; +SDR 16 TDI (BFBA); +RUNTEST 100 TCK; +SDR 16 TDI (BDF6); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (7D5F); +RUNTEST 100 TCK; +SDR 16 TDI (7FFB); +RUNTEST 100 TCK; +SDR 16 TDI (BDDF); +RUNTEST 100 TCK; +SDR 16 TDI (FFEB); +RUNTEST 100 TCK; +SDR 16 TDI (7FBD); RUNTEST 100 TCK; SDR 16 TDI (DFFF); RUNTEST 100 TCK; -SDR 16 TDI (BFDF); +SDR 16 TDI (BFEF); RUNTEST 100 TCK; -SDR 16 TDI (FFFF); +SDR 16 TDI (EF7F); RUNTEST 100 TCK; SDR 16 TDI (7FFF); RUNTEST 100 TCK; @@ -6127,81 +3391,737 @@ SDR 16 TDI (FFFF); RUNTEST 100 TCK; SDR 16 TDI (BFFF); RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (5FFF); -RUNTEST 100 TCK; -SDR 16 TDI (EAEF); -RUNTEST 100 TCK; -SDR 16 TDI (BBBF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); +SDR 16 TDI (EBDF); RUNTEST 100 TCK; SDR 16 TDI (7FFF); RUNTEST 100 TCK; +SDR 16 TDI (7FB6); +RUNTEST 100 TCK; +SDR 16 TDI (BE5B); +RUNTEST 100 TCK; +SDR 16 TDI (57F9); +RUNTEST 100 TCK; +SDR 16 TDI (6D3F); +RUNTEST 100 TCK; +SDR 16 TDI (5DFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (CFDF); +RUNTEST 100 TCK; +SDR 16 TDI (77BF); +RUNTEST 100 TCK; +SDR 16 TDI (DFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BEFE); +RUNTEST 100 TCK; +SDR 16 TDI (FEF5); +RUNTEST 100 TCK; +SDR 16 TDI (6BFF); +RUNTEST 100 TCK; SDR 16 TDI (FFFF); RUNTEST 100 TCK; +SDR 16 TDI (B6AE); +RUNTEST 100 TCK; +SDR 16 TDI (FDBF); +RUNTEST 100 TCK; +SDR 16 TDI (6FF3); +RUNTEST 100 TCK; +SDR 16 TDI (BEFF); +RUNTEST 100 TCK; SDR 16 TDI (BFFF); RUNTEST 100 TCK; SDR 16 TDI (FFFF); RUNTEST 100 TCK; -SDR 16 TDI (7FFF); +SDR 16 TDI (7FF7); RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (BFFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; -SDR 16 TDI (5FFF); -RUNTEST 100 TCK; -SDR 16 TDI (FFFF); +SDR 16 TDI (F7FD); RUNTEST 100 TCK; SDR 16 TDI (BF7F); RUNTEST 100 TCK; +SDR 16 TDI (FAFC); +RUNTEST 100 TCK; +SDR 16 TDI (7DDF); +RUNTEST 100 TCK; SDR 16 TDI (FFFF); RUNTEST 100 TCK; -SDR 16 TDI (7FF8); +SDR 16 TDI (BFB5); RUNTEST 100 TCK; -SDR 16 TDI (FFBF); +SDR 16 TDI (DFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7DFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (B9AE); +RUNTEST 100 TCK; +SDR 16 TDI (7FD7); +RUNTEST 100 TCK; +SDR 16 TDI (7FFB); +RUNTEST 100 TCK; +SDR 16 TDI (EFBF); +RUNTEST 100 TCK; +SDR 16 TDI (B7FE); +RUNTEST 100 TCK; +SDR 16 TDI (EFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7DFD); +RUNTEST 100 TCK; +SDR 16 TDI (FBDF); +RUNTEST 100 TCK; +SDR 16 TDI (BDAF); +RUNTEST 100 TCK; +SDR 16 TDI (FFEF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FEDF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FCF5); +RUNTEST 100 TCK; +SDR 16 TDI (6BFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FF7F); +RUNTEST 100 TCK; +SDR 16 TDI (7EFF); +RUNTEST 100 TCK; +SDR 16 TDI (DEEF); +RUNTEST 100 TCK; +SDR 16 TDI (B5FF); +RUNTEST 100 TCK; +SDR 16 TDI (F7FD); +RUNTEST 100 TCK; +SDR 16 TDI (7FBF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (AEFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (DFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BBDF); +RUNTEST 100 TCK; +SDR 16 TDI (7FEA); +RUNTEST 100 TCK; +SDR 16 TDI (75FF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (6EF9); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FDFB); +RUNTEST 100 TCK; +SDR 16 TDI (AFEF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (777F); +RUNTEST 100 TCK; +SDR 16 TDI (FFBB); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7F6F); +RUNTEST 100 TCK; +SDR 16 TDI (7DEF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFD); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFD); +RUNTEST 100 TCK; +SDR 16 TDI (6FFF); +RUNTEST 100 TCK; +SDR 16 TDI (F5FB); RUNTEST 100 TCK; SDR 16 TDI (BF77); RUNTEST 100 TCK; +SDR 16 TDI (FFBB); +RUNTEST 100 TCK; +SDR 16 TDI (7FEC); +RUNTEST 100 TCK; SDR 16 TDI (FFFF); RUNTEST 100 TCK; +SDR 16 TDI (B7FF); +RUNTEST 100 TCK; +SDR 16 TDI (FBFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BBFF); +RUNTEST 100 TCK; SDR 16 TDI (7FFF); RUNTEST 100 TCK; SDR 16 TDI (FFFF); RUNTEST 100 TCK; -SDR 16 TDI (BFFF); +SDR 16 TDI (BFFC); RUNTEST 100 TCK; -SDR 16 TDI (FFFE); +SDR 16 TDI (8EDB); RUNTEST 100 TCK; -SDR 16 TDI (5FFD); +SDR 16 TDI (6FF9); +RUNTEST 100 TCK; +SDR 16 TDI (973B); +RUNTEST 100 TCK; +SDR 16 TDI (A7BF); +RUNTEST 100 TCK; +SDR 16 TDI (4BFD); +RUNTEST 100 TCK; +SDR 16 TDI (6FFE); +RUNTEST 100 TCK; +SDR 16 TDI (FDDD); +RUNTEST 100 TCK; +SDR 16 TDI (BAFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFEF); +RUNTEST 100 TCK; +SDR 16 TDI (7BAF); +RUNTEST 100 TCK; +SDR 16 TDI (BDFF); +RUNTEST 100 TCK; +SDR 16 TDI (BF33); +RUNTEST 100 TCK; +SDR 16 TDI (9F7F); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BBFF); +RUNTEST 100 TCK; +SDR 16 TDI (77FD); +RUNTEST 100 TCK; +SDR 16 TDI (7F77); +RUNTEST 100 TCK; +SDR 16 TDI (7EFF); +RUNTEST 100 TCK; +SDR 16 TDI (BEF3); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7AA5); +RUNTEST 100 TCK; +SDR 16 TDI (DBFB); +RUNTEST 100 TCK; +SDR 16 TDI (AFBF); +RUNTEST 100 TCK; +SDR 16 TDI (EB7D); +RUNTEST 100 TCK; +SDR 16 TDI (7EFF); +RUNTEST 100 TCK; +SDR 16 TDI (6FEF); +RUNTEST 100 TCK; +SDR 16 TDI (BBFE); +RUNTEST 100 TCK; +SDR 16 TDI (FFEA); +RUNTEST 100 TCK; +SDR 16 TDI (77FF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); RUNTEST 100 TCK; SDR 16 TDI (BFFF); RUNTEST 100 TCK; +SDR 16 TDI (FD26); +RUNTEST 100 TCK; +SDR 16 TDI (77FF); +RUNTEST 100 TCK; +SDR 16 TDI (E9C4); +RUNTEST 100 TCK; +SDR 16 TDI (B94E); +RUNTEST 100 TCK; +SDR 16 TDI (F7B2); +RUNTEST 100 TCK; +SDR 16 TDI (755B); +RUNTEST 100 TCK; +SDR 16 TDI (37BF); +RUNTEST 100 TCK; +SDR 16 TDI (BFEF); +RUNTEST 100 TCK; +SDR 16 TDI (D4DF); +RUNTEST 100 TCK; +SDR 16 TDI (6F5F); +RUNTEST 100 TCK; +SDR 16 TDI (DEDF); +RUNTEST 100 TCK; +SDR 16 TDI (BFDD); +RUNTEST 100 TCK; +SDR 16 TDI (78FF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (B66E); +RUNTEST 100 TCK; +SDR 16 TDI (260D); +RUNTEST 100 TCK; +SDR 16 TDI (7DD4); +RUNTEST 100 TCK; +SDR 16 TDI (01F6); +RUNTEST 100 TCK; +SDR 16 TDI (B2A0); +RUNTEST 100 TCK; +SDR 16 TDI (2AE3); +RUNTEST 100 TCK; +SDR 16 TDI (60A0); +RUNTEST 100 TCK; +SDR 16 TDI (75A7); +RUNTEST 100 TCK; +SDR 16 TDI (BE1F); +RUNTEST 100 TCK; +SDR 16 TDI (382E); +RUNTEST 100 TCK; +SDR 16 TDI (6F8F); +RUNTEST 100 TCK; +SDR 16 TDI (CC0F); +RUNTEST 100 TCK; +SDR 16 TDI (B19B); +RUNTEST 100 TCK; +SDR 16 TDI (E075); +RUNTEST 100 TCK; +SDR 16 TDI (6BFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; SDR 16 TDI (BFED); RUNTEST 100 TCK; -SDR 16 TDI (DFFD); +SDR 16 TDI (4623); +RUNTEST 100 TCK; +SDR 16 TDI (7EF4); +RUNTEST 100 TCK; +SDR 16 TDI (E941); +RUNTEST 100 TCK; +SDR 16 TDI (AB28); +RUNTEST 100 TCK; +SDR 16 TDI (2B75); +RUNTEST 100 TCK; +SDR 16 TDI (6660); +RUNTEST 100 TCK; +SDR 16 TDI (7BA7); +RUNTEST 100 TCK; +SDR 16 TDI (A19E); +RUNTEST 100 TCK; +SDR 16 TDI (802F); +RUNTEST 100 TCK; +SDR 16 TDI (700F); +RUNTEST 100 TCK; +SDR 16 TDI (CC0F); +RUNTEST 100 TCK; +SDR 16 TDI (A802); +RUNTEST 100 TCK; +SDR 16 TDI (E07F); +RUNTEST 100 TCK; +SDR 16 TDI (7DFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (B97E); +RUNTEST 100 TCK; +SDR 16 TDI (2FFF); +RUNTEST 100 TCK; +SDR 16 TDI (77ED); +RUNTEST 100 TCK; +SDR 16 TDI (802F); +RUNTEST 100 TCK; +SDR 16 TDI (B7FA); +RUNTEST 100 TCK; +SDR 16 TDI (77FF); +RUNTEST 100 TCK; +SDR 16 TDI (7FE3); +RUNTEST 100 TCK; +SDR 16 TDI (764A); +RUNTEST 100 TCK; +SDR 16 TDI (A1EF); +RUNTEST 100 TCK; +SDR 16 TDI (C0B1); +RUNTEST 100 TCK; +SDR 16 TDI (70CF); +RUNTEST 100 TCK; +SDR 16 TDI (D0CF); +RUNTEST 100 TCK; +SDR 16 TDI (B987); +RUNTEST 100 TCK; +SDR 16 TDI (8075); +RUNTEST 100 TCK; +SDR 16 TDI (6BFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BD7B); +RUNTEST 100 TCK; +SDR 16 TDI (CDA3); +RUNTEST 100 TCK; +SDR 16 TDI (7FE1); +RUNTEST 100 TCK; +SDR 16 TDI (6033); +RUNTEST 100 TCK; +SDR 16 TDI (A426); +RUNTEST 100 TCK; +SDR 16 TDI (53F0); +RUNTEST 100 TCK; +SDR 16 TDI (7201); +RUNTEST 100 TCK; +SDR 16 TDI (1B4A); +RUNTEST 100 TCK; +SDR 16 TDI (B81F); +RUNTEST 100 TCK; +SDR 16 TDI (8036); +RUNTEST 100 TCK; +SDR 16 TDI (630F); +RUNTEST 100 TCK; +SDR 16 TDI (C0CF); +RUNTEST 100 TCK; +SDR 16 TDI (B804); +RUNTEST 100 TCK; +SDR 16 TDI (817F); RUNTEST 100 TCK; SDR 16 TDI (7FFF); RUNTEST 100 TCK; SDR 16 TDI (FFFF); RUNTEST 100 TCK; -SDR 16 TDI (B6FF); +SDR 16 TDI (BEAF); +RUNTEST 100 TCK; +SDR 16 TDI (3FBA); +RUNTEST 100 TCK; +SDR 16 TDI (63E7); +RUNTEST 100 TCK; +SDR 16 TDI (626F); +RUNTEST 100 TCK; +SDR 16 TDI (BB3B); +RUNTEST 100 TCK; +SDR 16 TDI (39F3); +RUNTEST 100 TCK; +SDR 16 TDI (6662); +RUNTEST 100 TCK; +SDR 16 TDI (FEEE); +RUNTEST 100 TCK; +SDR 16 TDI (BDC7); +RUNTEST 100 TCK; +SDR 16 TDI (B9BB); +RUNTEST 100 TCK; +SDR 16 TDI (778C); +RUNTEST 100 TCK; +SDR 16 TDI (0CE7); +RUNTEST 100 TCK; +SDR 16 TDI (B9B0); +RUNTEST 100 TCK; +SDR 16 TDI (A0EB); +RUNTEST 100 TCK; +SDR 16 TDI (77FF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFBB); +RUNTEST 100 TCK; +SDR 16 TDI (7333); +RUNTEST 100 TCK; +SDR 16 TDI (6957); +RUNTEST 100 TCK; +SDR 16 TDI (7767); +RUNTEST 100 TCK; +SDR 16 TDI (B373); +RUNTEST 100 TCK; +SDR 16 TDI (70AB); +RUNTEST 100 TCK; +SDR 16 TDI (7776); +RUNTEST 100 TCK; +SDR 16 TDI (7C44); +RUNTEST 100 TCK; +SDR 16 TDI (A885); +RUNTEST 100 TCK; +SDR 16 TDI (9C91); +RUNTEST 100 TCK; +SDR 16 TDI (62DD); +RUNTEST 100 TCK; +SDR 16 TDI (CDCA); +RUNTEST 100 TCK; +SDR 16 TDI (B58D); +RUNTEST 100 TCK; +SDR 16 TDI (9DFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BDFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (77CE); +RUNTEST 100 TCK; +SDR 16 TDI (EEFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFBF); +RUNTEST 100 TCK; +SDR 16 TDI (BFE7); +RUNTEST 100 TCK; +SDR 16 TDI (6EFF); +RUNTEST 100 TCK; +SDR 16 TDI (F777); +RUNTEST 100 TCK; +SDR 16 TDI (AEFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FF7); +RUNTEST 100 TCK; +SDR 16 TDI (6EFF); +RUNTEST 100 TCK; +SDR 16 TDI (6EFF); +RUNTEST 100 TCK; +SDR 16 TDI (B3F7); +RUNTEST 100 TCK; +SDR 16 TDI (F7FF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (F7EF); +RUNTEST 100 TCK; +SDR 16 TDI (6FF7); +RUNTEST 100 TCK; +SDR 16 TDI (FDF7); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (D7FF); +RUNTEST 100 TCK; +SDR 16 TDI (76FE); +RUNTEST 100 TCK; +SDR 16 TDI (BFFD); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (DFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFE); +RUNTEST 100 TCK; +SDR 16 TDI (BBFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BE75); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (B73E); +RUNTEST 100 TCK; +SDR 16 TDI (BA7B); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FF7); +RUNTEST 100 TCK; +SDR 16 TDI (FDF7); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FDFD); +RUNTEST 100 TCK; +SDR 16 TDI (7B7B); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BD7F); +RUNTEST 100 TCK; +SDR 16 TDI (FFFD); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (AFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFB5); +RUNTEST 100 TCK; +SDR 16 TDI (77F7); +RUNTEST 100 TCK; +SDR 16 TDI (FBFF); +RUNTEST 100 TCK; +SDR 16 TDI (BF7F); +RUNTEST 100 TCK; +SDR 16 TDI (D7FF); +RUNTEST 100 TCK; +SDR 16 TDI (77FF); +RUNTEST 100 TCK; +SDR 16 TDI (DFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (DFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7BFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BD7F); +RUNTEST 100 TCK; +SDR 16 TDI (FDFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (ABBB); +RUNTEST 100 TCK; +SDR 16 TDI (FBEF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (F6EE); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7F77); +RUNTEST 100 TCK; +SDR 16 TDI (7EF6); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FDFD); +RUNTEST 100 TCK; +SDR 16 TDI (7FBF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFE); +RUNTEST 100 TCK; +SDR 16 TDI (DFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7DFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FDEF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFE); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (AFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (6DBD); +RUNTEST 100 TCK; +SDR 16 TDI (7FDF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FB73); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFEE); RUNTEST 100 TCK; SDR 16 TDI (FFFF); RUNTEST 100 TCK; SDR 16 TDI (7FFF); RUNTEST 100 TCK; -SDR 16 TDI (D95F); +SDR 16 TDI (FFFF); RUNTEST 100 TCK; -SDR 16 TDI (BDCF); +SDR 16 TDI (BFFD); RUNTEST 100 TCK; SDR 16 TDI (FFFF); RUNTEST 100 TCK; -SDR 16 TDI (5FFF); +SDR 16 TDI (7FEF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFD); +RUNTEST 100 TCK; +SDR 16 TDI (B7EF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7F7F); +RUNTEST 100 TCK; +SDR 16 TDI (EFFF); +RUNTEST 100 TCK; +SDR 16 TDI (B7FF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FBD); +RUNTEST 100 TCK; +SDR 16 TDI (EFBF); +RUNTEST 100 TCK; +SDR 16 TDI (BFDF); +RUNTEST 100 TCK; +SDR 16 TDI (FF7F); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFD); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FF7); +RUNTEST 100 TCK; +SDR 16 TDI (EFFF); +RUNTEST 100 TCK; +SDR 16 TDI (B7FA); +RUNTEST 100 TCK; +SDR 16 TDI (6FFD); +RUNTEST 100 TCK; +SDR 16 TDI (7DFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FBE); +RUNTEST 100 TCK; +SDR 16 TDI (BF7F); +RUNTEST 100 TCK; +SDR 16 TDI (FDFF); +RUNTEST 100 TCK; +SDR 16 TDI (7F7B); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FB75); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); RUNTEST 100 TCK; SDR 16 TDI (FFFF); RUNTEST 100 TCK; @@ -6211,10 +4131,2090 @@ SDR 16 TDI (FDDF); RUNTEST 100 TCK; SDR 16 TDI (7FFF); RUNTEST 100 TCK; +SDR 16 TDI (7FFB); +RUNTEST 100 TCK; +SDR 16 TDI (AFDF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (6EDB); +RUNTEST 100 TCK; +SDR 16 TDI (FFEF); +RUNTEST 100 TCK; +SDR 16 TDI (B7FF); +RUNTEST 100 TCK; +SDR 16 TDI (FEF3); +RUNTEST 100 TCK; +SDR 16 TDI (7FFD); +RUNTEST 100 TCK; +SDR 16 TDI (DF7F); +RUNTEST 100 TCK; +SDR 16 TDI (BFD7); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BEDF); +RUNTEST 100 TCK; +SDR 16 TDI (5FFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FDF7); +RUNTEST 100 TCK; +SDR 16 TDI (BF7F); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7DFF); +RUNTEST 100 TCK; +SDR 16 TDI (E775); +RUNTEST 100 TCK; +SDR 16 TDI (ADFF); +RUNTEST 100 TCK; +SDR 16 TDI (FBFF); +RUNTEST 100 TCK; +SDR 16 TDI (75FF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFDF); +RUNTEST 100 TCK; +SDR 16 TDI (7FEE); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (B9DE); +RUNTEST 100 TCK; +SDR 16 TDI (7FF7); +RUNTEST 100 TCK; +SDR 16 TDI (77FF); +RUNTEST 100 TCK; +SDR 16 TDI (DDEF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BF7B); +RUNTEST 100 TCK; +SDR 16 TDI (6FBF); +RUNTEST 100 TCK; +SDR 16 TDI (FBFF); +RUNTEST 100 TCK; +SDR 16 TDI (BBFF); +RUNTEST 100 TCK; +SDR 16 TDI (FAFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BDFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFDB); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (EFBF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (75FB); +RUNTEST 100 TCK; +SDR 16 TDI (F77F); +RUNTEST 100 TCK; +SDR 16 TDI (AFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FDBD); +RUNTEST 100 TCK; +SDR 16 TDI (7FEB); +RUNTEST 100 TCK; +SDR 16 TDI (EFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFB); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFEF); +RUNTEST 100 TCK; +SDR 16 TDI (6FFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (7BF7); +RUNTEST 100 TCK; +SDR 16 TDI (B66E); +RUNTEST 100 TCK; +SDR 16 TDI (BBFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (BDE5); +RUNTEST 100 TCK; +SDR 16 TDI (BBDF); +RUNTEST 100 TCK; +SDR 16 TDI (FF7E); +RUNTEST 100 TCK; +SDR 16 TDI (767F); +RUNTEST 100 TCK; +SDR 16 TDI (FBFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FAFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (A75F); +RUNTEST 100 TCK; +SDR 16 TDI (FF7B); +RUNTEST 100 TCK; +SDR 16 TDI (6BFF); +RUNTEST 100 TCK; +SDR 16 TDI (D7DF); +RUNTEST 100 TCK; +SDR 16 TDI (BFBB); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7F77); +RUNTEST 100 TCK; +SDR 16 TDI (7EF9); +RUNTEST 100 TCK; +SDR 16 TDI (ADFF); +RUNTEST 100 TCK; +SDR 16 TDI (FBCB); +RUNTEST 100 TCK; +SDR 16 TDI (7FF9); +RUNTEST 100 TCK; +SDR 16 TDI (FDDF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFD); +RUNTEST 100 TCK; +SDR 16 TDI (FFF5); +RUNTEST 100 TCK; +SDR 16 TDI (6BFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (AEFF); +RUNTEST 100 TCK; +SDR 16 TDI (7EEF); +RUNTEST 100 TCK; +SDR 16 TDI (7FF7); +RUNTEST 100 TCK; +SDR 16 TDI (FBF6); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (E7FF); +RUNTEST 100 TCK; +SDR 16 TDI (6BFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFDF); +RUNTEST 100 TCK; +SDR 16 TDI (DF7F); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFBF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (DFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7DFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (A65F); +RUNTEST 100 TCK; +SDR 16 TDI (FFFD); +RUNTEST 100 TCK; +SDR 16 TDI (7FFE); +RUNTEST 100 TCK; +SDR 16 TDI (FF7F); +RUNTEST 100 TCK; +SDR 16 TDI (A7FF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFB); +RUNTEST 100 TCK; +SDR 16 TDI (7FBF); +RUNTEST 100 TCK; +SDR 16 TDI (FFE7); +RUNTEST 100 TCK; +SDR 16 TDI (BEFE); +RUNTEST 100 TCK; +SDR 16 TDI (FEFF); +RUNTEST 100 TCK; +SDR 16 TDI (77DB); +RUNTEST 100 TCK; +SDR 16 TDI (DB7F); +RUNTEST 100 TCK; +SDR 16 TDI (BDDF); +RUNTEST 100 TCK; +SDR 16 TDI (FBF5); +RUNTEST 100 TCK; +SDR 16 TDI (6BFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (AFFE); +RUNTEST 100 TCK; +SDR 16 TDI (FEBF); +RUNTEST 100 TCK; +SDR 16 TDI (6FF3); +RUNTEST 100 TCK; +SDR 16 TDI (2B3F); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFD); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FBBF); +RUNTEST 100 TCK; +SDR 16 TDI (AFFF); +RUNTEST 100 TCK; +SDR 16 TDI (F7F7); +RUNTEST 100 TCK; +SDR 16 TDI (7F7F); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (BD77); +RUNTEST 100 TCK; +SDR 16 TDI (FFEA); +RUNTEST 100 TCK; +SDR 16 TDI (75FF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BBFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FEF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFD); +RUNTEST 100 TCK; +SDR 16 TDI (9EEF); +RUNTEST 100 TCK; +SDR 16 TDI (FEFB); +RUNTEST 100 TCK; +SDR 16 TDI (7DFD); +RUNTEST 100 TCK; +SDR 16 TDI (FFFD); +RUNTEST 100 TCK; +SDR 16 TDI (BDFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFD); +RUNTEST 100 TCK; +SDR 16 TDI (6FFE); +RUNTEST 100 TCK; +SDR 16 TDI (EFEF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFB); +RUNTEST 100 TCK; +SDR 16 TDI (B37F); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (9FFD); +RUNTEST 100 TCK; +SDR 16 TDI (FBFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFD); +RUNTEST 100 TCK; +SDR 16 TDI (FFEB); +RUNTEST 100 TCK; +SDR 16 TDI (BFFE); +RUNTEST 100 TCK; +SDR 16 TDI (FFFE); +RUNTEST 100 TCK; +SDR 16 TDI (6FFF); +RUNTEST 100 TCK; +SDR 16 TDI (F9DF); +RUNTEST 100 TCK; +SDR 16 TDI (BFBF); +RUNTEST 100 TCK; +SDR 16 TDI (EDDF); +RUNTEST 100 TCK; +SDR 16 TDI (6A9F); +RUNTEST 100 TCK; +SDR 16 TDI (FBFF); +RUNTEST 100 TCK; +SDR 16 TDI (BEEE); +RUNTEST 100 TCK; +SDR 16 TDI (F77F); +RUNTEST 100 TCK; +SDR 16 TDI (5FFF); +RUNTEST 100 TCK; SDR 16 TDI (FFFF); RUNTEST 100 TCK; SDR 16 TDI (9FFF); RUNTEST 100 TCK; +SDR 16 TDI (FD2F); +RUNTEST 100 TCK; +SDR 16 TDI (4FFB); +RUNTEST 100 TCK; +SDR 16 TDI (C5CD); +RUNTEST 100 TCK; +SDR 16 TDI (BF7F); +RUNTEST 100 TCK; +SDR 16 TDI (D6F7); +RUNTEST 100 TCK; +SDR 16 TDI (773F); +RUNTEST 100 TCK; +SDR 16 TDI (FBE1); +RUNTEST 100 TCK; +SDR 16 TDI (9DDF); +RUNTEST 100 TCK; +SDR 16 TDI (97EB); +RUNTEST 100 TCK; +SDR 16 TDI (675D); +RUNTEST 100 TCK; +SDR 16 TDI (95CF); +RUNTEST 100 TCK; +SDR 16 TDI (BE4D); +RUNTEST 100 TCK; +SDR 16 TDI (5D7F); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BDFF); +RUNTEST 100 TCK; +SDR 16 TDI (BAD6); +RUNTEST 100 TCK; +SDR 16 TDI (7BFD); +RUNTEST 100 TCK; +SDR 16 TDI (BB37); +RUNTEST 100 TCK; +SDR 16 TDI (A7E5); +RUNTEST 100 TCK; +SDR 16 TDI (FFFE); +RUNTEST 100 TCK; +SDR 16 TDI (4DFF); +RUNTEST 100 TCK; +SDR 16 TDI (55DE); +RUNTEST 100 TCK; +SDR 16 TDI (8FFE); +RUNTEST 100 TCK; +SDR 16 TDI (EDF5); +RUNTEST 100 TCK; +SDR 16 TDI (5EA7); +RUNTEST 100 TCK; +SDR 16 TDI (7BFF); +RUNTEST 100 TCK; +SDR 16 TDI (B9F7); +RUNTEST 100 TCK; +SDR 16 TDI (E6FB); +RUNTEST 100 TCK; +SDR 16 TDI (57FF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (9FFC); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (77E6); +RUNTEST 100 TCK; +SDR 16 TDI (7EFA); +RUNTEST 100 TCK; +SDR 16 TDI (BEFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FF9); +RUNTEST 100 TCK; +SDR 16 TDI (7BF3); +RUNTEST 100 TCK; +SDR 16 TDI (FEBF); +RUNTEST 100 TCK; +SDR 16 TDI (B33F); +RUNTEST 100 TCK; +SDR 16 TDI (FA1E); +RUNTEST 100 TCK; +SDR 16 TDI (5BFA); +RUNTEST 100 TCK; +SDR 16 TDI (EF3F); +RUNTEST 100 TCK; +SDR 16 TDI (BFFB); +RUNTEST 100 TCK; +SDR 16 TDI (BBFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (8B5E); +RUNTEST 100 TCK; +SDR 16 TDI (702F); +RUNTEST 100 TCK; +SDR 16 TDI (47DF); +RUNTEST 100 TCK; +SDR 16 TDI (FF12); +RUNTEST 100 TCK; +SDR 16 TDI (B69F); +RUNTEST 100 TCK; +SDR 16 TDI (C3E0); +RUNTEST 100 TCK; +SDR 16 TDI (60BD); +RUNTEST 100 TCK; +SDR 16 TDI (FF2C); +RUNTEST 100 TCK; +SDR 16 TDI (8A5F); +RUNTEST 100 TCK; +SDR 16 TDI (1AA1); +RUNTEST 100 TCK; +SDR 16 TDI (7CC2); +RUNTEST 100 TCK; +SDR 16 TDI (FA2F); +RUNTEST 100 TCK; +SDR 16 TDI (B000); +RUNTEST 100 TCK; +SDR 16 TDI (60F4); +RUNTEST 100 TCK; +SDR 16 TDI (7BFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (AFFC); +RUNTEST 100 TCK; +SDR 16 TDI (7203); +RUNTEST 100 TCK; +SDR 16 TDI (47BD); +RUNTEST 100 TCK; +SDR 16 TDI (FCB1); +RUNTEST 100 TCK; +SDR 16 TDI (AE9C); +RUNTEST 100 TCK; +SDR 16 TDI (33D0); +RUNTEST 100 TCK; +SDR 16 TDI (60BC); +RUNTEST 100 TCK; +SDR 16 TDI (1028); +RUNTEST 100 TCK; +SDR 16 TDI (805E); +RUNTEST 100 TCK; +SDR 16 TDI (9A81); +RUNTEST 100 TCK; +SDR 16 TDI (50C3); +RUNTEST 100 TCK; +SDR 16 TDI (0B7F); +RUNTEST 100 TCK; +SDR 16 TDI (AD58); +RUNTEST 100 TCK; +SDR 16 TDI (70EE); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (965F); +RUNTEST 100 TCK; +SDR 16 TDI (B3EF); +RUNTEST 100 TCK; +SDR 16 TDI (6BFE); +RUNTEST 100 TCK; +SDR 16 TDI (9E0E); +RUNTEST 100 TCK; +SDR 16 TDI (B928); +RUNTEST 100 TCK; +SDR 16 TDI (3FF4); +RUNTEST 100 TCK; +SDR 16 TDI (62CA); +RUNTEST 100 TCK; +SDR 16 TDI (11D4); +RUNTEST 100 TCK; +SDR 16 TDI (BBBF); +RUNTEST 100 TCK; +SDR 16 TDI (CE40); +RUNTEST 100 TCK; +SDR 16 TDI (6F93); +RUNTEST 100 TCK; +SDR 16 TDI (F00F); +RUNTEST 100 TCK; +SDR 16 TDI (9E01); +RUNTEST 100 TCK; +SDR 16 TDI (98FD); +RUNTEST 100 TCK; +SDR 16 TDI (7BFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFF9); +RUNTEST 100 TCK; +SDR 16 TDI (B3F3); +RUNTEST 100 TCK; +SDR 16 TDI (6FFE); +RUNTEST 100 TCK; +SDR 16 TDI (132D); +RUNTEST 100 TCK; +SDR 16 TDI (AD2B); +RUNTEST 100 TCK; +SDR 16 TDI (03F0); +RUNTEST 100 TCK; +SDR 16 TDI (60CA); +RUNTEST 100 TCK; +SDR 16 TDI (71D0); +RUNTEST 100 TCK; +SDR 16 TDI (9BBF); +RUNTEST 100 TCK; +SDR 16 TDI (987C); +RUNTEST 100 TCK; +SDR 16 TDI (7303); +RUNTEST 100 TCK; +SDR 16 TDI (D00F); +RUNTEST 100 TCK; +SDR 16 TDI (BFF8); +RUNTEST 100 TCK; +SDR 16 TDI (7CFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (3B37); +RUNTEST 100 TCK; +SDR 16 TDI (61E6); +RUNTEST 100 TCK; +SDR 16 TDI (6267); +RUNTEST 100 TCK; +SDR 16 TDI (BBBB); +RUNTEST 100 TCK; +SDR 16 TDI (B8F3); +RUNTEST 100 TCK; +SDR 16 TDI (42EE); +RUNTEST 100 TCK; +SDR 16 TDI (FCEE); +RUNTEST 100 TCK; +SDR 16 TDI (99CF); +RUNTEST 100 TCK; +SDR 16 TDI (BB99); +RUNTEST 100 TCK; +SDR 16 TDI (57CE); +RUNTEST 100 TCK; +SDR 16 TDI (CDE7); +RUNTEST 100 TCK; +SDR 16 TDI (B9F9); +RUNTEST 100 TCK; +SDR 16 TDI (99C8); +RUNTEST 100 TCK; +SDR 16 TDI (77FF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (9FFE); +RUNTEST 100 TCK; +SDR 16 TDI (7277); +RUNTEST 100 TCK; +SDR 16 TDI (6957); +RUNTEST 100 TCK; +SDR 16 TDI (3737); +RUNTEST 100 TCK; +SDR 16 TDI (B111); +RUNTEST 100 TCK; +SDR 16 TDI (10B9); +RUNTEST 100 TCK; +SDR 16 TDI (7644); +RUNTEST 100 TCK; +SDR 16 TDI (5DCD); +RUNTEST 100 TCK; +SDR 16 TDI (BB85); +RUNTEST 100 TCK; +SDR 16 TDI (59DD); +RUNTEST 100 TCK; +SDR 16 TDI (73DC); +RUNTEST 100 TCK; +SDR 16 TDI (DDC2); +RUNTEST 100 TCK; +SDR 16 TDI (959D); +RUNTEST 100 TCK; +SDR 16 TDI (DDFD); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFB); +RUNTEST 100 TCK; +SDR 16 TDI (DFFB); +RUNTEST 100 TCK; +SDR 16 TDI (77CE); +RUNTEST 100 TCK; +SDR 16 TDI (EFEE); +RUNTEST 100 TCK; +SDR 16 TDI (BDDD); +RUNTEST 100 TCK; +SDR 16 TDI (DFE7); +RUNTEST 100 TCK; +SDR 16 TDI (7FDD); +RUNTEST 100 TCK; +SDR 16 TDI (DE7F); +RUNTEST 100 TCK; +SDR 16 TDI (9CEF); +RUNTEST 100 TCK; +SDR 16 TDI (FF3B); +RUNTEST 100 TCK; +SDR 16 TDI (7EEF); +RUNTEST 100 TCK; +SDR 16 TDI (FEFF); +RUNTEST 100 TCK; +SDR 16 TDI (B3FF); +RUNTEST 100 TCK; +SDR 16 TDI (BBDF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (EFDF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (3BDF); +RUNTEST 100 TCK; +SDR 16 TDI (99EE); +RUNTEST 100 TCK; +SDR 16 TDI (FFFB); +RUNTEST 100 TCK; +SDR 16 TDI (7DFF); +RUNTEST 100 TCK; +SDR 16 TDI (FD7F); +RUNTEST 100 TCK; +SDR 16 TDI (BBFF); +RUNTEST 100 TCK; +SDR 16 TDI (DFDF); +RUNTEST 100 TCK; +SDR 16 TDI (6FD6); +RUNTEST 100 TCK; +SDR 16 TDI (9FFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFE); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (9FFF); +RUNTEST 100 TCK; +SDR 16 TDI (7EF6); +RUNTEST 100 TCK; +SDR 16 TDI (6FFF); +RUNTEST 100 TCK; +SDR 16 TDI (F7F5); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (5FFD); +RUNTEST 100 TCK; +SDR 16 TDI (7FF7); +RUNTEST 100 TCK; +SDR 16 TDI (FFED); +RUNTEST 100 TCK; +SDR 16 TDI (BF3F); +RUNTEST 100 TCK; +SDR 16 TDI (FDFD); +RUNTEST 100 TCK; +SDR 16 TDI (5FBF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (9FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (6FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (8FFF); +RUNTEST 100 TCK; +SDR 16 TDI (DFE7); +RUNTEST 100 TCK; +SDR 16 TDI (5FFE); +RUNTEST 100 TCK; +SDR 16 TDI (FFEF); +RUNTEST 100 TCK; +SDR 16 TDI (B6ED); +RUNTEST 100 TCK; +SDR 16 TDI (7FFB); +RUNTEST 100 TCK; +SDR 16 TDI (7BFF); +RUNTEST 100 TCK; +SDR 16 TDI (FEBD); +RUNTEST 100 TCK; +SDR 16 TDI (9FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFD); +RUNTEST 100 TCK; +SDR 16 TDI (7FE6); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (AFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (6FFF); +RUNTEST 100 TCK; +SDR 16 TDI (D5BD); +RUNTEST 100 TCK; +SDR 16 TDI (9FFF); +RUNTEST 100 TCK; +SDR 16 TDI (DFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FEF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BDBF); +RUNTEST 100 TCK; +SDR 16 TDI (DDDE); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (6FFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFE); +RUNTEST 100 TCK; +SDR 16 TDI (FFBF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (9FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (5FFE); +RUNTEST 100 TCK; +SDR 16 TDI (DFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BEEF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFE); +RUNTEST 100 TCK; +SDR 16 TDI (7DFF); +RUNTEST 100 TCK; +SDR 16 TDI (DDF7); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FEFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FF7); +RUNTEST 100 TCK; +SDR 16 TDI (9F7F); +RUNTEST 100 TCK; +SDR 16 TDI (9FFE); +RUNTEST 100 TCK; +SDR 16 TDI (FBFB); +RUNTEST 100 TCK; +SDR 16 TDI (5FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFD); +RUNTEST 100 TCK; +SDR 16 TDI (6FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFE); +RUNTEST 100 TCK; +SDR 16 TDI (BBFD); +RUNTEST 100 TCK; +SDR 16 TDI (EFFF); +RUNTEST 100 TCK; +SDR 16 TDI (5FFB); +RUNTEST 100 TCK; +SDR 16 TDI (EFBF); +RUNTEST 100 TCK; +SDR 16 TDI (9F7F); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (9BFD); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (5FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FEEF); +RUNTEST 100 TCK; +SDR 16 TDI (5FFF); +RUNTEST 100 TCK; +SDR 16 TDI (4FFF); +RUNTEST 100 TCK; +SDR 16 TDI (9FFF); +RUNTEST 100 TCK; +SDR 16 TDI (DFFE); +RUNTEST 100 TCK; +SDR 16 TDI (6FFE); +RUNTEST 100 TCK; +SDR 16 TDI (FF7E); +RUNTEST 100 TCK; +SDR 16 TDI (9FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FB7F); +RUNTEST 100 TCK; +SDR 16 TDI (57F7); +RUNTEST 100 TCK; +SDR 16 TDI (FF6F); +RUNTEST 100 TCK; +SDR 16 TDI (BDFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFF7); +RUNTEST 100 TCK; +SDR 16 TDI (5BFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (9FFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFE); +RUNTEST 100 TCK; +SDR 16 TDI (6FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (89DE); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (5BFD); +RUNTEST 100 TCK; +SDR 16 TDI (BDF7); +RUNTEST 100 TCK; +SDR 16 TDI (BF7F); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (5FFF); +RUNTEST 100 TCK; +SDR 16 TDI (5FFF); +RUNTEST 100 TCK; +SDR 16 TDI (9FFB); +RUNTEST 100 TCK; +SDR 16 TDI (7BFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (9EF7); +RUNTEST 100 TCK; +SDR 16 TDI (FFDF); +RUNTEST 100 TCK; +SDR 16 TDI (5FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FDFE); +RUNTEST 100 TCK; +SDR 16 TDI (BDFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (5BFE); +RUNTEST 100 TCK; +SDR 16 TDI (EDDF); +RUNTEST 100 TCK; +SDR 16 TDI (9DFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7E7F); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (9FBF); +RUNTEST 100 TCK; +SDR 16 TDI (F7FF); +RUNTEST 100 TCK; +SDR 16 TDI (5FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (EEFF); +RUNTEST 100 TCK; +SDR 16 TDI (5FEF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFB); +RUNTEST 100 TCK; +SDR 16 TDI (9FBE); +RUNTEST 100 TCK; +SDR 16 TDI (FFF7); +RUNTEST 100 TCK; +SDR 16 TDI (7FBF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (9FFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (5BDB); +RUNTEST 100 TCK; +SDR 16 TDI (EDFF); +RUNTEST 100 TCK; +SDR 16 TDI (BBFF); +RUNTEST 100 TCK; +SDR 16 TDI (DFFF); +RUNTEST 100 TCK; +SDR 16 TDI (5FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (9FF7); +RUNTEST 100 TCK; +SDR 16 TDI (DFDF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (9BFD); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (5FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BBFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7E5E); +RUNTEST 100 TCK; +SDR 16 TDI (BBFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFE); +RUNTEST 100 TCK; +SDR 16 TDI (F7FF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (9EFF); +RUNTEST 100 TCK; +SDR 16 TDI (FEFF); +RUNTEST 100 TCK; +SDR 16 TDI (57FF); +RUNTEST 100 TCK; +SDR 16 TDI (DBFD); +RUNTEST 100 TCK; +SDR 16 TDI (ADBF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7BDE); +RUNTEST 100 TCK; +SDR 16 TDI (FDEF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7BFB); +RUNTEST 100 TCK; +SDR 16 TDI (DEFF); +RUNTEST 100 TCK; +SDR 16 TDI (9FDF); +RUNTEST 100 TCK; +SDR 16 TDI (DFFF); +RUNTEST 100 TCK; +SDR 16 TDI (5FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (A75E); +RUNTEST 100 TCK; +SDR 16 TDI (F7FF); +RUNTEST 100 TCK; +SDR 16 TDI (6DFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFEE); +RUNTEST 100 TCK; +SDR 16 TDI (BDFF); +RUNTEST 100 TCK; +SDR 16 TDI (B7FD); +RUNTEST 100 TCK; +SDR 16 TDI (7F76); +RUNTEST 100 TCK; +SDR 16 TDI (FFFD); +RUNTEST 100 TCK; +SDR 16 TDI (9BFE); +RUNTEST 100 TCK; +SDR 16 TDI (DFDD); +RUNTEST 100 TCK; +SDR 16 TDI (5B75); +RUNTEST 100 TCK; +SDR 16 TDI (EEF7); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFD); +RUNTEST 100 TCK; +SDR 16 TDI (7BFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (ADFF); +RUNTEST 100 TCK; +SDR 16 TDI (FF76); +RUNTEST 100 TCK; +SDR 16 TDI (7FFE); +RUNTEST 100 TCK; +SDR 16 TDI (FFBB); +RUNTEST 100 TCK; +SDR 16 TDI (9FF7); +RUNTEST 100 TCK; +SDR 16 TDI (FFF7); +RUNTEST 100 TCK; +SDR 16 TDI (5FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFD7); +RUNTEST 100 TCK; +SDR 16 TDI (AEFF); +RUNTEST 100 TCK; +SDR 16 TDI (F5FF); +RUNTEST 100 TCK; +SDR 16 TDI (6FFF); +RUNTEST 100 TCK; +SDR 16 TDI (B7EF); +RUNTEST 100 TCK; +SDR 16 TDI (BEDD); +RUNTEST 100 TCK; +SDR 16 TDI (BBFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (8B5E); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (5FFF); +RUNTEST 100 TCK; +SDR 16 TDI (F37F); +RUNTEST 100 TCK; +SDR 16 TDI (B77F); +RUNTEST 100 TCK; +SDR 16 TDI (DFFF); +RUNTEST 100 TCK; +SDR 16 TDI (77DD); +RUNTEST 100 TCK; +SDR 16 TDI (B9F7); +RUNTEST 100 TCK; +SDR 16 TDI (AFBF); +RUNTEST 100 TCK; +SDR 16 TDI (FF77); +RUNTEST 100 TCK; +SDR 16 TDI (6FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FBFF); +RUNTEST 100 TCK; +SDR 16 TDI (9D7F); +RUNTEST 100 TCK; +SDR 16 TDI (F7FD); +RUNTEST 100 TCK; +SDR 16 TDI (5BFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (ADFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFA); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (AEEF); +RUNTEST 100 TCK; +SDR 16 TDI (BBFF); +RUNTEST 100 TCK; +SDR 16 TDI (7F77); +RUNTEST 100 TCK; +SDR 16 TDI (FFEE); +RUNTEST 100 TCK; +SDR 16 TDI (9DFF); +RUNTEST 100 TCK; +SDR 16 TDI (EBFB); +RUNTEST 100 TCK; +SDR 16 TDI (5DFF); +RUNTEST 100 TCK; +SDR 16 TDI (BF7F); +RUNTEST 100 TCK; +SDR 16 TDI (BFF4); +RUNTEST 100 TCK; +SDR 16 TDI (BFFB); +RUNTEST 100 TCK; +SDR 16 TDI (77FF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (EEFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (DFFF); +RUNTEST 100 TCK; +SDR 16 TDI (9FFD); +RUNTEST 100 TCK; +SDR 16 TDI (FFFD); +RUNTEST 100 TCK; +SDR 16 TDI (5DFF); +RUNTEST 100 TCK; +SDR 16 TDI (FEFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFBF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FB7F); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (9FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFEF); +RUNTEST 100 TCK; +SDR 16 TDI (5FEF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (9BAB); +RUNTEST 100 TCK; +SDR 16 TDI (EFFB); +RUNTEST 100 TCK; +SDR 16 TDI (57DD); +RUNTEST 100 TCK; +SDR 16 TDI (DFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FEEF); +RUNTEST 100 TCK; +SDR 16 TDI (7EDF); +RUNTEST 100 TCK; +SDR 16 TDI (DD6F); +RUNTEST 100 TCK; +SDR 16 TDI (BDB7); +RUNTEST 100 TCK; +SDR 16 TDI (777F); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (9FFD); +RUNTEST 100 TCK; +SDR 16 TDI (7F7D); +RUNTEST 100 TCK; +SDR 16 TDI (4FFF); +RUNTEST 100 TCK; +SDR 16 TDI (BBFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFCA); +RUNTEST 100 TCK; +SDR 16 TDI (DBFB); +RUNTEST 100 TCK; +SDR 16 TDI (7BBB); +RUNTEST 100 TCK; +SDR 16 TDI (F8D5); +RUNTEST 100 TCK; +SDR 16 TDI (AABE); +RUNTEST 100 TCK; +SDR 16 TDI (E465); +RUNTEST 100 TCK; +SDR 16 TDI (69FD); +RUNTEST 100 TCK; +SDR 16 TDI (DFCF); +RUNTEST 100 TCK; +SDR 16 TDI (9FFA); +RUNTEST 100 TCK; +SDR 16 TDI (FFFE); +RUNTEST 100 TCK; +SDR 16 TDI (57FF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFE); +RUNTEST 100 TCK; +SDR 16 TDI (F6D7); +RUNTEST 100 TCK; +SDR 16 TDI (7FEA); +RUNTEST 100 TCK; +SDR 16 TDI (77F5); +RUNTEST 100 TCK; +SDR 16 TDI (BFF7); +RUNTEST 100 TCK; +SDR 16 TDI (AFF6); +RUNTEST 100 TCK; +SDR 16 TDI (7667); +RUNTEST 100 TCK; +SDR 16 TDI (1FFF); +RUNTEST 100 TCK; +SDR 16 TDI (9FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (5EEF); +RUNTEST 100 TCK; +SDR 16 TDI (A43F); +RUNTEST 100 TCK; +SDR 16 TDI (BA35); +RUNTEST 100 TCK; +SDR 16 TDI (717F); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (EFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7BFF); +RUNTEST 100 TCK; +SDR 16 TDI (FF5E); +RUNTEST 100 TCK; +SDR 16 TDI (803F); +RUNTEST 100 TCK; +SDR 16 TDI (77FD); +RUNTEST 100 TCK; +SDR 16 TDI (4FDD); +RUNTEST 100 TCK; +SDR 16 TDI (FFEA); +RUNTEST 100 TCK; +SDR 16 TDI (B5FF); +RUNTEST 100 TCK; +SDR 16 TDI (DB9A); +RUNTEST 100 TCK; +SDR 16 TDI (7F77); +RUNTEST 100 TCK; +SDR 16 TDI (7BF7); +RUNTEST 100 TCK; +SDR 16 TDI (BDCF); +RUNTEST 100 TCK; +SDR 16 TDI (8EFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (8A5D); +RUNTEST 100 TCK; +SDR 16 TDI (69FC); +RUNTEST 100 TCK; +SDR 16 TDI (47D6); +RUNTEST 100 TCK; +SDR 16 TDI (0B9F); +RUNTEST 100 TCK; +SDR 16 TDI (B780); +RUNTEST 100 TCK; +SDR 16 TDI (33EA); +RUNTEST 100 TCK; +SDR 16 TDI (6420); +RUNTEST 100 TCK; +SDR 16 TDI (1CCA); +RUNTEST 100 TCK; +SDR 16 TDI (B21F); +RUNTEST 100 TCK; +SDR 16 TDI (2147); +RUNTEST 100 TCK; +SDR 16 TDI (6430); +RUNTEST 100 TCK; +SDR 16 TDI (EECF); +RUNTEST 100 TCK; +SDR 16 TDI (939A); +RUNTEST 100 TCK; +SDR 16 TDI (A9EB); +RUNTEST 100 TCK; +SDR 16 TDI (4BFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (AEFE); +RUNTEST 100 TCK; +SDR 16 TDI (E9C3); +RUNTEST 100 TCK; +SDR 16 TDI (67B6); +RUNTEST 100 TCK; +SDR 16 TDI (0BE1); +RUNTEST 100 TCK; +SDR 16 TDI (BCF4); +RUNTEST 100 TCK; +SDR 16 TDI (03D0); +RUNTEST 100 TCK; +SDR 16 TDI (6400); +RUNTEST 100 TCK; +SDR 16 TDI (1CC4); +RUNTEST 100 TCK; +SDR 16 TDI (85FE); +RUNTEST 100 TCK; +SDR 16 TDI (A006); +RUNTEST 100 TCK; +SDR 16 TDI (500F); +RUNTEST 100 TCK; +SDR 16 TDI (22AF); +RUNTEST 100 TCK; +SDR 16 TDI (AA29); +RUNTEST 100 TCK; +SDR 16 TDI (9AEB); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BB5D); +RUNTEST 100 TCK; +SDR 16 TDI (9283); +RUNTEST 100 TCK; +SDR 16 TDI (7BEE); +RUNTEST 100 TCK; +SDR 16 TDI (4C61); +RUNTEST 100 TCK; +SDR 16 TDI (9B7D); +RUNTEST 100 TCK; +SDR 16 TDI (03FC); +RUNTEST 100 TCK; +SDR 16 TDI (5E05); +RUNTEST 100 TCK; +SDR 16 TDI (D9F0); +RUNTEST 100 TCK; +SDR 16 TDI (A01F); +RUNTEST 100 TCK; +SDR 16 TDI (C207); +RUNTEST 100 TCK; +SDR 16 TDI (7030); +RUNTEST 100 TCK; +SDR 16 TDI (DDC7); +RUNTEST 100 TCK; +SDR 16 TDI (BD9C); +RUNTEST 100 TCK; +SDR 16 TDI (C9FF); +RUNTEST 100 TCK; +SDR 16 TDI (6BFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BBFA); +RUNTEST 100 TCK; +SDR 16 TDI (D2B0); +RUNTEST 100 TCK; +SDR 16 TDI (67EE); +RUNTEST 100 TCK; +SDR 16 TDI (4D86); +RUNTEST 100 TCK; +SDR 16 TDI (AFFD); +RUNTEST 100 TCK; +SDR 16 TDI (1BF0); +RUNTEST 100 TCK; +SDR 16 TDI (5E00); +RUNTEST 100 TCK; +SDR 16 TDI (59F0); +RUNTEST 100 TCK; +SDR 16 TDI (A01F); +RUNTEST 100 TCK; +SDR 16 TDI (8007); +RUNTEST 100 TCK; +SDR 16 TDI (7000); +RUNTEST 100 TCK; +SDR 16 TDI (119F); +RUNTEST 100 TCK; +SDR 16 TDI (9C49); +RUNTEST 100 TCK; +SDR 16 TDI (9CBF); +RUNTEST 100 TCK; +SDR 16 TDI (5FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BBBB); +RUNTEST 100 TCK; +SDR 16 TDI (71EE); +RUNTEST 100 TCK; +SDR 16 TDI (EEEF); +RUNTEST 100 TCK; +SDR 16 TDI (B33B); +RUNTEST 100 TCK; +SDR 16 TDI (B1F7); +RUNTEST 100 TCK; +SDR 16 TDI (6623); +RUNTEST 100 TCK; +SDR 16 TDI (FECE); +RUNTEST 100 TCK; +SDR 16 TDI (9D8F); +RUNTEST 100 TCK; +SDR 16 TDI (D998); +RUNTEST 100 TCK; +SDR 16 TDI (59C8); +RUNTEST 100 TCK; +SDR 16 TDI (EEE3); +RUNTEST 100 TCK; +SDR 16 TDI (BBBB); +RUNTEST 100 TCK; +SDR 16 TDI (BBFA); +RUNTEST 100 TCK; +SDR 16 TDI (77FF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (5555); +RUNTEST 100 TCK; +SDR 16 TDI (6946); +RUNTEST 100 TCK; +SDR 16 TDI (7555); +RUNTEST 100 TCK; +SDR 16 TDI (9773); +RUNTEST 100 TCK; +SDR 16 TDI (34A3); +RUNTEST 100 TCK; +SDR 16 TDI (5776); +RUNTEST 100 TCK; +SDR 16 TDI (7C9C); +RUNTEST 100 TCK; +SDR 16 TDI (B925); +RUNTEST 100 TCK; +SDR 16 TDI (5DDD); +RUNTEST 100 TCK; +SDR 16 TDI (7B9D); +RUNTEST 100 TCK; +SDR 16 TDI (CCC2); +RUNTEST 100 TCK; +SDR 16 TDI (B199); +RUNTEST 100 TCK; +SDR 16 TDI (99FF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (9BF9); +RUNTEST 100 TCK; +SDR 16 TDI (DDDD); +RUNTEST 100 TCK; +SDR 16 TDI (5FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FDDD); +RUNTEST 100 TCK; +SDR 16 TDI (BBBF); +RUNTEST 100 TCK; +SDR 16 TDI (FBEF); +RUNTEST 100 TCK; +SDR 16 TDI (6FFF); +RUNTEST 100 TCK; +SDR 16 TDI (F7EF); +RUNTEST 100 TCK; +SDR 16 TDI (BFEF); +RUNTEST 100 TCK; +SDR 16 TDI (3FBF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (777F); +RUNTEST 100 TCK; +SDR 16 TDI (B777); +RUNTEST 100 TCK; +SDR 16 TDI (773F); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BEB7); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (DCEF); +RUNTEST 100 TCK; +SDR 16 TDI (BDBF); +RUNTEST 100 TCK; +SDR 16 TDI (9FFE); +RUNTEST 100 TCK; +SDR 16 TDI (7F5F); +RUNTEST 100 TCK; +SDR 16 TDI (7EFF); +RUNTEST 100 TCK; +SDR 16 TDI (B7FF); +RUNTEST 100 TCK; +SDR 16 TDI (FDF7); +RUNTEST 100 TCK; +SDR 16 TDI (7FDF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BDFF); +RUNTEST 100 TCK; +SDR 16 TDI (FBFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (DFFD); +RUNTEST 100 TCK; +SDR 16 TDI (7FF7); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFD); +RUNTEST 100 TCK; +SDR 16 TDI (FFFB); +RUNTEST 100 TCK; +SDR 16 TDI (77F5); +RUNTEST 100 TCK; +SDR 16 TDI (FF7D); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (DFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (9B9F); +RUNTEST 100 TCK; +SDR 16 TDI (BFDE); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (AFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFBA); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (DDEF); +RUNTEST 100 TCK; +SDR 16 TDI (BEBF); +RUNTEST 100 TCK; +SDR 16 TDI (5FFA); +RUNTEST 100 TCK; +SDR 16 TDI (7EB7); +RUNTEST 100 TCK; +SDR 16 TDI (FFBD); +RUNTEST 100 TCK; +SDR 16 TDI (AFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FEF); +RUNTEST 100 TCK; +SDR 16 TDI (DFEF); +RUNTEST 100 TCK; +SDR 16 TDI (BBFF); +RUNTEST 100 TCK; +SDR 16 TDI (FDFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (AFFF); +RUNTEST 100 TCK; +SDR 16 TDI (5DFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FF7); +RUNTEST 100 TCK; +SDR 16 TDI (FEFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFD); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (77FA); +RUNTEST 100 TCK; +SDR 16 TDI (FDFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BDF7); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFDF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (F5FF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFB); +RUNTEST 100 TCK; +SDR 16 TDI (BFBF); +RUNTEST 100 TCK; +SDR 16 TDI (BDFE); +RUNTEST 100 TCK; +SDR 16 TDI (EFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFD); +RUNTEST 100 TCK; +SDR 16 TDI (D6FF); +RUNTEST 100 TCK; +SDR 16 TDI (B77F); +RUNTEST 100 TCK; +SDR 16 TDI (EFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FF7); +RUNTEST 100 TCK; +SDR 16 TDI (FBBF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7BFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FF5); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (F7FF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFB); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (5ED7); +RUNTEST 100 TCK; +SDR 16 TDI (EFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FF77); +RUNTEST 100 TCK; +SDR 16 TDI (77FE); +RUNTEST 100 TCK; +SDR 16 TDI (FDFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFAF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FBFF); +RUNTEST 100 TCK; +SDR 16 TDI (5FFD); +RUNTEST 100 TCK; +SDR 16 TDI (F7DF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFE); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FDD); +RUNTEST 100 TCK; +SDR 16 TDI (E5FF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFF7); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FABF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7EFA); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BEFF); +RUNTEST 100 TCK; +SDR 16 TDI (EFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FF7); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (AF7F); +RUNTEST 100 TCK; +SDR 16 TDI (EEFF); +RUNTEST 100 TCK; +SDR 16 TDI (5FFB); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFE); +RUNTEST 100 TCK; +SDR 16 TDI (FBFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFBF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFB); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (5EEF); +RUNTEST 100 TCK; +SDR 16 TDI (EFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (DFFE); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (57FF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BF7F); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (EFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (5FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (6FEF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (4FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFBF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFB); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BF7F); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (5F6F); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (DFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFE); +RUNTEST 100 TCK; +SDR 16 TDI (5FFB); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFDF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BF7F); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (5FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FDFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFD); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (EFFF); +RUNTEST 100 TCK; +SDR 16 TDI (5FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFEF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (DFFF); +RUNTEST 100 TCK; +SDR 16 TDI (5FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FF8); +RUNTEST 100 TCK; +SDR 16 TDI (DDDF); +RUNTEST 100 TCK; +SDR 16 TDI (BDDF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FEFE); +RUNTEST 100 TCK; +SDR 16 TDI (5FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (EFFD); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BF7F); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFF); +RUNTEST 100 TCK; +SDR 16 TDI (EEEF); +RUNTEST 100 TCK; +SDR 16 TDI (BBBF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (5FFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (BFFF); +RUNTEST 100 TCK; +SDR 16 TDI (FFDF); +RUNTEST 100 TCK; +SDR 16 TDI (7FFD); +RUNTEST 100 TCK; +SDR 16 TDI (FFFF); +RUNTEST 100 TCK; +SDR 16 TDI (9FDF); +RUNTEST 100 TCK; SDR 16 TDI (EFFD); RUNTEST 100 TCK; SDR 16 TDI (53FF); @@ -6227,9 +6227,9 @@ SDR 16 TDI (E7FF); RUNTEST 100 TCK; SDR 16 TDI (7FFF); RUNTEST 100 TCK; -SDR 16 TDI (7FF3); +SDR 16 TDI (FFF3); RUNTEST 100 TCK; -SDR 16 TDI (BF7F); +SDR 16 TDI (BFFF); RUNTEST 100 TCK; SDR 16 TDI (FFFF); RUNTEST 100 TCK; @@ -6243,25 +6243,25 @@ SDR 16 TDI (FFFF); RUNTEST 100 TCK; SDR 16 TDI (7FFF); RUNTEST 100 TCK; -SDR 16 TDI (FFFF); -RUNTEST 100 TCK; SDR 16 TDI (BFFF); RUNTEST 100 TCK; +SDR 16 TDI (BFFE); +RUNTEST 100 TCK; SDR 16 TDI (FFFF); RUNTEST 100 TCK; SDR 16 TDI (5FFF); RUNTEST 100 TCK; SDR 16 TDI (FFFB); RUNTEST 100 TCK; -SDR 16 TDI (BFFF); +SDR 16 TDI (B7FF); RUNTEST 100 TCK; SDR 16 TDI (FFFF); RUNTEST 100 TCK; SDR 16 TDI (7FFF); RUNTEST 100 TCK; -SDR 16 TDI (FFFF); +SDR 16 TDI (BBBF); RUNTEST 100 TCK; -SDR 16 TDI (BFFF); +SDR 16 TDI (BEEF); RUNTEST 100 TCK; SDR 16 TDI (FFFF); RUNTEST 100 TCK; @@ -7806,7 +7806,7 @@ SDR 16 TDI (FFFF) TDO (7FFF); SDR 16 TDI (FFFF) TDO (FFFF); SDR 16 TDI (FFFF) TDO (BFF7); SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (7FFB); SDR 16 TDI (FFFF) TDO (FFFF); SDR 16 TDI (FFFF) TDO (BFFF); SDR 16 TDI (FFFF) TDO (FFFF); @@ -7818,20 +7818,20 @@ SDR 16 TDI (FFFF) TDO (7FFF); SDR 16 TDI (FFFF) TDO (FFFF); SDR 16 TDI (FFFF) TDO (BFFF); SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (67FF); +SDR 16 TDI (FFFF) TDO (77FF); SDR 16 TDI (FFFF) TDO (FFFF); SDR 16 TDI (FFFF) TDO (BFFF); SDR 16 TDI (FFFF) TDO (C666); -SDR 16 TDI (FFFF) TDO (6FF9); +SDR 16 TDI (FFFF) TDO (6FFB); SDR 16 TDI (FFFF) TDO (FF7F); SDR 16 TDI (FFFF) TDO (BC66); -SDR 16 TDI (FFFF) TDO (67FE); +SDR 16 TDI (FFFF) TDO (67F6); SDR 16 TDI (FFFF) TDO (733F); SDR 16 TDI (FFFF) TDO (FF19); -SDR 16 TDI (FFFF) TDO (BD3F); -SDR 16 TDI (FFFF) TDO (ECCF); -SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (AF3F); +SDR 16 TDI (FFFF) TDO (E4CF); SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FF7F); SDR 16 TDI (FFFF) TDO (BFCC); SDR 16 TDI (FFFF) TDO (CFFF); SDR 16 TDI (FFFF) TDO (6FFF); @@ -7841,3038 +7841,3038 @@ SDR 16 TDI (FFFF) TDO (FFFF); SDR 16 TDI (FFFF) TDO (7FF7); SDR 16 TDI (FFFF) TDO (FFFF); SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFF7); -SDR 16 TDI (FFFF) TDO (77BF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (77DF); SDR 16 TDI (FFFF) TDO (EFFF); -SDR 16 TDI (FFFF) TDO (B7FF); -SDR 16 TDI (FFFF) TDO (F7FF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FF7F); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (6FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7FFB); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (77FF); -SDR 16 TDI (FFFF) TDO (FBFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFEF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7FDF); -SDR 16 TDI (FFFF) TDO (EFFF); -SDR 16 TDI (FFFF) TDO (ADFF); -SDR 16 TDI (FFFF) TDO (EFFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFFE); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7FEF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFFA); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (EEFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FF7F); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFFE); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFE); -SDR 16 TDI (FFFF) TDO (F7FF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (CFFF); -SDR 16 TDI (FFFF) TDO (BFBF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7DFF); -SDR 16 TDI (FFFF) TDO (FFBF); -SDR 16 TDI (FFFF) TDO (BFFE); -SDR 16 TDI (FFFF) TDO (FFFE); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FF7F); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (DFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (777F); -SDR 16 TDI (FFFF) TDO (EFFF); -SDR 16 TDI (FFFF) TDO (BF7F); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7BFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFFE); -SDR 16 TDI (FFFF) TDO (6FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FF7F); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (BFFE); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7F7F); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7DFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (6FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (F7FF); -SDR 16 TDI (FFFF) TDO (77FF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFDF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (77FF); -SDR 16 TDI (FFFF) TDO (FF7F); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BEFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (77F7); -SDR 16 TDI (FFFF) TDO (FFFE); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FBFF); -SDR 16 TDI (FFFF) TDO (76FF); -SDR 16 TDI (FFFF) TDO (ABFD); -SDR 16 TDI (FFFF) TDO (BBBF); -SDR 16 TDI (FFFF) TDO (FFDA); -SDR 16 TDI (FFFF) TDO (7DFE); -SDR 16 TDI (FFFF) TDO (FFBF); -SDR 16 TDI (FFFF) TDO (BFEF); -SDR 16 TDI (FFFF) TDO (FEFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FDFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (7F7F); -SDR 16 TDI (FFFF) TDO (BFEF); -SDR 16 TDI (FFFF) TDO (7FFE); -SDR 16 TDI (FFFF) TDO (7FF5); -SDR 16 TDI (FFFF) TDO (EF5F); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (DBFF); -SDR 16 TDI (FFFF) TDO (7B7B); -SDR 16 TDI (FFFF) TDO (EFFF); -SDR 16 TDI (FFFF) TDO (BDFE); -SDR 16 TDI (FFFF) TDO (DDFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFF7); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (7FFB); -SDR 16 TDI (FFFF) TDO (EF7E); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7FF7); -SDR 16 TDI (FFFF) TDO (EFFD); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FCCD); -SDR 16 TDI (FFFF) TDO (7BFD); -SDR 16 TDI (FFFF) TDO (FF7F); -SDR 16 TDI (FFFF) TDO (BDFF); -SDR 16 TDI (FFFF) TDO (7DFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FDFF); -SDR 16 TDI (FFFF) TDO (6FF7); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (BFEF); -SDR 16 TDI (FFFF) TDO (77FD); -SDR 16 TDI (FFFF) TDO (76FB); -SDR 16 TDI (FFFF) TDO (D7AF); -SDR 16 TDI (FFFF) TDO (BDDF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (6DBB); -SDR 16 TDI (FFFF) TDO (EFFF); -SDR 16 TDI (FFFF) TDO (BFF7); -SDR 16 TDI (FFFF) TDO (BEFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (F7EF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (7FB7); -SDR 16 TDI (FFFF) TDO (BAFB); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7BBF); -SDR 16 TDI (FFFF) TDO (FF7F); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFBF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (EEFF); -SDR 16 TDI (FFFF) TDO (BFFD); -SDR 16 TDI (FFFF) TDO (EFFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (EDFF); -SDR 16 TDI (FFFF) TDO (7FEF); -SDR 16 TDI (FFFF) TDO (AFFD); -SDR 16 TDI (FFFF) TDO (BFDF); -SDR 16 TDI (FFFF) TDO (FFF7); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (BFFE); -SDR 16 TDI (FFFF) TDO (B7FF); -SDR 16 TDI (FFFF) TDO (BEEF); -SDR 16 TDI (FFFF) TDO (7FFB); -SDR 16 TDI (FFFF) TDO (FFFF); SDR 16 TDI (FFFF) TDO (BBFF); -SDR 16 TDI (FFFF) TDO (FF7F); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFE); +SDR 16 TDI (FFFF) TDO (6FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FEF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFF5); SDR 16 TDI (FFFF) TDO (7FFF); SDR 16 TDI (FFFF) TDO (FFFF); SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (DFFF); +SDR 16 TDI (FFFF) TDO (FFFF); SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (F7FD); -SDR 16 TDI (FFFF) TDO (B7BF); -SDR 16 TDI (FFFF) TDO (FFFB); -SDR 16 TDI (FFFF) TDO (6CDF); -SDR 16 TDI (FFFF) TDO (DFFD); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (6FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (EFFF); SDR 16 TDI (FFFF) TDO (AFFF); -SDR 16 TDI (FFFF) TDO (FFDF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFD); SDR 16 TDI (FFFF) TDO (FFFF); SDR 16 TDI (FFFF) TDO (7FFF); SDR 16 TDI (FFFF) TDO (FFFF); SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (F9EF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (3FD7); -SDR 16 TDI (FFFF) TDO (BDEB); SDR 16 TDI (FFFF) TDO (FFFF); SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (EF7F); +SDR 16 TDI (FFFF) TDO (FFFF); SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FF77); -SDR 16 TDI (FFFF) TDO (7FF7); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (6FDF); SDR 16 TDI (FFFF) TDO (EEFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (F77F); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (B55F); -SDR 16 TDI (FFFF) TDO (FEBF); -SDR 16 TDI (FFFF) TDO (6FEF); -SDR 16 TDI (FFFF) TDO (FF7F); -SDR 16 TDI (FFFF) TDO (B6FF); -SDR 16 TDI (FFFF) TDO (FBFB); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFF6); -SDR 16 TDI (FFFF) TDO (ADDF); -SDR 16 TDI (FFFF) TDO (FB7C); -SDR 16 TDI (FFFF) TDO (7FBF); -SDR 16 TDI (FFFF) TDO (FDFF); -SDR 16 TDI (FFFF) TDO (BDDF); -SDR 16 TDI (FFFF) TDO (3775); -SDR 16 TDI (FFFF) TDO (69FF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFFD); -SDR 16 TDI (FFFF) TDO (7FFE); -SDR 16 TDI (FFFF) TDO (FBCC); -SDR 16 TDI (FFFF) TDO (BF7F); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (773F); -SDR 16 TDI (FFFF) TDO (FF7F); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFEF); -SDR 16 TDI (FFFF) TDO (7FE7); -SDR 16 TDI (FFFF) TDO (DFAF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7DFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (B55F); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (F7DD); -SDR 16 TDI (FFFF) TDO (BFF7); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7FF6); -SDR 16 TDI (FFFF) TDO (FFDF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFDF); -SDR 16 TDI (FFFF) TDO (7FFE); -SDR 16 TDI (FFFF) TDO (F7FF); -SDR 16 TDI (FFFF) TDO (BFFD); -SDR 16 TDI (FFFF) TDO (FF75); -SDR 16 TDI (FFFF) TDO (69FF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BAAF); -SDR 16 TDI (FFFF) TDO (FEFF); -SDR 16 TDI (FFFF) TDO (7FEF); -SDR 16 TDI (FFFF) TDO (FFFE); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFFE); -SDR 16 TDI (FFFF) TDO (7FFD); -SDR 16 TDI (FFFF) TDO (FFB9); -SDR 16 TDI (FFFF) TDO (BDDF); -SDR 16 TDI (FFFF) TDO (FBBA); -SDR 16 TDI (FFFF) TDO (7DBB); -SDR 16 TDI (FFFF) TDO (7FBF); -SDR 16 TDI (FFFF) TDO (BBBF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (7DFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFFE); -SDR 16 TDI (FFFF) TDO (6FFF); -SDR 16 TDI (FFFF) TDO (D3F7); -SDR 16 TDI (FFFF) TDO (B97F); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7FAF); -SDR 16 TDI (FFFF) TDO (FFEF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFF7); -SDR 16 TDI (FFFF) TDO (7BFF); -SDR 16 TDI (FFFF) TDO (EDEF); -SDR 16 TDI (FFFF) TDO (BF77); -SDR 16 TDI (FFFF) TDO (75FF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFBF); -SDR 16 TDI (FFFF) TDO (7BFC); -SDR 16 TDI (FFFF) TDO (FF7F); -SDR 16 TDI (FFFF) TDO (BFFB); -SDR 16 TDI (FFFF) TDO (77F9); -SDR 16 TDI (FFFF) TDO (77FB); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7FEF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FF7C); -SDR 16 TDI (FFFF) TDO (6DF7); -SDR 16 TDI (FFFF) TDO (3E9F); -SDR 16 TDI (FFFF) TDO (BC7F); -SDR 16 TDI (FFFF) TDO (33FD); -SDR 16 TDI (FFFF) TDO (6FCA); -SDR 16 TDI (FFFF) TDO (FFB6); -SDR 16 TDI (FFFF) TDO (AFFF); -SDR 16 TDI (FFFF) TDO (FF21); -SDR 16 TDI (FFFF) TDO (7DE7); -SDR 16 TDI (FFFF) TDO (8FBF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BBBF); -SDR 16 TDI (FFFF) TDO (FCFF); -SDR 16 TDI (FFFF) TDO (7FEF); -SDR 16 TDI (FFFF) TDO (FBE3); -SDR 16 TDI (FFFF) TDO (BFBB); -SDR 16 TDI (FFFF) TDO (FFF7); -SDR 16 TDI (FFFF) TDO (7F37); -SDR 16 TDI (FFFF) TDO (FF4B); -SDR 16 TDI (FFFF) TDO (B99F); -SDR 16 TDI (FFFF) TDO (F9DE); -SDR 16 TDI (FFFF) TDO (779B); -SDR 16 TDI (FFFF) TDO (786F); -SDR 16 TDI (FFFF) TDO (BDDC); -SDR 16 TDI (FFFF) TDO (727F); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFBF); -SDR 16 TDI (FFFF) TDO (77FC); -SDR 16 TDI (FFFF) TDO (E57C); -SDR 16 TDI (FFFF) TDO (A3F7); -SDR 16 TDI (FFFF) TDO (FFFA); -SDR 16 TDI (FFFF) TDO (77FD); -SDR 16 TDI (FFFF) TDO (7FFD); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (6F7D); -SDR 16 TDI (FFFF) TDO (FFDF); -SDR 16 TDI (FFFF) TDO (BAAF); -SDR 16 TDI (FFFF) TDO (8FFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (B66F); -SDR 16 TDI (FFFF) TDO (FCFC); -SDR 16 TDI (FFFF) TDO (67DE); -SDR 16 TDI (FFFF) TDO (1FFA); -SDR 16 TDI (FFFF) TDO (A000); -SDR 16 TDI (FFFF) TDO (FFE0); -SDR 16 TDI (FFFF) TDO (7882); -SDR 16 TDI (FFFF) TDO (1F0F); -SDR 16 TDI (FFFF) TDO (A61F); -SDR 16 TDI (FFFF) TDO (7FE7); -SDR 16 TDI (FFFF) TDO (7245); -SDR 16 TDI (FFFF) TDO (A8EF); -SDR 16 TDI (FFFF) TDO (B781); -SDR 16 TDI (FFFF) TDO (80F5); -SDR 16 TDI (FFFF) TDO (69FF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BEDF); -SDR 16 TDI (FFFF) TDO (FC3C); -SDR 16 TDI (FFFF) TDO (67A0); -SDR 16 TDI (FFFF) TDO (1BA2); -SDR 16 TDI (FFFF) TDO (A000); -SDR 16 TDI (FFFF) TDO (FFD0); -SDR 16 TDI (FFFF) TDO (7800); -SDR 16 TDI (FFFF) TDO (1F0F); -SDR 16 TDI (FFFF) TDO (A01E); -SDR 16 TDI (FFFF) TDO (F9F6); -SDR 16 TDI (FFFF) TDO (6280); -SDR 16 TDI (FFFF) TDO (A8CF); -SDR 16 TDI (FFFF) TDO (AF81); -SDR 16 TDI (FFFF) TDO (907F); -SDR 16 TDI (FFFF) TDO (7DFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (B77F); -SDR 16 TDI (FFFF) TDO (FDFC); -SDR 16 TDI (FFFF) TDO (67E7); -SDR 16 TDI (FFFF) TDO (1FFB); -SDR 16 TDI (FFFF) TDO (A230); -SDR 16 TDI (FFFF) TDO (33F0); -SDR 16 TDI (FFFF) TDO (6001); -SDR 16 TDI (FFFF) TDO (9F0F); -SDR 16 TDI (FFFF) TDO (BF9F); -SDR 16 TDI (FFFF) TDO (FFE7); -SDR 16 TDI (FFFF) TDO (7253); -SDR 16 TDI (FFFF) TDO (00DF); -SDR 16 TDI (FFFF) TDO (BF09); -SDR 16 TDI (FFFF) TDO (80F5); -SDR 16 TDI (FFFF) TDO (6BFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BDFF); -SDR 16 TDI (FFFF) TDO (FDBE); -SDR 16 TDI (FFFF) TDO (67E1); -SDR 16 TDI (FFFF) TDO (01C2); -SDR 16 TDI (FFFF) TDO (A030); -SDR 16 TDI (FFFF) TDO (33F4); -SDR 16 TDI (FFFF) TDO (6001); -SDR 16 TDI (FFFF) TDO (9F7E); -SDR 16 TDI (FFFF) TDO (BF9F); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (6290); -SDR 16 TDI (FFFF) TDO (80DF); -SDR 16 TDI (FFFF) TDO (BF09); -SDR 16 TDI (FFFF) TDO (007F); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BAA7); -SDR 16 TDI (FFFF) TDO (3332); -SDR 16 TDI (FFFF) TDO (61E6); -SDR 16 TDI (FFFF) TDO (EE6F); -SDR 16 TDI (FFFF) TDO (A318); -SDR 16 TDI (FFFF) TDO (11F2); -SDR 16 TDI (FFFF) TDO (6144); -SDR 16 TDI (FFFF) TDO (3CEC); -SDR 16 TDI (FFFF) TDO (BDCF); -SDR 16 TDI (FFFF) TDO (9BB8); -SDR 16 TDI (FFFF) TDO (73C9); -SDR 16 TDI (FFFF) TDO (CCE7); -SDR 16 TDI (FFFF) TDO (B89C); -SDR 16 TDI (FFFF) TDO (98FF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (7777); -SDR 16 TDI (FFFF) TDO (6952); -SDR 16 TDI (FFFF) TDO (6767); -SDR 16 TDI (FFFF) TDO (B773); -SDR 16 TDI (FFFF) TDO (22A1); -SDR 16 TDI (FFFF) TDO (6627); -SDR 16 TDI (FFFF) TDO (7DCD); -SDR 16 TDI (FFFF) TDO (B985); -SDR 16 TDI (FFFF) TDO (599D); -SDR 16 TDI (FFFF) TDO (79DD); -SDR 16 TDI (FFFF) TDO (DDC2); -SDR 16 TDI (FFFF) TDO (B5DD); -SDR 16 TDI (FFFF) TDO (DDFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BEF7); -SDR 16 TDI (FFFF) TDO (FFBF); -SDR 16 TDI (FFFF) TDO (77CF); -SDR 16 TDI (FFFF) TDO (FEFD); -SDR 16 TDI (FFFF) TDO (BF99); -SDR 16 TDI (FFFF) TDO (DFEE); -SDR 16 TDI (FFFF) TDO (7DDD); -SDR 16 TDI (FFFF) TDO (FFFE); -SDR 16 TDI (FFFF) TDO (BFDF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (EEFF); -SDR 16 TDI (FFFF) TDO (B3BB); -SDR 16 TDI (FFFF) TDO (BBFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7FF7); -SDR 16 TDI (FFFF) TDO (FFFB); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (EBFA); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFF7); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FF7F); -SDR 16 TDI (FFFF) TDO (7BFF); -SDR 16 TDI (FFFF) TDO (BF7F); -SDR 16 TDI (FFFF) TDO (BEFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFD7); -SDR 16 TDI (FFFF) TDO (5FFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (F7F7); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7D7D); -SDR 16 TDI (FFFF) TDO (DDFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FBFB); -SDR 16 TDI (FFFF) TDO (6DFF); -SDR 16 TDI (FFFF) TDO (FDFF); -SDR 16 TDI (FFFF) TDO (BFBF); -SDR 16 TDI (FFFF) TDO (DBFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (EFEF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (D7FD); -SDR 16 TDI (FFFF) TDO (7FFD); -SDR 16 TDI (FFFF) TDO (DFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFFE); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FEFF); -SDR 16 TDI (FFFF) TDO (BEFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (7DFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BBBF); -SDR 16 TDI (FFFF) TDO (EFFF); -SDR 16 TDI (FFFF) TDO (7FF7); -SDR 16 TDI (FFFF) TDO (FFFD); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFFB); -SDR 16 TDI (FFFF) TDO (7D7F); -SDR 16 TDI (FFFF) TDO (FDFB); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FF7F); -SDR 16 TDI (FFFF) TDO (77FF); -SDR 16 TDI (FFFF) TDO (BFBF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7DFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BEFB); -SDR 16 TDI (FFFF) TDO (7FE7); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (7F7F); -SDR 16 TDI (FFFF) TDO (BFBF); -SDR 16 TDI (FFFF) TDO (F7FB); -SDR 16 TDI (FFFF) TDO (737F); -SDR 16 TDI (FFFF) TDO (DBFF); -SDR 16 TDI (FFFF) TDO (BFBF); -SDR 16 TDI (FFFF) TDO (FDF6); -SDR 16 TDI (FFFF) TDO (7DFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFDF); -SDR 16 TDI (FFFF) TDO (7EFF); -SDR 16 TDI (FFFF) TDO (77FF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFD); -SDR 16 TDI (FFFF) TDO (F7FF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (F7DC); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (7FF7); -SDR 16 TDI (FFFF) TDO (EFAF); -SDR 16 TDI (FFFF) TDO (BCFF); -SDR 16 TDI (FFFF) TDO (DFFF); -SDR 16 TDI (FFFF) TDO (7B7E); -SDR 16 TDI (FFFF) TDO (DFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FDFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BF5D); -SDR 16 TDI (FFFF) TDO (FEFF); -SDR 16 TDI (FFFF) TDO (77FF); -SDR 16 TDI (FFFF) TDO (FFFD); -SDR 16 TDI (FFFF) TDO (BF7F); -SDR 16 TDI (FFFF) TDO (F7FF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFDF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (DEFF); -SDR 16 TDI (FFFF) TDO (6BF9); -SDR 16 TDI (FFFF) TDO (FBBF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (BBDB); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (6EBF); -SDR 16 TDI (FFFF) TDO (AFFF); -SDR 16 TDI (FFFF) TDO (BFFB); -SDR 16 TDI (FFFF) TDO (6B77); -SDR 16 TDI (FFFF) TDO (B77F); -SDR 16 TDI (FFFF) TDO (BB5F); -SDR 16 TDI (FFFF) TDO (FBF7); -SDR 16 TDI (FFFF) TDO (7D7F); -SDR 16 TDI (FFFF) TDO (DFFF); -SDR 16 TDI (FFFF) TDO (BFDF); -SDR 16 TDI (FFFF) TDO (FAFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BEFF); -SDR 16 TDI (FFFF) TDO (FAFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFC); -SDR 16 TDI (FFFF) TDO (BEFE); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (7FF7); -SDR 16 TDI (FFFF) TDO (DFFD); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFB7); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFF7); -SDR 16 TDI (FFFF) TDO (EFFB); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFEF); -SDR 16 TDI (FFFF) TDO (7FEF); -SDR 16 TDI (FFFF) TDO (7BFF); -SDR 16 TDI (FFFF) TDO (BF77); -SDR 16 TDI (FFFF) TDO (FFF7); -SDR 16 TDI (FFFF) TDO (7CBD); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BBFF); -SDR 16 TDI (FFFF) TDO (FEFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (F7FF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FDFE); -SDR 16 TDI (FFFF) TDO (B96F); -SDR 16 TDI (FFFF) TDO (FFFB); -SDR 16 TDI (FFFF) TDO (7D75); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (BFF7); -SDR 16 TDI (FFFF) TDO (7FFA); -SDR 16 TDI (FFFF) TDO (FEFF); -SDR 16 TDI (FFFF) TDO (BFBB); -SDR 16 TDI (FFFF) TDO (F37F); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BDFF); -SDR 16 TDI (FFFF) TDO (FEDF); -SDR 16 TDI (FFFF) TDO (77FE); -SDR 16 TDI (FFFF) TDO (FFFD); -SDR 16 TDI (FFFF) TDO (BFF9); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (7FBF); -SDR 16 TDI (FFFF) TDO (5FFE); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFBF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFF7); -SDR 16 TDI (FFFF) TDO (FFFB); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (B55F); -SDR 16 TDI (FFFF) TDO (F7BF); -SDR 16 TDI (FFFF) TDO (7FFB); -SDR 16 TDI (FFFF) TDO (EFEF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (7BFD); -SDR 16 TDI (FFFF) TDO (7BFF); -SDR 16 TDI (FFFF) TDO (7FDF); -SDR 16 TDI (FFFF) TDO (BFBF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (7DF4); -SDR 16 TDI (FFFF) TDO (79FF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFD); -SDR 16 TDI (FFFF) TDO (7FFE); -SDR 16 TDI (FFFF) TDO (7FFE); -SDR 16 TDI (FFFF) TDO (BF3A); -SDR 16 TDI (FFFF) TDO (BBFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7FF7); -SDR 16 TDI (FFFF) TDO (BEFB); -SDR 16 TDI (FFFF) TDO (ADFF); -SDR 16 TDI (FFFF) TDO (BFBB); -SDR 16 TDI (FFFF) TDO (77D9); -SDR 16 TDI (FFFF) TDO (7BBF); -SDR 16 TDI (FFFF) TDO (BEF3); -SDR 16 TDI (FFFF) TDO (EEFF); -SDR 16 TDI (FFFF) TDO (7DFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (B55E); -SDR 16 TDI (FFFF) TDO (FFF7); -SDR 16 TDI (FFFF) TDO (6FEF); -SDR 16 TDI (FFFF) TDO (FBFE); -SDR 16 TDI (FFFF) TDO (BD9B); -SDR 16 TDI (FFFF) TDO (FFF7); -SDR 16 TDI (FFFF) TDO (777F); -SDR 16 TDI (FFFF) TDO (FFFE); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FBFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (DDDF); -SDR 16 TDI (FFFF) TDO (BD5F); -SDR 16 TDI (FFFF) TDO (DF75); -SDR 16 TDI (FFFF) TDO (69FF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (AAAF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7DEB); -SDR 16 TDI (FFFF) TDO (DFFF); -SDR 16 TDI (FFFF) TDO (BFB7); -SDR 16 TDI (FFFF) TDO (FBFF); -SDR 16 TDI (FFFF) TDO (6FF6); -SDR 16 TDI (FFFF) TDO (DDFF); -SDR 16 TDI (FFFF) TDO (ADFF); -SDR 16 TDI (FFFF) TDO (FFDF); -SDR 16 TDI (FFFF) TDO (7EFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (BFEF); -SDR 16 TDI (FFFF) TDO (6FFF); -SDR 16 TDI (FFFF) TDO (7DFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (EEFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (DFFE); -SDR 16 TDI (FFFF) TDO (7CFF); -SDR 16 TDI (FFFF) TDO (FFDB); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (BEFF); -SDR 16 TDI (FFFF) TDO (775B); -SDR 16 TDI (FFFF) TDO (DFFF); -SDR 16 TDI (FFFF) TDO (BFDF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFEF); -SDR 16 TDI (FFFF) TDO (7FFE); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (B6FF); -SDR 16 TDI (FFFF) TDO (6FFB); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFD); -SDR 16 TDI (FFFF) TDO (6CFB); -SDR 16 TDI (FFFF) TDO (7DBF); -SDR 16 TDI (FFFF) TDO (FEFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFFD); -SDR 16 TDI (FFFF) TDO (6DED); -SDR 16 TDI (FFFF) TDO (F37F); -SDR 16 TDI (FFFF) TDO (A77F); -SDR 16 TDI (FFFF) TDO (CFFE); -SDR 16 TDI (FFFF) TDO (7F76); -SDR 16 TDI (FFFF) TDO (BFF3); -SDR 16 TDI (FFFF) TDO (B7FD); -SDR 16 TDI (FFFF) TDO (3AFB); -SDR 16 TDI (FFFF) TDO (7717); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (BFF5); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BEEC); -SDR 16 TDI (FFFF) TDO (FE5F); -SDR 16 TDI (FFFF) TDO (7FFA); -SDR 16 TDI (FFFF) TDO (7FFC); -SDR 16 TDI (FFFF) TDO (B8BF); -SDR 16 TDI (FFFF) TDO (77FB); -SDR 16 TDI (FFFF) TDO (62EF); -SDR 16 TDI (FFFF) TDO (FFCF); -SDR 16 TDI (FFFF) TDO (ADBF); -SDR 16 TDI (FFFF) TDO (FDFF); -SDR 16 TDI (FFFF) TDO (7FEB); -SDR 16 TDI (FFFF) TDO (D45F); -SDR 16 TDI (FFFF) TDO (BE5F); -SDR 16 TDI (FFFF) TDO (566A); -SDR 16 TDI (FFFF) TDO (77FF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (67F7); -SDR 16 TDI (FFFF) TDO (7FF7); -SDR 16 TDI (FFFF) TDO (9FD7); -SDR 16 TDI (FFFF) TDO (BFE3); -SDR 16 TDI (FFFF) TDO (BBF5); -SDR 16 TDI (FFFF) TDO (7DFF); -SDR 16 TDI (FFFF) TDO (5CFD); -SDR 16 TDI (FFFF) TDO (BBFF); -SDR 16 TDI (FFFF) TDO (D71D); -SDR 16 TDI (FFFF) TDO (78FD); -SDR 16 TDI (FFFF) TDO (AFFF); -SDR 16 TDI (FFFF) TDO (BDAE); -SDR 16 TDI (FFFF) TDO (EDFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (B99D); -SDR 16 TDI (FFFF) TDO (69FC); -SDR 16 TDI (FFFF) TDO (67C0); -SDR 16 TDI (FFFF) TDO (0B9E); -SDR 16 TDI (FFFF) TDO (B4A0); -SDR 16 TDI (FFFF) TDO (03EE); -SDR 16 TDI (FFFF) TDO (7580); -SDR 16 TDI (FFFF) TDO (1302); -SDR 16 TDI (FFFF) TDO (A01E); -SDR 16 TDI (FFFF) TDO (1819); -SDR 16 TDI (FFFF) TDO (70AF); -SDR 16 TDI (FFFF) TDO (FC0F); -SDR 16 TDI (FFFF) TDO (B079); -SDR 16 TDI (FFFF) TDO (87F5); -SDR 16 TDI (FFFF) TDO (6BFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (ABFE); -SDR 16 TDI (FFFF) TDO (E9C3); -SDR 16 TDI (FFFF) TDO (67A0); -SDR 16 TDI (FFFF) TDO (0BE0); -SDR 16 TDI (FFFF) TDO (A0A0); -SDR 16 TDI (FFFF) TDO (03D0); -SDR 16 TDI (FFFF) TDO (7580); -SDR 16 TDI (FFFF) TDO (1302); -SDR 16 TDI (FFFF) TDO (B41B); -SDR 16 TDI (FFFF) TDO (9F99); -SDR 16 TDI (FFFF) TDO (70AB); -SDR 16 TDI (FFFF) TDO (0C0F); -SDR 16 TDI (FFFF) TDO (AAA9); -SDR 16 TDI (FFFF) TDO (D07F); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BD5D); -SDR 16 TDI (FFFF) TDO (9283); -SDR 16 TDI (FFFF) TDO (7FF0); -SDR 16 TDI (FFFF) TDO (2C60); -SDR 16 TDI (FFFF) TDO (AA40); -SDR 16 TDI (FFFF) TDO (E3FF); -SDR 16 TDI (FFFF) TDO (6C06); -SDR 16 TDI (FFFF) TDO (30C7); -SDR 16 TDI (FFFF) TDO (A47F); -SDR 16 TDI (FFFF) TDO (E066); -SDR 16 TDI (FFFF) TDO (610F); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (B86C); -SDR 16 TDI (FFFF) TDO (84F5); -SDR 16 TDI (FFFF) TDO (6BFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFE); -SDR 16 TDI (FFFF) TDO (D2B0); -SDR 16 TDI (FFFF) TDO (67F6); -SDR 16 TDI (FFFF) TDO (0D86); -SDR 16 TDI (FFFF) TDO (A040); -SDR 16 TDI (FFFF) TDO (C3F0); -SDR 16 TDI (FFFF) TDO (7C06); -SDR 16 TDI (FFFF) TDO (10C1); -SDR 16 TDI (FFFF) TDO (A07F); -SDR 16 TDI (FFFF) TDO (9DE6); -SDR 16 TDI (FFFF) TDO (6083); -SDR 16 TDI (FFFF) TDO (3C0F); -SDR 16 TDI (FFFF) TDO (BCC8); -SDR 16 TDI (FFFF) TDO (07FF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BAA7); -SDR 16 TDI (FFFF) TDO (BBBB); -SDR 16 TDI (FFFF) TDO (71EE); -SDR 16 TDI (FFFF) TDO (2EEF); -SDR 16 TDI (FFFF) TDO (B219); -SDR 16 TDI (FFFF) TDO (31F1); -SDR 16 TDI (FFFF) TDO (6286); -SDR 16 TDI (FFFF) TDO (38CF); -SDR 16 TDI (FFFF) TDO (B9AF); -SDR 16 TDI (FFFF) TDO (9999); -SDR 16 TDI (FFFF) TDO (71CF); -SDR 16 TDI (FFFF) TDO (CEC7); -SDR 16 TDI (FFFF) TDO (BA9C); -SDR 16 TDI (FFFF) TDO (9BFE); -SDR 16 TDI (FFFF) TDO (77FF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFF7); -SDR 16 TDI (FFFF) TDO (1111); -SDR 16 TDI (FFFF) TDO (6167); -SDR 16 TDI (FFFF) TDO (6445); -SDR 16 TDI (FFFF) TDO (B763); -SDR 16 TDI (FFFF) TDO (36A9); -SDR 16 TDI (FFFF) TDO (7677); -SDR 16 TDI (FFFF) TDO (79DC); -SDR 16 TDI (FFFF) TDO (BBA5); -SDR 16 TDI (FFFF) TDO (19D9); -SDR 16 TDI (FFFF) TDO (79DC); -SDR 16 TDI (FFFF) TDO (DC9A); -SDR 16 TDI (FFFF) TDO (B1CD); -SDR 16 TDI (FFFF) TDO (D9FF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFD); -SDR 16 TDI (FFFF) TDO (DDDD); -SDR 16 TDI (FFFF) TDO (7FDF); -SDR 16 TDI (FFFF) TDO (FDDD); -SDR 16 TDI (FFFF) TDO (BBDD); -SDR 16 TDI (FFFF) TDO (BBEF); -SDR 16 TDI (FFFF) TDO (7FCF); -SDR 16 TDI (FFFF) TDO (FEF7); -SDR 16 TDI (FFFF) TDO (BFC7); -SDR 16 TDI (FFFF) TDO (7FBF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (EFEF); -SDR 16 TDI (FFFF) TDO (B77F); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (EFFF); -SDR 16 TDI (FFFF) TDO (6FEF); -SDR 16 TDI (FFFF) TDO (FDF7); -SDR 16 TDI (FFFF) TDO (BF77); -SDR 16 TDI (FFFF) TDO (EBFA); -SDR 16 TDI (FFFF) TDO (7FEE); -SDR 16 TDI (FFFF) TDO (DF7F); -SDR 16 TDI (FFFF) TDO (BEBF); -SDR 16 TDI (FFFF) TDO (F7DF); -SDR 16 TDI (FFFF) TDO (6DFB); -SDR 16 TDI (FFFF) TDO (FEDF); -SDR 16 TDI (FFFF) TDO (BD7F); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FD7F); -SDR 16 TDI (FFFF) TDO (7FFE); -SDR 16 TDI (FFFF) TDO (FF3F); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (77FF); -SDR 16 TDI (FFFF) TDO (FFF7); -SDR 16 TDI (FFFF) TDO (BBFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7BFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (F7DF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (DD7F); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FB7F); -SDR 16 TDI (FFFF) TDO (BFF7); -SDR 16 TDI (FFFF) TDO (BBFD); -SDR 16 TDI (FFFF) TDO (7FFE); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (BBBF); -SDR 16 TDI (FFFF) TDO (EFDF); -SDR 16 TDI (FFFF) TDO (6BF7); -SDR 16 TDI (FFFF) TDO (FFDF); -SDR 16 TDI (FFFF) TDO (BEFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFBF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (77F7); -SDR 16 TDI (FFFF) TDO (FFEF); -SDR 16 TDI (FFFF) TDO (BF7F); -SDR 16 TDI (FFFF) TDO (EFFB); -SDR 16 TDI (FFFF) TDO (77EF); -SDR 16 TDI (FFFF) TDO (FF77); -SDR 16 TDI (FFFF) TDO (BEFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7EFF); -SDR 16 TDI (FFFF) TDO (FDFF); SDR 16 TDI (FFFF) TDO (BDFF); SDR 16 TDI (FFFF) TDO (F7FF); SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BBBF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (DFFB); -SDR 16 TDI (FFFF) TDO (BFBF); -SDR 16 TDI (FFFF) TDO (F7FF); -SDR 16 TDI (FFFF) TDO (7FFB); -SDR 16 TDI (FFFF) TDO (DBED); -SDR 16 TDI (FFFF) TDO (BD3F); -SDR 16 TDI (FFFF) TDO (FEF7); -SDR 16 TDI (FFFF) TDO (66FF); -SDR 16 TDI (FFFF) TDO (FFEF); -SDR 16 TDI (FFFF) TDO (BFF7); -SDR 16 TDI (FFFF) TDO (FFFB); +SDR 16 TDI (FFFF) TDO (BF7F); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFE); SDR 16 TDI (FFFF) TDO (7FFF); SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFE); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FBFF); +SDR 16 TDI (FFFF) TDO (7FFF); SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7FF3); -SDR 16 TDI (FFFF) TDO (F7FE); -SDR 16 TDI (FFFF) TDO (BBDE); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7FF7); -SDR 16 TDI (FFFF) TDO (EF7F); SDR 16 TDI (FFFF) TDO (BFFF); SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7FB7); -SDR 16 TDI (FFFF) TDO (EFBF); -SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (7FBF); +SDR 16 TDI (FFFF) TDO (EFFF); +SDR 16 TDI (FFFF) TDO (BF7F); +SDR 16 TDI (FFFF) TDO (FFBF); +SDR 16 TDI (FFFF) TDO (7FBF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BBFB); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFF); SDR 16 TDI (FFFF) TDO (7FFF); SDR 16 TDI (FFFF) TDO (FFFF); SDR 16 TDI (FFFF) TDO (BDF7); -SDR 16 TDI (FFFF) TDO (7EEB); -SDR 16 TDI (FFFF) TDO (77FF); -SDR 16 TDI (FFFF) TDO (FFBF); -SDR 16 TDI (FFFF) TDO (B77D); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7DFF); +SDR 16 TDI (FFFF) TDO (EBFF); SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (6EFE); -SDR 16 TDI (FFFF) TDO (DF5F); -SDR 16 TDI (FFFF) TDO (BEFF); -SDR 16 TDI (FFFF) TDO (BBFB); -SDR 16 TDI (FFFF) TDO (7BFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BBFF); -SDR 16 TDI (FFFF) TDO (FBF7); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFD); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7FEB); -SDR 16 TDI (FFFF) TDO (D7FB); -SDR 16 TDI (FFFF) TDO (AFDF); -SDR 16 TDI (FFFF) TDO (F7FF); -SDR 16 TDI (FFFF) TDO (7FF3); -SDR 16 TDI (FFFF) TDO (F7FD); -SDR 16 TDI (FFFF) TDO (BDDF); -SDR 16 TDI (FFFF) TDO (FF76); -SDR 16 TDI (FFFF) TDO (7D7B); -SDR 16 TDI (FFFF) TDO (EF5F); -SDR 16 TDI (FFFF) TDO (BFEF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BAFF); -SDR 16 TDI (FFFF) TDO (F9FF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (BF7B); -SDR 16 TDI (FFFF) TDO (BFFB); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7BDD); -SDR 16 TDI (FFFF) TDO (F7FB); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FF6F); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (AFFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFDF); -SDR 16 TDI (FFFF) TDO (7FEF); -SDR 16 TDI (FFFF) TDO (7FEF); -SDR 16 TDI (FFFF) TDO (BEFF); -SDR 16 TDI (FFFF) TDO (FFF7); -SDR 16 TDI (FFFF) TDO (6FFF); -SDR 16 TDI (FFFF) TDO (7FFD); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (BFBE); -SDR 16 TDI (FFFF) TDO (7FDF); -SDR 16 TDI (FFFF) TDO (FBFF); -SDR 16 TDI (FFFF) TDO (BBEF); -SDR 16 TDI (FFFF) TDO (7EFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (B7FF); -SDR 16 TDI (FFFF) TDO (F7FF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BDBF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7EFF); -SDR 16 TDI (FFFF) TDO (77FF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FB7B); -SDR 16 TDI (FFFF) TDO (6FFE); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BDBF); -SDR 16 TDI (FFFF) TDO (737F); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BEFF); -SDR 16 TDI (FFFF) TDO (FEEF); -SDR 16 TDI (FFFF) TDO (77FE); -SDR 16 TDI (FFFF) TDO (DEEB); -SDR 16 TDI (FFFF) TDO (BFF7); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (6BBB); -SDR 16 TDI (FFFF) TDO (FFFA); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFAF); -SDR 16 TDI (FFFF) TDO (7FEF); -SDR 16 TDI (FFFF) TDO (FBFF); -SDR 16 TDI (FFFF) TDO (BFF7); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (B7FF); -SDR 16 TDI (FFFF) TDO (77FF); -SDR 16 TDI (FFFF) TDO (EFF7); -SDR 16 TDI (FFFF) TDO (BF7F); -SDR 16 TDI (FFFF) TDO (77FF); -SDR 16 TDI (FFFF) TDO (7DD5); -SDR 16 TDI (FFFF) TDO (F7FF); -SDR 16 TDI (FFFF) TDO (B7DF); -SDR 16 TDI (FFFF) TDO (FFFD); -SDR 16 TDI (FFFF) TDO (7EF7); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (BFEF); -SDR 16 TDI (FFFF) TDO (FFFD); -SDR 16 TDI (FFFF) TDO (7BFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BB7F); -SDR 16 TDI (FFFF) TDO (FFFE); -SDR 16 TDI (FFFF) TDO (7FFD); -SDR 16 TDI (FFFF) TDO (DF3B); -SDR 16 TDI (FFFF) TDO (B5FF); -SDR 16 TDI (FFFF) TDO (FFFE); -SDR 16 TDI (FFFF) TDO (777F); -SDR 16 TDI (FFFF) TDO (5FEF); -SDR 16 TDI (FFFF) TDO (BFFE); -SDR 16 TDI (FFFF) TDO (F7FF); -SDR 16 TDI (FFFF) TDO (6B7F); -SDR 16 TDI (FFFF) TDO (FF5F); -SDR 16 TDI (FFFF) TDO (BFBF); -SDR 16 TDI (FFFF) TDO (F5FF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (B7BE); -SDR 16 TDI (FFFF) TDO (FF7B); -SDR 16 TDI (FFFF) TDO (7FF7); -SDR 16 TDI (FFFF) TDO (7BFF); -SDR 16 TDI (FFFF) TDO (BFF7); -SDR 16 TDI (FFFF) TDO (FFFB); -SDR 16 TDI (FFFF) TDO (7FDB); -SDR 16 TDI (FFFF) TDO (BFFD); -SDR 16 TDI (FFFF) TDO (AFFF); -SDR 16 TDI (FFFF) TDO (CBDE); -SDR 16 TDI (FFFF) TDO (7DEB); -SDR 16 TDI (FFFF) TDO (EFFF); -SDR 16 TDI (FFFF) TDO (BCFB); -SDR 16 TDI (FFFF) TDO (BF7D); -SDR 16 TDI (FFFF) TDO (7BFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (AFFB); -SDR 16 TDI (FFFF) TDO (DFFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FDDE); -SDR 16 TDI (FFFF) TDO (BD3F); -SDR 16 TDI (FFFF) TDO (FFEF); -SDR 16 TDI (FFFF) TDO (7FEE); -SDR 16 TDI (FFFF) TDO (FFEB); -SDR 16 TDI (FFFF) TDO (BBDB); -SDR 16 TDI (FFFF) TDO (BFFB); -SDR 16 TDI (FFFF) TDO (77FF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (EEFF); -SDR 16 TDI (FFFF) TDO (7DFD); -SDR 16 TDI (FFFF) TDO (DFFF); -SDR 16 TDI (FFFF) TDO (BDDD); -SDR 16 TDI (FFFF) TDO (FFFD); -SDR 16 TDI (FFFF) TDO (6B7F); -SDR 16 TDI (FFFF) TDO (FBF7); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FD7D); -SDR 16 TDI (FFFF) TDO (7B7F); -SDR 16 TDI (FFFF) TDO (7F7F); -SDR 16 TDI (FFFF) TDO (BFEF); -SDR 16 TDI (FFFF) TDO (EDFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFE); -SDR 16 TDI (FFFF) TDO (FFEF); -SDR 16 TDI (FFFF) TDO (7FF7); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (AFBE); -SDR 16 TDI (FFFF) TDO (EFF7); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BF7F); -SDR 16 TDI (FFFF) TDO (FF5F); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (EEFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (7F7F); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFD); -SDR 16 TDI (FFFF) TDO (FFF5); -SDR 16 TDI (FFFF) TDO (7DE0); -SDR 16 TDI (FFFF) TDO (13F6); -SDR 16 TDI (FFFF) TDO (AEFD); -SDR 16 TDI (FFFF) TDO (4FFF); -SDR 16 TDI (FFFF) TDO (6C97); -SDR 16 TDI (FFFF) TDO (B3EF); -SDR 16 TDI (FFFF) TDO (A77F); -SDR 16 TDI (FFFF) TDO (F9F9); -SDR 16 TDI (FFFF) TDO (7676); -SDR 16 TDI (FFFF) TDO (FE6F); -SDR 16 TDI (FFFF) TDO (BBE9); -SDR 16 TDI (FFFF) TDO (33FF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BDFE); -SDR 16 TDI (FFFF) TDO (FEDF); -SDR 16 TDI (FFFF) TDO (6FFF); -SDR 16 TDI (FFFF) TDO (FFFD); -SDR 16 TDI (FFFF) TDO (B5F2); -SDR 16 TDI (FFFF) TDO (FFFC); -SDR 16 TDI (FFFF) TDO (7F7B); -SDR 16 TDI (FFFF) TDO (DEDA); -SDR 16 TDI (FFFF) TDO (BCFF); -SDR 16 TDI (FFFF) TDO (F7EF); -SDR 16 TDI (FFFF) TDO (7FCF); -SDR 16 TDI (FFFF) TDO (DFFB); -SDR 16 TDI (FFFF) TDO (BFF7); -SDR 16 TDI (FFFF) TDO (CD6A); -SDR 16 TDI (FFFF) TDO (77FF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (677F); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FF5F); -SDR 16 TDI (FFFF) TDO (BF2F); -SDR 16 TDI (FFFF) TDO (F7F3); -SDR 16 TDI (FFFF) TDO (73FD); -SDR 16 TDI (FFFF) TDO (7FFD); -SDR 16 TDI (FFFF) TDO (BF9E); -SDR 16 TDI (FFFF) TDO (CE1E); -SDR 16 TDI (FFFF) TDO (69BB); -SDR 16 TDI (FFFF) TDO (2F9F); -SDR 16 TDI (FFFF) TDO (BC9F); SDR 16 TDI (FFFF) TDO (FEFF); SDR 16 TDI (FFFF) TDO (7FFF); SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BBAD); -SDR 16 TDI (FFFF) TDO (69FC); -SDR 16 TDI (FFFF) TDO (67C2); -SDR 16 TDI (FFFF) TDO (0B9E); -SDR 16 TDI (FFFF) TDO (A130); -SDR 16 TDI (FFFF) TDO (EFEF); -SDR 16 TDI (FFFF) TDO (7404); -SDR 16 TDI (FFFF) TDO (BC00); -SDR 16 TDI (FFFF) TDO (B17F); -SDR 16 TDI (FFFF) TDO (0100); -SDR 16 TDI (FFFF) TDO (6888); -SDR 16 TDI (FFFF) TDO (5C1F); -SDR 16 TDI (FFFF) TDO (B768); -SDR 16 TDI (FFFF) TDO (0075); -SDR 16 TDI (FFFF) TDO (6BFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFE); +SDR 16 TDI (FFFF) TDO (6FFF); SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BF5E); -SDR 16 TDI (FFFF) TDO (E9C3); -SDR 16 TDI (FFFF) TDO (67A0); -SDR 16 TDI (FFFF) TDO (0BE0); -SDR 16 TDI (FFFF) TDO (A3F0); -SDR 16 TDI (FFFF) TDO (8FDE); -SDR 16 TDI (FFFF) TDO (78A7); -SDR 16 TDI (FFFF) TDO (BA00); -SDR 16 TDI (FFFF) TDO (A11E); -SDR 16 TDI (FFFF) TDO (8002); -SDR 16 TDI (FFFF) TDO (6000); -SDR 16 TDI (FFFF) TDO (5C2F); -SDR 16 TDI (FFFF) TDO (AF08); -SDR 16 TDI (FFFF) TDO (10FF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (F7FF); SDR 16 TDI (FFFF) TDO (7FFF); SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (B5FD); -SDR 16 TDI (FFFF) TDO (9283); -SDR 16 TDI (FFFF) TDO (7FE0); -SDR 16 TDI (FFFF) TDO (4C61); -SDR 16 TDI (FFFF) TDO (A538); -SDR 16 TDI (FFFF) TDO (EFF3); -SDR 16 TDI (FFFF) TDO (6066); -SDR 16 TDI (FFFF) TDO (1CC8); -SDR 16 TDI (FFFF) TDO (B19F); -SDR 16 TDI (FFFF) TDO (C208); -SDR 16 TDI (FFFF) TDO (6078); -SDR 16 TDI (FFFF) TDO (BC6F); -SDR 16 TDI (FFFF) TDO (BF99); -SDR 16 TDI (FFFF) TDO (F875); -SDR 16 TDI (FFFF) TDO (6BFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7DDF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FBF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BDFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (6FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BDFE); -SDR 16 TDI (FFFF) TDO (D2B0); -SDR 16 TDI (FFFF) TDO (67E0); -SDR 16 TDI (FFFF) TDO (0D86); -SDR 16 TDI (FFFF) TDO (A338); -SDR 16 TDI (FFFF) TDO (2FFC); -SDR 16 TDI (FFFF) TDO (6126); -SDR 16 TDI (FFFF) TDO (19C8); -SDR 16 TDI (FFFF) TDO (A19F); -SDR 16 TDI (FFFF) TDO (E00A); -SDR 16 TDI (FFFF) TDO (70F0); -SDR 16 TDI (FFFF) TDO (9C1F); -SDR 16 TDI (FFFF) TDO (BF98); -SDR 16 TDI (FFFF) TDO (787F); SDR 16 TDI (FFFF) TDO (7FFF); SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BA3F); -SDR 16 TDI (FFFF) TDO (BBBB); -SDR 16 TDI (FFFF) TDO (71E6); -SDR 16 TDI (FFFF) TDO (6EEF); -SDR 16 TDI (FFFF) TDO (B333); -SDR 16 TDI (FFFF) TDO (75F3); -SDR 16 TDI (FFFF) TDO (6E7F); -SDR 16 TDI (FFFF) TDO (7EE8); -SDR 16 TDI (FFFF) TDO (B9CF); -SDR 16 TDI (FFFF) TDO (D98B); -SDR 16 TDI (FFFF) TDO (71E8); -SDR 16 TDI (FFFF) TDO (8E83); -SDR 16 TDI (FFFF) TDO (B998); -SDR 16 TDI (FFFF) TDO (89FA); -SDR 16 TDI (FFFF) TDO (77FF); +SDR 16 TDI (FFFF) TDO (BEF7); SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BD7F); -SDR 16 TDI (FFFF) TDO (1111); -SDR 16 TDI (FFFF) TDO (6177); -SDR 16 TDI (FFFF) TDO (2445); -SDR 16 TDI (FFFF) TDO (B777); -SDR 16 TDI (FFFF) TDO (74AB); -SDR 16 TDI (FFFF) TDO (6767); -SDR 16 TDI (FFFF) TDO (7CCD); -SDR 16 TDI (FFFF) TDO (BB85); -SDR 16 TDI (FFFF) TDO (5DD9); -SDR 16 TDI (FFFF) TDO (7BCD); -SDR 16 TDI (FFFF) TDO (DCD2); -SDR 16 TDI (FFFF) TDO (B5DD); -SDR 16 TDI (FFFF) TDO (D9FF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BF7F); +SDR 16 TDI (FFFF) TDO (FFDF); SDR 16 TDI (FFFF) TDO (7FFF); SDR 16 TDI (FFFF) TDO (FFFF); SDR 16 TDI (FFFF) TDO (BFFD); -SDR 16 TDI (FFFF) TDO (DDDD); -SDR 16 TDI (FFFF) TDO (7FCF); -SDR 16 TDI (FFFF) TDO (FDDD); -SDR 16 TDI (FFFF) TDO (BBBB); -SDR 16 TDI (FFFF) TDO (FFE7); -SDR 16 TDI (FFFF) TDO (7EFF); -SDR 16 TDI (FFFF) TDO (F7FF); -SDR 16 TDI (FFFF) TDO (BCEF); -SDR 16 TDI (FFFF) TDO (3FFF); +SDR 16 TDI (FFFF) TDO (FFFE); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFF7); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFDF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFB); +SDR 16 TDI (FFFF) TDO (EFFF); +SDR 16 TDI (FFFF) TDO (BFBF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (DFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFF); SDR 16 TDI (FFFF) TDO (77FF); -SDR 16 TDI (FFFF) TDO (E7FF); +SDR 16 TDI (FFFF) TDO (FF7E); +SDR 16 TDI (FFFF) TDO (BF7F); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (A7FF); +SDR 16 TDI (FFFF) TDO (B7FF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7B7B); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BDF7); +SDR 16 TDI (FFFF) TDO (DDFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFE); +SDR 16 TDI (FFFF) TDO (FEFF); +SDR 16 TDI (FFFF) TDO (7FEE); +SDR 16 TDI (FFFF) TDO (FFFB); +SDR 16 TDI (FFFF) TDO (BBFE); +SDR 16 TDI (FFFF) TDO (FFF7); +SDR 16 TDI (FFFF) TDO (6FBF); +SDR 16 TDI (FFFF) TDO (E7AF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (AFFF); +SDR 16 TDI (FFFF) TDO (7DFF); +SDR 16 TDI (FFFF) TDO (DFBF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (DFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFB); +SDR 16 TDI (FFFF) TDO (6FFF); +SDR 16 TDI (FFFF) TDO (FF7F); +SDR 16 TDI (FFFF) TDO (AFAF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (7FFD); +SDR 16 TDI (FFFF) TDO (DFFF); +SDR 16 TDI (FFFF) TDO (AFBF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (77B7); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BBEF); +SDR 16 TDI (FFFF) TDO (FBFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (7F7F); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BDFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (EFFB); +SDR 16 TDI (FFFF) TDO (BDFF); +SDR 16 TDI (FFFF) TDO (FFFE); +SDR 16 TDI (FFFF) TDO (7DFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (BFFB); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFE); +SDR 16 TDI (FFFF) TDO (EFFF); +SDR 16 TDI (FFFF) TDO (7FEF); +SDR 16 TDI (FFFF) TDO (FFFD); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFF7); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (DFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FEFF); +SDR 16 TDI (FFFF) TDO (BBFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFD); +SDR 16 TDI (FFFF) TDO (DFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFD); +SDR 16 TDI (FFFF) TDO (BDFF); +SDR 16 TDI (FFFF) TDO (FFF7); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (DFBF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (6FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BBFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (7FBF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (EFFB); +SDR 16 TDI (FFFF) TDO (BBFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7DFF); +SDR 16 TDI (FFFF) TDO (BEFF); +SDR 16 TDI (FFFF) TDO (BFFD); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (B55F); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (6FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BBFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (F9AA); +SDR 16 TDI (FFFF) TDO (B3FF); +SDR 16 TDI (FFFF) TDO (FFFA); +SDR 16 TDI (FFFF) TDO (75FF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BBBF); +SDR 16 TDI (FFFF) TDO (FFF5); +SDR 16 TDI (FFFF) TDO (69FF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FDFF); +SDR 16 TDI (FFFF) TDO (7FFD); +SDR 16 TDI (FFFF) TDO (FFBF); +SDR 16 TDI (FFFF) TDO (AF6B); +SDR 16 TDI (FFFF) TDO (EF7F); +SDR 16 TDI (FFFF) TDO (7FFB); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (BFBF); +SDR 16 TDI (FFFF) TDO (B7EF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFEF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7DFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (B55F); +SDR 16 TDI (FFFF) TDO (FF7F); +SDR 16 TDI (FFFF) TDO (7FF7); +SDR 16 TDI (FFFF) TDO (FF77); +SDR 16 TDI (FFFF) TDO (AFDF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (7FBF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFD); +SDR 16 TDI (FFFF) TDO (FDBF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (DDFF); +SDR 16 TDI (FFFF) TDO (BFFD); +SDR 16 TDI (FFFF) TDO (DDF5); +SDR 16 TDI (FFFF) TDO (69FF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BAAF); +SDR 16 TDI (FFFF) TDO (FDFF); +SDR 16 TDI (FFFF) TDO (7FFD); +SDR 16 TDI (FFFF) TDO (FFDD); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFBB); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFE); +SDR 16 TDI (FFFF) TDO (7DFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFBF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7DFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFBB); +SDR 16 TDI (FFFF) TDO (EFFD); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFDD); +SDR 16 TDI (FFFF) TDO (BFDF); +SDR 16 TDI (FFFF) TDO (CFEF); +SDR 16 TDI (FFFF) TDO (7BFF); +SDR 16 TDI (FFFF) TDO (BBAF); +SDR 16 TDI (FFFF) TDO (BDFE); +SDR 16 TDI (FFFF) TDO (FEFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFD); +SDR 16 TDI (FFFF) TDO (7F7F); +SDR 16 TDI (FFFF) TDO (77FF); +SDR 16 TDI (FFFF) TDO (3F73); +SDR 16 TDI (FFFF) TDO (BBFE); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7BFF); +SDR 16 TDI (FFFF) TDO (FDFF); +SDR 16 TDI (FFFF) TDO (BBFF); +SDR 16 TDI (FFFF) TDO (FFBF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (D9BD); +SDR 16 TDI (FFFF) TDO (AFFC); +SDR 16 TDI (FFFF) TDO (ECFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FCFF); +SDR 16 TDI (FFFF) TDO (77FD); +SDR 16 TDI (FFFF) TDO (FF13); +SDR 16 TDI (FFFF) TDO (AB5B); +SDR 16 TDI (FFFF) TDO (9F7D); +SDR 16 TDI (FFFF) TDO (7FBF); +SDR 16 TDI (FFFF) TDO (F4DD); +SDR 16 TDI (FFFF) TDO (A99F); +SDR 16 TDI (FFFF) TDO (E7F7); +SDR 16 TDI (FFFF) TDO (6BFF); +SDR 16 TDI (FFFF) TDO (FFBF); +SDR 16 TDI (FFFF) TDO (BDDF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (B9BF); +SDR 16 TDI (FFFF) TDO (BF3F); +SDR 16 TDI (FFFF) TDO (6FF2); +SDR 16 TDI (FFFF) TDO (FEEE); +SDR 16 TDI (FFFF) TDO (BFEF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (DFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FD8F); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (B3EF); +SDR 16 TDI (FFFF) TDO (BBFE); +SDR 16 TDI (FFFF) TDO (767F); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFD); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (DFFD); +SDR 16 TDI (FFFF) TDO (B7B5); +SDR 16 TDI (FFFF) TDO (6FFF); +SDR 16 TDI (FFFF) TDO (7DFD); +SDR 16 TDI (FFFF) TDO (FF22); +SDR 16 TDI (FFFF) TDO (BFFB); +SDR 16 TDI (FFFF) TDO (9FFC); +SDR 16 TDI (FFFF) TDO (74FF); +SDR 16 TDI (FFFF) TDO (CC5E); +SDR 16 TDI (FFFF) TDO (B7B9); +SDR 16 TDI (FFFF) TDO (D9FF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (B76C); +SDR 16 TDI (FFFF) TDO (FEFF); +SDR 16 TDI (FFFF) TDO (7FDF); +SDR 16 TDI (FFFF) TDO (9E80); +SDR 16 TDI (FFFF) TDO (A700); +SDR 16 TDI (FFFF) TDO (1BE9); +SDR 16 TDI (FFFF) TDO (78B9); +SDR 16 TDI (FFFF) TDO (F00F); +SDR 16 TDI (FFFF) TDO (A1FF); +SDR 16 TDI (FFFF) TDO (2800); +SDR 16 TDI (FFFF) TDO (60FF); +SDR 16 TDI (FFFF) TDO (AF8F); +SDR 16 TDI (FFFF) TDO (A004); +SDR 16 TDI (FFFF) TDO (7875); +SDR 16 TDI (FFFF) TDO (69FF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BEDC); +SDR 16 TDI (FFFF) TDO (3FFF); +SDR 16 TDI (FFFF) TDO (7FAA); +SDR 16 TDI (FFFF) TDO (7EA0); +SDR 16 TDI (FFFF) TDO (A300); +SDR 16 TDI (FFFF) TDO (23F9); +SDR 16 TDI (FFFF) TDO (7EBE); +SDR 16 TDI (FFFF) TDO (102D); +SDR 16 TDI (FFFF) TDO (A1FF); +SDR 16 TDI (FFFF) TDO (A858); +SDR 16 TDI (FFFF) TDO (60FF); +SDR 16 TDI (FFFF) TDO (A08D); +SDR 16 TDI (FFFF) TDO (B800); +SDR 16 TDI (FFFF) TDO (007F); +SDR 16 TDI (FFFF) TDO (7DFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (B77C); +SDR 16 TDI (FFFF) TDO (FCFC); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (9E00); +SDR 16 TDI (FFFF) TDO (A0E3); +SDR 16 TDI (FFFF) TDO (17FE); +SDR 16 TDI (FFFF) TDO (6646); +SDR 16 TDI (FFFF) TDO (1C06); +SDR 16 TDI (FFFF) TDO (A19F); +SDR 16 TDI (FFFF) TDO (D804); +SDR 16 TDI (FFFF) TDO (78FF); +SDR 16 TDI (FFFF) TDO (57BF); +SDR 16 TDI (FFFF) TDO (B998); +SDR 16 TDI (FFFF) TDO (00F5); +SDR 16 TDI (FFFF) TDO (6BFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFEC); +SDR 16 TDI (FFFF) TDO (3CFC); +SDR 16 TDI (FFFF) TDO (7FFE); +SDR 16 TDI (FFFF) TDO (7E04); +SDR 16 TDI (FFFF) TDO (A0C0); +SDR 16 TDI (FFFF) TDO (23FE); +SDR 16 TDI (FFFF) TDO (7858); +SDR 16 TDI (FFFF) TDO (700F); +SDR 16 TDI (FFFF) TDO (B99F); +SDR 16 TDI (FFFF) TDO (C878); +SDR 16 TDI (FFFF) TDO (60FF); +SDR 16 TDI (FFFF) TDO (588F); +SDR 16 TDI (FFFF) TDO (B998); +SDR 16 TDI (FFFF) TDO (787F); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (B8AF); +SDR 16 TDI (FFFF) TDO (33B3); +SDR 16 TDI (FFFF) TDO (63EE); +SDR 16 TDI (FFFF) TDO (E6E7); +SDR 16 TDI (FFFF) TDO (A323); +SDR 16 TDI (FFFF) TDO (39F7); +SDR 16 TDI (FFFF) TDO (6EEE); +SDR 16 TDI (FFFF) TDO (FEEC); +SDR 16 TDI (FFFF) TDO (BD8F); +SDR 16 TDI (FFFF) TDO (9989); +SDR 16 TDI (FFFF) TDO (77CC); +SDR 16 TDI (FFFF) TDO (CCE7); +SDR 16 TDI (FFFF) TDO (B999); +SDR 16 TDI (FFFF) TDO (99FF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BEFE); +SDR 16 TDI (FFFF) TDO (7737); +SDR 16 TDI (FFFF) TDO (6946); +SDR 16 TDI (FFFF) TDO (7673); +SDR 16 TDI (FFFF) TDO (B736); +SDR 16 TDI (FFFF) TDO (70A2); +SDR 16 TDI (FFFF) TDO (6444); +SDR 16 TDI (FFFF) TDO (5CCD); +SDR 16 TDI (FFFF) TDO (B9B5); +SDR 16 TDI (FFFF) TDO (19DD); +SDR 16 TDI (FFFF) TDO (73DD); +SDR 16 TDI (FFFF) TDO (CCC2); +SDR 16 TDI (FFFF) TDO (B5DC); +SDR 16 TDI (FFFF) TDO (DCFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFEF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (77DF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFEF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FEFE); +SDR 16 TDI (FFFF) TDO (BDDF); +SDR 16 TDI (FFFF) TDO (7F3B); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FF73); SDR 16 TDI (FFFF) TDO (B3BF); SDR 16 TDI (FFFF) TDO (BFFF); SDR 16 TDI (FFFF) TDO (7FFF); SDR 16 TDI (FFFF) TDO (FFFF); SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (BF7D); -SDR 16 TDI (FFFF) TDO (7FEF); -SDR 16 TDI (FFFF) TDO (FDFF); -SDR 16 TDI (FFFF) TDO (BFFE); -SDR 16 TDI (FFFF) TDO (DFFF); -SDR 16 TDI (FFFF) TDO (6DFF); -SDR 16 TDI (FFFF) TDO (F7DB); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (CDDB); -SDR 16 TDI (FFFF) TDO (7F67); -SDR 16 TDI (FFFF) TDO (DBFF); -SDR 16 TDI (FFFF) TDO (BEFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BDFF); -SDR 16 TDI (FFFF) TDO (EFFF); -SDR 16 TDI (FFFF) TDO (7FFB); -SDR 16 TDI (FFFF) TDO (F77B); -SDR 16 TDI (FFFF) TDO (B5DF); -SDR 16 TDI (FFFF) TDO (FFF6); -SDR 16 TDI (FFFF) TDO (7FDE); -SDR 16 TDI (FFFF) TDO (FDFF); -SDR 16 TDI (FFFF) TDO (BFDF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7BFD); -SDR 16 TDI (FFFF) TDO (FF6F); -SDR 16 TDI (FFFF) TDO (BDDF); -SDR 16 TDI (FFFF) TDO (FDFD); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (B5DD); -SDR 16 TDI (FFFF) TDO (EFFF); -SDR 16 TDI (FFFF) TDO (73BF); -SDR 16 TDI (FFFF) TDO (F7FF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (DBFF); -SDR 16 TDI (FFFF) TDO (7F7E); -SDR 16 TDI (FFFF) TDO (FF7F); -SDR 16 TDI (FFFF) TDO (BBFF); -SDR 16 TDI (FFFF) TDO (FDFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BBFF); -SDR 16 TDI (FFFF) TDO (FF7E); -SDR 16 TDI (FFFF) TDO (7FF7); -SDR 16 TDI (FFFF) TDO (F57F); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFFE); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FDE7); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (EFDB); -SDR 16 TDI (FFFF) TDO (7BE7); -SDR 16 TDI (FFFF) TDO (D7FF); -SDR 16 TDI (FFFF) TDO (BEDF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFB); -SDR 16 TDI (FFFF) TDO (F7FB); -SDR 16 TDI (FFFF) TDO (7FFB); -SDR 16 TDI (FFFF) TDO (FFDF); -SDR 16 TDI (FFFF) TDO (B77F); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7FFB); -SDR 16 TDI (FFFF) TDO (FF7F); -SDR 16 TDI (FFFF) TDO (BDFF); -SDR 16 TDI (FFFF) TDO (DD37); -SDR 16 TDI (FFFF) TDO (7DF5); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFDF); -SDR 16 TDI (FFFF) TDO (7FEF); -SDR 16 TDI (FFFF) TDO (77FF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFD); -SDR 16 TDI (FFFF) TDO (7DEF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFB); -SDR 16 TDI (FFFF) TDO (FBFB); -SDR 16 TDI (FFFF) TDO (7F3F); -SDR 16 TDI (FFFF) TDO (AFF7); -SDR 16 TDI (FFFF) TDO (B7FF); -SDR 16 TDI (FFFF) TDO (F7FF); -SDR 16 TDI (FFFF) TDO (6FFF); -SDR 16 TDI (FFFF) TDO (FFBF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (DFFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFDD); -SDR 16 TDI (FFFF) TDO (77D7); -SDR 16 TDI (FFFF) TDO (77FD); -SDR 16 TDI (FFFF) TDO (EFDF); -SDR 16 TDI (FFFF) TDO (AFFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (6BEF); -SDR 16 TDI (FFFF) TDO (FBFF); -SDR 16 TDI (FFFF) TDO (AFDF); -SDR 16 TDI (FFFF) TDO (FFF3); -SDR 16 TDI (FFFF) TDO (67FF); -SDR 16 TDI (FFFF) TDO (FEEF); -SDR 16 TDI (FFFF) TDO (BFEF); -SDR 16 TDI (FFFF) TDO (DBFD); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FDFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (B7B7); -SDR 16 TDI (FFFF) TDO (FBF7); -SDR 16 TDI (FFFF) TDO (7EDB); -SDR 16 TDI (FFFF) TDO (DF77); -SDR 16 TDI (FFFF) TDO (BDFF); -SDR 16 TDI (FFFF) TDO (CB5F); -SDR 16 TDI (FFFF) TDO (7EF5); -SDR 16 TDI (FFFF) TDO (FFBF); -SDR 16 TDI (FFFF) TDO (BFBF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BDFF); -SDR 16 TDI (FFFF) TDO (F9FB); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FBFF); -SDR 16 TDI (FFFF) TDO (BA7F); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (6DEC); -SDR 16 TDI (FFFF) TDO (EDE7); -SDR 16 TDI (FFFF) TDO (B5FF); -SDR 16 TDI (FFFF) TDO (FBFB); -SDR 16 TDI (FFFF) TDO (7B9F); -SDR 16 TDI (FFFF) TDO (7BFF); -SDR 16 TDI (FFFF) TDO (BFF6); -SDR 16 TDI (FFFF) TDO (FF7F); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BF7F); -SDR 16 TDI (FFFF) TDO (FFBF); -SDR 16 TDI (FFFF) TDO (7FEE); -SDR 16 TDI (FFFF) TDO (BEFD); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFF7); -SDR 16 TDI (FFFF) TDO (7F7F); -SDR 16 TDI (FFFF) TDO (BB7F); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (BF77); -SDR 16 TDI (FFFF) TDO (6EF7); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BBBF); -SDR 16 TDI (FFFF) TDO (EFFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BDFF); -SDR 16 TDI (FFFF) TDO (F7FF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FF7F); -SDR 16 TDI (FFFF) TDO (B7EF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7DF7); -SDR 16 TDI (FFFF) TDO (FFFE); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (BFB7); -SDR 16 TDI (FFFF) TDO (7BF6); -SDR 16 TDI (FFFF) TDO (EFFF); -SDR 16 TDI (FFFF) TDO (BFFB); -SDR 16 TDI (FFFF) TDO (B7FF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BF7F); -SDR 16 TDI (FFFF) TDO (FEBB); -SDR 16 TDI (FFFF) TDO (77FE); -SDR 16 TDI (FFFF) TDO (DBFB); -SDR 16 TDI (FFFF) TDO (BD7F); -SDR 16 TDI (FFFF) TDO (FBFF); -SDR 16 TDI (FFFF) TDO (6EFB); -SDR 16 TDI (FFFF) TDO (55AB); -SDR 16 TDI (FFFF) TDO (B3FF); -SDR 16 TDI (FFFF) TDO (FB7A); -SDR 16 TDI (FFFF) TDO (7D6F); -SDR 16 TDI (FFFF) TDO (77FF); -SDR 16 TDI (FFFF) TDO (BFB6); -SDR 16 TDI (FFFF) TDO (FF7F); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BDAD); -SDR 16 TDI (FFFF) TDO (F7FF); -SDR 16 TDI (FFFF) TDO (6FFE); -SDR 16 TDI (FFFF) TDO (EFFF); -SDR 16 TDI (FFFF) TDO (BFD9); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7DFC); -SDR 16 TDI (FFFF) TDO (FFB9); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFBF); -SDR 16 TDI (FFFF) TDO (6E77); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFB); -SDR 16 TDI (FFFF) TDO (BEF5); -SDR 16 TDI (FFFF) TDO (6BFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BBFF); -SDR 16 TDI (FFFF) TDO (7FFE); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FF33); -SDR 16 TDI (FFFF) TDO (B5FF); -SDR 16 TDI (FFFF) TDO (FFFD); -SDR 16 TDI (FFFF) TDO (7EDF); -SDR 16 TDI (FFFF) TDO (B5FF); -SDR 16 TDI (FFFF) TDO (BBBF); -SDR 16 TDI (FFFF) TDO (F5FF); -SDR 16 TDI (FFFF) TDO (7FFE); -SDR 16 TDI (FFFF) TDO (7EDF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (7DFF); -SDR 16 TDI (FFFF) TDO (7DFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (B65E); -SDR 16 TDI (FFFF) TDO (FF7B); -SDR 16 TDI (FFFF) TDO (7FEF); -SDR 16 TDI (FFFF) TDO (FBFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (E7FA); -SDR 16 TDI (FFFF) TDO (73AF); -SDR 16 TDI (FFFF) TDO (FFDF); -SDR 16 TDI (FFFF) TDO (BFFB); -SDR 16 TDI (FFFF) TDO (3FFD); -SDR 16 TDI (FFFF) TDO (7BEB); -SDR 16 TDI (FFFF) TDO (6BFF); -SDR 16 TDI (FFFF) TDO (BDDF); -SDR 16 TDI (FFFF) TDO (F7F5); -SDR 16 TDI (FFFF) TDO (6BFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7FFB); -SDR 16 TDI (FFFF) TDO (DFFF); -SDR 16 TDI (FFFF) TDO (AFFF); -SDR 16 TDI (FFFF) TDO (FFDF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (B76B); -SDR 16 TDI (FFFF) TDO (BF7F); -SDR 16 TDI (FFFF) TDO (FEFE); -SDR 16 TDI (FFFF) TDO (757F); -SDR 16 TDI (FFFF) TDO (DFFF); -SDR 16 TDI (FFFF) TDO (BFF3); -SDR 16 TDI (FFFF) TDO (7B6A); -SDR 16 TDI (FFFF) TDO (75FF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (EEFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (B99D); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7775); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (AFFF); -SDR 16 TDI (FFFF) TDO (F7DF); -SDR 16 TDI (FFFF) TDO (7FEF); -SDR 16 TDI (FFFF) TDO (FD6F); -SDR 16 TDI (FFFF) TDO (AEFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFEF); -SDR 16 TDI (FFFF) TDO (7DED); -SDR 16 TDI (FFFF) TDO (DFFF); -SDR 16 TDI (FFFF) TDO (AFFB); -SDR 16 TDI (FFFF) TDO (5BFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (7EFF); -SDR 16 TDI (FFFF) TDO (AABF); -SDR 16 TDI (FFFF) TDO (FCFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (F7BF); -SDR 16 TDI (FFFF) TDO (BF7F); -SDR 16 TDI (FFFF) TDO (EFFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FF75); -SDR 16 TDI (FFFF) TDO (6DEC); -SDR 16 TDI (FFFF) TDO (B3F6); -SDR 16 TDI (FFFF) TDO (A7D3); -SDR 16 TDI (FFFF) TDO (AFFF); -SDR 16 TDI (FFFF) TDO (7FB1); -SDR 16 TDI (FFFF) TDO (93C1); -SDR 16 TDI (FFFF) TDO (BFFE); -SDR 16 TDI (FFFF) TDO (FF3E); -SDR 16 TDI (FFFF) TDO (73C3); -SDR 16 TDI (FFFF) TDO (3FBF); -SDR 16 TDI (FFFF) TDO (BFFE); -SDR 16 TDI (FFFF) TDO (5BFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (B3FC); -SDR 16 TDI (FFFF) TDO (7EDF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFD); -SDR 16 TDI (FFFF) TDO (BFEF); -SDR 16 TDI (FFFF) TDO (D7FC); -SDR 16 TDI (FFFF) TDO (73FF); -SDR 16 TDI (FFFF) TDO (FC3F); -SDR 16 TDI (FFFF) TDO (BEFF); -SDR 16 TDI (FFFF) TDO (E6FD); -SDR 16 TDI (FFFF) TDO (7EFD); -SDR 16 TDI (FFFF) TDO (E6EF); -SDR 16 TDI (FFFF) TDO (BCE9); -SDR 16 TDI (FFFF) TDO (BCEA); -SDR 16 TDI (FFFF) TDO (77FF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (E7FF); -SDR 16 TDI (FFFF) TDO (7FF3); -SDR 16 TDI (FFFF) TDO (5F5F); -SDR 16 TDI (FFFF) TDO (B8BC); -SDR 16 TDI (FFFF) TDO (FBEB); -SDR 16 TDI (FFFF) TDO (6C4E); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (A11B); -SDR 16 TDI (FFFF) TDO (D9DF); -SDR 16 TDI (FFFF) TDO (6D3F); -SDR 16 TDI (FFFF) TDO (D95F); -SDR 16 TDI (FFFF) TDO (B75F); -SDR 16 TDI (FFFF) TDO (E77F); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BE5D); -SDR 16 TDI (FFFF) TDO (69FC); -SDR 16 TDI (FFFF) TDO (67C0); -SDR 16 TDI (FFFF) TDO (0B9E); -SDR 16 TDI (FFFF) TDO (A320); -SDR 16 TDI (FFFF) TDO (03C0); -SDR 16 TDI (FFFF) TDO (60A2); -SDR 16 TDI (FFFF) TDO (5E39); -SDR 16 TDI (FFFF) TDO (B997); -SDR 16 TDI (FFFF) TDO (6084); -SDR 16 TDI (FFFF) TDO (7CB5); -SDR 16 TDI (FFFF) TDO (F48F); -SDR 16 TDI (FFFF) TDO (A49F); -SDR 16 TDI (FFFF) TDO (E3F5); -SDR 16 TDI (FFFF) TDO (6BFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BAFE); -SDR 16 TDI (FFFF) TDO (E9C3); -SDR 16 TDI (FFFF) TDO (67A0); -SDR 16 TDI (FFFF) TDO (0BE0); -SDR 16 TDI (FFFF) TDO (A382); -SDR 16 TDI (FFFF) TDO (03D0); -SDR 16 TDI (FFFF) TDO (62E0); -SDR 16 TDI (FFFF) TDO (1201); -SDR 16 TDI (FFFF) TDO (A01F); -SDR 16 TDI (FFFF) TDO (8884); -SDR 16 TDI (FFFF) TDO (6080); -SDR 16 TDI (FFFF) TDO (F43F); -SDR 16 TDI (FFFF) TDO (AC1E); -SDR 16 TDI (FFFF) TDO (897F); -SDR 16 TDI (FFFF) TDO (7DFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BF6D); -SDR 16 TDI (FFFF) TDO (9283); -SDR 16 TDI (FFFF) TDO (7FF0); -SDR 16 TDI (FFFF) TDO (0C61); -SDR 16 TDI (FFFF) TDO (A32C); -SDR 16 TDI (FFFF) TDO (23F9); -SDR 16 TDI (FFFF) TDO (6000); -SDR 16 TDI (FFFF) TDO (7CDB); -SDR 16 TDI (FFFF) TDO (B77F); -SDR 16 TDI (FFFF) TDO (E7E6); -SDR 16 TDI (FFFF) TDO (7BCF); -SDR 16 TDI (FFFF) TDO (0F8F); -SDR 16 TDI (FFFF) TDO (BEBF); -SDR 16 TDI (FFFF) TDO (F975); -SDR 16 TDI (FFFF) TDO (6BFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFDE); -SDR 16 TDI (FFFF) TDO (D2B0); -SDR 16 TDI (FFFF) TDO (67F6); -SDR 16 TDI (FFFF) TDO (4D86); -SDR 16 TDI (FFFF) TDO (A37E); -SDR 16 TDI (FFFF) TDO (33F0); -SDR 16 TDI (FFFF) TDO (6000); -SDR 16 TDI (FFFF) TDO (7CD3); -SDR 16 TDI (FFFF) TDO (B77F); -SDR 16 TDI (FFFF) TDO (EE66); -SDR 16 TDI (FFFF) TDO (6BC9); -SDR 16 TDI (FFFF) TDO (49FF); -SDR 16 TDI (FFFF) TDO (BE3C); -SDR 16 TDI (FFFF) TDO (897F); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BE27); -SDR 16 TDI (FFFF) TDO (BBBB); -SDR 16 TDI (FFFF) TDO (71EE); -SDR 16 TDI (FFFF) TDO (6EEF); -SDR 16 TDI (FFFF) TDO (A3BB); -SDR 16 TDI (FFFF) TDO (B1F3); -SDR 16 TDI (FFFF) TDO (66E6); -SDR 16 TDI (FFFF) TDO (7CCF); -SDR 16 TDI (FFFF) TDO (B98F); -SDR 16 TDI (FFFF) TDO (D99F); -SDR 16 TDI (FFFF) TDO (73EE); -SDR 16 TDI (FFFF) TDO (8EC7); -SDR 16 TDI (FFFF) TDO (BDD9); -SDR 16 TDI (FFFF) TDO (99EB); -SDR 16 TDI (FFFF) TDO (77FF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BF77); -SDR 16 TDI (FFFF) TDO (1111); -SDR 16 TDI (FFFF) TDO (6167); -SDR 16 TDI (FFFF) TDO (6445); -SDR 16 TDI (FFFF) TDO (A777); -SDR 16 TDI (FFFF) TDO (74A9); -SDR 16 TDI (FFFF) TDO (7277); -SDR 16 TDI (FFFF) TDO (3CDC); -SDR 16 TDI (FFFF) TDO (BB25); -SDR 16 TDI (FFFF) TDO (1DD9); -SDR 16 TDI (FFFF) TDO (7BCC); -SDR 16 TDI (FFFF) TDO (DC92); -SDR 16 TDI (FFFF) TDO (B5CC); -SDR 16 TDI (FFFF) TDO (DDFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFDD); -SDR 16 TDI (FFFF) TDO (DDDD); -SDR 16 TDI (FFFF) TDO (7FDE); -SDR 16 TDI (FFFF) TDO (FDDD); -SDR 16 TDI (FFFF) TDO (BBFF); -SDR 16 TDI (FFFF) TDO (F8FF); -SDR 16 TDI (FFFF) TDO (6FCE); -SDR 16 TDI (FFFF) TDO (F7FF); -SDR 16 TDI (FFFF) TDO (BDEF); -SDR 16 TDI (FFFF) TDO (77BF); -SDR 16 TDI (FFFF) TDO (7F77); -SDR 16 TDI (FFFF) TDO (E7F7); -SDR 16 TDI (FFFF) TDO (B3BB); -SDR 16 TDI (FFFF) TDO (BBFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (BAEE); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (BEDF); -SDR 16 TDI (FFFF) TDO (B7EF); -SDR 16 TDI (FFFF) TDO (F7FF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FEFF); -SDR 16 TDI (FFFF) TDO (BBFF); -SDR 16 TDI (FFFF) TDO (DF6D); -SDR 16 TDI (FFFF) TDO (6B5F); -SDR 16 TDI (FFFF) TDO (DFFF); -SDR 16 TDI (FFFF) TDO (BBDE); -SDR 16 TDI (FFFF) TDO (EFFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FF77); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (F7FD); -SDR 16 TDI (FFFF) TDO (BE7D); -SDR 16 TDI (FFFF) TDO (EFFB); -SDR 16 TDI (FFFF) TDO (76EB); -SDR 16 TDI (FFFF) TDO (F7DE); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (EBDF); -SDR 16 TDI (FFFF) TDO (7FFB); -SDR 16 TDI (FFFF) TDO (BBDF); -SDR 16 TDI (FFFF) TDO (BF7B); -SDR 16 TDI (FFFF) TDO (BDFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (AFFF); -SDR 16 TDI (FFFF) TDO (76E5); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFD); -SDR 16 TDI (FFFF) TDO (B7DE); -SDR 16 TDI (FFFF) TDO (FFF7); -SDR 16 TDI (FFFF) TDO (77FF); -SDR 16 TDI (FFFF) TDO (FFDF); -SDR 16 TDI (FFFF) TDO (BBFF); -SDR 16 TDI (FFFF) TDO (FFF5); -SDR 16 TDI (FFFF) TDO (7FEF); -SDR 16 TDI (FFFF) TDO (EFFF); -SDR 16 TDI (FFFF) TDO (BEFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (AFAB); -SDR 16 TDI (FFFF) TDO (FFBF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (D6BF); -SDR 16 TDI (FFFF) TDO (BF7F); -SDR 16 TDI (FFFF) TDO (F7FF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FAFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (DF5E); -SDR 16 TDI (FFFF) TDO (7B7F); -SDR 16 TDI (FFFF) TDO (FFDF); -SDR 16 TDI (FFFF) TDO (BDDE); -SDR 16 TDI (FFFF) TDO (F5FB); -SDR 16 TDI (FFFF) TDO (7DFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFD); -SDR 16 TDI (FFFF) TDO (FEF7); -SDR 16 TDI (FFFF) TDO (7FF3); -SDR 16 TDI (FFFF) TDO (FECD); -SDR 16 TDI (FFFF) TDO (BEFF); -SDR 16 TDI (FFFF) TDO (EFFF); -SDR 16 TDI (FFFF) TDO (7EF7); -SDR 16 TDI (FFFF) TDO (7DFF); -SDR 16 TDI (FFFF) TDO (BDFF); -SDR 16 TDI (FFFF) TDO (CF77); -SDR 16 TDI (FFFF) TDO (777F); -SDR 16 TDI (FFFF) TDO (FF7F); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FEFB); -SDR 16 TDI (FFFF) TDO (77FF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FBEF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (AFFF); -SDR 16 TDI (FFFF) TDO (FBFB); -SDR 16 TDI (FFFF) TDO (75BF); -SDR 16 TDI (FFFF) TDO (AB7F); -SDR 16 TDI (FFFF) TDO (BFBF); -SDR 16 TDI (FFFF) TDO (FDFF); -SDR 16 TDI (FFFF) TDO (7FF7); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (BDFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFD); -SDR 16 TDI (FFFF) TDO (B7DF); -SDR 16 TDI (FFFF) TDO (77FD); -SDR 16 TDI (FFFF) TDO (EFFD); -SDR 16 TDI (FFFF) TDO (BBFF); -SDR 16 TDI (FFFF) TDO (BFFD); -SDR 16 TDI (FFFF) TDO (7FFB); -SDR 16 TDI (FFFF) TDO (677E); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FF7F); -SDR 16 TDI (FFFF) TDO (7F7F); -SDR 16 TDI (FFFF) TDO (EEFF); -SDR 16 TDI (FFFF) TDO (BFEF); -SDR 16 TDI (FFFF) TDO (FF7F); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); SDR 16 TDI (FFFF) TDO (FDF7); -SDR 16 TDI (FFFF) TDO (7FEF); -SDR 16 TDI (FFFF) TDO (FF37); -SDR 16 TDI (FFFF) TDO (ADFF); -SDR 16 TDI (FFFF) TDO (EBF7); -SDR 16 TDI (FFFF) TDO (6ACF); -SDR 16 TDI (FFFF) TDO (DDFF); -SDR 16 TDI (FFFF) TDO (BDDF); -SDR 16 TDI (FFFF) TDO (ADF7); -SDR 16 TDI (FFFF) TDO (77FB); -SDR 16 TDI (FFFF) TDO (FFBF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BEFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FDF7); SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (BBFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFDD); -SDR 16 TDI (FFFF) TDO (B77F); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (75BF); -SDR 16 TDI (FFFF) TDO (B7DF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (6FDE); -SDR 16 TDI (FFFF) TDO (DE6F); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FBBF); -SDR 16 TDI (FFFF) TDO (79BF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (B7FF); -SDR 16 TDI (FFFF) TDO (EDD7); -SDR 16 TDI (FFFF) TDO (7FEF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (AEBE); -SDR 16 TDI (FFFF) TDO (FFF7); -SDR 16 TDI (FFFF) TDO (7FF3); -SDR 16 TDI (FFFF) TDO (F7FF); -SDR 16 TDI (FFFF) TDO (BDFF); -SDR 16 TDI (FFFF) TDO (BFF3); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BBFF); -SDR 16 TDI (FFFF) TDO (5FFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFDF); -SDR 16 TDI (FFFF) TDO (D757); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (F4EF); -SDR 16 TDI (FFFF) TDO (BF7B); -SDR 16 TDI (FFFF) TDO (7FFB); -SDR 16 TDI (FFFF) TDO (77DF); -SDR 16 TDI (FFFF) TDO (D77B); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (DFFF); -SDR 16 TDI (FFFF) TDO (7EFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BBFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (B7FE); -SDR 16 TDI (FFFF) TDO (7EFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (5FBE); -SDR 16 TDI (FFFF) TDO (B6DE); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7FF5); -SDR 16 TDI (FFFF) TDO (7DEF); -SDR 16 TDI (FFFF) TDO (BDFF); -SDR 16 TDI (FFFF) TDO (FDAD); -SDR 16 TDI (FFFF) TDO (77BF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (5FFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (AE5F); -SDR 16 TDI (FFFF) TDO (EBF7); -SDR 16 TDI (FFFF) TDO (7FFE); -SDR 16 TDI (FFFF) TDO (DFDB); -SDR 16 TDI (FFFF) TDO (BAB7); -SDR 16 TDI (FFFF) TDO (FFFE); -SDR 16 TDI (FFFF) TDO (7FDF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (ABDF); -SDR 16 TDI (FFFF) TDO (FFDE); -SDR 16 TDI (FFFF) TDO (7FFE); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFF5); -SDR 16 TDI (FFFF) TDO (6BFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (ABFD); SDR 16 TDI (FFFF) TDO (FFDF); -SDR 16 TDI (FFFF) TDO (77FB); -SDR 16 TDI (FFFF) TDO (FAEF); -SDR 16 TDI (FFFF) TDO (AFFF); -SDR 16 TDI (FFFF) TDO (FF7F); -SDR 16 TDI (FFFF) TDO (7F77); -SDR 16 TDI (FFFF) TDO (FFF9); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (BB77); -SDR 16 TDI (FFFF) TDO (7ADB); -SDR 16 TDI (FFFF) TDO (FFBF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (EEFF); -SDR 16 TDI (FFFF) TDO (7DFF); +SDR 16 TDI (FFFF) TDO (6F7D); SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (AF5F); -SDR 16 TDI (FFFF) TDO (9FAE); -SDR 16 TDI (FFFF) TDO (7FF7); +SDR 16 TDI (FFFF) TDO (BCFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFF7); +SDR 16 TDI (FFFF) TDO (FF7F); +SDR 16 TDI (FFFF) TDO (7FFF); SDR 16 TDI (FFFF) TDO (EFFF); SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (F7FB); -SDR 16 TDI (FFFF) TDO (77BB); -SDR 16 TDI (FFFF) TDO (FEDF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (6FEB); +SDR 16 TDI (FFFF) TDO (DBFF); SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FF7D); +SDR 16 TDI (FFFF) TDO (FFFD); SDR 16 TDI (FFFF) TDO (7FFB); -SDR 16 TDI (FFFF) TDO (EEFE); +SDR 16 TDI (FFFF) TDO (FFFF); SDR 16 TDI (FFFF) TDO (BFFE); -SDR 16 TDI (FFFF) TDO (FFF5); -SDR 16 TDI (FFFF) TDO (6BFF); SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (A5FE); -SDR 16 TDI (FFFF) TDO (FE7F); SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFD); -SDR 16 TDI (FFFF) TDO (AE7F); -SDR 16 TDI (FFFF) TDO (EFF6); -SDR 16 TDI (FFFF) TDO (7B6F); -SDR 16 TDI (FFFF) TDO (BFDD); -SDR 16 TDI (FFFF) TDO (BF7D); -SDR 16 TDI (FFFF) TDO (F5FF); -SDR 16 TDI (FFFF) TDO (7F7F); -SDR 16 TDI (FFFF) TDO (FEFF); -SDR 16 TDI (FFFF) TDO (B7FF); -SDR 16 TDI (FFFF) TDO (FFEA); -SDR 16 TDI (FFFF) TDO (75FF); SDR 16 TDI (FFFF) TDO (FFFF); SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (BFF7); -SDR 16 TDI (FFFF) TDO (6BFD); -SDR 16 TDI (FFFF) TDO (FD57); -SDR 16 TDI (FFFF) TDO (9FEF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (77FF); -SDR 16 TDI (FFFF) TDO (FA77); -SDR 16 TDI (FFFF) TDO (B7FF); -SDR 16 TDI (FFFF) TDO (FFAA); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (BFBF); -SDR 16 TDI (FFFF) TDO (BEFF); -SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (FDB7); SDR 16 TDI (FFFF) TDO (7FFF); SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (9FFF); -SDR 16 TDI (FFFF) TDO (FEFD); -SDR 16 TDI (FFFF) TDO (7FF7); -SDR 16 TDI (FFFF) TDO (F7FF); -SDR 16 TDI (FFFF) TDO (B7E7); -SDR 16 TDI (FFFF) TDO (D7FF); -SDR 16 TDI (FFFF) TDO (7BFB); -SDR 16 TDI (FFFF) TDO (DB7F); -SDR 16 TDI (FFFF) TDO (BEDF); -SDR 16 TDI (FFFF) TDO (B7FF); -SDR 16 TDI (FFFF) TDO (7F5E); -SDR 16 TDI (FFFF) TDO (FBFF); -SDR 16 TDI (FFFF) TDO (BFEF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (5FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (9FFF); -SDR 16 TDI (FFFF) TDO (BD25); -SDR 16 TDI (FFFF) TDO (4DEF); -SDR 16 TDI (FFFF) TDO (FFFD); -SDR 16 TDI (FFFF) TDO (BA5B); -SDR 16 TDI (FFFF) TDO (E7F5); -SDR 16 TDI (FFFF) TDO (7D5B); -SDR 16 TDI (FFFF) TDO (F5FF); -SDR 16 TDI (FFFF) TDO (9E9D); -SDR 16 TDI (FFFF) TDO (9FD7); -SDR 16 TDI (FFFF) TDO (7FFA); -SDR 16 TDI (FFFF) TDO (DE7D); -SDR 16 TDI (FFFF) TDO (BEFE); +SDR 16 TDI (FFFF) TDO (BDFF); SDR 16 TDI (FFFF) TDO (FFFF); SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (B5FC); -SDR 16 TDI (FFFF) TDO (67FA); -SDR 16 TDI (FFFF) TDO (77F9); -SDR 16 TDI (FFFF) TDO (4AE3); -SDR 16 TDI (FFFF) TDO (ADF7); -SDR 16 TDI (FFFF) TDO (DF7F); -SDR 16 TDI (FFFF) TDO (56EF); -SDR 16 TDI (FFFF) TDO (7E82); -SDR 16 TDI (FFFF) TDO (9BFF); -SDR 16 TDI (FFFF) TDO (F0EB); -SDR 16 TDI (FFFF) TDO (5B97); -SDR 16 TDI (FFFF) TDO (BFBF); -SDR 16 TDI (FFFF) TDO (B7FF); -SDR 16 TDI (FFFF) TDO (FF7B); -SDR 16 TDI (FFFF) TDO (57FF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (9FFF); -SDR 16 TDI (FFFF) TDO (DEDF); -SDR 16 TDI (FFFF) TDO (7FF7); -SDR 16 TDI (FFFF) TDO (F51E); -SDR 16 TDI (FFFF) TDO (B7AF); -SDR 16 TDI (FFFF) TDO (FBFA); -SDR 16 TDI (FFFF) TDO (6BB5); -SDR 16 TDI (FFFF) TDO (9B7D); -SDR 16 TDI (FFFF) TDO (A77F); -SDR 16 TDI (FFFF) TDO (EF3C); -SDR 16 TDI (FFFF) TDO (4E6D); -SDR 16 TDI (FFFF) TDO (F5FF); -SDR 16 TDI (FFFF) TDO (BFF7); -SDR 16 TDI (FFFF) TDO (F7FF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (8F5F); -SDR 16 TDI (FFFF) TDO (002E); -SDR 16 TDI (FFFF) TDO (5FCF); -SDR 16 TDI (FFFF) TDO (EFBA); -SDR 16 TDI (FFFF) TDO (A36B); -SDR 16 TDI (FFFF) TDO (F7EC); -SDR 16 TDI (FFFF) TDO (602B); -SDR 16 TDI (FFFF) TDO (9970); -SDR 16 TDI (FFFF) TDO (8A77); -SDR 16 TDI (FFFF) TDO (084C); -SDR 16 TDI (FFFF) TDO (7041); -SDR 16 TDI (FFFF) TDO (A06F); -SDR 16 TDI (FFFF) TDO (A4E2); -SDR 16 TDI (FFFF) TDO (E7EC); -SDR 16 TDI (FFFF) TDO (7BFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (A7FE); -SDR 16 TDI (FFFF) TDO (8022); -SDR 16 TDI (FFFF) TDO (47A5); -SDR 16 TDI (FFFF) TDO (E422); -SDR 16 TDI (FFFF) TDO (AB2B); -SDR 16 TDI (FFFF) TDO (F2F0); -SDR 16 TDI (FFFF) TDO (6A0B); -SDR 16 TDI (FFFF) TDO (91F4); -SDR 16 TDI (FFFF) TDO (881B); -SDR 16 TDI (FFFF) TDO (8944); -SDR 16 TDI (FFFF) TDO (4040); -SDR 16 TDI (FFFF) TDO (A08F); -SDR 16 TDI (FFFF) TDO (BCFA); -SDR 16 TDI (FFFF) TDO (F86F); -SDR 16 TDI (FFFF) TDO (6FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (9D5F); -SDR 16 TDI (FFFF) TDO (022E); -SDR 16 TDI (FFFF) TDO (7FF7); -SDR 16 TDI (FFFF) TDO (F7BA); -SDR 16 TDI (FFFF) TDO (A28F); -SDR 16 TDI (FFFF) TDO (EBFB); -SDR 16 TDI (FFFF) TDO (6410); -SDR 16 TDI (FFFF) TDO (1EB0); -SDR 16 TDI (FFFF) TDO (AFBF); -SDR 16 TDI (FFFF) TDO (F86B); -SDR 16 TDI (FFFF) TDO (7040); -SDR 16 TDI (FFFF) TDO (6C5F); -SDR 16 TDI (FFFF) TDO (9F19); -SDR 16 TDI (FFFF) TDO (187D); -SDR 16 TDI (FFFF) TDO (7BFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BBFE); -SDR 16 TDI (FFFF) TDO (6422); -SDR 16 TDI (FFFF) TDO (67E4); -SDR 16 TDI (FFFF) TDO (0422); -SDR 16 TDI (FFFF) TDO (A203); -SDR 16 TDI (FFFF) TDO (E3FB); -SDR 16 TDI (FFFF) TDO (7213); -SDR 16 TDI (FFFF) TDO (36F0); -SDR 16 TDI (FFFF) TDO (8BBF); -SDR 16 TDI (FFFF) TDO (E063); -SDR 16 TDI (FFFF) TDO (6FD0); -SDR 16 TDI (FFFF) TDO (608F); -SDR 16 TDI (FFFF) TDO (BF61); -SDR 16 TDI (FFFF) TDO (61BF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFDF); -SDR 16 TDI (FFFF) TDO (BA3B); -SDR 16 TDI (FFFF) TDO (71EE); -SDR 16 TDI (FFFF) TDO (EEEF); -SDR 16 TDI (FFFF) TDO (A123); -SDR 16 TDI (FFFF) TDO (11F3); -SDR 16 TDI (FFFF) TDO (484D); -SDR 16 TDI (FFFF) TDO (3888); -SDR 16 TDI (FFFF) TDO (938F); -SDR 16 TDI (FFFF) TDO (B888); -SDR 16 TDI (FFFF) TDO (50CC); -SDR 16 TDI (FFFF) TDO (CCE7); -SDR 16 TDI (FFFF) TDO (BBBB); -SDR 16 TDI (FFFF) TDO (BBEA); -SDR 16 TDI (FFFF) TDO (67FF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (97FF); -SDR 16 TDI (FFFF) TDO (3373); -SDR 16 TDI (FFFF) TDO (6146); -SDR 16 TDI (FFFF) TDO (6667); -SDR 16 TDI (FFFF) TDO (B737); -SDR 16 TDI (FFFF) TDO (72A9); -SDR 16 TDI (FFFF) TDO (6623); -SDR 16 TDI (FFFF) TDO (7DD9); -SDR 16 TDI (FFFF) TDO (BBB5); -SDR 16 TDI (FFFF) TDO (1CDD); -SDR 16 TDI (FFFF) TDO (73C9); -SDR 16 TDI (FFFF) TDO (C9C2); -SDR 16 TDI (FFFF) TDO (9111); -SDR 16 TDI (FFFF) TDO (117F); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFDD); +SDR 16 TDI (FFFF) TDO (DEF7); +SDR 16 TDI (FFFF) TDO (BFFF); SDR 16 TDI (FFFF) TDO (FFDD); -SDR 16 TDI (FFFF) TDO (7FDD); -SDR 16 TDI (FFFF) TDO (FDDD); -SDR 16 TDI (FFFF) TDO (BDBF); -SDR 16 TDI (FFFF) TDO (DFEF); -SDR 16 TDI (FFFF) TDO (7CDD); -SDR 16 TDI (FFFF) TDO (FFEE); -SDR 16 TDI (FFFF) TDO (9FDF); -SDR 16 TDI (FFFF) TDO (7BFF); -SDR 16 TDI (FFFF) TDO (7E7F); -SDR 16 TDI (FFFF) TDO (FFF7); -SDR 16 TDI (FFFF) TDO (B7FF); -SDR 16 TDI (FFFF) TDO (FFBF); -SDR 16 TDI (FFFF) TDO (6FFF); +SDR 16 TDI (FFFF) TDO (7FFE); SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (A7F7); -SDR 16 TDI (FFFF) TDO (7FF7); -SDR 16 TDI (FFFF) TDO (EEEF); -SDR 16 TDI (FFFF) TDO (95E7); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (7DFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFB5); -SDR 16 TDI (FFFF) TDO (6FF5); -SDR 16 TDI (FFFF) TDO (BF7F); -SDR 16 TDI (FFFF) TDO (BF7C); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (9FFE); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (BFFD); -SDR 16 TDI (FFFF) TDO (BFBE); -SDR 16 TDI (FFFF) TDO (7BF6); -SDR 16 TDI (FFFF) TDO (74D5); -SDR 16 TDI (FFFF) TDO (FF9F); -SDR 16 TDI (FFFF) TDO (B2BF); -SDR 16 TDI (FFFF) TDO (D2FF); -SDR 16 TDI (FFFF) TDO (5F7F); -SDR 16 TDI (FFFF) TDO (F7FF); -SDR 16 TDI (FFFF) TDO (9FBF); -SDR 16 TDI (FFFF) TDO (ADDF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (8FFF); -SDR 16 TDI (FFFF) TDO (7FF7); -SDR 16 TDI (FFFF) TDO (5FEF); -SDR 16 TDI (FFFF) TDO (F7F5); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFFD); -SDR 16 TDI (FFFF) TDO (77DD); -SDR 16 TDI (FFFF) TDO (FEFF); -SDR 16 TDI (FFFF) TDO (9F7F); -SDR 16 TDI (FFFF) TDO (DFDD); -SDR 16 TDI (FFFF) TDO (6FF7); -SDR 16 TDI (FFFF) TDO (7FFF); SDR 16 TDI (FFFF) TDO (BEFF); -SDR 16 TDI (FFFF) TDO (FDFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7DFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BBAF); +SDR 16 TDI (FFFF) TDO (FFFF); SDR 16 TDI (FFFF) TDO (7FFF); SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFE); +SDR 16 TDI (FFFF) TDO (7F7F); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BBFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7DFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFD); +SDR 16 TDI (FFFF) TDO (FBFB); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFD); +SDR 16 TDI (FFFF) TDO (AFBF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FF7F); +SDR 16 TDI (FFFF) TDO (BB7F); +SDR 16 TDI (FFFF) TDO (FDFF); +SDR 16 TDI (FFFF) TDO (7DFF); +SDR 16 TDI (FFFF) TDO (FDFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FAFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (7FBE); +SDR 16 TDI (FFFF) TDO (6FF3); +SDR 16 TDI (FFFF) TDO (6FFF); +SDR 16 TDI (FFFF) TDO (BFE7); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (7F7D); +SDR 16 TDI (FFFF) TDO (CFFF); +SDR 16 TDI (FFFF) TDO (BFBF); +SDR 16 TDI (FFFF) TDO (DFFD); +SDR 16 TDI (FFFF) TDO (7FFA); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFBF); +SDR 16 TDI (FFFF) TDO (DFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFF7); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FEFF); +SDR 16 TDI (FFFF) TDO (BB77); +SDR 16 TDI (FFFF) TDO (FBF7); +SDR 16 TDI (FFFF) TDO (6F6F); +SDR 16 TDI (FFFF) TDO (CF7F); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (DFBD); +SDR 16 TDI (FFFF) TDO (7FFD); +SDR 16 TDI (FFFF) TDO (EFFF); +SDR 16 TDI (FFFF) TDO (BFDF); +SDR 16 TDI (FFFF) TDO (DFF7); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFD); +SDR 16 TDI (FFFF) TDO (FB75); +SDR 16 TDI (FFFF) TDO (6FEB); +SDR 16 TDI (FFFF) TDO (77FA); +SDR 16 TDI (FFFF) TDO (BFEF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (7FFD); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BB3F); +SDR 16 TDI (FFFF) TDO (FDFF); +SDR 16 TDI (FFFF) TDO (7DFB); +SDR 16 TDI (FFFF) TDO (FDFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FD7F); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (6BB7); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BEFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFF7); +SDR 16 TDI (FFFF) TDO (ABFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFEF); +SDR 16 TDI (FFFF) TDO (DDFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BEBF); +SDR 16 TDI (FFFF) TDO (FDEF); +SDR 16 TDI (FFFF) TDO (7FEF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFF7); +SDR 16 TDI (FFFF) TDO (7FFE); +SDR 16 TDI (FFFF) TDO (F5FD); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (DDF7); +SDR 16 TDI (FFFF) TDO (7BFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BBFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BDFF); +SDR 16 TDI (FFFF) TDO (DDF7); +SDR 16 TDI (FFFF) TDO (7FF7); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (BDFB); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFB); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFE); +SDR 16 TDI (FFFF) TDO (7BFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BBF7); +SDR 16 TDI (FFFF) TDO (EDFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFBF); +SDR 16 TDI (FFFF) TDO (7B9F); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (7AFA); +SDR 16 TDI (FFFF) TDO (ADFF); +SDR 16 TDI (FFFF) TDO (FDEF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (B55F); +SDR 16 TDI (FFFF) TDO (9FB7); +SDR 16 TDI (FFFF) TDO (7FFA); +SDR 16 TDI (FFFF) TDO (EECD); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FEAE); +SDR 16 TDI (FFFF) TDO (BFDF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFDF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFF5); +SDR 16 TDI (FFFF) TDO (69FF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (F7FF); +SDR 16 TDI (FFFF) TDO (6FFF); +SDR 16 TDI (FFFF) TDO (FBFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (EFF7); +SDR 16 TDI (FFFF) TDO (6EFF); +SDR 16 TDI (FFFF) TDO (BBFF); +SDR 16 TDI (FFFF) TDO (BBFF); +SDR 16 TDI (FFFF) TDO (FFDE); +SDR 16 TDI (FFFF) TDO (77FF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BBFA); +SDR 16 TDI (FFFF) TDO (BBFF); +SDR 16 TDI (FFFF) TDO (7DFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (B55F); +SDR 16 TDI (FFFF) TDO (DFFF); +SDR 16 TDI (FFFF) TDO (7FF7); +SDR 16 TDI (FFFF) TDO (FFFF); SDR 16 TDI (FFFF) TDO (AFFF); -SDR 16 TDI (FFFF) TDO (D7FF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FEFF); -SDR 16 TDI (FFFF) TDO (99D7); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FDF); +SDR 16 TDI (FFFF) TDO (FF7F); +SDR 16 TDI (FFFF) TDO (BEFF); +SDR 16 TDI (FFFF) TDO (BFFC); +SDR 16 TDI (FFFF) TDO (7FFE); +SDR 16 TDI (FFFF) TDO (FDFF); +SDR 16 TDI (FFFF) TDO (BFBF); +SDR 16 TDI (FFFF) TDO (FFF5); +SDR 16 TDI (FFFF) TDO (69FF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (AAAD); +SDR 16 TDI (FFFF) TDO (7BF7); +SDR 16 TDI (FFFF) TDO (6FFD); +SDR 16 TDI (FFFF) TDO (DFDD); SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (7DEE); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7DFF); SDR 16 TDI (FFFF) TDO (FFDF); -SDR 16 TDI (FFFF) TDO (BDDF); -SDR 16 TDI (FFFF) TDO (EFF7); -SDR 16 TDI (FFFF) TDO (7F7D); -SDR 16 TDI (FFFF) TDO (FBBF); +SDR 16 TDI (FFFF) TDO (BFBF); +SDR 16 TDI (FFFF) TDO (FF6F); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (F7FF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7DFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FBFF); +SDR 16 TDI (FFFF) TDO (BEEF); +SDR 16 TDI (FFFF) TDO (FFF5); +SDR 16 TDI (FFFF) TDO (6FF7); +SDR 16 TDI (FFFF) TDO (F9FF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFB); +SDR 16 TDI (FFFF) TDO (7FFE); +SDR 16 TDI (FFFF) TDO (FEFD); SDR 16 TDI (FFFF) TDO (BFFC); SDR 16 TDI (FFFF) TDO (FFFE); SDR 16 TDI (FFFF) TDO (7FFF); SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (9FFF); -SDR 16 TDI (FFFF) TDO (FEFF); -SDR 16 TDI (FFFF) TDO (5FFD); -SDR 16 TDI (FFFF) TDO (FF5F); -SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (BFFD); +SDR 16 TDI (FFFF) TDO (FFBF); +SDR 16 TDI (FFFF) TDO (7FF7); +SDR 16 TDI (FFFF) TDO (5777); +SDR 16 TDI (FFFF) TDO (BFFE); +SDR 16 TDI (FFFF) TDO (FFBD); SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (7FDD); +SDR 16 TDI (FFFF) TDO (FFFD); +SDR 16 TDI (FFFF) TDO (B37F); +SDR 16 TDI (FFFF) TDO (DDCF); +SDR 16 TDI (FFFF) TDO (7BFF); SDR 16 TDI (FFFF) TDO (FBFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FD6F); -SDR 16 TDI (FFFF) TDO (6EFF); -SDR 16 TDI (FFFF) TDO (DFFF); -SDR 16 TDI (FFFF) TDO (9BEE); -SDR 16 TDI (FFFF) TDO (FBFB); -SDR 16 TDI (FFFF) TDO (57FF); +SDR 16 TDI (FFFF) TDO (BFBF); SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFEF); SDR 16 TDI (FFFF) TDO (7FFF); SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BBFF); -SDR 16 TDI (FFFF) TDO (FFF7); -SDR 16 TDI (FFFF) TDO (5F77); -SDR 16 TDI (FFFF) TDO (AF7D); -SDR 16 TDI (FFFF) TDO (9F7F); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7BF9); -SDR 16 TDI (FFFF) TDO (FB5F); -SDR 16 TDI (FFFF) TDO (9FFF); SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (5FFF); -SDR 16 TDI (FFFF) TDO (FFFF); SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (BBDF); -SDR 16 TDI (FFFF) TDO (57EC); -SDR 16 TDI (FFFF) TDO (EF7F); -SDR 16 TDI (FFFF) TDO (9FFB); -SDR 16 TDI (FFFF) TDO (FFFB); -SDR 16 TDI (FFFF) TDO (7FFE); -SDR 16 TDI (FFFF) TDO (EFFF); -SDR 16 TDI (FFFF) TDO (9EFF); -SDR 16 TDI (FFFF) TDO (FF7F); -SDR 16 TDI (FFFF) TDO (4FFF); -SDR 16 TDI (FFFF) TDO (D7FF); -SDR 16 TDI (FFFF) TDO (BDF7); -SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FEE); +SDR 16 TDI (FFFF) TDO (D4ED); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (DFFB); +SDR 16 TDI (FFFF) TDO (6BFF); +SDR 16 TDI (FFFF) TDO (F5BF); +SDR 16 TDI (FFFF) TDO (AFFF); +SDR 16 TDI (FFFF) TDO (FEFE); +SDR 16 TDI (FFFF) TDO (6FFD); +SDR 16 TDI (FFFF) TDO (F5FE); +SDR 16 TDI (FFFF) TDO (BF9E); SDR 16 TDI (FFFF) TDO (5FFF); +SDR 16 TDI (FFFF) TDO (7FFF); SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (9FFF); +SDR 16 TDI (FFFF) TDO (BEEF); +SDR 16 TDI (FFFF) TDO (EF3F); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (EBDF); +SDR 16 TDI (FFFF) TDO (AFED); +SDR 16 TDI (FFFF) TDO (FFF6); +SDR 16 TDI (FFFF) TDO (773F); +SDR 16 TDI (FFFF) TDO (DBCE); +SDR 16 TDI (FFFF) TDO (B8BF); +SDR 16 TDI (FFFF) TDO (9BF3); +SDR 16 TDI (FFFF) TDO (77FE); +SDR 16 TDI (FFFF) TDO (FEDF); +SDR 16 TDI (FFFF) TDO (BDFD); +SDR 16 TDI (FFFF) TDO (FFEA); +SDR 16 TDI (FFFF) TDO (77FF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFC); +SDR 16 TDI (FFFF) TDO (53F3); +SDR 16 TDI (FFFF) TDO (67F1); +SDR 16 TDI (FFFF) TDO (3F33); +SDR 16 TDI (FFFF) TDO (BEFF); +SDR 16 TDI (FFFF) TDO (FFBD); +SDR 16 TDI (FFFF) TDO (7FEF); +SDR 16 TDI (FFFF) TDO (FE7D); +SDR 16 TDI (FFFF) TDO (BF5F); +SDR 16 TDI (FFFF) TDO (FF8D); +SDR 16 TDI (FFFF) TDO (7BFF); +SDR 16 TDI (FFFF) TDO (FBFF); +SDR 16 TDI (FFFF) TDO (BFFB); SDR 16 TDI (FFFF) TDO (FDFF); SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFBF); -SDR 16 TDI (FFFF) TDO (9BFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (5ED3); -SDR 16 TDI (FFFF) TDO (D77D); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FDF7); -SDR 16 TDI (FFFF) TDO (59F6); -SDR 16 TDI (FFFF) TDO (FF9F); -SDR 16 TDI (FFFF) TDO (9FFF); -SDR 16 TDI (FFFF) TDO (3BFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (B59C); +SDR 16 TDI (FFFF) TDO (000F); +SDR 16 TDI (FFFF) TDO (7FC0); +SDR 16 TDI (FFFF) TDO (0200); +SDR 16 TDI (FFFF) TDO (BE9F); +SDR 16 TDI (FFFF) TDO (C3E0); +SDR 16 TDI (FFFF) TDO (6019); +SDR 16 TDI (FFFF) TDO (F803); +SDR 16 TDI (FFFF) TDO (BF5F); +SDR 16 TDI (FFFF) TDO (0098); +SDR 16 TDI (FFFF) TDO (60FC); +SDR 16 TDI (FFFF) TDO (F00F); +SDR 16 TDI (FFFF) TDO (B01F); +SDR 16 TDI (FFFF) TDO (8075); +SDR 16 TDI (FFFF) TDO (6BFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (AFFC); +SDR 16 TDI (FFFF) TDO (000F); +SDR 16 TDI (FFFF) TDO (7FA0); +SDR 16 TDI (FFFF) TDO (0000); +SDR 16 TDI (FFFF) TDO (BE9C); +SDR 16 TDI (FFFF) TDO (3370); +SDR 16 TDI (FFFF) TDO (6018); +SDR 16 TDI (FFFF) TDO (1003); +SDR 16 TDI (FFFF) TDO (A7DE); +SDR 16 TDI (FFFF) TDO (80B8); +SDR 16 TDI (FFFF) TDO (60FC); +SDR 16 TDI (FFFF) TDO (FC0D); +SDR 16 TDI (FFFF) TDO (B81B); +SDR 16 TDI (FFFF) TDO (807F); SDR 16 TDI (FFFF) TDO (7FFF); SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (9FF7); -SDR 16 TDI (FFFF) TDO (BDDF); -SDR 16 TDI (FFFF) TDO (5FFF); -SDR 16 TDI (FFFF) TDO (D7D7); -SDR 16 TDI (FFFF) TDO (BAFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (5FAD); -SDR 16 TDI (FFFF) TDO (FB7F); -SDR 16 TDI (FFFF) TDO (9FFF); -SDR 16 TDI (FFFF) TDO (FDFE); -SDR 16 TDI (FFFF) TDO (77FF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (9FFF); -SDR 16 TDI (FFFF) TDO (FBAF); -SDR 16 TDI (FFFF) TDO (5FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (5FEF); -SDR 16 TDI (FFFF) TDO (FBFF); -SDR 16 TDI (FFFF) TDO (9FBE); -SDR 16 TDI (FFFF) TDO (FFFB); -SDR 16 TDI (FFFF) TDO (7FFE); -SDR 16 TDI (FFFF) TDO (FFFB); -SDR 16 TDI (FFFF) TDO (93FF); -SDR 16 TDI (FFFF) TDO (BF77); -SDR 16 TDI (FFFF) TDO (5EFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BBFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (5FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (9FFF); -SDR 16 TDI (FFFF) TDO (FFBF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFF7); -SDR 16 TDI (FFFF) TDO (8FFD); -SDR 16 TDI (FFFF) TDO (FFF7); -SDR 16 TDI (FFFF) TDO (5EDD); -SDR 16 TDI (FFFF) TDO (BE66); -SDR 16 TDI (FFFF) TDO (BBFF); -SDR 16 TDI (FFFF) TDO (BDBB); -SDR 16 TDI (FFFF) TDO (6FFF); -SDR 16 TDI (FFFF) TDO (FEFF); -SDR 16 TDI (FFFF) TDO (BFBF); -SDR 16 TDI (FFFF) TDO (ADFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (9FFB); -SDR 16 TDI (FFFF) TDO (7EEF); -SDR 16 TDI (FFFF) TDO (5FFF); -SDR 16 TDI (FFFF) TDO (ABBF); -SDR 16 TDI (FFFF) TDO (B5BF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7FEE); -SDR 16 TDI (FFFF) TDO (FBFF); -SDR 16 TDI (FFFF) TDO (B7FF); -SDR 16 TDI (FFFF) TDO (FF6F); -SDR 16 TDI (FFFF) TDO (79FF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (9FFF); -SDR 16 TDI (FFFF) TDO (FFB7); -SDR 16 TDI (FFFF) TDO (5FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (AB5F); -SDR 16 TDI (FFFF) TDO (B7FD); -SDR 16 TDI (FFFF) TDO (77FF); -SDR 16 TDI (FFFF) TDO (AFF6); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (7EFF); -SDR 16 TDI (FFFF) TDO (BB9F); -SDR 16 TDI (FFFF) TDO (97FF); -SDR 16 TDI (FFFF) TDO (FFDD); -SDR 16 TDI (FFFF) TDO (5FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFFD); -SDR 16 TDI (FFFF) TDO (7BFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (AEFF); -SDR 16 TDI (FFFF) TDO (FFBF); -SDR 16 TDI (FFFF) TDO (7FB6); -SDR 16 TDI (FFFF) TDO (FBFF); -SDR 16 TDI (FFFF) TDO (979F); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (57FF); -SDR 16 TDI (FFFF) TDO (FDF5); -SDR 16 TDI (FFFF) TDO (BDDF); -SDR 16 TDI (FFFF) TDO (BD7F); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFBF); -SDR 16 TDI (FFFF) TDO (BBBF); -SDR 16 TDI (FFFF) TDO (7EFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (8A5F); -SDR 16 TDI (FFFF) TDO (DFFF); -SDR 16 TDI (FFFF) TDO (5FFF); -SDR 16 TDI (FFFF) TDO (FF7D); -SDR 16 TDI (FFFF) TDO (BFFB); -SDR 16 TDI (FFFF) TDO (DBF7); -SDR 16 TDI (FFFF) TDO (7DFE); -SDR 16 TDI (FFFF) TDO (FF7F); -SDR 16 TDI (FFFF) TDO (AEFF); -SDR 16 TDI (FFFF) TDO (FFEF); -SDR 16 TDI (FFFF) TDO (7FBF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (9FFA); -SDR 16 TDI (FFFF) TDO (FFFD); -SDR 16 TDI (FFFF) TDO (5BFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (AFFD); -SDR 16 TDI (FFFF) TDO (FD7F); -SDR 16 TDI (FFFF) TDO (7FEF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFDF); -SDR 16 TDI (FFFF) TDO (FFFD); -SDR 16 TDI (FFFF) TDO (6EFF); -SDR 16 TDI (FFFF) TDO (F5FB); -SDR 16 TDI (FFFF) TDO (9DFF); -SDR 16 TDI (FFFF) TDO (F6FD); -SDR 16 TDI (FFFF) TDO (57FF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFB); -SDR 16 TDI (FFFF) TDO (FFFB); -SDR 16 TDI (FFFF) TDO (77FF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (7FD7); -SDR 16 TDI (FFFF) TDO (7FFE); -SDR 16 TDI (FFFF) TDO (BBDF); -SDR 16 TDI (FFFF) TDO (9DF6); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (5FFF); -SDR 16 TDI (FFFF) TDO (FFFD); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (DDFF); -SDR 16 TDI (FFFF) TDO (6EFB); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (BAEF); -SDR 16 TDI (FFFF) TDO (DFFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (9FFF); -SDR 16 TDI (FFFF) TDO (D5DF); -SDR 16 TDI (FFFF) TDO (5FFF); -SDR 16 TDI (FFFF) TDO (FF35); -SDR 16 TDI (FFFF) TDO (96BD); -SDR 16 TDI (FFFF) TDO (EBFD); -SDR 16 TDI (FFFF) TDO (5DDF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (BEBD); -SDR 16 TDI (FFFF) TDO (F7EF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FBFE); -SDR 16 TDI (FFFF) TDO (BEFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (9BFF); -SDR 16 TDI (FFFF) TDO (B72F); -SDR 16 TDI (FFFF) TDO (4FEF); -SDR 16 TDI (FFFF) TDO (9256); -SDR 16 TDI (FFFF) TDO (B3DE); -SDR 16 TDI (FFFF) TDO (DBFA); -SDR 16 TDI (FFFF) TDO (6AFE); -SDR 16 TDI (FFFF) TDO (FEB2); -SDR 16 TDI (FFFF) TDO (AFFD); -SDR 16 TDI (FFFF) TDO (F0D3); -SDR 16 TDI (FFFF) TDO (7DFF); -SDR 16 TDI (FFFF) TDO (FF7F); -SDR 16 TDI (FFFF) TDO (9DED); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (5FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BDFF); -SDR 16 TDI (FFFF) TDO (7DDD); -SDR 16 TDI (FFFF) TDO (7FB7); -SDR 16 TDI (FFFF) TDO (FDBF); -SDR 16 TDI (FFFF) TDO (BE6D); -SDR 16 TDI (FFFF) TDO (A7FD); -SDR 16 TDI (FFFF) TDO (77FF); -SDR 16 TDI (FFFF) TDO (DB5D); -SDR 16 TDI (FFFF) TDO (97DF); -SDR 16 TDI (FFFF) TDO (BF7F); -SDR 16 TDI (FFFF) TDO (57BF); -SDR 16 TDI (FFFF) TDO (B7FF); -SDR 16 TDI (FFFF) TDO (BB5E); -SDR 16 TDI (FFFF) TDO (FF7F); -SDR 16 TDI (FFFF) TDO (7BFF); +SDR 16 TDI (FFFF) TDO (B95C); +SDR 16 TDI (FFFF) TDO (2303); +SDR 16 TDI (FFFF) TDO (67F1); +SDR 16 TDI (FFFF) TDO (0111); +SDR 16 TDI (FFFF) TDO (A928); +SDR 16 TDI (FFFF) TDO (3FF1); +SDR 16 TDI (FFFF) TDO (6326); +SDR 16 TDI (FFFF) TDO (1080); +SDR 16 TDI (FFFF) TDO (BF3F); +SDR 16 TDI (FFFF) TDO (E098); +SDR 16 TDI (FFFF) TDO (6CFF); +SDR 16 TDI (FFFF) TDO (F90F); +SDR 16 TDI (FFFF) TDO (B87F); +SDR 16 TDI (FFFF) TDO (8075); +SDR 16 TDI (FFFF) TDO (6BFF); SDR 16 TDI (FFFF) TDO (FFFF); SDR 16 TDI (FFFF) TDO (BFFE); -SDR 16 TDI (FFFF) TDO (CAFB); -SDR 16 TDI (FFFF) TDO (7FFE); -SDR 16 TDI (FFFF) TDO (7FE9); -SDR 16 TDI (FFFF) TDO (9DB3); +SDR 16 TDI (FFFF) TDO (0303); +SDR 16 TDI (FFFF) TDO (67E0); +SDR 16 TDI (FFFF) TDO (0001); +SDR 16 TDI (FFFF) TDO (A92B); +SDR 16 TDI (FFFF) TDO (03F0); +SDR 16 TDI (FFFF) TDO (6326); +SDR 16 TDI (FFFF) TDO (7000); +SDR 16 TDI (FFFF) TDO (BE9F); +SDR 16 TDI (FFFF) TDO (E0C2); +SDR 16 TDI (FFFF) TDO (6CFF); +SDR 16 TDI (FFFF) TDO (FC0F); +SDR 16 TDI (FFFF) TDO (B87F); +SDR 16 TDI (FFFF) TDO (807F); SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (5D5F); -SDR 16 TDI (FFFF) TDO (75FF); -SDR 16 TDI (FFFF) TDO (B83F); -SDR 16 TDI (FFFF) TDO (CFEC); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BAAE); +SDR 16 TDI (FFFF) TDO (3181); +SDR 16 TDI (FFFF) TDO (63E2); +SDR 16 TDI (FFFF) TDO (6023); +SDR 16 TDI (FFFF) TDO (BBBB); +SDR 16 TDI (FFFF) TDO (B9F3); +SDR 16 TDI (FFFF) TDO (662E); +SDR 16 TDI (FFFF) TDO (F682); +SDR 16 TDI (FFFF) TDO (B8CF); +SDR 16 TDI (FFFF) TDO (98B2); +SDR 16 TDI (FFFF) TDO (63CC); +SDR 16 TDI (FFFF) TDO (ECC7); +SDR 16 TDI (FFFF) TDO (B999); +SDR 16 TDI (FFFF) TDO (99FE); +SDR 16 TDI (FFFF) TDO (77FF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (6732); +SDR 16 TDI (FFFF) TDO (6557); +SDR 16 TDI (FFFF) TDO (2776); +SDR 16 TDI (FFFF) TDO (B111); +SDR 16 TDI (FFFF) TDO (10AB); +SDR 16 TDI (FFFF) TDO (7364); +SDR 16 TDI (FFFF) TDO (58DC); +SDR 16 TDI (FFFF) TDO (B315); +SDR 16 TDI (FFFF) TDO (4D89); +SDR 16 TDI (FFFF) TDO (79DC); +SDR 16 TDI (FFFF) TDO (C9CA); +SDR 16 TDI (FFFF) TDO (B199); +SDR 16 TDI (FFFF) TDO (99FF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FD9D); +SDR 16 TDI (FFFF) TDO (7FDF); +SDR 16 TDI (FFFF) TDO (FDFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFE7); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (F7F7); +SDR 16 TDI (FFFF) TDO (BCFF); +SDR 16 TDI (FFFF) TDO (7FF7); +SDR 16 TDI (FFFF) TDO (6FFF); +SDR 16 TDI (FFFF) TDO (FF7F); +SDR 16 TDI (FFFF) TDO (B77F); +SDR 16 TDI (FFFF) TDO (F77F); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (7BFF); +SDR 16 TDI (FFFF) TDO (7FF7); +SDR 16 TDI (FFFF) TDO (F6FF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (DFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFBF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (7F7B); +SDR 16 TDI (FFFF) TDO (DFDF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (B7DF); +SDR 16 TDI (FFFF) TDO (FDF7); +SDR 16 TDI (FFFF) TDO (6FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (BBE9); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFD); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FDFF); +SDR 16 TDI (FFFF) TDO (BFEF); +SDR 16 TDI (FFFF) TDO (FFDF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FDFB); +SDR 16 TDI (FFFF) TDO (77FF); +SDR 16 TDI (FFFF) TDO (EFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFD); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFD); +SDR 16 TDI (FFFF) TDO (7F7B); +SDR 16 TDI (FFFF) TDO (FEDF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFBB); +SDR 16 TDI (FFFF) TDO (BBFF); +SDR 16 TDI (FFFF) TDO (7FF7); +SDR 16 TDI (FFFF) TDO (FEFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (EFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFBF); +SDR 16 TDI (FFFF) TDO (DFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (EFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFD); +SDR 16 TDI (FFFF) TDO (FFEF); +SDR 16 TDI (FFFF) TDO (6FFF); +SDR 16 TDI (FFFF) TDO (FFFD); +SDR 16 TDI (FFFF) TDO (A7DF); +SDR 16 TDI (FFFF) TDO (7FF9); +SDR 16 TDI (FFFF) TDO (77EF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (69FF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BDFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FEF7); +SDR 16 TDI (FFFF) TDO (7FEF); +SDR 16 TDI (FFFF) TDO (FF3F); +SDR 16 TDI (FFFF) TDO (BDFF); +SDR 16 TDI (FFFF) TDO (F7FF); SDR 16 TDI (FFFF) TDO (7FFB); +SDR 16 TDI (FFFF) TDO (EFB7); +SDR 16 TDI (FFFF) TDO (BDBF); +SDR 16 TDI (FFFF) TDO (DFEF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFEF); +SDR 16 TDI (FFFF) TDO (BFDF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFD7); +SDR 16 TDI (FFFF) TDO (FDFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (EFFF); +SDR 16 TDI (FFFF) TDO (BFDA); +SDR 16 TDI (FFFF) TDO (EFFF); +SDR 16 TDI (FFFF) TDO (7FB7); +SDR 16 TDI (FFFF) TDO (FEFE); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (DFBF); +SDR 16 TDI (FFFF) TDO (7BFF); +SDR 16 TDI (FFFF) TDO (FFDF); +SDR 16 TDI (FFFF) TDO (BDDF); +SDR 16 TDI (FFFF) TDO (FFF7); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFE); +SDR 16 TDI (FFFF) TDO (FFD7); +SDR 16 TDI (FFFF) TDO (77EF); +SDR 16 TDI (FFFF) TDO (FF5A); +SDR 16 TDI (FFFF) TDO (BAFF); +SDR 16 TDI (FFFF) TDO (B7F9); +SDR 16 TDI (FFFF) TDO (6FFD); +SDR 16 TDI (FFFF) TDO (DF77); +SDR 16 TDI (FFFF) TDO (BDBF); +SDR 16 TDI (FFFF) TDO (FFF6); +SDR 16 TDI (FFFF) TDO (7DFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (E6FF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (A5FB); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (77FB); +SDR 16 TDI (FFFF) TDO (F5E6); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FD7D); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (DDFF); +SDR 16 TDI (FFFF) TDO (BFFA); +SDR 16 TDI (FFFF) TDO (AFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFD); +SDR 16 TDI (FFFF) TDO (FFA7); +SDR 16 TDI (FFFF) TDO (7FEF); +SDR 16 TDI (FFFF) TDO (EDBB); +SDR 16 TDI (FFFF) TDO (BF5E); +SDR 16 TDI (FFFF) TDO (7FFB); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (DFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (7BE7); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BBB7); +SDR 16 TDI (FFFF) TDO (FDFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (BFD7); +SDR 16 TDI (FFFF) TDO (7FFE); +SDR 16 TDI (FFFF) TDO (FEEE); +SDR 16 TDI (FFFF) TDO (BDDF); +SDR 16 TDI (FFFF) TDO (7FF7); +SDR 16 TDI (FFFF) TDO (7EFD); +SDR 16 TDI (FFFF) TDO (D7F7); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (BDFD); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BDFF); +SDR 16 TDI (FFFF) TDO (F7FF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFD); +SDR 16 TDI (FFFF) TDO (D5BF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (CBBB); +SDR 16 TDI (FFFF) TDO (B776); +SDR 16 TDI (FFFF) TDO (FBFF); +SDR 16 TDI (FFFF) TDO (6FFF); +SDR 16 TDI (FFFF) TDO (FDEE); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FF7F); +SDR 16 TDI (FFFF) TDO (77E7); +SDR 16 TDI (FFFF) TDO (DEEF); +SDR 16 TDI (FFFF) TDO (BFCB); +SDR 16 TDI (FFFF) TDO (5DFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFE); +SDR 16 TDI (FFFF) TDO (FBBF); +SDR 16 TDI (FFFF) TDO (7FB7); +SDR 16 TDI (FFFF) TDO (EEAD); +SDR 16 TDI (FFFF) TDO (BBEF); +SDR 16 TDI (FFFF) TDO (FFF6); +SDR 16 TDI (FFFF) TDO (7FFC); +SDR 16 TDI (FFFF) TDO (DEF7); +SDR 16 TDI (FFFF) TDO (BDFF); +SDR 16 TDI (FFFF) TDO (DFB5); +SDR 16 TDI (FFFF) TDO (77FB); +SDR 16 TDI (FFFF) TDO (FDFF); +SDR 16 TDI (FFFF) TDO (BFBD); +SDR 16 TDI (FFFF) TDO (DFFD); +SDR 16 TDI (FFFF) TDO (7BFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BBBF); +SDR 16 TDI (FFFF) TDO (6FE5); +SDR 16 TDI (FFFF) TDO (7FFF); SDR 16 TDI (FFFF) TDO (FFFE); -SDR 16 TDI (FFFF) TDO (BEFB); +SDR 16 TDI (FFFF) TDO (BDBF); +SDR 16 TDI (FFFF) TDO (EFFF); +SDR 16 TDI (FFFF) TDO (7F2F); +SDR 16 TDI (FFFF) TDO (FFDE); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FDD); +SDR 16 TDI (FFFF) TDO (ABBF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (F3FF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFBF); +SDR 16 TDI (FFFF) TDO (EFFD); +SDR 16 TDI (FFFF) TDO (77FE); +SDR 16 TDI (FFFF) TDO (FFDF); +SDR 16 TDI (FFFF) TDO (BEF7); +SDR 16 TDI (FFFF) TDO (77FF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (BBBB); +SDR 16 TDI (FFFF) TDO (B7BF); +SDR 16 TDI (FFFF) TDO (F7FE); +SDR 16 TDI (FFFF) TDO (7DBF); +SDR 16 TDI (FFFF) TDO (F7AF); +SDR 16 TDI (FFFF) TDO (AFFE); +SDR 16 TDI (FFFF) TDO (F6FD); +SDR 16 TDI (FFFF) TDO (7BFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (B7FF); +SDR 16 TDI (FFFF) TDO (F5E7); +SDR 16 TDI (FFFF) TDO (6FFC); +SDR 16 TDI (FFFF) TDO (DFFD); +SDR 16 TDI (FFFF) TDO (BFBD); +SDR 16 TDI (FFFF) TDO (7FFB); +SDR 16 TDI (FFFF) TDO (7B33); +SDR 16 TDI (FFFF) TDO (FFDF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFF3); +SDR 16 TDI (FFFF) TDO (7FDF); +SDR 16 TDI (FFFF) TDO (EDDF); +SDR 16 TDI (FFFF) TDO (BFB7); +SDR 16 TDI (FFFF) TDO (FFFB); +SDR 16 TDI (FFFF) TDO (77FF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFD); +SDR 16 TDI (FFFF) TDO (7F7F); +SDR 16 TDI (FFFF) TDO (7FEF); +SDR 16 TDI (FFFF) TDO (F577); +SDR 16 TDI (FFFF) TDO (BFDF); +SDR 16 TDI (FFFF) TDO (FFFE); +SDR 16 TDI (FFFF) TDO (7FFE); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BF3F); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (BB7D); +SDR 16 TDI (FFFF) TDO (FDFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FDFF); +SDR 16 TDI (FFFF) TDO (7FFB); +SDR 16 TDI (FFFF) TDO (DDFF); +SDR 16 TDI (FFFF) TDO (BFF6); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (77FF); +SDR 16 TDI (FFFF) TDO (F5BE); +SDR 16 TDI (FFFF) TDO (BAFD); +SDR 16 TDI (FFFF) TDO (FFBF); +SDR 16 TDI (FFFF) TDO (7AFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFEE); +SDR 16 TDI (FFFF) TDO (DF7F); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (BDB7); +SDR 16 TDI (FFFF) TDO (7FFC); +SDR 16 TDI (FFFF) TDO (FA29); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (7E44); +SDR 16 TDI (FFFF) TDO (7EFF); +SDR 16 TDI (FFFF) TDO (BE1D); +SDR 16 TDI (FFFF) TDO (CFCA); +SDR 16 TDI (FFFF) TDO (77FF); +SDR 16 TDI (FFFF) TDO (761F); +SDR 16 TDI (FFFF) TDO (BFBB); +SDR 16 TDI (FFFF) TDO (5FFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (56FE); +SDR 16 TDI (FFFF) TDO (7FAF); +SDR 16 TDI (FFFF) TDO (4FFF); +SDR 16 TDI (FFFF) TDO (B616); +SDR 16 TDI (FFFF) TDO (D7F4); +SDR 16 TDI (FFFF) TDO (6FBB); +SDR 16 TDI (FFFF) TDO (B727); +SDR 16 TDI (FFFF) TDO (BDFF); +SDR 16 TDI (FFFF) TDO (FFF7); +SDR 16 TDI (FFFF) TDO (7E9D); +SDR 16 TDI (FFFF) TDO (BDFF); +SDR 16 TDI (FFFF) TDO (BBF5); +SDR 16 TDI (FFFF) TDO (EE6A); +SDR 16 TDI (FFFF) TDO (77FF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFC); +SDR 16 TDI (FFFF) TDO (EB49); +SDR 16 TDI (FFFF) TDO (67F3); +SDR 16 TDI (FFFF) TDO (B5D6); +SDR 16 TDI (FFFF) TDO (BDE9); +SDR 16 TDI (FFFF) TDO (BFFB); +SDR 16 TDI (FFFF) TDO (7BFF); +SDR 16 TDI (FFFF) TDO (D9D8); +SDR 16 TDI (FFFF) TDO (B3FF); +SDR 16 TDI (FFFF) TDO (FFBD); +SDR 16 TDI (FFFF) TDO (79E7); +SDR 16 TDI (FFFF) TDO (CBEF); +SDR 16 TDI (FFFF) TDO (AECE); +SDR 16 TDI (FFFF) TDO (B1FF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (B9AE); +SDR 16 TDI (FFFF) TDO (F238); +SDR 16 TDI (FFFF) TDO (7FD3); +SDR 16 TDI (FFFF) TDO (4B82); +SDR 16 TDI (FFFF) TDO (A001); +SDR 16 TDI (FFFF) TDO (7FE7); +SDR 16 TDI (FFFF) TDO (6200); +SDR 16 TDI (FFFF) TDO (3E81); +SDR 16 TDI (FFFF) TDO (A61F); +SDR 16 TDI (FFFF) TDO (07E7); +SDR 16 TDI (FFFF) TDO (78A0); +SDR 16 TDI (FFFF) TDO (075F); +SDR 16 TDI (FFFF) TDO (B118); +SDR 16 TDI (FFFF) TDO (8075); +SDR 16 TDI (FFFF) TDO (6BFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (B6AC); +SDR 16 TDI (FFFF) TDO (0A00); +SDR 16 TDI (FFFF) TDO (67A2); +SDR 16 TDI (FFFF) TDO (0022); +SDR 16 TDI (FFFF) TDO (A100); +SDR 16 TDI (FFFF) TDO (43DC); +SDR 16 TDI (FFFF) TDO (6200); +SDR 16 TDI (FFFF) TDO (1A58); +SDR 16 TDI (FFFF) TDO (A613); +SDR 16 TDI (FFFF) TDO (8787); +SDR 16 TDI (FFFF) TDO (74A0); +SDR 16 TDI (FFFF) TDO (000F); +SDR 16 TDI (FFFF) TDO (A918); +SDR 16 TDI (FFFF) TDO (007F); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFE); +SDR 16 TDI (FFFF) TDO (FFF7); +SDR 16 TDI (FFFF) TDO (6FEF); +SDR 16 TDI (FFFF) TDO (6FFE); +SDR 16 TDI (FFFF) TDO (A023); +SDR 16 TDI (FFFF) TDO (83F8); +SDR 16 TDI (FFFF) TDO (6222); +SDR 16 TDI (FFFF) TDO (19E2); +SDR 16 TDI (FFFF) TDO (AF1F); +SDR 16 TDI (FFFF) TDO (CFE7); +SDR 16 TDI (FFFF) TDO (66B0); +SDR 16 TDI (FFFF) TDO (C06F); +SDR 16 TDI (FFFF) TDO (B918); +SDR 16 TDI (FFFF) TDO (20F5); +SDR 16 TDI (FFFF) TDO (6BFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BF7B); +SDR 16 TDI (FFFF) TDO (04CF); +SDR 16 TDI (FFFF) TDO (6FE7); +SDR 16 TDI (FFFF) TDO (6E39); +SDR 16 TDI (FFFF) TDO (BC02); +SDR 16 TDI (FFFF) TDO (83FC); +SDR 16 TDI (FFFF) TDO (6200); +SDR 16 TDI (FFFF) TDO (1960); +SDR 16 TDI (FFFF) TDO (AE1F); +SDR 16 TDI (FFFF) TDO (CF8F); +SDR 16 TDI (FFFF) TDO (68BF); +SDR 16 TDI (FFFF) TDO (402F); +SDR 16 TDI (FFFF) TDO (B910); +SDR 16 TDI (FFFF) TDO (007F); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (B89F); +SDR 16 TDI (FFFF) TDO (3B3B); +SDR 16 TDI (FFFF) TDO (73EE); +SDR 16 TDI (FFFF) TDO (E666); +SDR 16 TDI (FFFF) TDO (AA23); +SDR 16 TDI (FFFF) TDO (19F4); +SDR 16 TDI (FFFF) TDO (6626); +SDR 16 TDI (FFFF) TDO (DCCC); +SDR 16 TDI (FFFF) TDO (B18F); +SDR 16 TDI (FFFF) TDO (99A3); +SDR 16 TDI (FFFF) TDO (61E8); +SDR 16 TDI (FFFF) TDO (CCE7); +SDR 16 TDI (FFFF) TDO (B899); +SDR 16 TDI (FFFF) TDO (98FA); +SDR 16 TDI (FFFF) TDO (77FF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFB); +SDR 16 TDI (FFFF) TDO (7373); +SDR 16 TDI (FFFF) TDO (6146); +SDR 16 TDI (FFFF) TDO (7777); +SDR 16 TDI (FFFF) TDO (B376); +SDR 16 TDI (FFFF) TDO (72A3); +SDR 16 TDI (FFFF) TDO (7736); +SDR 16 TDI (FFFF) TDO (3999); +SDR 16 TDI (FFFF) TDO (BB35); +SDR 16 TDI (FFFF) TDO (5998); +SDR 16 TDI (FFFF) TDO (7BDD); +SDR 16 TDI (FFFF) TDO (DDC2); +SDR 16 TDI (FFFF) TDO (B5CD); +SDR 16 TDI (FFFF) TDO (9DFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BD6F); +SDR 16 TDI (FFFF) TDO (9F9D); +SDR 16 TDI (FFFF) TDO (7BDD); +SDR 16 TDI (FFFF) TDO (CEEE); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (DBFE); +SDR 16 TDI (FFFF) TDO (6FFF); +SDR 16 TDI (FFFF) TDO (DEFF); +SDR 16 TDI (FFFF) TDO (BDFF); +SDR 16 TDI (FFFF) TDO (3FF7); +SDR 16 TDI (FFFF) TDO (6FFF); +SDR 16 TDI (FFFF) TDO (EE73); +SDR 16 TDI (FFFF) TDO (BFFB); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (E7F5); +SDR 16 TDI (FFFF) TDO (6FFF); +SDR 16 TDI (FFFF) TDO (7F7B); +SDR 16 TDI (FFFF) TDO (AD9F); +SDR 16 TDI (FFFF) TDO (FBFF); +SDR 16 TDI (FFFF) TDO (7DFC); +SDR 16 TDI (FFFF) TDO (F7BF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FDDB); +SDR 16 TDI (FFFF) TDO (7F7F); +SDR 16 TDI (FFFF) TDO (EFEF); +SDR 16 TDI (FFFF) TDO (BFFF); SDR 16 TDI (FFFF) TDO (3FFF); SDR 16 TDI (FFFF) TDO (7FFF); SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (875C); -SDR 16 TDI (FFFF) TDO (B834); -SDR 16 TDI (FFFF) TDO (47D8); -SDR 16 TDI (FFFF) TDO (807B); -SDR 16 TDI (FFFF) TDO (B23E); -SDR 16 TDI (FFFF) TDO (23ED); -SDR 16 TDI (FFFF) TDO (6FFE); -SDR 16 TDI (FFFF) TDO (7B3A); -SDR 16 TDI (FFFF) TDO (B997); -SDR 16 TDI (FFFF) TDO (192C); -SDR 16 TDI (FFFF) TDO (617A); -SDR 16 TDI (FFFF) TDO (7F0F); -SDR 16 TDI (FFFF) TDO (9000); -SDR 16 TDI (FFFF) TDO (67EA); -SDR 16 TDI (FFFF) TDO (5FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (AEFC); -SDR 16 TDI (FFFF) TDO (9420); -SDR 16 TDI (FFFF) TDO (67B8); -SDR 16 TDI (FFFF) TDO (821E); -SDR 16 TDI (FFFF) TDO (A0F8); -SDR 16 TDI (FFFF) TDO (0FD3); -SDR 16 TDI (FFFF) TDO (667E); -SDR 16 TDI (FFFF) TDO (1814); -SDR 16 TDI (FFFF) TDO (999B); -SDR 16 TDI (FFFF) TDO (980C); -SDR 16 TDI (FFFF) TDO (417A); -SDR 16 TDI (FFFF) TDO (70CD); -SDR 16 TDI (FFFF) TDO (B800); -SDR 16 TDI (FFFF) TDO (607F); -SDR 16 TDI (FFFF) TDO (6FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (B75F); -SDR 16 TDI (FFFF) TDO (763B); -SDR 16 TDI (FFFF) TDO (7FE0); -SDR 16 TDI (FFFF) TDO (109B); -SDR 16 TDI (FFFF) TDO (923C); -SDR 16 TDI (FFFF) TDO (2FF1); -SDR 16 TDI (FFFF) TDO (47FE); -SDR 16 TDI (FFFF) TDO (7CB0); -SDR 16 TDI (FFFF) TDO (BBBF); -SDR 16 TDI (FFFF) TDO (D86E); -SDR 16 TDI (FFFF) TDO (61A4); -SDR 16 TDI (FFFF) TDO (A0FF); -SDR 16 TDI (FFFF) TDO (B8C0); -SDR 16 TDI (FFFF) TDO (986B); -SDR 16 TDI (FFFF) TDO (77FF); -SDR 16 TDI (FFFF) TDO (FFFF); SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (7C20); -SDR 16 TDI (FFFF) TDO (67E1); -SDR 16 TDI (FFFF) TDO (328C); -SDR 16 TDI (FFFF) TDO (A3FC); -SDR 16 TDI (FFFF) TDO (0FF3); -SDR 16 TDI (FFFF) TDO (467E); -SDR 16 TDI (FFFF) TDO (1CA0); -SDR 16 TDI (FFFF) TDO (A23F); -SDR 16 TDI (FFFF) TDO (C02E); -SDR 16 TDI (FFFF) TDO (61A4); -SDR 16 TDI (FFFF) TDO (AC0F); -SDR 16 TDI (FFFF) TDO (9840); -SDR 16 TDI (FFFF) TDO (19FE); -SDR 16 TDI (FFFF) TDO (5FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFD7); -SDR 16 TDI (FFFF) TDO (B23B); -SDR 16 TDI (FFFF) TDO (63E6); -SDR 16 TDI (FFFF) TDO (FE67); -SDR 16 TDI (FFFF) TDO (B330); -SDR 16 TDI (FFFF) TDO (B1FE); -SDR 16 TDI (FFFF) TDO (6666); -SDR 16 TDI (FFFF) TDO (7CFC); -SDR 16 TDI (FFFF) TDO (9DCF); -SDR 16 TDI (FFFF) TDO (B9F9); -SDR 16 TDI (FFFF) TDO (51EE); -SDR 16 TDI (FFFF) TDO (EEE7); -SDR 16 TDI (FFFF) TDO (B9C9); -SDR 16 TDI (FFFF) TDO (BBFA); -SDR 16 TDI (FFFF) TDO (77FF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFDF); -SDR 16 TDI (FFFF) TDO (3773); -SDR 16 TDI (FFFF) TDO (6956); -SDR 16 TDI (FFFF) TDO (6777); -SDR 16 TDI (FFFF) TDO (9273); -SDR 16 TDI (FFFF) TDO (26A1); -SDR 16 TDI (FFFF) TDO (5626); -SDR 16 TDI (FFFF) TDO (7DCC); -SDR 16 TDI (FFFF) TDO (B985); -SDR 16 TDI (FFFF) TDO (1C9D); -SDR 16 TDI (FFFF) TDO (7B44); -SDR 16 TDI (FFFF) TDO (4442); -SDR 16 TDI (FFFF) TDO (B5CD); -SDR 16 TDI (FFFF) TDO (917F); +SDR 16 TDI (FFFF) TDO (7EEF); +SDR 16 TDI (FFFF) TDO (7FF7); +SDR 16 TDI (FFFF) TDO (F7FF); +SDR 16 TDI (FFFF) TDO (B7F7); SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (9FF9); -SDR 16 TDI (FFFF) TDO (FBDF); -SDR 16 TDI (FFFF) TDO (53CF); +SDR 16 TDI (FFFF) TDO (7FF7); SDR 16 TDI (FFFF) TDO (FEEE); -SDR 16 TDI (FFFF) TDO (BBFD); -SDR 16 TDI (FFFF) TDO (FFEE); -SDR 16 TDI (FFFF) TDO (6FDE); -SDR 16 TDI (FFFF) TDO (DFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (7BFB); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); SDR 16 TDI (FFFF) TDO (B3FF); -SDR 16 TDI (FFFF) TDO (FFFE); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (7DFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFFD); -SDR 16 TDI (FFFF) TDO (7BF7); -SDR 16 TDI (FFFF) TDO (7E6D); -SDR 16 TDI (FFFF) TDO (BEDF); -SDR 16 TDI (FFFF) TDO (FEFB); -SDR 16 TDI (FFFF) TDO (7B7F); -SDR 16 TDI (FFFF) TDO (F7FF); -SDR 16 TDI (FFFF) TDO (BFFE); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (7577); -SDR 16 TDI (FFFF) TDO (6FFD); -SDR 16 TDI (FFFF) TDO (F7FF); -SDR 16 TDI (FFFF) TDO (B7DD); -SDR 16 TDI (FFFF) TDO (FFFB); -SDR 16 TDI (FFFF) TDO (777D); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BBFF); -SDR 16 TDI (FFFF) TDO (D5D7); -SDR 16 TDI (FFFF) TDO (6FFB); -SDR 16 TDI (FFFF) TDO (BF7F); -SDR 16 TDI (FFFF) TDO (BFF7); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7BFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (AFFF); -SDR 16 TDI (FFFF) TDO (7FF7); -SDR 16 TDI (FFFF) TDO (6FFB); -SDR 16 TDI (FFFF) TDO (7BFF); -SDR 16 TDI (FFFF) TDO (B7FD); -SDR 16 TDI (FFFF) TDO (FFF7); -SDR 16 TDI (FFFF) TDO (77FD); -SDR 16 TDI (FFFF) TDO (FFAF); -SDR 16 TDI (FFFF) TDO (BFBF); -SDR 16 TDI (FFFF) TDO (AD77); -SDR 16 TDI (FFFF) TDO (7FBF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (AFFF); -SDR 16 TDI (FFFF) TDO (F57F); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (F7FF); -SDR 16 TDI (FFFF) TDO (BFDF); -SDR 16 TDI (FFFF) TDO (FFFD); -SDR 16 TDI (FFFF) TDO (7D76); -SDR 16 TDI (FFFF) TDO (FDFD); -SDR 16 TDI (FFFF) TDO (BB7F); -SDR 16 TDI (FFFF) TDO (FFDA); -SDR 16 TDI (FFFF) TDO (77FF); -SDR 16 TDI (FFFF) TDO (FBBF); -SDR 16 TDI (FFFF) TDO (BFF7); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (BDFB); -SDR 16 TDI (FFFF) TDO (7FFB); -SDR 16 TDI (FFFF) TDO (FF5E); -SDR 16 TDI (FFFF) TDO (B5DF); -SDR 16 TDI (FFFF) TDO (D7FF); -SDR 16 TDI (FFFF) TDO (7FFB); -SDR 16 TDI (FFFF) TDO (F9BE); -SDR 16 TDI (FFFF) TDO (BD3F); -SDR 16 TDI (FFFF) TDO (FEF3); -SDR 16 TDI (FFFF) TDO (7EF7); -SDR 16 TDI (FFFF) TDO (FEFF); -SDR 16 TDI (FFFF) TDO (BFEF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFDF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (EFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFFA); -SDR 16 TDI (FFFF) TDO (5DFF); -SDR 16 TDI (FFFF) TDO (EFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FDFF); -SDR 16 TDI (FFFF) TDO (77FF); -SDR 16 TDI (FFFF) TDO (DFBF); -SDR 16 TDI (FFFF) TDO (BFFE); -SDR 16 TDI (FFFF) TDO (FBFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (5FFF); -SDR 16 TDI (FFFF) TDO (FFBF); -SDR 16 TDI (FFFF) TDO (AADF); -SDR 16 TDI (FFFF) TDO (FFF6); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (EA7E); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FB7B); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (DDFF); -SDR 16 TDI (FFFF) TDO (BFF7); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FEDB); -SDR 16 TDI (FFFF) TDO (7FFB); -SDR 16 TDI (FFFF) TDO (FF7F); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (D7FF); -SDR 16 TDI (FFFF) TDO (7BFD); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BB5F); -SDR 16 TDI (FFFF) TDO (FFEF); -SDR 16 TDI (FFFF) TDO (5DFB); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFF6); -SDR 16 TDI (FFFF) TDO (77EF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (F7FB); -SDR 16 TDI (FFFF) TDO (5FDF); -SDR 16 TDI (FFFF) TDO (EFFB); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (F7FF); -SDR 16 TDI (FFFF) TDO (7FFE); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (BF7F); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (5FFD); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (77FF); -SDR 16 TDI (FFFF) TDO (EFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (7FF7); -SDR 16 TDI (FFFF) TDO (FFEF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (DFFF); -SDR 16 TDI (FFFF) TDO (5FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7FF5); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFFB); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (DFFF); -SDR 16 TDI (FFFF) TDO (5FFF); -SDR 16 TDI (FFFF) TDO (FFDF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFF9); -SDR 16 TDI (FFFF) TDO (77FF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FBFF); -SDR 16 TDI (FFFF) TDO (4FBF); -SDR 16 TDI (FFFF) TDO (FFFB); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (F7FF); -SDR 16 TDI (FFFF) TDO (7FF9); -SDR 16 TDI (FFFF) TDO (7FFF); SDR 16 TDI (FFFF) TDO (BEFF); -SDR 16 TDI (FFFF) TDO (DFFF); +SDR 16 TDI (FFFF) TDO (7FDD); +SDR 16 TDI (FFFF) TDO (BDFF); +SDR 16 TDI (FFFF) TDO (BDBF); +SDR 16 TDI (FFFF) TDO (FFDF); SDR 16 TDI (FFFF) TDO (7FFF); SDR 16 TDI (FFFF) TDO (FFFF); SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFEE); -SDR 16 TDI (FFFF) TDO (5FFF); +SDR 16 TDI (FFFF) TDO (7FFD); +SDR 16 TDI (FFFF) TDO (6FFF); +SDR 16 TDI (FFFF) TDO (7FFD); +SDR 16 TDI (FFFF) TDO (B7DF); +SDR 16 TDI (FFFF) TDO (77FF); +SDR 16 TDI (FFFF) TDO (7BF4); +SDR 16 TDI (FFFF) TDO (FF7F); +SDR 16 TDI (FFFF) TDO (BBFF); +SDR 16 TDI (FFFF) TDO (FFDF); +SDR 16 TDI (FFFF) TDO (7FED); +SDR 16 TDI (FFFF) TDO (DDFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BBBF); +SDR 16 TDI (FFFF) TDO (D7FB); +SDR 16 TDI (FFFF) TDO (7FEF); +SDR 16 TDI (FFFF) TDO (F6FE); +SDR 16 TDI (FFFF) TDO (BD77); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (F7FF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FDFD); +SDR 16 TDI (FFFF) TDO (7F7F); +SDR 16 TDI (FFFF) TDO (FFDF); +SDR 16 TDI (FFFF) TDO (BDFF); +SDR 16 TDI (FFFF) TDO (3FFB); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BAFF); +SDR 16 TDI (FFFF) TDO (FDFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFDA); +SDR 16 TDI (FFFF) TDO (BDBF); +SDR 16 TDI (FFFF) TDO (FBFF); +SDR 16 TDI (FFFF) TDO (7DFF); +SDR 16 TDI (FFFF) TDO (DFFD); +SDR 16 TDI (FFFF) TDO (BD7F); +SDR 16 TDI (FFFF) TDO (DEF7); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FE7F); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFBB); +SDR 16 TDI (FFFF) TDO (7FFF); SDR 16 TDI (FFFF) TDO (FFFF); SDR 16 TDI (FFFF) TDO (BFFD); -SDR 16 TDI (FFFF) TDO (EFFD); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFB); +SDR 16 TDI (FFFF) TDO (FFF7); +SDR 16 TDI (FFFF) TDO (BFF5); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FDD); +SDR 16 TDI (FFFF) TDO (E7DF); +SDR 16 TDI (FFFF) TDO (BFBF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7EF5); +SDR 16 TDI (FFFF) TDO (DFDF); +SDR 16 TDI (FFFF) TDO (BFFE); +SDR 16 TDI (FFFF) TDO (FEFF); SDR 16 TDI (FFFF) TDO (7FFF); SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFD); +SDR 16 TDI (FFFF) TDO (E9FB); +SDR 16 TDI (FFFF) TDO (7FEC); +SDR 16 TDI (FFFF) TDO (FFDE); +SDR 16 TDI (FFFF) TDO (BF77); +SDR 16 TDI (FFFF) TDO (E7F7); +SDR 16 TDI (FFFF) TDO (7CCC); +SDR 16 TDI (FFFF) TDO (FF9D); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FF3B); +SDR 16 TDI (FFFF) TDO (7EFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FB77); +SDR 16 TDI (FFFF) TDO (7BFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFEB); +SDR 16 TDI (FFFF) TDO (BDFE); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); SDR 16 TDI (FFFF) TDO (B7FF); -SDR 16 TDI (FFFF) TDO (EFFF); +SDR 16 TDI (FFFF) TDO (BD3F); +SDR 16 TDI (FFFF) TDO (DFF7); +SDR 16 TDI (FFFF) TDO (7FF9); +SDR 16 TDI (FFFF) TDO (ED9F); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (7FFF); SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (BFFF); SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (5FFF); +SDR 16 TDI (FFFF) TDO (BDFF); +SDR 16 TDI (FFFF) TDO (DFAF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFDB); +SDR 16 TDI (FFFF) TDO (BAF6); SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7B3F); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FBFB); +SDR 16 TDI (FFFF) TDO (7D7E); +SDR 16 TDI (FFFF) TDO (EFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (AF7F); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BF7E); +SDR 16 TDI (FFFF) TDO (76F7); +SDR 16 TDI (FFFF) TDO (7FEE); +SDR 16 TDI (FFFF) TDO (BCFE); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (7FF7); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (7F57); +SDR 16 TDI (FFFF) TDO (BBFF); +SDR 16 TDI (FFFF) TDO (BFF7); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BBF7); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFD); +SDR 16 TDI (FFFF) TDO (F7DF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FD7F); +SDR 16 TDI (FFFF) TDO (B7BF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FEF); +SDR 16 TDI (FFFF) TDO (FF5F); SDR 16 TDI (FFFF) TDO (BFFF); SDR 16 TDI (FFFF) TDO (FDFF); -SDR 16 TDI (FFFF) TDO (7FFD); +SDR 16 TDI (FFFF) TDO (7EFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (BDBF); +SDR 16 TDI (FFFF) TDO (DBFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BE7F); +SDR 16 TDI (FFFF) TDO (AEB7); +SDR 16 TDI (FFFF) TDO (7FFE); +SDR 16 TDI (FFFF) TDO (BFBA); +SDR 16 TDI (FFFF) TDO (BDF6); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (7D5F); +SDR 16 TDI (FFFF) TDO (7FFB); +SDR 16 TDI (FFFF) TDO (BDDF); +SDR 16 TDI (FFFF) TDO (FFEB); +SDR 16 TDI (FFFF) TDO (7FBD); SDR 16 TDI (FFFF) TDO (DFFF); -SDR 16 TDI (FFFF) TDO (BFDF); -SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFEF); +SDR 16 TDI (FFFF) TDO (EF7F); SDR 16 TDI (FFFF) TDO (7FFF); SDR 16 TDI (FFFF) TDO (FFFF); SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (5FFF); -SDR 16 TDI (FFFF) TDO (EAEF); -SDR 16 TDI (FFFF) TDO (BBBF); -SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (EBDF); SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (7FB6); +SDR 16 TDI (FFFF) TDO (BE5B); +SDR 16 TDI (FFFF) TDO (57F9); +SDR 16 TDI (FFFF) TDO (6D3F); +SDR 16 TDI (FFFF) TDO (5DFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (CFDF); +SDR 16 TDI (FFFF) TDO (77BF); +SDR 16 TDI (FFFF) TDO (DFFF); +SDR 16 TDI (FFFF) TDO (BEFE); +SDR 16 TDI (FFFF) TDO (FEF5); +SDR 16 TDI (FFFF) TDO (6BFF); SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (B6AE); +SDR 16 TDI (FFFF) TDO (FDBF); +SDR 16 TDI (FFFF) TDO (6FF3); +SDR 16 TDI (FFFF) TDO (BEFF); SDR 16 TDI (FFFF) TDO (BFFF); SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (5FFF); -SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FF7); +SDR 16 TDI (FFFF) TDO (F7FD); SDR 16 TDI (FFFF) TDO (BF7F); +SDR 16 TDI (FFFF) TDO (FAFC); +SDR 16 TDI (FFFF) TDO (7DDF); SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (7FF8); -SDR 16 TDI (FFFF) TDO (FFBF); +SDR 16 TDI (FFFF) TDO (BFB5); +SDR 16 TDI (FFFF) TDO (DFFF); +SDR 16 TDI (FFFF) TDO (7DFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (B9AE); +SDR 16 TDI (FFFF) TDO (7FD7); +SDR 16 TDI (FFFF) TDO (7FFB); +SDR 16 TDI (FFFF) TDO (EFBF); +SDR 16 TDI (FFFF) TDO (B7FE); +SDR 16 TDI (FFFF) TDO (EFFF); +SDR 16 TDI (FFFF) TDO (7DFD); +SDR 16 TDI (FFFF) TDO (FBDF); +SDR 16 TDI (FFFF) TDO (BDAF); +SDR 16 TDI (FFFF) TDO (FFEF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FEDF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FCF5); +SDR 16 TDI (FFFF) TDO (6BFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FF7F); +SDR 16 TDI (FFFF) TDO (7EFF); +SDR 16 TDI (FFFF) TDO (DEEF); +SDR 16 TDI (FFFF) TDO (B5FF); +SDR 16 TDI (FFFF) TDO (F7FD); +SDR 16 TDI (FFFF) TDO (7FBF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (AEFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (DFFF); +SDR 16 TDI (FFFF) TDO (BBDF); +SDR 16 TDI (FFFF) TDO (7FEA); +SDR 16 TDI (FFFF) TDO (75FF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (6EF9); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FDFB); +SDR 16 TDI (FFFF) TDO (AFEF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (777F); +SDR 16 TDI (FFFF) TDO (FFBB); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7F6F); +SDR 16 TDI (FFFF) TDO (7DEF); +SDR 16 TDI (FFFF) TDO (BFFD); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFD); +SDR 16 TDI (FFFF) TDO (6FFF); +SDR 16 TDI (FFFF) TDO (F5FB); SDR 16 TDI (FFFF) TDO (BF77); +SDR 16 TDI (FFFF) TDO (FFBB); +SDR 16 TDI (FFFF) TDO (7FEC); SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (B7FF); +SDR 16 TDI (FFFF) TDO (FBFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (BBFF); SDR 16 TDI (FFFF) TDO (7FFF); SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFC); +SDR 16 TDI (FFFF) TDO (8EDB); +SDR 16 TDI (FFFF) TDO (6FF9); +SDR 16 TDI (FFFF) TDO (973B); +SDR 16 TDI (FFFF) TDO (A7BF); +SDR 16 TDI (FFFF) TDO (4BFD); +SDR 16 TDI (FFFF) TDO (6FFE); +SDR 16 TDI (FFFF) TDO (FDDD); +SDR 16 TDI (FFFF) TDO (BAFF); +SDR 16 TDI (FFFF) TDO (BFEF); +SDR 16 TDI (FFFF) TDO (7BAF); +SDR 16 TDI (FFFF) TDO (BDFF); +SDR 16 TDI (FFFF) TDO (BF33); +SDR 16 TDI (FFFF) TDO (9F7F); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BBFF); +SDR 16 TDI (FFFF) TDO (77FD); +SDR 16 TDI (FFFF) TDO (7F77); +SDR 16 TDI (FFFF) TDO (7EFF); +SDR 16 TDI (FFFF) TDO (BEF3); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7AA5); +SDR 16 TDI (FFFF) TDO (DBFB); +SDR 16 TDI (FFFF) TDO (AFBF); +SDR 16 TDI (FFFF) TDO (EB7D); +SDR 16 TDI (FFFF) TDO (7EFF); +SDR 16 TDI (FFFF) TDO (6FEF); +SDR 16 TDI (FFFF) TDO (BBFE); +SDR 16 TDI (FFFF) TDO (FFEA); +SDR 16 TDI (FFFF) TDO (77FF); +SDR 16 TDI (FFFF) TDO (FFFF); SDR 16 TDI (FFFF) TDO (BFFF); -SDR 16 TDI (FFFF) TDO (FFFE); -SDR 16 TDI (FFFF) TDO (5FFD); -SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FD26); +SDR 16 TDI (FFFF) TDO (77FF); +SDR 16 TDI (FFFF) TDO (E9C4); +SDR 16 TDI (FFFF) TDO (B94E); +SDR 16 TDI (FFFF) TDO (F7B2); +SDR 16 TDI (FFFF) TDO (755B); +SDR 16 TDI (FFFF) TDO (37BF); +SDR 16 TDI (FFFF) TDO (BFEF); +SDR 16 TDI (FFFF) TDO (D4DF); +SDR 16 TDI (FFFF) TDO (6F5F); +SDR 16 TDI (FFFF) TDO (DEDF); +SDR 16 TDI (FFFF) TDO (BFDD); +SDR 16 TDI (FFFF) TDO (78FF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (B66E); +SDR 16 TDI (FFFF) TDO (260D); +SDR 16 TDI (FFFF) TDO (7DD4); +SDR 16 TDI (FFFF) TDO (01F6); +SDR 16 TDI (FFFF) TDO (B2A0); +SDR 16 TDI (FFFF) TDO (2AE3); +SDR 16 TDI (FFFF) TDO (60A0); +SDR 16 TDI (FFFF) TDO (75A7); +SDR 16 TDI (FFFF) TDO (BE1F); +SDR 16 TDI (FFFF) TDO (382E); +SDR 16 TDI (FFFF) TDO (6F8F); +SDR 16 TDI (FFFF) TDO (CC0F); +SDR 16 TDI (FFFF) TDO (B19B); +SDR 16 TDI (FFFF) TDO (E075); +SDR 16 TDI (FFFF) TDO (6BFF); +SDR 16 TDI (FFFF) TDO (FFFF); SDR 16 TDI (FFFF) TDO (BFED); -SDR 16 TDI (FFFF) TDO (DFFD); +SDR 16 TDI (FFFF) TDO (4623); +SDR 16 TDI (FFFF) TDO (7EF4); +SDR 16 TDI (FFFF) TDO (E941); +SDR 16 TDI (FFFF) TDO (AB28); +SDR 16 TDI (FFFF) TDO (2B75); +SDR 16 TDI (FFFF) TDO (6660); +SDR 16 TDI (FFFF) TDO (7BA7); +SDR 16 TDI (FFFF) TDO (A19E); +SDR 16 TDI (FFFF) TDO (802F); +SDR 16 TDI (FFFF) TDO (700F); +SDR 16 TDI (FFFF) TDO (CC0F); +SDR 16 TDI (FFFF) TDO (A802); +SDR 16 TDI (FFFF) TDO (E07F); +SDR 16 TDI (FFFF) TDO (7DFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (B97E); +SDR 16 TDI (FFFF) TDO (2FFF); +SDR 16 TDI (FFFF) TDO (77ED); +SDR 16 TDI (FFFF) TDO (802F); +SDR 16 TDI (FFFF) TDO (B7FA); +SDR 16 TDI (FFFF) TDO (77FF); +SDR 16 TDI (FFFF) TDO (7FE3); +SDR 16 TDI (FFFF) TDO (764A); +SDR 16 TDI (FFFF) TDO (A1EF); +SDR 16 TDI (FFFF) TDO (C0B1); +SDR 16 TDI (FFFF) TDO (70CF); +SDR 16 TDI (FFFF) TDO (D0CF); +SDR 16 TDI (FFFF) TDO (B987); +SDR 16 TDI (FFFF) TDO (8075); +SDR 16 TDI (FFFF) TDO (6BFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BD7B); +SDR 16 TDI (FFFF) TDO (CDA3); +SDR 16 TDI (FFFF) TDO (7FE1); +SDR 16 TDI (FFFF) TDO (6033); +SDR 16 TDI (FFFF) TDO (A426); +SDR 16 TDI (FFFF) TDO (53F0); +SDR 16 TDI (FFFF) TDO (7201); +SDR 16 TDI (FFFF) TDO (1B4A); +SDR 16 TDI (FFFF) TDO (B81F); +SDR 16 TDI (FFFF) TDO (8036); +SDR 16 TDI (FFFF) TDO (630F); +SDR 16 TDI (FFFF) TDO (C0CF); +SDR 16 TDI (FFFF) TDO (B804); +SDR 16 TDI (FFFF) TDO (817F); SDR 16 TDI (FFFF) TDO (7FFF); SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (B6FF); +SDR 16 TDI (FFFF) TDO (BEAF); +SDR 16 TDI (FFFF) TDO (3FBA); +SDR 16 TDI (FFFF) TDO (63E7); +SDR 16 TDI (FFFF) TDO (626F); +SDR 16 TDI (FFFF) TDO (BB3B); +SDR 16 TDI (FFFF) TDO (39F3); +SDR 16 TDI (FFFF) TDO (6662); +SDR 16 TDI (FFFF) TDO (FEEE); +SDR 16 TDI (FFFF) TDO (BDC7); +SDR 16 TDI (FFFF) TDO (B9BB); +SDR 16 TDI (FFFF) TDO (778C); +SDR 16 TDI (FFFF) TDO (0CE7); +SDR 16 TDI (FFFF) TDO (B9B0); +SDR 16 TDI (FFFF) TDO (A0EB); +SDR 16 TDI (FFFF) TDO (77FF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFBB); +SDR 16 TDI (FFFF) TDO (7333); +SDR 16 TDI (FFFF) TDO (6957); +SDR 16 TDI (FFFF) TDO (7767); +SDR 16 TDI (FFFF) TDO (B373); +SDR 16 TDI (FFFF) TDO (70AB); +SDR 16 TDI (FFFF) TDO (7776); +SDR 16 TDI (FFFF) TDO (7C44); +SDR 16 TDI (FFFF) TDO (A885); +SDR 16 TDI (FFFF) TDO (9C91); +SDR 16 TDI (FFFF) TDO (62DD); +SDR 16 TDI (FFFF) TDO (CDCA); +SDR 16 TDI (FFFF) TDO (B58D); +SDR 16 TDI (FFFF) TDO (9DFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BDFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (77CE); +SDR 16 TDI (FFFF) TDO (EEFF); +SDR 16 TDI (FFFF) TDO (BFBF); +SDR 16 TDI (FFFF) TDO (BFE7); +SDR 16 TDI (FFFF) TDO (6EFF); +SDR 16 TDI (FFFF) TDO (F777); +SDR 16 TDI (FFFF) TDO (AEFF); +SDR 16 TDI (FFFF) TDO (7FF7); +SDR 16 TDI (FFFF) TDO (6EFF); +SDR 16 TDI (FFFF) TDO (6EFF); +SDR 16 TDI (FFFF) TDO (B3F7); +SDR 16 TDI (FFFF) TDO (F7FF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (F7EF); +SDR 16 TDI (FFFF) TDO (6FF7); +SDR 16 TDI (FFFF) TDO (FDF7); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (D7FF); +SDR 16 TDI (FFFF) TDO (76FE); +SDR 16 TDI (FFFF) TDO (BFFD); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (DFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (BFFE); +SDR 16 TDI (FFFF) TDO (BBFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (BE75); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (B73E); +SDR 16 TDI (FFFF) TDO (BA7B); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (7FF7); +SDR 16 TDI (FFFF) TDO (FDF7); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FDFD); +SDR 16 TDI (FFFF) TDO (7B7B); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BD7F); +SDR 16 TDI (FFFF) TDO (FFFD); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (AFFF); +SDR 16 TDI (FFFF) TDO (FFB5); +SDR 16 TDI (FFFF) TDO (77F7); +SDR 16 TDI (FFFF) TDO (FBFF); +SDR 16 TDI (FFFF) TDO (BF7F); +SDR 16 TDI (FFFF) TDO (D7FF); +SDR 16 TDI (FFFF) TDO (77FF); +SDR 16 TDI (FFFF) TDO (DFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (DFFF); +SDR 16 TDI (FFFF) TDO (7BFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BD7F); +SDR 16 TDI (FFFF) TDO (FDFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (ABBB); +SDR 16 TDI (FFFF) TDO (FBEF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (F6EE); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7F77); +SDR 16 TDI (FFFF) TDO (7EF6); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FDFD); +SDR 16 TDI (FFFF) TDO (7FBF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (BFFE); +SDR 16 TDI (FFFF) TDO (DFFF); +SDR 16 TDI (FFFF) TDO (7DFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FDEF); +SDR 16 TDI (FFFF) TDO (7FFE); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (AFFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (6DBD); +SDR 16 TDI (FFFF) TDO (7FDF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FB73); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFEE); SDR 16 TDI (FFFF) TDO (FFFF); SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (D95F); -SDR 16 TDI (FFFF) TDO (BDCF); SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (5FFF); +SDR 16 TDI (FFFF) TDO (BFFD); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FEF); +SDR 16 TDI (FFFF) TDO (FFFD); +SDR 16 TDI (FFFF) TDO (B7EF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (7F7F); +SDR 16 TDI (FFFF) TDO (EFFF); +SDR 16 TDI (FFFF) TDO (B7FF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FBD); +SDR 16 TDI (FFFF) TDO (EFBF); +SDR 16 TDI (FFFF) TDO (BFDF); +SDR 16 TDI (FFFF) TDO (FF7F); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFD); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FF7); +SDR 16 TDI (FFFF) TDO (EFFF); +SDR 16 TDI (FFFF) TDO (B7FA); +SDR 16 TDI (FFFF) TDO (6FFD); +SDR 16 TDI (FFFF) TDO (7DFF); +SDR 16 TDI (FFFF) TDO (7FBE); +SDR 16 TDI (FFFF) TDO (BF7F); +SDR 16 TDI (FFFF) TDO (FDFF); +SDR 16 TDI (FFFF) TDO (7F7B); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FB75); +SDR 16 TDI (FFFF) TDO (7FFF); SDR 16 TDI (FFFF) TDO (FFFF); SDR 16 TDI (FFFF) TDO (BFFF); SDR 16 TDI (FFFF) TDO (FDDF); SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (7FFB); +SDR 16 TDI (FFFF) TDO (AFDF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (6EDB); +SDR 16 TDI (FFFF) TDO (FFEF); +SDR 16 TDI (FFFF) TDO (B7FF); +SDR 16 TDI (FFFF) TDO (FEF3); +SDR 16 TDI (FFFF) TDO (7FFD); +SDR 16 TDI (FFFF) TDO (DF7F); +SDR 16 TDI (FFFF) TDO (BFD7); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BEDF); +SDR 16 TDI (FFFF) TDO (5FFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FDF7); +SDR 16 TDI (FFFF) TDO (BF7F); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7DFF); +SDR 16 TDI (FFFF) TDO (E775); +SDR 16 TDI (FFFF) TDO (ADFF); +SDR 16 TDI (FFFF) TDO (FBFF); +SDR 16 TDI (FFFF) TDO (75FF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFDF); +SDR 16 TDI (FFFF) TDO (7FEE); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (B9DE); +SDR 16 TDI (FFFF) TDO (7FF7); +SDR 16 TDI (FFFF) TDO (77FF); +SDR 16 TDI (FFFF) TDO (DDEF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (BF7B); +SDR 16 TDI (FFFF) TDO (6FBF); +SDR 16 TDI (FFFF) TDO (FBFF); +SDR 16 TDI (FFFF) TDO (BBFF); +SDR 16 TDI (FFFF) TDO (FAFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BDFF); +SDR 16 TDI (FFFF) TDO (FFDB); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (EFBF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (75FB); +SDR 16 TDI (FFFF) TDO (F77F); +SDR 16 TDI (FFFF) TDO (AFFF); +SDR 16 TDI (FFFF) TDO (FDBD); +SDR 16 TDI (FFFF) TDO (7FEB); +SDR 16 TDI (FFFF) TDO (EFFF); +SDR 16 TDI (FFFF) TDO (BFFB); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFEF); +SDR 16 TDI (FFFF) TDO (6FFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (7BF7); +SDR 16 TDI (FFFF) TDO (B66E); +SDR 16 TDI (FFFF) TDO (BBFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (BDE5); +SDR 16 TDI (FFFF) TDO (BBDF); +SDR 16 TDI (FFFF) TDO (FF7E); +SDR 16 TDI (FFFF) TDO (767F); +SDR 16 TDI (FFFF) TDO (FBFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FAFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (A75F); +SDR 16 TDI (FFFF) TDO (FF7B); +SDR 16 TDI (FFFF) TDO (6BFF); +SDR 16 TDI (FFFF) TDO (D7DF); +SDR 16 TDI (FFFF) TDO (BFBB); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (7F77); +SDR 16 TDI (FFFF) TDO (7EF9); +SDR 16 TDI (FFFF) TDO (ADFF); +SDR 16 TDI (FFFF) TDO (FBCB); +SDR 16 TDI (FFFF) TDO (7FF9); +SDR 16 TDI (FFFF) TDO (FDDF); +SDR 16 TDI (FFFF) TDO (BFFD); +SDR 16 TDI (FFFF) TDO (FFF5); +SDR 16 TDI (FFFF) TDO (6BFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (AEFF); +SDR 16 TDI (FFFF) TDO (7EEF); +SDR 16 TDI (FFFF) TDO (7FF7); +SDR 16 TDI (FFFF) TDO (FBF6); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (E7FF); +SDR 16 TDI (FFFF) TDO (6BFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (BFDF); +SDR 16 TDI (FFFF) TDO (DF7F); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (BFBF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (DFFF); +SDR 16 TDI (FFFF) TDO (7DFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (A65F); +SDR 16 TDI (FFFF) TDO (FFFD); +SDR 16 TDI (FFFF) TDO (7FFE); +SDR 16 TDI (FFFF) TDO (FF7F); +SDR 16 TDI (FFFF) TDO (A7FF); +SDR 16 TDI (FFFF) TDO (FFFB); +SDR 16 TDI (FFFF) TDO (7FBF); +SDR 16 TDI (FFFF) TDO (FFE7); +SDR 16 TDI (FFFF) TDO (BEFE); +SDR 16 TDI (FFFF) TDO (FEFF); +SDR 16 TDI (FFFF) TDO (77DB); +SDR 16 TDI (FFFF) TDO (DB7F); +SDR 16 TDI (FFFF) TDO (BDDF); +SDR 16 TDI (FFFF) TDO (FBF5); +SDR 16 TDI (FFFF) TDO (6BFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (AFFE); +SDR 16 TDI (FFFF) TDO (FEBF); +SDR 16 TDI (FFFF) TDO (6FF3); +SDR 16 TDI (FFFF) TDO (2B3F); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFD); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FBBF); +SDR 16 TDI (FFFF) TDO (AFFF); +SDR 16 TDI (FFFF) TDO (F7F7); +SDR 16 TDI (FFFF) TDO (7F7F); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (BD77); +SDR 16 TDI (FFFF) TDO (FFEA); +SDR 16 TDI (FFFF) TDO (75FF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BBFF); +SDR 16 TDI (FFFF) TDO (7FEF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFD); +SDR 16 TDI (FFFF) TDO (9EEF); +SDR 16 TDI (FFFF) TDO (FEFB); +SDR 16 TDI (FFFF) TDO (7DFD); +SDR 16 TDI (FFFF) TDO (FFFD); +SDR 16 TDI (FFFF) TDO (BDFF); +SDR 16 TDI (FFFF) TDO (BFFD); +SDR 16 TDI (FFFF) TDO (6FFE); +SDR 16 TDI (FFFF) TDO (EFEF); +SDR 16 TDI (FFFF) TDO (BFFB); +SDR 16 TDI (FFFF) TDO (B37F); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (9FFD); +SDR 16 TDI (FFFF) TDO (FBFF); +SDR 16 TDI (FFFF) TDO (7FFD); +SDR 16 TDI (FFFF) TDO (FFEB); +SDR 16 TDI (FFFF) TDO (BFFE); +SDR 16 TDI (FFFF) TDO (FFFE); +SDR 16 TDI (FFFF) TDO (6FFF); +SDR 16 TDI (FFFF) TDO (F9DF); +SDR 16 TDI (FFFF) TDO (BFBF); +SDR 16 TDI (FFFF) TDO (EDDF); +SDR 16 TDI (FFFF) TDO (6A9F); +SDR 16 TDI (FFFF) TDO (FBFF); +SDR 16 TDI (FFFF) TDO (BEEE); +SDR 16 TDI (FFFF) TDO (F77F); +SDR 16 TDI (FFFF) TDO (5FFF); SDR 16 TDI (FFFF) TDO (FFFF); SDR 16 TDI (FFFF) TDO (9FFF); +SDR 16 TDI (FFFF) TDO (FD2F); +SDR 16 TDI (FFFF) TDO (4FFB); +SDR 16 TDI (FFFF) TDO (C5CD); +SDR 16 TDI (FFFF) TDO (BF7F); +SDR 16 TDI (FFFF) TDO (D6F7); +SDR 16 TDI (FFFF) TDO (773F); +SDR 16 TDI (FFFF) TDO (FBE1); +SDR 16 TDI (FFFF) TDO (9DDF); +SDR 16 TDI (FFFF) TDO (97EB); +SDR 16 TDI (FFFF) TDO (675D); +SDR 16 TDI (FFFF) TDO (95CF); +SDR 16 TDI (FFFF) TDO (BE4D); +SDR 16 TDI (FFFF) TDO (5D7F); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BDFF); +SDR 16 TDI (FFFF) TDO (BAD6); +SDR 16 TDI (FFFF) TDO (7BFD); +SDR 16 TDI (FFFF) TDO (BB37); +SDR 16 TDI (FFFF) TDO (A7E5); +SDR 16 TDI (FFFF) TDO (FFFE); +SDR 16 TDI (FFFF) TDO (4DFF); +SDR 16 TDI (FFFF) TDO (55DE); +SDR 16 TDI (FFFF) TDO (8FFE); +SDR 16 TDI (FFFF) TDO (EDF5); +SDR 16 TDI (FFFF) TDO (5EA7); +SDR 16 TDI (FFFF) TDO (7BFF); +SDR 16 TDI (FFFF) TDO (B9F7); +SDR 16 TDI (FFFF) TDO (E6FB); +SDR 16 TDI (FFFF) TDO (57FF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (9FFC); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (77E6); +SDR 16 TDI (FFFF) TDO (7EFA); +SDR 16 TDI (FFFF) TDO (BEFF); +SDR 16 TDI (FFFF) TDO (7FF9); +SDR 16 TDI (FFFF) TDO (7BF3); +SDR 16 TDI (FFFF) TDO (FEBF); +SDR 16 TDI (FFFF) TDO (B33F); +SDR 16 TDI (FFFF) TDO (FA1E); +SDR 16 TDI (FFFF) TDO (5BFA); +SDR 16 TDI (FFFF) TDO (EF3F); +SDR 16 TDI (FFFF) TDO (BFFB); +SDR 16 TDI (FFFF) TDO (BBFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (8B5E); +SDR 16 TDI (FFFF) TDO (702F); +SDR 16 TDI (FFFF) TDO (47DF); +SDR 16 TDI (FFFF) TDO (FF12); +SDR 16 TDI (FFFF) TDO (B69F); +SDR 16 TDI (FFFF) TDO (C3E0); +SDR 16 TDI (FFFF) TDO (60BD); +SDR 16 TDI (FFFF) TDO (FF2C); +SDR 16 TDI (FFFF) TDO (8A5F); +SDR 16 TDI (FFFF) TDO (1AA1); +SDR 16 TDI (FFFF) TDO (7CC2); +SDR 16 TDI (FFFF) TDO (FA2F); +SDR 16 TDI (FFFF) TDO (B000); +SDR 16 TDI (FFFF) TDO (60F4); +SDR 16 TDI (FFFF) TDO (7BFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (AFFC); +SDR 16 TDI (FFFF) TDO (7203); +SDR 16 TDI (FFFF) TDO (47BD); +SDR 16 TDI (FFFF) TDO (FCB1); +SDR 16 TDI (FFFF) TDO (AE9C); +SDR 16 TDI (FFFF) TDO (33D0); +SDR 16 TDI (FFFF) TDO (60BC); +SDR 16 TDI (FFFF) TDO (1028); +SDR 16 TDI (FFFF) TDO (805E); +SDR 16 TDI (FFFF) TDO (9A81); +SDR 16 TDI (FFFF) TDO (50C3); +SDR 16 TDI (FFFF) TDO (0B7F); +SDR 16 TDI (FFFF) TDO (AD58); +SDR 16 TDI (FFFF) TDO (70EE); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (965F); +SDR 16 TDI (FFFF) TDO (B3EF); +SDR 16 TDI (FFFF) TDO (6BFE); +SDR 16 TDI (FFFF) TDO (9E0E); +SDR 16 TDI (FFFF) TDO (B928); +SDR 16 TDI (FFFF) TDO (3FF4); +SDR 16 TDI (FFFF) TDO (62CA); +SDR 16 TDI (FFFF) TDO (11D4); +SDR 16 TDI (FFFF) TDO (BBBF); +SDR 16 TDI (FFFF) TDO (CE40); +SDR 16 TDI (FFFF) TDO (6F93); +SDR 16 TDI (FFFF) TDO (F00F); +SDR 16 TDI (FFFF) TDO (9E01); +SDR 16 TDI (FFFF) TDO (98FD); +SDR 16 TDI (FFFF) TDO (7BFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFF9); +SDR 16 TDI (FFFF) TDO (B3F3); +SDR 16 TDI (FFFF) TDO (6FFE); +SDR 16 TDI (FFFF) TDO (132D); +SDR 16 TDI (FFFF) TDO (AD2B); +SDR 16 TDI (FFFF) TDO (03F0); +SDR 16 TDI (FFFF) TDO (60CA); +SDR 16 TDI (FFFF) TDO (71D0); +SDR 16 TDI (FFFF) TDO (9BBF); +SDR 16 TDI (FFFF) TDO (987C); +SDR 16 TDI (FFFF) TDO (7303); +SDR 16 TDI (FFFF) TDO (D00F); +SDR 16 TDI (FFFF) TDO (BFF8); +SDR 16 TDI (FFFF) TDO (7CFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (3B37); +SDR 16 TDI (FFFF) TDO (61E6); +SDR 16 TDI (FFFF) TDO (6267); +SDR 16 TDI (FFFF) TDO (BBBB); +SDR 16 TDI (FFFF) TDO (B8F3); +SDR 16 TDI (FFFF) TDO (42EE); +SDR 16 TDI (FFFF) TDO (FCEE); +SDR 16 TDI (FFFF) TDO (99CF); +SDR 16 TDI (FFFF) TDO (BB99); +SDR 16 TDI (FFFF) TDO (57CE); +SDR 16 TDI (FFFF) TDO (CDE7); +SDR 16 TDI (FFFF) TDO (B9F9); +SDR 16 TDI (FFFF) TDO (99C8); +SDR 16 TDI (FFFF) TDO (77FF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (9FFE); +SDR 16 TDI (FFFF) TDO (7277); +SDR 16 TDI (FFFF) TDO (6957); +SDR 16 TDI (FFFF) TDO (3737); +SDR 16 TDI (FFFF) TDO (B111); +SDR 16 TDI (FFFF) TDO (10B9); +SDR 16 TDI (FFFF) TDO (7644); +SDR 16 TDI (FFFF) TDO (5DCD); +SDR 16 TDI (FFFF) TDO (BB85); +SDR 16 TDI (FFFF) TDO (59DD); +SDR 16 TDI (FFFF) TDO (73DC); +SDR 16 TDI (FFFF) TDO (DDC2); +SDR 16 TDI (FFFF) TDO (959D); +SDR 16 TDI (FFFF) TDO (DDFD); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFB); +SDR 16 TDI (FFFF) TDO (DFFB); +SDR 16 TDI (FFFF) TDO (77CE); +SDR 16 TDI (FFFF) TDO (EFEE); +SDR 16 TDI (FFFF) TDO (BDDD); +SDR 16 TDI (FFFF) TDO (DFE7); +SDR 16 TDI (FFFF) TDO (7FDD); +SDR 16 TDI (FFFF) TDO (DE7F); +SDR 16 TDI (FFFF) TDO (9CEF); +SDR 16 TDI (FFFF) TDO (FF3B); +SDR 16 TDI (FFFF) TDO (7EEF); +SDR 16 TDI (FFFF) TDO (FEFF); +SDR 16 TDI (FFFF) TDO (B3FF); +SDR 16 TDI (FFFF) TDO (BBDF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (EFDF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (3BDF); +SDR 16 TDI (FFFF) TDO (99EE); +SDR 16 TDI (FFFF) TDO (FFFB); +SDR 16 TDI (FFFF) TDO (7DFF); +SDR 16 TDI (FFFF) TDO (FD7F); +SDR 16 TDI (FFFF) TDO (BBFF); +SDR 16 TDI (FFFF) TDO (DFDF); +SDR 16 TDI (FFFF) TDO (6FD6); +SDR 16 TDI (FFFF) TDO (9FFF); +SDR 16 TDI (FFFF) TDO (BFFE); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (9FFF); +SDR 16 TDI (FFFF) TDO (7EF6); +SDR 16 TDI (FFFF) TDO (6FFF); +SDR 16 TDI (FFFF) TDO (F7F5); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (5FFD); +SDR 16 TDI (FFFF) TDO (7FF7); +SDR 16 TDI (FFFF) TDO (FFED); +SDR 16 TDI (FFFF) TDO (BF3F); +SDR 16 TDI (FFFF) TDO (FDFD); +SDR 16 TDI (FFFF) TDO (5FBF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (9FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (6FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (8FFF); +SDR 16 TDI (FFFF) TDO (DFE7); +SDR 16 TDI (FFFF) TDO (5FFE); +SDR 16 TDI (FFFF) TDO (FFEF); +SDR 16 TDI (FFFF) TDO (B6ED); +SDR 16 TDI (FFFF) TDO (7FFB); +SDR 16 TDI (FFFF) TDO (7BFF); +SDR 16 TDI (FFFF) TDO (FEBD); +SDR 16 TDI (FFFF) TDO (9FFF); +SDR 16 TDI (FFFF) TDO (FFFD); +SDR 16 TDI (FFFF) TDO (7FE6); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (AFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (6FFF); +SDR 16 TDI (FFFF) TDO (D5BD); +SDR 16 TDI (FFFF) TDO (9FFF); +SDR 16 TDI (FFFF) TDO (DFFF); +SDR 16 TDI (FFFF) TDO (7FEF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BDBF); +SDR 16 TDI (FFFF) TDO (DDDE); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (6FFF); +SDR 16 TDI (FFFF) TDO (BFFE); +SDR 16 TDI (FFFF) TDO (FFBF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (9FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (5FFE); +SDR 16 TDI (FFFF) TDO (DFFF); +SDR 16 TDI (FFFF) TDO (BEEF); +SDR 16 TDI (FFFF) TDO (FFFE); +SDR 16 TDI (FFFF) TDO (7DFF); +SDR 16 TDI (FFFF) TDO (DDF7); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FEFF); +SDR 16 TDI (FFFF) TDO (7FF7); +SDR 16 TDI (FFFF) TDO (9F7F); +SDR 16 TDI (FFFF) TDO (9FFE); +SDR 16 TDI (FFFF) TDO (FBFB); +SDR 16 TDI (FFFF) TDO (5FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (BFFD); +SDR 16 TDI (FFFF) TDO (6FFF); +SDR 16 TDI (FFFF) TDO (FFFE); +SDR 16 TDI (FFFF) TDO (BBFD); +SDR 16 TDI (FFFF) TDO (EFFF); +SDR 16 TDI (FFFF) TDO (5FFB); +SDR 16 TDI (FFFF) TDO (EFBF); +SDR 16 TDI (FFFF) TDO (9F7F); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (9BFD); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (5FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FEEF); +SDR 16 TDI (FFFF) TDO (5FFF); +SDR 16 TDI (FFFF) TDO (4FFF); +SDR 16 TDI (FFFF) TDO (9FFF); +SDR 16 TDI (FFFF) TDO (DFFE); +SDR 16 TDI (FFFF) TDO (6FFE); +SDR 16 TDI (FFFF) TDO (FF7E); +SDR 16 TDI (FFFF) TDO (9FFF); +SDR 16 TDI (FFFF) TDO (FB7F); +SDR 16 TDI (FFFF) TDO (57F7); +SDR 16 TDI (FFFF) TDO (FF6F); +SDR 16 TDI (FFFF) TDO (BDFF); +SDR 16 TDI (FFFF) TDO (FFF7); +SDR 16 TDI (FFFF) TDO (5BFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (9FFF); +SDR 16 TDI (FFFF) TDO (BFFE); +SDR 16 TDI (FFFF) TDO (6FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (89DE); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (5BFD); +SDR 16 TDI (FFFF) TDO (BDF7); +SDR 16 TDI (FFFF) TDO (BF7F); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (5FFF); +SDR 16 TDI (FFFF) TDO (5FFF); +SDR 16 TDI (FFFF) TDO (9FFB); +SDR 16 TDI (FFFF) TDO (7BFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (9EF7); +SDR 16 TDI (FFFF) TDO (FFDF); +SDR 16 TDI (FFFF) TDO (5FFF); +SDR 16 TDI (FFFF) TDO (FDFE); +SDR 16 TDI (FFFF) TDO (BDFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (5BFE); +SDR 16 TDI (FFFF) TDO (EDDF); +SDR 16 TDI (FFFF) TDO (9DFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7E7F); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (9FBF); +SDR 16 TDI (FFFF) TDO (F7FF); +SDR 16 TDI (FFFF) TDO (5FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (EEFF); +SDR 16 TDI (FFFF) TDO (5FEF); +SDR 16 TDI (FFFF) TDO (BFFB); +SDR 16 TDI (FFFF) TDO (9FBE); +SDR 16 TDI (FFFF) TDO (FFF7); +SDR 16 TDI (FFFF) TDO (7FBF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (9FFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (5BDB); +SDR 16 TDI (FFFF) TDO (EDFF); +SDR 16 TDI (FFFF) TDO (BBFF); +SDR 16 TDI (FFFF) TDO (DFFF); +SDR 16 TDI (FFFF) TDO (5FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (9FF7); +SDR 16 TDI (FFFF) TDO (DFDF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (9BFD); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (5FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BBFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7E5E); +SDR 16 TDI (FFFF) TDO (BBFF); +SDR 16 TDI (FFFF) TDO (BFFE); +SDR 16 TDI (FFFF) TDO (F7FF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (9EFF); +SDR 16 TDI (FFFF) TDO (FEFF); +SDR 16 TDI (FFFF) TDO (57FF); +SDR 16 TDI (FFFF) TDO (DBFD); +SDR 16 TDI (FFFF) TDO (ADBF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7BDE); +SDR 16 TDI (FFFF) TDO (FDEF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7BFB); +SDR 16 TDI (FFFF) TDO (DEFF); +SDR 16 TDI (FFFF) TDO (9FDF); +SDR 16 TDI (FFFF) TDO (DFFF); +SDR 16 TDI (FFFF) TDO (5FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (A75E); +SDR 16 TDI (FFFF) TDO (F7FF); +SDR 16 TDI (FFFF) TDO (6DFF); +SDR 16 TDI (FFFF) TDO (FFEE); +SDR 16 TDI (FFFF) TDO (BDFF); +SDR 16 TDI (FFFF) TDO (B7FD); +SDR 16 TDI (FFFF) TDO (7F76); +SDR 16 TDI (FFFF) TDO (FFFD); +SDR 16 TDI (FFFF) TDO (9BFE); +SDR 16 TDI (FFFF) TDO (DFDD); +SDR 16 TDI (FFFF) TDO (5B75); +SDR 16 TDI (FFFF) TDO (EEF7); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFD); +SDR 16 TDI (FFFF) TDO (7BFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (ADFF); +SDR 16 TDI (FFFF) TDO (FF76); +SDR 16 TDI (FFFF) TDO (7FFE); +SDR 16 TDI (FFFF) TDO (FFBB); +SDR 16 TDI (FFFF) TDO (9FF7); +SDR 16 TDI (FFFF) TDO (FFF7); +SDR 16 TDI (FFFF) TDO (5FFF); +SDR 16 TDI (FFFF) TDO (FFD7); +SDR 16 TDI (FFFF) TDO (AEFF); +SDR 16 TDI (FFFF) TDO (F5FF); +SDR 16 TDI (FFFF) TDO (6FFF); +SDR 16 TDI (FFFF) TDO (B7EF); +SDR 16 TDI (FFFF) TDO (BEDD); +SDR 16 TDI (FFFF) TDO (BBFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (8B5E); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (5FFF); +SDR 16 TDI (FFFF) TDO (F37F); +SDR 16 TDI (FFFF) TDO (B77F); +SDR 16 TDI (FFFF) TDO (DFFF); +SDR 16 TDI (FFFF) TDO (77DD); +SDR 16 TDI (FFFF) TDO (B9F7); +SDR 16 TDI (FFFF) TDO (AFBF); +SDR 16 TDI (FFFF) TDO (FF77); +SDR 16 TDI (FFFF) TDO (6FFF); +SDR 16 TDI (FFFF) TDO (FBFF); +SDR 16 TDI (FFFF) TDO (9D7F); +SDR 16 TDI (FFFF) TDO (F7FD); +SDR 16 TDI (FFFF) TDO (5BFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (ADFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFA); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (AEEF); +SDR 16 TDI (FFFF) TDO (BBFF); +SDR 16 TDI (FFFF) TDO (7F77); +SDR 16 TDI (FFFF) TDO (FFEE); +SDR 16 TDI (FFFF) TDO (9DFF); +SDR 16 TDI (FFFF) TDO (EBFB); +SDR 16 TDI (FFFF) TDO (5DFF); +SDR 16 TDI (FFFF) TDO (BF7F); +SDR 16 TDI (FFFF) TDO (BFF4); +SDR 16 TDI (FFFF) TDO (BFFB); +SDR 16 TDI (FFFF) TDO (77FF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (EEFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (DFFF); +SDR 16 TDI (FFFF) TDO (9FFD); +SDR 16 TDI (FFFF) TDO (FFFD); +SDR 16 TDI (FFFF) TDO (5DFF); +SDR 16 TDI (FFFF) TDO (FEFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFBF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FB7F); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (9FFF); +SDR 16 TDI (FFFF) TDO (FFEF); +SDR 16 TDI (FFFF) TDO (5FEF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (9BAB); +SDR 16 TDI (FFFF) TDO (EFFB); +SDR 16 TDI (FFFF) TDO (57DD); +SDR 16 TDI (FFFF) TDO (DFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FEEF); +SDR 16 TDI (FFFF) TDO (7EDF); +SDR 16 TDI (FFFF) TDO (DD6F); +SDR 16 TDI (FFFF) TDO (BDB7); +SDR 16 TDI (FFFF) TDO (777F); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (9FFD); +SDR 16 TDI (FFFF) TDO (7F7D); +SDR 16 TDI (FFFF) TDO (4FFF); +SDR 16 TDI (FFFF) TDO (BBFF); +SDR 16 TDI (FFFF) TDO (BFCA); +SDR 16 TDI (FFFF) TDO (DBFB); +SDR 16 TDI (FFFF) TDO (7BBB); +SDR 16 TDI (FFFF) TDO (F8D5); +SDR 16 TDI (FFFF) TDO (AABE); +SDR 16 TDI (FFFF) TDO (E465); +SDR 16 TDI (FFFF) TDO (69FD); +SDR 16 TDI (FFFF) TDO (DFCF); +SDR 16 TDI (FFFF) TDO (9FFA); +SDR 16 TDI (FFFF) TDO (FFFE); +SDR 16 TDI (FFFF) TDO (57FF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFE); +SDR 16 TDI (FFFF) TDO (F6D7); +SDR 16 TDI (FFFF) TDO (7FEA); +SDR 16 TDI (FFFF) TDO (77F5); +SDR 16 TDI (FFFF) TDO (BFF7); +SDR 16 TDI (FFFF) TDO (AFF6); +SDR 16 TDI (FFFF) TDO (7667); +SDR 16 TDI (FFFF) TDO (1FFF); +SDR 16 TDI (FFFF) TDO (9FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (5EEF); +SDR 16 TDI (FFFF) TDO (A43F); +SDR 16 TDI (FFFF) TDO (BA35); +SDR 16 TDI (FFFF) TDO (717F); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (EFFF); +SDR 16 TDI (FFFF) TDO (7BFF); +SDR 16 TDI (FFFF) TDO (FF5E); +SDR 16 TDI (FFFF) TDO (803F); +SDR 16 TDI (FFFF) TDO (77FD); +SDR 16 TDI (FFFF) TDO (4FDD); +SDR 16 TDI (FFFF) TDO (FFEA); +SDR 16 TDI (FFFF) TDO (B5FF); +SDR 16 TDI (FFFF) TDO (DB9A); +SDR 16 TDI (FFFF) TDO (7F77); +SDR 16 TDI (FFFF) TDO (7BF7); +SDR 16 TDI (FFFF) TDO (BDCF); +SDR 16 TDI (FFFF) TDO (8EFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (8A5D); +SDR 16 TDI (FFFF) TDO (69FC); +SDR 16 TDI (FFFF) TDO (47D6); +SDR 16 TDI (FFFF) TDO (0B9F); +SDR 16 TDI (FFFF) TDO (B780); +SDR 16 TDI (FFFF) TDO (33EA); +SDR 16 TDI (FFFF) TDO (6420); +SDR 16 TDI (FFFF) TDO (1CCA); +SDR 16 TDI (FFFF) TDO (B21F); +SDR 16 TDI (FFFF) TDO (2147); +SDR 16 TDI (FFFF) TDO (6430); +SDR 16 TDI (FFFF) TDO (EECF); +SDR 16 TDI (FFFF) TDO (939A); +SDR 16 TDI (FFFF) TDO (A9EB); +SDR 16 TDI (FFFF) TDO (4BFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (AEFE); +SDR 16 TDI (FFFF) TDO (E9C3); +SDR 16 TDI (FFFF) TDO (67B6); +SDR 16 TDI (FFFF) TDO (0BE1); +SDR 16 TDI (FFFF) TDO (BCF4); +SDR 16 TDI (FFFF) TDO (03D0); +SDR 16 TDI (FFFF) TDO (6400); +SDR 16 TDI (FFFF) TDO (1CC4); +SDR 16 TDI (FFFF) TDO (85FE); +SDR 16 TDI (FFFF) TDO (A006); +SDR 16 TDI (FFFF) TDO (500F); +SDR 16 TDI (FFFF) TDO (22AF); +SDR 16 TDI (FFFF) TDO (AA29); +SDR 16 TDI (FFFF) TDO (9AEB); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BB5D); +SDR 16 TDI (FFFF) TDO (9283); +SDR 16 TDI (FFFF) TDO (7BEE); +SDR 16 TDI (FFFF) TDO (4C61); +SDR 16 TDI (FFFF) TDO (9B7D); +SDR 16 TDI (FFFF) TDO (03FC); +SDR 16 TDI (FFFF) TDO (5E05); +SDR 16 TDI (FFFF) TDO (D9F0); +SDR 16 TDI (FFFF) TDO (A01F); +SDR 16 TDI (FFFF) TDO (C207); +SDR 16 TDI (FFFF) TDO (7030); +SDR 16 TDI (FFFF) TDO (DDC7); +SDR 16 TDI (FFFF) TDO (BD9C); +SDR 16 TDI (FFFF) TDO (C9FF); +SDR 16 TDI (FFFF) TDO (6BFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BBFA); +SDR 16 TDI (FFFF) TDO (D2B0); +SDR 16 TDI (FFFF) TDO (67EE); +SDR 16 TDI (FFFF) TDO (4D86); +SDR 16 TDI (FFFF) TDO (AFFD); +SDR 16 TDI (FFFF) TDO (1BF0); +SDR 16 TDI (FFFF) TDO (5E00); +SDR 16 TDI (FFFF) TDO (59F0); +SDR 16 TDI (FFFF) TDO (A01F); +SDR 16 TDI (FFFF) TDO (8007); +SDR 16 TDI (FFFF) TDO (7000); +SDR 16 TDI (FFFF) TDO (119F); +SDR 16 TDI (FFFF) TDO (9C49); +SDR 16 TDI (FFFF) TDO (9CBF); +SDR 16 TDI (FFFF) TDO (5FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (BBBB); +SDR 16 TDI (FFFF) TDO (71EE); +SDR 16 TDI (FFFF) TDO (EEEF); +SDR 16 TDI (FFFF) TDO (B33B); +SDR 16 TDI (FFFF) TDO (B1F7); +SDR 16 TDI (FFFF) TDO (6623); +SDR 16 TDI (FFFF) TDO (FECE); +SDR 16 TDI (FFFF) TDO (9D8F); +SDR 16 TDI (FFFF) TDO (D998); +SDR 16 TDI (FFFF) TDO (59C8); +SDR 16 TDI (FFFF) TDO (EEE3); +SDR 16 TDI (FFFF) TDO (BBBB); +SDR 16 TDI (FFFF) TDO (BBFA); +SDR 16 TDI (FFFF) TDO (77FF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (5555); +SDR 16 TDI (FFFF) TDO (6946); +SDR 16 TDI (FFFF) TDO (7555); +SDR 16 TDI (FFFF) TDO (9773); +SDR 16 TDI (FFFF) TDO (34A3); +SDR 16 TDI (FFFF) TDO (5776); +SDR 16 TDI (FFFF) TDO (7C9C); +SDR 16 TDI (FFFF) TDO (B925); +SDR 16 TDI (FFFF) TDO (5DDD); +SDR 16 TDI (FFFF) TDO (7B9D); +SDR 16 TDI (FFFF) TDO (CCC2); +SDR 16 TDI (FFFF) TDO (B199); +SDR 16 TDI (FFFF) TDO (99FF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (9BF9); +SDR 16 TDI (FFFF) TDO (DDDD); +SDR 16 TDI (FFFF) TDO (5FFF); +SDR 16 TDI (FFFF) TDO (FDDD); +SDR 16 TDI (FFFF) TDO (BBBF); +SDR 16 TDI (FFFF) TDO (FBEF); +SDR 16 TDI (FFFF) TDO (6FFF); +SDR 16 TDI (FFFF) TDO (F7EF); +SDR 16 TDI (FFFF) TDO (BFEF); +SDR 16 TDI (FFFF) TDO (3FBF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (777F); +SDR 16 TDI (FFFF) TDO (B777); +SDR 16 TDI (FFFF) TDO (773F); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (BEB7); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (DCEF); +SDR 16 TDI (FFFF) TDO (BDBF); +SDR 16 TDI (FFFF) TDO (9FFE); +SDR 16 TDI (FFFF) TDO (7F5F); +SDR 16 TDI (FFFF) TDO (7EFF); +SDR 16 TDI (FFFF) TDO (B7FF); +SDR 16 TDI (FFFF) TDO (FDF7); +SDR 16 TDI (FFFF) TDO (7FDF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BDFF); +SDR 16 TDI (FFFF) TDO (FBFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (DFFD); +SDR 16 TDI (FFFF) TDO (7FF7); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFD); +SDR 16 TDI (FFFF) TDO (FFFB); +SDR 16 TDI (FFFF) TDO (77F5); +SDR 16 TDI (FFFF) TDO (FF7D); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (DFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (9B9F); +SDR 16 TDI (FFFF) TDO (BFDE); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (AFFF); +SDR 16 TDI (FFFF) TDO (FFBA); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (DDEF); +SDR 16 TDI (FFFF) TDO (BEBF); +SDR 16 TDI (FFFF) TDO (5FFA); +SDR 16 TDI (FFFF) TDO (7EB7); +SDR 16 TDI (FFFF) TDO (FFBD); +SDR 16 TDI (FFFF) TDO (AFFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FEF); +SDR 16 TDI (FFFF) TDO (DFEF); +SDR 16 TDI (FFFF) TDO (BBFF); +SDR 16 TDI (FFFF) TDO (FDFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (AFFF); +SDR 16 TDI (FFFF) TDO (5DFF); +SDR 16 TDI (FFFF) TDO (7FF7); +SDR 16 TDI (FFFF) TDO (FEFF); +SDR 16 TDI (FFFF) TDO (BFFD); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (77FA); +SDR 16 TDI (FFFF) TDO (FDFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (BDF7); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFDF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (F5FF); +SDR 16 TDI (FFFF) TDO (7FFB); +SDR 16 TDI (FFFF) TDO (BFBF); +SDR 16 TDI (FFFF) TDO (BDFE); +SDR 16 TDI (FFFF) TDO (EFFF); +SDR 16 TDI (FFFF) TDO (7FFD); +SDR 16 TDI (FFFF) TDO (D6FF); +SDR 16 TDI (FFFF) TDO (B77F); +SDR 16 TDI (FFFF) TDO (EFFF); +SDR 16 TDI (FFFF) TDO (7FF7); +SDR 16 TDI (FFFF) TDO (FBBF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (7BFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (7FF5); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (F7FF); +SDR 16 TDI (FFFF) TDO (BFFB); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (5ED7); +SDR 16 TDI (FFFF) TDO (EFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FF77); +SDR 16 TDI (FFFF) TDO (77FE); +SDR 16 TDI (FFFF) TDO (FDFF); +SDR 16 TDI (FFFF) TDO (BFAF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FBFF); +SDR 16 TDI (FFFF) TDO (5FFD); +SDR 16 TDI (FFFF) TDO (F7DF); +SDR 16 TDI (FFFF) TDO (BFFE); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FDD); +SDR 16 TDI (FFFF) TDO (E5FF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFF7); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FABF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (7EFA); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (BEFF); +SDR 16 TDI (FFFF) TDO (EFFF); +SDR 16 TDI (FFFF) TDO (7FF7); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (AF7F); +SDR 16 TDI (FFFF) TDO (EEFF); +SDR 16 TDI (FFFF) TDO (5FFB); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFE); +SDR 16 TDI (FFFF) TDO (FBFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFBF); +SDR 16 TDI (FFFF) TDO (7FFB); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (5EEF); +SDR 16 TDI (FFFF) TDO (EFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (DFFE); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (57FF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BF7F); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (EFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (5FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (6FEF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (4FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFBF); +SDR 16 TDI (FFFF) TDO (7FFB); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BF7F); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (5F6F); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (DFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFE); +SDR 16 TDI (FFFF) TDO (5FFB); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFDF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BF7F); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (5FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FDFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFD); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (EFFF); +SDR 16 TDI (FFFF) TDO (5FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFEF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (DFFF); +SDR 16 TDI (FFFF) TDO (5FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FF8); +SDR 16 TDI (FFFF) TDO (DDDF); +SDR 16 TDI (FFFF) TDO (BDDF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FEFE); +SDR 16 TDI (FFFF) TDO (5FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (EFFD); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BF7F); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (7FFF); +SDR 16 TDI (FFFF) TDO (EEEF); +SDR 16 TDI (FFFF) TDO (BBBF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (5FFF); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (FFDF); +SDR 16 TDI (FFFF) TDO (7FFD); +SDR 16 TDI (FFFF) TDO (FFFF); +SDR 16 TDI (FFFF) TDO (9FDF); SDR 16 TDI (FFFF) TDO (EFFD); SDR 16 TDI (FFFF) TDO (53FF); SDR 16 TDI (FFFF) TDO (FFFB); SDR 16 TDI (FFFF) TDO (977F); SDR 16 TDI (FFFF) TDO (E7FF); SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (7FF3); -SDR 16 TDI (FFFF) TDO (BF7F); +SDR 16 TDI (FFFF) TDO (FFF3); +SDR 16 TDI (FFFF) TDO (BFFF); SDR 16 TDI (FFFF) TDO (FFFF); SDR 16 TDI (FFFF) TDO (7FFF); SDR 16 TDI (FFFF) TDO (FFFF); SDR 16 TDI (FFFF) TDO (BFFF); SDR 16 TDI (FFFF) TDO (FFFF); SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (BFFE); SDR 16 TDI (FFFF) TDO (FFFF); SDR 16 TDI (FFFF) TDO (5FFF); SDR 16 TDI (FFFF) TDO (FFFB); -SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (B7FF); SDR 16 TDI (FFFF) TDO (FFFF); SDR 16 TDI (FFFF) TDO (7FFF); -SDR 16 TDI (FFFF) TDO (FFFF); -SDR 16 TDI (FFFF) TDO (BFFF); +SDR 16 TDI (FFFF) TDO (BBBF); +SDR 16 TDI (FFFF) TDO (BEEF); SDR 16 TDI (FFFF) TDO (FFFF); SDR 16 TDI (FFFF) TDO (7FFF); SDR 16 TDI (FFFF) TDO (FFFF); diff --git a/cpld/serv_req_info.txt b/cpld/serv_req_info.txt deleted file mode 100755 index 065cfbd..0000000 --- a/cpld/serv_req_info.txt +++ /dev/null @@ -1,8 +0,0 @@ - - quartus.exe - MEM - *** Fatal Error: Out of memory in module quartus.exe (1999 megabytes used) - Mon Mar 22 01:13:02 2021 - Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - - diff --git a/cpld/simulation/questa/GR8RAM.sft b/cpld/simulation/questa/GR8RAM.sft new file mode 100644 index 0000000..9a92a1e --- /dev/null +++ b/cpld/simulation/questa/GR8RAM.sft @@ -0,0 +1 @@ +set tool_name "Questa Intel FPGA (Verilog)" diff --git a/cpld/simulation/questa/GR8RAM.vo b/cpld/simulation/questa/GR8RAM.vo new file mode 100644 index 0000000..a571de9 --- /dev/null +++ b/cpld/simulation/questa/GR8RAM.vo @@ -0,0 +1,9751 @@ +// Copyright (C) 2022 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and any partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the applicable agreement for further details, at +// https://fpgasoftware.intel.com/eula. + +// VENDOR "Altera" +// PROGRAM "Quartus Prime" +// VERSION "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition" + +// DATE "02/28/2023 11:21:31" + +// +// Device: Altera EPM240T100C5 Package TQFP100 +// + +// +// This Verilog file should be used for Questa Intel FPGA (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module GR8RAM ( + C25M, + PHI0, + nRES, + nRESout, + SetFW, + INTin, + INTout, + DMAin, + DMAout, + nNMIout, + nIRQout, + nRDYout, + nINHout, + RWout, + nDMAout, + RA, + nWE, + RD, + RAdir, + RDdir, + nIOSEL, + nDEVSEL, + nIOSTRB, + SBA, + SA, + nRCS, + nRAS, + nCAS, + nSWE, + DQML, + DQMH, + RCKE, + SD, + nFCS, + FCK, + MISO, + MOSI); +input C25M; +input PHI0; +input nRES; +output nRESout; +input [1:0] SetFW; +input INTin; +output INTout; +input DMAin; +output DMAout; +output nNMIout; +output nIRQout; +output nRDYout; +output nINHout; +output RWout; +output nDMAout; +input [15:0] RA; +input nWE; +inout [7:0] RD; +output RAdir; +output RDdir; +input nIOSEL; +input nDEVSEL; +input nIOSTRB; +output [1:0] SBA; +output [12:0] SA; +output nRCS; +output nRAS; +output nCAS; +output nSWE; +output DQML; +output DQMH; +output RCKE; +inout [7:0] SD; +output nFCS; +output FCK; +input MISO; +inout MOSI; + +// Design Ports Information + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +wire \nIOSTRBr~regout ; +wire \RD[0]~0 ; +wire \RD[1]~1 ; +wire \RD[2]~2 ; +wire \RD[3]~3 ; +wire \RD[4]~4 ; +wire \RD[5]~5 ; +wire \RD[6]~6 ; +wire \RD[7]~7 ; +wire \SD[0]~0 ; +wire \SD[1]~1 ; +wire \SD[2]~2 ; +wire \SD[3]~3 ; +wire \SD[4]~4 ; +wire \SD[5]~5 ; +wire \SD[6]~6 ; +wire \SD[7]~7 ; +wire \MOSI~0 ; +wire \C25M~combout ; +wire \Equal1~0_combout ; +wire \PHI0~combout ; +wire \PHI0r1~regout ; +wire \nWE~combout ; +wire \PHI0r2~regout ; +wire \PS~0 ; +wire \Equal2~1_combout ; +wire \LS[1]~3 ; +wire \LS[2]~7 ; +wire \LS[2]~7COUT1_28 ; +wire \LS[3]~11 ; +wire \LS[3]~11COUT1_29 ; +wire \LS[4]~13 ; +wire \LS[4]~13COUT1_30 ; +wire \LS[5]~15 ; +wire \LS[5]~15COUT1_31 ; +wire \LS[6]~17 ; +wire \Equal3~0_combout ; +wire \LS[7]~19 ; +wire \LS[7]~19COUT1_32 ; +wire \LS[8]~21 ; +wire \LS[8]~21COUT1_33 ; +wire \LS[9]~23 ; +wire \LS[9]~23COUT1_34 ; +wire \LS[10]~1 ; +wire \LS[10]~1COUT1_35 ; +wire \LS[11]~5 ; +wire \Equal3~1_combout ; +wire \Equal3~2_combout ; +wire \Equal5~0_combout ; +wire \Equal6~0_combout ; +wire \LS[12]~9 ; +wire \LS[12]~9COUT1_36 ; +wire \IS.111~regout ; +wire \nRESout~reg0_regout ; +wire \INTin~combout ; +wire \DMAin~combout ; +wire \IS~17_combout ; +wire \IS~18_combout ; +wire \Equal3~3_combout ; +wire \Equal4~0 ; +wire \Equal3~4 ; +wire \IS~19_combout ; +wire \IS.110~regout ; +wire \SA[1]~3_combout ; +wire \Mux22~0_combout ; +wire \RAMRegSpecSEL~0 ; +wire \SA[1]~2_combout ; +wire \Mux24~0_combout ; +wire \Mux24~1_combout ; +wire \nRES~combout ; +wire \nRESr~regout ; +wire \nDEVSEL~combout ; +wire \nRCS~0_combout ; +wire \nWEr~regout ; +wire \Equal19~0_combout ; +wire \always9~1_combout ; +wire \RAMRegSpecSEL~1 ; +wire \always9~3_combout ; +wire \always9~4_combout ; +wire \always9~5_combout ; +wire \AddrIncL~regout ; +wire \Addr[0]~47 ; +wire \Addr[0]~47COUT1_61 ; +wire \Addr[1]~5 ; +wire \Addr[1]~5COUT1_62 ; +wire \Addr[2]~9 ; +wire \Addr[2]~9COUT1_63 ; +wire \Addr[3]~13 ; +wire \Addr[3]~13COUT1_64 ; +wire \Addr[4]~17 ; +wire \Addr[5]~21 ; +wire \Addr[5]~21COUT1_65 ; +wire \Addr[6]~25 ; +wire \Addr[6]~25COUT1_66 ; +wire \AddrIncM~1_combout ; +wire \AddrIncM~0_combout ; +wire \AddrIncM~2_combout ; +wire \AddrIncM~regout ; +wire \Addr[8]~33 ; +wire \Addr[8]~33COUT1_55 ; +wire \Addr[9]~37 ; +wire \Addr[9]~37COUT1_56 ; +wire \Addr[10]~3 ; +wire \Addr[10]~3COUT1_57 ; +wire \Mux23~0_combout ; +wire \Mux23~1_combout ; +wire \nIOSEL~combout ; +wire \REGEN~regout ; +wire \CXXXr~regout ; +wire \Equal9~0 ; +wire \always9~0_combout ; +wire \SetFWLoaded~regout ; +wire \always9~2_combout ; +wire \AddrIncH~0_combout ; +wire \Addr[11]~7 ; +wire \Addr[11]~7COUT1_58 ; +wire \Addr[12]~11 ; +wire \Addr[13]~15 ; +wire \Addr[13]~15COUT1_59 ; +wire \AddrIncH~1_combout ; +wire \AddrIncH~2_combout ; +wire \Addr[14]~19 ; +wire \Addr[14]~19COUT1_60 ; +wire \AddrIncH~regout ; +wire \Addr[16]~27 ; +wire \Addr[16]~27COUT1_49 ; +wire \Addr[17]~31 ; +wire \Addr[17]~31COUT1_50 ; +wire \Addr[18]~35 ; +wire \Addr[18]~35COUT1_51 ; +wire \Addr[19]~39 ; +wire \Addr[19]~39COUT1_52 ; +wire \Addr[20]~41 ; +wire \Addr[21]~43 ; +wire \Addr[21]~43COUT1_53 ; +wire \Addr[22]~45 ; +wire \Addr[22]~45COUT1_54 ; +wire \RAMSpecSEL~0 ; +wire \RAMSpecSEL~1_combout ; +wire \SA[1]~4_combout ; +wire \always8~0 ; +wire \nIOSTRB~combout ; +wire \always8~1 ; +wire \always8~2 ; +wire \always8~3 ; +wire \always8~4_combout ; +wire \IOROMEN~regout ; +wire \Equal16~0_combout ; +wire \Equal16~1_combout ; +wire \Equal16~2_combout ; +wire \comb~1_combout ; +wire \comb~0 ; +wire \comb~2_combout ; +wire \Mux14~2_combout ; +wire \Mux14~3_combout ; +wire \Mux14~0_combout ; +wire \Mux14~1_combout ; +wire \SBA[0]~reg0_regout ; +wire \Mux13~0_combout ; +wire \SBA[1]~reg0_regout ; +wire \Mux24~2 ; +wire \Mux24~3_combout ; +wire \SA[1]~5_combout ; +wire \SA[1]~6_combout ; +wire \SA[0]~reg0_regout ; +wire \Mux23~2 ; +wire \Mux23~3_combout ; +wire \SA[1]~reg0_regout ; +wire \Mux22~1 ; +wire \Bank~regout ; +wire \Mux22~2_combout ; +wire \Mux22~3_combout ; +wire \SA[2]~reg0_regout ; +wire \SA[3]~15_combout ; +wire \SA[3]~9_combout ; +wire \Mux21~3_combout ; +wire \Mux21~2 ; +wire \Mux21~4_combout ; +wire \SA[3]~8_combout ; +wire \SA[3]~reg0_regout ; +wire \Mux20~4_combout ; +wire \Mux20~2_combout ; +wire \Mux20~3_combout ; +wire \SA[4]~reg0_regout ; +wire \Mux19~3_combout ; +wire \Mux19~5_combout ; +wire \Mux19~2 ; +wire \Mux19~4_combout ; +wire \SA[5]~reg0_regout ; +wire \Mux18~4_combout ; +wire \Mux18~3_combout ; +wire \Mux18~2_combout ; +wire \SA[6]~reg0_regout ; +wire \Mux17~4_combout ; +wire \Mux17~2_combout ; +wire \Mux17~3_combout ; +wire \SA[7]~reg0_regout ; +wire \Mux16~3_combout ; +wire \Mux16~4_combout ; +wire \Mux16~2 ; +wire \SA[8]~reg0_regout ; +wire \SA[1]~7_combout ; +wire \SA~10_combout ; +wire \SA[9]~reg0_regout ; +wire \Mux15~0_combout ; +wire \Mux15~1_combout ; +wire \SA[10]~reg0_regout ; +wire \SA[11]~reg0_regout ; +wire \SA[12]~reg0_regout ; +wire \nRCS~3_combout ; +wire \nRCS~4_combout ; +wire \Mux12~1_combout ; +wire \Mux12~2_combout ; +wire \nRCS~5_combout ; +wire \Mux12~3_combout ; +wire \nRCS~1 ; +wire \IS.000~regout ; +wire \nRCS~2_combout ; +wire \Mux12~0_combout ; +wire \nRCS~reg0_regout ; +wire \nRAS~reg0_regout ; +wire \nCAS~reg0_regout ; +wire \IS.001~regout ; +wire \Selector0~0_combout ; +wire \nSWE~reg0_regout ; +wire \Equal1~1_combout ; +wire \Selector1~0_combout ; +wire \DQMH~0_combout ; +wire \DQML~reg0_regout ; +wire \Selector2~0_combout ; +wire \DQMH~reg0_regout ; +wire \Mux11~0_combout ; +wire \Mux11~1_combout ; +wire \Mux11~2_combout ; +wire \Mux11~3_combout ; +wire \Equal2~0_combout ; +wire \RCKE~reg0_regout ; +wire \IS.100~regout ; +wire \IS.101~regout ; +wire \FCS~regout ; +wire \FCKOE~regout ; +wire \FCKout~regout ; +wire \RDD[1]~23_combout ; +wire \RDD[1]~22_combout ; +wire \RDD~4_combout ; +wire \Equal20~0_combout ; +wire \RDD~6_combout ; +wire \RDD~8_combout ; +wire \RDD~10_combout ; +wire \RDD[4]~12_combout ; +wire \RDD~14_combout ; +wire \RDD[4]~13_combout ; +wire \RDD~16_combout ; +wire \RDD~18_combout ; +wire \RDD~20_combout ; +wire \SDOE~regout ; +wire \MISO~combout ; +wire \Mux2~0_combout ; +wire \Mux2~1_combout ; +wire \Mux2~2 ; +wire \Mux2~3_combout ; +wire \SA[1]~14_combout ; +wire \MOSIout~regout ; +wire \MOSIOE~regout ; +wire [1:0] SetFWr; +wire [15:0] \RA~combout ; +wire [1:0] \SetFW~combout ; +wire [3:0] PS; +wire [11:0] RAr; +wire [23:0] Addr; +wire [13:0] LS; +wire [7:0] RDD; +wire [3:0] nRESf; +wire [7:0] WRD; + + +// Location: PIN_86, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +maxii_io \RD[0]~I ( + .datain(RDD[0]), + .oe(\comb~2_combout ), + .combout(\RD[0]~0 ), + .padio(RD[0])); +// synopsys translate_off +defparam \RD[0]~I .bus_hold = "true"; +defparam \RD[0]~I .operation_mode = "bidir"; +// synopsys translate_on + +// Location: PIN_87, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +maxii_io \RD[1]~I ( + .datain(RDD[1]), + .oe(\comb~2_combout ), + .combout(\RD[1]~1 ), + .padio(RD[1])); +// synopsys translate_off +defparam \RD[1]~I .bus_hold = "true"; +defparam \RD[1]~I .operation_mode = "bidir"; +// synopsys translate_on + +// Location: PIN_88, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +maxii_io \RD[2]~I ( + .datain(RDD[2]), + .oe(\comb~2_combout ), + .combout(\RD[2]~2 ), + .padio(RD[2])); +// synopsys translate_off +defparam \RD[2]~I .bus_hold = "true"; +defparam \RD[2]~I .operation_mode = "bidir"; +// synopsys translate_on + +// Location: PIN_89, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +maxii_io \RD[3]~I ( + .datain(RDD[3]), + .oe(\comb~2_combout ), + .combout(\RD[3]~3 ), + .padio(RD[3])); +// synopsys translate_off +defparam \RD[3]~I .bus_hold = "true"; +defparam \RD[3]~I .operation_mode = "bidir"; +// synopsys translate_on + +// Location: PIN_90, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +maxii_io \RD[4]~I ( + .datain(RDD[4]), + .oe(\comb~2_combout ), + .combout(\RD[4]~4 ), + .padio(RD[4])); +// synopsys translate_off +defparam \RD[4]~I .bus_hold = "true"; +defparam \RD[4]~I .operation_mode = "bidir"; +// synopsys translate_on + +// Location: PIN_91, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +maxii_io \RD[5]~I ( + .datain(RDD[5]), + .oe(\comb~2_combout ), + .combout(\RD[5]~5 ), + .padio(RD[5])); +// synopsys translate_off +defparam \RD[5]~I .bus_hold = "true"; +defparam \RD[5]~I .operation_mode = "bidir"; +// synopsys translate_on + +// Location: PIN_92, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +maxii_io \RD[6]~I ( + .datain(RDD[6]), + .oe(\comb~2_combout ), + .combout(\RD[6]~6 ), + .padio(RD[6])); +// synopsys translate_off +defparam \RD[6]~I .bus_hold = "true"; +defparam \RD[6]~I .operation_mode = "bidir"; +// synopsys translate_on + +// Location: PIN_99, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +maxii_io \RD[7]~I ( + .datain(RDD[7]), + .oe(\comb~2_combout ), + .combout(\RD[7]~7 ), + .padio(RD[7])); +// synopsys translate_off +defparam \RD[7]~I .bus_hold = "true"; +defparam \RD[7]~I .operation_mode = "bidir"; +// synopsys translate_on + +// Location: PIN_50, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA +maxii_io \SD[0]~I ( + .datain(WRD[0]), + .oe(\SDOE~regout ), + .combout(\SD[0]~0 ), + .padio(SD[0])); +// synopsys translate_off +defparam \SD[0]~I .operation_mode = "bidir"; +// synopsys translate_on + +// Location: PIN_47, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA +maxii_io \SD[1]~I ( + .datain(WRD[1]), + .oe(\SDOE~regout ), + .combout(\SD[1]~1 ), + .padio(SD[1])); +// synopsys translate_off +defparam \SD[1]~I .operation_mode = "bidir"; +// synopsys translate_on + +// Location: PIN_56, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA +maxii_io \SD[2]~I ( + .datain(WRD[2]), + .oe(\SDOE~regout ), + .combout(\SD[2]~2 ), + .padio(SD[2])); +// synopsys translate_off +defparam \SD[2]~I .operation_mode = "bidir"; +// synopsys translate_on + +// Location: PIN_55, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA +maxii_io \SD[3]~I ( + .datain(WRD[3]), + .oe(\SDOE~regout ), + .combout(\SD[3]~3 ), + .padio(SD[3])); +// synopsys translate_off +defparam \SD[3]~I .operation_mode = "bidir"; +// synopsys translate_on + +// Location: PIN_51, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA +maxii_io \SD[4]~I ( + .datain(WRD[4]), + .oe(\SDOE~regout ), + .combout(\SD[4]~4 ), + .padio(SD[4])); +// synopsys translate_off +defparam \SD[4]~I .operation_mode = "bidir"; +// synopsys translate_on + +// Location: PIN_52, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA +maxii_io \SD[5]~I ( + .datain(WRD[5]), + .oe(\SDOE~regout ), + .combout(\SD[5]~5 ), + .padio(SD[5])); +// synopsys translate_off +defparam \SD[5]~I .operation_mode = "bidir"; +// synopsys translate_on + +// Location: PIN_53, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA +maxii_io \SD[6]~I ( + .datain(WRD[6]), + .oe(\SDOE~regout ), + .combout(\SD[6]~6 ), + .padio(SD[6])); +// synopsys translate_off +defparam \SD[6]~I .operation_mode = "bidir"; +// synopsys translate_on + +// Location: PIN_54, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA +maxii_io \SD[7]~I ( + .datain(WRD[7]), + .oe(\SDOE~regout ), + .combout(\SD[7]~7 ), + .padio(SD[7])); +// synopsys translate_off +defparam \SD[7]~I .operation_mode = "bidir"; +// synopsys translate_on + +// Location: PIN_15, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +maxii_io \MOSI~I ( + .datain(\MOSIout~regout ), + .oe(\MOSIOE~regout ), + .combout(\MOSI~0 ), + .padio(MOSI)); +// synopsys translate_off +defparam \MOSI~I .bus_hold = "true"; +defparam \MOSI~I .operation_mode = "bidir"; +// synopsys translate_on + +// Location: PIN_64, I/O Standard: 3.3-V LVTTL, Current Strength: Default +maxii_io \C25M~I ( + .datain(gnd), + .oe(gnd), + .combout(\C25M~combout ), + .padio(C25M)); +// synopsys translate_off +defparam \C25M~I .operation_mode = "input"; +// synopsys translate_on + +// Location: LC_X7_Y2_N4 +maxii_lcell \Equal1~0 ( +// Equation(s): +// \Equal1~0_combout = (!PS[1] & (((!PS[3])))) + + .clk(gnd), + .dataa(PS[1]), + .datab(vcc), + .datac(PS[3]), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Equal1~0_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Equal1~0 .lut_mask = "0505"; +defparam \Equal1~0 .operation_mode = "normal"; +defparam \Equal1~0 .output_mode = "comb_only"; +defparam \Equal1~0 .register_cascade_mode = "off"; +defparam \Equal1~0 .sum_lutc_input = "datac"; +defparam \Equal1~0 .synch_mode = "off"; +// synopsys translate_on + +// Location: PIN_41, I/O Standard: 3.3V Schmitt Trigger Input, Current Strength: Default +maxii_io \PHI0~I ( + .datain(gnd), + .oe(gnd), + .combout(\PHI0~combout ), + .padio(PHI0)); +// synopsys translate_off +defparam \PHI0~I .operation_mode = "input"; +// synopsys translate_on + +// Location: LC_X5_Y1_N6 +maxii_lcell PHI0r1( +// Equation(s): +// \PS~0 = (((PHI0r1 & !\PHI0r2~regout ))) +// \PHI0r1~regout = DFFEAS(\PS~0 , GLOBAL(\C25M~combout ), VCC, , , \PHI0~combout , , , VCC) + + .clk(\C25M~combout ), + .dataa(vcc), + .datab(vcc), + .datac(\PHI0~combout ), + .datad(\PHI0r2~regout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\PS~0 ), + .regout(\PHI0r1~regout ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam PHI0r1.lut_mask = "00f0"; +defparam PHI0r1.operation_mode = "normal"; +defparam PHI0r1.output_mode = "reg_and_comb"; +defparam PHI0r1.register_cascade_mode = "off"; +defparam PHI0r1.sum_lutc_input = "qfbk"; +defparam PHI0r1.synch_mode = "on"; +// synopsys translate_on + +// Location: PIN_43, I/O Standard: 3.3V Schmitt Trigger Input, Current Strength: Default +maxii_io \nWE~I ( + .datain(gnd), + .oe(gnd), + .combout(\nWE~combout ), + .padio(nWE)); +// synopsys translate_off +defparam \nWE~I .operation_mode = "input"; +// synopsys translate_on + +// Location: LC_X5_Y1_N8 +maxii_lcell PHI0r2( +// Equation(s): +// \comb~0 = (\PHI0~combout & (((PHI0r2 & \nWE~combout )))) +// \PHI0r2~regout = DFFEAS(\comb~0 , GLOBAL(\C25M~combout ), VCC, , , \PHI0r1~regout , , , VCC) + + .clk(\C25M~combout ), + .dataa(\PHI0~combout ), + .datab(vcc), + .datac(\PHI0r1~regout ), + .datad(\nWE~combout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\comb~0 ), + .regout(\PHI0r2~regout ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam PHI0r2.lut_mask = "a000"; +defparam PHI0r2.operation_mode = "normal"; +defparam PHI0r2.output_mode = "reg_and_comb"; +defparam PHI0r2.register_cascade_mode = "off"; +defparam PHI0r2.sum_lutc_input = "qfbk"; +defparam PHI0r2.synch_mode = "on"; +// synopsys translate_on + +// Location: LC_X6_Y1_N1 +maxii_lcell \PS[0] ( +// Equation(s): +// PS[0] = DFFEAS((!PS[0] & (((\PS~0 ) # (PS[2])) # (!\Equal1~0_combout ))), GLOBAL(\C25M~combout ), VCC, , , , , , ) + + .clk(\C25M~combout ), + .dataa(\Equal1~0_combout ), + .datab(\PS~0 ), + .datac(PS[2]), + .datad(PS[0]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(PS[0]), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \PS[0] .lut_mask = "00fd"; +defparam \PS[0] .operation_mode = "normal"; +defparam \PS[0] .output_mode = "reg_only"; +defparam \PS[0] .register_cascade_mode = "off"; +defparam \PS[0] .sum_lutc_input = "datac"; +defparam \PS[0] .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X2_Y4_N8 +maxii_lcell \PS[1] ( +// Equation(s): +// PS[1] = DFFEAS(PS[1] $ ((((PS[0])))), GLOBAL(\C25M~combout ), VCC, , , , , , ) + + .clk(\C25M~combout ), + .dataa(PS[1]), + .datab(vcc), + .datac(vcc), + .datad(PS[0]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(PS[1]), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \PS[1] .lut_mask = "55aa"; +defparam \PS[1] .operation_mode = "normal"; +defparam \PS[1] .output_mode = "reg_only"; +defparam \PS[1] .register_cascade_mode = "off"; +defparam \PS[1] .sum_lutc_input = "datac"; +defparam \PS[1] .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X2_Y1_N2 +maxii_lcell \PS[2] ( +// Equation(s): +// PS[2] = DFFEAS((PS[2] $ (((PS[1] & PS[0])))), GLOBAL(\C25M~combout ), VCC, , , , , , ) + + .clk(\C25M~combout ), + .dataa(vcc), + .datab(PS[2]), + .datac(PS[1]), + .datad(PS[0]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(PS[2]), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \PS[2] .lut_mask = "3ccc"; +defparam \PS[2] .operation_mode = "normal"; +defparam \PS[2] .output_mode = "reg_only"; +defparam \PS[2] .register_cascade_mode = "off"; +defparam \PS[2] .sum_lutc_input = "datac"; +defparam \PS[2] .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X2_Y1_N3 +maxii_lcell \PS[3] ( +// Equation(s): +// PS[3] = DFFEAS(PS[3] $ (((PS[2] & (PS[1] & PS[0])))), GLOBAL(\C25M~combout ), VCC, , , , , , ) + + .clk(\C25M~combout ), + .dataa(PS[3]), + .datab(PS[2]), + .datac(PS[1]), + .datad(PS[0]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(PS[3]), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \PS[3] .lut_mask = "6aaa"; +defparam \PS[3] .operation_mode = "normal"; +defparam \PS[3] .output_mode = "reg_only"; +defparam \PS[3] .register_cascade_mode = "off"; +defparam \PS[3] .sum_lutc_input = "datac"; +defparam \PS[3] .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X2_Y1_N5 +maxii_lcell \Equal2~1 ( +// Equation(s): +// \Equal2~1_combout = (PS[3] & (PS[2] & (PS[1] & PS[0]))) + + .clk(gnd), + .dataa(PS[3]), + .datab(PS[2]), + .datac(PS[1]), + .datad(PS[0]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Equal2~1_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Equal2~1 .lut_mask = "8000"; +defparam \Equal2~1 .operation_mode = "normal"; +defparam \Equal2~1 .output_mode = "comb_only"; +defparam \Equal2~1 .register_cascade_mode = "off"; +defparam \Equal2~1 .sum_lutc_input = "datac"; +defparam \Equal2~1 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X2_Y3_N1 +maxii_lcell \LS[0] ( +// Equation(s): +// LS[0] = DFFEAS(((\Equal2~1_combout $ (LS[0]))), GLOBAL(\C25M~combout ), VCC, , , , , , ) + + .clk(\C25M~combout ), + .dataa(vcc), + .datab(vcc), + .datac(\Equal2~1_combout ), + .datad(LS[0]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(LS[0]), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \LS[0] .lut_mask = "0ff0"; +defparam \LS[0] .operation_mode = "normal"; +defparam \LS[0] .output_mode = "reg_only"; +defparam \LS[0] .register_cascade_mode = "off"; +defparam \LS[0] .sum_lutc_input = "datac"; +defparam \LS[0] .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X2_Y3_N4 +maxii_lcell \LS[1] ( +// Equation(s): +// LS[1] = DFFEAS(LS[1] $ ((LS[0])), GLOBAL(\C25M~combout ), VCC, , \Equal2~1_combout , , , , ) +// \LS[1]~3 = CARRY((LS[1] & (LS[0]))) + + .clk(\C25M~combout ), + .dataa(LS[1]), + .datab(LS[0]), + .datac(vcc), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal2~1_combout ), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(LS[1]), + .cout(\LS[1]~3 ), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \LS[1] .lut_mask = "6688"; +defparam \LS[1] .operation_mode = "arithmetic"; +defparam \LS[1] .output_mode = "reg_only"; +defparam \LS[1] .register_cascade_mode = "off"; +defparam \LS[1] .sum_lutc_input = "datac"; +defparam \LS[1] .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X2_Y3_N5 +maxii_lcell \LS[2] ( +// Equation(s): +// LS[2] = DFFEAS(LS[2] $ ((((\LS[1]~3 )))), GLOBAL(\C25M~combout ), VCC, , \Equal2~1_combout , , , , ) +// \LS[2]~7 = CARRY(((!\LS[1]~3 )) # (!LS[2])) +// \LS[2]~7COUT1_28 = CARRY(((!\LS[1]~3 )) # (!LS[2])) + + .clk(\C25M~combout ), + .dataa(LS[2]), + .datab(vcc), + .datac(vcc), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal2~1_combout ), + .cin(\LS[1]~3 ), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(LS[2]), + .cout(), + .cout0(\LS[2]~7 ), + .cout1(\LS[2]~7COUT1_28 )); +// synopsys translate_off +defparam \LS[2] .cin_used = "true"; +defparam \LS[2] .lut_mask = "5a5f"; +defparam \LS[2] .operation_mode = "arithmetic"; +defparam \LS[2] .output_mode = "reg_only"; +defparam \LS[2] .register_cascade_mode = "off"; +defparam \LS[2] .sum_lutc_input = "cin"; +defparam \LS[2] .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X2_Y3_N6 +maxii_lcell \LS[3] ( +// Equation(s): +// LS[3] = DFFEAS(LS[3] $ ((((!(!\LS[1]~3 & \LS[2]~7 ) # (\LS[1]~3 & \LS[2]~7COUT1_28 ))))), GLOBAL(\C25M~combout ), VCC, , \Equal2~1_combout , , , , ) +// \LS[3]~11 = CARRY((LS[3] & ((!\LS[2]~7 )))) +// \LS[3]~11COUT1_29 = CARRY((LS[3] & ((!\LS[2]~7COUT1_28 )))) + + .clk(\C25M~combout ), + .dataa(LS[3]), + .datab(vcc), + .datac(vcc), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal2~1_combout ), + .cin(\LS[1]~3 ), + .cin0(\LS[2]~7 ), + .cin1(\LS[2]~7COUT1_28 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(LS[3]), + .cout(), + .cout0(\LS[3]~11 ), + .cout1(\LS[3]~11COUT1_29 )); +// synopsys translate_off +defparam \LS[3] .cin0_used = "true"; +defparam \LS[3] .cin1_used = "true"; +defparam \LS[3] .cin_used = "true"; +defparam \LS[3] .lut_mask = "a50a"; +defparam \LS[3] .operation_mode = "arithmetic"; +defparam \LS[3] .output_mode = "reg_only"; +defparam \LS[3] .register_cascade_mode = "off"; +defparam \LS[3] .sum_lutc_input = "cin"; +defparam \LS[3] .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X2_Y3_N7 +maxii_lcell \LS[4] ( +// Equation(s): +// LS[4] = DFFEAS((LS[4] $ (((!\LS[1]~3 & \LS[3]~11 ) # (\LS[1]~3 & \LS[3]~11COUT1_29 )))), GLOBAL(\C25M~combout ), VCC, , \Equal2~1_combout , , , , ) +// \LS[4]~13 = CARRY(((!\LS[3]~11 ) # (!LS[4]))) +// \LS[4]~13COUT1_30 = CARRY(((!\LS[3]~11COUT1_29 ) # (!LS[4]))) + + .clk(\C25M~combout ), + .dataa(vcc), + .datab(LS[4]), + .datac(vcc), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal2~1_combout ), + .cin(\LS[1]~3 ), + .cin0(\LS[3]~11 ), + .cin1(\LS[3]~11COUT1_29 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(LS[4]), + .cout(), + .cout0(\LS[4]~13 ), + .cout1(\LS[4]~13COUT1_30 )); +// synopsys translate_off +defparam \LS[4] .cin0_used = "true"; +defparam \LS[4] .cin1_used = "true"; +defparam \LS[4] .cin_used = "true"; +defparam \LS[4] .lut_mask = "3c3f"; +defparam \LS[4] .operation_mode = "arithmetic"; +defparam \LS[4] .output_mode = "reg_only"; +defparam \LS[4] .register_cascade_mode = "off"; +defparam \LS[4] .sum_lutc_input = "cin"; +defparam \LS[4] .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X2_Y3_N8 +maxii_lcell \LS[5] ( +// Equation(s): +// LS[5] = DFFEAS(LS[5] $ ((((!(!\LS[1]~3 & \LS[4]~13 ) # (\LS[1]~3 & \LS[4]~13COUT1_30 ))))), GLOBAL(\C25M~combout ), VCC, , \Equal2~1_combout , , , , ) +// \LS[5]~15 = CARRY((LS[5] & ((!\LS[4]~13 )))) +// \LS[5]~15COUT1_31 = CARRY((LS[5] & ((!\LS[4]~13COUT1_30 )))) + + .clk(\C25M~combout ), + .dataa(LS[5]), + .datab(vcc), + .datac(vcc), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal2~1_combout ), + .cin(\LS[1]~3 ), + .cin0(\LS[4]~13 ), + .cin1(\LS[4]~13COUT1_30 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(LS[5]), + .cout(), + .cout0(\LS[5]~15 ), + .cout1(\LS[5]~15COUT1_31 )); +// synopsys translate_off +defparam \LS[5] .cin0_used = "true"; +defparam \LS[5] .cin1_used = "true"; +defparam \LS[5] .cin_used = "true"; +defparam \LS[5] .lut_mask = "a50a"; +defparam \LS[5] .operation_mode = "arithmetic"; +defparam \LS[5] .output_mode = "reg_only"; +defparam \LS[5] .register_cascade_mode = "off"; +defparam \LS[5] .sum_lutc_input = "cin"; +defparam \LS[5] .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X2_Y3_N9 +maxii_lcell \LS[6] ( +// Equation(s): +// LS[6] = DFFEAS((LS[6] $ (((!\LS[1]~3 & \LS[5]~15 ) # (\LS[1]~3 & \LS[5]~15COUT1_31 )))), GLOBAL(\C25M~combout ), VCC, , \Equal2~1_combout , , , , ) +// \LS[6]~17 = CARRY(((!\LS[5]~15COUT1_31 ) # (!LS[6]))) + + .clk(\C25M~combout ), + .dataa(vcc), + .datab(LS[6]), + .datac(vcc), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal2~1_combout ), + .cin(\LS[1]~3 ), + .cin0(\LS[5]~15 ), + .cin1(\LS[5]~15COUT1_31 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(LS[6]), + .cout(\LS[6]~17 ), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \LS[6] .cin0_used = "true"; +defparam \LS[6] .cin1_used = "true"; +defparam \LS[6] .cin_used = "true"; +defparam \LS[6] .lut_mask = "3c3f"; +defparam \LS[6] .operation_mode = "arithmetic"; +defparam \LS[6] .output_mode = "reg_only"; +defparam \LS[6] .register_cascade_mode = "off"; +defparam \LS[6] .sum_lutc_input = "cin"; +defparam \LS[6] .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X3_Y3_N0 +maxii_lcell \LS[7] ( +// Equation(s): +// LS[7] = DFFEAS((LS[7] $ ((!\LS[6]~17 ))), GLOBAL(\C25M~combout ), VCC, , \Equal2~1_combout , , , , ) +// \LS[7]~19 = CARRY(((LS[7] & !\LS[6]~17 ))) +// \LS[7]~19COUT1_32 = CARRY(((LS[7] & !\LS[6]~17 ))) + + .clk(\C25M~combout ), + .dataa(vcc), + .datab(LS[7]), + .datac(vcc), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal2~1_combout ), + .cin(\LS[6]~17 ), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(LS[7]), + .cout(), + .cout0(\LS[7]~19 ), + .cout1(\LS[7]~19COUT1_32 )); +// synopsys translate_off +defparam \LS[7] .cin_used = "true"; +defparam \LS[7] .lut_mask = "c30c"; +defparam \LS[7] .operation_mode = "arithmetic"; +defparam \LS[7] .output_mode = "reg_only"; +defparam \LS[7] .register_cascade_mode = "off"; +defparam \LS[7] .sum_lutc_input = "cin"; +defparam \LS[7] .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X2_Y3_N2 +maxii_lcell \Equal3~0 ( +// Equation(s): +// \Equal3~0_combout = (LS[1] & (LS[7] & (LS[3] & LS[6]))) + + .clk(gnd), + .dataa(LS[1]), + .datab(LS[7]), + .datac(LS[3]), + .datad(LS[6]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Equal3~0_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Equal3~0 .lut_mask = "8000"; +defparam \Equal3~0 .operation_mode = "normal"; +defparam \Equal3~0 .output_mode = "comb_only"; +defparam \Equal3~0 .register_cascade_mode = "off"; +defparam \Equal3~0 .sum_lutc_input = "datac"; +defparam \Equal3~0 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X3_Y3_N1 +maxii_lcell \LS[8] ( +// Equation(s): +// LS[8] = DFFEAS((LS[8] $ (((!\LS[6]~17 & \LS[7]~19 ) # (\LS[6]~17 & \LS[7]~19COUT1_32 )))), GLOBAL(\C25M~combout ), VCC, , \Equal2~1_combout , , , , ) +// \LS[8]~21 = CARRY(((!\LS[7]~19 ) # (!LS[8]))) +// \LS[8]~21COUT1_33 = CARRY(((!\LS[7]~19COUT1_32 ) # (!LS[8]))) + + .clk(\C25M~combout ), + .dataa(vcc), + .datab(LS[8]), + .datac(vcc), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal2~1_combout ), + .cin(\LS[6]~17 ), + .cin0(\LS[7]~19 ), + .cin1(\LS[7]~19COUT1_32 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(LS[8]), + .cout(), + .cout0(\LS[8]~21 ), + .cout1(\LS[8]~21COUT1_33 )); +// synopsys translate_off +defparam \LS[8] .cin0_used = "true"; +defparam \LS[8] .cin1_used = "true"; +defparam \LS[8] .cin_used = "true"; +defparam \LS[8] .lut_mask = "3c3f"; +defparam \LS[8] .operation_mode = "arithmetic"; +defparam \LS[8] .output_mode = "reg_only"; +defparam \LS[8] .register_cascade_mode = "off"; +defparam \LS[8] .sum_lutc_input = "cin"; +defparam \LS[8] .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X3_Y3_N2 +maxii_lcell \LS[9] ( +// Equation(s): +// LS[9] = DFFEAS((LS[9] $ ((!(!\LS[6]~17 & \LS[8]~21 ) # (\LS[6]~17 & \LS[8]~21COUT1_33 )))), GLOBAL(\C25M~combout ), VCC, , \Equal2~1_combout , , , , ) +// \LS[9]~23 = CARRY(((LS[9] & !\LS[8]~21 ))) +// \LS[9]~23COUT1_34 = CARRY(((LS[9] & !\LS[8]~21COUT1_33 ))) + + .clk(\C25M~combout ), + .dataa(vcc), + .datab(LS[9]), + .datac(vcc), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal2~1_combout ), + .cin(\LS[6]~17 ), + .cin0(\LS[8]~21 ), + .cin1(\LS[8]~21COUT1_33 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(LS[9]), + .cout(), + .cout0(\LS[9]~23 ), + .cout1(\LS[9]~23COUT1_34 )); +// synopsys translate_off +defparam \LS[9] .cin0_used = "true"; +defparam \LS[9] .cin1_used = "true"; +defparam \LS[9] .cin_used = "true"; +defparam \LS[9] .lut_mask = "c30c"; +defparam \LS[9] .operation_mode = "arithmetic"; +defparam \LS[9] .output_mode = "reg_only"; +defparam \LS[9] .register_cascade_mode = "off"; +defparam \LS[9] .sum_lutc_input = "cin"; +defparam \LS[9] .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X3_Y3_N3 +maxii_lcell \LS[10] ( +// Equation(s): +// LS[10] = DFFEAS(LS[10] $ (((((!\LS[6]~17 & \LS[9]~23 ) # (\LS[6]~17 & \LS[9]~23COUT1_34 ))))), GLOBAL(\C25M~combout ), VCC, , \Equal2~1_combout , , , , ) +// \LS[10]~1 = CARRY(((!\LS[9]~23 )) # (!LS[10])) +// \LS[10]~1COUT1_35 = CARRY(((!\LS[9]~23COUT1_34 )) # (!LS[10])) + + .clk(\C25M~combout ), + .dataa(LS[10]), + .datab(vcc), + .datac(vcc), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal2~1_combout ), + .cin(\LS[6]~17 ), + .cin0(\LS[9]~23 ), + .cin1(\LS[9]~23COUT1_34 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(LS[10]), + .cout(), + .cout0(\LS[10]~1 ), + .cout1(\LS[10]~1COUT1_35 )); +// synopsys translate_off +defparam \LS[10] .cin0_used = "true"; +defparam \LS[10] .cin1_used = "true"; +defparam \LS[10] .cin_used = "true"; +defparam \LS[10] .lut_mask = "5a5f"; +defparam \LS[10] .operation_mode = "arithmetic"; +defparam \LS[10] .output_mode = "reg_only"; +defparam \LS[10] .register_cascade_mode = "off"; +defparam \LS[10] .sum_lutc_input = "cin"; +defparam \LS[10] .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X3_Y3_N4 +maxii_lcell \LS[11] ( +// Equation(s): +// LS[11] = DFFEAS(LS[11] $ ((((!(!\LS[6]~17 & \LS[10]~1 ) # (\LS[6]~17 & \LS[10]~1COUT1_35 ))))), GLOBAL(\C25M~combout ), VCC, , \Equal2~1_combout , , , , ) +// \LS[11]~5 = CARRY((LS[11] & ((!\LS[10]~1COUT1_35 )))) + + .clk(\C25M~combout ), + .dataa(LS[11]), + .datab(vcc), + .datac(vcc), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal2~1_combout ), + .cin(\LS[6]~17 ), + .cin0(\LS[10]~1 ), + .cin1(\LS[10]~1COUT1_35 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(LS[11]), + .cout(\LS[11]~5 ), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \LS[11] .cin0_used = "true"; +defparam \LS[11] .cin1_used = "true"; +defparam \LS[11] .cin_used = "true"; +defparam \LS[11] .lut_mask = "a50a"; +defparam \LS[11] .operation_mode = "arithmetic"; +defparam \LS[11] .output_mode = "reg_only"; +defparam \LS[11] .register_cascade_mode = "off"; +defparam \LS[11] .sum_lutc_input = "cin"; +defparam \LS[11] .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X3_Y3_N5 +maxii_lcell \LS[12] ( +// Equation(s): +// LS[12] = DFFEAS(LS[12] $ ((((\LS[11]~5 )))), GLOBAL(\C25M~combout ), VCC, , \Equal2~1_combout , , , , ) +// \LS[12]~9 = CARRY(((!\LS[11]~5 )) # (!LS[12])) +// \LS[12]~9COUT1_36 = CARRY(((!\LS[11]~5 )) # (!LS[12])) + + .clk(\C25M~combout ), + .dataa(LS[12]), + .datab(vcc), + .datac(vcc), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal2~1_combout ), + .cin(\LS[11]~5 ), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(LS[12]), + .cout(), + .cout0(\LS[12]~9 ), + .cout1(\LS[12]~9COUT1_36 )); +// synopsys translate_off +defparam \LS[12] .cin_used = "true"; +defparam \LS[12] .lut_mask = "5a5f"; +defparam \LS[12] .operation_mode = "arithmetic"; +defparam \LS[12] .output_mode = "reg_only"; +defparam \LS[12] .register_cascade_mode = "off"; +defparam \LS[12] .sum_lutc_input = "cin"; +defparam \LS[12] .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X3_Y3_N9 +maxii_lcell \Equal3~1 ( +// Equation(s): +// \Equal3~1_combout = (LS[10] & (LS[8] & (LS[11] & LS[9]))) + + .clk(gnd), + .dataa(LS[10]), + .datab(LS[8]), + .datac(LS[11]), + .datad(LS[9]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Equal3~1_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Equal3~1 .lut_mask = "8000"; +defparam \Equal3~1 .operation_mode = "normal"; +defparam \Equal3~1 .output_mode = "comb_only"; +defparam \Equal3~1 .register_cascade_mode = "off"; +defparam \Equal3~1 .sum_lutc_input = "datac"; +defparam \Equal3~1 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X3_Y3_N8 +maxii_lcell \Equal3~2 ( +// Equation(s): +// \Equal3~2_combout = ((\Equal3~0_combout & (LS[12] & \Equal3~1_combout ))) + + .clk(gnd), + .dataa(vcc), + .datab(\Equal3~0_combout ), + .datac(LS[12]), + .datad(\Equal3~1_combout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Equal3~2_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Equal3~2 .lut_mask = "c000"; +defparam \Equal3~2 .operation_mode = "normal"; +defparam \Equal3~2 .output_mode = "comb_only"; +defparam \Equal3~2 .register_cascade_mode = "off"; +defparam \Equal3~2 .sum_lutc_input = "datac"; +defparam \Equal3~2 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X2_Y3_N3 +maxii_lcell \Equal5~0 ( +// Equation(s): +// \Equal5~0_combout = (LS[5] & (((LS[4] & \Equal3~2_combout )))) + + .clk(gnd), + .dataa(LS[5]), + .datab(vcc), + .datac(LS[4]), + .datad(\Equal3~2_combout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Equal5~0_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Equal5~0 .lut_mask = "a000"; +defparam \Equal5~0 .operation_mode = "normal"; +defparam \Equal5~0 .output_mode = "comb_only"; +defparam \Equal5~0 .register_cascade_mode = "off"; +defparam \Equal5~0 .sum_lutc_input = "datac"; +defparam \Equal5~0 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X2_Y2_N6 +maxii_lcell \Equal6~0 ( +// Equation(s): +// \Equal6~0_combout = (LS[0] & (\Equal5~0_combout & (LS[2]))) + + .clk(gnd), + .dataa(LS[0]), + .datab(\Equal5~0_combout ), + .datac(LS[2]), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Equal6~0_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Equal6~0 .lut_mask = "8080"; +defparam \Equal6~0 .operation_mode = "normal"; +defparam \Equal6~0 .output_mode = "comb_only"; +defparam \Equal6~0 .register_cascade_mode = "off"; +defparam \Equal6~0 .sum_lutc_input = "datac"; +defparam \Equal6~0 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X3_Y3_N6 +maxii_lcell \LS[13] ( +// Equation(s): +// LS[13] = DFFEAS((((!\LS[11]~5 & \LS[12]~9 ) # (\LS[11]~5 & \LS[12]~9COUT1_36 ) $ (!LS[13]))), GLOBAL(\C25M~combout ), VCC, , \Equal2~1_combout , , , , ) + + .clk(\C25M~combout ), + .dataa(vcc), + .datab(vcc), + .datac(vcc), + .datad(LS[13]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal2~1_combout ), + .cin(\LS[11]~5 ), + .cin0(\LS[12]~9 ), + .cin1(\LS[12]~9COUT1_36 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(LS[13]), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \LS[13] .cin0_used = "true"; +defparam \LS[13] .cin1_used = "true"; +defparam \LS[13] .cin_used = "true"; +defparam \LS[13] .lut_mask = "f00f"; +defparam \LS[13] .operation_mode = "normal"; +defparam \LS[13] .output_mode = "reg_only"; +defparam \LS[13] .register_cascade_mode = "off"; +defparam \LS[13] .sum_lutc_input = "cin"; +defparam \LS[13] .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X2_Y2_N9 +maxii_lcell \IS.111 ( +// Equation(s): +// \IS.111~regout = DFFEAS((\IS.111~regout ) # ((\Equal2~1_combout & (\Equal6~0_combout & LS[13]))), GLOBAL(\C25M~combout ), VCC, , , , , , ) + + .clk(\C25M~combout ), + .dataa(\Equal2~1_combout ), + .datab(\IS.111~regout ), + .datac(\Equal6~0_combout ), + .datad(LS[13]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\IS.111~regout ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \IS.111 .lut_mask = "eccc"; +defparam \IS.111 .operation_mode = "normal"; +defparam \IS.111 .output_mode = "reg_only"; +defparam \IS.111 .register_cascade_mode = "off"; +defparam \IS.111 .sum_lutc_input = "datac"; +defparam \IS.111 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X3_Y1_N8 +maxii_lcell \nRESout~reg0 ( +// Equation(s): +// \nRESout~reg0_regout = DFFEAS((((\IS.111~regout ) # (\nRESout~reg0_regout ))), GLOBAL(\C25M~combout ), VCC, , , , , , ) + + .clk(\C25M~combout ), + .dataa(vcc), + .datab(vcc), + .datac(\IS.111~regout ), + .datad(\nRESout~reg0_regout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\nRESout~reg0_regout ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \nRESout~reg0 .lut_mask = "fff0"; +defparam \nRESout~reg0 .operation_mode = "normal"; +defparam \nRESout~reg0 .output_mode = "reg_only"; +defparam \nRESout~reg0 .register_cascade_mode = "off"; +defparam \nRESout~reg0 .sum_lutc_input = "datac"; +defparam \nRESout~reg0 .synch_mode = "off"; +// synopsys translate_on + +// Location: PIN_49, I/O Standard: 3.3-V LVTTL, Current Strength: Default +maxii_io \INTin~I ( + .datain(gnd), + .oe(gnd), + .combout(\INTin~combout ), + .padio(INTin)); +// synopsys translate_off +defparam \INTin~I .operation_mode = "input"; +// synopsys translate_on + +// Location: PIN_48, I/O Standard: 3.3-V LVTTL, Current Strength: Default +maxii_io \DMAin~I ( + .datain(gnd), + .oe(gnd), + .combout(\DMAin~combout ), + .padio(DMAin)); +// synopsys translate_off +defparam \DMAin~I .operation_mode = "input"; +// synopsys translate_on + +// Location: LC_X2_Y2_N4 +maxii_lcell \IS~17 ( +// Equation(s): +// \IS~17_combout = (((\IS.111~regout ) # (!\Equal2~1_combout ))) + + .clk(gnd), + .dataa(vcc), + .datab(vcc), + .datac(\Equal2~1_combout ), + .datad(\IS.111~regout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\IS~17_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \IS~17 .lut_mask = "ff0f"; +defparam \IS~17 .operation_mode = "normal"; +defparam \IS~17 .output_mode = "comb_only"; +defparam \IS~17 .register_cascade_mode = "off"; +defparam \IS~17 .sum_lutc_input = "datac"; +defparam \IS~17 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X2_Y2_N2 +maxii_lcell \IS~18 ( +// Equation(s): +// \IS~18_combout = ((LS[2] & (!LS[0])) # (!LS[2] & ((LS[0]) # (LS[13])))) # (!\Equal5~0_combout ) + + .clk(gnd), + .dataa(LS[2]), + .datab(\Equal5~0_combout ), + .datac(LS[0]), + .datad(LS[13]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\IS~18_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \IS~18 .lut_mask = "7f7b"; +defparam \IS~18 .operation_mode = "normal"; +defparam \IS~18 .output_mode = "comb_only"; +defparam \IS~18 .register_cascade_mode = "off"; +defparam \IS~18 .sum_lutc_input = "datac"; +defparam \IS~18 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X2_Y3_N0 +maxii_lcell \Equal3~3 ( +// Equation(s): +// \Equal3~3_combout = (LS[2] & (!LS[4] & (!LS[13] & !LS[5]))) + + .clk(gnd), + .dataa(LS[2]), + .datab(LS[4]), + .datac(LS[13]), + .datad(LS[5]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Equal3~3_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Equal3~3 .lut_mask = "0002"; +defparam \Equal3~3 .operation_mode = "normal"; +defparam \Equal3~3 .output_mode = "comb_only"; +defparam \Equal3~3 .register_cascade_mode = "off"; +defparam \Equal3~3 .sum_lutc_input = "datac"; +defparam \Equal3~3 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X2_Y2_N0 +maxii_lcell \IS.100 ( +// Equation(s): +// \Equal4~0 = (LS[0] & (((\Equal3~3_combout & \Equal3~2_combout )))) +// \IS.100~regout = DFFEAS(\Equal4~0 , GLOBAL(\C25M~combout ), VCC, , \IS~19_combout , , , , ) + + .clk(\C25M~combout ), + .dataa(LS[0]), + .datab(vcc), + .datac(\Equal3~3_combout ), + .datad(\Equal3~2_combout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\IS~19_combout ), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Equal4~0 ), + .regout(\IS.100~regout ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \IS.100 .lut_mask = "a000"; +defparam \IS.100 .operation_mode = "normal"; +defparam \IS.100 .output_mode = "reg_and_comb"; +defparam \IS.100 .register_cascade_mode = "off"; +defparam \IS.100 .sum_lutc_input = "datac"; +defparam \IS.100 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X2_Y2_N3 +maxii_lcell \IS.001 ( +// Equation(s): +// \Equal3~4 = (!LS[0] & (((\Equal3~3_combout & \Equal3~2_combout )))) +// \IS.001~regout = DFFEAS(\Equal3~4 , GLOBAL(\C25M~combout ), VCC, , \IS~19_combout , , , , ) + + .clk(\C25M~combout ), + .dataa(LS[0]), + .datab(vcc), + .datac(\Equal3~3_combout ), + .datad(\Equal3~2_combout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\IS~19_combout ), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Equal3~4 ), + .regout(\IS.001~regout ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \IS.001 .lut_mask = "5000"; +defparam \IS.001 .operation_mode = "normal"; +defparam \IS.001 .output_mode = "reg_and_comb"; +defparam \IS.001 .register_cascade_mode = "off"; +defparam \IS.001 .sum_lutc_input = "datac"; +defparam \IS.001 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X2_Y2_N7 +maxii_lcell \IS~19 ( +// Equation(s): +// \IS~19_combout = (!\IS~17_combout & (((\Equal4~0 ) # (\Equal3~4 )) # (!\IS~18_combout ))) + + .clk(gnd), + .dataa(\IS~17_combout ), + .datab(\IS~18_combout ), + .datac(\Equal4~0 ), + .datad(\Equal3~4 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\IS~19_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \IS~19 .lut_mask = "5551"; +defparam \IS~19 .operation_mode = "normal"; +defparam \IS~19 .output_mode = "comb_only"; +defparam \IS~19 .register_cascade_mode = "off"; +defparam \IS~19 .sum_lutc_input = "datac"; +defparam \IS~19 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X2_Y2_N5 +maxii_lcell \IS.110 ( +// Equation(s): +// \IS.110~regout = DFFEAS((LS[2] & (\Equal5~0_combout & (LS[0] & !LS[13]))), GLOBAL(\C25M~combout ), VCC, , \IS~19_combout , , , , ) + + .clk(\C25M~combout ), + .dataa(LS[2]), + .datab(\Equal5~0_combout ), + .datac(LS[0]), + .datad(LS[13]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\IS~19_combout ), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\IS.110~regout ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \IS.110 .lut_mask = "0080"; +defparam \IS.110 .operation_mode = "normal"; +defparam \IS.110 .output_mode = "reg_only"; +defparam \IS.110 .register_cascade_mode = "off"; +defparam \IS.110 .sum_lutc_input = "datac"; +defparam \IS.110 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X4_Y2_N3 +maxii_lcell \SA[1]~3 ( +// Equation(s): +// \SA[1]~3_combout = (((!PS[1] & \IS.110~regout )) # (!PS[0])) + + .clk(gnd), + .dataa(vcc), + .datab(PS[1]), + .datac(\IS.110~regout ), + .datad(PS[0]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\SA[1]~3_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \SA[1]~3 .lut_mask = "30ff"; +defparam \SA[1]~3 .operation_mode = "normal"; +defparam \SA[1]~3 .output_mode = "comb_only"; +defparam \SA[1]~3 .register_cascade_mode = "off"; +defparam \SA[1]~3 .sum_lutc_input = "datac"; +defparam \SA[1]~3 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X3_Y3_N7 +maxii_lcell \Mux22~0 ( +// Equation(s): +// \Mux22~0_combout = ((PS[0] & (LS[12]))) + + .clk(gnd), + .dataa(vcc), + .datab(PS[0]), + .datac(LS[12]), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Mux22~0_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Mux22~0 .lut_mask = "c0c0"; +defparam \Mux22~0 .operation_mode = "normal"; +defparam \Mux22~0 .output_mode = "comb_only"; +defparam \Mux22~0 .register_cascade_mode = "off"; +defparam \Mux22~0 .sum_lutc_input = "datac"; +defparam \Mux22~0 .synch_mode = "off"; +// synopsys translate_on + +// Location: PIN_4, I/O Standard: 3.3-V LVTTL, Current Strength: Default +maxii_io \RA[3]~I ( + .datain(gnd), + .oe(gnd), + .combout(\RA~combout [3]), + .padio(RA[3])); +// synopsys translate_off +defparam \RA[3]~I .operation_mode = "input"; +// synopsys translate_on + +// Location: PIN_98, I/O Standard: 3.3-V LVTTL, Current Strength: Default +maxii_io \RA[1]~I ( + .datain(gnd), + .oe(gnd), + .combout(\RA~combout [1]), + .padio(RA[1])); +// synopsys translate_off +defparam \RA[1]~I .operation_mode = "input"; +// synopsys translate_on + +// Location: LC_X4_Y3_N4 +maxii_lcell \RAr[1] ( +// Equation(s): +// \RAMRegSpecSEL~0 = (RAr[0] & (((RAr[1])))) +// RAr[1] = DFFEAS(\RAMRegSpecSEL~0 , GLOBAL(\PHI0~combout ), VCC, , , \RA~combout [1], , , VCC) + + .clk(\PHI0~combout ), + .dataa(RAr[0]), + .datab(vcc), + .datac(\RA~combout [1]), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\RAMRegSpecSEL~0 ), + .regout(RAr[1]), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \RAr[1] .lut_mask = "a0a0"; +defparam \RAr[1] .operation_mode = "normal"; +defparam \RAr[1] .output_mode = "reg_and_comb"; +defparam \RAr[1] .register_cascade_mode = "off"; +defparam \RAr[1] .sum_lutc_input = "qfbk"; +defparam \RAr[1] .synch_mode = "on"; +// synopsys translate_on + +// Location: LC_X3_Y2_N3 +maxii_lcell \SA[1]~2 ( +// Equation(s): +// \SA[1]~2_combout = (PS[1]) # (((\IS.110~regout ) # (!PS[0]))) + + .clk(gnd), + .dataa(PS[1]), + .datab(vcc), + .datac(\IS.110~regout ), + .datad(PS[0]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\SA[1]~2_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \SA[1]~2 .lut_mask = "faff"; +defparam \SA[1]~2 .operation_mode = "normal"; +defparam \SA[1]~2 .output_mode = "comb_only"; +defparam \SA[1]~2 .register_cascade_mode = "off"; +defparam \SA[1]~2 .sum_lutc_input = "datac"; +defparam \SA[1]~2 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X4_Y3_N8 +maxii_lcell \Mux24~0 ( +// Equation(s): +// \Mux24~0_combout = ((LS[10] & ((PS[0])))) + + .clk(gnd), + .dataa(vcc), + .datab(LS[10]), + .datac(vcc), + .datad(PS[0]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Mux24~0_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Mux24~0 .lut_mask = "cc00"; +defparam \Mux24~0 .operation_mode = "normal"; +defparam \Mux24~0 .output_mode = "comb_only"; +defparam \Mux24~0 .register_cascade_mode = "off"; +defparam \Mux24~0 .sum_lutc_input = "datac"; +defparam \Mux24~0 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X4_Y3_N3 +maxii_lcell \Mux24~1 ( +// Equation(s): +// \Mux24~1_combout = (\SA[1]~4_combout & (((RAr[1] & \SA[1]~3_combout )))) # (!\SA[1]~4_combout & ((\Mux24~0_combout ) # ((!\SA[1]~3_combout )))) + + .clk(gnd), + .dataa(\Mux24~0_combout ), + .datab(\SA[1]~4_combout ), + .datac(RAr[1]), + .datad(\SA[1]~3_combout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Mux24~1_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Mux24~1 .lut_mask = "e233"; +defparam \Mux24~1 .operation_mode = "normal"; +defparam \Mux24~1 .output_mode = "comb_only"; +defparam \Mux24~1 .register_cascade_mode = "off"; +defparam \Mux24~1 .sum_lutc_input = "datac"; +defparam \Mux24~1 .synch_mode = "off"; +// synopsys translate_on + +// Location: PIN_14, I/O Standard: 3.3-V LVTTL, Current Strength: Default +maxii_io \RA[10]~I ( + .datain(gnd), + .oe(gnd), + .combout(\RA~combout [10]), + .padio(RA[10])); +// synopsys translate_off +defparam \RA[10]~I .operation_mode = "input"; +// synopsys translate_on + +// Location: PIN_44, I/O Standard: 3.3V Schmitt Trigger Input, Current Strength: Default +maxii_io \nRES~I ( + .datain(gnd), + .oe(gnd), + .combout(\nRES~combout ), + .padio(nRES)); +// synopsys translate_off +defparam \nRES~I .operation_mode = "input"; +// synopsys translate_on + +// Location: LC_X3_Y1_N4 +maxii_lcell \nRESf[0] ( +// Equation(s): +// nRESf[0] = DFFEAS(GND, GLOBAL(\C25M~combout ), VCC, , , \nRES~combout , , , VCC) + + .clk(\C25M~combout ), + .dataa(vcc), + .datab(vcc), + .datac(\nRES~combout ), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(nRESf[0]), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \nRESf[0] .lut_mask = "0000"; +defparam \nRESf[0] .operation_mode = "normal"; +defparam \nRESf[0] .output_mode = "reg_only"; +defparam \nRESf[0] .register_cascade_mode = "off"; +defparam \nRESf[0] .sum_lutc_input = "datac"; +defparam \nRESf[0] .synch_mode = "on"; +// synopsys translate_on + +// Location: LC_X3_Y1_N6 +maxii_lcell \nRESf[1] ( +// Equation(s): +// nRESf[1] = DFFEAS(GND, GLOBAL(\C25M~combout ), VCC, , , nRESf[0], , , VCC) + + .clk(\C25M~combout ), + .dataa(vcc), + .datab(vcc), + .datac(nRESf[0]), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(nRESf[1]), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \nRESf[1] .lut_mask = "0000"; +defparam \nRESf[1] .operation_mode = "normal"; +defparam \nRESf[1] .output_mode = "reg_only"; +defparam \nRESf[1] .register_cascade_mode = "off"; +defparam \nRESf[1] .sum_lutc_input = "datac"; +defparam \nRESf[1] .synch_mode = "on"; +// synopsys translate_on + +// Location: LC_X3_Y1_N5 +maxii_lcell \nRESf[2] ( +// Equation(s): +// nRESf[2] = DFFEAS(GND, GLOBAL(\C25M~combout ), VCC, , , nRESf[1], , , VCC) + + .clk(\C25M~combout ), + .dataa(vcc), + .datab(vcc), + .datac(nRESf[1]), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(nRESf[2]), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \nRESf[2] .lut_mask = "0000"; +defparam \nRESf[2] .operation_mode = "normal"; +defparam \nRESf[2] .output_mode = "reg_only"; +defparam \nRESf[2] .register_cascade_mode = "off"; +defparam \nRESf[2] .sum_lutc_input = "datac"; +defparam \nRESf[2] .synch_mode = "on"; +// synopsys translate_on + +// Location: LC_X3_Y1_N9 +maxii_lcell \nRESf[3] ( +// Equation(s): +// nRESf[3] = DFFEAS(GND, GLOBAL(\C25M~combout ), VCC, , , nRESf[2], , , VCC) + + .clk(\C25M~combout ), + .dataa(vcc), + .datab(vcc), + .datac(nRESf[2]), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(nRESf[3]), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \nRESf[3] .lut_mask = "0000"; +defparam \nRESf[3] .operation_mode = "normal"; +defparam \nRESf[3] .output_mode = "reg_only"; +defparam \nRESf[3] .register_cascade_mode = "off"; +defparam \nRESf[3] .sum_lutc_input = "datac"; +defparam \nRESf[3] .synch_mode = "on"; +// synopsys translate_on + +// Location: LC_X3_Y1_N7 +maxii_lcell nRESr( +// Equation(s): +// \nRESr~regout = DFFEAS((nRESf[0]) # ((nRESf[3]) # ((nRESf[2]) # (nRESf[1]))), GLOBAL(\C25M~combout ), VCC, , , , , , ) + + .clk(\C25M~combout ), + .dataa(nRESf[0]), + .datab(nRESf[3]), + .datac(nRESf[2]), + .datad(nRESf[1]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\nRESr~regout ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam nRESr.lut_mask = "fffe"; +defparam nRESr.operation_mode = "normal"; +defparam nRESr.output_mode = "reg_only"; +defparam nRESr.register_cascade_mode = "off"; +defparam nRESr.sum_lutc_input = "datac"; +defparam nRESr.synch_mode = "off"; +// synopsys translate_on + +// Location: PIN_40, I/O Standard: 3.3V Schmitt Trigger Input, Current Strength: Default +maxii_io \nDEVSEL~I ( + .datain(gnd), + .oe(gnd), + .combout(\nDEVSEL~combout ), + .padio(nDEVSEL)); +// synopsys translate_off +defparam \nDEVSEL~I .operation_mode = "input"; +// synopsys translate_on + +// Location: LC_X5_Y1_N3 +maxii_lcell \nRCS~0 ( +// Equation(s): +// \nRCS~0_combout = (((!\nDEVSEL~combout & \IS.111~regout ))) + + .clk(gnd), + .dataa(vcc), + .datab(vcc), + .datac(\nDEVSEL~combout ), + .datad(\IS.111~regout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\nRCS~0_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \nRCS~0 .lut_mask = "0f00"; +defparam \nRCS~0 .operation_mode = "normal"; +defparam \nRCS~0 .output_mode = "comb_only"; +defparam \nRCS~0 .register_cascade_mode = "off"; +defparam \nRCS~0 .sum_lutc_input = "datac"; +defparam \nRCS~0 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X5_Y1_N2 +maxii_lcell nWEr( +// Equation(s): +// \nRCS~1 = (\IS.110~regout ) # ((\nRCS~0_combout & (\RAMSpecSEL~1_combout & !nWEr))) +// \nWEr~regout = DFFEAS(\nRCS~1 , GLOBAL(\PHI0~combout ), VCC, , , \nWE~combout , , , VCC) + + .clk(\PHI0~combout ), + .dataa(\nRCS~0_combout ), + .datab(\RAMSpecSEL~1_combout ), + .datac(\nWE~combout ), + .datad(\IS.110~regout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\nRCS~1 ), + .regout(\nWEr~regout ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam nWEr.lut_mask = "ff08"; +defparam nWEr.operation_mode = "normal"; +defparam nWEr.output_mode = "reg_and_comb"; +defparam nWEr.register_cascade_mode = "off"; +defparam nWEr.sum_lutc_input = "qfbk"; +defparam nWEr.synch_mode = "on"; +// synopsys translate_on + +// Location: LC_X2_Y1_N7 +maxii_lcell \Equal19~0 ( +// Equation(s): +// \Equal19~0_combout = (PS[3] & (!PS[2] & (!PS[1] & !PS[0]))) + + .clk(gnd), + .dataa(PS[3]), + .datab(PS[2]), + .datac(PS[1]), + .datad(PS[0]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Equal19~0_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Equal19~0 .lut_mask = "0002"; +defparam \Equal19~0 .operation_mode = "normal"; +defparam \Equal19~0 .output_mode = "comb_only"; +defparam \Equal19~0 .register_cascade_mode = "off"; +defparam \Equal19~0 .sum_lutc_input = "datac"; +defparam \Equal19~0 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X5_Y1_N5 +maxii_lcell \always9~1 ( +// Equation(s): +// \always9~1_combout = (!\nWEr~regout & (!\nDEVSEL~combout & (\Equal19~0_combout & \always9~0_combout ))) + + .clk(gnd), + .dataa(\nWEr~regout ), + .datab(\nDEVSEL~combout ), + .datac(\Equal19~0_combout ), + .datad(\always9~0_combout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\always9~1_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \always9~1 .lut_mask = "1000"; +defparam \always9~1 .operation_mode = "normal"; +defparam \always9~1 .output_mode = "comb_only"; +defparam \always9~1 .register_cascade_mode = "off"; +defparam \always9~1 .sum_lutc_input = "datac"; +defparam \always9~1 .synch_mode = "off"; +// synopsys translate_on + +// Location: PIN_97, I/O Standard: 3.3-V LVTTL, Current Strength: Default +maxii_io \RA[2]~I ( + .datain(gnd), + .oe(gnd), + .combout(\RA~combout [2]), + .padio(RA[2])); +// synopsys translate_off +defparam \RA[2]~I .operation_mode = "input"; +// synopsys translate_on + +// Location: LC_X4_Y3_N0 +maxii_lcell \RAr[2] ( +// Equation(s): +// \RAMRegSpecSEL~1 = (!RAr[3] & (((!RAr[2])))) +// RAr[2] = DFFEAS(\RAMRegSpecSEL~1 , GLOBAL(\PHI0~combout ), VCC, , , \RA~combout [2], , , VCC) + + .clk(\PHI0~combout ), + .dataa(RAr[3]), + .datab(vcc), + .datac(\RA~combout [2]), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\RAMRegSpecSEL~1 ), + .regout(RAr[2]), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \RAr[2] .lut_mask = "0505"; +defparam \RAr[2] .operation_mode = "normal"; +defparam \RAr[2] .output_mode = "reg_and_comb"; +defparam \RAr[2] .register_cascade_mode = "off"; +defparam \RAr[2] .sum_lutc_input = "qfbk"; +defparam \RAr[2] .synch_mode = "on"; +// synopsys translate_on + +// Location: LC_X7_Y3_N7 +maxii_lcell \always9~3 ( +// Equation(s): +// \always9~3_combout = (\always9~1_combout & (RAr[0] & (!RAr[1] & \RAMRegSpecSEL~1 ))) + + .clk(gnd), + .dataa(\always9~1_combout ), + .datab(RAr[0]), + .datac(RAr[1]), + .datad(\RAMRegSpecSEL~1 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\always9~3_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \always9~3 .lut_mask = "0800"; +defparam \always9~3 .operation_mode = "normal"; +defparam \always9~3 .output_mode = "comb_only"; +defparam \always9~3 .register_cascade_mode = "off"; +defparam \always9~3 .sum_lutc_input = "datac"; +defparam \always9~3 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X6_Y3_N9 +maxii_lcell \always9~4 ( +// Equation(s): +// \always9~4_combout = (\RAMRegSpecSEL~1 & (!RAr[1] & (\always9~1_combout & !RAr[0]))) + + .clk(gnd), + .dataa(\RAMRegSpecSEL~1 ), + .datab(RAr[1]), + .datac(\always9~1_combout ), + .datad(RAr[0]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\always9~4_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \always9~4 .lut_mask = "0020"; +defparam \always9~4 .operation_mode = "normal"; +defparam \always9~4 .output_mode = "comb_only"; +defparam \always9~4 .register_cascade_mode = "off"; +defparam \always9~4 .sum_lutc_input = "datac"; +defparam \always9~4 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X4_Y1_N1 +maxii_lcell \always9~5 ( +// Equation(s): +// \always9~5_combout = (!\nDEVSEL~combout & (((\Equal19~0_combout )))) + + .clk(gnd), + .dataa(\nDEVSEL~combout ), + .datab(vcc), + .datac(\Equal19~0_combout ), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\always9~5_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \always9~5 .lut_mask = "5050"; +defparam \always9~5 .operation_mode = "normal"; +defparam \always9~5 .output_mode = "comb_only"; +defparam \always9~5 .register_cascade_mode = "off"; +defparam \always9~5 .sum_lutc_input = "datac"; +defparam \always9~5 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X4_Y3_N6 +maxii_lcell AddrIncL( +// Equation(s): +// \AddrIncL~regout = DFFEAS((\always9~5_combout & (\always9~0_combout & (\RAMRegSpecSEL~0 & \RAMRegSpecSEL~1 ))), GLOBAL(\C25M~combout ), GLOBAL(\nRESr~regout ), , , , , , ) + + .clk(\C25M~combout ), + .dataa(\always9~5_combout ), + .datab(\always9~0_combout ), + .datac(\RAMRegSpecSEL~0 ), + .datad(\RAMRegSpecSEL~1 ), + .aclr(!\nRESr~regout ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\AddrIncL~regout ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam AddrIncL.lut_mask = "8000"; +defparam AddrIncL.operation_mode = "normal"; +defparam AddrIncL.output_mode = "reg_only"; +defparam AddrIncL.register_cascade_mode = "off"; +defparam AddrIncL.sum_lutc_input = "datac"; +defparam AddrIncL.synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X6_Y3_N0 +maxii_lcell \Addr[0] ( +// Equation(s): +// Addr[0] = DFFEAS(\AddrIncL~regout $ ((Addr[0])), GLOBAL(\C25M~combout ), GLOBAL(\nRESr~regout ), , , \RD[0]~0 , , , \always9~4_combout ) +// \Addr[0]~47 = CARRY((\AddrIncL~regout & (Addr[0]))) +// \Addr[0]~47COUT1_61 = CARRY((\AddrIncL~regout & (Addr[0]))) + + .clk(\C25M~combout ), + .dataa(\AddrIncL~regout ), + .datab(Addr[0]), + .datac(\RD[0]~0 ), + .datad(vcc), + .aclr(!\nRESr~regout ), + .aload(gnd), + .sclr(gnd), + .sload(\always9~4_combout ), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(Addr[0]), + .cout(), + .cout0(\Addr[0]~47 ), + .cout1(\Addr[0]~47COUT1_61 )); +// synopsys translate_off +defparam \Addr[0] .lut_mask = "6688"; +defparam \Addr[0] .operation_mode = "arithmetic"; +defparam \Addr[0] .output_mode = "reg_only"; +defparam \Addr[0] .register_cascade_mode = "off"; +defparam \Addr[0] .sum_lutc_input = "datac"; +defparam \Addr[0] .synch_mode = "on"; +// synopsys translate_on + +// Location: LC_X6_Y3_N1 +maxii_lcell \Addr[1] ( +// Equation(s): +// Addr[1] = DFFEAS((Addr[1] $ ((\Addr[0]~47 ))), GLOBAL(\C25M~combout ), GLOBAL(\nRESr~regout ), , , \RD[1]~1 , , , \always9~4_combout ) +// \Addr[1]~5 = CARRY(((!\Addr[0]~47 ) # (!Addr[1]))) +// \Addr[1]~5COUT1_62 = CARRY(((!\Addr[0]~47COUT1_61 ) # (!Addr[1]))) + + .clk(\C25M~combout ), + .dataa(vcc), + .datab(Addr[1]), + .datac(\RD[1]~1 ), + .datad(vcc), + .aclr(!\nRESr~regout ), + .aload(gnd), + .sclr(gnd), + .sload(\always9~4_combout ), + .ena(vcc), + .cin(gnd), + .cin0(\Addr[0]~47 ), + .cin1(\Addr[0]~47COUT1_61 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(Addr[1]), + .cout(), + .cout0(\Addr[1]~5 ), + .cout1(\Addr[1]~5COUT1_62 )); +// synopsys translate_off +defparam \Addr[1] .cin0_used = "true"; +defparam \Addr[1] .cin1_used = "true"; +defparam \Addr[1] .lut_mask = "3c3f"; +defparam \Addr[1] .operation_mode = "arithmetic"; +defparam \Addr[1] .output_mode = "reg_only"; +defparam \Addr[1] .register_cascade_mode = "off"; +defparam \Addr[1] .sum_lutc_input = "cin"; +defparam \Addr[1] .synch_mode = "on"; +// synopsys translate_on + +// Location: LC_X6_Y3_N2 +maxii_lcell \Addr[2] ( +// Equation(s): +// Addr[2] = DFFEAS((Addr[2] $ ((!\Addr[1]~5 ))), GLOBAL(\C25M~combout ), GLOBAL(\nRESr~regout ), , , \RD[2]~2 , , , \always9~4_combout ) +// \Addr[2]~9 = CARRY(((Addr[2] & !\Addr[1]~5 ))) +// \Addr[2]~9COUT1_63 = CARRY(((Addr[2] & !\Addr[1]~5COUT1_62 ))) + + .clk(\C25M~combout ), + .dataa(vcc), + .datab(Addr[2]), + .datac(\RD[2]~2 ), + .datad(vcc), + .aclr(!\nRESr~regout ), + .aload(gnd), + .sclr(gnd), + .sload(\always9~4_combout ), + .ena(vcc), + .cin(gnd), + .cin0(\Addr[1]~5 ), + .cin1(\Addr[1]~5COUT1_62 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(Addr[2]), + .cout(), + .cout0(\Addr[2]~9 ), + .cout1(\Addr[2]~9COUT1_63 )); +// synopsys translate_off +defparam \Addr[2] .cin0_used = "true"; +defparam \Addr[2] .cin1_used = "true"; +defparam \Addr[2] .lut_mask = "c30c"; +defparam \Addr[2] .operation_mode = "arithmetic"; +defparam \Addr[2] .output_mode = "reg_only"; +defparam \Addr[2] .register_cascade_mode = "off"; +defparam \Addr[2] .sum_lutc_input = "cin"; +defparam \Addr[2] .synch_mode = "on"; +// synopsys translate_on + +// Location: LC_X6_Y3_N3 +maxii_lcell \Addr[3] ( +// Equation(s): +// Addr[3] = DFFEAS(Addr[3] $ ((((\Addr[2]~9 )))), GLOBAL(\C25M~combout ), GLOBAL(\nRESr~regout ), , , \RD[3]~3 , , , \always9~4_combout ) +// \Addr[3]~13 = CARRY(((!\Addr[2]~9 )) # (!Addr[3])) +// \Addr[3]~13COUT1_64 = CARRY(((!\Addr[2]~9COUT1_63 )) # (!Addr[3])) + + .clk(\C25M~combout ), + .dataa(Addr[3]), + .datab(vcc), + .datac(\RD[3]~3 ), + .datad(vcc), + .aclr(!\nRESr~regout ), + .aload(gnd), + .sclr(gnd), + .sload(\always9~4_combout ), + .ena(vcc), + .cin(gnd), + .cin0(\Addr[2]~9 ), + .cin1(\Addr[2]~9COUT1_63 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(Addr[3]), + .cout(), + .cout0(\Addr[3]~13 ), + .cout1(\Addr[3]~13COUT1_64 )); +// synopsys translate_off +defparam \Addr[3] .cin0_used = "true"; +defparam \Addr[3] .cin1_used = "true"; +defparam \Addr[3] .lut_mask = "5a5f"; +defparam \Addr[3] .operation_mode = "arithmetic"; +defparam \Addr[3] .output_mode = "reg_only"; +defparam \Addr[3] .register_cascade_mode = "off"; +defparam \Addr[3] .sum_lutc_input = "cin"; +defparam \Addr[3] .synch_mode = "on"; +// synopsys translate_on + +// Location: LC_X6_Y3_N4 +maxii_lcell \Addr[4] ( +// Equation(s): +// Addr[4] = DFFEAS(Addr[4] $ ((((!\Addr[3]~13 )))), GLOBAL(\C25M~combout ), GLOBAL(\nRESr~regout ), , , \RD[4]~4 , , , \always9~4_combout ) +// \Addr[4]~17 = CARRY((Addr[4] & ((!\Addr[3]~13COUT1_64 )))) + + .clk(\C25M~combout ), + .dataa(Addr[4]), + .datab(vcc), + .datac(\RD[4]~4 ), + .datad(vcc), + .aclr(!\nRESr~regout ), + .aload(gnd), + .sclr(gnd), + .sload(\always9~4_combout ), + .ena(vcc), + .cin(gnd), + .cin0(\Addr[3]~13 ), + .cin1(\Addr[3]~13COUT1_64 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(Addr[4]), + .cout(\Addr[4]~17 ), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Addr[4] .cin0_used = "true"; +defparam \Addr[4] .cin1_used = "true"; +defparam \Addr[4] .lut_mask = "a50a"; +defparam \Addr[4] .operation_mode = "arithmetic"; +defparam \Addr[4] .output_mode = "reg_only"; +defparam \Addr[4] .register_cascade_mode = "off"; +defparam \Addr[4] .sum_lutc_input = "cin"; +defparam \Addr[4] .synch_mode = "on"; +// synopsys translate_on + +// Location: LC_X6_Y3_N5 +maxii_lcell \Addr[5] ( +// Equation(s): +// Addr[5] = DFFEAS(Addr[5] $ ((((\Addr[4]~17 )))), GLOBAL(\C25M~combout ), GLOBAL(\nRESr~regout ), , , \RD[5]~5 , , , \always9~4_combout ) +// \Addr[5]~21 = CARRY(((!\Addr[4]~17 )) # (!Addr[5])) +// \Addr[5]~21COUT1_65 = CARRY(((!\Addr[4]~17 )) # (!Addr[5])) + + .clk(\C25M~combout ), + .dataa(Addr[5]), + .datab(vcc), + .datac(\RD[5]~5 ), + .datad(vcc), + .aclr(!\nRESr~regout ), + .aload(gnd), + .sclr(gnd), + .sload(\always9~4_combout ), + .ena(vcc), + .cin(\Addr[4]~17 ), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(Addr[5]), + .cout(), + .cout0(\Addr[5]~21 ), + .cout1(\Addr[5]~21COUT1_65 )); +// synopsys translate_off +defparam \Addr[5] .cin_used = "true"; +defparam \Addr[5] .lut_mask = "5a5f"; +defparam \Addr[5] .operation_mode = "arithmetic"; +defparam \Addr[5] .output_mode = "reg_only"; +defparam \Addr[5] .register_cascade_mode = "off"; +defparam \Addr[5] .sum_lutc_input = "cin"; +defparam \Addr[5] .synch_mode = "on"; +// synopsys translate_on + +// Location: LC_X6_Y3_N6 +maxii_lcell \Addr[6] ( +// Equation(s): +// Addr[6] = DFFEAS((Addr[6] $ ((!(!\Addr[4]~17 & \Addr[5]~21 ) # (\Addr[4]~17 & \Addr[5]~21COUT1_65 )))), GLOBAL(\C25M~combout ), GLOBAL(\nRESr~regout ), , , \RD[6]~6 , , , \always9~4_combout ) +// \Addr[6]~25 = CARRY(((Addr[6] & !\Addr[5]~21 ))) +// \Addr[6]~25COUT1_66 = CARRY(((Addr[6] & !\Addr[5]~21COUT1_65 ))) + + .clk(\C25M~combout ), + .dataa(vcc), + .datab(Addr[6]), + .datac(\RD[6]~6 ), + .datad(vcc), + .aclr(!\nRESr~regout ), + .aload(gnd), + .sclr(gnd), + .sload(\always9~4_combout ), + .ena(vcc), + .cin(\Addr[4]~17 ), + .cin0(\Addr[5]~21 ), + .cin1(\Addr[5]~21COUT1_65 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(Addr[6]), + .cout(), + .cout0(\Addr[6]~25 ), + .cout1(\Addr[6]~25COUT1_66 )); +// synopsys translate_off +defparam \Addr[6] .cin0_used = "true"; +defparam \Addr[6] .cin1_used = "true"; +defparam \Addr[6] .cin_used = "true"; +defparam \Addr[6] .lut_mask = "c30c"; +defparam \Addr[6] .operation_mode = "arithmetic"; +defparam \Addr[6] .output_mode = "reg_only"; +defparam \Addr[6] .register_cascade_mode = "off"; +defparam \Addr[6] .sum_lutc_input = "cin"; +defparam \Addr[6] .synch_mode = "on"; +// synopsys translate_on + +// Location: LC_X6_Y3_N7 +maxii_lcell \Addr[7] ( +// Equation(s): +// Addr[7] = DFFEAS((Addr[7] $ (((!\Addr[4]~17 & \Addr[6]~25 ) # (\Addr[4]~17 & \Addr[6]~25COUT1_66 )))), GLOBAL(\C25M~combout ), GLOBAL(\nRESr~regout ), , , \RD[7]~7 , , , \always9~4_combout ) + + .clk(\C25M~combout ), + .dataa(vcc), + .datab(Addr[7]), + .datac(\RD[7]~7 ), + .datad(vcc), + .aclr(!\nRESr~regout ), + .aload(gnd), + .sclr(gnd), + .sload(\always9~4_combout ), + .ena(vcc), + .cin(\Addr[4]~17 ), + .cin0(\Addr[6]~25 ), + .cin1(\Addr[6]~25COUT1_66 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(Addr[7]), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Addr[7] .cin0_used = "true"; +defparam \Addr[7] .cin1_used = "true"; +defparam \Addr[7] .cin_used = "true"; +defparam \Addr[7] .lut_mask = "3c3c"; +defparam \Addr[7] .operation_mode = "normal"; +defparam \Addr[7] .output_mode = "reg_only"; +defparam \Addr[7] .register_cascade_mode = "off"; +defparam \Addr[7] .sum_lutc_input = "cin"; +defparam \Addr[7] .synch_mode = "on"; +// synopsys translate_on + +// Location: LC_X6_Y3_N8 +maxii_lcell \AddrIncM~1 ( +// Equation(s): +// \AddrIncM~1_combout = (Addr[5] & (Addr[6] & (Addr[4] & Addr[3]))) + + .clk(gnd), + .dataa(Addr[5]), + .datab(Addr[6]), + .datac(Addr[4]), + .datad(Addr[3]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\AddrIncM~1_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \AddrIncM~1 .lut_mask = "8000"; +defparam \AddrIncM~1 .operation_mode = "normal"; +defparam \AddrIncM~1 .output_mode = "comb_only"; +defparam \AddrIncM~1 .register_cascade_mode = "off"; +defparam \AddrIncM~1 .sum_lutc_input = "datac"; +defparam \AddrIncM~1 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X5_Y3_N3 +maxii_lcell \AddrIncM~0 ( +// Equation(s): +// \AddrIncM~0_combout = ((\AddrIncL~regout & (Addr[0]))) + + .clk(gnd), + .dataa(vcc), + .datab(\AddrIncL~regout ), + .datac(Addr[0]), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\AddrIncM~0_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \AddrIncM~0 .lut_mask = "c0c0"; +defparam \AddrIncM~0 .operation_mode = "normal"; +defparam \AddrIncM~0 .output_mode = "comb_only"; +defparam \AddrIncM~0 .register_cascade_mode = "off"; +defparam \AddrIncM~0 .sum_lutc_input = "datac"; +defparam \AddrIncM~0 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X5_Y3_N6 +maxii_lcell \AddrIncM~2 ( +// Equation(s): +// \AddrIncM~2_combout = (Addr[1] & (Addr[2] & (\AddrIncM~1_combout & \AddrIncM~0_combout ))) + + .clk(gnd), + .dataa(Addr[1]), + .datab(Addr[2]), + .datac(\AddrIncM~1_combout ), + .datad(\AddrIncM~0_combout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\AddrIncM~2_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \AddrIncM~2 .lut_mask = "8000"; +defparam \AddrIncM~2 .operation_mode = "normal"; +defparam \AddrIncM~2 .output_mode = "comb_only"; +defparam \AddrIncM~2 .register_cascade_mode = "off"; +defparam \AddrIncM~2 .sum_lutc_input = "datac"; +defparam \AddrIncM~2 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X5_Y2_N9 +maxii_lcell AddrIncM( +// Equation(s): +// \AddrIncM~regout = DFFEAS((Addr[7] & ((\always9~4_combout & ((!\RD[7]~7 ))) # (!\always9~4_combout & (\AddrIncM~2_combout )))), GLOBAL(\C25M~combout ), GLOBAL(\nRESr~regout ), , , , , , ) + + .clk(\C25M~combout ), + .dataa(Addr[7]), + .datab(\AddrIncM~2_combout ), + .datac(\RD[7]~7 ), + .datad(\always9~4_combout ), + .aclr(!\nRESr~regout ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\AddrIncM~regout ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam AddrIncM.lut_mask = "0a88"; +defparam AddrIncM.operation_mode = "normal"; +defparam AddrIncM.output_mode = "reg_only"; +defparam AddrIncM.register_cascade_mode = "off"; +defparam AddrIncM.sum_lutc_input = "datac"; +defparam AddrIncM.synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X5_Y2_N0 +maxii_lcell \Addr[8] ( +// Equation(s): +// Addr[8] = DFFEAS(\AddrIncM~regout $ ((Addr[8])), GLOBAL(\C25M~combout ), GLOBAL(\nRESr~regout ), , , \RD[0]~0 , , , \always9~3_combout ) +// \Addr[8]~33 = CARRY((\AddrIncM~regout & (Addr[8]))) +// \Addr[8]~33COUT1_55 = CARRY((\AddrIncM~regout & (Addr[8]))) + + .clk(\C25M~combout ), + .dataa(\AddrIncM~regout ), + .datab(Addr[8]), + .datac(\RD[0]~0 ), + .datad(vcc), + .aclr(!\nRESr~regout ), + .aload(gnd), + .sclr(gnd), + .sload(\always9~3_combout ), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(Addr[8]), + .cout(), + .cout0(\Addr[8]~33 ), + .cout1(\Addr[8]~33COUT1_55 )); +// synopsys translate_off +defparam \Addr[8] .lut_mask = "6688"; +defparam \Addr[8] .operation_mode = "arithmetic"; +defparam \Addr[8] .output_mode = "reg_only"; +defparam \Addr[8] .register_cascade_mode = "off"; +defparam \Addr[8] .sum_lutc_input = "datac"; +defparam \Addr[8] .synch_mode = "on"; +// synopsys translate_on + +// Location: LC_X5_Y2_N1 +maxii_lcell \Addr[9] ( +// Equation(s): +// Addr[9] = DFFEAS((Addr[9] $ ((\Addr[8]~33 ))), GLOBAL(\C25M~combout ), GLOBAL(\nRESr~regout ), , , \RD[1]~1 , , , \always9~3_combout ) +// \Addr[9]~37 = CARRY(((!\Addr[8]~33 ) # (!Addr[9]))) +// \Addr[9]~37COUT1_56 = CARRY(((!\Addr[8]~33COUT1_55 ) # (!Addr[9]))) + + .clk(\C25M~combout ), + .dataa(vcc), + .datab(Addr[9]), + .datac(\RD[1]~1 ), + .datad(vcc), + .aclr(!\nRESr~regout ), + .aload(gnd), + .sclr(gnd), + .sload(\always9~3_combout ), + .ena(vcc), + .cin(gnd), + .cin0(\Addr[8]~33 ), + .cin1(\Addr[8]~33COUT1_55 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(Addr[9]), + .cout(), + .cout0(\Addr[9]~37 ), + .cout1(\Addr[9]~37COUT1_56 )); +// synopsys translate_off +defparam \Addr[9] .cin0_used = "true"; +defparam \Addr[9] .cin1_used = "true"; +defparam \Addr[9] .lut_mask = "3c3f"; +defparam \Addr[9] .operation_mode = "arithmetic"; +defparam \Addr[9] .output_mode = "reg_only"; +defparam \Addr[9] .register_cascade_mode = "off"; +defparam \Addr[9] .sum_lutc_input = "cin"; +defparam \Addr[9] .synch_mode = "on"; +// synopsys translate_on + +// Location: LC_X5_Y2_N2 +maxii_lcell \Addr[10] ( +// Equation(s): +// Addr[10] = DFFEAS((Addr[10] $ ((!\Addr[9]~37 ))), GLOBAL(\C25M~combout ), GLOBAL(\nRESr~regout ), , , \RD[2]~2 , , , \always9~3_combout ) +// \Addr[10]~3 = CARRY(((Addr[10] & !\Addr[9]~37 ))) +// \Addr[10]~3COUT1_57 = CARRY(((Addr[10] & !\Addr[9]~37COUT1_56 ))) + + .clk(\C25M~combout ), + .dataa(vcc), + .datab(Addr[10]), + .datac(\RD[2]~2 ), + .datad(vcc), + .aclr(!\nRESr~regout ), + .aload(gnd), + .sclr(gnd), + .sload(\always9~3_combout ), + .ena(vcc), + .cin(gnd), + .cin0(\Addr[9]~37 ), + .cin1(\Addr[9]~37COUT1_56 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(Addr[10]), + .cout(), + .cout0(\Addr[10]~3 ), + .cout1(\Addr[10]~3COUT1_57 )); +// synopsys translate_off +defparam \Addr[10] .cin0_used = "true"; +defparam \Addr[10] .cin1_used = "true"; +defparam \Addr[10] .lut_mask = "c30c"; +defparam \Addr[10] .operation_mode = "arithmetic"; +defparam \Addr[10] .output_mode = "reg_only"; +defparam \Addr[10] .register_cascade_mode = "off"; +defparam \Addr[10] .sum_lutc_input = "cin"; +defparam \Addr[10] .synch_mode = "on"; +// synopsys translate_on + +// Location: LC_X3_Y2_N4 +maxii_lcell \RAr[10] ( +// Equation(s): +// \Mux24~2 = (\SA[1]~2_combout & (\Mux24~1_combout )) # (!\SA[1]~2_combout & ((\Mux24~1_combout & (RAr[10])) # (!\Mux24~1_combout & ((Addr[10]))))) +// RAr[10] = DFFEAS(\Mux24~2 , GLOBAL(\PHI0~combout ), VCC, , , \RA~combout [10], , , VCC) + + .clk(\PHI0~combout ), + .dataa(\SA[1]~2_combout ), + .datab(\Mux24~1_combout ), + .datac(\RA~combout [10]), + .datad(Addr[10]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Mux24~2 ), + .regout(RAr[10]), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \RAr[10] .lut_mask = "d9c8"; +defparam \RAr[10] .operation_mode = "normal"; +defparam \RAr[10] .output_mode = "reg_and_comb"; +defparam \RAr[10] .register_cascade_mode = "off"; +defparam \RAr[10] .sum_lutc_input = "qfbk"; +defparam \RAr[10] .synch_mode = "on"; +// synopsys translate_on + +// Location: PIN_8, I/O Standard: 3.3-V LVTTL, Current Strength: Default +maxii_io \RA[9]~I ( + .datain(gnd), + .oe(gnd), + .combout(\RA~combout [9]), + .padio(RA[9])); +// synopsys translate_off +defparam \RA[9]~I .operation_mode = "input"; +// synopsys translate_on + +// Location: LC_X3_Y2_N2 +maxii_lcell \RAr[9] ( +// Equation(s): +// \Mux16~2 = (((RAr[9] & !PS[0]))) +// RAr[9] = DFFEAS(\Mux16~2 , GLOBAL(\PHI0~combout ), VCC, , , \RA~combout [9], , , VCC) + + .clk(\PHI0~combout ), + .dataa(vcc), + .datab(vcc), + .datac(\RA~combout [9]), + .datad(PS[0]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Mux16~2 ), + .regout(RAr[9]), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \RAr[9] .lut_mask = "00f0"; +defparam \RAr[9] .operation_mode = "normal"; +defparam \RAr[9] .output_mode = "reg_and_comb"; +defparam \RAr[9] .register_cascade_mode = "off"; +defparam \RAr[9] .sum_lutc_input = "qfbk"; +defparam \RAr[9] .synch_mode = "on"; +// synopsys translate_on + +// Location: PIN_6, I/O Standard: 3.3-V LVTTL, Current Strength: Default +maxii_io \RA[7]~I ( + .datain(gnd), + .oe(gnd), + .combout(\RA~combout [7]), + .padio(RA[7])); +// synopsys translate_off +defparam \RA[7]~I .operation_mode = "input"; +// synopsys translate_on + +// Location: LC_X5_Y2_N3 +maxii_lcell \Addr[11] ( +// Equation(s): +// Addr[11] = DFFEAS(Addr[11] $ ((((\Addr[10]~3 )))), GLOBAL(\C25M~combout ), GLOBAL(\nRESr~regout ), , , \RD[3]~3 , , , \always9~3_combout ) +// \Addr[11]~7 = CARRY(((!\Addr[10]~3 )) # (!Addr[11])) +// \Addr[11]~7COUT1_58 = CARRY(((!\Addr[10]~3COUT1_57 )) # (!Addr[11])) + + .clk(\C25M~combout ), + .dataa(Addr[11]), + .datab(vcc), + .datac(\RD[3]~3 ), + .datad(vcc), + .aclr(!\nRESr~regout ), + .aload(gnd), + .sclr(gnd), + .sload(\always9~3_combout ), + .ena(vcc), + .cin(gnd), + .cin0(\Addr[10]~3 ), + .cin1(\Addr[10]~3COUT1_57 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(Addr[11]), + .cout(), + .cout0(\Addr[11]~7 ), + .cout1(\Addr[11]~7COUT1_58 )); +// synopsys translate_off +defparam \Addr[11] .cin0_used = "true"; +defparam \Addr[11] .cin1_used = "true"; +defparam \Addr[11] .lut_mask = "5a5f"; +defparam \Addr[11] .operation_mode = "arithmetic"; +defparam \Addr[11] .output_mode = "reg_only"; +defparam \Addr[11] .register_cascade_mode = "off"; +defparam \Addr[11] .sum_lutc_input = "cin"; +defparam \Addr[11] .synch_mode = "on"; +// synopsys translate_on + +// Location: PIN_34, I/O Standard: 3.3-V LVTTL, Current Strength: Default +maxii_io \RA[11]~I ( + .datain(gnd), + .oe(gnd), + .combout(\RA~combout [11]), + .padio(RA[11])); +// synopsys translate_off +defparam \RA[11]~I .operation_mode = "input"; +// synopsys translate_on + +// Location: LC_X3_Y2_N8 +maxii_lcell \Mux23~0 ( +// Equation(s): +// \Mux23~0_combout = ((LS[11] & ((PS[0])))) + + .clk(gnd), + .dataa(vcc), + .datab(LS[11]), + .datac(vcc), + .datad(PS[0]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Mux23~0_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Mux23~0 .lut_mask = "cc00"; +defparam \Mux23~0 .operation_mode = "normal"; +defparam \Mux23~0 .output_mode = "comb_only"; +defparam \Mux23~0 .register_cascade_mode = "off"; +defparam \Mux23~0 .sum_lutc_input = "datac"; +defparam \Mux23~0 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X4_Y2_N1 +maxii_lcell \Mux23~1 ( +// Equation(s): +// \Mux23~1_combout = (\SA[1]~3_combout & ((\SA[1]~4_combout & ((RAr[2]))) # (!\SA[1]~4_combout & (\Mux23~0_combout )))) # (!\SA[1]~3_combout & (!\SA[1]~4_combout )) + + .clk(gnd), + .dataa(\SA[1]~3_combout ), + .datab(\SA[1]~4_combout ), + .datac(\Mux23~0_combout ), + .datad(RAr[2]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Mux23~1_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Mux23~1 .lut_mask = "b931"; +defparam \Mux23~1 .operation_mode = "normal"; +defparam \Mux23~1 .output_mode = "comb_only"; +defparam \Mux23~1 .register_cascade_mode = "off"; +defparam \Mux23~1 .sum_lutc_input = "datac"; +defparam \Mux23~1 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X3_Y2_N7 +maxii_lcell \RAr[11] ( +// Equation(s): +// \Mux23~2 = (\SA[1]~2_combout & (((\Mux23~1_combout )))) # (!\SA[1]~2_combout & ((\Mux23~1_combout & ((RAr[11]))) # (!\Mux23~1_combout & (Addr[11])))) +// RAr[11] = DFFEAS(\Mux23~2 , GLOBAL(\PHI0~combout ), VCC, , , \RA~combout [11], , , VCC) + + .clk(\PHI0~combout ), + .dataa(\SA[1]~2_combout ), + .datab(Addr[11]), + .datac(\RA~combout [11]), + .datad(\Mux23~1_combout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Mux23~2 ), + .regout(RAr[11]), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \RAr[11] .lut_mask = "fa44"; +defparam \RAr[11] .operation_mode = "normal"; +defparam \RAr[11] .output_mode = "reg_and_comb"; +defparam \RAr[11] .register_cascade_mode = "off"; +defparam \RAr[11] .sum_lutc_input = "qfbk"; +defparam \RAr[11] .synch_mode = "on"; +// synopsys translate_on + +// Location: PIN_7, I/O Standard: 3.3-V LVTTL, Current Strength: Default +maxii_io \RA[8]~I ( + .datain(gnd), + .oe(gnd), + .combout(\RA~combout [8]), + .padio(RA[8])); +// synopsys translate_off +defparam \RA[8]~I .operation_mode = "input"; +// synopsys translate_on + +// Location: LC_X3_Y2_N6 +maxii_lcell \RAr[8] ( +// Equation(s): +// \Equal9~0 = (!RAr[10] & (!RAr[11] & (!RAr[8] & !RAr[9]))) +// RAr[8] = DFFEAS(\Equal9~0 , GLOBAL(\PHI0~combout ), VCC, , , \RA~combout [8], , , VCC) + + .clk(\PHI0~combout ), + .dataa(RAr[10]), + .datab(RAr[11]), + .datac(\RA~combout [8]), + .datad(RAr[9]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Equal9~0 ), + .regout(RAr[8]), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \RAr[8] .lut_mask = "0001"; +defparam \RAr[8] .operation_mode = "normal"; +defparam \RAr[8] .output_mode = "reg_and_comb"; +defparam \RAr[8] .register_cascade_mode = "off"; +defparam \RAr[8] .sum_lutc_input = "qfbk"; +defparam \RAr[8] .synch_mode = "on"; +// synopsys translate_on + +// Location: LC_X3_Y2_N0 +maxii_lcell \RAr[7] ( +// Equation(s): +// \always8~2 = (RAr[10] & (RAr[9] & (RAr[7] & RAr[8]))) +// RAr[7] = DFFEAS(\always8~2 , GLOBAL(\PHI0~combout ), VCC, , , \RA~combout [7], , , VCC) + + .clk(\PHI0~combout ), + .dataa(RAr[10]), + .datab(RAr[9]), + .datac(\RA~combout [7]), + .datad(RAr[8]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\always8~2 ), + .regout(RAr[7]), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \RAr[7] .lut_mask = "8000"; +defparam \RAr[7] .operation_mode = "normal"; +defparam \RAr[7] .output_mode = "reg_and_comb"; +defparam \RAr[7] .register_cascade_mode = "off"; +defparam \RAr[7] .sum_lutc_input = "qfbk"; +defparam \RAr[7] .synch_mode = "on"; +// synopsys translate_on + +// Location: PIN_39, I/O Standard: 3.3V Schmitt Trigger Input, Current Strength: Default +maxii_io \nIOSEL~I ( + .datain(gnd), + .oe(gnd), + .combout(\nIOSEL~combout ), + .padio(nIOSEL)); +// synopsys translate_off +defparam \nIOSEL~I .operation_mode = "input"; +// synopsys translate_on + +// Location: LC_X4_Y1_N0 +maxii_lcell REGEN( +// Equation(s): +// \REGEN~regout = DFFEAS(((\REGEN~regout ) # ((\Equal19~0_combout & !\nIOSEL~combout ))), GLOBAL(\C25M~combout ), GLOBAL(\nRESr~regout ), , , , , , ) + + .clk(\C25M~combout ), + .dataa(vcc), + .datab(\REGEN~regout ), + .datac(\Equal19~0_combout ), + .datad(\nIOSEL~combout ), + .aclr(!\nRESr~regout ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\REGEN~regout ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam REGEN.lut_mask = "ccfc"; +defparam REGEN.operation_mode = "normal"; +defparam REGEN.output_mode = "reg_only"; +defparam REGEN.register_cascade_mode = "off"; +defparam REGEN.sum_lutc_input = "datac"; +defparam REGEN.synch_mode = "off"; +// synopsys translate_on + +// Location: PIN_37, I/O Standard: 3.3-V LVTTL, Current Strength: Default +maxii_io \RA[14]~I ( + .datain(gnd), + .oe(gnd), + .combout(\RA~combout [14]), + .padio(RA[14])); +// synopsys translate_off +defparam \RA[14]~I .operation_mode = "input"; +// synopsys translate_on + +// Location: PIN_35, I/O Standard: 3.3-V LVTTL, Current Strength: Default +maxii_io \RA[12]~I ( + .datain(gnd), + .oe(gnd), + .combout(\RA~combout [12]), + .padio(RA[12])); +// synopsys translate_off +defparam \RA[12]~I .operation_mode = "input"; +// synopsys translate_on + +// Location: PIN_38, I/O Standard: 3.3-V LVTTL, Current Strength: Default +maxii_io \RA[15]~I ( + .datain(gnd), + .oe(gnd), + .combout(\RA~combout [15]), + .padio(RA[15])); +// synopsys translate_off +defparam \RA[15]~I .operation_mode = "input"; +// synopsys translate_on + +// Location: PIN_36, I/O Standard: 3.3-V LVTTL, Current Strength: Default +maxii_io \RA[13]~I ( + .datain(gnd), + .oe(gnd), + .combout(\RA~combout [13]), + .padio(RA[13])); +// synopsys translate_off +defparam \RA[13]~I .operation_mode = "input"; +// synopsys translate_on + +// Location: LC_X4_Y1_N6 +maxii_lcell CXXXr( +// Equation(s): +// \CXXXr~regout = DFFEAS((\RA~combout [14] & (!\RA~combout [12] & (\RA~combout [15] & !\RA~combout [13]))), GLOBAL(\PHI0~combout ), VCC, , , , , , ) + + .clk(\PHI0~combout ), + .dataa(\RA~combout [14]), + .datab(\RA~combout [12]), + .datac(\RA~combout [15]), + .datad(\RA~combout [13]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\CXXXr~regout ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam CXXXr.lut_mask = "0020"; +defparam CXXXr.operation_mode = "normal"; +defparam CXXXr.output_mode = "reg_only"; +defparam CXXXr.register_cascade_mode = "off"; +defparam CXXXr.sum_lutc_input = "datac"; +defparam CXXXr.synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X4_Y1_N5 +maxii_lcell \always9~0 ( +// Equation(s): +// \always9~0_combout = (RAr[7] & (\REGEN~regout & (\CXXXr~regout & \Equal9~0 ))) + + .clk(gnd), + .dataa(RAr[7]), + .datab(\REGEN~regout ), + .datac(\CXXXr~regout ), + .datad(\Equal9~0 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\always9~0_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \always9~0 .lut_mask = "8000"; +defparam \always9~0 .operation_mode = "normal"; +defparam \always9~0 .output_mode = "comb_only"; +defparam \always9~0 .register_cascade_mode = "off"; +defparam \always9~0 .sum_lutc_input = "datac"; +defparam \always9~0 .synch_mode = "off"; +// synopsys translate_on + +// Location: PIN_96, I/O Standard: 3.3V Schmitt Trigger Input, Current Strength: Default +maxii_io \SetFW[0]~I ( + .datain(gnd), + .oe(gnd), + .combout(\SetFW~combout [0]), + .padio(SetFW[0])); +// synopsys translate_off +defparam \SetFW[0]~I .operation_mode = "input"; +// synopsys translate_on + +// Location: LC_X4_Y2_N8 +maxii_lcell SetFWLoaded( +// Equation(s): +// \SetFWLoaded~regout = DFFEAS(VCC, GLOBAL(\C25M~combout ), VCC, , , , , , ) + + .clk(\C25M~combout ), + .dataa(vcc), + .datab(vcc), + .datac(vcc), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\SetFWLoaded~regout ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam SetFWLoaded.lut_mask = "ffff"; +defparam SetFWLoaded.operation_mode = "normal"; +defparam SetFWLoaded.output_mode = "reg_only"; +defparam SetFWLoaded.register_cascade_mode = "off"; +defparam SetFWLoaded.sum_lutc_input = "datac"; +defparam SetFWLoaded.synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X4_Y2_N7 +maxii_lcell \SetFWr[0] ( +// Equation(s): +// \Mux2~2 = (LS[1] & (((!LS[2])))) # (!LS[1] & (\Equal1~0_combout & (!SetFWr[0] & LS[2]))) +// SetFWr[0] = DFFEAS(\Mux2~2 , GLOBAL(\C25M~combout ), VCC, , !\SetFWLoaded~regout , \SetFW~combout [0], , , VCC) + + .clk(\C25M~combout ), + .dataa(LS[1]), + .datab(\Equal1~0_combout ), + .datac(\SetFW~combout [0]), + .datad(LS[2]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(!\SetFWLoaded~regout ), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Mux2~2 ), + .regout(SetFWr[0]), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \SetFWr[0] .lut_mask = "04aa"; +defparam \SetFWr[0] .operation_mode = "normal"; +defparam \SetFWr[0] .output_mode = "reg_and_comb"; +defparam \SetFWr[0] .register_cascade_mode = "off"; +defparam \SetFWr[0] .sum_lutc_input = "qfbk"; +defparam \SetFWr[0] .synch_mode = "on"; +// synopsys translate_on + +// Location: PIN_95, I/O Standard: 3.3V Schmitt Trigger Input, Current Strength: Default +maxii_io \SetFW[1]~I ( + .datain(gnd), + .oe(gnd), + .combout(\SetFW~combout [1]), + .padio(SetFW[1])); +// synopsys translate_off +defparam \SetFW[1]~I .operation_mode = "input"; +// synopsys translate_on + +// Location: LC_X7_Y3_N6 +maxii_lcell \always9~2 ( +// Equation(s): +// \always9~2_combout = (\always9~1_combout & (!RAr[0] & (RAr[1] & \RAMRegSpecSEL~1 ))) + + .clk(gnd), + .dataa(\always9~1_combout ), + .datab(RAr[0]), + .datac(RAr[1]), + .datad(\RAMRegSpecSEL~1 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\always9~2_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \always9~2 .lut_mask = "2000"; +defparam \always9~2 .operation_mode = "normal"; +defparam \always9~2 .output_mode = "comb_only"; +defparam \always9~2 .register_cascade_mode = "off"; +defparam \always9~2 .sum_lutc_input = "datac"; +defparam \always9~2 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X4_Y2_N9 +maxii_lcell \AddrIncH~0 ( +// Equation(s): +// \AddrIncH~0_combout = ((\AddrIncM~regout & (Addr[8]))) + + .clk(gnd), + .dataa(vcc), + .datab(\AddrIncM~regout ), + .datac(Addr[8]), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\AddrIncH~0_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \AddrIncH~0 .lut_mask = "c0c0"; +defparam \AddrIncH~0 .operation_mode = "normal"; +defparam \AddrIncH~0 .output_mode = "comb_only"; +defparam \AddrIncH~0 .register_cascade_mode = "off"; +defparam \AddrIncH~0 .sum_lutc_input = "datac"; +defparam \AddrIncH~0 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X5_Y2_N4 +maxii_lcell \Addr[12] ( +// Equation(s): +// Addr[12] = DFFEAS(Addr[12] $ ((((!\Addr[11]~7 )))), GLOBAL(\C25M~combout ), GLOBAL(\nRESr~regout ), , , \RD[4]~4 , , , \always9~3_combout ) +// \Addr[12]~11 = CARRY((Addr[12] & ((!\Addr[11]~7COUT1_58 )))) + + .clk(\C25M~combout ), + .dataa(Addr[12]), + .datab(vcc), + .datac(\RD[4]~4 ), + .datad(vcc), + .aclr(!\nRESr~regout ), + .aload(gnd), + .sclr(gnd), + .sload(\always9~3_combout ), + .ena(vcc), + .cin(gnd), + .cin0(\Addr[11]~7 ), + .cin1(\Addr[11]~7COUT1_58 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(Addr[12]), + .cout(\Addr[12]~11 ), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Addr[12] .cin0_used = "true"; +defparam \Addr[12] .cin1_used = "true"; +defparam \Addr[12] .lut_mask = "a50a"; +defparam \Addr[12] .operation_mode = "arithmetic"; +defparam \Addr[12] .output_mode = "reg_only"; +defparam \Addr[12] .register_cascade_mode = "off"; +defparam \Addr[12] .sum_lutc_input = "cin"; +defparam \Addr[12] .synch_mode = "on"; +// synopsys translate_on + +// Location: LC_X5_Y2_N5 +maxii_lcell \Addr[13] ( +// Equation(s): +// Addr[13] = DFFEAS(Addr[13] $ ((((\Addr[12]~11 )))), GLOBAL(\C25M~combout ), GLOBAL(\nRESr~regout ), , , \RD[5]~5 , , , \always9~3_combout ) +// \Addr[13]~15 = CARRY(((!\Addr[12]~11 )) # (!Addr[13])) +// \Addr[13]~15COUT1_59 = CARRY(((!\Addr[12]~11 )) # (!Addr[13])) + + .clk(\C25M~combout ), + .dataa(Addr[13]), + .datab(vcc), + .datac(\RD[5]~5 ), + .datad(vcc), + .aclr(!\nRESr~regout ), + .aload(gnd), + .sclr(gnd), + .sload(\always9~3_combout ), + .ena(vcc), + .cin(\Addr[12]~11 ), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(Addr[13]), + .cout(), + .cout0(\Addr[13]~15 ), + .cout1(\Addr[13]~15COUT1_59 )); +// synopsys translate_off +defparam \Addr[13] .cin_used = "true"; +defparam \Addr[13] .lut_mask = "5a5f"; +defparam \Addr[13] .operation_mode = "arithmetic"; +defparam \Addr[13] .output_mode = "reg_only"; +defparam \Addr[13] .register_cascade_mode = "off"; +defparam \Addr[13] .sum_lutc_input = "cin"; +defparam \Addr[13] .synch_mode = "on"; +// synopsys translate_on + +// Location: LC_X5_Y2_N6 +maxii_lcell \Addr[14] ( +// Equation(s): +// Addr[14] = DFFEAS(Addr[14] $ ((((!(!\Addr[12]~11 & \Addr[13]~15 ) # (\Addr[12]~11 & \Addr[13]~15COUT1_59 ))))), GLOBAL(\C25M~combout ), GLOBAL(\nRESr~regout ), , , \RD[6]~6 , , , \always9~3_combout ) +// \Addr[14]~19 = CARRY((Addr[14] & ((!\Addr[13]~15 )))) +// \Addr[14]~19COUT1_60 = CARRY((Addr[14] & ((!\Addr[13]~15COUT1_59 )))) + + .clk(\C25M~combout ), + .dataa(Addr[14]), + .datab(vcc), + .datac(\RD[6]~6 ), + .datad(vcc), + .aclr(!\nRESr~regout ), + .aload(gnd), + .sclr(gnd), + .sload(\always9~3_combout ), + .ena(vcc), + .cin(\Addr[12]~11 ), + .cin0(\Addr[13]~15 ), + .cin1(\Addr[13]~15COUT1_59 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(Addr[14]), + .cout(), + .cout0(\Addr[14]~19 ), + .cout1(\Addr[14]~19COUT1_60 )); +// synopsys translate_off +defparam \Addr[14] .cin0_used = "true"; +defparam \Addr[14] .cin1_used = "true"; +defparam \Addr[14] .cin_used = "true"; +defparam \Addr[14] .lut_mask = "a50a"; +defparam \Addr[14] .operation_mode = "arithmetic"; +defparam \Addr[14] .output_mode = "reg_only"; +defparam \Addr[14] .register_cascade_mode = "off"; +defparam \Addr[14] .sum_lutc_input = "cin"; +defparam \Addr[14] .synch_mode = "on"; +// synopsys translate_on + +// Location: LC_X5_Y2_N8 +maxii_lcell \AddrIncH~1 ( +// Equation(s): +// \AddrIncH~1_combout = (Addr[13] & (Addr[12] & (Addr[14] & Addr[11]))) + + .clk(gnd), + .dataa(Addr[13]), + .datab(Addr[12]), + .datac(Addr[14]), + .datad(Addr[11]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\AddrIncH~1_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \AddrIncH~1 .lut_mask = "8000"; +defparam \AddrIncH~1 .operation_mode = "normal"; +defparam \AddrIncH~1 .output_mode = "comb_only"; +defparam \AddrIncH~1 .register_cascade_mode = "off"; +defparam \AddrIncH~1 .sum_lutc_input = "datac"; +defparam \AddrIncH~1 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X4_Y2_N4 +maxii_lcell \AddrIncH~2 ( +// Equation(s): +// \AddrIncH~2_combout = (Addr[9] & (\AddrIncH~0_combout & (Addr[10] & \AddrIncH~1_combout ))) + + .clk(gnd), + .dataa(Addr[9]), + .datab(\AddrIncH~0_combout ), + .datac(Addr[10]), + .datad(\AddrIncH~1_combout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\AddrIncH~2_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \AddrIncH~2 .lut_mask = "8000"; +defparam \AddrIncH~2 .operation_mode = "normal"; +defparam \AddrIncH~2 .output_mode = "comb_only"; +defparam \AddrIncH~2 .register_cascade_mode = "off"; +defparam \AddrIncH~2 .sum_lutc_input = "datac"; +defparam \AddrIncH~2 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X5_Y2_N7 +maxii_lcell \Addr[15] ( +// Equation(s): +// Addr[15] = DFFEAS((Addr[15] $ (((!\Addr[12]~11 & \Addr[14]~19 ) # (\Addr[12]~11 & \Addr[14]~19COUT1_60 )))), GLOBAL(\C25M~combout ), GLOBAL(\nRESr~regout ), , , \RD[7]~7 , , , \always9~3_combout ) + + .clk(\C25M~combout ), + .dataa(vcc), + .datab(Addr[15]), + .datac(\RD[7]~7 ), + .datad(vcc), + .aclr(!\nRESr~regout ), + .aload(gnd), + .sclr(gnd), + .sload(\always9~3_combout ), + .ena(vcc), + .cin(\Addr[12]~11 ), + .cin0(\Addr[14]~19 ), + .cin1(\Addr[14]~19COUT1_60 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(Addr[15]), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Addr[15] .cin0_used = "true"; +defparam \Addr[15] .cin1_used = "true"; +defparam \Addr[15] .cin_used = "true"; +defparam \Addr[15] .lut_mask = "3c3c"; +defparam \Addr[15] .operation_mode = "normal"; +defparam \Addr[15] .output_mode = "reg_only"; +defparam \Addr[15] .register_cascade_mode = "off"; +defparam \Addr[15] .sum_lutc_input = "cin"; +defparam \Addr[15] .synch_mode = "on"; +// synopsys translate_on + +// Location: LC_X6_Y2_N2 +maxii_lcell AddrIncH( +// Equation(s): +// \AddrIncH~regout = DFFEAS((Addr[15] & ((\always9~3_combout & ((!\RD[7]~7 ))) # (!\always9~3_combout & (\AddrIncH~2_combout )))), GLOBAL(\C25M~combout ), GLOBAL(\nRESr~regout ), , , , , , ) + + .clk(\C25M~combout ), + .dataa(\AddrIncH~2_combout ), + .datab(\always9~3_combout ), + .datac(\RD[7]~7 ), + .datad(Addr[15]), + .aclr(!\nRESr~regout ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\AddrIncH~regout ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam AddrIncH.lut_mask = "2e00"; +defparam AddrIncH.operation_mode = "normal"; +defparam AddrIncH.output_mode = "reg_only"; +defparam AddrIncH.register_cascade_mode = "off"; +defparam AddrIncH.sum_lutc_input = "datac"; +defparam AddrIncH.synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X7_Y4_N0 +maxii_lcell \Addr[16] ( +// Equation(s): +// Addr[16] = DFFEAS(\AddrIncH~regout $ ((Addr[16])), GLOBAL(\C25M~combout ), GLOBAL(\nRESr~regout ), , , \RD[0]~0 , , , \always9~2_combout ) +// \Addr[16]~27 = CARRY((\AddrIncH~regout & (Addr[16]))) +// \Addr[16]~27COUT1_49 = CARRY((\AddrIncH~regout & (Addr[16]))) + + .clk(\C25M~combout ), + .dataa(\AddrIncH~regout ), + .datab(Addr[16]), + .datac(\RD[0]~0 ), + .datad(vcc), + .aclr(!\nRESr~regout ), + .aload(gnd), + .sclr(gnd), + .sload(\always9~2_combout ), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(Addr[16]), + .cout(), + .cout0(\Addr[16]~27 ), + .cout1(\Addr[16]~27COUT1_49 )); +// synopsys translate_off +defparam \Addr[16] .lut_mask = "6688"; +defparam \Addr[16] .operation_mode = "arithmetic"; +defparam \Addr[16] .output_mode = "reg_only"; +defparam \Addr[16] .register_cascade_mode = "off"; +defparam \Addr[16] .sum_lutc_input = "datac"; +defparam \Addr[16] .synch_mode = "on"; +// synopsys translate_on + +// Location: LC_X7_Y4_N1 +maxii_lcell \Addr[17] ( +// Equation(s): +// Addr[17] = DFFEAS((Addr[17] $ ((\Addr[16]~27 ))), GLOBAL(\C25M~combout ), GLOBAL(\nRESr~regout ), , , \RD[1]~1 , , , \always9~2_combout ) +// \Addr[17]~31 = CARRY(((!\Addr[16]~27 ) # (!Addr[17]))) +// \Addr[17]~31COUT1_50 = CARRY(((!\Addr[16]~27COUT1_49 ) # (!Addr[17]))) + + .clk(\C25M~combout ), + .dataa(vcc), + .datab(Addr[17]), + .datac(\RD[1]~1 ), + .datad(vcc), + .aclr(!\nRESr~regout ), + .aload(gnd), + .sclr(gnd), + .sload(\always9~2_combout ), + .ena(vcc), + .cin(gnd), + .cin0(\Addr[16]~27 ), + .cin1(\Addr[16]~27COUT1_49 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(Addr[17]), + .cout(), + .cout0(\Addr[17]~31 ), + .cout1(\Addr[17]~31COUT1_50 )); +// synopsys translate_off +defparam \Addr[17] .cin0_used = "true"; +defparam \Addr[17] .cin1_used = "true"; +defparam \Addr[17] .lut_mask = "3c3f"; +defparam \Addr[17] .operation_mode = "arithmetic"; +defparam \Addr[17] .output_mode = "reg_only"; +defparam \Addr[17] .register_cascade_mode = "off"; +defparam \Addr[17] .sum_lutc_input = "cin"; +defparam \Addr[17] .synch_mode = "on"; +// synopsys translate_on + +// Location: LC_X7_Y4_N2 +maxii_lcell \Addr[18] ( +// Equation(s): +// Addr[18] = DFFEAS((Addr[18] $ ((!\Addr[17]~31 ))), GLOBAL(\C25M~combout ), GLOBAL(\nRESr~regout ), , , \RD[2]~2 , , , \always9~2_combout ) +// \Addr[18]~35 = CARRY(((Addr[18] & !\Addr[17]~31 ))) +// \Addr[18]~35COUT1_51 = CARRY(((Addr[18] & !\Addr[17]~31COUT1_50 ))) + + .clk(\C25M~combout ), + .dataa(vcc), + .datab(Addr[18]), + .datac(\RD[2]~2 ), + .datad(vcc), + .aclr(!\nRESr~regout ), + .aload(gnd), + .sclr(gnd), + .sload(\always9~2_combout ), + .ena(vcc), + .cin(gnd), + .cin0(\Addr[17]~31 ), + .cin1(\Addr[17]~31COUT1_50 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(Addr[18]), + .cout(), + .cout0(\Addr[18]~35 ), + .cout1(\Addr[18]~35COUT1_51 )); +// synopsys translate_off +defparam \Addr[18] .cin0_used = "true"; +defparam \Addr[18] .cin1_used = "true"; +defparam \Addr[18] .lut_mask = "c30c"; +defparam \Addr[18] .operation_mode = "arithmetic"; +defparam \Addr[18] .output_mode = "reg_only"; +defparam \Addr[18] .register_cascade_mode = "off"; +defparam \Addr[18] .sum_lutc_input = "cin"; +defparam \Addr[18] .synch_mode = "on"; +// synopsys translate_on + +// Location: LC_X7_Y4_N3 +maxii_lcell \Addr[19] ( +// Equation(s): +// Addr[19] = DFFEAS(Addr[19] $ ((((\Addr[18]~35 )))), GLOBAL(\C25M~combout ), GLOBAL(\nRESr~regout ), , , \RD[3]~3 , , , \always9~2_combout ) +// \Addr[19]~39 = CARRY(((!\Addr[18]~35 )) # (!Addr[19])) +// \Addr[19]~39COUT1_52 = CARRY(((!\Addr[18]~35COUT1_51 )) # (!Addr[19])) + + .clk(\C25M~combout ), + .dataa(Addr[19]), + .datab(vcc), + .datac(\RD[3]~3 ), + .datad(vcc), + .aclr(!\nRESr~regout ), + .aload(gnd), + .sclr(gnd), + .sload(\always9~2_combout ), + .ena(vcc), + .cin(gnd), + .cin0(\Addr[18]~35 ), + .cin1(\Addr[18]~35COUT1_51 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(Addr[19]), + .cout(), + .cout0(\Addr[19]~39 ), + .cout1(\Addr[19]~39COUT1_52 )); +// synopsys translate_off +defparam \Addr[19] .cin0_used = "true"; +defparam \Addr[19] .cin1_used = "true"; +defparam \Addr[19] .lut_mask = "5a5f"; +defparam \Addr[19] .operation_mode = "arithmetic"; +defparam \Addr[19] .output_mode = "reg_only"; +defparam \Addr[19] .register_cascade_mode = "off"; +defparam \Addr[19] .sum_lutc_input = "cin"; +defparam \Addr[19] .synch_mode = "on"; +// synopsys translate_on + +// Location: LC_X7_Y4_N4 +maxii_lcell \Addr[20] ( +// Equation(s): +// Addr[20] = DFFEAS(Addr[20] $ ((((!\Addr[19]~39 )))), GLOBAL(\C25M~combout ), GLOBAL(\nRESr~regout ), , , \RD[4]~4 , , , \always9~2_combout ) +// \Addr[20]~41 = CARRY((Addr[20] & ((!\Addr[19]~39COUT1_52 )))) + + .clk(\C25M~combout ), + .dataa(Addr[20]), + .datab(vcc), + .datac(\RD[4]~4 ), + .datad(vcc), + .aclr(!\nRESr~regout ), + .aload(gnd), + .sclr(gnd), + .sload(\always9~2_combout ), + .ena(vcc), + .cin(gnd), + .cin0(\Addr[19]~39 ), + .cin1(\Addr[19]~39COUT1_52 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(Addr[20]), + .cout(\Addr[20]~41 ), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Addr[20] .cin0_used = "true"; +defparam \Addr[20] .cin1_used = "true"; +defparam \Addr[20] .lut_mask = "a50a"; +defparam \Addr[20] .operation_mode = "arithmetic"; +defparam \Addr[20] .output_mode = "reg_only"; +defparam \Addr[20] .register_cascade_mode = "off"; +defparam \Addr[20] .sum_lutc_input = "cin"; +defparam \Addr[20] .synch_mode = "on"; +// synopsys translate_on + +// Location: LC_X7_Y4_N5 +maxii_lcell \Addr[21] ( +// Equation(s): +// Addr[21] = DFFEAS(Addr[21] $ ((((\Addr[20]~41 )))), GLOBAL(\C25M~combout ), GLOBAL(\nRESr~regout ), , , \RD[5]~5 , , , \always9~2_combout ) +// \Addr[21]~43 = CARRY(((!\Addr[20]~41 )) # (!Addr[21])) +// \Addr[21]~43COUT1_53 = CARRY(((!\Addr[20]~41 )) # (!Addr[21])) + + .clk(\C25M~combout ), + .dataa(Addr[21]), + .datab(vcc), + .datac(\RD[5]~5 ), + .datad(vcc), + .aclr(!\nRESr~regout ), + .aload(gnd), + .sclr(gnd), + .sload(\always9~2_combout ), + .ena(vcc), + .cin(\Addr[20]~41 ), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(Addr[21]), + .cout(), + .cout0(\Addr[21]~43 ), + .cout1(\Addr[21]~43COUT1_53 )); +// synopsys translate_off +defparam \Addr[21] .cin_used = "true"; +defparam \Addr[21] .lut_mask = "5a5f"; +defparam \Addr[21] .operation_mode = "arithmetic"; +defparam \Addr[21] .output_mode = "reg_only"; +defparam \Addr[21] .register_cascade_mode = "off"; +defparam \Addr[21] .sum_lutc_input = "cin"; +defparam \Addr[21] .synch_mode = "on"; +// synopsys translate_on + +// Location: LC_X7_Y4_N6 +maxii_lcell \Addr[22] ( +// Equation(s): +// Addr[22] = DFFEAS(Addr[22] $ ((((!(!\Addr[20]~41 & \Addr[21]~43 ) # (\Addr[20]~41 & \Addr[21]~43COUT1_53 ))))), GLOBAL(\C25M~combout ), GLOBAL(\nRESr~regout ), , , \RD[6]~6 , , , \always9~2_combout ) +// \Addr[22]~45 = CARRY((Addr[22] & ((!\Addr[21]~43 )))) +// \Addr[22]~45COUT1_54 = CARRY((Addr[22] & ((!\Addr[21]~43COUT1_53 )))) + + .clk(\C25M~combout ), + .dataa(Addr[22]), + .datab(vcc), + .datac(\RD[6]~6 ), + .datad(vcc), + .aclr(!\nRESr~regout ), + .aload(gnd), + .sclr(gnd), + .sload(\always9~2_combout ), + .ena(vcc), + .cin(\Addr[20]~41 ), + .cin0(\Addr[21]~43 ), + .cin1(\Addr[21]~43COUT1_53 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(Addr[22]), + .cout(), + .cout0(\Addr[22]~45 ), + .cout1(\Addr[22]~45COUT1_54 )); +// synopsys translate_off +defparam \Addr[22] .cin0_used = "true"; +defparam \Addr[22] .cin1_used = "true"; +defparam \Addr[22] .cin_used = "true"; +defparam \Addr[22] .lut_mask = "a50a"; +defparam \Addr[22] .operation_mode = "arithmetic"; +defparam \Addr[22] .output_mode = "reg_only"; +defparam \Addr[22] .register_cascade_mode = "off"; +defparam \Addr[22] .sum_lutc_input = "cin"; +defparam \Addr[22] .synch_mode = "on"; +// synopsys translate_on + +// Location: LC_X7_Y4_N7 +maxii_lcell \Addr[23] ( +// Equation(s): +// Addr[23] = DFFEAS((Addr[23] $ (((!\Addr[20]~41 & \Addr[22]~45 ) # (\Addr[20]~41 & \Addr[22]~45COUT1_54 )))), GLOBAL(\C25M~combout ), GLOBAL(\nRESr~regout ), , , \RD[7]~7 , , , \always9~2_combout ) + + .clk(\C25M~combout ), + .dataa(vcc), + .datab(Addr[23]), + .datac(\RD[7]~7 ), + .datad(vcc), + .aclr(!\nRESr~regout ), + .aload(gnd), + .sclr(gnd), + .sload(\always9~2_combout ), + .ena(vcc), + .cin(\Addr[20]~41 ), + .cin0(\Addr[22]~45 ), + .cin1(\Addr[22]~45COUT1_54 ), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(Addr[23]), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Addr[23] .cin0_used = "true"; +defparam \Addr[23] .cin1_used = "true"; +defparam \Addr[23] .cin_used = "true"; +defparam \Addr[23] .lut_mask = "3c3c"; +defparam \Addr[23] .operation_mode = "normal"; +defparam \Addr[23] .output_mode = "reg_only"; +defparam \Addr[23] .register_cascade_mode = "off"; +defparam \Addr[23] .sum_lutc_input = "cin"; +defparam \Addr[23] .synch_mode = "on"; +// synopsys translate_on + +// Location: LC_X4_Y2_N6 +maxii_lcell \SetFWr[1] ( +// Equation(s): +// \RAMSpecSEL~0 = (((SetFWr[1]) # (!Addr[23])) # (!SetFWr[0])) +// SetFWr[1] = DFFEAS(\RAMSpecSEL~0 , GLOBAL(\C25M~combout ), VCC, , !\SetFWLoaded~regout , \SetFW~combout [1], , , VCC) + + .clk(\C25M~combout ), + .dataa(vcc), + .datab(SetFWr[0]), + .datac(\SetFW~combout [1]), + .datad(Addr[23]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(!\SetFWLoaded~regout ), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\RAMSpecSEL~0 ), + .regout(SetFWr[1]), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \SetFWr[1] .lut_mask = "f3ff"; +defparam \SetFWr[1] .operation_mode = "normal"; +defparam \SetFWr[1] .output_mode = "reg_and_comb"; +defparam \SetFWr[1] .register_cascade_mode = "off"; +defparam \SetFWr[1] .sum_lutc_input = "qfbk"; +defparam \SetFWr[1] .synch_mode = "on"; +// synopsys translate_on + +// Location: LC_X4_Y3_N7 +maxii_lcell \RAMSpecSEL~1 ( +// Equation(s): +// \RAMSpecSEL~1_combout = (\RAMRegSpecSEL~0 & (\always9~0_combout & (\RAMSpecSEL~0 & \RAMRegSpecSEL~1 ))) + + .clk(gnd), + .dataa(\RAMRegSpecSEL~0 ), + .datab(\always9~0_combout ), + .datac(\RAMSpecSEL~0 ), + .datad(\RAMRegSpecSEL~1 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\RAMSpecSEL~1_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \RAMSpecSEL~1 .lut_mask = "8000"; +defparam \RAMSpecSEL~1 .operation_mode = "normal"; +defparam \RAMSpecSEL~1 .output_mode = "comb_only"; +defparam \RAMSpecSEL~1 .register_cascade_mode = "off"; +defparam \RAMSpecSEL~1 .sum_lutc_input = "datac"; +defparam \RAMSpecSEL~1 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X4_Y2_N0 +maxii_lcell \SA[1]~4 ( +// Equation(s): +// \SA[1]~4_combout = (PS[1]) # ((PS[0] & (!\IS.110~regout & \RAMSpecSEL~1_combout ))) + + .clk(gnd), + .dataa(PS[0]), + .datab(PS[1]), + .datac(\IS.110~regout ), + .datad(\RAMSpecSEL~1_combout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\SA[1]~4_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \SA[1]~4 .lut_mask = "cecc"; +defparam \SA[1]~4 .operation_mode = "normal"; +defparam \SA[1]~4 .output_mode = "comb_only"; +defparam \SA[1]~4 .register_cascade_mode = "off"; +defparam \SA[1]~4 .sum_lutc_input = "datac"; +defparam \SA[1]~4 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X4_Y3_N9 +maxii_lcell \RAr[3] ( +// Equation(s): +// \Mux22~1 = (\SA[1]~3_combout & ((\SA[1]~4_combout & ((RAr[3]))) # (!\SA[1]~4_combout & (\Mux22~0_combout )))) # (!\SA[1]~3_combout & (((!\SA[1]~4_combout )))) +// RAr[3] = DFFEAS(\Mux22~1 , GLOBAL(\PHI0~combout ), VCC, , , \RA~combout [3], , , VCC) + + .clk(\PHI0~combout ), + .dataa(\SA[1]~3_combout ), + .datab(\Mux22~0_combout ), + .datac(\RA~combout [3]), + .datad(\SA[1]~4_combout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Mux22~1 ), + .regout(RAr[3]), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \RAr[3] .lut_mask = "a0dd"; +defparam \RAr[3] .operation_mode = "normal"; +defparam \RAr[3] .output_mode = "reg_and_comb"; +defparam \RAr[3] .register_cascade_mode = "off"; +defparam \RAr[3] .sum_lutc_input = "qfbk"; +defparam \RAr[3] .synch_mode = "on"; +// synopsys translate_on + +// Location: PIN_100, I/O Standard: 3.3-V LVTTL, Current Strength: Default +maxii_io \RA[0]~I ( + .datain(gnd), + .oe(gnd), + .combout(\RA~combout [0]), + .padio(RA[0])); +// synopsys translate_off +defparam \RA[0]~I .operation_mode = "input"; +// synopsys translate_on + +// Location: LC_X4_Y3_N5 +maxii_lcell \RAr[0] ( +// Equation(s): +// \always8~0 = (RAr[1] & (RAr[2] & (RAr[0] & RAr[3]))) +// RAr[0] = DFFEAS(\always8~0 , GLOBAL(\PHI0~combout ), VCC, , , \RA~combout [0], , , VCC) + + .clk(\PHI0~combout ), + .dataa(RAr[1]), + .datab(RAr[2]), + .datac(\RA~combout [0]), + .datad(RAr[3]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\always8~0 ), + .regout(RAr[0]), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \RAr[0] .lut_mask = "8000"; +defparam \RAr[0] .operation_mode = "normal"; +defparam \RAr[0] .output_mode = "reg_and_comb"; +defparam \RAr[0] .register_cascade_mode = "off"; +defparam \RAr[0] .sum_lutc_input = "qfbk"; +defparam \RAr[0] .synch_mode = "on"; +// synopsys translate_on + +// Location: PIN_42, I/O Standard: 3.3V Schmitt Trigger Input, Current Strength: Default +maxii_io \nIOSTRB~I ( + .datain(gnd), + .oe(gnd), + .combout(\nIOSTRB~combout ), + .padio(nIOSTRB)); +// synopsys translate_off +defparam \nIOSTRB~I .operation_mode = "input"; +// synopsys translate_on + +// Location: PIN_3, I/O Standard: 3.3-V LVTTL, Current Strength: Default +maxii_io \RA[6]~I ( + .datain(gnd), + .oe(gnd), + .combout(\RA~combout [6]), + .padio(RA[6])); +// synopsys translate_off +defparam \RA[6]~I .operation_mode = "input"; +// synopsys translate_on + +// Location: LC_X3_Y4_N4 +maxii_lcell \RAr[6] ( +// Equation(s): +// \Mux19~2 = (((RAr[6]) # (PS[0]))) +// RAr[6] = DFFEAS(\Mux19~2 , GLOBAL(\PHI0~combout ), VCC, , , \RA~combout [6], , , VCC) + + .clk(\PHI0~combout ), + .dataa(vcc), + .datab(vcc), + .datac(\RA~combout [6]), + .datad(PS[0]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Mux19~2 ), + .regout(RAr[6]), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \RAr[6] .lut_mask = "fff0"; +defparam \RAr[6] .operation_mode = "normal"; +defparam \RAr[6] .output_mode = "reg_and_comb"; +defparam \RAr[6] .register_cascade_mode = "off"; +defparam \RAr[6] .sum_lutc_input = "qfbk"; +defparam \RAr[6] .synch_mode = "on"; +// synopsys translate_on + +// Location: PIN_1, I/O Standard: 3.3-V LVTTL, Current Strength: Default +maxii_io \RA[4]~I ( + .datain(gnd), + .oe(gnd), + .combout(\RA~combout [4]), + .padio(RA[4])); +// synopsys translate_off +defparam \RA[4]~I .operation_mode = "input"; +// synopsys translate_on + +// Location: LC_X3_Y4_N3 +maxii_lcell \RAr[4] ( +// Equation(s): +// \Mux21~2 = (((RAr[4] & !PS[0]))) +// RAr[4] = DFFEAS(\Mux21~2 , GLOBAL(\PHI0~combout ), VCC, , , \RA~combout [4], , , VCC) + + .clk(\PHI0~combout ), + .dataa(vcc), + .datab(vcc), + .datac(\RA~combout [4]), + .datad(PS[0]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Mux21~2 ), + .regout(RAr[4]), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \RAr[4] .lut_mask = "00f0"; +defparam \RAr[4] .operation_mode = "normal"; +defparam \RAr[4] .output_mode = "reg_and_comb"; +defparam \RAr[4] .register_cascade_mode = "off"; +defparam \RAr[4] .sum_lutc_input = "qfbk"; +defparam \RAr[4] .synch_mode = "on"; +// synopsys translate_on + +// Location: LC_X3_Y4_N2 +maxii_lcell nIOSTRBr( +// Equation(s): +// \always8~1 = (((!nIOSTRBr & RAr[4]))) + + .clk(\C25M~combout ), + .dataa(vcc), + .datab(vcc), + .datac(\nIOSTRB~combout ), + .datad(RAr[4]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\always8~1 ), + .regout(\nIOSTRBr~regout ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam nIOSTRBr.lut_mask = "0f00"; +defparam nIOSTRBr.operation_mode = "normal"; +defparam nIOSTRBr.output_mode = "comb_only"; +defparam nIOSTRBr.register_cascade_mode = "off"; +defparam nIOSTRBr.sum_lutc_input = "qfbk"; +defparam nIOSTRBr.synch_mode = "on"; +// synopsys translate_on + +// Location: PIN_2, I/O Standard: 3.3-V LVTTL, Current Strength: Default +maxii_io \RA[5]~I ( + .datain(gnd), + .oe(gnd), + .combout(\RA~combout [5]), + .padio(RA[5])); +// synopsys translate_off +defparam \RA[5]~I .operation_mode = "input"; +// synopsys translate_on + +// Location: LC_X3_Y4_N7 +maxii_lcell \RAr[5] ( +// Equation(s): +// \always8~3 = (RAr[6] & (\always8~1 & (RAr[5] & \always8~2 ))) +// RAr[5] = DFFEAS(\always8~3 , GLOBAL(\PHI0~combout ), VCC, , , \RA~combout [5], , , VCC) + + .clk(\PHI0~combout ), + .dataa(RAr[6]), + .datab(\always8~1 ), + .datac(\RA~combout [5]), + .datad(\always8~2 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\always8~3 ), + .regout(RAr[5]), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \RAr[5] .lut_mask = "8000"; +defparam \RAr[5] .operation_mode = "normal"; +defparam \RAr[5] .output_mode = "reg_and_comb"; +defparam \RAr[5] .register_cascade_mode = "off"; +defparam \RAr[5] .sum_lutc_input = "qfbk"; +defparam \RAr[5] .synch_mode = "on"; +// synopsys translate_on + +// Location: LC_X4_Y1_N7 +maxii_lcell \always8~4 ( +// Equation(s): +// \always8~4_combout = (\always8~0 & (\Equal19~0_combout & (!\nIOSTRB~combout & \always8~3 ))) + + .clk(gnd), + .dataa(\always8~0 ), + .datab(\Equal19~0_combout ), + .datac(\nIOSTRB~combout ), + .datad(\always8~3 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\always8~4_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \always8~4 .lut_mask = "0800"; +defparam \always8~4 .operation_mode = "normal"; +defparam \always8~4 .output_mode = "comb_only"; +defparam \always8~4 .register_cascade_mode = "off"; +defparam \always8~4 .sum_lutc_input = "datac"; +defparam \always8~4 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X4_Y1_N4 +maxii_lcell IOROMEN( +// Equation(s): +// \IOROMEN~regout = DFFEAS((!\always8~4_combout & ((\IOROMEN~regout ) # ((\Equal19~0_combout & !\nIOSEL~combout )))), GLOBAL(\C25M~combout ), VCC, , , , , !\nRESr~regout , ) + + .clk(\C25M~combout ), + .dataa(\IOROMEN~regout ), + .datab(\always8~4_combout ), + .datac(\Equal19~0_combout ), + .datad(\nIOSEL~combout ), + .aclr(gnd), + .aload(gnd), + .sclr(!\nRESr~regout ), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\IOROMEN~regout ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam IOROMEN.lut_mask = "2232"; +defparam IOROMEN.operation_mode = "normal"; +defparam IOROMEN.output_mode = "reg_only"; +defparam IOROMEN.register_cascade_mode = "off"; +defparam IOROMEN.sum_lutc_input = "datac"; +defparam IOROMEN.synch_mode = "on"; +// synopsys translate_on + +// Location: LC_X4_Y3_N2 +maxii_lcell \Equal16~0 ( +// Equation(s): +// \Equal16~0_combout = (\RA~combout [2] & (\RA~combout [3] & (\RA~combout [1] & \RA~combout [0]))) + + .clk(gnd), + .dataa(\RA~combout [2]), + .datab(\RA~combout [3]), + .datac(\RA~combout [1]), + .datad(\RA~combout [0]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Equal16~0_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Equal16~0 .lut_mask = "8000"; +defparam \Equal16~0 .operation_mode = "normal"; +defparam \Equal16~0 .output_mode = "comb_only"; +defparam \Equal16~0 .register_cascade_mode = "off"; +defparam \Equal16~0 .sum_lutc_input = "datac"; +defparam \Equal16~0 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X3_Y4_N1 +maxii_lcell \Equal16~1 ( +// Equation(s): +// \Equal16~1_combout = (\RA~combout [4] & (\RA~combout [7] & (\RA~combout [6] & \RA~combout [5]))) + + .clk(gnd), + .dataa(\RA~combout [4]), + .datab(\RA~combout [7]), + .datac(\RA~combout [6]), + .datad(\RA~combout [5]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Equal16~1_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Equal16~1 .lut_mask = "8000"; +defparam \Equal16~1 .operation_mode = "normal"; +defparam \Equal16~1 .output_mode = "comb_only"; +defparam \Equal16~1 .register_cascade_mode = "off"; +defparam \Equal16~1 .sum_lutc_input = "datac"; +defparam \Equal16~1 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X3_Y2_N1 +maxii_lcell \Equal16~2 ( +// Equation(s): +// \Equal16~2_combout = (\RA~combout [9] & (\RA~combout [8] & (\RA~combout [10] & \Equal16~1_combout ))) + + .clk(gnd), + .dataa(\RA~combout [9]), + .datab(\RA~combout [8]), + .datac(\RA~combout [10]), + .datad(\Equal16~1_combout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Equal16~2_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Equal16~2 .lut_mask = "8000"; +defparam \Equal16~2 .operation_mode = "normal"; +defparam \Equal16~2 .output_mode = "comb_only"; +defparam \Equal16~2 .register_cascade_mode = "off"; +defparam \Equal16~2 .sum_lutc_input = "datac"; +defparam \Equal16~2 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X4_Y1_N3 +maxii_lcell \comb~1 ( +// Equation(s): +// \comb~1_combout = (\IOROMEN~regout & (!\nIOSTRB~combout & ((!\Equal16~2_combout ) # (!\Equal16~0_combout )))) + + .clk(gnd), + .dataa(\IOROMEN~regout ), + .datab(\Equal16~0_combout ), + .datac(\nIOSTRB~combout ), + .datad(\Equal16~2_combout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\comb~1_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \comb~1 .lut_mask = "020a"; +defparam \comb~1 .operation_mode = "normal"; +defparam \comb~1 .output_mode = "comb_only"; +defparam \comb~1 .register_cascade_mode = "off"; +defparam \comb~1 .sum_lutc_input = "datac"; +defparam \comb~1 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X4_Y1_N8 +maxii_lcell \comb~2 ( +// Equation(s): +// \comb~2_combout = (\comb~0 & ((\comb~1_combout ) # ((!\nDEVSEL~combout ) # (!\nIOSEL~combout )))) + + .clk(gnd), + .dataa(\comb~1_combout ), + .datab(\nIOSEL~combout ), + .datac(\nDEVSEL~combout ), + .datad(\comb~0 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\comb~2_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \comb~2 .lut_mask = "bf00"; +defparam \comb~2 .operation_mode = "normal"; +defparam \comb~2 .output_mode = "comb_only"; +defparam \comb~2 .register_cascade_mode = "off"; +defparam \comb~2 .sum_lutc_input = "datac"; +defparam \comb~2 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X7_Y2_N1 +maxii_lcell \Mux14~2 ( +// Equation(s): +// \Mux14~2_combout = (((PS[1]) # (PS[0]))) + + .clk(gnd), + .dataa(vcc), + .datab(vcc), + .datac(PS[1]), + .datad(PS[0]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Mux14~2_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Mux14~2 .lut_mask = "fff0"; +defparam \Mux14~2 .operation_mode = "normal"; +defparam \Mux14~2 .output_mode = "comb_only"; +defparam \Mux14~2 .register_cascade_mode = "off"; +defparam \Mux14~2 .sum_lutc_input = "datac"; +defparam \Mux14~2 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X7_Y2_N7 +maxii_lcell \Mux14~3 ( +// Equation(s): +// \Mux14~3_combout = (Addr[23] & (!SetFWr[1] & (!\IS.110~regout & !\Mux14~2_combout ))) + + .clk(gnd), + .dataa(Addr[23]), + .datab(SetFWr[1]), + .datac(\IS.110~regout ), + .datad(\Mux14~2_combout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Mux14~3_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Mux14~3 .lut_mask = "0002"; +defparam \Mux14~3 .operation_mode = "normal"; +defparam \Mux14~3 .output_mode = "comb_only"; +defparam \Mux14~3 .register_cascade_mode = "off"; +defparam \Mux14~3 .sum_lutc_input = "datac"; +defparam \Mux14~3 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X7_Y2_N8 +maxii_lcell \Mux14~0 ( +// Equation(s): +// \Mux14~0_combout = (Addr[23] & (!SetFWr[1] & (PS[1] $ (PS[0])))) + + .clk(gnd), + .dataa(Addr[23]), + .datab(SetFWr[1]), + .datac(PS[1]), + .datad(PS[0]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Mux14~0_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Mux14~0 .lut_mask = "0220"; +defparam \Mux14~0 .operation_mode = "normal"; +defparam \Mux14~0 .output_mode = "comb_only"; +defparam \Mux14~0 .register_cascade_mode = "off"; +defparam \Mux14~0 .sum_lutc_input = "datac"; +defparam \Mux14~0 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X7_Y2_N9 +maxii_lcell \Mux14~1 ( +// Equation(s): +// \Mux14~1_combout = (\RAMSpecSEL~1_combout & (\Mux14~0_combout & ((PS[1]) # (!\IS.110~regout )))) + + .clk(gnd), + .dataa(PS[1]), + .datab(\RAMSpecSEL~1_combout ), + .datac(\IS.110~regout ), + .datad(\Mux14~0_combout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Mux14~1_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Mux14~1 .lut_mask = "8c00"; +defparam \Mux14~1 .operation_mode = "normal"; +defparam \Mux14~1 .output_mode = "comb_only"; +defparam \Mux14~1 .register_cascade_mode = "off"; +defparam \Mux14~1 .sum_lutc_input = "datac"; +defparam \Mux14~1 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X7_Y2_N0 +maxii_lcell \SBA[0]~reg0 ( +// Equation(s): +// \SBA[0]~reg0_regout = DFFEAS(((PS[3] & (\Mux14~3_combout )) # (!PS[3] & ((\Mux14~1_combout )))), GLOBAL(\C25M~combout ), VCC, , , , , PS[2], ) + + .clk(\C25M~combout ), + .dataa(vcc), + .datab(\Mux14~3_combout ), + .datac(PS[3]), + .datad(\Mux14~1_combout ), + .aclr(gnd), + .aload(gnd), + .sclr(PS[2]), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\SBA[0]~reg0_regout ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \SBA[0]~reg0 .lut_mask = "cfc0"; +defparam \SBA[0]~reg0 .operation_mode = "normal"; +defparam \SBA[0]~reg0 .output_mode = "reg_only"; +defparam \SBA[0]~reg0 .register_cascade_mode = "off"; +defparam \SBA[0]~reg0 .sum_lutc_input = "datac"; +defparam \SBA[0]~reg0 .synch_mode = "on"; +// synopsys translate_on + +// Location: LC_X4_Y2_N5 +maxii_lcell \Mux13~0 ( +// Equation(s): +// \Mux13~0_combout = (PS[0] & (!PS[1] & ((\IS.110~regout ) # (!\RAMSpecSEL~1_combout )))) # (!PS[0] & (PS[1] & ((!\RAMSpecSEL~1_combout )))) + + .clk(gnd), + .dataa(PS[0]), + .datab(PS[1]), + .datac(\IS.110~regout ), + .datad(\RAMSpecSEL~1_combout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Mux13~0_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Mux13~0 .lut_mask = "2066"; +defparam \Mux13~0 .operation_mode = "normal"; +defparam \Mux13~0 .output_mode = "comb_only"; +defparam \Mux13~0 .register_cascade_mode = "off"; +defparam \Mux13~0 .sum_lutc_input = "datac"; +defparam \Mux13~0 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X6_Y2_N8 +maxii_lcell \SBA[1]~reg0 ( +// Equation(s): +// \SBA[1]~reg0_regout = DFFEAS((PS[3] & (\IS.110~regout & ((!\Mux14~2_combout )))) # (!PS[3] & (((\Mux13~0_combout )))), GLOBAL(\C25M~combout ), VCC, , , , , PS[2], ) + + .clk(\C25M~combout ), + .dataa(\IS.110~regout ), + .datab(\Mux13~0_combout ), + .datac(PS[3]), + .datad(\Mux14~2_combout ), + .aclr(gnd), + .aload(gnd), + .sclr(PS[2]), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\SBA[1]~reg0_regout ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \SBA[1]~reg0 .lut_mask = "0cac"; +defparam \SBA[1]~reg0 .operation_mode = "normal"; +defparam \SBA[1]~reg0 .output_mode = "reg_only"; +defparam \SBA[1]~reg0 .register_cascade_mode = "off"; +defparam \SBA[1]~reg0 .sum_lutc_input = "datac"; +defparam \SBA[1]~reg0 .synch_mode = "on"; +// synopsys translate_on + +// Location: LC_X6_Y2_N7 +maxii_lcell \Mux24~3 ( +// Equation(s): +// \Mux24~3_combout = (PS[3] & (LS[1] & ((!\Mux14~2_combout )))) # (!PS[3] & (((\Mux24~2 )))) + + .clk(gnd), + .dataa(PS[3]), + .datab(LS[1]), + .datac(\Mux24~2 ), + .datad(\Mux14~2_combout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Mux24~3_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Mux24~3 .lut_mask = "50d8"; +defparam \Mux24~3 .operation_mode = "normal"; +defparam \Mux24~3 .output_mode = "comb_only"; +defparam \Mux24~3 .register_cascade_mode = "off"; +defparam \Mux24~3 .sum_lutc_input = "datac"; +defparam \Mux24~3 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X6_Y4_N4 +maxii_lcell \SA[1]~5 ( +// Equation(s): +// \SA[1]~5_combout = ((PS[0]) # ((\IS.110~regout & PS[3]))) + + .clk(gnd), + .dataa(vcc), + .datab(\IS.110~regout ), + .datac(PS[3]), + .datad(PS[0]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\SA[1]~5_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \SA[1]~5 .lut_mask = "ffc0"; +defparam \SA[1]~5 .operation_mode = "normal"; +defparam \SA[1]~5 .output_mode = "comb_only"; +defparam \SA[1]~5 .register_cascade_mode = "off"; +defparam \SA[1]~5 .sum_lutc_input = "datac"; +defparam \SA[1]~5 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X6_Y4_N7 +maxii_lcell \SA[1]~6 ( +// Equation(s): +// \SA[1]~6_combout = (\SA[1]~5_combout ) # ((PS[1] & ((PS[3]) # (!\RAMSpecSEL~1_combout ))) # (!PS[1] & (!PS[3]))) + + .clk(gnd), + .dataa(\SA[1]~5_combout ), + .datab(PS[1]), + .datac(PS[3]), + .datad(\RAMSpecSEL~1_combout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\SA[1]~6_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \SA[1]~6 .lut_mask = "ebef"; +defparam \SA[1]~6 .operation_mode = "normal"; +defparam \SA[1]~6 .output_mode = "comb_only"; +defparam \SA[1]~6 .register_cascade_mode = "off"; +defparam \SA[1]~6 .sum_lutc_input = "datac"; +defparam \SA[1]~6 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X6_Y2_N5 +maxii_lcell \SA[0]~reg0 ( +// Equation(s): +// \SA[0]~reg0_regout = DFFEAS(((\SA[1]~6_combout & ((\Mux24~3_combout ))) # (!\SA[1]~6_combout & (Addr[1]))), GLOBAL(\C25M~combout ), VCC, , , , , PS[2], ) + + .clk(\C25M~combout ), + .dataa(Addr[1]), + .datab(vcc), + .datac(\Mux24~3_combout ), + .datad(\SA[1]~6_combout ), + .aclr(gnd), + .aload(gnd), + .sclr(PS[2]), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\SA[0]~reg0_regout ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \SA[0]~reg0 .lut_mask = "f0aa"; +defparam \SA[0]~reg0 .operation_mode = "normal"; +defparam \SA[0]~reg0 .output_mode = "reg_only"; +defparam \SA[0]~reg0 .register_cascade_mode = "off"; +defparam \SA[0]~reg0 .sum_lutc_input = "datac"; +defparam \SA[0]~reg0 .synch_mode = "on"; +// synopsys translate_on + +// Location: LC_X6_Y2_N6 +maxii_lcell \Mux23~3 ( +// Equation(s): +// \Mux23~3_combout = (PS[3] & (!\Mux14~2_combout & (LS[2]))) # (!PS[3] & (((\Mux23~2 )))) + + .clk(gnd), + .dataa(\Mux14~2_combout ), + .datab(LS[2]), + .datac(PS[3]), + .datad(\Mux23~2 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Mux23~3_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Mux23~3 .lut_mask = "4f40"; +defparam \Mux23~3 .operation_mode = "normal"; +defparam \Mux23~3 .output_mode = "comb_only"; +defparam \Mux23~3 .register_cascade_mode = "off"; +defparam \Mux23~3 .sum_lutc_input = "datac"; +defparam \Mux23~3 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X6_Y2_N4 +maxii_lcell \SA[1]~reg0 ( +// Equation(s): +// \SA[1]~reg0_regout = DFFEAS(((\SA[1]~6_combout & ((\Mux23~3_combout ))) # (!\SA[1]~6_combout & (Addr[2]))), GLOBAL(\C25M~combout ), VCC, , , , , PS[2], ) + + .clk(\C25M~combout ), + .dataa(vcc), + .datab(Addr[2]), + .datac(\Mux23~3_combout ), + .datad(\SA[1]~6_combout ), + .aclr(gnd), + .aload(gnd), + .sclr(PS[2]), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\SA[1]~reg0_regout ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \SA[1]~reg0 .lut_mask = "f0cc"; +defparam \SA[1]~reg0 .operation_mode = "normal"; +defparam \SA[1]~reg0 .output_mode = "reg_only"; +defparam \SA[1]~reg0 .register_cascade_mode = "off"; +defparam \SA[1]~reg0 .sum_lutc_input = "datac"; +defparam \SA[1]~reg0 .synch_mode = "on"; +// synopsys translate_on + +// Location: LC_X6_Y2_N9 +maxii_lcell Bank( +// Equation(s): +// \Bank~regout = DFFEAS((\always9~1_combout & ((\always8~0 & (\RD[0]~0 )) # (!\always8~0 & ((\Bank~regout ))))) # (!\always9~1_combout & (((\Bank~regout )))), GLOBAL(\C25M~combout ), GLOBAL(\nRESr~regout ), , , , , , ) + + .clk(\C25M~combout ), + .dataa(\always9~1_combout ), + .datab(\RD[0]~0 ), + .datac(\always8~0 ), + .datad(\Bank~regout ), + .aclr(!\nRESr~regout ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\Bank~regout ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam Bank.lut_mask = "df80"; +defparam Bank.operation_mode = "normal"; +defparam Bank.output_mode = "reg_only"; +defparam Bank.register_cascade_mode = "off"; +defparam Bank.sum_lutc_input = "datac"; +defparam Bank.synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X6_Y2_N3 +maxii_lcell \Mux22~2 ( +// Equation(s): +// \Mux22~2_combout = (\SA[1]~2_combout & (((\Mux22~1 )))) # (!\SA[1]~2_combout & ((\Mux22~1 & ((\Bank~regout ))) # (!\Mux22~1 & (Addr[12])))) + + .clk(gnd), + .dataa(Addr[12]), + .datab(\SA[1]~2_combout ), + .datac(\Mux22~1 ), + .datad(\Bank~regout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Mux22~2_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Mux22~2 .lut_mask = "f2c2"; +defparam \Mux22~2 .operation_mode = "normal"; +defparam \Mux22~2 .output_mode = "comb_only"; +defparam \Mux22~2 .register_cascade_mode = "off"; +defparam \Mux22~2 .sum_lutc_input = "datac"; +defparam \Mux22~2 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X6_Y2_N0 +maxii_lcell \Mux22~3 ( +// Equation(s): +// \Mux22~3_combout = (PS[3] & (((LS[3] & !\Mux14~2_combout )))) # (!PS[3] & (\Mux22~2_combout )) + + .clk(gnd), + .dataa(\Mux22~2_combout ), + .datab(LS[3]), + .datac(PS[3]), + .datad(\Mux14~2_combout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Mux22~3_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Mux22~3 .lut_mask = "0aca"; +defparam \Mux22~3 .operation_mode = "normal"; +defparam \Mux22~3 .output_mode = "comb_only"; +defparam \Mux22~3 .register_cascade_mode = "off"; +defparam \Mux22~3 .sum_lutc_input = "datac"; +defparam \Mux22~3 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X6_Y2_N1 +maxii_lcell \SA[2]~reg0 ( +// Equation(s): +// \SA[2]~reg0_regout = DFFEAS(((\SA[1]~6_combout & ((\Mux22~3_combout ))) # (!\SA[1]~6_combout & (Addr[3]))), GLOBAL(\C25M~combout ), VCC, , , , , PS[2], ) + + .clk(\C25M~combout ), + .dataa(vcc), + .datab(Addr[3]), + .datac(\Mux22~3_combout ), + .datad(\SA[1]~6_combout ), + .aclr(gnd), + .aload(gnd), + .sclr(PS[2]), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\SA[2]~reg0_regout ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \SA[2]~reg0 .lut_mask = "f0cc"; +defparam \SA[2]~reg0 .operation_mode = "normal"; +defparam \SA[2]~reg0 .output_mode = "reg_only"; +defparam \SA[2]~reg0 .register_cascade_mode = "off"; +defparam \SA[2]~reg0 .sum_lutc_input = "datac"; +defparam \SA[2]~reg0 .synch_mode = "on"; +// synopsys translate_on + +// Location: LC_X6_Y4_N6 +maxii_lcell \SA[3]~15 ( +// Equation(s): +// \SA[3]~15_combout = (PS[3] & (!PS[1] & (!\IS.110~regout & !PS[0]))) # (!PS[3] & (PS[1])) + + .clk(gnd), + .dataa(PS[3]), + .datab(PS[1]), + .datac(\IS.110~regout ), + .datad(PS[0]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\SA[3]~15_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \SA[3]~15 .lut_mask = "4446"; +defparam \SA[3]~15 .operation_mode = "normal"; +defparam \SA[3]~15 .output_mode = "comb_only"; +defparam \SA[3]~15 .register_cascade_mode = "off"; +defparam \SA[3]~15 .sum_lutc_input = "datac"; +defparam \SA[3]~15 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X6_Y4_N8 +maxii_lcell \SA[3]~9 ( +// Equation(s): +// \SA[3]~9_combout = ((PS[3] & (!PS[1] & !PS[0]))) # (!\SA[1]~6_combout ) + + .clk(gnd), + .dataa(PS[3]), + .datab(PS[1]), + .datac(\SA[1]~6_combout ), + .datad(PS[0]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\SA[3]~9_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \SA[3]~9 .lut_mask = "0f2f"; +defparam \SA[3]~9 .operation_mode = "normal"; +defparam \SA[3]~9 .output_mode = "comb_only"; +defparam \SA[3]~9 .register_cascade_mode = "off"; +defparam \SA[3]~9 .sum_lutc_input = "datac"; +defparam \SA[3]~9 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X4_Y4_N6 +maxii_lcell \Mux21~3 ( +// Equation(s): +// \Mux21~3_combout = (\SA[3]~15_combout & (((Addr[4]) # (!\SA[3]~9_combout )))) # (!\SA[3]~15_combout & (LS[4] & ((\SA[3]~9_combout )))) + + .clk(gnd), + .dataa(\SA[3]~15_combout ), + .datab(LS[4]), + .datac(Addr[4]), + .datad(\SA[3]~9_combout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Mux21~3_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Mux21~3 .lut_mask = "e4aa"; +defparam \Mux21~3 .operation_mode = "normal"; +defparam \Mux21~3 .output_mode = "comb_only"; +defparam \Mux21~3 .register_cascade_mode = "off"; +defparam \Mux21~3 .sum_lutc_input = "datac"; +defparam \Mux21~3 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X3_Y4_N8 +maxii_lcell \Mux21~4 ( +// Equation(s): +// \Mux21~4_combout = (Addr[13] & (PS[0] & (\RAMSpecSEL~1_combout & !\IS.110~regout ))) + + .clk(gnd), + .dataa(Addr[13]), + .datab(PS[0]), + .datac(\RAMSpecSEL~1_combout ), + .datad(\IS.110~regout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Mux21~4_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Mux21~4 .lut_mask = "0080"; +defparam \Mux21~4 .operation_mode = "normal"; +defparam \Mux21~4 .output_mode = "comb_only"; +defparam \Mux21~4 .register_cascade_mode = "off"; +defparam \Mux21~4 .sum_lutc_input = "datac"; +defparam \Mux21~4 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X6_Y4_N2 +maxii_lcell \SA[3]~8 ( +// Equation(s): +// \SA[3]~8_combout = (PS[3]) # ((!\SA[1]~5_combout & (PS[1] & \RAMSpecSEL~1_combout ))) + + .clk(gnd), + .dataa(\SA[1]~5_combout ), + .datab(PS[1]), + .datac(PS[3]), + .datad(\RAMSpecSEL~1_combout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\SA[3]~8_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \SA[3]~8 .lut_mask = "f4f0"; +defparam \SA[3]~8 .operation_mode = "normal"; +defparam \SA[3]~8 .output_mode = "comb_only"; +defparam \SA[3]~8 .register_cascade_mode = "off"; +defparam \SA[3]~8 .sum_lutc_input = "datac"; +defparam \SA[3]~8 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X4_Y4_N3 +maxii_lcell \SA[3]~reg0 ( +// Equation(s): +// \SA[3]~reg0_regout = DFFEAS((\Mux21~3_combout & ((\Mux21~2 ) # ((\SA[3]~8_combout )))) # (!\Mux21~3_combout & (((\Mux21~4_combout & !\SA[3]~8_combout )))), GLOBAL(\C25M~combout ), VCC, , , , , PS[2], ) + + .clk(\C25M~combout ), + .dataa(\Mux21~3_combout ), + .datab(\Mux21~2 ), + .datac(\Mux21~4_combout ), + .datad(\SA[3]~8_combout ), + .aclr(gnd), + .aload(gnd), + .sclr(PS[2]), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\SA[3]~reg0_regout ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \SA[3]~reg0 .lut_mask = "aad8"; +defparam \SA[3]~reg0 .operation_mode = "normal"; +defparam \SA[3]~reg0 .output_mode = "reg_only"; +defparam \SA[3]~reg0 .register_cascade_mode = "off"; +defparam \SA[3]~reg0 .sum_lutc_input = "datac"; +defparam \SA[3]~reg0 .synch_mode = "on"; +// synopsys translate_on + +// Location: LC_X3_Y4_N9 +maxii_lcell \Mux20~4 ( +// Equation(s): +// \Mux20~4_combout = (\RAMSpecSEL~1_combout & (PS[0] & (Addr[14] & !\IS.110~regout ))) + + .clk(gnd), + .dataa(\RAMSpecSEL~1_combout ), + .datab(PS[0]), + .datac(Addr[14]), + .datad(\IS.110~regout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Mux20~4_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Mux20~4 .lut_mask = "0080"; +defparam \Mux20~4 .operation_mode = "normal"; +defparam \Mux20~4 .output_mode = "comb_only"; +defparam \Mux20~4 .register_cascade_mode = "off"; +defparam \Mux20~4 .sum_lutc_input = "datac"; +defparam \Mux20~4 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X2_Y4_N0 +maxii_lcell \Mux20~2 ( +// Equation(s): +// \Mux20~2_combout = (RAr[5] & (((!PS[0])))) + + .clk(gnd), + .dataa(RAr[5]), + .datab(vcc), + .datac(vcc), + .datad(PS[0]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Mux20~2_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Mux20~2 .lut_mask = "00aa"; +defparam \Mux20~2 .operation_mode = "normal"; +defparam \Mux20~2 .output_mode = "comb_only"; +defparam \Mux20~2 .register_cascade_mode = "off"; +defparam \Mux20~2 .sum_lutc_input = "datac"; +defparam \Mux20~2 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X4_Y4_N7 +maxii_lcell \Mux20~3 ( +// Equation(s): +// \Mux20~3_combout = (\SA[3]~9_combout & ((\SA[3]~15_combout & ((Addr[5]))) # (!\SA[3]~15_combout & (LS[5])))) # (!\SA[3]~9_combout & (((\SA[3]~15_combout )))) + + .clk(gnd), + .dataa(LS[5]), + .datab(\SA[3]~9_combout ), + .datac(\SA[3]~15_combout ), + .datad(Addr[5]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Mux20~3_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Mux20~3 .lut_mask = "f838"; +defparam \Mux20~3 .operation_mode = "normal"; +defparam \Mux20~3 .output_mode = "comb_only"; +defparam \Mux20~3 .register_cascade_mode = "off"; +defparam \Mux20~3 .sum_lutc_input = "datac"; +defparam \Mux20~3 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X4_Y4_N4 +maxii_lcell \SA[4]~reg0 ( +// Equation(s): +// \SA[4]~reg0_regout = DFFEAS((\Mux20~3_combout & (((\Mux20~2_combout ) # (\SA[3]~8_combout )))) # (!\Mux20~3_combout & (\Mux20~4_combout & ((!\SA[3]~8_combout )))), GLOBAL(\C25M~combout ), VCC, , , , , PS[2], ) + + .clk(\C25M~combout ), + .dataa(\Mux20~4_combout ), + .datab(\Mux20~2_combout ), + .datac(\Mux20~3_combout ), + .datad(\SA[3]~8_combout ), + .aclr(gnd), + .aload(gnd), + .sclr(PS[2]), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\SA[4]~reg0_regout ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \SA[4]~reg0 .lut_mask = "f0ca"; +defparam \SA[4]~reg0 .operation_mode = "normal"; +defparam \SA[4]~reg0 .output_mode = "reg_only"; +defparam \SA[4]~reg0 .register_cascade_mode = "off"; +defparam \SA[4]~reg0 .sum_lutc_input = "datac"; +defparam \SA[4]~reg0 .synch_mode = "on"; +// synopsys translate_on + +// Location: LC_X6_Y4_N5 +maxii_lcell \Mux19~3 ( +// Equation(s): +// \Mux19~3_combout = (\SA[3]~15_combout & (Addr[6] & ((\SA[3]~9_combout )))) # (!\SA[3]~15_combout & (((LS[6]) # (!\SA[3]~9_combout )))) + + .clk(gnd), + .dataa(Addr[6]), + .datab(\SA[3]~15_combout ), + .datac(LS[6]), + .datad(\SA[3]~9_combout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Mux19~3_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Mux19~3 .lut_mask = "b833"; +defparam \Mux19~3 .operation_mode = "normal"; +defparam \Mux19~3 .output_mode = "comb_only"; +defparam \Mux19~3 .register_cascade_mode = "off"; +defparam \Mux19~3 .sum_lutc_input = "datac"; +defparam \Mux19~3 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X6_Y4_N9 +maxii_lcell \Mux19~5 ( +// Equation(s): +// \Mux19~5_combout = (\IS.110~regout ) # (((Addr[15]) # (!PS[0])) # (!\RAMSpecSEL~1_combout )) + + .clk(gnd), + .dataa(\IS.110~regout ), + .datab(\RAMSpecSEL~1_combout ), + .datac(Addr[15]), + .datad(PS[0]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Mux19~5_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Mux19~5 .lut_mask = "fbff"; +defparam \Mux19~5 .operation_mode = "normal"; +defparam \Mux19~5 .output_mode = "comb_only"; +defparam \Mux19~5 .register_cascade_mode = "off"; +defparam \Mux19~5 .sum_lutc_input = "datac"; +defparam \Mux19~5 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X6_Y4_N3 +maxii_lcell \Mux19~4 ( +// Equation(s): +// \Mux19~4_combout = (\Mux19~3_combout & ((\Mux19~5_combout ) # ((\SA[3]~8_combout )))) # (!\Mux19~3_combout & (((\Mux19~2 & !\SA[3]~8_combout )))) + + .clk(gnd), + .dataa(\Mux19~3_combout ), + .datab(\Mux19~5_combout ), + .datac(\Mux19~2 ), + .datad(\SA[3]~8_combout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Mux19~4_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Mux19~4 .lut_mask = "aad8"; +defparam \Mux19~4 .operation_mode = "normal"; +defparam \Mux19~4 .output_mode = "comb_only"; +defparam \Mux19~4 .register_cascade_mode = "off"; +defparam \Mux19~4 .sum_lutc_input = "datac"; +defparam \Mux19~4 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X6_Y4_N1 +maxii_lcell \SA[5]~reg0 ( +// Equation(s): +// \SA[5]~reg0_regout = DFFEAS((((\Mux19~4_combout ))), GLOBAL(\C25M~combout ), VCC, , , VCC, , , PS[2]) + + .clk(\C25M~combout ), + .dataa(vcc), + .datab(vcc), + .datac(vcc), + .datad(\Mux19~4_combout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(PS[2]), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\SA[5]~reg0_regout ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \SA[5]~reg0 .lut_mask = "ff00"; +defparam \SA[5]~reg0 .operation_mode = "normal"; +defparam \SA[5]~reg0 .output_mode = "reg_only"; +defparam \SA[5]~reg0 .register_cascade_mode = "off"; +defparam \SA[5]~reg0 .sum_lutc_input = "datac"; +defparam \SA[5]~reg0 .synch_mode = "on"; +// synopsys translate_on + +// Location: LC_X3_Y4_N0 +maxii_lcell \Mux18~4 ( +// Equation(s): +// \Mux18~4_combout = (!\IS.110~regout & (PS[0] & (\RAMSpecSEL~1_combout & Addr[16]))) + + .clk(gnd), + .dataa(\IS.110~regout ), + .datab(PS[0]), + .datac(\RAMSpecSEL~1_combout ), + .datad(Addr[16]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Mux18~4_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Mux18~4 .lut_mask = "4000"; +defparam \Mux18~4 .operation_mode = "normal"; +defparam \Mux18~4 .output_mode = "comb_only"; +defparam \Mux18~4 .register_cascade_mode = "off"; +defparam \Mux18~4 .sum_lutc_input = "datac"; +defparam \Mux18~4 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X4_Y4_N0 +maxii_lcell \Mux18~3 ( +// Equation(s): +// \Mux18~3_combout = (\SA[3]~15_combout & ((Addr[7]) # ((!\SA[3]~9_combout )))) # (!\SA[3]~15_combout & (((LS[7] & \SA[3]~9_combout )))) + + .clk(gnd), + .dataa(\SA[3]~15_combout ), + .datab(Addr[7]), + .datac(LS[7]), + .datad(\SA[3]~9_combout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Mux18~3_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Mux18~3 .lut_mask = "d8aa"; +defparam \Mux18~3 .operation_mode = "normal"; +defparam \Mux18~3 .output_mode = "comb_only"; +defparam \Mux18~3 .register_cascade_mode = "off"; +defparam \Mux18~3 .sum_lutc_input = "datac"; +defparam \Mux18~3 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X3_Y2_N9 +maxii_lcell \Mux18~2 ( +// Equation(s): +// \Mux18~2_combout = (((RAr[7] & !PS[0]))) + + .clk(gnd), + .dataa(vcc), + .datab(vcc), + .datac(RAr[7]), + .datad(PS[0]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Mux18~2_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Mux18~2 .lut_mask = "00f0"; +defparam \Mux18~2 .operation_mode = "normal"; +defparam \Mux18~2 .output_mode = "comb_only"; +defparam \Mux18~2 .register_cascade_mode = "off"; +defparam \Mux18~2 .sum_lutc_input = "datac"; +defparam \Mux18~2 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X4_Y4_N8 +maxii_lcell \SA[6]~reg0 ( +// Equation(s): +// \SA[6]~reg0_regout = DFFEAS((\SA[3]~8_combout & (((\Mux18~3_combout )))) # (!\SA[3]~8_combout & ((\Mux18~3_combout & ((\Mux18~2_combout ))) # (!\Mux18~3_combout & (\Mux18~4_combout )))), GLOBAL(\C25M~combout ), VCC, , , , , PS[2], ) + + .clk(\C25M~combout ), + .dataa(\Mux18~4_combout ), + .datab(\SA[3]~8_combout ), + .datac(\Mux18~3_combout ), + .datad(\Mux18~2_combout ), + .aclr(gnd), + .aload(gnd), + .sclr(PS[2]), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\SA[6]~reg0_regout ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \SA[6]~reg0 .lut_mask = "f2c2"; +defparam \SA[6]~reg0 .operation_mode = "normal"; +defparam \SA[6]~reg0 .output_mode = "reg_only"; +defparam \SA[6]~reg0 .register_cascade_mode = "off"; +defparam \SA[6]~reg0 .sum_lutc_input = "datac"; +defparam \SA[6]~reg0 .synch_mode = "on"; +// synopsys translate_on + +// Location: LC_X3_Y4_N5 +maxii_lcell \Mux17~4 ( +// Equation(s): +// \Mux17~4_combout = (Addr[17] & (PS[0] & (\RAMSpecSEL~1_combout & !\IS.110~regout ))) + + .clk(gnd), + .dataa(Addr[17]), + .datab(PS[0]), + .datac(\RAMSpecSEL~1_combout ), + .datad(\IS.110~regout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Mux17~4_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Mux17~4 .lut_mask = "0080"; +defparam \Mux17~4 .operation_mode = "normal"; +defparam \Mux17~4 .output_mode = "comb_only"; +defparam \Mux17~4 .register_cascade_mode = "off"; +defparam \Mux17~4 .sum_lutc_input = "datac"; +defparam \Mux17~4 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X3_Y2_N5 +maxii_lcell \Mux17~2 ( +// Equation(s): +// \Mux17~2_combout = (((RAr[8] & !PS[0]))) + + .clk(gnd), + .dataa(vcc), + .datab(vcc), + .datac(RAr[8]), + .datad(PS[0]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Mux17~2_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Mux17~2 .lut_mask = "00f0"; +defparam \Mux17~2 .operation_mode = "normal"; +defparam \Mux17~2 .output_mode = "comb_only"; +defparam \Mux17~2 .register_cascade_mode = "off"; +defparam \Mux17~2 .sum_lutc_input = "datac"; +defparam \Mux17~2 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X4_Y4_N2 +maxii_lcell \Mux17~3 ( +// Equation(s): +// \Mux17~3_combout = (\SA[3]~15_combout & ((Addr[8]) # ((!\SA[3]~9_combout )))) # (!\SA[3]~15_combout & (((LS[8] & \SA[3]~9_combout )))) + + .clk(gnd), + .dataa(Addr[8]), + .datab(LS[8]), + .datac(\SA[3]~15_combout ), + .datad(\SA[3]~9_combout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Mux17~3_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Mux17~3 .lut_mask = "acf0"; +defparam \Mux17~3 .operation_mode = "normal"; +defparam \Mux17~3 .output_mode = "comb_only"; +defparam \Mux17~3 .register_cascade_mode = "off"; +defparam \Mux17~3 .sum_lutc_input = "datac"; +defparam \Mux17~3 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X4_Y4_N9 +maxii_lcell \SA[7]~reg0 ( +// Equation(s): +// \SA[7]~reg0_regout = DFFEAS((\SA[3]~8_combout & (((\Mux17~3_combout )))) # (!\SA[3]~8_combout & ((\Mux17~3_combout & ((\Mux17~2_combout ))) # (!\Mux17~3_combout & (\Mux17~4_combout )))), GLOBAL(\C25M~combout ), VCC, , , , , PS[2], ) + + .clk(\C25M~combout ), + .dataa(\Mux17~4_combout ), + .datab(\SA[3]~8_combout ), + .datac(\Mux17~2_combout ), + .datad(\Mux17~3_combout ), + .aclr(gnd), + .aload(gnd), + .sclr(PS[2]), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\SA[7]~reg0_regout ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \SA[7]~reg0 .lut_mask = "fc22"; +defparam \SA[7]~reg0 .operation_mode = "normal"; +defparam \SA[7]~reg0 .output_mode = "reg_only"; +defparam \SA[7]~reg0 .register_cascade_mode = "off"; +defparam \SA[7]~reg0 .sum_lutc_input = "datac"; +defparam \SA[7]~reg0 .synch_mode = "on"; +// synopsys translate_on + +// Location: LC_X4_Y4_N5 +maxii_lcell \Mux16~3 ( +// Equation(s): +// \Mux16~3_combout = (\SA[3]~15_combout & ((Addr[9]) # ((!\SA[3]~9_combout )))) # (!\SA[3]~15_combout & (((LS[9] & \SA[3]~9_combout )))) + + .clk(gnd), + .dataa(Addr[9]), + .datab(LS[9]), + .datac(\SA[3]~15_combout ), + .datad(\SA[3]~9_combout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Mux16~3_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Mux16~3 .lut_mask = "acf0"; +defparam \Mux16~3 .operation_mode = "normal"; +defparam \Mux16~3 .output_mode = "comb_only"; +defparam \Mux16~3 .register_cascade_mode = "off"; +defparam \Mux16~3 .sum_lutc_input = "datac"; +defparam \Mux16~3 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X3_Y4_N6 +maxii_lcell \Mux16~4 ( +// Equation(s): +// \Mux16~4_combout = (Addr[18] & (PS[0] & (\RAMSpecSEL~1_combout & !\IS.110~regout ))) + + .clk(gnd), + .dataa(Addr[18]), + .datab(PS[0]), + .datac(\RAMSpecSEL~1_combout ), + .datad(\IS.110~regout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Mux16~4_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Mux16~4 .lut_mask = "0080"; +defparam \Mux16~4 .operation_mode = "normal"; +defparam \Mux16~4 .output_mode = "comb_only"; +defparam \Mux16~4 .register_cascade_mode = "off"; +defparam \Mux16~4 .sum_lutc_input = "datac"; +defparam \Mux16~4 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X4_Y4_N1 +maxii_lcell \SA[8]~reg0 ( +// Equation(s): +// \SA[8]~reg0_regout = DFFEAS((\Mux16~3_combout & (((\Mux16~2 ) # (\SA[3]~8_combout )))) # (!\Mux16~3_combout & (\Mux16~4_combout & ((!\SA[3]~8_combout )))), GLOBAL(\C25M~combout ), VCC, , , , , PS[2], ) + + .clk(\C25M~combout ), + .dataa(\Mux16~3_combout ), + .datab(\Mux16~4_combout ), + .datac(\Mux16~2 ), + .datad(\SA[3]~8_combout ), + .aclr(gnd), + .aload(gnd), + .sclr(PS[2]), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\SA[8]~reg0_regout ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \SA[8]~reg0 .lut_mask = "aae4"; +defparam \SA[8]~reg0 .operation_mode = "normal"; +defparam \SA[8]~reg0 .output_mode = "reg_only"; +defparam \SA[8]~reg0 .register_cascade_mode = "off"; +defparam \SA[8]~reg0 .sum_lutc_input = "datac"; +defparam \SA[8]~reg0 .synch_mode = "on"; +// synopsys translate_on + +// Location: LC_X7_Y1_N0 +maxii_lcell \SA[1]~7 ( +// Equation(s): +// \SA[1]~7_combout = (PS[0] & (((!\IS.110~regout )))) + + .clk(gnd), + .dataa(PS[0]), + .datab(vcc), + .datac(vcc), + .datad(\IS.110~regout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\SA[1]~7_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \SA[1]~7 .lut_mask = "00aa"; +defparam \SA[1]~7 .operation_mode = "normal"; +defparam \SA[1]~7 .output_mode = "comb_only"; +defparam \SA[1]~7 .register_cascade_mode = "off"; +defparam \SA[1]~7 .sum_lutc_input = "datac"; +defparam \SA[1]~7 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X7_Y2_N5 +maxii_lcell \SA~10 ( +// Equation(s): +// \SA~10_combout = (\SA[1]~7_combout & (\RAMSpecSEL~1_combout & (!PS[2] & \Equal1~0_combout ))) + + .clk(gnd), + .dataa(\SA[1]~7_combout ), + .datab(\RAMSpecSEL~1_combout ), + .datac(PS[2]), + .datad(\Equal1~0_combout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\SA~10_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \SA~10 .lut_mask = "0800"; +defparam \SA~10 .operation_mode = "normal"; +defparam \SA~10 .output_mode = "comb_only"; +defparam \SA~10 .register_cascade_mode = "off"; +defparam \SA~10 .sum_lutc_input = "datac"; +defparam \SA~10 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X7_Y4_N9 +maxii_lcell \SA[9]~reg0 ( +// Equation(s): +// \SA[9]~reg0_regout = DFFEAS((((Addr[19])) # (!\SA~10_combout )), GLOBAL(\C25M~combout ), VCC, , , , , , ) + + .clk(\C25M~combout ), + .dataa(vcc), + .datab(\SA~10_combout ), + .datac(vcc), + .datad(Addr[19]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\SA[9]~reg0_regout ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \SA[9]~reg0 .lut_mask = "ff33"; +defparam \SA[9]~reg0 .operation_mode = "normal"; +defparam \SA[9]~reg0 .output_mode = "reg_only"; +defparam \SA[9]~reg0 .register_cascade_mode = "off"; +defparam \SA[9]~reg0 .sum_lutc_input = "datac"; +defparam \SA[9]~reg0 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X7_Y2_N6 +maxii_lcell \Mux15~0 ( +// Equation(s): +// \Mux15~0_combout = (PS[2]) # ((PS[1] $ (PS[3])) # (!PS[0])) + + .clk(gnd), + .dataa(PS[1]), + .datab(PS[3]), + .datac(PS[2]), + .datad(PS[0]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Mux15~0_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Mux15~0 .lut_mask = "f6ff"; +defparam \Mux15~0 .operation_mode = "normal"; +defparam \Mux15~0 .output_mode = "comb_only"; +defparam \Mux15~0 .register_cascade_mode = "off"; +defparam \Mux15~0 .sum_lutc_input = "datac"; +defparam \Mux15~0 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X7_Y3_N8 +maxii_lcell \Mux15~1 ( +// Equation(s): +// \Mux15~1_combout = ((\IS.110~regout ) # ((!SetFWr[1] & Addr[20]))) + + .clk(gnd), + .dataa(vcc), + .datab(SetFWr[1]), + .datac(\IS.110~regout ), + .datad(Addr[20]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Mux15~1_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Mux15~1 .lut_mask = "f3f0"; +defparam \Mux15~1 .operation_mode = "normal"; +defparam \Mux15~1 .output_mode = "comb_only"; +defparam \Mux15~1 .register_cascade_mode = "off"; +defparam \Mux15~1 .sum_lutc_input = "datac"; +defparam \Mux15~1 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X7_Y3_N2 +maxii_lcell \SA[10]~reg0 ( +// Equation(s): +// \SA[10]~reg0_regout = DFFEAS((\Mux15~0_combout ) # ((!PS[1] & ((\Mux15~1_combout ) # (!\RAMSpecSEL~1_combout )))), GLOBAL(\C25M~combout ), VCC, , , , , , ) + + .clk(\C25M~combout ), + .dataa(PS[1]), + .datab(\RAMSpecSEL~1_combout ), + .datac(\Mux15~0_combout ), + .datad(\Mux15~1_combout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\SA[10]~reg0_regout ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \SA[10]~reg0 .lut_mask = "f5f1"; +defparam \SA[10]~reg0 .operation_mode = "normal"; +defparam \SA[10]~reg0 .output_mode = "reg_only"; +defparam \SA[10]~reg0 .register_cascade_mode = "off"; +defparam \SA[10]~reg0 .sum_lutc_input = "datac"; +defparam \SA[10]~reg0 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X7_Y4_N8 +maxii_lcell \SA[11]~reg0 ( +// Equation(s): +// \SA[11]~reg0_regout = DFFEAS(((!SetFWr[1] & (Addr[21] & \SA~10_combout ))), GLOBAL(\C25M~combout ), VCC, , , , , , ) + + .clk(\C25M~combout ), + .dataa(vcc), + .datab(SetFWr[1]), + .datac(Addr[21]), + .datad(\SA~10_combout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\SA[11]~reg0_regout ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \SA[11]~reg0 .lut_mask = "3000"; +defparam \SA[11]~reg0 .operation_mode = "normal"; +defparam \SA[11]~reg0 .output_mode = "reg_only"; +defparam \SA[11]~reg0 .register_cascade_mode = "off"; +defparam \SA[11]~reg0 .sum_lutc_input = "datac"; +defparam \SA[11]~reg0 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X7_Y3_N3 +maxii_lcell \SA[12]~reg0 ( +// Equation(s): +// \SA[12]~reg0_regout = DFFEAS(((!SetFWr[1] & (Addr[22] & \SA~10_combout ))), GLOBAL(\C25M~combout ), VCC, , , , , , ) + + .clk(\C25M~combout ), + .dataa(vcc), + .datab(SetFWr[1]), + .datac(Addr[22]), + .datad(\SA~10_combout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\SA[12]~reg0_regout ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \SA[12]~reg0 .lut_mask = "3000"; +defparam \SA[12]~reg0 .operation_mode = "normal"; +defparam \SA[12]~reg0 .output_mode = "reg_only"; +defparam \SA[12]~reg0 .register_cascade_mode = "off"; +defparam \SA[12]~reg0 .sum_lutc_input = "datac"; +defparam \SA[12]~reg0 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X4_Y1_N2 +maxii_lcell \nRCS~3 ( +// Equation(s): +// \nRCS~3_combout = (\CXXXr~regout & (\nWEr~regout & ((\IOROMEN~regout ) # (!RAr[11])))) + + .clk(gnd), + .dataa(\IOROMEN~regout ), + .datab(RAr[11]), + .datac(\CXXXr~regout ), + .datad(\nWEr~regout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\nRCS~3_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \nRCS~3 .lut_mask = "b000"; +defparam \nRCS~3 .operation_mode = "normal"; +defparam \nRCS~3 .output_mode = "comb_only"; +defparam \nRCS~3 .register_cascade_mode = "off"; +defparam \nRCS~3 .sum_lutc_input = "datac"; +defparam \nRCS~3 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X4_Y1_N9 +maxii_lcell \nRCS~4 ( +// Equation(s): +// \nRCS~4_combout = ((!\Equal9~0 & ((\nRCS~3_combout )))) + + .clk(gnd), + .dataa(vcc), + .datab(\Equal9~0 ), + .datac(vcc), + .datad(\nRCS~3_combout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\nRCS~4_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \nRCS~4 .lut_mask = "3300"; +defparam \nRCS~4 .operation_mode = "normal"; +defparam \nRCS~4 .output_mode = "comb_only"; +defparam \nRCS~4 .register_cascade_mode = "off"; +defparam \nRCS~4 .sum_lutc_input = "datac"; +defparam \nRCS~4 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X5_Y1_N9 +maxii_lcell \Mux12~1 ( +// Equation(s): +// \Mux12~1_combout = (\nWEr~regout & (((PS[1])))) + + .clk(gnd), + .dataa(\nWEr~regout ), + .datab(vcc), + .datac(vcc), + .datad(PS[1]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Mux12~1_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Mux12~1 .lut_mask = "aa00"; +defparam \Mux12~1 .operation_mode = "normal"; +defparam \Mux12~1 .output_mode = "comb_only"; +defparam \Mux12~1 .register_cascade_mode = "off"; +defparam \Mux12~1 .sum_lutc_input = "datac"; +defparam \Mux12~1 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X5_Y1_N0 +maxii_lcell \Mux12~2 ( +// Equation(s): +// \Mux12~2_combout = (\IS.111~regout & (\Mux12~1_combout & ((\RAMSpecSEL~1_combout ) # (\nRCS~4_combout )))) + + .clk(gnd), + .dataa(\IS.111~regout ), + .datab(\RAMSpecSEL~1_combout ), + .datac(\nRCS~4_combout ), + .datad(\Mux12~1_combout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Mux12~2_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Mux12~2 .lut_mask = "a800"; +defparam \Mux12~2 .operation_mode = "normal"; +defparam \Mux12~2 .output_mode = "comb_only"; +defparam \Mux12~2 .register_cascade_mode = "off"; +defparam \Mux12~2 .sum_lutc_input = "datac"; +defparam \Mux12~2 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X5_Y1_N7 +maxii_lcell \nRCS~5 ( +// Equation(s): +// \nRCS~5_combout = (\IS.110~regout ) # ((\IS.111~regout & ((\nRCS~4_combout ) # (\RAMSpecSEL~1_combout )))) + + .clk(gnd), + .dataa(\IS.111~regout ), + .datab(\IS.110~regout ), + .datac(\nRCS~4_combout ), + .datad(\RAMSpecSEL~1_combout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\nRCS~5_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \nRCS~5 .lut_mask = "eeec"; +defparam \nRCS~5 .operation_mode = "normal"; +defparam \nRCS~5 .output_mode = "comb_only"; +defparam \nRCS~5 .register_cascade_mode = "off"; +defparam \nRCS~5 .sum_lutc_input = "datac"; +defparam \nRCS~5 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X6_Y1_N6 +maxii_lcell \Mux12~3 ( +// Equation(s): +// \Mux12~3_combout = (\Mux12~2_combout & ((PS[1] $ (!PS[0])))) # (!\Mux12~2_combout & (((PS[1]) # (!PS[0])) # (!\nRCS~5_combout ))) + + .clk(gnd), + .dataa(\Mux12~2_combout ), + .datab(\nRCS~5_combout ), + .datac(PS[1]), + .datad(PS[0]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Mux12~3_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Mux12~3 .lut_mask = "f15f"; +defparam \Mux12~3 .operation_mode = "normal"; +defparam \Mux12~3 .output_mode = "comb_only"; +defparam \Mux12~3 .register_cascade_mode = "off"; +defparam \Mux12~3 .sum_lutc_input = "datac"; +defparam \Mux12~3 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X3_Y1_N2 +maxii_lcell \IS.000 ( +// Equation(s): +// \IS.000~regout = DFFEAS(VCC, GLOBAL(\C25M~combout ), VCC, , \IS~19_combout , , , , ) + + .clk(\C25M~combout ), + .dataa(vcc), + .datab(vcc), + .datac(vcc), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\IS~19_combout ), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\IS.000~regout ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \IS.000 .lut_mask = "ffff"; +defparam \IS.000 .operation_mode = "normal"; +defparam \IS.000 .output_mode = "reg_only"; +defparam \IS.000 .register_cascade_mode = "off"; +defparam \IS.000 .sum_lutc_input = "datac"; +defparam \IS.000 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X3_Y1_N3 +maxii_lcell \nRCS~2 ( +// Equation(s): +// \nRCS~2_combout = (\IS.111~regout & (LS[1] & (LS[0]))) # (!\IS.111~regout & (((\IS.000~regout )))) + + .clk(gnd), + .dataa(\IS.111~regout ), + .datab(LS[1]), + .datac(LS[0]), + .datad(\IS.000~regout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\nRCS~2_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \nRCS~2 .lut_mask = "d580"; +defparam \nRCS~2 .operation_mode = "normal"; +defparam \nRCS~2 .output_mode = "comb_only"; +defparam \nRCS~2 .register_cascade_mode = "off"; +defparam \nRCS~2 .sum_lutc_input = "datac"; +defparam \nRCS~2 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X6_Y1_N9 +maxii_lcell \Mux12~0 ( +// Equation(s): +// \Mux12~0_combout = (PS[1] & (((PS[0] & !\nRCS~2_combout )))) # (!PS[1] & (((PS[0])) # (!\nRCS~1 ))) + + .clk(gnd), + .dataa(PS[1]), + .datab(\nRCS~1 ), + .datac(PS[0]), + .datad(\nRCS~2_combout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Mux12~0_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Mux12~0 .lut_mask = "51f1"; +defparam \Mux12~0 .operation_mode = "normal"; +defparam \Mux12~0 .output_mode = "comb_only"; +defparam \Mux12~0 .register_cascade_mode = "off"; +defparam \Mux12~0 .sum_lutc_input = "datac"; +defparam \Mux12~0 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X6_Y1_N4 +maxii_lcell \nRCS~reg0 ( +// Equation(s): +// \nRCS~reg0_regout = DFFEAS((!PS[2] & ((PS[3] & ((!\Mux12~0_combout ))) # (!PS[3] & (!\Mux12~3_combout )))), GLOBAL(\C25M~combout ), VCC, , , , , , ) + + .clk(\C25M~combout ), + .dataa(\Mux12~3_combout ), + .datab(PS[3]), + .datac(PS[2]), + .datad(\Mux12~0_combout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\nRCS~reg0_regout ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \nRCS~reg0 .lut_mask = "010d"; +defparam \nRCS~reg0 .operation_mode = "normal"; +defparam \nRCS~reg0 .output_mode = "reg_only"; +defparam \nRCS~reg0 .register_cascade_mode = "off"; +defparam \nRCS~reg0 .sum_lutc_input = "datac"; +defparam \nRCS~reg0 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X7_Y2_N2 +maxii_lcell \nRAS~reg0 ( +// Equation(s): +// \nRAS~reg0_regout = DFFEAS((!PS[2] & ((PS[1] & (PS[3])) # (!PS[1] & (!PS[3] & PS[0])))), GLOBAL(\C25M~combout ), VCC, , , , , , ) + + .clk(\C25M~combout ), + .dataa(PS[1]), + .datab(PS[3]), + .datac(PS[2]), + .datad(PS[0]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\nRAS~reg0_regout ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \nRAS~reg0 .lut_mask = "0908"; +defparam \nRAS~reg0 .operation_mode = "normal"; +defparam \nRAS~reg0 .output_mode = "reg_only"; +defparam \nRAS~reg0 .register_cascade_mode = "off"; +defparam \nRAS~reg0 .sum_lutc_input = "datac"; +defparam \nRAS~reg0 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X7_Y2_N3 +maxii_lcell \nCAS~reg0 ( +// Equation(s): +// \nCAS~reg0_regout = DFFEAS((!PS[2] & ((PS[1] & (PS[3] $ (!PS[0]))) # (!PS[1] & (PS[3] & !PS[0])))), GLOBAL(\C25M~combout ), VCC, , , , , , ) + + .clk(\C25M~combout ), + .dataa(PS[1]), + .datab(PS[3]), + .datac(PS[2]), + .datad(PS[0]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\nCAS~reg0_regout ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \nCAS~reg0 .lut_mask = "0806"; +defparam \nCAS~reg0 .operation_mode = "normal"; +defparam \nCAS~reg0 .output_mode = "reg_only"; +defparam \nCAS~reg0 .register_cascade_mode = "off"; +defparam \nCAS~reg0 .sum_lutc_input = "datac"; +defparam \nCAS~reg0 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X2_Y4_N4 +maxii_lcell \Selector0~0 ( +// Equation(s): +// \Selector0~0_combout = (((!PS[1]) # (!\IS.001~regout ))) + + .clk(gnd), + .dataa(vcc), + .datab(vcc), + .datac(\IS.001~regout ), + .datad(PS[1]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Selector0~0_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Selector0~0 .lut_mask = "0fff"; +defparam \Selector0~0 .operation_mode = "normal"; +defparam \Selector0~0 .output_mode = "comb_only"; +defparam \Selector0~0 .register_cascade_mode = "off"; +defparam \Selector0~0 .sum_lutc_input = "datac"; +defparam \Selector0~0 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X2_Y4_N6 +maxii_lcell \nSWE~reg0 ( +// Equation(s): +// \nSWE~reg0_regout = DFFEAS((PS[3] & (!PS[2] & ((!PS[0]) # (!\Selector0~0_combout )))), GLOBAL(\C25M~combout ), VCC, , , , , , ) + + .clk(\C25M~combout ), + .dataa(\Selector0~0_combout ), + .datab(PS[3]), + .datac(PS[2]), + .datad(PS[0]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\nSWE~reg0_regout ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \nSWE~reg0 .lut_mask = "040c"; +defparam \nSWE~reg0 .operation_mode = "normal"; +defparam \nSWE~reg0 .output_mode = "reg_only"; +defparam \nSWE~reg0 .register_cascade_mode = "off"; +defparam \nSWE~reg0 .sum_lutc_input = "datac"; +defparam \nSWE~reg0 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X7_Y1_N1 +maxii_lcell \Equal1~1 ( +// Equation(s): +// \Equal1~1_combout = (!PS[0] & (((!PS[2])))) + + .clk(gnd), + .dataa(PS[0]), + .datab(vcc), + .datac(PS[2]), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Equal1~1_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Equal1~1 .lut_mask = "0505"; +defparam \Equal1~1 .operation_mode = "normal"; +defparam \Equal1~1 .output_mode = "comb_only"; +defparam \Equal1~1 .register_cascade_mode = "off"; +defparam \Equal1~1 .sum_lutc_input = "datac"; +defparam \Equal1~1 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X7_Y3_N1 +maxii_lcell \Selector1~0 ( +// Equation(s): +// \Selector1~0_combout = (PS[3] & ((LS[0]) # ((PS[1])))) # (!PS[3] & (((RAr[0]) # (!PS[1])))) + + .clk(gnd), + .dataa(PS[3]), + .datab(LS[0]), + .datac(RAr[0]), + .datad(PS[1]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Selector1~0_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Selector1~0 .lut_mask = "fadd"; +defparam \Selector1~0 .operation_mode = "normal"; +defparam \Selector1~0 .output_mode = "comb_only"; +defparam \Selector1~0 .register_cascade_mode = "off"; +defparam \Selector1~0 .sum_lutc_input = "datac"; +defparam \Selector1~0 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X7_Y3_N4 +maxii_lcell \DQMH~0 ( +// Equation(s): +// \DQMH~0_combout = (PS[1] & (((!PS[3] & \RAMSpecSEL~1_combout )))) # (!PS[1] & (!\IS.110~regout & (PS[3]))) + + .clk(gnd), + .dataa(PS[1]), + .datab(\IS.110~regout ), + .datac(PS[3]), + .datad(\RAMSpecSEL~1_combout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\DQMH~0_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \DQMH~0 .lut_mask = "1a10"; +defparam \DQMH~0 .operation_mode = "normal"; +defparam \DQMH~0 .output_mode = "comb_only"; +defparam \DQMH~0 .register_cascade_mode = "off"; +defparam \DQMH~0 .sum_lutc_input = "datac"; +defparam \DQMH~0 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X7_Y3_N9 +maxii_lcell \DQML~reg0 ( +// Equation(s): +// \DQML~reg0_regout = DFFEAS((\Equal1~1_combout & ((\DQMH~0_combout & ((!Addr[0]))) # (!\DQMH~0_combout & (!\Selector1~0_combout )))), GLOBAL(\C25M~combout ), VCC, , , , , , ) + + .clk(\C25M~combout ), + .dataa(\Equal1~1_combout ), + .datab(\Selector1~0_combout ), + .datac(\DQMH~0_combout ), + .datad(Addr[0]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\DQML~reg0_regout ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \DQML~reg0 .lut_mask = "02a2"; +defparam \DQML~reg0 .operation_mode = "normal"; +defparam \DQML~reg0 .output_mode = "reg_only"; +defparam \DQML~reg0 .register_cascade_mode = "off"; +defparam \DQML~reg0 .sum_lutc_input = "datac"; +defparam \DQML~reg0 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X7_Y3_N0 +maxii_lcell \Selector2~0 ( +// Equation(s): +// \Selector2~0_combout = (PS[3] & (((PS[1])) # (!LS[0]))) # (!PS[3] & (((!PS[1]) # (!RAr[0])))) + + .clk(gnd), + .dataa(PS[3]), + .datab(LS[0]), + .datac(RAr[0]), + .datad(PS[1]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Selector2~0_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Selector2~0 .lut_mask = "af77"; +defparam \Selector2~0 .operation_mode = "normal"; +defparam \Selector2~0 .output_mode = "comb_only"; +defparam \Selector2~0 .register_cascade_mode = "off"; +defparam \Selector2~0 .sum_lutc_input = "datac"; +defparam \Selector2~0 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X7_Y3_N5 +maxii_lcell \DQMH~reg0 ( +// Equation(s): +// \DQMH~reg0_regout = DFFEAS((\Equal1~1_combout & ((\DQMH~0_combout & (Addr[0])) # (!\DQMH~0_combout & ((!\Selector2~0_combout ))))), GLOBAL(\C25M~combout ), VCC, , , , , , ) + + .clk(\C25M~combout ), + .dataa(Addr[0]), + .datab(\Selector2~0_combout ), + .datac(\Equal1~1_combout ), + .datad(\DQMH~0_combout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\DQMH~reg0_regout ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \DQMH~reg0 .lut_mask = "a030"; +defparam \DQMH~reg0 .operation_mode = "normal"; +defparam \DQMH~reg0 .output_mode = "reg_only"; +defparam \DQMH~reg0 .register_cascade_mode = "off"; +defparam \DQMH~reg0 .sum_lutc_input = "datac"; +defparam \DQMH~reg0 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X6_Y1_N0 +maxii_lcell \Mux11~0 ( +// Equation(s): +// \Mux11~0_combout = (PS[3] & (PS[1] & (\nRCS~2_combout ))) # (!PS[3] & (((\Mux12~2_combout )))) + + .clk(gnd), + .dataa(PS[1]), + .datab(\nRCS~2_combout ), + .datac(PS[3]), + .datad(\Mux12~2_combout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Mux11~0_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Mux11~0 .lut_mask = "8f80"; +defparam \Mux11~0 .operation_mode = "normal"; +defparam \Mux11~0 .output_mode = "comb_only"; +defparam \Mux11~0 .register_cascade_mode = "off"; +defparam \Mux11~0 .sum_lutc_input = "datac"; +defparam \Mux11~0 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X6_Y1_N5 +maxii_lcell \Mux11~1 ( +// Equation(s): +// \Mux11~1_combout = (\nRCS~5_combout & ((PS[0]) # ((!PS[3] & \PS~0 )))) + + .clk(gnd), + .dataa(PS[3]), + .datab(\nRCS~5_combout ), + .datac(\PS~0 ), + .datad(PS[0]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Mux11~1_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Mux11~1 .lut_mask = "cc40"; +defparam \Mux11~1 .operation_mode = "normal"; +defparam \Mux11~1 .output_mode = "comb_only"; +defparam \Mux11~1 .register_cascade_mode = "off"; +defparam \Mux11~1 .sum_lutc_input = "datac"; +defparam \Mux11~1 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X6_Y1_N2 +maxii_lcell \Mux11~2 ( +// Equation(s): +// \Mux11~2_combout = (\Mux11~1_combout ) # ((PS[3] & ((\nRCS~1 ) # (PS[0])))) + + .clk(gnd), + .dataa(\Mux11~1_combout ), + .datab(\nRCS~1 ), + .datac(PS[3]), + .datad(PS[0]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Mux11~2_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Mux11~2 .lut_mask = "faea"; +defparam \Mux11~2 .operation_mode = "normal"; +defparam \Mux11~2 .output_mode = "comb_only"; +defparam \Mux11~2 .register_cascade_mode = "off"; +defparam \Mux11~2 .sum_lutc_input = "datac"; +defparam \Mux11~2 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X6_Y1_N3 +maxii_lcell \Mux11~3 ( +// Equation(s): +// \Mux11~3_combout = (!PS[2] & ((\Mux11~0_combout ) # ((!PS[1] & \Mux11~2_combout )))) + + .clk(gnd), + .dataa(PS[1]), + .datab(\Mux11~0_combout ), + .datac(PS[2]), + .datad(\Mux11~2_combout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Mux11~3_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Mux11~3 .lut_mask = "0d0c"; +defparam \Mux11~3 .operation_mode = "normal"; +defparam \Mux11~3 .output_mode = "comb_only"; +defparam \Mux11~3 .register_cascade_mode = "off"; +defparam \Mux11~3 .sum_lutc_input = "datac"; +defparam \Mux11~3 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X6_Y1_N7 +maxii_lcell \Equal2~0 ( +// Equation(s): +// \Equal2~0_combout = (PS[1] & (((PS[2] & PS[0])))) + + .clk(gnd), + .dataa(PS[1]), + .datab(vcc), + .datac(PS[2]), + .datad(PS[0]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Equal2~0_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Equal2~0 .lut_mask = "a000"; +defparam \Equal2~0 .operation_mode = "normal"; +defparam \Equal2~0 .output_mode = "comb_only"; +defparam \Equal2~0 .register_cascade_mode = "off"; +defparam \Equal2~0 .sum_lutc_input = "datac"; +defparam \Equal2~0 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X6_Y1_N8 +maxii_lcell \RCKE~reg0 ( +// Equation(s): +// \RCKE~reg0_regout = DFFEAS((!\Mux11~3_combout & (((PS[3]) # (!\Equal2~0_combout )) # (!\nRCS~1 ))), GLOBAL(\C25M~combout ), VCC, , , , , , ) + + .clk(\C25M~combout ), + .dataa(\Mux11~3_combout ), + .datab(\nRCS~1 ), + .datac(PS[3]), + .datad(\Equal2~0_combout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\RCKE~reg0_regout ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \RCKE~reg0 .lut_mask = "5155"; +defparam \RCKE~reg0 .operation_mode = "normal"; +defparam \RCKE~reg0 .output_mode = "reg_only"; +defparam \RCKE~reg0 .register_cascade_mode = "off"; +defparam \RCKE~reg0 .sum_lutc_input = "datac"; +defparam \RCKE~reg0 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X2_Y2_N1 +maxii_lcell \IS.101 ( +// Equation(s): +// \IS.101~regout = DFFEAS((!LS[2] & (\Equal5~0_combout & (!LS[0] & !LS[13]))), GLOBAL(\C25M~combout ), VCC, , \IS~19_combout , , , , ) + + .clk(\C25M~combout ), + .dataa(LS[2]), + .datab(\Equal5~0_combout ), + .datac(LS[0]), + .datad(LS[13]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\IS~19_combout ), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\IS.101~regout ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \IS.101 .lut_mask = "0004"; +defparam \IS.101 .operation_mode = "normal"; +defparam \IS.101 .output_mode = "reg_only"; +defparam \IS.101 .register_cascade_mode = "off"; +defparam \IS.101 .sum_lutc_input = "datac"; +defparam \IS.101 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X2_Y4_N9 +maxii_lcell FCS( +// Equation(s): +// \FCS~regout = DFFEAS((\IS.110~regout ) # ((\IS.100~regout ) # ((\IS.101~regout ))), GLOBAL(\C25M~combout ), VCC, , , , , , ) + + .clk(\C25M~combout ), + .dataa(\IS.110~regout ), + .datab(\IS.100~regout ), + .datac(\IS.101~regout ), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\FCS~regout ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam FCS.lut_mask = "fefe"; +defparam FCS.operation_mode = "normal"; +defparam FCS.output_mode = "reg_only"; +defparam FCS.register_cascade_mode = "off"; +defparam FCS.sum_lutc_input = "datac"; +defparam FCS.synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X3_Y1_N1 +maxii_lcell FCKOE( +// Equation(s): +// \FCKOE~regout = DFFEAS((((\IS.111~regout ) # (\IS.000~regout ))), GLOBAL(\C25M~combout ), VCC, , , , , , ) + + .clk(\C25M~combout ), + .dataa(vcc), + .datab(vcc), + .datac(\IS.111~regout ), + .datad(\IS.000~regout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\FCKOE~regout ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam FCKOE.lut_mask = "fff0"; +defparam FCKOE.operation_mode = "normal"; +defparam FCKOE.output_mode = "reg_only"; +defparam FCKOE.register_cascade_mode = "off"; +defparam FCKOE.sum_lutc_input = "datac"; +defparam FCKOE.synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X2_Y4_N2 +maxii_lcell FCKout( +// Equation(s): +// \FCKout~regout = DFFEAS(((!\IS.101~regout & ((PS[3]) # (!\IS.110~regout )))) # (!PS[0]), GLOBAL(\C25M~combout ), VCC, , , , , , ) + + .clk(\C25M~combout ), + .dataa(\IS.110~regout ), + .datab(PS[3]), + .datac(\IS.101~regout ), + .datad(PS[0]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\FCKout~regout ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam FCKout.lut_mask = "0dff"; +defparam FCKout.operation_mode = "normal"; +defparam FCKout.output_mode = "reg_only"; +defparam FCKout.register_cascade_mode = "off"; +defparam FCKout.sum_lutc_input = "datac"; +defparam FCKout.synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X5_Y4_N7 +maxii_lcell \RDD[1]~23 ( +// Equation(s): +// \RDD[1]~23_combout = (!RAr[3] & (\always9~0_combout & (!RAr[2] & !RAr[1]))) + + .clk(gnd), + .dataa(RAr[3]), + .datab(\always9~0_combout ), + .datac(RAr[2]), + .datad(RAr[1]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\RDD[1]~23_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \RDD[1]~23 .lut_mask = "0004"; +defparam \RDD[1]~23 .operation_mode = "normal"; +defparam \RDD[1]~23 .output_mode = "comb_only"; +defparam \RDD[1]~23 .register_cascade_mode = "off"; +defparam \RDD[1]~23 .sum_lutc_input = "datac"; +defparam \RDD[1]~23 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X4_Y3_N1 +maxii_lcell \RDD[1]~22 ( +// Equation(s): +// \RDD[1]~22_combout = (!RAr[3] & (!RAr[2] & (!RAr[0] & \always9~0_combout ))) + + .clk(gnd), + .dataa(RAr[3]), + .datab(RAr[2]), + .datac(RAr[0]), + .datad(\always9~0_combout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\RDD[1]~22_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \RDD[1]~22 .lut_mask = "0100"; +defparam \RDD[1]~22 .operation_mode = "normal"; +defparam \RDD[1]~22 .output_mode = "comb_only"; +defparam \RDD[1]~22 .register_cascade_mode = "off"; +defparam \RDD[1]~22 .sum_lutc_input = "datac"; +defparam \RDD[1]~22 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X5_Y3_N7 +maxii_lcell \RDD~4 ( +// Equation(s): +// \RDD~4_combout = (\RDD[1]~23_combout & ((Addr[8]) # ((\RDD[1]~22_combout )))) # (!\RDD[1]~23_combout & (((!\RDD[1]~22_combout & \SD[0]~0 )))) + + .clk(gnd), + .dataa(\RDD[1]~23_combout ), + .datab(Addr[8]), + .datac(\RDD[1]~22_combout ), + .datad(\SD[0]~0 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\RDD~4_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \RDD~4 .lut_mask = "ada8"; +defparam \RDD~4 .operation_mode = "normal"; +defparam \RDD~4 .output_mode = "comb_only"; +defparam \RDD~4 .register_cascade_mode = "off"; +defparam \RDD~4 .sum_lutc_input = "datac"; +defparam \RDD~4 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X2_Y4_N5 +maxii_lcell \Equal20~0 ( +// Equation(s): +// \Equal20~0_combout = (!PS[1] & (!PS[3] & (PS[2] & PS[0]))) + + .clk(gnd), + .dataa(PS[1]), + .datab(PS[3]), + .datac(PS[2]), + .datad(PS[0]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Equal20~0_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Equal20~0 .lut_mask = "1000"; +defparam \Equal20~0 .operation_mode = "normal"; +defparam \Equal20~0 .output_mode = "comb_only"; +defparam \Equal20~0 .register_cascade_mode = "off"; +defparam \Equal20~0 .sum_lutc_input = "datac"; +defparam \Equal20~0 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X5_Y3_N4 +maxii_lcell \RDD[0] ( +// Equation(s): +// RDD[0] = DFFEAS((\RDD~4_combout & ((Addr[0]) # ((!\RDD[1]~22_combout )))) # (!\RDD~4_combout & (((\RDD[1]~22_combout & Addr[16])))), !GLOBAL(\C25M~combout ), VCC, , \Equal20~0_combout , , , , ) + + .clk(!\C25M~combout ), + .dataa(Addr[0]), + .datab(\RDD~4_combout ), + .datac(\RDD[1]~22_combout ), + .datad(Addr[16]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal20~0_combout ), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(RDD[0]), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \RDD[0] .lut_mask = "bc8c"; +defparam \RDD[0] .operation_mode = "normal"; +defparam \RDD[0] .output_mode = "reg_only"; +defparam \RDD[0] .register_cascade_mode = "off"; +defparam \RDD[0] .sum_lutc_input = "datac"; +defparam \RDD[0] .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X5_Y3_N1 +maxii_lcell \RDD~6 ( +// Equation(s): +// \RDD~6_combout = (\RDD[1]~23_combout & ((Addr[9]) # ((\RDD[1]~22_combout )))) # (!\RDD[1]~23_combout & (((!\RDD[1]~22_combout & \SD[1]~1 )))) + + .clk(gnd), + .dataa(\RDD[1]~23_combout ), + .datab(Addr[9]), + .datac(\RDD[1]~22_combout ), + .datad(\SD[1]~1 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\RDD~6_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \RDD~6 .lut_mask = "ada8"; +defparam \RDD~6 .operation_mode = "normal"; +defparam \RDD~6 .output_mode = "comb_only"; +defparam \RDD~6 .register_cascade_mode = "off"; +defparam \RDD~6 .sum_lutc_input = "datac"; +defparam \RDD~6 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X5_Y3_N2 +maxii_lcell \RDD[1] ( +// Equation(s): +// RDD[1] = DFFEAS((\RDD[1]~22_combout & ((\RDD~6_combout & ((Addr[1]))) # (!\RDD~6_combout & (Addr[17])))) # (!\RDD[1]~22_combout & (\RDD~6_combout )), !GLOBAL(\C25M~combout ), VCC, , \Equal20~0_combout , , , , ) + + .clk(!\C25M~combout ), + .dataa(\RDD[1]~22_combout ), + .datab(\RDD~6_combout ), + .datac(Addr[17]), + .datad(Addr[1]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal20~0_combout ), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(RDD[1]), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \RDD[1] .lut_mask = "ec64"; +defparam \RDD[1] .operation_mode = "normal"; +defparam \RDD[1] .output_mode = "reg_only"; +defparam \RDD[1] .register_cascade_mode = "off"; +defparam \RDD[1] .sum_lutc_input = "datac"; +defparam \RDD[1] .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X5_Y3_N9 +maxii_lcell \RDD~8 ( +// Equation(s): +// \RDD~8_combout = (\RDD[1]~23_combout & (((\RDD[1]~22_combout ) # (Addr[10])))) # (!\RDD[1]~23_combout & (\SD[2]~2 & (!\RDD[1]~22_combout ))) + + .clk(gnd), + .dataa(\RDD[1]~23_combout ), + .datab(\SD[2]~2 ), + .datac(\RDD[1]~22_combout ), + .datad(Addr[10]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\RDD~8_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \RDD~8 .lut_mask = "aea4"; +defparam \RDD~8 .operation_mode = "normal"; +defparam \RDD~8 .output_mode = "comb_only"; +defparam \RDD~8 .register_cascade_mode = "off"; +defparam \RDD~8 .sum_lutc_input = "datac"; +defparam \RDD~8 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X5_Y3_N0 +maxii_lcell \RDD[2] ( +// Equation(s): +// RDD[2] = DFFEAS((\RDD[1]~22_combout & ((\RDD~8_combout & (Addr[2])) # (!\RDD~8_combout & ((Addr[18]))))) # (!\RDD[1]~22_combout & (\RDD~8_combout )), !GLOBAL(\C25M~combout ), VCC, , \Equal20~0_combout , , , , ) + + .clk(!\C25M~combout ), + .dataa(\RDD[1]~22_combout ), + .datab(\RDD~8_combout ), + .datac(Addr[2]), + .datad(Addr[18]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal20~0_combout ), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(RDD[2]), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \RDD[2] .lut_mask = "e6c4"; +defparam \RDD[2] .operation_mode = "normal"; +defparam \RDD[2] .output_mode = "reg_only"; +defparam \RDD[2] .register_cascade_mode = "off"; +defparam \RDD[2] .sum_lutc_input = "datac"; +defparam \RDD[2] .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X5_Y3_N8 +maxii_lcell \RDD~10 ( +// Equation(s): +// \RDD~10_combout = (\RDD[1]~22_combout & (((\RDD[1]~23_combout )))) # (!\RDD[1]~22_combout & ((\RDD[1]~23_combout & (Addr[11])) # (!\RDD[1]~23_combout & ((\SD[3]~3 ))))) + + .clk(gnd), + .dataa(\RDD[1]~22_combout ), + .datab(Addr[11]), + .datac(\RDD[1]~23_combout ), + .datad(\SD[3]~3 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\RDD~10_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \RDD~10 .lut_mask = "e5e0"; +defparam \RDD~10 .operation_mode = "normal"; +defparam \RDD~10 .output_mode = "comb_only"; +defparam \RDD~10 .register_cascade_mode = "off"; +defparam \RDD~10 .sum_lutc_input = "datac"; +defparam \RDD~10 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X5_Y3_N5 +maxii_lcell \RDD[3] ( +// Equation(s): +// RDD[3] = DFFEAS((\RDD[1]~22_combout & ((\RDD~10_combout & (Addr[3])) # (!\RDD~10_combout & ((Addr[19]))))) # (!\RDD[1]~22_combout & (((\RDD~10_combout )))), !GLOBAL(\C25M~combout ), VCC, , \Equal20~0_combout , , , , ) + + .clk(!\C25M~combout ), + .dataa(Addr[3]), + .datab(Addr[19]), + .datac(\RDD[1]~22_combout ), + .datad(\RDD~10_combout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal20~0_combout ), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(RDD[3]), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \RDD[3] .lut_mask = "afc0"; +defparam \RDD[3] .operation_mode = "normal"; +defparam \RDD[3] .output_mode = "reg_only"; +defparam \RDD[3] .register_cascade_mode = "off"; +defparam \RDD[3] .sum_lutc_input = "datac"; +defparam \RDD[3] .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X5_Y4_N4 +maxii_lcell \RDD[4]~12 ( +// Equation(s): +// \RDD[4]~12_combout = ((RAr[0] $ (!RAr[1])) # (!\always9~0_combout )) # (!\RAMRegSpecSEL~1 ) + + .clk(gnd), + .dataa(\RAMRegSpecSEL~1 ), + .datab(\always9~0_combout ), + .datac(RAr[0]), + .datad(RAr[1]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\RDD[4]~12_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \RDD[4]~12 .lut_mask = "f77f"; +defparam \RDD[4]~12 .operation_mode = "normal"; +defparam \RDD[4]~12 .output_mode = "comb_only"; +defparam \RDD[4]~12 .register_cascade_mode = "off"; +defparam \RDD[4]~12 .sum_lutc_input = "datac"; +defparam \RDD[4]~12 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X5_Y4_N8 +maxii_lcell \RDD~14 ( +// Equation(s): +// \RDD~14_combout = (\RDD[4]~12_combout & (((Addr[4] & \RDD[1]~23_combout )))) # (!\RDD[4]~12_combout & ((Addr[12]) # ((!\RDD[1]~23_combout )))) + + .clk(gnd), + .dataa(\RDD[4]~12_combout ), + .datab(Addr[12]), + .datac(Addr[4]), + .datad(\RDD[1]~23_combout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\RDD~14_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \RDD~14 .lut_mask = "e455"; +defparam \RDD~14 .operation_mode = "normal"; +defparam \RDD~14 .output_mode = "comb_only"; +defparam \RDD~14 .register_cascade_mode = "off"; +defparam \RDD~14 .sum_lutc_input = "datac"; +defparam \RDD~14 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X5_Y4_N9 +maxii_lcell \RDD[4]~13 ( +// Equation(s): +// \RDD[4]~13_combout = (!\RDD[1]~23_combout & ((\RDD[4]~12_combout ) # ((!SetFWr[1])))) + + .clk(gnd), + .dataa(\RDD[4]~12_combout ), + .datab(\RDD[1]~23_combout ), + .datac(SetFWr[1]), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\RDD[4]~13_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \RDD[4]~13 .lut_mask = "2323"; +defparam \RDD[4]~13 .operation_mode = "normal"; +defparam \RDD[4]~13 .output_mode = "comb_only"; +defparam \RDD[4]~13 .register_cascade_mode = "off"; +defparam \RDD[4]~13 .sum_lutc_input = "datac"; +defparam \RDD[4]~13 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X5_Y4_N5 +maxii_lcell \RDD[4] ( +// Equation(s): +// RDD[4] = DFFEAS((\RDD~14_combout & (((Addr[20])) # (!\RDD[4]~13_combout ))) # (!\RDD~14_combout & (\RDD[4]~13_combout & (\SD[4]~4 ))), !GLOBAL(\C25M~combout ), VCC, , \Equal20~0_combout , , , , ) + + .clk(!\C25M~combout ), + .dataa(\RDD~14_combout ), + .datab(\RDD[4]~13_combout ), + .datac(\SD[4]~4 ), + .datad(Addr[20]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal20~0_combout ), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(RDD[4]), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \RDD[4] .lut_mask = "ea62"; +defparam \RDD[4] .operation_mode = "normal"; +defparam \RDD[4] .output_mode = "reg_only"; +defparam \RDD[4] .register_cascade_mode = "off"; +defparam \RDD[4] .sum_lutc_input = "datac"; +defparam \RDD[4] .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X5_Y4_N0 +maxii_lcell \RDD~16 ( +// Equation(s): +// \RDD~16_combout = (\RDD[4]~12_combout & (\RDD[1]~23_combout & ((Addr[5])))) # (!\RDD[4]~12_combout & (((Addr[13])) # (!\RDD[1]~23_combout ))) + + .clk(gnd), + .dataa(\RDD[4]~12_combout ), + .datab(\RDD[1]~23_combout ), + .datac(Addr[13]), + .datad(Addr[5]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\RDD~16_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \RDD~16 .lut_mask = "d951"; +defparam \RDD~16 .operation_mode = "normal"; +defparam \RDD~16 .output_mode = "comb_only"; +defparam \RDD~16 .register_cascade_mode = "off"; +defparam \RDD~16 .sum_lutc_input = "datac"; +defparam \RDD~16 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X5_Y4_N1 +maxii_lcell \RDD[5] ( +// Equation(s): +// RDD[5] = DFFEAS((\RDD[4]~13_combout & ((\RDD~16_combout & ((Addr[21]))) # (!\RDD~16_combout & (\SD[5]~5 )))) # (!\RDD[4]~13_combout & (((\RDD~16_combout )))), !GLOBAL(\C25M~combout ), VCC, , \Equal20~0_combout , , , , ) + + .clk(!\C25M~combout ), + .dataa(\SD[5]~5 ), + .datab(\RDD[4]~13_combout ), + .datac(Addr[21]), + .datad(\RDD~16_combout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal20~0_combout ), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(RDD[5]), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \RDD[5] .lut_mask = "f388"; +defparam \RDD[5] .operation_mode = "normal"; +defparam \RDD[5] .output_mode = "reg_only"; +defparam \RDD[5] .register_cascade_mode = "off"; +defparam \RDD[5] .sum_lutc_input = "datac"; +defparam \RDD[5] .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X5_Y4_N6 +maxii_lcell \RDD~18 ( +// Equation(s): +// \RDD~18_combout = (\RDD[1]~23_combout & ((\RDD[4]~12_combout & ((Addr[6]))) # (!\RDD[4]~12_combout & (Addr[14])))) # (!\RDD[1]~23_combout & (((!\RDD[4]~12_combout )))) + + .clk(gnd), + .dataa(Addr[14]), + .datab(\RDD[1]~23_combout ), + .datac(\RDD[4]~12_combout ), + .datad(Addr[6]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\RDD~18_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \RDD~18 .lut_mask = "cb0b"; +defparam \RDD~18 .operation_mode = "normal"; +defparam \RDD~18 .output_mode = "comb_only"; +defparam \RDD~18 .register_cascade_mode = "off"; +defparam \RDD~18 .sum_lutc_input = "datac"; +defparam \RDD~18 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X5_Y4_N2 +maxii_lcell \RDD[6] ( +// Equation(s): +// RDD[6] = DFFEAS((\RDD[4]~13_combout & ((\RDD~18_combout & (Addr[22])) # (!\RDD~18_combout & ((\SD[6]~6 ))))) # (!\RDD[4]~13_combout & (((\RDD~18_combout )))), !GLOBAL(\C25M~combout ), VCC, , \Equal20~0_combout , , , , ) + + .clk(!\C25M~combout ), + .dataa(Addr[22]), + .datab(\RDD[4]~13_combout ), + .datac(\RDD~18_combout ), + .datad(\SD[6]~6 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal20~0_combout ), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(RDD[6]), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \RDD[6] .lut_mask = "bcb0"; +defparam \RDD[6] .operation_mode = "normal"; +defparam \RDD[6] .output_mode = "reg_only"; +defparam \RDD[6] .register_cascade_mode = "off"; +defparam \RDD[6] .sum_lutc_input = "datac"; +defparam \RDD[6] .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X6_Y4_N0 +maxii_lcell \RDD~20 ( +// Equation(s): +// \RDD~20_combout = (\RDD[4]~12_combout & (Addr[7] & ((\RDD[1]~23_combout )))) # (!\RDD[4]~12_combout & (((Addr[15]) # (!\RDD[1]~23_combout )))) + + .clk(gnd), + .dataa(Addr[7]), + .datab(\RDD[4]~12_combout ), + .datac(Addr[15]), + .datad(\RDD[1]~23_combout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\RDD~20_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \RDD~20 .lut_mask = "b833"; +defparam \RDD~20 .operation_mode = "normal"; +defparam \RDD~20 .output_mode = "comb_only"; +defparam \RDD~20 .register_cascade_mode = "off"; +defparam \RDD~20 .sum_lutc_input = "datac"; +defparam \RDD~20 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X5_Y4_N3 +maxii_lcell \RDD[7] ( +// Equation(s): +// RDD[7] = DFFEAS((\RDD~20_combout & (((Addr[23]) # (!\RDD[4]~13_combout )))) # (!\RDD~20_combout & (\SD[7]~7 & ((\RDD[4]~13_combout )))), !GLOBAL(\C25M~combout ), VCC, , \Equal20~0_combout , , , , ) + + .clk(!\C25M~combout ), + .dataa(\RDD~20_combout ), + .datab(\SD[7]~7 ), + .datac(Addr[23]), + .datad(\RDD[4]~13_combout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal20~0_combout ), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(RDD[7]), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \RDD[7] .lut_mask = "e4aa"; +defparam \RDD[7] .operation_mode = "normal"; +defparam \RDD[7] .output_mode = "reg_only"; +defparam \RDD[7] .register_cascade_mode = "off"; +defparam \RDD[7] .sum_lutc_input = "datac"; +defparam \RDD[7] .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X7_Y1_N6 +maxii_lcell \WRD[0] ( +// Equation(s): +// WRD[0] = DFFEAS((\IS.110~regout & (\MOSI~0 )) # (!\IS.110~regout & (((\RD[0]~0 )))), GLOBAL(\C25M~combout ), VCC, , , WRD[0], , , PS[0]) + + .clk(\C25M~combout ), + .dataa(\IS.110~regout ), + .datab(\MOSI~0 ), + .datac(WRD[0]), + .datad(\RD[0]~0 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(PS[0]), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(WRD[0]), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \WRD[0] .lut_mask = "dd88"; +defparam \WRD[0] .operation_mode = "normal"; +defparam \WRD[0] .output_mode = "reg_only"; +defparam \WRD[0] .register_cascade_mode = "off"; +defparam \WRD[0] .sum_lutc_input = "datac"; +defparam \WRD[0] .synch_mode = "on"; +// synopsys translate_on + +// Location: LC_X5_Y1_N4 +maxii_lcell SDOE( +// Equation(s): +// \SDOE~regout = DFFEAS((((\Equal19~0_combout & \nRCS~1 ))), GLOBAL(\C25M~combout ), VCC, , , , , , ) + + .clk(\C25M~combout ), + .dataa(vcc), + .datab(vcc), + .datac(\Equal19~0_combout ), + .datad(\nRCS~1 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\SDOE~regout ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam SDOE.lut_mask = "f000"; +defparam SDOE.operation_mode = "normal"; +defparam SDOE.output_mode = "reg_only"; +defparam SDOE.register_cascade_mode = "off"; +defparam SDOE.sum_lutc_input = "datac"; +defparam SDOE.synch_mode = "off"; +// synopsys translate_on + +// Location: PIN_16, I/O Standard: 3.3-V LVTTL, Current Strength: Default +maxii_io \MISO~I ( + .datain(gnd), + .oe(gnd), + .combout(\MISO~combout ), + .padio(MISO)); +// synopsys translate_off +defparam \MISO~I .bus_hold = "true"; +defparam \MISO~I .operation_mode = "input"; +// synopsys translate_on + +// Location: LC_X7_Y1_N7 +maxii_lcell \WRD[1] ( +// Equation(s): +// WRD[1] = DFFEAS((\IS.110~regout & (\MISO~combout )) # (!\IS.110~regout & (((\RD[1]~1 )))), GLOBAL(\C25M~combout ), VCC, , , WRD[1], , , PS[0]) + + .clk(\C25M~combout ), + .dataa(\IS.110~regout ), + .datab(\MISO~combout ), + .datac(WRD[1]), + .datad(\RD[1]~1 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(PS[0]), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(WRD[1]), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \WRD[1] .lut_mask = "dd88"; +defparam \WRD[1] .operation_mode = "normal"; +defparam \WRD[1] .output_mode = "reg_only"; +defparam \WRD[1] .register_cascade_mode = "off"; +defparam \WRD[1] .sum_lutc_input = "datac"; +defparam \WRD[1] .synch_mode = "on"; +// synopsys translate_on + +// Location: LC_X7_Y1_N2 +maxii_lcell \WRD[2] ( +// Equation(s): +// WRD[2] = DFFEAS(((\IS.110~regout & (WRD[0])) # (!\IS.110~regout & ((\RD[2]~2 )))), GLOBAL(\C25M~combout ), VCC, , , WRD[2], , , PS[0]) + + .clk(\C25M~combout ), + .dataa(WRD[0]), + .datab(\RD[2]~2 ), + .datac(WRD[2]), + .datad(\IS.110~regout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(PS[0]), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(WRD[2]), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \WRD[2] .lut_mask = "aacc"; +defparam \WRD[2] .operation_mode = "normal"; +defparam \WRD[2] .output_mode = "reg_only"; +defparam \WRD[2] .register_cascade_mode = "off"; +defparam \WRD[2] .sum_lutc_input = "datac"; +defparam \WRD[2] .synch_mode = "on"; +// synopsys translate_on + +// Location: LC_X7_Y1_N3 +maxii_lcell \WRD[3] ( +// Equation(s): +// WRD[3] = DFFEAS(((\IS.110~regout & (WRD[1])) # (!\IS.110~regout & ((\RD[3]~3 )))), GLOBAL(\C25M~combout ), VCC, , , WRD[3], , , PS[0]) + + .clk(\C25M~combout ), + .dataa(WRD[1]), + .datab(\RD[3]~3 ), + .datac(WRD[3]), + .datad(\IS.110~regout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(PS[0]), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(WRD[3]), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \WRD[3] .lut_mask = "aacc"; +defparam \WRD[3] .operation_mode = "normal"; +defparam \WRD[3] .output_mode = "reg_only"; +defparam \WRD[3] .register_cascade_mode = "off"; +defparam \WRD[3] .sum_lutc_input = "datac"; +defparam \WRD[3] .synch_mode = "on"; +// synopsys translate_on + +// Location: LC_X7_Y1_N5 +maxii_lcell \WRD[4] ( +// Equation(s): +// WRD[4] = DFFEAS((\IS.110~regout & (((WRD[2])))) # (!\IS.110~regout & (\RD[4]~4 )), GLOBAL(\C25M~combout ), VCC, , , WRD[4], , , PS[0]) + + .clk(\C25M~combout ), + .dataa(\IS.110~regout ), + .datab(\RD[4]~4 ), + .datac(WRD[4]), + .datad(WRD[2]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(PS[0]), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(WRD[4]), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \WRD[4] .lut_mask = "ee44"; +defparam \WRD[4] .operation_mode = "normal"; +defparam \WRD[4] .output_mode = "reg_only"; +defparam \WRD[4] .register_cascade_mode = "off"; +defparam \WRD[4] .sum_lutc_input = "datac"; +defparam \WRD[4] .synch_mode = "on"; +// synopsys translate_on + +// Location: LC_X7_Y1_N8 +maxii_lcell \WRD[5] ( +// Equation(s): +// WRD[5] = DFFEAS((\IS.110~regout & (((WRD[3])))) # (!\IS.110~regout & (\RD[5]~5 )), GLOBAL(\C25M~combout ), VCC, , , WRD[5], , , PS[0]) + + .clk(\C25M~combout ), + .dataa(\IS.110~regout ), + .datab(\RD[5]~5 ), + .datac(WRD[5]), + .datad(WRD[3]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(PS[0]), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(WRD[5]), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \WRD[5] .lut_mask = "ee44"; +defparam \WRD[5] .operation_mode = "normal"; +defparam \WRD[5] .output_mode = "reg_only"; +defparam \WRD[5] .register_cascade_mode = "off"; +defparam \WRD[5] .sum_lutc_input = "datac"; +defparam \WRD[5] .synch_mode = "on"; +// synopsys translate_on + +// Location: LC_X7_Y1_N9 +maxii_lcell \WRD[6] ( +// Equation(s): +// WRD[6] = DFFEAS(((\IS.110~regout & (WRD[4])) # (!\IS.110~regout & ((\RD[6]~6 )))), GLOBAL(\C25M~combout ), VCC, , , WRD[6], , , PS[0]) + + .clk(\C25M~combout ), + .dataa(WRD[4]), + .datab(\RD[6]~6 ), + .datac(WRD[6]), + .datad(\IS.110~regout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(PS[0]), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(WRD[6]), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \WRD[6] .lut_mask = "aacc"; +defparam \WRD[6] .operation_mode = "normal"; +defparam \WRD[6] .output_mode = "reg_only"; +defparam \WRD[6] .register_cascade_mode = "off"; +defparam \WRD[6] .sum_lutc_input = "datac"; +defparam \WRD[6] .synch_mode = "on"; +// synopsys translate_on + +// Location: LC_X7_Y1_N4 +maxii_lcell \WRD[7] ( +// Equation(s): +// WRD[7] = DFFEAS((\IS.110~regout & (((WRD[5])))) # (!\IS.110~regout & (\RD[7]~7 )), GLOBAL(\C25M~combout ), VCC, , , WRD[7], , , PS[0]) + + .clk(\C25M~combout ), + .dataa(\IS.110~regout ), + .datab(\RD[7]~7 ), + .datac(WRD[7]), + .datad(WRD[5]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(PS[0]), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(WRD[7]), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \WRD[7] .lut_mask = "ee44"; +defparam \WRD[7] .operation_mode = "normal"; +defparam \WRD[7] .output_mode = "reg_only"; +defparam \WRD[7] .register_cascade_mode = "off"; +defparam \WRD[7] .sum_lutc_input = "datac"; +defparam \WRD[7] .synch_mode = "on"; +// synopsys translate_on + +// Location: LC_X4_Y2_N2 +maxii_lcell \Mux2~0 ( +// Equation(s): +// \Mux2~0_combout = (LS[1] & (!PS[1] & ((!LS[2])))) # (!LS[1] & (PS[1] & (!SetFWr[1] & LS[2]))) + + .clk(gnd), + .dataa(LS[1]), + .datab(PS[1]), + .datac(SetFWr[1]), + .datad(LS[2]), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Mux2~0_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Mux2~0 .lut_mask = "0422"; +defparam \Mux2~0 .operation_mode = "normal"; +defparam \Mux2~0 .output_mode = "comb_only"; +defparam \Mux2~0 .register_cascade_mode = "off"; +defparam \Mux2~0 .sum_lutc_input = "datac"; +defparam \Mux2~0 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X2_Y1_N8 +maxii_lcell \Mux2~1 ( +// Equation(s): +// \Mux2~1_combout = (((LS[0] & \Mux2~0_combout ))) + + .clk(gnd), + .dataa(vcc), + .datab(vcc), + .datac(LS[0]), + .datad(\Mux2~0_combout ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Mux2~1_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Mux2~1 .lut_mask = "f000"; +defparam \Mux2~1 .operation_mode = "normal"; +defparam \Mux2~1 .output_mode = "comb_only"; +defparam \Mux2~1 .register_cascade_mode = "off"; +defparam \Mux2~1 .sum_lutc_input = "datac"; +defparam \Mux2~1 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X2_Y1_N9 +maxii_lcell \Mux2~3 ( +// Equation(s): +// \Mux2~3_combout = (((LS[0] & \Mux2~2 ))) + + .clk(gnd), + .dataa(vcc), + .datab(vcc), + .datac(LS[0]), + .datad(\Mux2~2 ), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\Mux2~3_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \Mux2~3 .lut_mask = "f000"; +defparam \Mux2~3 .operation_mode = "normal"; +defparam \Mux2~3 .output_mode = "comb_only"; +defparam \Mux2~3 .register_cascade_mode = "off"; +defparam \Mux2~3 .sum_lutc_input = "datac"; +defparam \Mux2~3 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X2_Y1_N6 +maxii_lcell \SA[1]~14 ( +// Equation(s): +// \SA[1]~14_combout = PS[3] $ ((((PS[1])))) + + .clk(gnd), + .dataa(PS[3]), + .datab(vcc), + .datac(PS[1]), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(\SA[1]~14_combout ), + .regout(), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam \SA[1]~14 .lut_mask = "5a5a"; +defparam \SA[1]~14 .operation_mode = "normal"; +defparam \SA[1]~14 .output_mode = "comb_only"; +defparam \SA[1]~14 .register_cascade_mode = "off"; +defparam \SA[1]~14 .sum_lutc_input = "datac"; +defparam \SA[1]~14 .synch_mode = "off"; +// synopsys translate_on + +// Location: LC_X2_Y1_N4 +maxii_lcell MOSIout( +// Equation(s): +// \MOSIout~regout = DFFEAS((PS[2] & (((\Mux2~3_combout )))) # (!PS[2] & (\Mux2~1_combout & ((\SA[1]~14_combout )))), GLOBAL(\C25M~combout ), VCC, , PS[0], , , !PS[0], ) + + .clk(\C25M~combout ), + .dataa(\Mux2~1_combout ), + .datab(\Mux2~3_combout ), + .datac(\SA[1]~14_combout ), + .datad(PS[2]), + .aclr(gnd), + .aload(gnd), + .sclr(!PS[0]), + .sload(gnd), + .ena(PS[0]), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\MOSIout~regout ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam MOSIout.lut_mask = "cca0"; +defparam MOSIout.operation_mode = "normal"; +defparam MOSIout.output_mode = "reg_only"; +defparam MOSIout.register_cascade_mode = "off"; +defparam MOSIout.sum_lutc_input = "datac"; +defparam MOSIout.synch_mode = "on"; +// synopsys translate_on + +// Location: LC_X2_Y2_N8 +maxii_lcell MOSIOE( +// Equation(s): +// \MOSIOE~regout = DFFEAS(GND, GLOBAL(\C25M~combout ), VCC, , , \IS.101~regout , , , VCC) + + .clk(\C25M~combout ), + .dataa(vcc), + .datab(vcc), + .datac(\IS.101~regout ), + .datad(vcc), + .aclr(gnd), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .cin(gnd), + .cin0(gnd), + .cin1(vcc), + .inverta(gnd), + .regcascin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .combout(), + .regout(\MOSIOE~regout ), + .cout(), + .cout0(), + .cout1()); +// synopsys translate_off +defparam MOSIOE.lut_mask = "0000"; +defparam MOSIOE.operation_mode = "normal"; +defparam MOSIOE.output_mode = "reg_only"; +defparam MOSIOE.register_cascade_mode = "off"; +defparam MOSIOE.sum_lutc_input = "datac"; +defparam MOSIOE.synch_mode = "on"; +// synopsys translate_on + +// Location: PIN_30, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +maxii_io \nRESout~I ( + .datain(\nRESout~reg0_regout ), + .oe(vcc), + .combout(), + .padio(nRESout)); +// synopsys translate_off +defparam \nRESout~I .operation_mode = "output"; +// synopsys translate_on + +// Location: PIN_20, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA +maxii_io \INTout~I ( + .datain(\INTin~combout ), + .oe(vcc), + .combout(), + .padio(INTout)); +// synopsys translate_off +defparam \INTout~I .operation_mode = "output"; +// synopsys translate_on + +// Location: PIN_18, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA +maxii_io \DMAout~I ( + .datain(\DMAin~combout ), + .oe(vcc), + .combout(), + .padio(DMAout)); +// synopsys translate_off +defparam \DMAout~I .operation_mode = "output"; +// synopsys translate_on + +// Location: PIN_26, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA +maxii_io \nNMIout~I ( + .datain(vcc), + .oe(vcc), + .combout(), + .padio(nNMIout)); +// synopsys translate_off +defparam \nNMIout~I .operation_mode = "output"; +// synopsys translate_on + +// Location: PIN_29, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA +maxii_io \nIRQout~I ( + .datain(vcc), + .oe(vcc), + .combout(), + .padio(nIRQout)); +// synopsys translate_off +defparam \nIRQout~I .operation_mode = "output"; +// synopsys translate_on + +// Location: PIN_28, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA +maxii_io \nRDYout~I ( + .datain(vcc), + .oe(vcc), + .combout(), + .padio(nRDYout)); +// synopsys translate_off +defparam \nRDYout~I .operation_mode = "output"; +// synopsys translate_on + +// Location: PIN_27, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA +maxii_io \nINHout~I ( + .datain(vcc), + .oe(vcc), + .combout(), + .padio(nINHout)); +// synopsys translate_off +defparam \nINHout~I .operation_mode = "output"; +// synopsys translate_on + +// Location: PIN_33, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA +maxii_io \RWout~I ( + .datain(vcc), + .oe(vcc), + .combout(), + .padio(RWout)); +// synopsys translate_off +defparam \RWout~I .operation_mode = "output"; +// synopsys translate_on + +// Location: PIN_21, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA +maxii_io \nDMAout~I ( + .datain(vcc), + .oe(vcc), + .combout(), + .padio(nDMAout)); +// synopsys translate_off +defparam \nDMAout~I .operation_mode = "output"; +// synopsys translate_on + +// Location: PIN_19, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +maxii_io \RAdir~I ( + .datain(vcc), + .oe(vcc), + .combout(), + .padio(RAdir)); +// synopsys translate_off +defparam \RAdir~I .operation_mode = "output"; +// synopsys translate_on + +// Location: PIN_17, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +maxii_io \RDdir~I ( + .datain(!\comb~2_combout ), + .oe(vcc), + .combout(), + .padio(RDdir)); +// synopsys translate_off +defparam \RDdir~I .operation_mode = "output"; +// synopsys translate_on + +// Location: PIN_69, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +maxii_io \SBA[0]~I ( + .datain(\SBA[0]~reg0_regout ), + .oe(vcc), + .combout(), + .padio(SBA[0])); +// synopsys translate_off +defparam \SBA[0]~I .operation_mode = "output"; +// synopsys translate_on + +// Location: PIN_71, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +maxii_io \SBA[1]~I ( + .datain(\SBA[1]~reg0_regout ), + .oe(vcc), + .combout(), + .padio(SBA[1])); +// synopsys translate_off +defparam \SBA[1]~I .operation_mode = "output"; +// synopsys translate_on + +// Location: PIN_75, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +maxii_io \SA[0]~I ( + .datain(\SA[0]~reg0_regout ), + .oe(vcc), + .combout(), + .padio(SA[0])); +// synopsys translate_off +defparam \SA[0]~I .operation_mode = "output"; +// synopsys translate_on + +// Location: PIN_81, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +maxii_io \SA[1]~I ( + .datain(\SA[1]~reg0_regout ), + .oe(vcc), + .combout(), + .padio(SA[1])); +// synopsys translate_off +defparam \SA[1]~I .operation_mode = "output"; +// synopsys translate_on + +// Location: PIN_82, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +maxii_io \SA[2]~I ( + .datain(\SA[2]~reg0_regout ), + .oe(vcc), + .combout(), + .padio(SA[2])); +// synopsys translate_off +defparam \SA[2]~I .operation_mode = "output"; +// synopsys translate_on + +// Location: PIN_84, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +maxii_io \SA[3]~I ( + .datain(\SA[3]~reg0_regout ), + .oe(vcc), + .combout(), + .padio(SA[3])); +// synopsys translate_off +defparam \SA[3]~I .operation_mode = "output"; +// synopsys translate_on + +// Location: PIN_76, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +maxii_io \SA[4]~I ( + .datain(\SA[4]~reg0_regout ), + .oe(vcc), + .combout(), + .padio(SA[4])); +// synopsys translate_off +defparam \SA[4]~I .operation_mode = "output"; +// synopsys translate_on + +// Location: PIN_83, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +maxii_io \SA[5]~I ( + .datain(\SA[5]~reg0_regout ), + .oe(vcc), + .combout(), + .padio(SA[5])); +// synopsys translate_off +defparam \SA[5]~I .operation_mode = "output"; +// synopsys translate_on + +// Location: PIN_77, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +maxii_io \SA[6]~I ( + .datain(\SA[6]~reg0_regout ), + .oe(vcc), + .combout(), + .padio(SA[6])); +// synopsys translate_off +defparam \SA[6]~I .operation_mode = "output"; +// synopsys translate_on + +// Location: PIN_78, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +maxii_io \SA[7]~I ( + .datain(\SA[7]~reg0_regout ), + .oe(vcc), + .combout(), + .padio(SA[7])); +// synopsys translate_off +defparam \SA[7]~I .operation_mode = "output"; +// synopsys translate_on + +// Location: PIN_74, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +maxii_io \SA[8]~I ( + .datain(\SA[8]~reg0_regout ), + .oe(vcc), + .combout(), + .padio(SA[8])); +// synopsys translate_off +defparam \SA[8]~I .operation_mode = "output"; +// synopsys translate_on + +// Location: PIN_72, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +maxii_io \SA[9]~I ( + .datain(\SA[9]~reg0_regout ), + .oe(vcc), + .combout(), + .padio(SA[9])); +// synopsys translate_off +defparam \SA[9]~I .operation_mode = "output"; +// synopsys translate_on + +// Location: PIN_73, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +maxii_io \SA[10]~I ( + .datain(\SA[10]~reg0_regout ), + .oe(vcc), + .combout(), + .padio(SA[10])); +// synopsys translate_off +defparam \SA[10]~I .operation_mode = "output"; +// synopsys translate_on + +// Location: PIN_70, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +maxii_io \SA[11]~I ( + .datain(\SA[11]~reg0_regout ), + .oe(vcc), + .combout(), + .padio(SA[11])); +// synopsys translate_off +defparam \SA[11]~I .operation_mode = "output"; +// synopsys translate_on + +// Location: PIN_68, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +maxii_io \SA[12]~I ( + .datain(\SA[12]~reg0_regout ), + .oe(vcc), + .combout(), + .padio(SA[12])); +// synopsys translate_off +defparam \SA[12]~I .operation_mode = "output"; +// synopsys translate_on + +// Location: PIN_67, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +maxii_io \nRCS~I ( + .datain(!\nRCS~reg0_regout ), + .oe(vcc), + .combout(), + .padio(nRCS)); +// synopsys translate_off +defparam \nRCS~I .operation_mode = "output"; +// synopsys translate_on + +// Location: PIN_62, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +maxii_io \nRAS~I ( + .datain(!\nRAS~reg0_regout ), + .oe(vcc), + .combout(), + .padio(nRAS)); +// synopsys translate_off +defparam \nRAS~I .operation_mode = "output"; +// synopsys translate_on + +// Location: PIN_61, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +maxii_io \nCAS~I ( + .datain(!\nCAS~reg0_regout ), + .oe(vcc), + .combout(), + .padio(nCAS)); +// synopsys translate_off +defparam \nCAS~I .operation_mode = "output"; +// synopsys translate_on + +// Location: PIN_58, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +maxii_io \nSWE~I ( + .datain(!\nSWE~reg0_regout ), + .oe(vcc), + .combout(), + .padio(nSWE)); +// synopsys translate_off +defparam \nSWE~I .operation_mode = "output"; +// synopsys translate_on + +// Location: PIN_85, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +maxii_io \DQML~I ( + .datain(!\DQML~reg0_regout ), + .oe(vcc), + .combout(), + .padio(DQML)); +// synopsys translate_off +defparam \DQML~I .operation_mode = "output"; +// synopsys translate_on + +// Location: PIN_57, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +maxii_io \DQMH~I ( + .datain(!\DQMH~reg0_regout ), + .oe(vcc), + .combout(), + .padio(DQMH)); +// synopsys translate_off +defparam \DQMH~I .operation_mode = "output"; +// synopsys translate_on + +// Location: PIN_66, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +maxii_io \RCKE~I ( + .datain(!\RCKE~reg0_regout ), + .oe(vcc), + .combout(), + .padio(RCKE)); +// synopsys translate_off +defparam \RCKE~I .operation_mode = "output"; +// synopsys translate_on + +// Location: PIN_5, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +maxii_io \nFCS~I ( + .datain(!\FCS~regout ), + .oe(\FCKOE~regout ), + .combout(), + .padio(nFCS)); +// synopsys translate_off +defparam \nFCS~I .operation_mode = "output"; +// synopsys translate_on + +// Location: PIN_12, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA +maxii_io \FCK~I ( + .datain(\FCKout~regout ), + .oe(\FCKOE~regout ), + .combout(), + .padio(FCK)); +// synopsys translate_off +defparam \FCK~I .bus_hold = "true"; +defparam \FCK~I .operation_mode = "output"; +// synopsys translate_on + +endmodule diff --git a/cpld2/GR8RAM.qpf b/cpld2/GR8RAM.qpf deleted file mode 100644 index c72b9e0..0000000 --- a/cpld2/GR8RAM.qpf +++ /dev/null @@ -1,31 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 2022 Intel Corporation. All rights reserved. -# Your use of Intel Corporation's design tools, logic functions -# and other software and tools, and any partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Intel Program License -# Subscription Agreement, the Intel Quartus Prime License Agreement, -# the Intel FPGA IP License Agreement, or other applicable license -# agreement, including, without limitation, that your use is for -# the sole purpose of programming logic devices manufactured by -# Intel and sold by Intel or its authorized distributors. Please -# refer to the applicable agreement for further details, at -# https://fpgasoftware.intel.com/eula. -# -# -------------------------------------------------------------------------- # -# -# Quartus Prime -# Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition -# Date created = 11:15:44 February 28, 2023 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "22.1" -DATE = "11:15:44 February 28, 2023" - -# Revisions - -PROJECT_REVISION = "GR8RAM" diff --git a/cpld2/GR8RAM.qsf b/cpld2/GR8RAM.qsf deleted file mode 100644 index e2e3f88..0000000 --- a/cpld2/GR8RAM.qsf +++ /dev/null @@ -1,257 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2013 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 32-bit -# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition -# Date created = 13:41:40 March 15, 2021 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# GR8RAM_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - -set_global_assignment -name FAMILY "MAX II" -set_global_assignment -name DEVICE EPM240T100C5 -set_global_assignment -name TOP_LEVEL_ENTITY GR8RAM -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 22.1STD.0 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:15:44 FEBRUARY 28, 2023" -set_global_assignment -name LAST_QUARTUS_VERSION "22.1std.0 Lite Edition" -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100 -set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 5 -set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1" -set_global_assignment -name POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR 3.3V -set_global_assignment -name EDA_SIMULATION_TOOL "Questa Intel FPGA (Verilog)" -set_global_assignment -name EDA_NETLIST_WRITER_OUTPUT_DIR simulation/questa -section_id eda_simulation -set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation -set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation -set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing -set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol -set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity -set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan -set_location_assignment PIN_2 -to RA[5] -set_location_assignment PIN_3 -to RA[6] -set_location_assignment PIN_4 -to RA[3] -set_location_assignment PIN_5 -to nFCS -set_location_assignment PIN_6 -to RA[7] -set_location_assignment PIN_7 -to RA[8] -set_location_assignment PIN_8 -to RA[9] -set_location_assignment PIN_12 -to FCK -set_location_assignment PIN_14 -to RA[10] -set_location_assignment PIN_15 -to MOSI -set_location_assignment PIN_16 -to MISO -set_location_assignment PIN_30 -to nRESout -set_location_assignment PIN_34 -to RA[11] -set_location_assignment PIN_35 -to RA[12] -set_location_assignment PIN_36 -to RA[13] -set_location_assignment PIN_37 -to RA[14] -set_location_assignment PIN_38 -to RA[15] -set_location_assignment PIN_39 -to nIOSEL -set_location_assignment PIN_42 -to nIOSTRB -set_location_assignment PIN_40 -to nDEVSEL -set_location_assignment PIN_41 -to PHI0 -set_location_assignment PIN_43 -to nWE -set_location_assignment PIN_44 -to nRES -set_location_assignment PIN_47 -to SD[1] -set_location_assignment PIN_50 -to SD[0] -set_location_assignment PIN_51 -to SD[4] -set_location_assignment PIN_100 -to RA[0] -set_location_assignment PIN_99 -to RD[7] -set_location_assignment PIN_52 -to SD[5] -set_location_assignment PIN_54 -to SD[7] -set_location_assignment PIN_55 -to SD[3] -set_location_assignment PIN_56 -to SD[2] -set_location_assignment PIN_53 -to SD[6] -set_location_assignment PIN_57 -to DQMH -set_location_assignment PIN_58 -to nSWE -set_location_assignment PIN_62 -to nRAS -set_location_assignment PIN_61 -to nCAS -set_location_assignment PIN_64 -to C25M -set_location_assignment PIN_66 -to RCKE -set_location_assignment PIN_67 -to nRCS -set_location_assignment PIN_68 -to SA[12] -set_location_assignment PIN_69 -to SBA[0] -set_location_assignment PIN_70 -to SA[11] -set_location_assignment PIN_71 -to SBA[1] -set_location_assignment PIN_72 -to SA[9] -set_location_assignment PIN_73 -to SA[10] -set_location_assignment PIN_74 -to SA[8] -set_location_assignment PIN_75 -to SA[0] -set_location_assignment PIN_76 -to SA[4] -set_location_assignment PIN_77 -to SA[6] -set_location_assignment PIN_78 -to SA[7] -set_location_assignment PIN_81 -to SA[1] -set_location_assignment PIN_82 -to SA[2] -set_location_assignment PIN_83 -to SA[5] -set_location_assignment PIN_84 -to SA[3] -set_location_assignment PIN_85 -to DQML -set_location_assignment PIN_86 -to RD[0] -set_location_assignment PIN_87 -to RD[1] -set_location_assignment PIN_88 -to RD[2] -set_location_assignment PIN_89 -to RD[3] -set_location_assignment PIN_90 -to RD[4] -set_location_assignment PIN_91 -to RD[5] -set_location_assignment PIN_92 -to RD[6] -set_location_assignment PIN_97 -to RA[2] -set_location_assignment PIN_98 -to RA[1] -set_location_assignment PIN_96 -to SetFW[0] -set_location_assignment PIN_95 -to SetFW[1] -set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 1 -set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 2 -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nFCS -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nFCS -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to FCK -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to FCK -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to MOSI -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to MOSI -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to MISO -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to MISO -set_location_assignment PIN_21 -to nDMAout -set_location_assignment PIN_19 -to RAdir -set_location_assignment PIN_20 -to INTout -set_location_assignment PIN_26 -to nNMIout -set_location_assignment PIN_27 -to nINHout -set_location_assignment PIN_28 -to nRDYout -set_location_assignment PIN_29 -to nIRQout -set_location_assignment PIN_33 -to RWout -set_location_assignment PIN_48 -to DMAin -set_location_assignment PIN_49 -to INTin -set_location_assignment PIN_17 -to RDdir -set_location_assignment PIN_18 -to DMAout -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RA -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RA -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RA -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RD -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RD -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to RD -set_instance_assignment -name SLOW_SLEW_RATE OFF -to RD -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RD -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAdir -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to RAdir -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RAdir -set_instance_assignment -name SLOW_SLEW_RATE ON -to RAdir -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RAdir -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RDdir -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to RDdir -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RDdir -set_instance_assignment -name SLOW_SLEW_RATE ON -to RDdir -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RDdir -set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to PHI0 -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to PHI0 -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to PHI0 -set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to nWE -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nWE -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nWE -set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to nDEVSEL -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nDEVSEL -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nDEVSEL -set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to nIOSEL -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nIOSEL -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nIOSEL -set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to nIOSTRB -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nIOSTRB -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nIOSTRB -set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to nRES -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nRES -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nRES -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nRESout -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nRESout -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nRESout -set_instance_assignment -name SLOW_SLEW_RATE ON -to nRESout -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRESout -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nFCS -set_instance_assignment -name SLOW_SLEW_RATE ON -to nFCS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nFCS -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FCK -set_instance_assignment -name SLOW_SLEW_RATE ON -to FCK -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to FCK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MOSI -set_instance_assignment -name SLOW_SLEW_RATE ON -to MOSI -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MOSI -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MISO -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to C25M -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to C25M -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to C25M -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nRCS -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nRCS -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nRCS -set_instance_assignment -name SLOW_SLEW_RATE ON -to nRCS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRCS -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nRAS -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nRAS -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nRAS -set_instance_assignment -name SLOW_SLEW_RATE ON -to nRAS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRAS -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nCAS -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nCAS -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nCAS -set_instance_assignment -name SLOW_SLEW_RATE ON -to nCAS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nCAS -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nSWE -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nSWE -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nSWE -set_instance_assignment -name SLOW_SLEW_RATE ON -to nSWE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSWE -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RCKE -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RCKE -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RCKE -set_instance_assignment -name SLOW_SLEW_RATE ON -to RCKE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RCKE -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SBA -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SBA -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SBA -set_instance_assignment -name SLOW_SLEW_RATE ON -to SBA -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SBA -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SA -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SA -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SA -set_instance_assignment -name SLOW_SLEW_RATE ON -to SA -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SA -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQMH -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to DQMH -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to DQMH -set_instance_assignment -name SLOW_SLEW_RATE ON -to DQMH -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to DQMH -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQML -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to DQML -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to DQML -set_instance_assignment -name SLOW_SLEW_RATE ON -to DQML -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to DQML -set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to SetFW -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SetFW -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SetFW -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SD -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SD -set_instance_assignment -name SLOW_SLEW_RATE ON -to SD -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SD -set_global_assignment -name SDC_FILE GR8RAM.sdc \ No newline at end of file diff --git a/cpld2/GR8RAM.qws b/cpld2/GR8RAM.qws deleted file mode 100644 index 63563b7..0000000 Binary files a/cpld2/GR8RAM.qws and /dev/null differ diff --git a/cpld2/GR8RAM.sdc b/cpld2/GR8RAM.sdc deleted file mode 100644 index a7c9d8f..0000000 --- a/cpld2/GR8RAM.sdc +++ /dev/null @@ -1,3 +0,0 @@ -create_clock -period 40 [get_ports C25M] -create_clock -period 978 [get_ports PHI0] -set_clock_groups -asynchronous -group C25M -group PHI0 \ No newline at end of file diff --git a/cpld2/GR8RAM.v b/cpld2/GR8RAM.v deleted file mode 100644 index 41dd3b5..0000000 --- a/cpld2/GR8RAM.v +++ /dev/null @@ -1,568 +0,0 @@ -module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, - INTin, INTout, DMAin, DMAout, - nNMIout, nIRQout, nRDYout, nINHout, RWout, nDMAout, - RA, nWE, RD, RAdir, RDdir, nIOSEL, nDEVSEL, nIOSTRB, - SBA, SA, nRCS, nRAS, nCAS, nSWE, DQML, DQMH, RCKE, SD, - nFCS, FCK, MISO, MOSI); - - /* Clock signals */ - input C25M, PHI0; - reg PHI0r1, PHI0r2; - always @(posedge C25M) begin PHI0r1 <= PHI0; PHI0r2 <= PHI0r1; end - - /* Reset filter */ - input nRES; - reg [3:0] nRESf = 0; - reg nRESr = 0; - always @(posedge C25M) begin - nRESf[3:0] <= { nRESf[2:0], nRES }; - nRESr <= nRESf[3] || nRESf[2] || nRESf[1] || nRESf[0]; - end - - /* Firmware select */ - input [1:0] SetFW; - reg [1:0] SetFWr; - reg SetFWLoaded = 0; - always @(posedge C25M) begin - if (~SetFWLoaded) begin - SetFWLoaded <= 1; - SetFWr[1:0] <= SetFW[1:0]; - end - end - wire [1:0] SetROM = ~SetFWr[1:0]; - wire SetEN16MB = SetROM[1:0]==2'b11; - wire SetEN24bit = SetROM[1]; - - /* State counter from PHI0 rising edge */ - reg [3:0] PS = 0; - wire PSStart = PS==0 && PHI0r1 && ~PHI0r2; - always @(posedge C25M) begin - if (PSStart) PS <= 1; - else if (PS==0) PS <= 0; - else PS <= PS+1; - end - - /* Long state counter: counts from 0 to $3FFF */ - reg [13:0] LS = 0; - always @(posedge C25M) begin if (PS==15) LS <= LS+1; end - - /* Init state */ - output reg nRESout = 0; - reg [2:0] IS = 0; - always @(posedge C25M) begin - if (IS==7) nRESout <= 1; - else if (PS==15) begin - if (LS==14'h1FCE) IS <= 1; // PC all + load mode - else if (LS==14'h1FCF) IS <= 4; // AREF pause, SPI select - else if (LS==14'h1FFA) IS <= 5; // SPI flash command - else if (LS==14'h1FFF) IS <= 6; // Flash load driver - else if (LS==14'h3FFF) IS <= 7; // Operating mode - end - end - - /* Apple IO area select signals */ - input nIOSEL, nDEVSEL, nIOSTRB; - - /* Apple address bus */ - input [15:0] RA; input nWE; - reg [11:0] RAr; reg nWEr; - reg CXXXr; - always @(posedge PHI0) begin - CXXXr <= RA[15:12]==4'hC; - RAr[11:0] <= RA[11:0]; - nWEr <= nWE; - end - - /* Apple select signals */ - wire ROMSpecRD = CXXXr && RAr[11:8]!=4'h0 && nWEr && ((RAr[11] && IOROMEN) || (~RAr[11])); - wire REGSpecSEL = CXXXr && RAr[11:8]==4'h0 && RAr[7] && REGEN; - wire BankSpecSEL = REGSpecSEL && RAr[3:0]==4'hF; - wire RAMRegSpecSEL = REGSpecSEL && RAr[3:0]==4'h3; - wire RAMSpecSEL = RAMRegSpecSEL && (~SetEN24bit || SetEN16MB || ~Addr[23]); - wire AddrHSpecSEL = REGSpecSEL && RAr[3:0]==4'h2; - wire AddrMSpecSEL = REGSpecSEL && RAr[3:0]==4'h1; - wire AddrLSpecSEL = REGSpecSEL && RAr[3:0]==4'h0; - wire BankSEL = REGEN && ~nDEVSEL && BankSpecSEL; - wire RAMRegSEL = ~nDEVSEL && RAMRegSpecSEL; - wire RAMSEL = ~nDEVSEL && RAMSpecSEL; - wire RAMWR = RAMSEL && ~nWEr; - wire AddrHSEL = REGEN && ~nDEVSEL && AddrHSpecSEL; - wire AddrMSEL = REGEN && ~nDEVSEL && AddrMSpecSEL; - wire AddrLSEL = REGEN && ~nDEVSEL && AddrLSpecSEL; - - /* IOROMEN and REGEN control */ - reg IOROMEN = 0; - reg REGEN = 0; - reg nIOSTRBr; - wire IOROMRES = RAr[10:0]==11'h7FF && ~nIOSTRB && ~nIOSTRBr; - always @(posedge C25M, negedge nRESr) begin - if (~nRESr) REGEN <= 0; - else if (PS==8 && ~nIOSEL) REGEN <= 1; - end - always @(posedge C25M) begin - nIOSTRBr <= nIOSTRB; - if (~nRESr) IOROMEN <= 0; - else if (PS==8 && IOROMRES) IOROMEN <= 0; - else if (PS==8 && ~nIOSEL) IOROMEN <= 1; - end - - /* Apple data bus */ - inout [7:0] RD = RDdir ? 8'bZ : RDD[7:0]; - reg [7:0] RDD; - output RDdir = ~(PHI0r2 && nWE && PHI0 && - (~nDEVSEL || ~nIOSEL || (~nIOSTRB && IOROMEN && RA[10:0]!=11'h7FF))); - - /* Slinky address registers */ - reg [23:0] Addr = 0; - reg AddrIncL = 0; - reg AddrIncM = 0; - reg AddrIncH = 0; - always @(posedge C25M, negedge nRESr) begin - if (~nRESr) begin - Addr[23:0] <= 24'h000000; - AddrIncL <= 0; - AddrIncM <= 0; - AddrIncH <= 0; - end else begin - if (PS==8 && RAMRegSEL) AddrIncL <= 1; - else AddrIncL <= 0; - - if (PS==8 && AddrLSEL && ~nWEr) begin - Addr[7:0] <= RD[7:0]; - AddrIncM <= Addr[7] && ~RD[7]; - end else if (AddrIncL) begin - Addr[7:0] <= Addr[7:0]+1; - AddrIncM <= Addr[7:0]==8'hFF; - end else AddrIncM <= 0; - - if (PS==8 && AddrMSEL && ~nWEr) begin - Addr[15:8] <= RD[7:0]; - AddrIncH <= Addr[15] && ~RD[7]; - end else if (AddrIncM) begin - Addr[15:8] <= Addr[15:8]+1; - AddrIncH <= Addr[15:8]==8'hFF; - end else AddrIncH <= 0; - - if (PS==8 && AddrHSEL && ~nWEr) begin - Addr[23:16] <= RD[7:0]; - end else if (AddrIncH) begin - Addr[23:16] <= Addr[23:16]+1; - end - end - end - - /* ROM bank register */ - reg Bank = 0; - always @(posedge C25M, negedge nRESr) begin - if (~nRESr) Bank <= 0; - else if (PS==8 && BankSEL && ~nWEr) begin - Bank <= RD[0]; - end - end - - /* SPI flash control signals */ - output nFCS = FCKOE ? ~FCS : 1'bZ; - reg FCS = 0; - output FCK = FCKOE ? FCKout : 1'bZ; - reg FCKOE = 0; - reg FCKout = 0; - inout MOSI = MOSIOE ? MOSIout : 1'bZ; - reg MOSIOE = 0; - input MISO; - always @(posedge C25M) begin - case (PS[3:0]) - 0: begin // NOP CKE - FCKout <= 1'b1; - end 1: begin // ACT - FCKout <= ~(IS==5 || IS==6); - end 2: begin // RD - FCKout <= 1'b1; - end 3: begin // NOP CKE - FCKout <= ~(IS==5 || IS==6); - end 4: begin // NOP CKE - FCKout <= 1'b1; - end 5: begin // NOP CKE - FCKout <= ~(IS==5 || IS==6); - end 6: begin // NOP CKE - FCKout <= 1'b1; - end 7: begin // NOP CKE - FCKout <= ~(IS==5 || IS==6); - end 8: begin // WR AP - FCKout <= 1'b1; - end 9: begin // NOP CKE - FCKout <= ~(IS==5); - end 10: begin // PC all - FCKout <= 1'b1; - end 11: begin // AREF - FCKout <= ~(IS==5); - end 12: begin // NOP CKE - FCKout <= 1'b1; - end 13: begin // NOP CKE - FCKout <= ~(IS==5); - end 14: begin // NOP CKE - FCKout <= 1'b1; - end 15: begin // NOP CKE - FCKout <= ~(IS==5); - end - endcase - FCS <= IS==4 || IS==5 || IS==6; - MOSIOE <= IS==5; - FCKOE <= IS==1 || IS==4 || IS==5 || IS==6 || IS==7; - end - - /* SPI flash MOSI control */ - reg MOSIout = 0; - always @(posedge C25M) begin - case (PS[3:0]) - 1: begin - case (LS[2:0]) - 3'h3: MOSIout <= 1'b0; // Command bit 7 - 3'h4: MOSIout <= 1'b0; // Address bit 23 - 3'h5: MOSIout <= 1'b0; // Address bit 15 - 3'h6: MOSIout <= 1'b0; // Address bit 7 - default MOSIout <= 1'b0; - endcase - end 3: begin - case (LS[2:0]) - 3'h3: MOSIout <= 1'b0; // Command bit 6 - 3'h4: MOSIout <= 1'b0; // Address bit 22 - 3'h5: MOSIout <= SetROM[1]; // Address bit 14 - 3'h6: MOSIout <= 1'b0; // Address bit 6 - default MOSIout <= 1'b0; - endcase - end 5: begin - case (LS[2:0]) - 3'h3: MOSIout <= 1'b1; // Command bit 5 - 3'h4: MOSIout <= 1'b0; // Address bit 21 - 3'h5: MOSIout <= SetROM[0]; // Address bit 13 - 3'h6: MOSIout <= 1'b0; // Address bit 5 - default MOSIout <= 1'b0; - endcase - end 7: begin - case (LS[2:0]) - 3'h3: MOSIout <= 1'b1; // Command bit 4 - 3'h4: MOSIout <= 1'b0; // Address bit 20 - 3'h5: MOSIout <= 1'b0; // Address bit 12 - 3'h6: MOSIout <= 1'b0; // Address bit 4 - default MOSIout <= 1'b0; - endcase - end 9: begin - case (LS[2:0]) - 3'h3: MOSIout <= 1'b1; // Command bit 3 - 3'h4: MOSIout <= 1'b0; // Address bit 19 - 3'h5: MOSIout <= 1'b0; // Address bit 11 - 3'h6: MOSIout <= 1'b0; // Address bit 3 - default MOSIout <= 1'b0; - endcase - end 11: begin - case (LS[2:0]) - 3'h3: MOSIout <= 1'b0; // Command bit 2 - 3'h4: MOSIout <= 1'b0; // Address bit 18 - 3'h5: MOSIout <= 1'b0; // Address bit 10 - 3'h6: MOSIout <= 1'b0; // Address bit 2 - default MOSIout <= 1'b0; - endcase - end 13: begin - case (LS[2:0]) - 3'h3: MOSIout <= 1'b1; // Command bit 1 - 3'h4: MOSIout <= 1'b0; // Address bit 16 - 3'h5: MOSIout <= 1'b0; // Address bit 9 - 3'h6: MOSIout <= 1'b0; // Address bit 1 - default MOSIout <= 1'b0; - endcase - end 15: begin - case (LS[2:0]) - 3'h3: MOSIout <= 1'b1; // Command bit 0 - 3'h4: MOSIout <= 1'b0; // Address bit 15 - 3'h5: MOSIout <= 1'b0; // Address bit 7 - 3'h6: MOSIout <= 1'b0; // Address bit 0 - default MOSIout <= 1'b0; - endcase - end - endcase - end - - /* SDRAM data bus */ - inout [7:0] SD = SDOE ? WRD[7:0] : 8'bZ; - reg [7:0] WRD; - reg SDOE = 0; - always @(posedge C25M) begin - case (PS[3:0]) - 0: begin // NOP CKE - if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI }; - else WRD[7:0] <= RD[7:0]; - end 1: begin // ACT - end 2: begin // RD - if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI }; - else WRD[7:0] <= RD[7:0]; - end 3: begin // NOP CKE - end 4: begin // NOP CKE - if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI }; - else WRD[7:0] <= RD[7:0]; - end 5: begin // NOP CKE - end 6: begin // NOP CKE - if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI }; - else WRD[7:0] <= RD[7:0]; - end 7: begin // NOP CKE - end 8: begin // WR AP - if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI }; - else WRD[7:0] <= RD[7:0]; - end 9: begin // NOP CKE - end 10: begin // PC all - if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI }; - else WRD[7:0] <= RD[7:0]; - end 11: begin // AREF - end 12: begin // NOP CKE - if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI }; - else WRD[7:0] <= RD[7:0]; - end 13: begin // NOP CKE - end 14: begin // NOP CKE - if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI }; - else WRD[7:0] <= RD[7:0]; - end 15: begin // NOP CKE - end - endcase - end - - /* Apple data bus from SDRAM */ - always @(negedge C25M) begin - if (PS==5) begin - if (AddrLSpecSEL) RDD[7:0] <= Addr[7:0]; - else if (AddrMSpecSEL) RDD[7:0] <= Addr[15:8]; - else if (AddrHSpecSEL) RDD[7:0] <= { SetEN24bit ? Addr[23:20] : 4'hF, Addr[19:16] }; - else RDD[7:0] <= SD[7:0]; - end - end - - /* SDRAM command */ - output reg RCKE = 1; - output reg nRCS = 1; - output reg nRAS = 1; - output reg nCAS = 1; - output reg nSWE = 1; - wire RefReqd = LS[1:0] == 2'b11; - always @(posedge C25M) begin - case (PS[3:0]) - 0: begin // NOP CKE / NOP CKD - RCKE <= PSStart && (IS==6 || (IS==7 && (ROMSpecRD || RAMSpecSEL))); - nRCS <= 1; - nRAS <= 1; - nCAS <= 1; - nSWE <= 1; - SDOE <= 0; - end 1: begin // ACT CKE / NOP CKD (ACT) - RCKE <= IS==6 || (IS==7 && (ROMSpecRD || RAMSpecSEL)); - nRCS <= ~(IS==6 || (IS==7 && (ROMSpecRD || RAMSpecSEL))); - nRAS <= 0; - nCAS <= 1; - nSWE <= 1; - SDOE <= 0; - end 2: begin // RD CKE / NOP CKD (RD) - RCKE <= IS==7 && nWEr && (ROMSpecRD || RAMSpecSEL); - nRCS <= ~(IS==7 && nWEr && (ROMSpecRD || RAMSpecSEL)); - nRAS <= 1; - nCAS <= 0; - nSWE <= 1; - SDOE <= 0; - end 3: begin // NOP CKE / CKD - RCKE <= IS==7 && nWEr && (ROMSpecRD || RAMSpecSEL); - nRCS <= 1; - nRAS <= 1; - nCAS <= 1; - nSWE <= 1; - SDOE <= 0; - end 4: begin // NOP CKD - RCKE <= 0; - nRCS <= 1; - nRAS <= 1; - nCAS <= 1; - nSWE <= 1; - SDOE <= 0; - end 5: begin // NOP CKD - RCKE <= 0; - nRCS <= 1; - nRAS <= 1; - nCAS <= 1; - nSWE <= 1; - SDOE <= 0; - end 6: begin // NOP CKD - RCKE <= 0; - nRCS <= 1; - nRAS <= 1; - nCAS <= 1; - nSWE <= 1; - SDOE <= 0; - end 7: begin // NOP CKE / CKD - RCKE <= IS==6 || (RAMWR && IS==7); - nRCS <= 1; - nRAS <= 1; - nCAS <= 1; - nSWE <= 1; - SDOE <= 0; - end 8: begin // WR AP CKE / NOP CKD (WR AP) - RCKE <= IS==6 || (RAMWR && IS==7); - nRCS <= ~(IS==6 || (RAMWR && IS==7)); - nRAS <= 1; - nCAS <= 0; - nSWE <= 0; - SDOE <= IS==6 || (RAMWR && IS==7); - end 9: begin // NOP CKE / NOP CKD - RCKE <= 1; - nRCS <= 1; - nRAS <= 1; - nCAS <= 1; - nSWE <= 1; - SDOE <= 0; - end 10: begin // PC all CKE / PC all CKD - RCKE <= IS==1 || IS==4 || IS==5 || IS==6 || (IS==7 && RefReqd); - nRCS <= 0; - nRAS <= 0; - nCAS <= 1; - nSWE <= 0; - SDOE <= 0; - end 11: begin // LDM CKE / AREF CKE / NOP CKD - RCKE <= IS==1 || IS==4 || IS==5 || IS==6 || (IS==7 && RefReqd); - nRCS <= ~(IS==1 || IS==4 || IS==5 || IS==6 || (IS==7 && RefReqd)); - nRAS <= 0; - nCAS <= 0; - nSWE <= ~(IS==1); - SDOE <= 0; - end default: begin // NOP CKD - RCKE <= 0; - nRCS <= 1; - nRAS <= 1; - nCAS <= 1; - nSWE <= 1; - SDOE <= 0; - end - endcase - end - - /* SDRAM address */ - output reg DQML = 1; - output reg DQMH = 1; - output reg [1:0] SBA; - output reg [12:0] SA; - always @(posedge C25M) begin - case (PS[3:0]) - 0: begin // NOP CKE - DQML <= 1'b1; - DQMH <= 1'b1; - SBA[1:0] <= 2'b00; - SA[12:0] <= 13'b0011000100000; - end 1: begin // ACT - DQML <= 1'b1; - DQMH <= 1'b1; - if (IS==6) begin - SBA[1:0] <= { 2'b10 }; - SA[12:0] <= { 10'b0011000100, LS[12:10] }; - end else if (RAMSpecSEL) begin - SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 }; - SA[12:10] <= SetEN24bit ? Addr[22:20] : 3'b000; - SA[9:0] <= Addr[19:10]; - end else begin - SBA[1:0] <= 2'b10; - SA[12:0] <= { 10'b0011000100, Bank, RAr[11:10] }; - end - end 2: begin // RD - if (RAMSpecSEL) begin - SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 }; - SA[12:0] <= { 4'b0011, Addr[9:1] }; - DQML <= Addr[0]; - DQMH <= ~Addr[0]; - end else begin - SBA[1:0] <= 2'b10; - SA[12:0] <= { 4'b0011, RAr[9:1]}; - DQML <= RAr[0]; - DQMH <= ~RAr[0]; - end - end 3: begin // NOP CKE - DQML <= 1'b1; - DQMH <= 1'b1; - SBA[1:0] <= 2'b00; - SA[12:0] <= 13'b0011000100000; - end 4: begin // NOP CKE - DQML <= 1'b1; - DQMH <= 1'b1; - SBA[1:0] <= 2'b00; - SA[12:0] <= 13'b0011000100000; - end 5: begin // NOP CKE - DQML <= 1'b1; - DQMH <= 1'b1; - SBA[1:0] <= 2'b00; - SA[12:0] <= 13'b0011000100000; - end 6: begin // NOP CKE - DQML <= 1'b1; - DQMH <= 1'b1; - SBA[1:0] <= 2'b00; - SA[12:0] <= 13'b0011000100000; - end 7: begin // NOP CKE - DQML <= 1'b1; - DQMH <= 1'b1; - SBA[1:0] <= 2'b00; - SA[12:0] <= 13'b0011000100000; - end 8: begin // WR AP - if (IS==6) begin - SBA[1:0] <= 2'b10; - SA[12:0] <= { 4'b0011, LS[9:1] }; - DQML <= LS[0]; - DQMH <= ~LS[0]; - end else begin - SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 }; - SA[12:0] <= { 4'b0011, Addr[9:1] }; - DQML <= Addr[0]; - DQMH <= ~Addr[0]; - end - end 9: begin // NOP CKE - DQML <= 1'b1; - DQMH <= 1'b1; - SBA[1:0] <= 2'b00; - SA[12:0] <= 13'b0011000100000; - end 10: begin // PC all - DQML <= 1'b1; - DQMH <= 1'b1; - SBA[1:0] <= 2'b00; - SA[12:0] <= 13'b0011000100000; - end 11: begin // AREF / load mode - DQML <= 1'b1; - DQMH <= 1'b1; - SBA[1:0] <= 2'b00; - SA[12:0] <= 13'b0001000100000; - end 12: begin // NOP CKE - DQML <= 1'b1; - DQMH <= 1'b1; - SBA[1:0] <= 2'b00; - SA[12:0] <= 13'b0011000100000; - end 13: begin // NOP CKE - DQML <= 1'b1; - DQMH <= 1'b1; - SBA[1:0] <= 2'b00; - SA[12:0] <= 13'b0011000100000; - end 14: begin // NOP CKE - DQML <= 1'b1; - DQMH <= 1'b1; - SBA[1:0] <= 2'b00; - SA[12:0] <= 13'b0011000100000; - end 15: begin // NOP CKE - DQML <= 1'b1; - DQMH <= 1'b1; - SBA[1:0] <= 2'b00; - SA[12:0] <= 13'b0011000100000; - end - endcase - end - - /* DMA/INT in/out */ - input INTin, DMAin; - output INTout = INTin; - output DMAout = DMAin; - - /* Unused Pins */ - output RAdir = 1; - output nDMAout = 1; - output nNMIout = 1; - output nINHout = 1; - output nRDYout = 1; - output nIRQout = 1; - output RWout = 1; -endmodule diff --git a/cpld2/db/GR8RAM.db_info b/cpld2/db/GR8RAM.db_info deleted file mode 100644 index 5865109..0000000 --- a/cpld2/db/GR8RAM.db_info +++ /dev/null @@ -1,3 +0,0 @@ -Quartus_Version = Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition -Version_Index = 553882368 -Creation_Time = Tue Feb 28 11:15:44 2023