diff --git a/cpld/GR8RAM.qws b/cpld/GR8RAM.qws new file mode 100644 index 0000000..6c79ab4 Binary files /dev/null and b/cpld/GR8RAM.qws differ diff --git a/cpld/GR8RAM.v b/cpld/GR8RAM.v index ae7506a..839b3d0 100644 --- a/cpld/GR8RAM.v +++ b/cpld/GR8RAM.v @@ -54,14 +54,14 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, input [15:0] RA; input nWE; /* Apple select signals */ - wire ROMSpecSEL = RA[15:12]==4'hC && RA[11:8]!=4'h0; + wire ROMSpecRD = RA[15:12]==4'hC && RA[11:8]!=4'h0 && nWE; wire BankSpecSEL = RA[3:0]==4'hF; wire REGSpecSEL = RA[15:12]==4'hC && RA[11:8]==4'h0 && RA[7] && REGEN; - wire RAMSpecSEL = REGSpecSEL && RA[3:0]==4'h3 && (~SetLim1M || Addr[23:20]==0) && (~SetLim8M || ~Addr[23]); + wire RAMSpecSEL = REGSpecSEL && RA[3:0]==4'h3; wire AddrHSpecSEL = REGSpecSEL && RA[3:0]==4'h2; wire AddrMSpecSEL = REGSpecSEL && RA[3:0]==4'h1; wire AddrLSpecSEL = REGSpecSEL && RA[3:0]==4'h0; - reg ROMSpecSELr, RAMSpecSELr, nWEr; + reg ROMSpecRDr, RAMSpecSELr, nWEr; wire BankSEL = REGEN && ~nDEVSEL && BankSpecSEL; wire RAMSEL = ~nDEVSEL && RAMSpecSELr; wire RAMWR = RAMSEL && ~nWEr; @@ -69,7 +69,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, wire AddrMSEL = REGEN && ~nDEVSEL && AddrMSpecSEL; wire AddrLSEL = REGEN && ~nDEVSEL && AddrLSpecSEL; always @(posedge PHI0) begin - ROMSpecSELr <= ROMSpecSEL; + ROMSpecRDr <= ROMSpecRD; RAMSpecSELr <= RAMSpecSEL; nWEr <= nWE; end @@ -191,12 +191,12 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, endcase FCS <= IS==4 || IS==5 || IS==6; MOSIOE <= IS==5; - FCKOE <= IS==1 || IS==2 || IS==3 || IS==4 || IS==5 || IS==6 || IS==7; + FCKOE <= IS==1 || IS==4 || IS==5 || IS==6 || IS==7; end always @(posedge C25M) begin case (PS[3:0]) - 1, 2: begin + 1: begin case (LS[2:0]) 3'h3: MOSIout <= 1'b0; // Command bit 7 3'h4: MOSIout <= 1'b0; // Address bit 23 @@ -204,23 +204,23 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, 3'h6: MOSIout <= 1'b0; // Address bit 7 default MOSIout <= 1'b0; endcase - end 3, 4: begin + end 3: begin case (LS[2:0]) 3'h3: MOSIout <= 1'b0; // Command bit 6 3'h4: MOSIout <= 1'b0; // Address bit 22 - 3'h5: MOSIout <= SetFW[1]; // Address bit 14 + 3'h5: MOSIout <= SetROM[1]; // Address bit 14 3'h6: MOSIout <= 1'b0; // Address bit 6 default MOSIout <= 1'b0; endcase - end 5, 6: begin + end 5: begin case (LS[2:0]) 3'h3: MOSIout <= 1'b1; // Command bit 5 3'h4: MOSIout <= 1'b0; // Address bit 21 - 3'h5: MOSIout <= SetFW[0]; // Address bit 13 + 3'h5: MOSIout <= SetROM[0]; // Address bit 13 3'h6: MOSIout <= 1'b0; // Address bit 5 default MOSIout <= 1'b0; endcase - end 7, 8: begin + end 7: begin case (LS[2:0]) 3'h3: MOSIout <= 1'b1; // Command bit 4 3'h4: MOSIout <= 1'b0; // Address bit 20 @@ -228,7 +228,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, 3'h6: MOSIout <= 1'b0; // Address bit 4 default MOSIout <= 1'b0; endcase - end 9, 10: begin + end 9: begin case (LS[2:0]) 3'h3: MOSIout <= 1'b1; // Command bit 3 3'h4: MOSIout <= 1'b0; // Address bit 19 @@ -236,7 +236,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, 3'h6: MOSIout <= 1'b0; // Address bit 3 default MOSIout <= 1'b0; endcase - end 11, 12: begin + end 11: begin case (LS[2:0]) 3'h3: MOSIout <= 1'b0; // Command bit 2 3'h4: MOSIout <= 1'b0; // Address bit 18 @@ -244,7 +244,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, 3'h6: MOSIout <= 1'b0; // Address bit 2 default MOSIout <= 1'b0; endcase - end 13, 14: begin + end 13: begin case (LS[2:0]) 3'h3: MOSIout <= 1'b1; // Command bit 1 3'h4: MOSIout <= 1'b0; // Address bit 16 @@ -252,7 +252,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, 3'h6: MOSIout <= 1'b0; // Address bit 1 default MOSIout <= 1'b0; endcase - end 15, 0: begin + end 15: begin case (LS[2:0]) 3'h3: MOSIout <= 1'b1; // Command bit 0 3'h4: MOSIout <= 1'b0; // Address bit 15 @@ -265,6 +265,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, end input [1:0] SetFW; + wire [1:0] SetROM = 2'b01; wire SetRF = SetFW[1:0] != 2'b11; wire SetLim1M = SetFW[1]; wire SetLim8M = SetFW[1:0] != 2'b00; @@ -276,40 +277,40 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, always @(posedge C25M) begin case (PS[3:0]) 0: begin // NOP CKE - if (IS==6) WRD[7:0] <= { MISO, MOSI, WRD[5:0] }; + if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI }; else WRD[7:0] <= RD[7:0]; end 1: begin // ACT end 2: begin // RD - if (IS==6) WRD[7:0] <= { MISO, MOSI, WRD[5:0] }; + if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI }; else WRD[7:0] <= RD[7:0]; end 3: begin // NOP CKE end 4: begin // NOP CKE - if (AddrLSpecSEL) RDD[7:0] <= Addr[7:0]; - else if (AddrMSpecSEL) RDD[7:0] <= Addr[15:8]; - else if (AddrHSpecSEL && SetRF) RDD[7:0] <= Addr[23:16]; - else if (AddrHSpecSEL && ~SetRF) RDD[7:0] <= {4'hF, Addr[19:16]}; - else RDD[7:0] <= SD[7:0]; - if (IS==6) WRD[7:0] <= { MISO, MOSI, WRD[5:0] }; + if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI }; else WRD[7:0] <= RD[7:0]; end 5: begin // NOP CKE + if (AddrLSpecSEL) RDD[7:0] <= Addr[7:0]; + else if (AddrMSpecSEL) RDD[7:0] <= Addr[15:8]; + else if (AddrHSpecSEL) RDD[7:0] <= Addr[23:16]; + else if (AddrHSpecSEL) RDD[7:0] <= {4'hF, Addr[19:16]}; + else RDD[7:0] <= SD[7:0]; end 6: begin // NOP CKE - if (IS==6) WRD[7:0] <= { MISO, MOSI, WRD[5:0] }; + if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI }; else WRD[7:0] <= RD[7:0]; end 7: begin // NOP CKE end 8: begin // WR AP - if (IS==6) WRD[7:0] <= { MISO, MOSI, WRD[5:0] }; + if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI }; else WRD[7:0] <= RD[7:0]; end 9: begin // NOP CKE end 10: begin // PC all - if (IS==6) WRD[7:0] <= { MISO, MOSI, WRD[5:0] }; + if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI }; else WRD[7:0] <= RD[7:0]; end 11: begin // AREF end 12: begin // NOP CKE - if (IS==6) WRD[7:0] <= { MISO, MOSI, WRD[5:0] }; + if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI }; else WRD[7:0] <= RD[7:0]; end 13: begin // NOP CKE end 14: begin // NOP CKE - if (IS==6) WRD[7:0] <= { MISO, MOSI, WRD[5:0] }; + if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI }; else WRD[7:0] <= RD[7:0]; end 15: begin // NOP CKE end @@ -325,7 +326,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, end /* SDRAM address/command */ - output RCKE = 1; + output reg RCKE = 1; output reg nRCS = 1; output reg nRAS = 1; output reg nCAS = 1; @@ -333,98 +334,92 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, wire RefReqd = LS[1:0] == 2'b11; always @(posedge C25M) begin case (PS[3:0]) - 0: begin // NOP + 0: begin // NOP CKE / NOP CKD + RCKE <= PSStart; nRCS <= 1'b1; nRAS <= 1'b1; nCAS <= 1'b1; nSWE <= 1'b1; SDOE <= 0; - end 1: begin // ACT / NOP (ACT) - nRCS <= ~(IS==6 || (((ROMSpecSELr && nWEr) || RAMSpecSELr) && IS==7)); + end 1: begin // ACT CKE / NOP CKD (ACT) + RCKE <= (ROMSpecRDr || RAMSpecSELr) && nWEr && IS==7; + nRCS <= ~(IS==6 || ((ROMSpecRDr || RAMSpecSELr) && IS==7)); nRAS <= 1'b0; nCAS <= 1'b1; nSWE <= 1'b1; SDOE <= 0; - end 2: begin // RD / NOP (RD) - nRCS <= ~((ROMSpecSELr || RAMSpecSELr) && nWEr && IS==7); + end 2: begin // RD CKE / NOP CKD (RD) + RCKE <= (ROMSpecRDr || RAMSpecSELr) && nWEr && IS==7; + nRCS <= ~((ROMSpecRDr || RAMSpecSELr) && nWEr && IS==7); nRAS <= 1'b1; nCAS <= 1'b0; nSWE <= 1'b1; SDOE <= 0; - end 3: begin // NOP + end 3: begin // NOP CKE / CKD + RCKE <= (ROMSpecRDr || RAMSpecSELr) && nWEr && IS==7; nRCS <= 1'b1; nRAS <= 1'b1; nCAS <= 1'b1; nSWE <= 1'b1; SDOE <= 0; - end 4: begin // NOP + end 4: begin // NOP CKD + RCKE <= 1'b0; nRCS <= 1'b1; nRAS <= 1'b1; nCAS <= 1'b1; nSWE <= 1'b1; SDOE <= 0; - end 5: begin // NOP + end 5: begin // NOP CKD + RCKE <= 1'b0; nRCS <= 1'b1; nRAS <= 1'b1; nCAS <= 1'b1; nSWE <= 1'b1; SDOE <= 0; - end 6: begin // NOP + end 6: begin // NOP CKD + RCKE <= 1'b0; nRCS <= 1'b1; nRAS <= 1'b1; nCAS <= 1'b1; nSWE <= 1'b1; SDOE <= 0; - end 7: begin // NOP + end 7: begin // NOP CKE / CKD + RCKE <= IS==6 || (RAMWR && IS==7); nRCS <= 1'b1; nRAS <= 1'b1; nCAS <= 1'b1; nSWE <= 1'b1; SDOE <= 0; - end 8: begin // WR AP / NOP (WR AP) + end 8: begin // WR AP CKE / NOP CKD (WR AP) + RCKE <= IS==6 || (RAMWR && IS==7); nRCS <= ~(IS==6 || (RAMWR && IS==7)); nRAS <= 1'b1; nCAS <= 1'b0; nSWE <= 1'b0; SDOE <= IS==6 || (RAMWR && IS==7); - end 9: begin // NOP + end 9: begin // NOP CKE / NOP CKD + RCKE <= 1'b1; nRCS <= 1'b1; nRAS <= 1'b1; nCAS <= 1'b1; nSWE <= 1'b1; SDOE <= 0; - end 10: begin // PC all / NOP (PC all) - nRCS <= ~((IS==6) || ((ROMSpecSELr || RAMSpecSELr) && IS==7) || - (RefReqd && (IS==4 || IS==5 || IS==6 || IS==7))); + end 10: begin // PC all CKE / PC all CKD + RCKE <= 1'b1; + nRCS <= 1'b0; nRAS <= 1'b0; nCAS <= 1'b1; nSWE <= 1'b0; SDOE <= 0; - end 11: begin // AREF - nRCS <= ~(RefReqd && (IS==4 || IS==5 || IS==6 || IS==7)); + end 11: begin // LDM CKE / AREF CKE / NOP CKD + RCKE <= IS==1 || IS==4 || IS==5 || IS==6 || (IS==7 && RefReqd); + nRCS <= ~(IS==1 || IS==4 || IS==5 || IS==6 || (IS==7 && RefReqd)); nRAS <= 1'b0; nCAS <= 1'b0; - nSWE <= 1'b1; + nSWE <= ~(IS==1); SDOE <= 0; - end 12: begin // NOP - nRCS <= 1'b1; - nRAS <= 1'b1; - nCAS <= 1'b1; - nSWE <= 1'b1; - SDOE <= 0; - end 13: begin // NOP - nRCS <= 1'b1; - nRAS <= 1'b1; - nCAS <= 1'b1; - nSWE <= 1'b1; - SDOE <= 0; - end 14: begin // NOP - nRCS <= 1'b1; - nRAS <= 1'b1; - nCAS <= 1'b1; - nSWE <= 1'b1; - SDOE <= 0; - end 15: begin // NOP + end default: begin // NOP CKD + RCKE <= IS==1; nRCS <= 1'b1; nRAS <= 1'b1; nCAS <= 1'b1; @@ -451,15 +446,15 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, SBA[1:0] <= { 2'b10 }; SA[12:0] <= { 10'b0011000100, LS[12:10] }; end else if (RAMSpecSELr) begin - SBA[1:0] <= { 1'b0, Addr[23] && SetRF }; - SA[12:0] <= { SetRF ? Addr [22:20] : 3'b000, Addr[19:10]}; + SBA[1:0] <= { 1'b0, Addr[23] }; + SA[12:0] <= Addr [22:10]; end else begin SBA[1:0] <= 2'b10; SA[12:0] <= { 10'b0011000100, Bank, RA[11:10] }; end end 2: begin // RD if (RAMSpecSELr) begin - SBA[1:0] <= { 1'b0, Addr[23] && SetLim8M && SetRF }; + SBA[1:0] <= { 1'b0, Addr[23] }; SA[12:0] <= { 4'b0011, Addr[9:1] }; DQML <= Addr[0]; DQMH <= ~Addr[0]; @@ -501,7 +496,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, DQML <= LS[0]; DQMH <= ~LS[0]; end else begin - SBA[1:0] <= { 1'b0, Addr[23] && SetLim8M && SetRF }; + SBA[1:0] <= { 1'b0, Addr[23] }; SA[12:0] <= { 4'b0011, Addr[9:1] }; DQML <= Addr[0]; DQMH <= ~Addr[0]; diff --git a/cpld/db/GR8RAM.(0).cnf.cdb b/cpld/db/GR8RAM.(0).cnf.cdb index 8a01751..6614a7b 100755 Binary files a/cpld/db/GR8RAM.(0).cnf.cdb and b/cpld/db/GR8RAM.(0).cnf.cdb differ diff --git a/cpld/db/GR8RAM.(0).cnf.hdb b/cpld/db/GR8RAM.(0).cnf.hdb index b6aa653..3dfaa40 100755 Binary files a/cpld/db/GR8RAM.(0).cnf.hdb and b/cpld/db/GR8RAM.(0).cnf.hdb differ diff --git a/cpld/db/GR8RAM.asm.qmsg b/cpld/db/GR8RAM.asm.qmsg index 86a292a..ed9cb89 100755 --- a/cpld/db/GR8RAM.asm.qmsg +++ b/cpld/db/GR8RAM.asm.qmsg @@ -1,6 +1,6 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618731925004 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618731925004 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 18 03:45:24 2021 " "Processing started: Sun Apr 18 03:45:24 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618731925004 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1618731925004 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1618731925004 ""} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1618731925194 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1618731925204 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "381 " "Peak virtual memory: 381 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618731925334 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 18 03:45:25 2021 " "Processing ended: Sun Apr 18 03:45:25 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618731925334 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618731925334 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618731925334 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1618731925334 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618739752654 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618739752654 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 18 05:55:52 2021 " "Processing started: Sun Apr 18 05:55:52 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618739752654 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1618739752654 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1618739752654 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1618739752854 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1618739752854 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "381 " "Peak virtual memory: 381 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618739752994 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 18 05:55:52 2021 " "Processing ended: Sun Apr 18 05:55:52 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618739752994 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618739752994 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618739752994 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1618739752994 ""} diff --git a/cpld/db/GR8RAM.asm.rdb b/cpld/db/GR8RAM.asm.rdb index e0520d4..c9a5974 100755 Binary files a/cpld/db/GR8RAM.asm.rdb and b/cpld/db/GR8RAM.asm.rdb differ diff --git a/cpld/db/GR8RAM.asm_labs.ddb b/cpld/db/GR8RAM.asm_labs.ddb index 446edbc..e2fdcce 100755 Binary files a/cpld/db/GR8RAM.asm_labs.ddb and b/cpld/db/GR8RAM.asm_labs.ddb differ diff --git a/cpld/db/GR8RAM.cmp.cdb b/cpld/db/GR8RAM.cmp.cdb index ff3967e..83229eb 100755 Binary files a/cpld/db/GR8RAM.cmp.cdb and b/cpld/db/GR8RAM.cmp.cdb differ diff --git a/cpld/db/GR8RAM.cmp.hdb b/cpld/db/GR8RAM.cmp.hdb index d5623f7..9e1cc63 100755 Binary files a/cpld/db/GR8RAM.cmp.hdb and b/cpld/db/GR8RAM.cmp.hdb differ diff --git a/cpld/db/GR8RAM.cmp.idb b/cpld/db/GR8RAM.cmp.idb index 1b41e0f..de62ad4 100755 Binary files a/cpld/db/GR8RAM.cmp.idb and b/cpld/db/GR8RAM.cmp.idb differ diff --git a/cpld/db/GR8RAM.cmp.rdb b/cpld/db/GR8RAM.cmp.rdb index 4ec2617..f2585de 100755 Binary files a/cpld/db/GR8RAM.cmp.rdb and b/cpld/db/GR8RAM.cmp.rdb differ diff --git a/cpld/db/GR8RAM.cmp0.ddb b/cpld/db/GR8RAM.cmp0.ddb index 65b0bfc..f7d8629 100755 Binary files a/cpld/db/GR8RAM.cmp0.ddb and b/cpld/db/GR8RAM.cmp0.ddb differ diff --git a/cpld/db/GR8RAM.fit.qmsg b/cpld/db/GR8RAM.fit.qmsg index d19197a..bfbad3b 100755 --- a/cpld/db/GR8RAM.fit.qmsg +++ b/cpld/db/GR8RAM.fit.qmsg @@ -1,39 +1,39 @@ -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1618731921844 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1618731921844 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618731921884 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618731921884 ""} -{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1618731921934 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1618731921944 ""} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618731922034 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618731922034 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618731922034 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618731922034 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618731922034 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1618731922034 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1618731922114 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1618731922114 ""} -{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1618731922114 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1618731922114 ""} -{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618731922114 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618731922114 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 C25M " " 1.000 C25M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618731922114 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI0 " " 1.000 PHI0" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618731922114 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1618731922114 ""} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618731922124 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618731922124 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618731922124 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618731922134 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI0 Global clock " "Automatically promoted some destinations of signal \"PHI0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~1 " "Destination \"comb~1\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618731922134 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI0r1 " "Destination \"PHI0r1\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 11 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618731922134 ""} } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618731922134 ""} -{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI0 " "Pin \"PHI0\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { PHI0 } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PHI0" } } } } { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { PHI0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/" { { 0 { 0 ""} 0 369 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1618731922134 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "nRESr Global clock " "Automatically promoted signal \"nRESr\" to use Global clock" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 29 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618731922134 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618731922134 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1618731922134 ""} -{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1618731922144 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1618731922174 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1618731922174 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1618731922174 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1618731922174 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618731922224 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1618731922294 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618731922514 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1618731922524 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1618731923074 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618731923074 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1618731923104 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "34 " "Router estimated average interconnect usage is 34% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "34 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1618731923314 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1618731923314 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618731924004 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.27 " "Total time spent on timing analysis during the Fitter is 0.27 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1618731924014 ""} -{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618731924014 ""} -{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1618731924054 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1618731924104 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "547 " "Peak virtual memory: 547 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618731924124 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 18 03:45:24 2021 " "Processing ended: Sun Apr 18 03:45:24 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618731924124 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618731924124 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618731924124 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1618731924124 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1618739749924 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1618739749924 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618739749974 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618739749974 ""} +{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1618739750014 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1618739750024 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618739750114 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618739750114 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618739750114 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618739750114 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618739750114 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1618739750114 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1618739750204 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1618739750204 ""} +{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1618739750204 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1618739750204 ""} +{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618739750204 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618739750204 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 C25M " " 1.000 C25M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618739750204 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI0 " " 1.000 PHI0" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618739750204 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1618739750204 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618739750214 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618739750214 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618739750214 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618739750224 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI0 Global clock " "Automatically promoted some destinations of signal \"PHI0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~1 " "Destination \"comb~1\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618739750224 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI0r1 " "Destination \"PHI0r1\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 11 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618739750224 ""} } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618739750224 ""} +{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI0 " "Pin \"PHI0\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { PHI0 } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PHI0" } } } } { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { PHI0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/" { { 0 { 0 ""} 0 367 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1618739750224 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "nRESr Global clock " "Automatically promoted signal \"nRESr\" to use Global clock" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 29 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618739750224 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618739750224 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1618739750224 ""} +{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1618739750234 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1618739750264 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1618739750264 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1618739750264 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1618739750264 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618739750314 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1618739750384 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618739750554 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1618739750564 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1618739751074 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618739751074 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1618739751104 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "32 " "Router estimated average interconnect usage is 32% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "32 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 32% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 32% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 32% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1618739751304 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1618739751304 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618739751664 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.22 " "Total time spent on timing analysis during the Fitter is 0.22 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1618739751674 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618739751674 ""} +{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1618739751714 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1618739751754 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "545 " "Peak virtual memory: 545 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618739751784 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 18 05:55:51 2021 " "Processing ended: Sun Apr 18 05:55:51 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618739751784 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618739751784 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618739751784 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1618739751784 ""} diff --git a/cpld/db/GR8RAM.hier_info b/cpld/db/GR8RAM.hier_info index 5435e9b..3894490 100755 --- a/cpld/db/GR8RAM.hier_info +++ b/cpld/db/GR8RAM.hier_info @@ -96,21 +96,16 @@ C25M => nRESr.CLK C25M => nRESr0.CLK C25M => PHI0r2.CLK C25M => PHI0r1.CLK -C25M => IS~9.DATAIN +C25M => IS~7.DATAIN PHI0 => comb.IN1 PHI0 => nWEr.CLK PHI0 => RAMSpecSELr.CLK -PHI0 => ROMSpecSELr.CLK +PHI0 => ROMSpecRDr.CLK PHI0 => PHI0r1.DATAIN nRES => nRESr0.DATAIN nRESout <= nRESout~reg0.DB_MAX_OUTPUT_PORT_TYPE -SetFW[0] => Mux1.IN10 -SetFW[0] => Equal18.IN1 -SetFW[0] => Equal19.IN1 -SetFW[1] => MOSIout.DATAB -SetFW[1] => comb.IN1 -SetFW[1] => Equal18.IN0 -SetFW[1] => Equal19.IN0 +SetFW[0] => ~NO_FANOUT~ +SetFW[1] => ~NO_FANOUT~ RAdir <= INTin => INTout.DATAIN INTout <= INTin.DB_MAX_OUTPUT_PORT_TYPE @@ -131,57 +126,58 @@ nIOSTRB => comb.IN1 nIOSTRB => always5.IN1 RA[0] => DQML.DATAA RA[0] => Equal6.IN3 -RA[0] => Equal9.IN3 -RA[0] => Equal11.IN2 +RA[0] => Equal9.IN1 +RA[0] => Equal10.IN3 +RA[0] => Equal11.IN0 RA[0] => Equal12.IN3 -RA[0] => Equal13.IN3 -RA[0] => Equal14.IN10 +RA[0] => Equal13.IN10 RA[0] => DQMH.DATAA RA[1] => SA.DATAA RA[1] => Equal6.IN2 -RA[1] => Equal9.IN2 +RA[1] => Equal9.IN0 +RA[1] => Equal10.IN0 RA[1] => Equal11.IN3 RA[1] => Equal12.IN2 -RA[1] => Equal13.IN2 -RA[1] => Equal14.IN9 +RA[1] => Equal13.IN9 RA[2] => SA.DATAA RA[2] => Equal6.IN1 -RA[2] => Equal9.IN1 -RA[2] => Equal11.IN1 +RA[2] => Equal9.IN3 +RA[2] => Equal10.IN2 +RA[2] => Equal11.IN2 RA[2] => Equal12.IN1 -RA[2] => Equal13.IN1 -RA[2] => Equal14.IN8 +RA[2] => Equal13.IN8 RA[3] => SA.DATAA RA[3] => Equal6.IN0 -RA[3] => Equal9.IN0 -RA[3] => Equal11.IN0 +RA[3] => Equal9.IN2 +RA[3] => Equal10.IN1 +RA[3] => Equal11.IN1 RA[3] => Equal12.IN0 -RA[3] => Equal13.IN0 -RA[3] => Equal14.IN7 +RA[3] => Equal13.IN7 RA[4] => SA.DATAA -RA[4] => Equal14.IN6 +RA[4] => Equal13.IN6 RA[5] => SA.DATAA -RA[5] => Equal14.IN5 +RA[5] => Equal13.IN5 RA[6] => SA.DATAA -RA[6] => Equal14.IN4 +RA[6] => Equal13.IN4 RA[7] => comb.IN1 RA[7] => SA.DATAA -RA[7] => Equal14.IN3 +RA[7] => Equal13.IN3 RA[8] => SA.DATAA RA[8] => Equal8.IN3 -RA[8] => Equal14.IN2 +RA[8] => Equal13.IN2 RA[9] => SA.DATAA RA[9] => Equal8.IN2 -RA[9] => Equal14.IN1 +RA[9] => Equal13.IN1 RA[10] => SA.DATAA RA[10] => Equal8.IN1 -RA[10] => Equal14.IN0 +RA[10] => Equal13.IN0 RA[11] => SA.DATAA RA[11] => Equal8.IN0 -RA[12] => Equal7.IN1 -RA[13] => Equal7.IN0 -RA[14] => Equal7.IN3 -RA[15] => Equal7.IN2 +RA[12] => Equal7.IN3 +RA[13] => Equal7.IN2 +RA[14] => Equal7.IN1 +RA[15] => Equal7.IN0 +nWE => ROMSpecRD.IN1 nWE => comb.IN1 nWE => nWEr.DATAIN RD[0] <> RD[0] diff --git a/cpld/db/GR8RAM.hif b/cpld/db/GR8RAM.hif index 916cc63..84ea20b 100755 Binary files a/cpld/db/GR8RAM.hif and b/cpld/db/GR8RAM.hif differ diff --git a/cpld/db/GR8RAM.map.cdb b/cpld/db/GR8RAM.map.cdb index b9e18f1..55cc1fe 100755 Binary files a/cpld/db/GR8RAM.map.cdb and b/cpld/db/GR8RAM.map.cdb differ diff --git a/cpld/db/GR8RAM.map.hdb b/cpld/db/GR8RAM.map.hdb index de841a8..b951885 100755 Binary files a/cpld/db/GR8RAM.map.hdb and b/cpld/db/GR8RAM.map.hdb differ diff --git a/cpld/db/GR8RAM.map.qmsg b/cpld/db/GR8RAM.map.qmsg index 965736d..38cee4d 100755 --- a/cpld/db/GR8RAM.map.qmsg +++ b/cpld/db/GR8RAM.map.qmsg @@ -1,19 +1,23 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618731919693 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618731919693 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 18 03:45:19 2021 " "Processing started: Sun Apr 18 03:45:19 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618731919693 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618731919693 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618731919693 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1618731919933 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(93) " "Verilog HDL warning at GR8RAM.v(93): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 93 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618731919973 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(273) " "Verilog HDL warning at GR8RAM.v(273): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 273 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618731919973 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1618731919983 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1618731919983 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1618731920003 ""} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(34) " "Verilog HDL assignment warning at GR8RAM.v(34): truncated value with size 32 to match size of target (14)" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 34 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618731920003 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(117) " "Verilog HDL assignment warning at GR8RAM.v(117): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 117 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618731920003 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(125) " "Verilog HDL assignment warning at GR8RAM.v(125): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 125 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618731920003 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(132) " "Verilog HDL assignment warning at GR8RAM.v(132): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 132 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618731920003 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(324) " "Verilog HDL assignment warning at GR8RAM.v(324): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 324 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618731920013 "|GR8RAM"} -{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 -1 1618731920343 ""} -{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 15 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618731920483 "|GR8RAM|RAdir"} { "Warning" "WMLS_MLS_STUCK_PIN" "nDMAout VCC " "Pin \"nDMAout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 20 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618731920483 "|GR8RAM|nDMAout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nNMIout VCC " "Pin \"nNMIout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 21 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618731920483 "|GR8RAM|nNMIout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nIRQout VCC " "Pin \"nIRQout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 24 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618731920483 "|GR8RAM|nIRQout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nRDYout VCC " "Pin \"nRDYout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618731920483 "|GR8RAM|nRDYout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nINHout VCC " "Pin \"nINHout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 22 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618731920483 "|GR8RAM|nINHout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RWout VCC " "Pin \"RWout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618731920483 "|GR8RAM|RWout"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1618731920483 ""} -{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1618731920733 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "322 " "Implemented 322 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "28 " "Implemented 28 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1618731920743 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1618731920743 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1618731920743 ""} { "Info" "ICUT_CUT_TM_LCELLS" "242 " "Implemented 242 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1618731920743 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1618731920743 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1618731920773 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 14 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 14 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "421 " "Peak virtual memory: 421 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618731920783 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 18 03:45:20 2021 " "Processing ended: Sun Apr 18 03:45:20 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618731920783 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618731920783 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618731920783 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618731920783 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618739747817 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618739747817 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 18 05:55:47 2021 " "Processing started: Sun Apr 18 05:55:47 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618739747817 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618739747817 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618739747817 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1618739748057 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(93) " "Verilog HDL warning at GR8RAM.v(93): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 93 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618739748097 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(274) " "Verilog HDL warning at GR8RAM.v(274): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 274 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618739748097 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1618739748097 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1618739748097 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1618739748127 ""} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "SetRF GR8RAM.v(269) " "Verilog HDL or VHDL warning at GR8RAM.v(269): object \"SetRF\" assigned a value but never read" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 269 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1618739748127 "|GR8RAM"} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "SetLim1M GR8RAM.v(270) " "Verilog HDL or VHDL warning at GR8RAM.v(270): object \"SetLim1M\" assigned a value but never read" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 270 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1618739748127 "|GR8RAM"} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "SetLim8M GR8RAM.v(271) " "Verilog HDL or VHDL warning at GR8RAM.v(271): object \"SetLim8M\" assigned a value but never read" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 271 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1618739748127 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(34) " "Verilog HDL assignment warning at GR8RAM.v(34): truncated value with size 32 to match size of target (14)" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 34 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618739748127 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(117) " "Verilog HDL assignment warning at GR8RAM.v(117): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 117 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618739748127 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(125) " "Verilog HDL assignment warning at GR8RAM.v(125): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 125 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618739748127 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(132) " "Verilog HDL assignment warning at GR8RAM.v(132): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 132 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618739748127 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(325) " "Verilog HDL assignment warning at GR8RAM.v(325): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 325 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618739748137 "|GR8RAM"} +{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 -1 1618739748487 ""} +{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 15 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618739748597 "|GR8RAM|RAdir"} { "Warning" "WMLS_MLS_STUCK_PIN" "nDMAout VCC " "Pin \"nDMAout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 20 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618739748597 "|GR8RAM|nDMAout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nNMIout VCC " "Pin \"nNMIout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 21 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618739748597 "|GR8RAM|nNMIout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nIRQout VCC " "Pin \"nIRQout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 24 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618739748597 "|GR8RAM|nIRQout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nRDYout VCC " "Pin \"nRDYout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618739748597 "|GR8RAM|nRDYout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nINHout VCC " "Pin \"nINHout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 22 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618739748597 "|GR8RAM|nINHout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RWout VCC " "Pin \"RWout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618739748597 "|GR8RAM|RWout"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1618739748597 ""} +{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1618739748817 ""} +{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SetFW\[0\] " "No output dependent on input pin \"SetFW\[0\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 267 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1618739748827 "|GR8RAM|SetFW[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SetFW\[1\] " "No output dependent on input pin \"SetFW\[1\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 267 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1618739748827 "|GR8RAM|SetFW[1]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1618739748827 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "306 " "Implemented 306 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "28 " "Implemented 28 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1618739748827 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1618739748827 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1618739748827 ""} { "Info" "ICUT_CUT_TM_LCELLS" "226 " "Implemented 226 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1618739748827 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1618739748827 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1618739748857 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 20 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 20 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "421 " "Peak virtual memory: 421 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618739748877 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 18 05:55:48 2021 " "Processing ended: Sun Apr 18 05:55:48 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618739748877 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618739748877 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618739748877 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618739748877 ""} diff --git a/cpld/db/GR8RAM.map.rdb b/cpld/db/GR8RAM.map.rdb index 90b3b8b..1b23c9b 100755 Binary files a/cpld/db/GR8RAM.map.rdb and b/cpld/db/GR8RAM.map.rdb differ diff --git a/cpld/db/GR8RAM.pre_map.hdb b/cpld/db/GR8RAM.pre_map.hdb index ee4aba8..5415eab 100755 Binary files a/cpld/db/GR8RAM.pre_map.hdb and b/cpld/db/GR8RAM.pre_map.hdb differ diff --git a/cpld/db/GR8RAM.root_partition.map.reg_db.cdb b/cpld/db/GR8RAM.root_partition.map.reg_db.cdb index 5a362d9..2594dc9 100755 Binary files a/cpld/db/GR8RAM.root_partition.map.reg_db.cdb and b/cpld/db/GR8RAM.root_partition.map.reg_db.cdb differ diff --git a/cpld/db/GR8RAM.routing.rdb b/cpld/db/GR8RAM.routing.rdb index 24be5cf..d150b82 100755 Binary files a/cpld/db/GR8RAM.routing.rdb and b/cpld/db/GR8RAM.routing.rdb differ diff --git a/cpld/db/GR8RAM.rtlv.hdb b/cpld/db/GR8RAM.rtlv.hdb index 57571df..409f7ec 100755 Binary files a/cpld/db/GR8RAM.rtlv.hdb and b/cpld/db/GR8RAM.rtlv.hdb differ diff --git a/cpld/db/GR8RAM.rtlv_sg.cdb b/cpld/db/GR8RAM.rtlv_sg.cdb index 7795cd5..a1997f0 100755 Binary files a/cpld/db/GR8RAM.rtlv_sg.cdb and b/cpld/db/GR8RAM.rtlv_sg.cdb differ diff --git a/cpld/db/GR8RAM.sgdiff.cdb b/cpld/db/GR8RAM.sgdiff.cdb index aa0263e..dbec63e 100755 Binary files a/cpld/db/GR8RAM.sgdiff.cdb and b/cpld/db/GR8RAM.sgdiff.cdb differ diff --git a/cpld/db/GR8RAM.sgdiff.hdb b/cpld/db/GR8RAM.sgdiff.hdb index 4370539..3aa204c 100755 Binary files a/cpld/db/GR8RAM.sgdiff.hdb and b/cpld/db/GR8RAM.sgdiff.hdb differ diff --git a/cpld/db/GR8RAM.smp_dump.txt b/cpld/db/GR8RAM.smp_dump.txt index 365c18b..8062576 100755 --- a/cpld/db/GR8RAM.smp_dump.txt +++ b/cpld/db/GR8RAM.smp_dump.txt @@ -3,8 +3,6 @@ State Machine - |GR8RAM|IS Name IS.state_bit_2 IS.state_bit_1 IS.state_bit_0 IS.000 0 0 0 IS.001 0 0 1 -IS.010 1 1 0 -IS.011 1 1 1 IS.100 1 0 0 IS.101 1 0 1 IS.110 0 1 0 diff --git a/cpld/db/GR8RAM.sta.qmsg b/cpld/db/GR8RAM.sta.qmsg index 4a67a64..34bd00c 100755 --- a/cpld/db/GR8RAM.sta.qmsg +++ b/cpld/db/GR8RAM.sta.qmsg @@ -1,23 +1,23 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618731926284 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618731926284 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 18 03:45:26 2021 " "Processing started: Sun Apr 18 03:45:26 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618731926284 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618731926284 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618731926284 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1618731926354 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1618731926464 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618731926504 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618731926504 ""} -{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1618731926554 ""} -{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1618731926884 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1618731926924 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1618731926924 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C25M C25M " "create_clock -period 1.000 -name C25M C25M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618731926934 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI0 PHI0 " "create_clock -period 1.000 -name PHI0 PHI0" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618731926934 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618731926934 ""} -{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1618731926934 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1618731926944 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -9.691 " "Worst-case setup slack is -9.691" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731926944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731926944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.691 -732.295 C25M " " -9.691 -732.295 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731926944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.358 -1.358 PHI0 " " -1.358 -1.358 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731926944 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618731926944 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.092 " "Worst-case hold slack is 1.092" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731926944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731926944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.092 0.000 PHI0 " " 1.092 0.000 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731926944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.418 0.000 C25M " " 1.418 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731926944 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618731926944 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -5.009 " "Worst-case recovery slack is -5.009" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731926944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731926944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.009 -150.270 C25M " " -5.009 -150.270 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731926944 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618731926944 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "removal 5.455 " "Worst-case removal slack is 5.455" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731926954 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731926954 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 5.455 0.000 C25M " " 5.455 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731926954 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618731926954 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.289 " "Worst-case minimum pulse width slack is -2.289" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731926954 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731926954 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 C25M " " -2.289 -2.289 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731926954 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI0 " " -2.289 -2.289 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731926954 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618731926954 ""} -{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1618731926994 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618731927004 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618731927004 ""} -{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 3 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "368 " "Peak virtual memory: 368 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618731927044 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 18 03:45:27 2021 " "Processing ended: Sun Apr 18 03:45:27 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618731927044 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618731927044 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618731927044 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618731927044 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618739753974 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618739753974 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 18 05:55:53 2021 " "Processing started: Sun Apr 18 05:55:53 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618739753974 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618739753974 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618739753974 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1618739754034 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1618739754144 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618739754194 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618739754194 ""} +{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1618739754234 ""} +{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1618739754544 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1618739754584 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1618739754584 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C25M C25M " "create_clock -period 1.000 -name C25M C25M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618739754584 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI0 PHI0 " "create_clock -period 1.000 -name PHI0 PHI0" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618739754584 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618739754584 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1618739754584 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1618739754594 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -9.431 " "Worst-case setup slack is -9.431" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618739754594 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618739754594 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.431 -683.489 C25M " " -9.431 -683.489 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618739754594 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.421 -1.421 PHI0 " " -1.421 -1.421 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618739754594 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618739754594 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.384 " "Worst-case hold slack is 1.384" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618739754604 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618739754604 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.384 0.000 C25M " " 1.384 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618739754604 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.867 0.000 PHI0 " " 1.867 0.000 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618739754604 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618739754604 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -4.406 " "Worst-case recovery slack is -4.406" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618739754604 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618739754604 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.406 -132.180 C25M " " -4.406 -132.180 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618739754604 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618739754604 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "removal 4.852 " "Worst-case removal slack is 4.852" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618739754604 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618739754604 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.852 0.000 C25M " " 4.852 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618739754604 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618739754604 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.289 " "Worst-case minimum pulse width slack is -2.289" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618739754604 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618739754604 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 C25M " " -2.289 -2.289 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618739754604 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI0 " " -2.289 -2.289 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618739754604 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618739754604 ""} +{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1618739754644 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618739754654 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618739754654 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 3 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "368 " "Peak virtual memory: 368 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618739754694 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 18 05:55:54 2021 " "Processing ended: Sun Apr 18 05:55:54 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618739754694 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618739754694 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618739754694 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618739754694 ""} diff --git a/cpld/db/GR8RAM.sta.rdb b/cpld/db/GR8RAM.sta.rdb index 852f1d0..e2eaba9 100755 Binary files a/cpld/db/GR8RAM.sta.rdb and b/cpld/db/GR8RAM.sta.rdb differ diff --git a/cpld/db/GR8RAM.sta_cmp.5_slow.tdb b/cpld/db/GR8RAM.sta_cmp.5_slow.tdb index 66a297d..4c29540 100755 Binary files a/cpld/db/GR8RAM.sta_cmp.5_slow.tdb and b/cpld/db/GR8RAM.sta_cmp.5_slow.tdb differ diff --git a/cpld/db/GR8RAM.vpr.ammdb b/cpld/db/GR8RAM.vpr.ammdb index 8b5e92d..82e64e5 100755 Binary files a/cpld/db/GR8RAM.vpr.ammdb and b/cpld/db/GR8RAM.vpr.ammdb differ diff --git a/cpld/db/logic_util_heursitic.dat b/cpld/db/logic_util_heursitic.dat index 85e389e..5df7f72 100755 Binary files a/cpld/db/logic_util_heursitic.dat and b/cpld/db/logic_util_heursitic.dat differ diff --git a/cpld/db/prev_cmp_GR8RAM.qmsg b/cpld/db/prev_cmp_GR8RAM.qmsg index cf8b012..945e82f 100755 --- a/cpld/db/prev_cmp_GR8RAM.qmsg +++ b/cpld/db/prev_cmp_GR8RAM.qmsg @@ -1,100 +1,99 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618731317099 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618731317099 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 18 03:35:16 2021 " "Processing started: Sun Apr 18 03:35:16 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618731317099 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618731317099 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618731317099 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1618731317329 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(93) " "Verilog HDL warning at GR8RAM.v(93): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 93 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618731317379 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(273) " "Verilog HDL warning at GR8RAM.v(273): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 273 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618731317379 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1618731317379 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1618731317379 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1618731317409 ""} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(34) " "Verilog HDL assignment warning at GR8RAM.v(34): truncated value with size 32 to match size of target (14)" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 34 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618731317409 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(117) " "Verilog HDL assignment warning at GR8RAM.v(117): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 117 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618731317409 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(125) " "Verilog HDL assignment warning at GR8RAM.v(125): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 125 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618731317409 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(132) " "Verilog HDL assignment warning at GR8RAM.v(132): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 132 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618731317409 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(324) " "Verilog HDL assignment warning at GR8RAM.v(324): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 324 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618731317409 "|GR8RAM"} -{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 -1 1618731317749 ""} -{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 15 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618731317889 "|GR8RAM|RAdir"} { "Warning" "WMLS_MLS_STUCK_PIN" "nDMAout VCC " "Pin \"nDMAout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 20 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618731317889 "|GR8RAM|nDMAout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nNMIout VCC " "Pin \"nNMIout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 21 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618731317889 "|GR8RAM|nNMIout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nIRQout VCC " "Pin \"nIRQout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 24 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618731317889 "|GR8RAM|nIRQout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nRDYout VCC " "Pin \"nRDYout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618731317889 "|GR8RAM|nRDYout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nINHout VCC " "Pin \"nINHout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 22 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618731317889 "|GR8RAM|nINHout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RWout VCC " "Pin \"RWout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618731317889 "|GR8RAM|RWout"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1618731317889 ""} -{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1618731318139 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "322 " "Implemented 322 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "28 " "Implemented 28 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1618731318149 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1618731318149 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1618731318149 ""} { "Info" "ICUT_CUT_TM_LCELLS" "242 " "Implemented 242 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1618731318149 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1618731318149 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1618731318179 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 14 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 14 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "421 " "Peak virtual memory: 421 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618731318199 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 18 03:35:18 2021 " "Processing ended: Sun Apr 18 03:35:18 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618731318199 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618731318199 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618731318199 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618731318199 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618731319149 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 64-Bit " "Running Quartus II 64-Bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618731319149 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 18 03:35:18 2021 " "Processing started: Sun Apr 18 03:35:18 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618731319149 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1618731319149 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1618731319149 ""} -{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1618731319209 ""} -{ "Info" "0" "" "Project = GR8RAM" { } { } 0 0 "Project = GR8RAM" 0 0 "Fitter" 0 0 1618731319209 ""} -{ "Info" "0" "" "Revision = GR8RAM" { } { } 0 0 "Revision = GR8RAM" 0 0 "Fitter" 0 0 1618731319209 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1618731319249 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1618731319249 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618731319289 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618731319289 ""} -{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1618731319339 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1618731319349 ""} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618731319439 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618731319439 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618731319439 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618731319439 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618731319439 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1618731319439 ""} -{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "2 80 " "No exact pin location assignment(s) for 2 pins of 80 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DMAout " "Pin DMAout not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DMAout } } } { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 19 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DMAout } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/" { { 0 { 0 ""} 0 374 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1618731319459 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RDdir " "Pin RDdir not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { RDdir } } } { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 96 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { RDdir } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/" { { 0 { 0 ""} 0 385 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1618731319459 ""} } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1618731319459 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1618731319519 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1618731319519 ""} -{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1618731319529 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1618731319529 ""} -{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618731319529 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618731319529 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 C25M " " 1.000 C25M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618731319529 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI0 " " 1.000 PHI0" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618731319529 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1618731319529 ""} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618731319529 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618731319529 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618731319529 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618731319539 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI0 Global clock " "Automatically promoted some destinations of signal \"PHI0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~1 " "Destination \"comb~1\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618731319539 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI0r1 " "Destination \"PHI0r1\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 11 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618731319539 ""} } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618731319539 ""} -{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI0 " "Pin \"PHI0\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { PHI0 } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PHI0" } } } } { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { PHI0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/" { { 0 { 0 ""} 0 368 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1618731319539 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "nRESr Global clock " "Automatically promoted signal \"nRESr\" to use Global clock" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 29 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618731319539 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618731319539 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1618731319539 ""} -{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1618731319559 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1618731319579 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1618731319579 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1618731319579 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1618731319579 ""} -{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "2 unused 3.3V 0 2 0 " "Number of I/O pins in group: 2 (unused VREF, 3.3V VCCIO, 0 input, 2 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "I/O standards used: 3.3-V LVTTL." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1618731319599 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1618731319599 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1618731319599 ""} -{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.3V 36 2 " "I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 36 total pin(s) used -- 2 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1618731319599 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use 3.3V 42 0 " "I/O bank number 2 does not use VREF pins and has 3.3V VCCIO pins. 42 total pin(s) used -- 0 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1618731319599 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1618731319599 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1618731319599 ""} -{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "Ddir " "Node \"Ddir\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "Ddir" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1618731319629 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1618731319629 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618731319629 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1618731319699 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618731319919 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1618731319929 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1618731320523 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618731320523 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1618731320553 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "34 " "Router estimated average interconnect usage is 34% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "34 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1618731320763 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1618731320763 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618731321393 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.27 " "Total time spent on timing analysis during the Fitter is 0.27 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1618731321393 ""} -{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618731321403 ""} -{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1618731321443 ""} -{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1618731321443 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1618731321483 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 8 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "545 " "Peak virtual memory: 545 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618731321513 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 18 03:35:21 2021 " "Processing ended: Sun Apr 18 03:35:21 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618731321513 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618731321513 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618731321513 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1618731321513 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1618731322373 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618731322373 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 18 03:35:22 2021 " "Processing started: Sun Apr 18 03:35:22 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618731322373 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1618731322373 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1618731322373 ""} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1618731322563 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1618731322573 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "381 " "Peak virtual memory: 381 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618731322703 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 18 03:35:22 2021 " "Processing ended: Sun Apr 18 03:35:22 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618731322703 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618731322703 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618731322703 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1618731322703 ""} -{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1618731323273 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1618731323653 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618731323653 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 18 03:35:23 2021 " "Processing started: Sun Apr 18 03:35:23 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618731323653 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618731323653 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618731323653 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1618731323723 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1618731323823 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618731323873 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618731323873 ""} -{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1618731323923 ""} -{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1618731324243 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1618731324283 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1618731324283 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C25M C25M " "create_clock -period 1.000 -name C25M C25M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618731324283 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI0 PHI0 " "create_clock -period 1.000 -name PHI0 PHI0" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618731324283 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618731324283 ""} -{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1618731324283 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1618731324293 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -10.039 " "Worst-case setup slack is -10.039" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731324303 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731324303 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -10.039 -703.074 C25M " " -10.039 -703.074 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731324303 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.227 -1.227 PHI0 " " -1.227 -1.227 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731324303 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618731324303 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.063 " "Worst-case hold slack is 1.063" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731324303 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731324303 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.063 0.000 PHI0 " " 1.063 0.000 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731324303 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.544 0.000 C25M " " 1.544 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731324303 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618731324303 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -4.399 " "Worst-case recovery slack is -4.399" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731324303 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731324303 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.399 -131.970 C25M " " -4.399 -131.970 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731324303 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618731324303 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "removal 4.845 " "Worst-case removal slack is 4.845" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731324303 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731324303 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.845 0.000 C25M " " 4.845 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731324303 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618731324303 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.289 " "Worst-case minimum pulse width slack is -2.289" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731324303 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731324303 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 C25M " " -2.289 -2.289 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731324303 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI0 " " -2.289 -2.289 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618731324303 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618731324303 ""} -{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1618731324353 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618731324363 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618731324363 ""} -{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 3 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "368 " "Peak virtual memory: 368 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618731324393 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 18 03:35:24 2021 " "Processing ended: Sun Apr 18 03:35:24 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618731324393 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618731324393 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618731324393 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618731324393 ""} -{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 25 s " "Quartus II Full Compilation was successful. 0 errors, 25 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618731324988 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618739560494 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618739560494 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 18 05:52:40 2021 " "Processing started: Sun Apr 18 05:52:40 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618739560494 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618739560494 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618739560494 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1618739560724 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(93) " "Verilog HDL warning at GR8RAM.v(93): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 93 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618739560774 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(274) " "Verilog HDL warning at GR8RAM.v(274): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 274 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618739560774 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1618739560774 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1618739560774 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1618739560804 ""} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "SetRF GR8RAM.v(269) " "Verilog HDL or VHDL warning at GR8RAM.v(269): object \"SetRF\" assigned a value but never read" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 269 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1618739560804 "|GR8RAM"} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "SetLim1M GR8RAM.v(270) " "Verilog HDL or VHDL warning at GR8RAM.v(270): object \"SetLim1M\" assigned a value but never read" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 270 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1618739560804 "|GR8RAM"} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "SetLim8M GR8RAM.v(271) " "Verilog HDL or VHDL warning at GR8RAM.v(271): object \"SetLim8M\" assigned a value but never read" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 271 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1618739560804 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(34) " "Verilog HDL assignment warning at GR8RAM.v(34): truncated value with size 32 to match size of target (14)" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 34 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618739560804 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(117) " "Verilog HDL assignment warning at GR8RAM.v(117): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 117 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618739560804 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(125) " "Verilog HDL assignment warning at GR8RAM.v(125): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 125 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618739560804 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(132) " "Verilog HDL assignment warning at GR8RAM.v(132): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 132 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618739560814 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(325) " "Verilog HDL assignment warning at GR8RAM.v(325): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 325 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618739560814 "|GR8RAM"} +{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 -1 1618739561164 ""} +{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 15 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618739561274 "|GR8RAM|RAdir"} { "Warning" "WMLS_MLS_STUCK_PIN" "nDMAout VCC " "Pin \"nDMAout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 20 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618739561274 "|GR8RAM|nDMAout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nNMIout VCC " "Pin \"nNMIout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 21 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618739561274 "|GR8RAM|nNMIout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nIRQout VCC " "Pin \"nIRQout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 24 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618739561274 "|GR8RAM|nIRQout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nRDYout VCC " "Pin \"nRDYout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618739561274 "|GR8RAM|nRDYout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nINHout VCC " "Pin \"nINHout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 22 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618739561274 "|GR8RAM|nINHout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RWout VCC " "Pin \"RWout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618739561274 "|GR8RAM|RWout"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1618739561274 ""} +{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1618739561494 ""} +{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SetFW\[0\] " "No output dependent on input pin \"SetFW\[0\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 267 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1618739561504 "|GR8RAM|SetFW[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SetFW\[1\] " "No output dependent on input pin \"SetFW\[1\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 267 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1618739561504 "|GR8RAM|SetFW[1]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1618739561504 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "308 " "Implemented 308 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "28 " "Implemented 28 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1618739561504 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1618739561504 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1618739561504 ""} { "Info" "ICUT_CUT_TM_LCELLS" "228 " "Implemented 228 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1618739561504 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1618739561504 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1618739561534 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 20 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 20 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "421 " "Peak virtual memory: 421 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618739561554 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 18 05:52:41 2021 " "Processing ended: Sun Apr 18 05:52:41 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618739561554 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618739561554 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618739561554 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618739561554 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618739562534 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 64-Bit " "Running Quartus II 64-Bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618739562534 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 18 05:52:42 2021 " "Processing started: Sun Apr 18 05:52:42 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618739562534 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1618739562534 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1618739562534 ""} +{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1618739562594 ""} +{ "Info" "0" "" "Project = GR8RAM" { } { } 0 0 "Project = GR8RAM" 0 0 "Fitter" 0 0 1618739562594 ""} +{ "Info" "0" "" "Revision = GR8RAM" { } { } 0 0 "Revision = GR8RAM" 0 0 "Fitter" 0 0 1618739562604 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1618739562634 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1618739562644 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618739562684 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618739562684 ""} +{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1618739562724 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1618739562734 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618739562824 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618739562824 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618739562824 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618739562824 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618739562824 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1618739562824 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1618739562904 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1618739562904 ""} +{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1618739562914 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1618739562914 ""} +{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618739562914 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618739562914 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 C25M " " 1.000 C25M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618739562914 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI0 " " 1.000 PHI0" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618739562914 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1618739562914 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618739562914 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618739562914 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618739562914 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618739562924 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI0 Global clock " "Automatically promoted some destinations of signal \"PHI0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~1 " "Destination \"comb~1\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618739562924 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI0r1 " "Destination \"PHI0r1\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 11 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618739562924 ""} } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618739562924 ""} +{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI0 " "Pin \"PHI0\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { PHI0 } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PHI0" } } } } { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { PHI0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/" { { 0 { 0 ""} 0 367 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1618739562924 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "nRESr Global clock " "Automatically promoted signal \"nRESr\" to use Global clock" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 29 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618739562924 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618739562924 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1618739562924 ""} +{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1618739562944 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1618739562964 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1618739562964 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1618739562964 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1618739562964 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618739563014 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1618739563084 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618739563264 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1618739563274 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1618739563754 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618739563754 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1618739563784 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "32 " "Router estimated average interconnect usage is 32% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "32 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 32% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 32% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 32% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1618739563994 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1618739563994 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618739564304 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.19 " "Total time spent on timing analysis during the Fitter is 0.19 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1618739564314 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618739564314 ""} +{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1618739564354 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1618739564394 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "546 " "Peak virtual memory: 546 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618739564424 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 18 05:52:44 2021 " "Processing ended: Sun Apr 18 05:52:44 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618739564424 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618739564424 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618739564424 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1618739564424 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1618739565276 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618739565276 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 18 05:52:45 2021 " "Processing started: Sun Apr 18 05:52:45 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618739565276 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1618739565276 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1618739565276 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1618739565478 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1618739565478 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "381 " "Peak virtual memory: 381 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618739565618 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 18 05:52:45 2021 " "Processing ended: Sun Apr 18 05:52:45 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618739565618 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618739565618 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618739565618 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1618739565618 ""} +{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1618739566178 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1618739566556 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618739566556 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 18 05:52:46 2021 " "Processing started: Sun Apr 18 05:52:46 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618739566556 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618739566556 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618739566556 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1618739566616 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1618739566731 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618739566776 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618739566776 ""} +{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1618739566821 ""} +{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1618739567110 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1618739567150 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1618739567150 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C25M C25M " "create_clock -period 1.000 -name C25M C25M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618739567150 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI0 PHI0 " "create_clock -period 1.000 -name PHI0 PHI0" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618739567150 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618739567150 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1618739567150 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1618739567160 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -9.149 " "Worst-case setup slack is -9.149" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618739567170 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618739567170 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.149 -686.968 C25M " " -9.149 -686.968 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618739567170 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.511 0.000 PHI0 " " 0.511 0.000 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618739567170 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618739567170 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.065 " "Worst-case hold slack is -0.065" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618739567170 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618739567170 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.065 -0.065 PHI0 " " -0.065 -0.065 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618739567170 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.402 0.000 C25M " " 1.402 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618739567170 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618739567170 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -4.389 " "Worst-case recovery slack is -4.389" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618739567170 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618739567170 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.389 -131.670 C25M " " -4.389 -131.670 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618739567170 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618739567170 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "removal 4.835 " "Worst-case removal slack is 4.835" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618739567170 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618739567170 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.835 0.000 C25M " " 4.835 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618739567170 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618739567170 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.289 " "Worst-case minimum pulse width slack is -2.289" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618739567170 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618739567170 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 C25M " " -2.289 -2.289 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618739567170 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI0 " " -2.289 -2.289 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618739567170 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618739567170 ""} +{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1618739567220 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618739567230 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618739567230 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 3 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "368 " "Peak virtual memory: 368 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618739567260 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 18 05:52:47 2021 " "Processing ended: Sun Apr 18 05:52:47 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618739567260 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618739567260 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618739567260 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618739567260 ""} +{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 27 s " "Quartus II Full Compilation was successful. 0 errors, 27 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618739567855 ""} diff --git a/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt b/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt index 0052843..18e82ce 100755 Binary files a/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt and b/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt differ diff --git a/cpld/output_files/GR8RAM.asm.rpt b/cpld/output_files/GR8RAM.asm.rpt index 042a03c..f10fb9f 100755 --- a/cpld/output_files/GR8RAM.asm.rpt +++ b/cpld/output_files/GR8RAM.asm.rpt @@ -1,5 +1,5 @@ Assembler report for GR8RAM -Sun Apr 18 03:45:25 2021 +Sun Apr 18 05:55:52 2021 Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition @@ -37,7 +37,7 @@ applicable agreement for further details. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Sun Apr 18 03:45:25 2021 ; +; Assembler Status ; Successful - Sun Apr 18 05:55:52 2021 ; ; Revision Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ; ; Family ; MAX II ; @@ -90,8 +90,8 @@ applicable agreement for further details. ; Option ; Setting ; +----------------+----------------------------------------------------------------------------+ ; Device ; EPM240T100C5 ; -; JTAG usercode ; 0x0015FC20 ; -; Checksum ; 0x00160180 ; +; JTAG usercode ; 0x00164957 ; +; Checksum ; 0x00164C57 ; +----------------+----------------------------------------------------------------------------+ @@ -101,14 +101,14 @@ applicable agreement for further details. Info: ******************************************************************* Info: Running Quartus II 64-Bit Assembler Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - Info: Processing started: Sun Apr 18 03:45:24 2021 + Info: Processing started: Sun Apr 18 05:55:52 2021 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM Info (115031): Writing out detailed assembly data for power analysis Info (115030): Assembler is generating device programming files Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings Info: Peak virtual memory: 381 megabytes - Info: Processing ended: Sun Apr 18 03:45:25 2021 - Info: Elapsed time: 00:00:01 + Info: Processing ended: Sun Apr 18 05:55:52 2021 + Info: Elapsed time: 00:00:00 Info: Total CPU time (on all processors): 00:00:00 diff --git a/cpld/output_files/GR8RAM.cdf b/cpld/output_files/GR8RAM.cdf index fb7cb58..1622d9c 100644 --- a/cpld/output_files/GR8RAM.cdf +++ b/cpld/output_files/GR8RAM.cdf @@ -3,8 +3,8 @@ JedecChain; FileRevision(JESD32A); DefaultMfr(6E); - P ActionCode(Vfy) - Device PartName(EPM240T100) Path("C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/") File("GR8RAM.pof") MfrSpec(OpMask(2) SEC_Device(EPM240T100) Child_OpMask(2 2 2)); + P ActionCode(Cfg) + Device PartName(EPM240T100) Path("C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/") File("GR8RAM.pof") MfrSpec(OpMask(3) SEC_Device(EPM240T100) Child_OpMask(2 3 3)); ChainEnd; diff --git a/cpld/output_files/GR8RAM.done b/cpld/output_files/GR8RAM.done index 3bdf1c8..3e3e291 100755 --- a/cpld/output_files/GR8RAM.done +++ b/cpld/output_files/GR8RAM.done @@ -1 +1 @@ -Sun Apr 18 03:45:27 2021 +Sun Apr 18 05:55:55 2021 diff --git a/cpld/output_files/GR8RAM.fit.rpt b/cpld/output_files/GR8RAM.fit.rpt index d075299..cf490b5 100755 --- a/cpld/output_files/GR8RAM.fit.rpt +++ b/cpld/output_files/GR8RAM.fit.rpt @@ -1,5 +1,5 @@ Fitter report for GR8RAM -Sun Apr 18 03:45:24 2021 +Sun Apr 18 05:55:51 2021 Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition @@ -30,10 +30,8 @@ Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit 22. LAB Signals Sourced Out 23. LAB Distinct Inputs 24. Fitter Device Options - 25. Estimated Delay Added for Hold Timing Summary - 26. Estimated Delay Added for Hold Timing Details - 27. Fitter Messages - 28. Fitter Suppressed Messages + 25. Fitter Messages + 26. Fitter Suppressed Messages @@ -59,14 +57,14 @@ applicable agreement for further details. +-----------------------------------------------------------------------------+ ; Fitter Summary ; +---------------------------+-------------------------------------------------+ -; Fitter Status ; Successful - Sun Apr 18 03:45:24 2021 ; +; Fitter Status ; Successful - Sun Apr 18 05:55:51 2021 ; ; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; ; Revision Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ; ; Family ; MAX II ; ; Device ; EPM240T100C5 ; ; Timing Models ; Final ; -; Total logic elements ; 229 / 240 ( 95 % ) ; +; Total logic elements ; 220 / 240 ( 92 % ) ; ; Total pins ; 80 / 80 ( 100 % ) ; ; Total virtual pins ; 0 ; ; UFM blocks ; 0 / 1 ( 0 % ) ; @@ -144,24 +142,24 @@ The pin-out file can be found in C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/outpu +---------------------------------------------+--------------------+ ; Resource ; Usage ; +---------------------------------------------+--------------------+ -; Total logic elements ; 229 / 240 ( 95 % ) ; -; -- Combinational with no register ; 126 ; +; Total logic elements ; 220 / 240 ( 92 % ) ; +; -- Combinational with no register ; 117 ; ; -- Register only ; 1 ; ; -- Combinational with a register ; 102 ; ; ; ; ; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 135 ; -; -- 3 input functions ; 30 ; -; -- 2 input functions ; 63 ; +; -- 4 input functions ; 114 ; +; -- 3 input functions ; 46 ; +; -- 2 input functions ; 59 ; ; -- 1 input functions ; 0 ; ; -- 0 input functions ; 0 ; ; ; ; ; Logic elements by mode ; ; -; -- normal mode ; 196 ; +; -- normal mode ; 187 ; ; -- arithmetic mode ; 33 ; -; -- qfbk mode ; 4 ; +; -- qfbk mode ; 3 ; ; -- register cascade mode ; 0 ; -; -- synchronous clear/load mode ; 47 ; +; -- synchronous clear/load mode ; 49 ; ; -- asynchronous clear/load mode ; 30 ; ; ; ; ; Total registers ; 103 / 240 ( 43 % ) ; @@ -175,12 +173,12 @@ The pin-out file can be found in C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/outpu ; UFM blocks ; 0 / 1 ( 0 % ) ; ; Global clocks ; 3 / 4 ( 75 % ) ; ; JTAGs ; 0 / 1 ( 0 % ) ; -; Average interconnect usage (total/H/V) ; 51% / 57% / 44% ; -; Peak interconnect usage (total/H/V) ; 51% / 57% / 44% ; +; Average interconnect usage (total/H/V) ; 44% / 49% / 37% ; +; Peak interconnect usage (total/H/V) ; 44% / 49% / 37% ; ; Maximum fan-out ; 100 ; -; Highest non-global fan-out ; 50 ; -; Total fan-out ; 1064 ; -; Average fan-out ; 3.44 ; +; Highest non-global fan-out ; 55 ; +; Total fan-out ; 1024 ; +; Average fan-out ; 3.41 ; +---------------------------------------------+--------------------+ @@ -194,14 +192,14 @@ The pin-out file can be found in C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/outpu ; INTin ; 49 ; 1 ; 7 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; ; MISO ; 16 ; 1 ; 1 ; 2 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; ; PHI0 ; 41 ; 1 ; 5 ; 0 ; 1 ; 5 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; RA[0] ; 100 ; 2 ; 2 ; 5 ; 2 ; 10 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; +; RA[0] ; 100 ; 2 ; 2 ; 5 ; 2 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; ; RA[10] ; 14 ; 1 ; 1 ; 2 ; 0 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; ; RA[11] ; 34 ; 1 ; 3 ; 0 ; 1 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; ; RA[12] ; 35 ; 1 ; 3 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; ; RA[13] ; 36 ; 1 ; 4 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; ; RA[14] ; 37 ; 1 ; 4 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; ; RA[15] ; 38 ; 1 ; 4 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; RA[1] ; 98 ; 2 ; 2 ; 5 ; 0 ; 10 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; +; RA[1] ; 98 ; 2 ; 2 ; 5 ; 0 ; 7 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; ; RA[2] ; 97 ; 2 ; 3 ; 5 ; 3 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; ; RA[3] ; 4 ; 1 ; 1 ; 4 ; 2 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; ; RA[4] ; 1 ; 2 ; 2 ; 5 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; @@ -210,13 +208,13 @@ The pin-out file can be found in C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/outpu ; RA[7] ; 6 ; 1 ; 1 ; 3 ; 0 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; ; RA[8] ; 7 ; 1 ; 1 ; 3 ; 1 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; ; RA[9] ; 8 ; 1 ; 1 ; 3 ; 2 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; SetFW[0] ; 96 ; 2 ; 3 ; 5 ; 2 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; SetFW[1] ; 95 ; 2 ; 3 ; 5 ; 1 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; +; SetFW[0] ; 96 ; 2 ; 3 ; 5 ; 2 ; 0 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; +; SetFW[1] ; 95 ; 2 ; 3 ; 5 ; 1 ; 0 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; ; nDEVSEL ; 40 ; 1 ; 5 ; 0 ; 2 ; 4 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; ; nIOSEL ; 39 ; 1 ; 5 ; 0 ; 3 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; ; nIOSTRB ; 42 ; 1 ; 5 ; 0 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; ; nRES ; 44 ; 1 ; 6 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; nWE ; 43 ; 1 ; 6 ; 0 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; +; nWE ; 43 ; 1 ; 6 ; 0 ; 3 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; +----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+ @@ -249,17 +247,17 @@ The pin-out file can be found in C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/outpu ; SA[9] ; 72 ; 2 ; 8 ; 4 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; ; SBA[0] ; 69 ; 2 ; 8 ; 3 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; ; SBA[1] ; 71 ; 2 ; 8 ; 4 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; -; nCAS ; 61 ; 2 ; 8 ; 2 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; +; nCAS ; 61 ; 2 ; 8 ; 2 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; - ; - ; ; nDMAout ; 21 ; 1 ; 1 ; 1 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; ; nFCS ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; no ; no ; no ; yes ; no ; On ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; ; nINHout ; 27 ; 1 ; 2 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; ; nIRQout ; 29 ; 1 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; ; nNMIout ; 26 ; 1 ; 2 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; -; nRAS ; 62 ; 2 ; 8 ; 2 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; +; nRAS ; 62 ; 2 ; 8 ; 2 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; - ; - ; ; nRCS ; 67 ; 2 ; 8 ; 3 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; ; nRDYout ; 28 ; 1 ; 2 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; ; nRESout ; 30 ; 1 ; 3 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; -; nSWE ; 58 ; 2 ; 8 ; 2 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; +; nSWE ; 58 ; 2 ; 8 ; 2 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; - ; - ; +---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ @@ -270,8 +268,8 @@ The pin-out file can be found in C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/outpu +-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ ; MOSI ; 15 ; 1 ; 1 ; 2 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; MOSIOE ; - ; ; RD[0] ; 86 ; 2 ; 5 ; 5 ; 1 ; 5 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; comb~1 ; - ; -; RD[1] ; 87 ; 2 ; 5 ; 5 ; 2 ; 4 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; comb~1 ; - ; -; RD[2] ; 88 ; 2 ; 5 ; 5 ; 3 ; 4 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; comb~1 ; - ; +; RD[1] ; 87 ; 2 ; 5 ; 5 ; 2 ; 4 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; comb~1 ; - ; +; RD[2] ; 88 ; 2 ; 5 ; 5 ; 3 ; 4 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; comb~1 ; - ; ; RD[3] ; 89 ; 2 ; 4 ; 5 ; 0 ; 4 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; comb~1 ; - ; ; RD[4] ; 90 ; 2 ; 4 ; 5 ; 1 ; 4 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; comb~1 ; - ; ; RD[5] ; 91 ; 2 ; 4 ; 5 ; 2 ; 4 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; comb~1 ; - ; @@ -283,7 +281,7 @@ The pin-out file can be found in C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/outpu ; SD[3] ; 55 ; 2 ; 8 ; 1 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; ; SD[4] ; 51 ; 1 ; 7 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; ; SD[5] ; 52 ; 2 ; 8 ; 1 ; 4 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; -; SD[6] ; 53 ; 2 ; 8 ; 1 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; SDOE ; - ; +; SD[6] ; 53 ; 2 ; 8 ; 1 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; ; SD[7] ; 54 ; 2 ; 8 ; 1 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; +-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ @@ -428,7 +426,7 @@ Note: User assignments will override these defaults. The user specified values a +----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+ ; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ; +----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+ -; |GR8RAM ; 229 (229) ; 103 ; 0 ; 80 ; 0 ; 126 (126) ; 1 (1) ; 102 (102) ; 37 (37) ; 12 (12) ; |GR8RAM ; work ; +; |GR8RAM ; 220 (220) ; 103 ; 0 ; 80 ; 0 ; 117 (117) ; 1 (1) ; 102 (102) ; 37 (37) ; 5 (5) ; |GR8RAM ; work ; +----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. @@ -438,6 +436,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +----------+----------+---------------+ ; Name ; Pin Type ; Pad to Core 0 ; +----------+----------+---------------+ +; SetFW[0] ; Input ; (0) ; +; SetFW[1] ; Input ; (0) ; ; INTin ; Input ; (1) ; ; DMAin ; Input ; (1) ; ; nIOSTRB ; Input ; (1) ; @@ -457,8 +457,6 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; RA[8] ; Input ; (1) ; ; RA[9] ; Input ; (1) ; ; RA[10] ; Input ; (1) ; -; SetFW[0] ; Input ; (1) ; -; SetFW[1] ; Input ; (1) ; ; RA[11] ; Input ; (1) ; ; RA[14] ; Input ; (1) ; ; RA[15] ; Input ; (1) ; @@ -521,27 +519,26 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +----------+----------+---------------+ -+-----------------------------------------------------------------------------------------------------------------+ -; Control Signals ; -+------------+-------------+---------+-------------------------+--------+----------------------+------------------+ -; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; -+------------+-------------+---------+-------------------------+--------+----------------------+------------------+ -; C25M ; PIN_64 ; 100 ; Clock ; yes ; Global Clock ; GCLK3 ; -; Decoder1~0 ; LC_X6_Y3_N5 ; 8 ; Clock enable ; no ; -- ; -- ; -; Equal0~0 ; LC_X3_Y4_N6 ; 18 ; Clock enable ; no ; -- ; -- ; -; FCKOE ; LC_X2_Y1_N9 ; 2 ; Output enable ; no ; -- ; -- ; -; MOSIOE ; LC_X3_Y1_N7 ; 1 ; Output enable ; no ; -- ; -- ; -; PHI0 ; PIN_41 ; 5 ; Clock ; yes ; Global Clock ; GCLK1 ; -; PS[0] ; LC_X4_Y1_N2 ; 50 ; Clock enable ; no ; -- ; -- ; -; PS[2] ; LC_X4_Y1_N0 ; 29 ; Sync. clear, Sync. load ; no ; -- ; -- ; -; SDOE ; LC_X6_Y1_N7 ; 8 ; Output enable ; no ; -- ; -- ; -; WRD[0]~0 ; LC_X3_Y1_N6 ; 6 ; Clock enable ; no ; -- ; -- ; -; always6~4 ; LC_X3_Y4_N7 ; 8 ; Sync. load ; no ; -- ; -- ; -; always6~5 ; LC_X5_Y1_N8 ; 9 ; Sync. load ; no ; -- ; -- ; -; always6~6 ; LC_X5_Y2_N9 ; 9 ; Sync. load ; no ; -- ; -- ; -; comb~1 ; LC_X4_Y1_N4 ; 9 ; Output enable ; no ; -- ; -- ; -; nRESr ; LC_X2_Y3_N0 ; 30 ; Async. clear ; yes ; Global Clock ; GCLK2 ; -+------------+-------------+---------+-------------------------+--------+----------------------+------------------+ ++-------------------------------------------------------------------------------------------------------------------------------+ +; Control Signals ; ++------------+-------------+---------+---------------------------------------+--------+----------------------+------------------+ +; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; ++------------+-------------+---------+---------------------------------------+--------+----------------------+------------------+ +; C25M ; PIN_64 ; 100 ; Clock ; yes ; Global Clock ; GCLK3 ; +; Decoder1~0 ; LC_X5_Y4_N7 ; 8 ; Clock enable ; no ; -- ; -- ; +; Equal0~0 ; LC_X7_Y2_N8 ; 19 ; Clock enable ; no ; -- ; -- ; +; FCKOE ; LC_X2_Y3_N6 ; 2 ; Output enable ; no ; -- ; -- ; +; MOSIOE ; LC_X7_Y2_N6 ; 1 ; Output enable ; no ; -- ; -- ; +; PHI0 ; PIN_41 ; 5 ; Clock ; yes ; Global Clock ; GCLK1 ; +; PS[0] ; LC_X3_Y3_N9 ; 54 ; Clock enable, Sync. clear, Sync. load ; no ; -- ; -- ; +; PS[2] ; LC_X3_Y3_N5 ; 26 ; Sync. clear, Sync. load ; no ; -- ; -- ; +; SDOE ; LC_X6_Y2_N2 ; 8 ; Output enable ; no ; -- ; -- ; +; always6~4 ; LC_X3_Y1_N9 ; 8 ; Sync. load ; no ; -- ; -- ; +; always6~5 ; LC_X3_Y1_N3 ; 9 ; Sync. load ; no ; -- ; -- ; +; always6~6 ; LC_X3_Y1_N7 ; 9 ; Sync. load ; no ; -- ; -- ; +; comb~1 ; LC_X2_Y3_N7 ; 9 ; Output enable ; no ; -- ; -- ; +; nRESr ; LC_X2_Y3_N3 ; 30 ; Async. clear ; yes ; Global Clock ; GCLK2 ; ++------------+-------------+---------+---------------------------------------+--------+----------------------+------------------+ +-------------------------------------------------------------------------+ @@ -551,7 +548,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +-------+-------------+---------+----------------------+------------------+ ; C25M ; PIN_64 ; 100 ; Global Clock ; GCLK3 ; ; PHI0 ; PIN_41 ; 5 ; Global Clock ; GCLK1 ; -; nRESr ; LC_X2_Y3_N0 ; 30 ; Global Clock ; GCLK2 ; +; nRESr ; LC_X2_Y3_N3 ; 30 ; Global Clock ; GCLK2 ; +-------+-------------+---------+----------------------+------------------+ @@ -560,44 +557,40 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +---------------------+-----------+ ; Name ; Fan-Out ; +---------------------+-----------+ -; PS[0] ; 50 ; -; PS[1] ; 34 ; -; PS[2] ; 29 ; -; PS[3] ; 28 ; -; IS.110~0 ; 21 ; -; Equal0~0 ; 18 ; -; RAMSpecSELr ; 18 ; -; IS.state_bit_0 ; 16 ; -; IS.state_bit_1 ; 13 ; -; IS.state_bit_2 ; 12 ; -; LS[0] ; 11 ; -; RA[1] ; 10 ; -; RA[0] ; 10 ; +; PS[0] ; 55 ; +; PS[1] ; 32 ; +; PS[2] ; 26 ; +; PS[3] ; 26 ; +; IS.state_bit_0 ; 20 ; +; Equal0~0 ; 19 ; +; IS.110~0 ; 17 ; +; IS.state_bit_1 ; 17 ; +; LS[0] ; 13 ; +; RDD[1]~0 ; 12 ; +; AddrMSpecSEL ; 12 ; +; RAMSpecSELr ; 10 ; ; always6~6 ; 9 ; ; always6~5 ; 9 ; +; Mux15~0 ; 9 ; ; comb~1 ; 9 ; -; RDD[2]~21 ; 8 ; +; RA[0] ; 8 ; ; Decoder1~0 ; 8 ; -; RDD[2]~2 ; 8 ; ; SDOE ; 8 ; ; always6~4 ; 8 ; -; LS[1] ; 8 ; -; LS[2] ; 7 ; -; Equal15~0 ; 7 ; +; IS.state_bit_2 ; 8 ; +; LS[2] ; 8 ; +; RA[1] ; 7 ; +; SA[8]~15 ; 7 ; +; SA[8]~10 ; 7 ; +; Equal16~0 ; 7 ; ; RD[7]~7 ; 6 ; -; SetFW[1] ; 6 ; -; SetFW[0] ; 6 ; ; SA[8]~16 ; 6 ; -; WRD[0]~0 ; 6 ; -; SA[8]~12 ; 6 ; -; SA[8]~11 ; 6 ; -; Addr[23] ; 6 ; +; LS[1] ; 6 ; +; Mux14~6 ; 6 ; ; RD[0]~0 ; 5 ; -; always6~3 ; 5 ; -; LS[13] ; 5 ; ; Addr[0] ; 5 ; +; Equal17~0 ; 5 ; ; LS[6]~17 ; 5 ; -; IS.110~1 ; 5 ; ; LS[1]~3 ; 5 ; ; RD[6]~6 ; 4 ; ; RD[5]~5 ; 4 ; @@ -606,12 +599,11 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; RD[2]~2 ; 4 ; ; RD[1]~1 ; 4 ; ; nDEVSEL ; 4 ; -; RDD[7]~12 ; 4 ; -; RDD[7]~11 ; 4 ; -; nRCS~4 ; 4 ; -; Addr[22] ; 4 ; -; Addr[21] ; 4 ; -; Addr[20] ; 4 ; +; Equal8~0 ; 4 ; +; ROMSpecRD~0 ; 4 ; +; LS[13] ; 4 ; +; Equal1~2 ; 4 ; +; nRCS~0 ; 4 ; ; Addr[9] ; 4 ; ; Addr[8] ; 4 ; ; Addr[7] ; 4 ; @@ -624,35 +616,38 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; LS[4] ; 4 ; ; Addr[13] ; 4 ; ; Addr[3] ; 4 ; -; LS[12] ; 4 ; ; Addr[12] ; 4 ; ; Addr[2] ; 4 ; ; Addr[11] ; 4 ; -; SA[2]~10 ; 4 ; ; Addr[1] ; 4 ; ; Addr[10] ; 4 ; -; Mux14~6 ; 4 ; -; Equal18~0 ; 4 ; +; Addr[23] ; 4 ; ; RA[10] ; 3 ; ; RA[9] ; 3 ; ; RA[8] ; 3 ; ; RA[7] ; 3 ; ; RA[3] ; 3 ; ; RA[2] ; 3 ; +; nWE ; 3 ; ; nIOSEL ; 3 ; ; always6~8 ; 3 ; -; nRCS~8 ; 3 ; +; SA[2]~14 ; 3 ; +; WRD[5] ; 3 ; +; WRD[4] ; 3 ; +; WRD[3] ; 3 ; +; WRD[2] ; 3 ; +; WRD[1] ; 3 ; +; WRD[0] ; 3 ; +; always6~2 ; 3 ; ; REGEN ; 3 ; -; ROMSpecSEL~0 ; 3 ; -; Equal8~0 ; 3 ; -; Equal3~2 ; 3 ; -; Equal3~1 ; 3 ; +; Equal2~0 ; 3 ; +; Equal3~0 ; 3 ; ; Equal1~3 ; 3 ; -; Equal15~1 ; 3 ; ; nWEr ; 3 ; +; Addr[22] ; 3 ; +; Addr[21] ; 3 ; ; Addr[20]~41 ; 3 ; -; SA~14 ; 3 ; -; Equal20~0 ; 3 ; +; Addr[20] ; 3 ; ; Addr[19] ; 3 ; ; LS[9] ; 3 ; ; Addr[18] ; 3 ; @@ -663,9 +658,10 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; LS[6] ; 3 ; ; Addr[4]~17 ; 3 ; ; LS[3] ; 3 ; +; LS[12] ; 3 ; ; Addr[12]~11 ; 3 ; ; LS[11] ; 3 ; -; SA[2]~8 ; 3 ; +; SA[2]~9 ; 3 ; ; SA[2]~7 ; 3 ; ; LS[10] ; 3 ; ; SA[2]~6 ; 3 ; @@ -673,36 +669,30 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; RA[6] ; 2 ; ; RA[5] ; 2 ; ; RA[4] ; 2 ; -; nWE ; 2 ; ; nIOSTRB ; 2 ; -; Mux2~9 ; 2 ; -; Mux2~6 ; 2 ; -; Mux2~4 ; 2 ; -; Mux2~3 ; 2 ; +; WRD[7] ; 2 ; +; WRD[6] ; 2 ; ; AddrIncL ; 2 ; ; AddrIncM ; 2 ; -; always6~2 ; 2 ; -; Equal4~1 ; 2 ; -; Equal2~0 ; 2 ; -; IS.state_bit_2~0 ; 2 ; -; Equal4~0 ; 2 ; -; Equal1~1 ; 2 ; -; Equal1~0 ; 2 ; +; always6~3 ; 2 ; +; IS.state_bit_1~3 ; 2 ; +; IS.state_bit_1~0 ; 2 ; +; Equal3~1 ; 2 ; ; FCKOE ; 2 ; -; PS~0 ; 2 ; +; PHI0r1 ; 2 ; +; Selector1~1 ; 2 ; ; DQMH~0 ; 2 ; -; Mux12~2 ; 2 ; -; nRCS~6 ; 2 ; -; always7~1 ; 2 ; -; nRCS~3 ; 2 ; +; IS.001~0 ; 2 ; ; nRCS~2 ; 2 ; -; ROMSpecSELr ; 2 ; +; nRCS~1 ; 2 ; +; always7~1 ; 2 ; ; Bank ; 2 ; ; LS[11]~5 ; 2 ; -; SA[2]~9 ; 2 ; -; Mux14~3 ; 2 ; +; SA[2]~8 ; 2 ; +; Mux14~4 ; 2 ; ; always5~2 ; 2 ; ; always7~0 ; 2 ; +; PHI0r2 ; 2 ; ; IOROMEN ; 2 ; ; nRESout~reg0 ; 2 ; ; MOSI~0 ; 1 ; @@ -722,19 +712,18 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; RA[14] ; 1 ; ; DMAin ; 1 ; ; INTin ; 1 ; -; Mux11~7 ; 1 ; ; Mux14~7 ; 1 ; -; Mux2~7 ; 1 ; -; Mux2~5 ; 1 ; -; Mux2~2 ; 1 ; -; RDD~19 ; 1 ; -; RDD~17 ; 1 ; +; Mux2~1 ; 1 ; +; Mux2~0 ; 1 ; +; Decoder0~1 ; 1 ; ; RDD~15 ; 1 ; ; RDD~13 ; 1 ; +; RDD~11 ; 1 ; ; RDD~9 ; 1 ; ; RDD~7 ; 1 ; ; RDD~5 ; 1 ; ; RDD~3 ; 1 ; +; RDD~1 ; 1 ; ; AddrIncM~2 ; 1 ; ; AddrIncM~1 ; 1 ; ; AddrIncM~0 ; 1 ; @@ -742,8 +731,6 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; AddrIncH~1 ; 1 ; ; AddrIncH~0 ; 1 ; ; MOSIout ; 1 ; -; WRD[7] ; 1 ; -; WRD[6] ; 1 ; ; RDD[7] ; 1 ; ; RDD[6] ; 1 ; ; RDD[5] ; 1 ; @@ -754,40 +741,41 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; RDD[0] ; 1 ; ; MOSIOE ; 1 ; ; IS.101~0 ; 1 ; +; IS.state_bit_2~1 ; 1 ; +; IS.state_bit_2~0 ; 1 ; +; Equal1~4 ; 1 ; ; AddrIncH ; 1 ; ; always7~2 ; 1 ; -; RAMSpecSEL~1 ; 1 ; -; RAMSpecSEL~0 ; 1 ; -; IS.state_bit_2~2 ; 1 ; -; IS.state_bit_2~1 ; 1 ; +; IS.state_bit_1~2 ; 1 ; ; IS.state_bit_1~1 ; 1 ; -; IS.state_bit_1~0 ; 1 ; -; IS.state_bit_0~1 ; 1 ; -; IS.state_bit_0~0 ; 1 ; -; Equal3~0 ; 1 ; -; Equal1~2 ; 1 ; +; IS.state_bit_0~5 ; 1 ; +; IS.state_bit_0~4 ; 1 ; +; Equal4~0 ; 1 ; +; Equal1~1 ; 1 ; +; Equal1~0 ; 1 ; +; IS.111~0 ; 1 ; ; FCKout ; 1 ; ; FCS ; 1 ; -; Mux11~5 ; 1 ; ; Mux11~4 ; 1 ; -; PHI0r1 ; 1 ; ; Mux11~3 ; 1 ; ; Mux11~2 ; 1 ; +; Mux11~1 ; 1 ; +; Mux11~0 ; 1 ; +; Selector2~0 ; 1 ; ; Selector1~0 ; 1 ; -; Selector0~0 ; 1 ; ; Addr[0]~47COUT1_92 ; 1 ; ; Addr[0]~47 ; 1 ; -; Mux12~3 ; 1 ; -; nRCS~5 ; 1 ; +; Selector0~0 ; 1 ; +; Mux12~2 ; 1 ; ; Mux12~1 ; 1 ; +; ROMSpecRDr ; 1 ; ; Mux12~0 ; 1 ; +; Decoder0~0 ; 1 ; ; Addr[22]~45COUT1_78 ; 1 ; ; Addr[22]~45 ; 1 ; ; Addr[21]~43COUT1_76 ; 1 ; ; Addr[21]~43 ; 1 ; ; Mux15~1 ; 1 ; -; Mux15~0 ; 1 ; -; SA[2]~13 ; 1 ; ; Addr[19]~39COUT1_74 ; 1 ; ; Addr[19]~39 ; 1 ; ; Mux16~2 ; 1 ; @@ -862,22 +850,14 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; Mux24~3 ; 1 ; ; Mux24~2 ; 1 ; ; Mux24~1 ; 1 ; -; WRD[5] ; 1 ; ; Mux24~0 ; 1 ; ; LS[10]~1COUT1_52 ; 1 ; ; LS[10]~1 ; 1 ; -; WRD[4] ; 1 ; ; Addr[10]~3COUT1_84 ; 1 ; ; Addr[10]~3 ; 1 ; ; Mux13~0 ; 1 ; -; WRD[3] ; 1 ; -; WRD[2] ; 1 ; -; Mux14~5 ; 1 ; -; Mux14~4 ; 1 ; -; WRD[1] ; 1 ; -; WRD[0] ; 1 ; ; nRESr0 ; 1 ; -; Mux14~2 ; 1 ; +; Mux14~5 ; 1 ; ; always5~1 ; 1 ; ; always5~0 ; 1 ; ; RCKE~reg0 ; 1 ; @@ -902,7 +882,6 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; SA[0]~reg0 ; 1 ; ; SBA[1]~reg0 ; 1 ; ; SBA[0]~reg0 ; 1 ; -; PHI0r2 ; 1 ; ; comb~0 ; 1 ; +---------------------+-----------+ @@ -912,94 +891,94 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +-----------------------------+--------------------+ ; Other Routing Resource Type ; Usage ; +-----------------------------+--------------------+ -; C4s ; 281 / 784 ( 36 % ) ; -; Direct links ; 63 / 888 ( 7 % ) ; +; C4s ; 234 / 784 ( 30 % ) ; +; Direct links ; 57 / 888 ( 6 % ) ; ; Global clocks ; 3 / 4 ( 75 % ) ; -; LAB clocks ; 11 / 32 ( 34 % ) ; -; LUT chains ; 34 / 216 ( 16 % ) ; -; Local interconnects ; 483 / 888 ( 54 % ) ; -; R4s ; 341 / 704 ( 48 % ) ; +; LAB clocks ; 13 / 32 ( 41 % ) ; +; LUT chains ; 33 / 216 ( 15 % ) ; +; Local interconnects ; 433 / 888 ( 49 % ) ; +; R4s ; 294 / 704 ( 42 % ) ; +-----------------------------+--------------------+ +---------------------------------------------------------------------------+ ; LAB Logic Elements ; +--------------------------------------------+------------------------------+ -; Number of Logic Elements (Average = 9.54) ; Number of LABs (Total = 24) ; +; Number of Logic Elements (Average = 9.17) ; Number of LABs (Total = 24) ; +--------------------------------------------+------------------------------+ ; 1 ; 0 ; -; 2 ; 0 ; +; 2 ; 1 ; ; 3 ; 0 ; ; 4 ; 0 ; -; 5 ; 0 ; -; 6 ; 2 ; -; 7 ; 0 ; -; 8 ; 1 ; -; 9 ; 1 ; -; 10 ; 20 ; +; 5 ; 1 ; +; 6 ; 0 ; +; 7 ; 1 ; +; 8 ; 0 ; +; 9 ; 4 ; +; 10 ; 17 ; +--------------------------------------------+------------------------------+ +-------------------------------------------------------------------+ ; LAB-wide Signals ; +------------------------------------+------------------------------+ -; LAB-wide Signals (Average = 1.75) ; Number of LABs (Total = 24) ; +; LAB-wide Signals (Average = 2.00) ; Number of LABs (Total = 24) ; +------------------------------------+------------------------------+ -; 1 Async. clear ; 6 ; +; 1 Async. clear ; 7 ; ; 1 Clock ; 22 ; -; 1 Clock enable ; 3 ; -; 1 Sync. clear ; 6 ; -; 1 Sync. load ; 2 ; -; 2 Clock enables ; 1 ; +; 1 Clock enable ; 4 ; +; 1 Sync. clear ; 7 ; +; 1 Sync. load ; 6 ; ; 2 Clocks ; 2 ; +------------------------------------+------------------------------+ -+-----------------------------------------------------------------------------+ -; LAB Signals Sourced ; -+----------------------------------------------+------------------------------+ -; Number of Signals Sourced (Average = 10.08) ; Number of LABs (Total = 24) ; -+----------------------------------------------+------------------------------+ -; 0 ; 0 ; -; 1 ; 0 ; -; 2 ; 0 ; -; 3 ; 0 ; -; 4 ; 0 ; -; 5 ; 0 ; -; 6 ; 2 ; -; 7 ; 0 ; -; 8 ; 0 ; -; 9 ; 1 ; -; 10 ; 14 ; -; 11 ; 3 ; -; 12 ; 4 ; -+----------------------------------------------+------------------------------+ ++----------------------------------------------------------------------------+ +; LAB Signals Sourced ; ++---------------------------------------------+------------------------------+ +; Number of Signals Sourced (Average = 9.42) ; Number of LABs (Total = 24) ; ++---------------------------------------------+------------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 1 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 1 ; +; 6 ; 0 ; +; 7 ; 1 ; +; 8 ; 0 ; +; 9 ; 4 ; +; 10 ; 14 ; +; 11 ; 2 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 1 ; ++---------------------------------------------+------------------------------+ +--------------------------------------------------------------------------------+ ; LAB Signals Sourced Out ; +-------------------------------------------------+------------------------------+ -; Number of Signals Sourced Out (Average = 6.83) ; Number of LABs (Total = 24) ; +; Number of Signals Sourced Out (Average = 6.54) ; Number of LABs (Total = 24) ; +-------------------------------------------------+------------------------------+ ; 0 ; 0 ; -; 1 ; 0 ; -; 2 ; 1 ; -; 3 ; 3 ; -; 4 ; 2 ; -; 5 ; 2 ; -; 6 ; 4 ; -; 7 ; 1 ; -; 8 ; 0 ; -; 9 ; 7 ; -; 10 ; 3 ; -; 11 ; 1 ; +; 1 ; 1 ; +; 2 ; 0 ; +; 3 ; 2 ; +; 4 ; 3 ; +; 5 ; 4 ; +; 6 ; 1 ; +; 7 ; 4 ; +; 8 ; 1 ; +; 9 ; 4 ; +; 10 ; 4 ; +-------------------------------------------------+------------------------------+ +-----------------------------------------------------------------------------+ ; LAB Distinct Inputs ; +----------------------------------------------+------------------------------+ -; Number of Distinct Inputs (Average = 17.04) ; Number of LABs (Total = 24) ; +; Number of Distinct Inputs (Average = 15.13) ; Number of LABs (Total = 24) ; +----------------------------------------------+------------------------------+ ; 0 ; 0 ; ; 1 ; 0 ; @@ -1008,25 +987,21 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; 4 ; 0 ; ; 5 ; 0 ; ; 6 ; 0 ; -; 7 ; 1 ; +; 7 ; 2 ; ; 8 ; 0 ; ; 9 ; 1 ; ; 10 ; 1 ; ; 11 ; 1 ; -; 12 ; 1 ; -; 13 ; 1 ; +; 12 ; 2 ; +; 13 ; 3 ; ; 14 ; 2 ; -; 15 ; 3 ; -; 16 ; 1 ; +; 15 ; 0 ; +; 16 ; 3 ; ; 17 ; 1 ; ; 18 ; 0 ; -; 19 ; 1 ; -; 20 ; 3 ; -; 21 ; 1 ; -; 22 ; 2 ; -; 23 ; 1 ; -; 24 ; 1 ; -; 25 ; 2 ; +; 19 ; 2 ; +; 20 ; 1 ; +; 21 ; 5 ; +----------------------------------------------+------------------------------+ @@ -1045,25 +1020,6 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +----------------------------------------------+--------------------------+ -+------------------------------------------------------------+ -; Estimated Delay Added for Hold Timing Summary ; -+-----------------+----------------------+-------------------+ -; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ; -+-----------------+----------------------+-------------------+ -Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off. -This will disable optimization of problematic paths and expose them for further analysis using either the TimeQuest Timing Analyzer or the Classic Timing Analyzer. - - -+------------------------------------------------------------+ -; Estimated Delay Added for Hold Timing Details ; -+-----------------+----------------------+-------------------+ -; Source Register ; Destination Register ; Delay Added in ns ; -+-----------------+----------------------+-------------------+ -; PHI0 ; PHI0r1 ; 0.507 ; -+-----------------+----------------------+-------------------+ -Note: This table only shows the top 1 path(s) that have the largest delay added for hold. - - +-----------------+ ; Fitter Messages ; +-----------------+ @@ -1107,18 +1063,18 @@ Info (170191): Fitter placement operations beginning Info (170137): Fitter placement was successful Info (170192): Fitter placement operations ending: elapsed time is 00:00:01 Info (170193): Fitter routing operations beginning -Info (170195): Router estimated average interconnect usage is 34% of the available device resources - Info (170196): Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5 +Info (170195): Router estimated average interconnect usage is 32% of the available device resources + Info (170196): Router estimated peak interconnect usage is 32% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5 Info (170194): Fitter routing operations ending: elapsed time is 00:00:01 -Info (11888): Total time spent on timing analysis during the Fitter is 0.27 seconds. +Info (11888): Total time spent on timing analysis during the Fitter is 0.22 seconds. Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00 Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'. Info (144001): Generated suppressed messages file C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.fit.smsg Info: Quartus II 64-Bit Fitter was successful. 0 errors, 4 warnings - Info: Peak virtual memory: 547 megabytes - Info: Processing ended: Sun Apr 18 03:45:24 2021 - Info: Elapsed time: 00:00:03 - Info: Total CPU time (on all processors): 00:00:03 + Info: Peak virtual memory: 545 megabytes + Info: Processing ended: Sun Apr 18 05:55:51 2021 + Info: Elapsed time: 00:00:02 + Info: Total CPU time (on all processors): 00:00:02 +----------------------------+ diff --git a/cpld/output_files/GR8RAM.fit.summary b/cpld/output_files/GR8RAM.fit.summary index 9f627aa..346b115 100755 --- a/cpld/output_files/GR8RAM.fit.summary +++ b/cpld/output_files/GR8RAM.fit.summary @@ -1,11 +1,11 @@ -Fitter Status : Successful - Sun Apr 18 03:45:24 2021 +Fitter Status : Successful - Sun Apr 18 05:55:51 2021 Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition Revision Name : GR8RAM Top-level Entity Name : GR8RAM Family : MAX II Device : EPM240T100C5 Timing Models : Final -Total logic elements : 229 / 240 ( 95 % ) +Total logic elements : 220 / 240 ( 92 % ) Total pins : 80 / 80 ( 100 % ) Total virtual pins : 0 UFM blocks : 0 / 1 ( 0 % ) diff --git a/cpld/output_files/GR8RAM.flow.rpt b/cpld/output_files/GR8RAM.flow.rpt index 6492a6e..dab8a8c 100755 --- a/cpld/output_files/GR8RAM.flow.rpt +++ b/cpld/output_files/GR8RAM.flow.rpt @@ -1,5 +1,5 @@ Flow report for GR8RAM -Sun Apr 18 03:45:27 2021 +Sun Apr 18 05:55:54 2021 Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition @@ -40,14 +40,14 @@ applicable agreement for further details. +-----------------------------------------------------------------------------+ ; Flow Summary ; +---------------------------+-------------------------------------------------+ -; Flow Status ; Successful - Sun Apr 18 03:45:25 2021 ; +; Flow Status ; Successful - Sun Apr 18 05:55:52 2021 ; ; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; ; Revision Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ; ; Family ; MAX II ; ; Device ; EPM240T100C5 ; ; Timing Models ; Final ; -; Total logic elements ; 229 / 240 ( 95 % ) ; +; Total logic elements ; 220 / 240 ( 92 % ) ; ; Total pins ; 80 / 80 ( 100 % ) ; ; Total virtual pins ; 0 ; ; UFM blocks ; 0 / 1 ( 0 % ) ; @@ -59,7 +59,7 @@ applicable agreement for further details. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 04/18/2021 03:45:19 ; +; Start date & time ; 04/18/2021 05:55:48 ; ; Main task ; Compilation ; ; Revision Name ; GR8RAM ; +-------------------+---------------------+ @@ -75,7 +75,7 @@ applicable agreement for further details. ; ALM_REGISTER_PACKING_EFFORT ; High ; Medium ; -- ; -- ; ; AUTO_PACKED_REGISTERS_MAXII ; Minimize Area ; Auto ; -- ; -- ; ; AUTO_RESOURCE_SHARING ; On ; Off ; -- ; -- ; -; COMPILER_SIGNATURE_ID ; 136298148942.161873191903592 ; -- ; -- ; -- ; +; COMPILER_SIGNATURE_ID ; 136298148942.161873974705152 ; -- ; -- ; -- ; ; FINAL_PLACEMENT_OPTIMIZATION ; Always ; Automatically ; -- ; -- ; ; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ; ; IOBANK_VCCIO ; 3.3V ; -- ; -- ; 1 ; @@ -103,10 +103,10 @@ applicable agreement for further details. ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Analysis & Synthesis ; 00:00:01 ; 1.0 ; 421 MB ; 00:00:01 ; -; Fitter ; 00:00:03 ; 1.0 ; 547 MB ; 00:00:03 ; -; Assembler ; 00:00:01 ; 1.0 ; 381 MB ; 00:00:00 ; +; Fitter ; 00:00:02 ; 1.0 ; 545 MB ; 00:00:02 ; +; Assembler ; 00:00:00 ; 1.0 ; 381 MB ; 00:00:00 ; ; TimeQuest Timing Analyzer ; 00:00:01 ; 1.0 ; 368 MB ; 00:00:01 ; -; Total ; 00:00:06 ; -- ; -- ; 00:00:05 ; +; Total ; 00:00:04 ; -- ; -- ; 00:00:04 ; +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ diff --git a/cpld/output_files/GR8RAM.jdi b/cpld/output_files/GR8RAM.jdi index 3f1d964..2459804 100755 --- a/cpld/output_files/GR8RAM.jdi +++ b/cpld/output_files/GR8RAM.jdi @@ -1,6 +1,6 @@ - + diff --git a/cpld/output_files/GR8RAM.map.rpt b/cpld/output_files/GR8RAM.map.rpt index 8db2d70..2ab9922 100755 --- a/cpld/output_files/GR8RAM.map.rpt +++ b/cpld/output_files/GR8RAM.map.rpt @@ -1,5 +1,5 @@ Analysis & Synthesis report for GR8RAM -Sun Apr 18 03:45:20 2021 +Sun Apr 18 05:55:48 2021 Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition @@ -45,12 +45,12 @@ applicable agreement for further details. +-------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +-----------------------------+-------------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Sun Apr 18 03:45:20 2021 ; +; Analysis & Synthesis Status ; Successful - Sun Apr 18 05:55:48 2021 ; ; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; ; Revision Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ; ; Family ; MAX II ; -; Total logic elements ; 242 ; +; Total logic elements ; 226 ; ; Total pins ; 80 ; ; Total virtual pins ; 0 ; ; UFM blocks ; 0 / 1 ( 0 % ) ; @@ -155,24 +155,24 @@ Parallel compilation was disabled, but you have multiple processors available. E +---------------------------------------------+-------+ ; Resource ; Usage ; +---------------------------------------------+-------+ -; Total logic elements ; 242 ; -; -- Combinational with no register ; 139 ; -; -- Register only ; 14 ; -; -- Combinational with a register ; 89 ; +; Total logic elements ; 226 ; +; -- Combinational with no register ; 123 ; +; -- Register only ; 7 ; +; -- Combinational with a register ; 96 ; ; ; ; ; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 135 ; -; -- 3 input functions ; 30 ; -; -- 2 input functions ; 63 ; +; -- 4 input functions ; 114 ; +; -- 3 input functions ; 46 ; +; -- 2 input functions ; 59 ; ; -- 1 input functions ; 0 ; ; -- 0 input functions ; 0 ; ; ; ; ; Logic elements by mode ; ; -; -- normal mode ; 209 ; +; -- normal mode ; 193 ; ; -- arithmetic mode ; 33 ; ; -- qfbk mode ; 0 ; ; -- register cascade mode ; 0 ; -; -- synchronous clear/load mode ; 35 ; +; -- synchronous clear/load mode ; 44 ; ; -- asynchronous clear/load mode ; 30 ; ; ; ; ; Total registers ; 103 ; @@ -180,8 +180,8 @@ Parallel compilation was disabled, but you have multiple processors available. E ; I/O pins ; 80 ; ; Maximum fan-out node ; C25M ; ; Maximum fan-out ; 100 ; -; Total fan-out ; 1055 ; -; Average fan-out ; 3.28 ; +; Total fan-out ; 1013 ; +; Average fan-out ; 3.31 ; +---------------------------------------------+-------+ @@ -190,7 +190,7 @@ Parallel compilation was disabled, but you have multiple processors available. E +----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+ ; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ; +----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+ -; |GR8RAM ; 242 (242) ; 103 ; 0 ; 80 ; 0 ; 139 (139) ; 14 (14) ; 89 (89) ; 37 (37) ; 0 (0) ; |GR8RAM ; work ; +; |GR8RAM ; 226 (226) ; 103 ; 0 ; 80 ; 0 ; 123 (123) ; 7 (7) ; 96 (96) ; 37 (37) ; 0 (0) ; |GR8RAM ; work ; +----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. @@ -203,8 +203,6 @@ Encoding Type: Minimal Bits +--------+----------------+----------------+----------------+ ; IS.000 ; 0 ; 0 ; 0 ; ; IS.001 ; 0 ; 0 ; 1 ; -; IS.010 ; 1 ; 1 ; 0 ; -; IS.011 ; 1 ; 1 ; 1 ; ; IS.100 ; 1 ; 0 ; 0 ; ; IS.101 ; 1 ; 0 ; 1 ; ; IS.110 ; 0 ; 1 ; 0 ; @@ -217,7 +215,7 @@ Encoding Type: Minimal Bits +---------------------------------------+--------------------+ ; Register name ; Reason for Removal ; +---------------------------------------+--------------------+ -; IS~12 ; Lost fanout ; +; IS~10 ; Lost fanout ; ; Total Number of Removed Registers = 1 ; ; +---------------------------------------+--------------------+ @@ -228,11 +226,11 @@ Encoding Type: Minimal Bits ; Statistic ; Value ; +----------------------------------------------+-------+ ; Total registers ; 103 ; -; Number of registers using Synchronous Clear ; 10 ; -; Number of registers using Synchronous Load ; 25 ; +; Number of registers using Synchronous Clear ; 11 ; +; Number of registers using Synchronous Load ; 33 ; ; Number of registers using Asynchronous Clear ; 30 ; ; Number of registers using Asynchronous Load ; 0 ; -; Number of registers using Clock Enable ; 29 ; +; Number of registers using Clock Enable ; 22 ; ; Number of registers using Preset ; 0 ; +----------------------------------------------+-------+ @@ -258,16 +256,14 @@ Encoding Type: Minimal Bits +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ ; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ -; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |GR8RAM|PS[2] ; -; 5:1 ; 2 bits ; 6 LEs ; 2 LEs ; 4 LEs ; Yes ; |GR8RAM|SA[11]~reg0 ; +; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |GR8RAM|PS[1] ; +; 4:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |GR8RAM|SA[11]~reg0 ; ; 20:1 ; 6 bits ; 78 LEs ; 24 LEs ; 54 LEs ; Yes ; |GR8RAM|SA[8]~reg0 ; ; 20:1 ; 3 bits ; 39 LEs ; 18 LEs ; 21 LEs ; Yes ; |GR8RAM|SA[2]~reg0 ; -; 3:1 ; 6 bits ; 12 LEs ; 6 LEs ; 6 LEs ; Yes ; |GR8RAM|WRD[0] ; -; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |GR8RAM|WRD[7] ; -; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |GR8RAM|RDD[2] ; -; 5:1 ; 4 bits ; 12 LEs ; 8 LEs ; 4 LEs ; Yes ; |GR8RAM|RDD[7] ; +; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |GR8RAM|WRD[7] ; +; 4:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |GR8RAM|RDD[1] ; ; 18:1 ; 2 bits ; 24 LEs ; 8 LEs ; 16 LEs ; Yes ; |GR8RAM|DQMH~reg0 ; -; 8:1 ; 7 bits ; 35 LEs ; 28 LEs ; 7 LEs ; No ; |GR8RAM|IS ; +; 8:1 ; 5 bits ; 25 LEs ; 20 LEs ; 5 LEs ; No ; |GR8RAM|IS ; +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ @@ -277,17 +273,20 @@ Encoding Type: Minimal Bits Info: ******************************************************************* Info: Running Quartus II 64-Bit Analysis & Synthesis Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - Info: Processing started: Sun Apr 18 03:45:19 2021 + Info: Processing started: Sun Apr 18 05:55:47 2021 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM Warning (20028): Parallel compilation is not licensed and has been disabled Info (12021): Found 1 design units, including 1 entities, in source file gr8ram.v Info (12023): Found entity 1: GR8RAM Info (12127): Elaborating entity "GR8RAM" for the top level hierarchy +Warning (10036): Verilog HDL or VHDL warning at GR8RAM.v(269): object "SetRF" assigned a value but never read +Warning (10036): Verilog HDL or VHDL warning at GR8RAM.v(270): object "SetLim1M" assigned a value but never read +Warning (10036): Verilog HDL or VHDL warning at GR8RAM.v(271): object "SetLim8M" assigned a value but never read Warning (10230): Verilog HDL assignment warning at GR8RAM.v(34): truncated value with size 32 to match size of target (14) Warning (10230): Verilog HDL assignment warning at GR8RAM.v(117): truncated value with size 32 to match size of target (8) Warning (10230): Verilog HDL assignment warning at GR8RAM.v(125): truncated value with size 32 to match size of target (8) Warning (10230): Verilog HDL assignment warning at GR8RAM.v(132): truncated value with size 32 to match size of target (8) -Warning (10230): Verilog HDL assignment warning at GR8RAM.v(324): truncated value with size 32 to match size of target (4) +Warning (10230): Verilog HDL assignment warning at GR8RAM.v(325): truncated value with size 32 to match size of target (4) Info (17026): Resynthesizing 0 WYSIWYG logic cells and I/Os using "area" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched Warning (13024): Output pins are stuck at VCC or GND Warning (13410): Pin "RAdir" is stuck at VCC @@ -298,15 +297,18 @@ Warning (13024): Output pins are stuck at VCC or GND Warning (13410): Pin "nINHout" is stuck at VCC Warning (13410): Pin "RWout" is stuck at VCC Info (17049): 1 registers lost all their fanouts during netlist optimizations. -Info (21057): Implemented 322 device resources after synthesis - the final resource count might be different +Warning (21074): Design contains 2 input pin(s) that do not drive logic + Warning (15610): No output dependent on input pin "SetFW[0]" + Warning (15610): No output dependent on input pin "SetFW[1]" +Info (21057): Implemented 306 device resources after synthesis - the final resource count might be different Info (21058): Implemented 28 input pins Info (21059): Implemented 35 output pins Info (21060): Implemented 17 bidirectional pins - Info (21061): Implemented 242 logic cells + Info (21061): Implemented 226 logic cells Info (144001): Generated suppressed messages file C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg -Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 14 warnings +Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 20 warnings Info: Peak virtual memory: 421 megabytes - Info: Processing ended: Sun Apr 18 03:45:20 2021 + Info: Processing ended: Sun Apr 18 05:55:48 2021 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 diff --git a/cpld/output_files/GR8RAM.map.smsg b/cpld/output_files/GR8RAM.map.smsg index 35952bc..26e8737 100755 --- a/cpld/output_files/GR8RAM.map.smsg +++ b/cpld/output_files/GR8RAM.map.smsg @@ -1,2 +1,2 @@ Warning (10273): Verilog HDL warning at GR8RAM.v(93): extended using "x" or "z" -Warning (10273): Verilog HDL warning at GR8RAM.v(273): extended using "x" or "z" +Warning (10273): Verilog HDL warning at GR8RAM.v(274): extended using "x" or "z" diff --git a/cpld/output_files/GR8RAM.map.summary b/cpld/output_files/GR8RAM.map.summary index 6acbb30..7f2b4cf 100755 --- a/cpld/output_files/GR8RAM.map.summary +++ b/cpld/output_files/GR8RAM.map.summary @@ -1,9 +1,9 @@ -Analysis & Synthesis Status : Successful - Sun Apr 18 03:45:20 2021 +Analysis & Synthesis Status : Successful - Sun Apr 18 05:55:48 2021 Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition Revision Name : GR8RAM Top-level Entity Name : GR8RAM Family : MAX II -Total logic elements : 242 +Total logic elements : 226 Total pins : 80 Total virtual pins : 0 UFM blocks : 0 / 1 ( 0 % ) diff --git a/cpld/output_files/GR8RAM.pof b/cpld/output_files/GR8RAM.pof index a0b09c8..6d0ab1d 100755 Binary files a/cpld/output_files/GR8RAM.pof and b/cpld/output_files/GR8RAM.pof differ diff --git a/cpld/output_files/GR8RAM.sta.rpt b/cpld/output_files/GR8RAM.sta.rpt index 3a8a4a8..db2f30f 100755 --- a/cpld/output_files/GR8RAM.sta.rpt +++ b/cpld/output_files/GR8RAM.sta.rpt @@ -1,5 +1,5 @@ TimeQuest Timing Analyzer report for GR8RAM -Sun Apr 18 03:45:27 2021 +Sun Apr 18 05:55:54 2021 Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition @@ -18,8 +18,8 @@ Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit 10. Minimum Pulse Width Summary 11. Setup: 'C25M' 12. Setup: 'PHI0' - 13. Hold: 'PHI0' - 14. Hold: 'C25M' + 13. Hold: 'C25M' + 14. Hold: 'PHI0' 15. Recovery: 'C25M' 16. Removal: 'C25M' 17. Minimum Pulse Width: 'C25M' @@ -98,13 +98,13 @@ Parallel compilation was disabled, but you have multiple processors available. E +------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------+ -+-------------------------------------------------+ -; Fmax Summary ; -+-----------+-----------------+------------+------+ -; Fmax ; Restricted Fmax ; Clock Name ; Note ; -+-----------+-----------------+------------+------+ -; 98.64 MHz ; 98.64 MHz ; C25M ; ; -+-----------+-----------------+------------+------+ ++--------------------------------------------------+ +; Fmax Summary ; ++------------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++------------+-----------------+------------+------+ +; 100.52 MHz ; 100.52 MHz ; C25M ; ; ++------------+-----------------+------------+------+ This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. @@ -113,8 +113,8 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +-------+--------+---------------+ -; C25M ; -9.691 ; -732.295 ; -; PHI0 ; -1.358 ; -1.358 ; +; C25M ; -9.431 ; -683.489 ; +; PHI0 ; -1.421 ; -1.421 ; +-------+--------+---------------+ @@ -123,8 +123,8 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +-------+-------+---------------+ -; PHI0 ; 1.092 ; 0.000 ; -; C25M ; 1.418 ; 0.000 ; +; C25M ; 1.384 ; 0.000 ; +; PHI0 ; 1.867 ; 0.000 ; +-------+-------+---------------+ @@ -133,7 +133,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +-------+--------+---------------+ -; C25M ; -5.009 ; -150.270 ; +; C25M ; -4.406 ; -132.180 ; +-------+--------+---------------+ @@ -142,7 +142,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +-------+-------+---------------+ -; C25M ; 5.455 ; 0.000 ; +; C25M ; 4.852 ; 0.000 ; +-------+-------+---------------+ @@ -161,106 +161,106 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +--------+----------------+----------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+----------------+----------------+--------------+-------------+--------------+------------+------------+ -; -9.691 ; nWEr ; nRCS~reg0 ; PHI0 ; C25M ; 1.000 ; -2.776 ; 7.582 ; -; -9.602 ; RAMSpecSELr ; RCKE~reg0 ; PHI0 ; C25M ; 1.000 ; -2.776 ; 7.493 ; -; -9.597 ; ROMSpecSELr ; nRCS~reg0 ; PHI0 ; C25M ; 1.000 ; -2.776 ; 7.488 ; -; -9.555 ; RAMSpecSELr ; SA[1]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.776 ; 7.446 ; -; -9.510 ; RAMSpecSELr ; SA[3]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.776 ; 7.401 ; -; -9.406 ; RAMSpecSELr ; nRCS~reg0 ; PHI0 ; C25M ; 1.000 ; -2.776 ; 7.297 ; -; -9.356 ; ROMSpecSELr ; RCKE~reg0 ; PHI0 ; C25M ; 1.000 ; -2.776 ; 7.247 ; -; -9.306 ; nWEr ; RCKE~reg0 ; PHI0 ; C25M ; 1.000 ; -2.776 ; 7.197 ; -; -9.286 ; RAMSpecSELr ; SA[4]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.776 ; 7.177 ; -; -9.276 ; RAMSpecSELr ; SA[8]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.776 ; 7.167 ; -; -9.273 ; RAMSpecSELr ; SA[6]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.776 ; 7.164 ; -; -9.138 ; IS.state_bit_2 ; SA[1]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.805 ; -; -9.127 ; RAMSpecSELr ; SA[5]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.776 ; 7.018 ; -; -9.058 ; RAMSpecSELr ; SA[0]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.776 ; 6.949 ; -; -9.055 ; RAMSpecSELr ; SA[2]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.776 ; 6.946 ; -; -9.001 ; IS.state_bit_2 ; RCKE~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.668 ; -; -8.979 ; REGEN ; RDD[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.646 ; -; -8.978 ; IS.state_bit_2 ; SA[2]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.645 ; -; -8.930 ; REGEN ; RDD[2] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.597 ; -; -8.929 ; IS.state_bit_1 ; SA[1]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.596 ; -; -8.891 ; IS.state_bit_2 ; SA[0]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.558 ; -; -8.865 ; RAMSpecSELr ; SA[7]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.776 ; 6.756 ; -; -8.835 ; LS[10] ; IS.state_bit_2 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.502 ; -; -8.807 ; nWEr ; Addr[0] ; PHI0 ; C25M ; 1.000 ; -2.776 ; 6.698 ; -; -8.807 ; nWEr ; Addr[1] ; PHI0 ; C25M ; 1.000 ; -2.776 ; 6.698 ; -; -8.807 ; nWEr ; Addr[2] ; PHI0 ; C25M ; 1.000 ; -2.776 ; 6.698 ; -; -8.807 ; nWEr ; Addr[3] ; PHI0 ; C25M ; 1.000 ; -2.776 ; 6.698 ; -; -8.807 ; nWEr ; Addr[4] ; PHI0 ; C25M ; 1.000 ; -2.776 ; 6.698 ; -; -8.807 ; nWEr ; Addr[5] ; PHI0 ; C25M ; 1.000 ; -2.776 ; 6.698 ; -; -8.807 ; nWEr ; Addr[6] ; PHI0 ; C25M ; 1.000 ; -2.776 ; 6.698 ; -; -8.807 ; nWEr ; Addr[7] ; PHI0 ; C25M ; 1.000 ; -2.776 ; 6.698 ; -; -8.794 ; nWEr ; Addr[10] ; PHI0 ; C25M ; 1.000 ; -2.776 ; 6.685 ; -; -8.794 ; nWEr ; Addr[11] ; PHI0 ; C25M ; 1.000 ; -2.776 ; 6.685 ; -; -8.794 ; nWEr ; Addr[12] ; PHI0 ; C25M ; 1.000 ; -2.776 ; 6.685 ; -; -8.794 ; nWEr ; Addr[13] ; PHI0 ; C25M ; 1.000 ; -2.776 ; 6.685 ; -; -8.794 ; nWEr ; Addr[14] ; PHI0 ; C25M ; 1.000 ; -2.776 ; 6.685 ; -; -8.794 ; nWEr ; Addr[15] ; PHI0 ; C25M ; 1.000 ; -2.776 ; 6.685 ; -; -8.794 ; nWEr ; Addr[8] ; PHI0 ; C25M ; 1.000 ; -2.776 ; 6.685 ; -; -8.794 ; nWEr ; Addr[9] ; PHI0 ; C25M ; 1.000 ; -2.776 ; 6.685 ; -; -8.792 ; IS.state_bit_1 ; RCKE~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.459 ; -; -8.786 ; nWEr ; SDOE ; PHI0 ; C25M ; 1.000 ; -2.776 ; 6.677 ; -; -8.769 ; IS.state_bit_1 ; SA[2]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.436 ; -; -8.682 ; PS[0] ; SA[3]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.349 ; -; -8.682 ; IS.state_bit_1 ; SA[0]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.349 ; -; -8.681 ; IS.state_bit_1 ; nRCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.348 ; -; -8.677 ; LS[8] ; IS.state_bit_2 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.344 ; -; -8.618 ; PS[3] ; SA[3]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.285 ; -; -8.593 ; REGEN ; RDD[1] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.260 ; -; -8.581 ; REGEN ; RDD[3] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.248 ; -; -8.535 ; IS.state_bit_2 ; nRCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.202 ; -; -8.497 ; nWEr ; Addr[23] ; PHI0 ; C25M ; 1.000 ; -2.776 ; 6.388 ; -; -8.497 ; nWEr ; Addr[16] ; PHI0 ; C25M ; 1.000 ; -2.776 ; 6.388 ; -; -8.497 ; nWEr ; Addr[17] ; PHI0 ; C25M ; 1.000 ; -2.776 ; 6.388 ; -; -8.497 ; nWEr ; Addr[18] ; PHI0 ; C25M ; 1.000 ; -2.776 ; 6.388 ; -; -8.497 ; nWEr ; Addr[19] ; PHI0 ; C25M ; 1.000 ; -2.776 ; 6.388 ; -; -8.497 ; nWEr ; Addr[20] ; PHI0 ; C25M ; 1.000 ; -2.776 ; 6.388 ; -; -8.497 ; nWEr ; Addr[21] ; PHI0 ; C25M ; 1.000 ; -2.776 ; 6.388 ; -; -8.497 ; nWEr ; Addr[22] ; PHI0 ; C25M ; 1.000 ; -2.776 ; 6.388 ; -; -8.487 ; LS[11] ; IS.state_bit_2 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.154 ; -; -8.458 ; PS[0] ; SA[4]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.125 ; -; -8.448 ; PS[0] ; SA[8]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.115 ; -; -8.445 ; PS[0] ; SA[6]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.112 ; -; -8.417 ; IS.state_bit_0 ; SA[1]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.084 ; -; -8.405 ; PS[1] ; SA[1]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.072 ; -; -8.394 ; PS[3] ; SA[4]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.061 ; -; -8.390 ; LS[7] ; IS.state_bit_2 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.057 ; -; -8.384 ; PS[3] ; SA[8]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.051 ; -; -8.381 ; PS[3] ; SA[6]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.048 ; -; -8.375 ; IS.state_bit_1 ; SA[3]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.042 ; -; -8.338 ; LS[10] ; IS.state_bit_0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.005 ; -; -8.321 ; LS[1] ; IS.state_bit_2 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.988 ; -; -8.316 ; IS.state_bit_2 ; SA[6]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.983 ; -; -8.299 ; PS[0] ; SA[5]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.966 ; -; -8.280 ; IS.state_bit_0 ; RCKE~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.947 ; -; -8.280 ; LS[13] ; IS.state_bit_2 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.947 ; -; -8.279 ; PS[1] ; RCKE~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.946 ; -; -8.259 ; PS[1] ; SA[2]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.926 ; -; -8.257 ; IS.state_bit_0 ; SA[2]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.924 ; -; -8.254 ; LS[2] ; IS.state_bit_2 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.921 ; -; -8.244 ; IS.state_bit_2 ; SA[3]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.911 ; -; -8.235 ; PS[3] ; SA[5]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.902 ; -; -8.230 ; PS[0] ; SA[0]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.897 ; -; -8.227 ; PS[0] ; SA[2]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.894 ; -; -8.204 ; LS[4] ; IS.state_bit_2 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.871 ; -; -8.197 ; PS[0] ; SA[1]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.864 ; -; -8.180 ; LS[8] ; IS.state_bit_0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.847 ; -; -8.172 ; PS[1] ; SA[0]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.839 ; -; -8.170 ; IS.state_bit_0 ; SA[0]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.837 ; -; -8.166 ; PS[3] ; SA[0]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.833 ; -; -8.163 ; PS[3] ; SA[2]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.830 ; -; -8.156 ; RAMSpecSELr ; SDOE ; PHI0 ; C25M ; 1.000 ; -2.776 ; 6.047 ; -; -8.151 ; IS.state_bit_1 ; SA[4]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.818 ; -; -8.146 ; IS.state_bit_2 ; SA[7]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.813 ; -; -8.146 ; LS[6] ; IS.state_bit_2 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.813 ; -; -8.145 ; IS.state_bit_2 ; SA[5]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.812 ; -; -8.145 ; RAMSpecSELr ; SBA[0]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.776 ; 6.036 ; -; -8.141 ; IS.state_bit_1 ; SA[8]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.808 ; -; -8.139 ; LS[12] ; IS.state_bit_2 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.806 ; -; -8.138 ; LS[9] ; IS.state_bit_2 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.805 ; -; -8.138 ; IS.state_bit_1 ; SA[6]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.805 ; +; -9.431 ; RAMSpecSELr ; SA[0]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.798 ; 7.300 ; +; -9.357 ; RAMSpecSELr ; SA[6]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.798 ; 7.226 ; +; -9.350 ; RAMSpecSELr ; SA[4]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.798 ; 7.219 ; +; -9.343 ; RAMSpecSELr ; SA[3]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.798 ; 7.212 ; +; -9.340 ; nWEr ; nRCS~reg0 ; PHI0 ; C25M ; 1.000 ; -2.798 ; 7.209 ; +; -9.294 ; RAMSpecSELr ; SA[1]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.798 ; 7.163 ; +; -9.226 ; nWEr ; RCKE~reg0 ; PHI0 ; C25M ; 1.000 ; -2.798 ; 7.095 ; +; -9.127 ; RAMSpecSELr ; nRCS~reg0 ; PHI0 ; C25M ; 1.000 ; -2.798 ; 6.996 ; +; -8.948 ; IS.state_bit_0 ; SA[0]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.615 ; +; -8.868 ; RAMSpecSELr ; SA[2]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.798 ; 6.737 ; +; -8.811 ; IS.state_bit_0 ; SA[1]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.478 ; +; -8.804 ; ROMSpecRDr ; nRCS~reg0 ; PHI0 ; C25M ; 1.000 ; -2.798 ; 6.673 ; +; -8.762 ; RAMSpecSELr ; SA[8]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.798 ; 6.631 ; +; -8.655 ; nWEr ; Addr[23] ; PHI0 ; C25M ; 1.000 ; -2.798 ; 6.524 ; +; -8.655 ; nWEr ; Addr[16] ; PHI0 ; C25M ; 1.000 ; -2.798 ; 6.524 ; +; -8.655 ; nWEr ; Addr[17] ; PHI0 ; C25M ; 1.000 ; -2.798 ; 6.524 ; +; -8.655 ; nWEr ; Addr[18] ; PHI0 ; C25M ; 1.000 ; -2.798 ; 6.524 ; +; -8.655 ; nWEr ; Addr[19] ; PHI0 ; C25M ; 1.000 ; -2.798 ; 6.524 ; +; -8.655 ; nWEr ; Addr[20] ; PHI0 ; C25M ; 1.000 ; -2.798 ; 6.524 ; +; -8.655 ; nWEr ; Addr[21] ; PHI0 ; C25M ; 1.000 ; -2.798 ; 6.524 ; +; -8.655 ; nWEr ; Addr[22] ; PHI0 ; C25M ; 1.000 ; -2.798 ; 6.524 ; +; -8.584 ; RAMSpecSELr ; RCKE~reg0 ; PHI0 ; C25M ; 1.000 ; -2.798 ; 6.453 ; +; -8.447 ; RAMSpecSELr ; SA[7]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.798 ; 6.316 ; +; -8.385 ; IS.state_bit_0 ; SA[2]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.052 ; +; -8.382 ; PS[3] ; IS.state_bit_2 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.049 ; +; -8.369 ; RAMSpecSELr ; SA[12]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.798 ; 6.238 ; +; -8.368 ; RAMSpecSELr ; SA[10]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.798 ; 6.237 ; +; -8.367 ; RAMSpecSELr ; SA[11]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.798 ; 6.236 ; +; -8.361 ; RAMSpecSELr ; SA[9]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.798 ; 6.230 ; +; -8.275 ; LS[9] ; IS.state_bit_0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.942 ; +; -8.261 ; ROMSpecRDr ; RCKE~reg0 ; PHI0 ; C25M ; 1.000 ; -2.798 ; 6.130 ; +; -8.248 ; PS[1] ; Addr[23] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.915 ; +; -8.248 ; PS[1] ; Addr[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.915 ; +; -8.248 ; PS[1] ; Addr[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.915 ; +; -8.248 ; PS[1] ; Addr[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.915 ; +; -8.248 ; PS[1] ; Addr[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.915 ; +; -8.248 ; PS[1] ; Addr[20] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.915 ; +; -8.248 ; PS[1] ; Addr[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.915 ; +; -8.248 ; PS[1] ; Addr[22] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.915 ; +; -8.206 ; IS.state_bit_1 ; SA[0]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.873 ; +; -8.203 ; LS[11] ; IS.state_bit_0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.870 ; +; -8.157 ; PS[1] ; RCKE~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.824 ; +; -8.127 ; nWEr ; Addr[0] ; PHI0 ; C25M ; 1.000 ; -2.798 ; 5.996 ; +; -8.127 ; nWEr ; Addr[1] ; PHI0 ; C25M ; 1.000 ; -2.798 ; 5.996 ; +; -8.127 ; nWEr ; Addr[2] ; PHI0 ; C25M ; 1.000 ; -2.798 ; 5.996 ; +; -8.127 ; nWEr ; Addr[3] ; PHI0 ; C25M ; 1.000 ; -2.798 ; 5.996 ; +; -8.127 ; nWEr ; Addr[4] ; PHI0 ; C25M ; 1.000 ; -2.798 ; 5.996 ; +; -8.127 ; nWEr ; Addr[5] ; PHI0 ; C25M ; 1.000 ; -2.798 ; 5.996 ; +; -8.127 ; nWEr ; Addr[6] ; PHI0 ; C25M ; 1.000 ; -2.798 ; 5.996 ; +; -8.127 ; nWEr ; Addr[7] ; PHI0 ; C25M ; 1.000 ; -2.798 ; 5.996 ; +; -8.069 ; IS.state_bit_1 ; SA[1]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.736 ; +; -8.062 ; PS[2] ; IS.state_bit_2 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.729 ; +; -8.049 ; IS.state_bit_0 ; SA[7]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.716 ; +; -8.039 ; PS[1] ; IS.state_bit_2 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.706 ; +; -8.039 ; LS[8] ; IS.state_bit_0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.706 ; +; -8.038 ; PS[0] ; Addr[23] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.705 ; +; -8.038 ; PS[0] ; Addr[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.705 ; +; -8.038 ; PS[0] ; Addr[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.705 ; +; -8.038 ; PS[0] ; Addr[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.705 ; +; -8.038 ; PS[0] ; Addr[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.705 ; +; -8.038 ; PS[0] ; Addr[20] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.705 ; +; -8.038 ; PS[0] ; Addr[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.705 ; +; -8.038 ; PS[0] ; Addr[22] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.705 ; +; -8.036 ; LS[9] ; IS.state_bit_2 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.703 ; +; -8.018 ; IS.state_bit_0 ; SA[8]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.685 ; +; -7.964 ; LS[11] ; IS.state_bit_2 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.631 ; +; -7.917 ; IS.state_bit_1 ; SA[6]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.584 ; +; -7.910 ; IS.state_bit_1 ; SA[4]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.577 ; +; -7.903 ; IS.state_bit_1 ; SA[3]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.570 ; +; -7.899 ; PS[0] ; RCKE~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.566 ; +; -7.876 ; PS[2] ; Addr[23] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.543 ; +; -7.876 ; PS[2] ; Addr[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.543 ; +; -7.876 ; PS[2] ; Addr[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.543 ; +; -7.876 ; PS[2] ; Addr[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.543 ; +; -7.876 ; PS[2] ; Addr[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.543 ; +; -7.876 ; PS[2] ; Addr[20] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.543 ; +; -7.876 ; PS[2] ; Addr[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.543 ; +; -7.876 ; PS[2] ; Addr[22] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.543 ; +; -7.864 ; PS[0] ; SA[1]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.531 ; +; -7.832 ; RAMSpecSELr ; SA[5]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.798 ; 5.701 ; +; -7.800 ; LS[8] ; IS.state_bit_2 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.467 ; +; -7.798 ; IS.state_bit_0 ; nRCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.465 ; +; -7.741 ; PS[0] ; SA[0]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.408 ; +; -7.720 ; PS[1] ; Addr[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.387 ; +; -7.720 ; PS[1] ; Addr[1] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.387 ; +; -7.720 ; PS[1] ; Addr[2] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.387 ; +; -7.720 ; PS[1] ; Addr[3] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.387 ; +; -7.720 ; PS[1] ; Addr[4] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.387 ; +; -7.720 ; PS[1] ; Addr[5] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.387 ; +; -7.720 ; PS[1] ; Addr[6] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.387 ; +; -7.720 ; PS[1] ; Addr[7] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.387 ; +; -7.686 ; IS.state_bit_2 ; IS.state_bit_2 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.353 ; +; -7.686 ; PS[0] ; IS.state_bit_2 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.353 ; +; -7.657 ; nWEr ; Addr[10] ; PHI0 ; C25M ; 1.000 ; -2.798 ; 5.526 ; +; -7.657 ; nWEr ; Addr[11] ; PHI0 ; C25M ; 1.000 ; -2.798 ; 5.526 ; +; -7.657 ; nWEr ; Addr[12] ; PHI0 ; C25M ; 1.000 ; -2.798 ; 5.526 ; +; -7.657 ; nWEr ; Addr[13] ; PHI0 ; C25M ; 1.000 ; -2.798 ; 5.526 ; +; -7.657 ; nWEr ; Addr[14] ; PHI0 ; C25M ; 1.000 ; -2.798 ; 5.526 ; +; -7.657 ; nWEr ; Addr[15] ; PHI0 ; C25M ; 1.000 ; -2.798 ; 5.526 ; +; -7.657 ; nWEr ; Addr[8] ; PHI0 ; C25M ; 1.000 ; -2.798 ; 5.526 ; +--------+----------------+----------------+--------------+-------------+--------------+------------+------------+ @@ -269,170 +269,162 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ -; -1.358 ; Addr[22] ; RAMSpecSELr ; C25M ; PHI0 ; 1.000 ; 2.776 ; 4.801 ; -; -1.201 ; Addr[23] ; RAMSpecSELr ; C25M ; PHI0 ; 1.000 ; 2.776 ; 4.644 ; -; -1.057 ; Addr[20] ; RAMSpecSELr ; C25M ; PHI0 ; 1.000 ; 2.776 ; 4.500 ; -; -1.022 ; Addr[21] ; RAMSpecSELr ; C25M ; PHI0 ; 1.000 ; 2.776 ; 4.465 ; -; -0.977 ; REGEN ; RAMSpecSELr ; C25M ; PHI0 ; 1.000 ; 2.776 ; 4.420 ; +; -1.421 ; REGEN ; RAMSpecSELr ; C25M ; PHI0 ; 1.000 ; 2.798 ; 4.886 ; +--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ -+-------------------------------------------------------------------------------------------------------+ -; Hold: 'PHI0' ; -+-------+-----------+-------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+-------+-----------+-------------+--------------+-------------+--------------+------------+------------+ -; 1.092 ; Addr[23] ; RAMSpecSELr ; C25M ; PHI0 ; 0.000 ; 2.776 ; 4.089 ; -; 1.423 ; REGEN ; RAMSpecSELr ; C25M ; PHI0 ; 0.000 ; 2.776 ; 4.420 ; -; 1.468 ; Addr[21] ; RAMSpecSELr ; C25M ; PHI0 ; 0.000 ; 2.776 ; 4.465 ; -; 1.503 ; Addr[20] ; RAMSpecSELr ; C25M ; PHI0 ; 0.000 ; 2.776 ; 4.500 ; -; 1.804 ; Addr[22] ; RAMSpecSELr ; C25M ; PHI0 ; 0.000 ; 2.776 ; 4.801 ; -+-------+-----------+-------------+--------------+-------------+--------------+------------+------------+ - - +---------------------------------------------------------------------------------------------------------------+ ; Hold: 'C25M' ; +-------+----------------+----------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +-------+----------------+----------------+--------------+-------------+--------------+------------+------------+ -; 1.418 ; PHI0r1 ; PHI0r2 ; C25M ; C25M ; 0.000 ; 0.000 ; 1.639 ; -; 1.537 ; PHI0 ; PHI0r1 ; PHI0 ; C25M ; 0.000 ; 3.458 ; 5.216 ; -; 1.899 ; Bank ; Bank ; C25M ; C25M ; 0.000 ; 0.000 ; 2.120 ; -; 1.929 ; Addr[7] ; AddrIncM ; C25M ; C25M ; 0.000 ; 0.000 ; 2.150 ; -; 1.939 ; Addr[15] ; AddrIncH ; C25M ; C25M ; 0.000 ; 0.000 ; 2.160 ; -; 1.946 ; REGEN ; REGEN ; C25M ; C25M ; 0.000 ; 0.000 ; 2.167 ; -; 1.956 ; PS[2] ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.177 ; -; 1.986 ; IS.state_bit_2 ; IS.state_bit_0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.207 ; -; 2.037 ; PHI0 ; PHI0r1 ; PHI0 ; C25M ; -0.500 ; 3.458 ; 5.216 ; -; 2.048 ; LS[13] ; LS[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.269 ; -; 2.116 ; LS[7] ; LS[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.337 ; -; 2.117 ; Addr[10] ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; +; 1.384 ; WRD[6] ; WRD[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.605 ; +; 1.384 ; WRD[7] ; WRD[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.605 ; +; 1.398 ; nRESr0 ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 1.619 ; +; 1.404 ; WRD[2] ; WRD[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.625 ; +; 1.547 ; PHI0 ; PHI0r1 ; PHI0 ; C25M ; 0.000 ; 3.458 ; 5.226 ; +; 1.658 ; nRESout~reg0 ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 1.879 ; +; 1.668 ; PS[3] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.889 ; +; 1.676 ; LS[0] ; LS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.897 ; +; 1.799 ; WRD[0] ; WRD[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.020 ; +; 1.835 ; WRD[5] ; WRD[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.056 ; +; 1.898 ; Bank ; Bank ; C25M ; C25M ; 0.000 ; 0.000 ; 2.119 ; +; 1.936 ; IOROMEN ; IOROMEN ; C25M ; C25M ; 0.000 ; 0.000 ; 2.157 ; +; 1.963 ; IS.state_bit_0 ; IS.state_bit_0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.184 ; +; 1.965 ; IS.state_bit_0 ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.186 ; +; 1.965 ; PS[1] ; PS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.186 ; +; 1.974 ; PS[1] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.195 ; +; 2.047 ; PHI0 ; PHI0r1 ; PHI0 ; C25M ; -0.500 ; 3.458 ; 5.226 ; +; 2.107 ; LS[7] ; LS[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.328 ; +; 2.109 ; Addr[15] ; AddrIncH ; C25M ; C25M ; 0.000 ; 0.000 ; 2.330 ; +; 2.117 ; Addr[1] ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; +; 2.117 ; Addr[2] ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; +; 2.117 ; Addr[15] ; Addr[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; ; 2.117 ; Addr[17] ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; ; 2.117 ; Addr[18] ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; -; 2.117 ; Addr[9] ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; -; 2.124 ; Addr[0] ; Addr[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.345 ; +; 2.117 ; LS[9] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; +; 2.120 ; WRD[5] ; WRD[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.341 ; +; 2.121 ; WRD[3] ; WRD[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.342 ; ; 2.125 ; Addr[16] ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.346 ; -; 2.127 ; LS[6] ; LS[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.348 ; -; 2.132 ; Addr[8] ; Addr[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.353 ; -; 2.134 ; Addr[1] ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.355 ; -; 2.135 ; Addr[2] ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.356 ; -; 2.137 ; Addr[7] ; Addr[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.358 ; -; 2.143 ; LS[8] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.364 ; -; 2.145 ; Addr[15] ; Addr[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.366 ; -; 2.145 ; LS[9] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.366 ; -; 2.146 ; LS[0] ; LS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.367 ; -; 2.151 ; PS[0] ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.372 ; -; 2.151 ; LS[4] ; LS[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.372 ; -; 2.159 ; PS[2] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.380 ; -; 2.180 ; IS.state_bit_0 ; IS.state_bit_0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.401 ; +; 2.126 ; Addr[23] ; Addr[23] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ; +; 2.126 ; Addr[10] ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ; +; 2.126 ; Addr[7] ; Addr[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ; +; 2.134 ; Addr[0] ; Addr[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.355 ; +; 2.134 ; Addr[9] ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.355 ; +; 2.135 ; LS[6] ; LS[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.356 ; +; 2.139 ; WRD[2] ; WRD[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.360 ; +; 2.144 ; LS[4] ; LS[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.365 ; +; 2.212 ; Addr[3] ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.433 ; ; 2.212 ; Addr[19] ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.433 ; -; 2.222 ; Addr[11] ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.443 ; -; 2.222 ; Addr[3] ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.443 ; -; 2.223 ; nRESout~reg0 ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.444 ; -; 2.229 ; IOROMEN ; IOROMEN ; C25M ; C25M ; 0.000 ; 0.000 ; 2.450 ; -; 2.229 ; LS[12] ; LS[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.450 ; -; 2.230 ; Addr[13] ; Addr[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.451 ; +; 2.223 ; WRD[4] ; WRD[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.444 ; +; 2.226 ; WRD[0] ; WRD[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.447 ; +; 2.230 ; LS[12] ; LS[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.451 ; ; 2.230 ; Addr[5] ; Addr[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.451 ; -; 2.231 ; Addr[12] ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; +; 2.230 ; Addr[21] ; Addr[21] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.451 ; ; 2.231 ; Addr[4] ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; -; 2.231 ; Addr[14] ; Addr[14] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; ; 2.231 ; Addr[6] ; Addr[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; ; 2.231 ; Addr[20] ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; -; 2.241 ; LS[11] ; LS[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.462 ; -; 2.251 ; LS[2] ; LS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.472 ; -; 2.252 ; LS[1] ; LS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.473 ; -; 2.253 ; LS[10] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.474 ; -; 2.259 ; LS[5] ; LS[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.480 ; -; 2.260 ; PS[3] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.481 ; -; 2.295 ; PS[0] ; WRD[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.516 ; -; 2.403 ; PS[0] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.624 ; -; 2.509 ; PS[0] ; FCKout ; C25M ; C25M ; 0.000 ; 0.000 ; 2.730 ; -; 2.535 ; LS[0] ; LS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.756 ; -; 2.536 ; Addr[22] ; Addr[22] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.757 ; -; 2.549 ; LS[3] ; LS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.770 ; -; 2.700 ; Addr[21] ; Addr[21] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.921 ; -; 2.725 ; IS.state_bit_1 ; IS.state_bit_2 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.946 ; -; 2.730 ; IS.state_bit_1 ; IS.state_bit_0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.951 ; -; 2.892 ; IS.state_bit_2 ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.113 ; -; 2.909 ; PS[2] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.130 ; -; 2.948 ; LS[7] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.169 ; -; 2.949 ; Addr[9] ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; -; 2.949 ; Addr[10] ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; +; 2.231 ; Addr[22] ; Addr[22] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; +; 2.231 ; LS[13] ; LS[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; +; 2.241 ; Addr[11] ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.462 ; +; 2.249 ; Addr[12] ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.470 ; +; 2.250 ; LS[1] ; LS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.471 ; +; 2.251 ; LS[5] ; LS[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.472 ; +; 2.260 ; Addr[13] ; Addr[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.481 ; +; 2.261 ; LS[2] ; LS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.482 ; +; 2.262 ; LS[3] ; LS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.483 ; +; 2.262 ; Addr[14] ; Addr[14] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.483 ; +; 2.284 ; PS[1] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.505 ; +; 2.359 ; Addr[6] ; RDD[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.580 ; +; 2.443 ; PS[0] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.664 ; +; 2.509 ; LS[11] ; LS[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.730 ; +; 2.530 ; LS[8] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.751 ; +; 2.553 ; Addr[21] ; RDD[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.774 ; +; 2.564 ; Addr[3] ; RDD[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.785 ; +; 2.636 ; Addr[7] ; AddrIncM ; C25M ; C25M ; 0.000 ; 0.000 ; 2.857 ; +; 2.648 ; PS[0] ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.869 ; +; 2.651 ; PS[0] ; PS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.872 ; +; 2.655 ; IS.state_bit_1 ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.876 ; +; 2.656 ; IS.state_bit_1 ; IS.state_bit_0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.877 ; +; 2.673 ; Addr[19] ; RDD[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.894 ; +; 2.674 ; Addr[5] ; RDD[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.895 ; +; 2.930 ; IS.state_bit_0 ; FCKOE ; C25M ; C25M ; 0.000 ; 0.000 ; 3.151 ; +; 2.939 ; LS[7] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.160 ; +; 2.947 ; IS.state_bit_2 ; FCS ; C25M ; C25M ; 0.000 ; 0.000 ; 3.168 ; +; 2.949 ; LS[9] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; +; 2.949 ; Addr[1] ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; +; 2.949 ; Addr[2] ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; ; 2.949 ; Addr[17] ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; ; 2.949 ; Addr[18] ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; -; 2.956 ; Addr[0] ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.177 ; ; 2.957 ; Addr[16] ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.178 ; -; 2.958 ; IS.state_bit_2 ; FCKOE ; C25M ; C25M ; 0.000 ; 0.000 ; 3.179 ; -; 2.963 ; IS.state_bit_2 ; FCS ; C25M ; C25M ; 0.000 ; 0.000 ; 3.184 ; -; 2.964 ; Addr[8] ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.185 ; -; 2.966 ; Addr[1] ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.187 ; -; 2.967 ; Addr[2] ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.188 ; -; 2.975 ; LS[8] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.196 ; -; 2.977 ; LS[9] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.198 ; -; 2.978 ; Addr[2] ; RDD[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.199 ; -; 2.982 ; REGEN ; Bank ; C25M ; C25M ; 0.000 ; 0.000 ; 3.203 ; -; 2.983 ; LS[4] ; LS[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.204 ; -; 3.059 ; LS[7] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.280 ; -; 3.060 ; Addr[10] ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ; +; 2.958 ; Addr[10] ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.179 ; +; 2.960 ; Addr[20] ; SA[10]~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.181 ; +; 2.966 ; Addr[9] ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.187 ; +; 2.966 ; Addr[0] ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.187 ; +; 2.976 ; LS[4] ; LS[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.197 ; +; 3.014 ; PHI0r1 ; PHI0r2 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.235 ; +; 3.050 ; LS[7] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.271 ; +; 3.055 ; AddrIncM ; Addr[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.276 ; +; 3.060 ; LS[9] ; LS[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ; +; 3.060 ; Addr[2] ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ; ; 3.060 ; Addr[18] ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ; -; 3.060 ; Addr[9] ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ; +; 3.060 ; Addr[1] ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ; ; 3.060 ; Addr[17] ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ; -; 3.067 ; Addr[0] ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.288 ; -; 3.068 ; PHI0r1 ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.289 ; ; 3.068 ; Addr[16] ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.289 ; -; 3.075 ; Addr[8] ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.296 ; -; 3.077 ; Addr[1] ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.298 ; -; 3.078 ; Addr[2] ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.299 ; -; 3.086 ; LS[8] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.307 ; -; 3.088 ; LS[9] ; LS[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.309 ; -; 3.089 ; Addr[0] ; DQMH~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.310 ; -; 3.094 ; LS[4] ; LS[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.315 ; -; 3.095 ; Addr[0] ; DQML~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.316 ; -; 3.113 ; Addr[2] ; SA[1]~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.334 ; -; 3.152 ; Addr[19] ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.373 ; -; 3.162 ; Addr[11] ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.383 ; -; 3.162 ; Addr[3] ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.383 ; -; 3.169 ; LS[12] ; LS[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.390 ; -; 3.170 ; Addr[13] ; Addr[14] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.391 ; -; 3.170 ; Addr[5] ; Addr[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.391 ; +; 3.069 ; Addr[10] ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.290 ; +; 3.077 ; Addr[0] ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.298 ; +; 3.077 ; Addr[9] ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.298 ; +; 3.087 ; LS[4] ; LS[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.308 ; +; 3.099 ; PS[3] ; IOROMEN ; C25M ; C25M ; 0.000 ; 0.000 ; 3.320 ; +; 3.099 ; Addr[20] ; RDD[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.320 ; +; 3.139 ; Addr[21] ; SA[11]~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.360 ; +-------+----------------+----------------+--------------+-------------+--------------+------------+------------+ ++-------------------------------------------------------------------------------------------------------+ +; Hold: 'PHI0' ; ++-------+-----------+-------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+-----------+-------------+--------------+-------------+--------------+------------+------------+ +; 1.867 ; REGEN ; RAMSpecSELr ; C25M ; PHI0 ; 0.000 ; 2.798 ; 4.886 ; ++-------+-----------+-------------+--------------+-------------+--------------+------------+------------+ + + +-----------------------------------------------------------------------------------------------------+ ; Recovery: 'C25M' ; +--------+-----------+----------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+-----------+----------+--------------+-------------+--------------+------------+------------+ -; -5.009 ; nRESr ; IOROMEN ; C25M ; C25M ; 1.000 ; 0.000 ; 5.676 ; -; -5.009 ; nRESr ; Addr[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.676 ; -; -5.009 ; nRESr ; Addr[23] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.676 ; -; -5.009 ; nRESr ; Addr[10] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.676 ; -; -5.009 ; nRESr ; Addr[1] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.676 ; -; -5.009 ; nRESr ; Addr[11] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.676 ; -; -5.009 ; nRESr ; Addr[2] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.676 ; -; -5.009 ; nRESr ; Addr[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.676 ; -; -5.009 ; nRESr ; Bank ; C25M ; C25M ; 1.000 ; 0.000 ; 5.676 ; -; -5.009 ; nRESr ; Addr[3] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.676 ; -; -5.009 ; nRESr ; Addr[13] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.676 ; -; -5.009 ; nRESr ; Addr[4] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.676 ; -; -5.009 ; nRESr ; Addr[14] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.676 ; -; -5.009 ; nRESr ; Addr[5] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.676 ; -; -5.009 ; nRESr ; Addr[15] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.676 ; -; -5.009 ; nRESr ; Addr[6] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.676 ; -; -5.009 ; nRESr ; Addr[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.676 ; -; -5.009 ; nRESr ; Addr[7] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.676 ; -; -5.009 ; nRESr ; Addr[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.676 ; -; -5.009 ; nRESr ; Addr[8] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.676 ; -; -5.009 ; nRESr ; Addr[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.676 ; -; -5.009 ; nRESr ; Addr[9] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.676 ; -; -5.009 ; nRESr ; Addr[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.676 ; -; -5.009 ; nRESr ; Addr[20] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.676 ; -; -5.009 ; nRESr ; Addr[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.676 ; -; -5.009 ; nRESr ; Addr[22] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.676 ; -; -5.009 ; nRESr ; REGEN ; C25M ; C25M ; 1.000 ; 0.000 ; 5.676 ; -; -5.009 ; nRESr ; AddrIncH ; C25M ; C25M ; 1.000 ; 0.000 ; 5.676 ; -; -5.009 ; nRESr ; AddrIncM ; C25M ; C25M ; 1.000 ; 0.000 ; 5.676 ; -; -5.009 ; nRESr ; AddrIncL ; C25M ; C25M ; 1.000 ; 0.000 ; 5.676 ; +; -4.406 ; nRESr ; IOROMEN ; C25M ; C25M ; 1.000 ; 0.000 ; 5.073 ; +; -4.406 ; nRESr ; Addr[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.073 ; +; -4.406 ; nRESr ; Addr[23] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.073 ; +; -4.406 ; nRESr ; Addr[10] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.073 ; +; -4.406 ; nRESr ; Addr[1] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.073 ; +; -4.406 ; nRESr ; Addr[11] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.073 ; +; -4.406 ; nRESr ; Addr[2] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.073 ; +; -4.406 ; nRESr ; Addr[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.073 ; +; -4.406 ; nRESr ; Bank ; C25M ; C25M ; 1.000 ; 0.000 ; 5.073 ; +; -4.406 ; nRESr ; Addr[3] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.073 ; +; -4.406 ; nRESr ; Addr[13] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.073 ; +; -4.406 ; nRESr ; Addr[4] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.073 ; +; -4.406 ; nRESr ; Addr[14] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.073 ; +; -4.406 ; nRESr ; Addr[5] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.073 ; +; -4.406 ; nRESr ; Addr[15] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.073 ; +; -4.406 ; nRESr ; Addr[6] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.073 ; +; -4.406 ; nRESr ; Addr[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.073 ; +; -4.406 ; nRESr ; Addr[7] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.073 ; +; -4.406 ; nRESr ; Addr[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.073 ; +; -4.406 ; nRESr ; Addr[8] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.073 ; +; -4.406 ; nRESr ; Addr[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.073 ; +; -4.406 ; nRESr ; Addr[9] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.073 ; +; -4.406 ; nRESr ; Addr[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.073 ; +; -4.406 ; nRESr ; Addr[20] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.073 ; +; -4.406 ; nRESr ; Addr[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.073 ; +; -4.406 ; nRESr ; Addr[22] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.073 ; +; -4.406 ; nRESr ; REGEN ; C25M ; C25M ; 1.000 ; 0.000 ; 5.073 ; +; -4.406 ; nRESr ; AddrIncH ; C25M ; C25M ; 1.000 ; 0.000 ; 5.073 ; +; -4.406 ; nRESr ; AddrIncM ; C25M ; C25M ; 1.000 ; 0.000 ; 5.073 ; +; -4.406 ; nRESr ; AddrIncL ; C25M ; C25M ; 1.000 ; 0.000 ; 5.073 ; +--------+-----------+----------+--------------+-------------+--------------+------------+------------+ @@ -441,36 +433,36 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+-----------+----------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +-------+-----------+----------+--------------+-------------+--------------+------------+------------+ -; 5.455 ; nRESr ; IOROMEN ; C25M ; C25M ; 0.000 ; 0.000 ; 5.676 ; -; 5.455 ; nRESr ; Addr[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.676 ; -; 5.455 ; nRESr ; Addr[23] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.676 ; -; 5.455 ; nRESr ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.676 ; -; 5.455 ; nRESr ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.676 ; -; 5.455 ; nRESr ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.676 ; -; 5.455 ; nRESr ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.676 ; -; 5.455 ; nRESr ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.676 ; -; 5.455 ; nRESr ; Bank ; C25M ; C25M ; 0.000 ; 0.000 ; 5.676 ; -; 5.455 ; nRESr ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.676 ; -; 5.455 ; nRESr ; Addr[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.676 ; -; 5.455 ; nRESr ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.676 ; -; 5.455 ; nRESr ; Addr[14] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.676 ; -; 5.455 ; nRESr ; Addr[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.676 ; -; 5.455 ; nRESr ; Addr[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.676 ; -; 5.455 ; nRESr ; Addr[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.676 ; -; 5.455 ; nRESr ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.676 ; -; 5.455 ; nRESr ; Addr[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.676 ; -; 5.455 ; nRESr ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.676 ; -; 5.455 ; nRESr ; Addr[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.676 ; -; 5.455 ; nRESr ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.676 ; -; 5.455 ; nRESr ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.676 ; -; 5.455 ; nRESr ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.676 ; -; 5.455 ; nRESr ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.676 ; -; 5.455 ; nRESr ; Addr[21] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.676 ; -; 5.455 ; nRESr ; Addr[22] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.676 ; -; 5.455 ; nRESr ; REGEN ; C25M ; C25M ; 0.000 ; 0.000 ; 5.676 ; -; 5.455 ; nRESr ; AddrIncH ; C25M ; C25M ; 0.000 ; 0.000 ; 5.676 ; -; 5.455 ; nRESr ; AddrIncM ; C25M ; C25M ; 0.000 ; 0.000 ; 5.676 ; -; 5.455 ; nRESr ; AddrIncL ; C25M ; C25M ; 0.000 ; 0.000 ; 5.676 ; +; 4.852 ; nRESr ; IOROMEN ; C25M ; C25M ; 0.000 ; 0.000 ; 5.073 ; +; 4.852 ; nRESr ; Addr[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.073 ; +; 4.852 ; nRESr ; Addr[23] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.073 ; +; 4.852 ; nRESr ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.073 ; +; 4.852 ; nRESr ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.073 ; +; 4.852 ; nRESr ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.073 ; +; 4.852 ; nRESr ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.073 ; +; 4.852 ; nRESr ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.073 ; +; 4.852 ; nRESr ; Bank ; C25M ; C25M ; 0.000 ; 0.000 ; 5.073 ; +; 4.852 ; nRESr ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.073 ; +; 4.852 ; nRESr ; Addr[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.073 ; +; 4.852 ; nRESr ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.073 ; +; 4.852 ; nRESr ; Addr[14] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.073 ; +; 4.852 ; nRESr ; Addr[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.073 ; +; 4.852 ; nRESr ; Addr[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.073 ; +; 4.852 ; nRESr ; Addr[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.073 ; +; 4.852 ; nRESr ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.073 ; +; 4.852 ; nRESr ; Addr[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.073 ; +; 4.852 ; nRESr ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.073 ; +; 4.852 ; nRESr ; Addr[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.073 ; +; 4.852 ; nRESr ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.073 ; +; 4.852 ; nRESr ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.073 ; +; 4.852 ; nRESr ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.073 ; +; 4.852 ; nRESr ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.073 ; +; 4.852 ; nRESr ; Addr[21] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.073 ; +; 4.852 ; nRESr ; Addr[22] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.073 ; +; 4.852 ; nRESr ; REGEN ; C25M ; C25M ; 0.000 ; 0.000 ; 5.073 ; +; 4.852 ; nRESr ; AddrIncH ; C25M ; C25M ; 0.000 ; 0.000 ; 5.073 ; +; 4.852 ; nRESr ; AddrIncM ; C25M ; C25M ; 0.000 ; 0.000 ; 5.073 ; +; 4.852 ; nRESr ; AddrIncL ; C25M ; C25M ; 0.000 ; 0.000 ; 5.073 ; +-------+-----------+----------+--------------+-------------+--------------+------------+------------+ @@ -590,16 +582,16 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp ; -2.289 ; 1.000 ; 3.289 ; Port Rate ; PHI0 ; Rise ; PHI0 ; ; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI0 ; Rise ; RAMSpecSELr ; ; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI0 ; Rise ; RAMSpecSELr ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI0 ; Rise ; ROMSpecSELr ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI0 ; Rise ; ROMSpecSELr ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI0 ; Rise ; ROMSpecRDr ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI0 ; Rise ; ROMSpecRDr ; ; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI0 ; Rise ; nWEr ; ; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI0 ; Rise ; nWEr ; ; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI0 ; Rise ; PHI0|combout ; ; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI0 ; Rise ; PHI0|combout ; ; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI0 ; Rise ; RAMSpecSELr|clk ; ; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI0 ; Rise ; RAMSpecSELr|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI0 ; Rise ; ROMSpecSELr|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI0 ; Rise ; ROMSpecSELr|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI0 ; Rise ; ROMSpecRDr|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI0 ; Rise ; ROMSpecRDr|clk ; ; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI0 ; Rise ; nWEr|clk ; ; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI0 ; Rise ; nWEr|clk ; +--------+--------------+----------------+------------------+-------+------------+-----------------+ @@ -610,141 +602,129 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-----------+------------+--------+--------+------------+-----------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+--------+--------+------------+-----------------+ -; MISO ; C25M ; 3.207 ; 3.207 ; Rise ; C25M ; -; MOSI ; C25M ; 4.773 ; 4.773 ; Rise ; C25M ; -; PHI0 ; C25M ; 2.091 ; 2.091 ; Rise ; C25M ; -; RA[*] ; C25M ; 15.448 ; 15.448 ; Rise ; C25M ; -; RA[0] ; C25M ; 8.995 ; 8.995 ; Rise ; C25M ; -; RA[1] ; C25M ; 9.363 ; 9.363 ; Rise ; C25M ; -; RA[2] ; C25M ; 10.605 ; 10.605 ; Rise ; C25M ; -; RA[3] ; C25M ; 12.017 ; 12.017 ; Rise ; C25M ; -; RA[4] ; C25M ; 9.957 ; 9.957 ; Rise ; C25M ; -; RA[5] ; C25M ; 7.815 ; 7.815 ; Rise ; C25M ; -; RA[6] ; C25M ; 8.525 ; 8.525 ; Rise ; C25M ; -; RA[7] ; C25M ; 12.425 ; 12.425 ; Rise ; C25M ; -; RA[8] ; C25M ; 15.042 ; 15.042 ; Rise ; C25M ; -; RA[9] ; C25M ; 14.757 ; 14.757 ; Rise ; C25M ; -; RA[10] ; C25M ; 13.247 ; 13.247 ; Rise ; C25M ; -; RA[11] ; C25M ; 14.731 ; 14.731 ; Rise ; C25M ; -; RA[12] ; C25M ; 15.345 ; 15.345 ; Rise ; C25M ; -; RA[13] ; C25M ; 14.789 ; 14.789 ; Rise ; C25M ; -; RA[14] ; C25M ; 15.448 ; 15.448 ; Rise ; C25M ; -; RA[15] ; C25M ; 14.916 ; 14.916 ; Rise ; C25M ; -; RD[*] ; C25M ; 4.859 ; 4.859 ; Rise ; C25M ; -; RD[0] ; C25M ; 3.485 ; 3.485 ; Rise ; C25M ; -; RD[1] ; C25M ; 3.672 ; 3.672 ; Rise ; C25M ; -; RD[2] ; C25M ; 4.859 ; 4.859 ; Rise ; C25M ; -; RD[3] ; C25M ; 3.853 ; 3.853 ; Rise ; C25M ; -; RD[4] ; C25M ; 4.312 ; 4.312 ; Rise ; C25M ; -; RD[5] ; C25M ; 3.181 ; 3.181 ; Rise ; C25M ; -; RD[6] ; C25M ; 4.216 ; 4.216 ; Rise ; C25M ; -; RD[7] ; C25M ; 4.228 ; 4.228 ; Rise ; C25M ; -; SD[*] ; C25M ; 6.673 ; 6.673 ; Rise ; C25M ; -; SD[0] ; C25M ; 3.461 ; 3.461 ; Rise ; C25M ; -; SD[1] ; C25M ; 3.140 ; 3.140 ; Rise ; C25M ; -; SD[2] ; C25M ; 6.673 ; 6.673 ; Rise ; C25M ; -; SD[3] ; C25M ; 4.786 ; 4.786 ; Rise ; C25M ; -; SD[4] ; C25M ; 3.431 ; 3.431 ; Rise ; C25M ; -; SD[5] ; C25M ; 3.118 ; 3.118 ; Rise ; C25M ; -; SD[6] ; C25M ; 3.112 ; 3.112 ; Rise ; C25M ; -; SD[7] ; C25M ; 3.792 ; 3.792 ; Rise ; C25M ; -; SetFW[*] ; C25M ; 10.023 ; 10.023 ; Rise ; C25M ; -; SetFW[0] ; C25M ; 10.023 ; 10.023 ; Rise ; C25M ; -; SetFW[1] ; C25M ; 9.330 ; 9.330 ; Rise ; C25M ; -; nDEVSEL ; C25M ; 9.087 ; 9.087 ; Rise ; C25M ; -; nIOSEL ; C25M ; 3.410 ; 3.410 ; Rise ; C25M ; -; nIOSTRB ; C25M ; 7.724 ; 7.724 ; Rise ; C25M ; -; nRES ; C25M ; 3.263 ; 3.263 ; Rise ; C25M ; -; RA[*] ; PHI0 ; 7.446 ; 7.446 ; Rise ; PHI0 ; -; RA[0] ; PHI0 ; 0.649 ; 0.649 ; Rise ; PHI0 ; -; RA[1] ; PHI0 ; 4.217 ; 4.217 ; Rise ; PHI0 ; -; RA[2] ; PHI0 ; 2.603 ; 2.603 ; Rise ; PHI0 ; -; RA[3] ; PHI0 ; 4.015 ; 4.015 ; Rise ; PHI0 ; -; RA[7] ; PHI0 ; 4.423 ; 4.423 ; Rise ; PHI0 ; -; RA[8] ; PHI0 ; 7.040 ; 7.040 ; Rise ; PHI0 ; -; RA[9] ; PHI0 ; 6.755 ; 6.755 ; Rise ; PHI0 ; -; RA[10] ; PHI0 ; 5.245 ; 5.245 ; Rise ; PHI0 ; -; RA[11] ; PHI0 ; 6.729 ; 6.729 ; Rise ; PHI0 ; -; RA[12] ; PHI0 ; 7.343 ; 7.343 ; Rise ; PHI0 ; -; RA[13] ; PHI0 ; 6.787 ; 6.787 ; Rise ; PHI0 ; -; RA[14] ; PHI0 ; 7.446 ; 7.446 ; Rise ; PHI0 ; -; RA[15] ; PHI0 ; 6.914 ; 6.914 ; Rise ; PHI0 ; -; SetFW[*] ; PHI0 ; 4.443 ; 4.443 ; Rise ; PHI0 ; -; SetFW[0] ; PHI0 ; 1.360 ; 1.360 ; Rise ; PHI0 ; -; SetFW[1] ; PHI0 ; 4.443 ; 4.443 ; Rise ; PHI0 ; -; nWE ; PHI0 ; 4.843 ; 4.843 ; Rise ; PHI0 ; +; MISO ; C25M ; 3.807 ; 3.807 ; Rise ; C25M ; +; MOSI ; C25M ; 4.796 ; 4.796 ; Rise ; C25M ; +; PHI0 ; C25M ; 2.101 ; 2.101 ; Rise ; C25M ; +; RA[*] ; C25M ; 14.823 ; 14.823 ; Rise ; C25M ; +; RA[0] ; C25M ; 8.586 ; 8.586 ; Rise ; C25M ; +; RA[1] ; C25M ; 8.040 ; 8.040 ; Rise ; C25M ; +; RA[2] ; C25M ; 9.634 ; 9.634 ; Rise ; C25M ; +; RA[3] ; C25M ; 11.057 ; 11.057 ; Rise ; C25M ; +; RA[4] ; C25M ; 6.959 ; 6.959 ; Rise ; C25M ; +; RA[5] ; C25M ; 6.713 ; 6.713 ; Rise ; C25M ; +; RA[6] ; C25M ; 7.150 ; 7.150 ; Rise ; C25M ; +; RA[7] ; C25M ; 11.336 ; 11.336 ; Rise ; C25M ; +; RA[8] ; C25M ; 12.770 ; 12.770 ; Rise ; C25M ; +; RA[9] ; C25M ; 14.823 ; 14.823 ; Rise ; C25M ; +; RA[10] ; C25M ; 12.695 ; 12.695 ; Rise ; C25M ; +; RA[11] ; C25M ; 11.834 ; 11.834 ; Rise ; C25M ; +; RA[12] ; C25M ; 9.991 ; 9.991 ; Rise ; C25M ; +; RA[13] ; C25M ; 10.495 ; 10.495 ; Rise ; C25M ; +; RA[14] ; C25M ; 10.325 ; 10.325 ; Rise ; C25M ; +; RA[15] ; C25M ; 10.651 ; 10.651 ; Rise ; C25M ; +; RD[*] ; C25M ; 6.055 ; 6.055 ; Rise ; C25M ; +; RD[0] ; C25M ; 3.934 ; 3.934 ; Rise ; C25M ; +; RD[1] ; C25M ; 3.469 ; 3.469 ; Rise ; C25M ; +; RD[2] ; C25M ; 3.972 ; 3.972 ; Rise ; C25M ; +; RD[3] ; C25M ; 3.908 ; 3.908 ; Rise ; C25M ; +; RD[4] ; C25M ; 4.078 ; 4.078 ; Rise ; C25M ; +; RD[5] ; C25M ; 4.859 ; 4.859 ; Rise ; C25M ; +; RD[6] ; C25M ; 4.412 ; 4.412 ; Rise ; C25M ; +; RD[7] ; C25M ; 6.055 ; 6.055 ; Rise ; C25M ; +; SD[*] ; C25M ; 6.404 ; 6.404 ; Rise ; C25M ; +; SD[0] ; C25M ; 4.903 ; 4.903 ; Rise ; C25M ; +; SD[1] ; C25M ; 5.173 ; 5.173 ; Rise ; C25M ; +; SD[2] ; C25M ; 5.568 ; 5.568 ; Rise ; C25M ; +; SD[3] ; C25M ; 4.119 ; 4.119 ; Rise ; C25M ; +; SD[4] ; C25M ; 4.608 ; 4.608 ; Rise ; C25M ; +; SD[5] ; C25M ; 3.793 ; 3.793 ; Rise ; C25M ; +; SD[6] ; C25M ; 4.318 ; 4.318 ; Rise ; C25M ; +; SD[7] ; C25M ; 6.404 ; 6.404 ; Rise ; C25M ; +; nDEVSEL ; C25M ; 8.874 ; 8.874 ; Rise ; C25M ; +; nIOSEL ; C25M ; 4.688 ; 4.688 ; Rise ; C25M ; +; nIOSTRB ; C25M ; 6.542 ; 6.542 ; Rise ; C25M ; +; nRES ; C25M ; 3.240 ; 3.240 ; Rise ; C25M ; +; RA[*] ; PHI0 ; 8.690 ; 8.690 ; Rise ; PHI0 ; +; RA[0] ; PHI0 ; 2.027 ; 2.027 ; Rise ; PHI0 ; +; RA[1] ; PHI0 ; 1.242 ; 1.242 ; Rise ; PHI0 ; +; RA[2] ; PHI0 ; 3.501 ; 3.501 ; Rise ; PHI0 ; +; RA[3] ; PHI0 ; 4.924 ; 4.924 ; Rise ; PHI0 ; +; RA[7] ; PHI0 ; 5.203 ; 5.203 ; Rise ; PHI0 ; +; RA[8] ; PHI0 ; 6.637 ; 6.637 ; Rise ; PHI0 ; +; RA[9] ; PHI0 ; 8.690 ; 8.690 ; Rise ; PHI0 ; +; RA[10] ; PHI0 ; 6.562 ; 6.562 ; Rise ; PHI0 ; +; RA[11] ; PHI0 ; 5.701 ; 5.701 ; Rise ; PHI0 ; +; RA[12] ; PHI0 ; 4.533 ; 4.533 ; Rise ; PHI0 ; +; RA[13] ; PHI0 ; 5.037 ; 5.037 ; Rise ; PHI0 ; +; RA[14] ; PHI0 ; 4.867 ; 4.867 ; Rise ; PHI0 ; +; RA[15] ; PHI0 ; 5.193 ; 5.193 ; Rise ; PHI0 ; +; nWE ; PHI0 ; 0.784 ; 0.784 ; Rise ; PHI0 ; +-----------+------------+--------+--------+------------+-----------------+ -+---------------------------------------------------------------------------+ -; Hold Times ; -+-----------+------------+---------+---------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-----------+------------+---------+---------+------------+-----------------+ -; MISO ; C25M ; -2.653 ; -2.653 ; Rise ; C25M ; -; MOSI ; C25M ; -4.219 ; -4.219 ; Rise ; C25M ; -; PHI0 ; C25M ; -1.537 ; -1.537 ; Rise ; C25M ; -; RA[*] ; C25M ; -4.004 ; -4.004 ; Rise ; C25M ; -; RA[0] ; C25M ; -4.369 ; -4.369 ; Rise ; C25M ; -; RA[1] ; C25M ; -4.004 ; -4.004 ; Rise ; C25M ; -; RA[2] ; C25M ; -5.968 ; -5.968 ; Rise ; C25M ; -; RA[3] ; C25M ; -7.190 ; -7.190 ; Rise ; C25M ; -; RA[4] ; C25M ; -5.899 ; -5.899 ; Rise ; C25M ; -; RA[5] ; C25M ; -4.230 ; -4.230 ; Rise ; C25M ; -; RA[6] ; C25M ; -5.612 ; -5.612 ; Rise ; C25M ; -; RA[7] ; C25M ; -5.349 ; -5.349 ; Rise ; C25M ; -; RA[8] ; C25M ; -5.488 ; -5.488 ; Rise ; C25M ; -; RA[9] ; C25M ; -6.370 ; -6.370 ; Rise ; C25M ; -; RA[10] ; C25M ; -4.133 ; -4.133 ; Rise ; C25M ; -; RA[11] ; C25M ; -4.481 ; -4.481 ; Rise ; C25M ; -; RA[12] ; C25M ; -11.451 ; -11.451 ; Rise ; C25M ; -; RA[13] ; C25M ; -10.895 ; -10.895 ; Rise ; C25M ; -; RA[14] ; C25M ; -11.554 ; -11.554 ; Rise ; C25M ; -; RA[15] ; C25M ; -11.022 ; -11.022 ; Rise ; C25M ; -; RD[*] ; C25M ; -2.043 ; -2.043 ; Rise ; C25M ; -; RD[0] ; C25M ; -2.645 ; -2.645 ; Rise ; C25M ; -; RD[1] ; C25M ; -2.643 ; -2.643 ; Rise ; C25M ; -; RD[2] ; C25M ; -2.161 ; -2.161 ; Rise ; C25M ; -; RD[3] ; C25M ; -2.245 ; -2.245 ; Rise ; C25M ; -; RD[4] ; C25M ; -2.117 ; -2.117 ; Rise ; C25M ; -; RD[5] ; C25M ; -2.102 ; -2.102 ; Rise ; C25M ; -; RD[6] ; C25M ; -2.043 ; -2.043 ; Rise ; C25M ; -; RD[7] ; C25M ; -2.080 ; -2.080 ; Rise ; C25M ; -; SD[*] ; C25M ; -2.558 ; -2.558 ; Rise ; C25M ; -; SD[0] ; C25M ; -2.907 ; -2.907 ; Rise ; C25M ; -; SD[1] ; C25M ; -2.586 ; -2.586 ; Rise ; C25M ; -; SD[2] ; C25M ; -6.119 ; -6.119 ; Rise ; C25M ; -; SD[3] ; C25M ; -4.232 ; -4.232 ; Rise ; C25M ; -; SD[4] ; C25M ; -2.877 ; -2.877 ; Rise ; C25M ; -; SD[5] ; C25M ; -2.564 ; -2.564 ; Rise ; C25M ; -; SD[6] ; C25M ; -2.558 ; -2.558 ; Rise ; C25M ; -; SD[7] ; C25M ; -3.238 ; -3.238 ; Rise ; C25M ; -; SetFW[*] ; C25M ; -3.532 ; -3.532 ; Rise ; C25M ; -; SetFW[0] ; C25M ; -3.626 ; -3.626 ; Rise ; C25M ; -; SetFW[1] ; C25M ; -3.532 ; -3.532 ; Rise ; C25M ; -; nDEVSEL ; C25M ; -2.650 ; -2.650 ; Rise ; C25M ; -; nIOSEL ; C25M ; -2.835 ; -2.835 ; Rise ; C25M ; -; nIOSTRB ; C25M ; -6.727 ; -6.727 ; Rise ; C25M ; -; nRES ; C25M ; -2.709 ; -2.709 ; Rise ; C25M ; -; RA[*] ; PHI0 ; -0.095 ; -0.095 ; Rise ; PHI0 ; -; RA[0] ; PHI0 ; -0.095 ; -0.095 ; Rise ; PHI0 ; -; RA[1] ; PHI0 ; -3.663 ; -3.663 ; Rise ; PHI0 ; -; RA[2] ; PHI0 ; -2.049 ; -2.049 ; Rise ; PHI0 ; -; RA[3] ; PHI0 ; -3.461 ; -3.461 ; Rise ; PHI0 ; -; RA[7] ; PHI0 ; -3.869 ; -3.869 ; Rise ; PHI0 ; -; RA[8] ; PHI0 ; -2.719 ; -2.719 ; Rise ; PHI0 ; -; RA[9] ; PHI0 ; -2.434 ; -2.434 ; Rise ; PHI0 ; -; RA[10] ; PHI0 ; -0.924 ; -0.924 ; Rise ; PHI0 ; -; RA[11] ; PHI0 ; -2.408 ; -2.408 ; Rise ; PHI0 ; -; RA[12] ; PHI0 ; -4.978 ; -4.978 ; Rise ; PHI0 ; -; RA[13] ; PHI0 ; -4.422 ; -4.422 ; Rise ; PHI0 ; -; RA[14] ; PHI0 ; -5.081 ; -5.081 ; Rise ; PHI0 ; -; RA[15] ; PHI0 ; -4.549 ; -4.549 ; Rise ; PHI0 ; -; SetFW[*] ; PHI0 ; -0.806 ; -0.806 ; Rise ; PHI0 ; -; SetFW[0] ; PHI0 ; -0.806 ; -0.806 ; Rise ; PHI0 ; -; SetFW[1] ; PHI0 ; -3.889 ; -3.889 ; Rise ; PHI0 ; -; nWE ; PHI0 ; -4.289 ; -4.289 ; Rise ; PHI0 ; -+-----------+------------+---------+---------+------------+-----------------+ ++-------------------------------------------------------------------------+ +; Hold Times ; ++-----------+------------+--------+--------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+--------+--------+------------+-----------------+ +; MISO ; C25M ; -3.253 ; -3.253 ; Rise ; C25M ; +; MOSI ; C25M ; -4.242 ; -4.242 ; Rise ; C25M ; +; PHI0 ; C25M ; -1.547 ; -1.547 ; Rise ; C25M ; +; RA[*] ; C25M ; -3.716 ; -3.716 ; Rise ; C25M ; +; RA[0] ; C25M ; -3.716 ; -3.716 ; Rise ; C25M ; +; RA[1] ; C25M ; -3.753 ; -3.753 ; Rise ; C25M ; +; RA[2] ; C25M ; -5.743 ; -5.743 ; Rise ; C25M ; +; RA[3] ; C25M ; -6.033 ; -6.033 ; Rise ; C25M ; +; RA[4] ; C25M ; -5.827 ; -5.827 ; Rise ; C25M ; +; RA[5] ; C25M ; -5.069 ; -5.069 ; Rise ; C25M ; +; RA[6] ; C25M ; -5.769 ; -5.769 ; Rise ; C25M ; +; RA[7] ; C25M ; -5.902 ; -5.902 ; Rise ; C25M ; +; RA[8] ; C25M ; -4.498 ; -4.498 ; Rise ; C25M ; +; RA[9] ; C25M ; -4.646 ; -4.646 ; Rise ; C25M ; +; RA[10] ; C25M ; -5.696 ; -5.696 ; Rise ; C25M ; +; RA[11] ; C25M ; -4.623 ; -4.623 ; Rise ; C25M ; +; RA[12] ; C25M ; -6.309 ; -6.309 ; Rise ; C25M ; +; RA[13] ; C25M ; -6.813 ; -6.813 ; Rise ; C25M ; +; RA[14] ; C25M ; -6.643 ; -6.643 ; Rise ; C25M ; +; RA[15] ; C25M ; -6.969 ; -6.969 ; Rise ; C25M ; +; RD[*] ; C25M ; -2.112 ; -2.112 ; Rise ; C25M ; +; RD[0] ; C25M ; -2.658 ; -2.658 ; Rise ; C25M ; +; RD[1] ; C25M ; -2.117 ; -2.117 ; Rise ; C25M ; +; RD[2] ; C25M ; -2.212 ; -2.212 ; Rise ; C25M ; +; RD[3] ; C25M ; -2.645 ; -2.645 ; Rise ; C25M ; +; RD[4] ; C25M ; -2.151 ; -2.151 ; Rise ; C25M ; +; RD[5] ; C25M ; -2.112 ; -2.112 ; Rise ; C25M ; +; RD[6] ; C25M ; -2.241 ; -2.241 ; Rise ; C25M ; +; RD[7] ; C25M ; -2.167 ; -2.167 ; Rise ; C25M ; +; SD[*] ; C25M ; -3.239 ; -3.239 ; Rise ; C25M ; +; SD[0] ; C25M ; -4.349 ; -4.349 ; Rise ; C25M ; +; SD[1] ; C25M ; -4.619 ; -4.619 ; Rise ; C25M ; +; SD[2] ; C25M ; -5.014 ; -5.014 ; Rise ; C25M ; +; SD[3] ; C25M ; -3.565 ; -3.565 ; Rise ; C25M ; +; SD[4] ; C25M ; -4.054 ; -4.054 ; Rise ; C25M ; +; SD[5] ; C25M ; -3.239 ; -3.239 ; Rise ; C25M ; +; SD[6] ; C25M ; -3.764 ; -3.764 ; Rise ; C25M ; +; SD[7] ; C25M ; -5.850 ; -5.850 ; Rise ; C25M ; +; nDEVSEL ; C25M ; -2.601 ; -2.601 ; Rise ; C25M ; +; nIOSEL ; C25M ; -2.960 ; -2.960 ; Rise ; C25M ; +; nIOSTRB ; C25M ; -5.410 ; -5.410 ; Rise ; C25M ; +; nRES ; C25M ; -2.686 ; -2.686 ; Rise ; C25M ; +; RA[*] ; PHI0 ; -0.688 ; -0.688 ; Rise ; PHI0 ; +; RA[0] ; PHI0 ; -1.473 ; -1.473 ; Rise ; PHI0 ; +; RA[1] ; PHI0 ; -0.688 ; -0.688 ; Rise ; PHI0 ; +; RA[2] ; PHI0 ; -2.947 ; -2.947 ; Rise ; PHI0 ; +; RA[3] ; PHI0 ; -4.370 ; -4.370 ; Rise ; PHI0 ; +; RA[7] ; PHI0 ; -4.649 ; -4.649 ; Rise ; PHI0 ; +; RA[8] ; PHI0 ; -3.704 ; -3.704 ; Rise ; PHI0 ; +; RA[9] ; PHI0 ; -5.757 ; -5.757 ; Rise ; PHI0 ; +; RA[10] ; PHI0 ; -3.629 ; -3.629 ; Rise ; PHI0 ; +; RA[11] ; PHI0 ; -2.768 ; -2.768 ; Rise ; PHI0 ; +; RA[12] ; PHI0 ; -3.199 ; -3.199 ; Rise ; PHI0 ; +; RA[13] ; PHI0 ; -3.703 ; -3.703 ; Rise ; PHI0 ; +; RA[14] ; PHI0 ; -3.533 ; -3.533 ; Rise ; PHI0 ; +; RA[15] ; PHI0 ; -3.859 ; -3.859 ; Rise ; PHI0 ; +; nWE ; PHI0 ; 0.354 ; 0.354 ; Rise ; PHI0 ; ++-----------+------------+--------+--------+------------+-----------------+ +-------------------------------------------------------------------------+ @@ -752,113 +732,113 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-----------+------------+--------+--------+------------+-----------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+--------+--------+------------+-----------------+ -; DQMH ; C25M ; 8.822 ; 8.822 ; Rise ; C25M ; -; DQML ; C25M ; 11.807 ; 11.807 ; Rise ; C25M ; -; FCK ; C25M ; 8.749 ; 8.749 ; Rise ; C25M ; -; MOSI ; C25M ; 8.378 ; 8.378 ; Rise ; C25M ; -; RCKE ; C25M ; 9.898 ; 9.898 ; Rise ; C25M ; -; RD[*] ; C25M ; 10.058 ; 10.058 ; Rise ; C25M ; -; RD[0] ; C25M ; 10.058 ; 10.058 ; Rise ; C25M ; -; RD[1] ; C25M ; 8.785 ; 8.785 ; Rise ; C25M ; -; RD[2] ; C25M ; 9.255 ; 9.255 ; Rise ; C25M ; -; RD[3] ; C25M ; 9.249 ; 9.249 ; Rise ; C25M ; -; RD[4] ; C25M ; 8.834 ; 8.834 ; Rise ; C25M ; -; RD[5] ; C25M ; 9.259 ; 9.259 ; Rise ; C25M ; -; RD[6] ; C25M ; 8.783 ; 8.783 ; Rise ; C25M ; -; RD[7] ; C25M ; 8.702 ; 8.702 ; Rise ; C25M ; -; RDdir ; C25M ; 16.870 ; 16.870 ; Rise ; C25M ; -; SA[*] ; C25M ; 10.609 ; 10.609 ; Rise ; C25M ; -; SA[0] ; C25M ; 8.838 ; 8.838 ; Rise ; C25M ; -; SA[1] ; C25M ; 10.609 ; 10.609 ; Rise ; C25M ; -; SA[2] ; C25M ; 9.346 ; 9.346 ; Rise ; C25M ; -; SA[3] ; C25M ; 8.149 ; 8.149 ; Rise ; C25M ; -; SA[4] ; C25M ; 8.023 ; 8.023 ; Rise ; C25M ; -; SA[5] ; C25M ; 8.225 ; 8.225 ; Rise ; C25M ; -; SA[6] ; C25M ; 8.559 ; 8.559 ; Rise ; C25M ; -; SA[7] ; C25M ; 8.483 ; 8.483 ; Rise ; C25M ; -; SA[8] ; C25M ; 7.589 ; 7.589 ; Rise ; C25M ; -; SA[9] ; C25M ; 8.230 ; 8.230 ; Rise ; C25M ; -; SA[10] ; C25M ; 8.766 ; 8.766 ; Rise ; C25M ; -; SA[11] ; C25M ; 8.394 ; 8.394 ; Rise ; C25M ; -; SA[12] ; C25M ; 8.338 ; 8.338 ; Rise ; C25M ; -; SBA[*] ; C25M ; 8.683 ; 8.683 ; Rise ; C25M ; -; SBA[0] ; C25M ; 8.683 ; 8.683 ; Rise ; C25M ; -; SBA[1] ; C25M ; 8.474 ; 8.474 ; Rise ; C25M ; -; SD[*] ; C25M ; 10.171 ; 10.171 ; Rise ; C25M ; -; SD[0] ; C25M ; 8.728 ; 8.728 ; Rise ; C25M ; -; SD[1] ; C25M ; 8.231 ; 8.231 ; Rise ; C25M ; -; SD[2] ; C25M ; 8.242 ; 8.242 ; Rise ; C25M ; -; SD[3] ; C25M ; 8.828 ; 8.828 ; Rise ; C25M ; -; SD[4] ; C25M ; 10.171 ; 10.171 ; Rise ; C25M ; -; SD[5] ; C25M ; 8.719 ; 8.719 ; Rise ; C25M ; -; SD[6] ; C25M ; 6.942 ; 6.942 ; Rise ; C25M ; -; SD[7] ; C25M ; 8.113 ; 8.113 ; Rise ; C25M ; -; nCAS ; C25M ; 8.009 ; 8.009 ; Rise ; C25M ; -; nFCS ; C25M ; 9.004 ; 9.004 ; Rise ; C25M ; -; nRAS ; C25M ; 8.417 ; 8.417 ; Rise ; C25M ; -; nRCS ; C25M ; 11.091 ; 11.091 ; Rise ; C25M ; -; nRESout ; C25M ; 9.056 ; 9.056 ; Rise ; C25M ; -; nSWE ; C25M ; 8.685 ; 8.685 ; Rise ; C25M ; -; RDdir ; PHI0 ; 12.126 ; 12.126 ; Rise ; PHI0 ; -; RDdir ; PHI0 ; 12.126 ; 12.126 ; Fall ; PHI0 ; +; DQMH ; C25M ; 9.467 ; 9.467 ; Rise ; C25M ; +; DQML ; C25M ; 8.761 ; 8.761 ; Rise ; C25M ; +; FCK ; C25M ; 8.921 ; 8.921 ; Rise ; C25M ; +; MOSI ; C25M ; 7.606 ; 7.606 ; Rise ; C25M ; +; RCKE ; C25M ; 8.729 ; 8.729 ; Rise ; C25M ; +; RD[*] ; C25M ; 9.082 ; 9.082 ; Rise ; C25M ; +; RD[0] ; C25M ; 8.674 ; 8.674 ; Rise ; C25M ; +; RD[1] ; C25M ; 6.959 ; 6.959 ; Rise ; C25M ; +; RD[2] ; C25M ; 6.944 ; 6.944 ; Rise ; C25M ; +; RD[3] ; C25M ; 8.301 ; 8.301 ; Rise ; C25M ; +; RD[4] ; C25M ; 8.292 ; 8.292 ; Rise ; C25M ; +; RD[5] ; C25M ; 8.457 ; 8.457 ; Rise ; C25M ; +; RD[6] ; C25M ; 9.082 ; 9.082 ; Rise ; C25M ; +; RD[7] ; C25M ; 8.143 ; 8.143 ; Rise ; C25M ; +; RDdir ; C25M ; 11.821 ; 11.821 ; Rise ; C25M ; +; SA[*] ; C25M ; 9.176 ; 9.176 ; Rise ; C25M ; +; SA[0] ; C25M ; 8.347 ; 8.347 ; Rise ; C25M ; +; SA[1] ; C25M ; 8.098 ; 8.098 ; Rise ; C25M ; +; SA[2] ; C25M ; 8.123 ; 8.123 ; Rise ; C25M ; +; SA[3] ; C25M ; 8.213 ; 8.213 ; Rise ; C25M ; +; SA[4] ; C25M ; 9.176 ; 9.176 ; Rise ; C25M ; +; SA[5] ; C25M ; 8.811 ; 8.811 ; Rise ; C25M ; +; SA[6] ; C25M ; 8.780 ; 8.780 ; Rise ; C25M ; +; SA[7] ; C25M ; 8.738 ; 8.738 ; Rise ; C25M ; +; SA[8] ; C25M ; 8.077 ; 8.077 ; Rise ; C25M ; +; SA[9] ; C25M ; 8.361 ; 8.361 ; Rise ; C25M ; +; SA[10] ; C25M ; 8.470 ; 8.470 ; Rise ; C25M ; +; SA[11] ; C25M ; 8.498 ; 8.498 ; Rise ; C25M ; +; SA[12] ; C25M ; 8.320 ; 8.320 ; Rise ; C25M ; +; SBA[*] ; C25M ; 9.367 ; 9.367 ; Rise ; C25M ; +; SBA[0] ; C25M ; 9.367 ; 9.367 ; Rise ; C25M ; +; SBA[1] ; C25M ; 8.694 ; 8.694 ; Rise ; C25M ; +; SD[*] ; C25M ; 8.867 ; 8.867 ; Rise ; C25M ; +; SD[0] ; C25M ; 8.311 ; 8.311 ; Rise ; C25M ; +; SD[1] ; C25M ; 8.235 ; 8.235 ; Rise ; C25M ; +; SD[2] ; C25M ; 8.376 ; 8.376 ; Rise ; C25M ; +; SD[3] ; C25M ; 8.541 ; 8.541 ; Rise ; C25M ; +; SD[4] ; C25M ; 8.489 ; 8.489 ; Rise ; C25M ; +; SD[5] ; C25M ; 8.493 ; 8.493 ; Rise ; C25M ; +; SD[6] ; C25M ; 8.466 ; 8.466 ; Rise ; C25M ; +; SD[7] ; C25M ; 8.867 ; 8.867 ; Rise ; C25M ; +; nCAS ; C25M ; 6.924 ; 6.924 ; Rise ; C25M ; +; nFCS ; C25M ; 8.134 ; 8.134 ; Rise ; C25M ; +; nRAS ; C25M ; 6.944 ; 6.944 ; Rise ; C25M ; +; nRCS ; C25M ; 8.339 ; 8.339 ; Rise ; C25M ; +; nRESout ; C25M ; 8.235 ; 8.235 ; Rise ; C25M ; +; nSWE ; C25M ; 6.923 ; 6.923 ; Rise ; C25M ; +; RDdir ; PHI0 ; 9.322 ; 9.322 ; Rise ; PHI0 ; +; RDdir ; PHI0 ; 9.322 ; 9.322 ; Fall ; PHI0 ; +-----------+------------+--------+--------+------------+-----------------+ -+-------------------------------------------------------------------------+ -; Minimum Clock to Output Times ; -+-----------+------------+--------+--------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-----------+------------+--------+--------+------------+-----------------+ -; DQMH ; C25M ; 8.822 ; 8.822 ; Rise ; C25M ; -; DQML ; C25M ; 11.807 ; 11.807 ; Rise ; C25M ; -; FCK ; C25M ; 8.749 ; 8.749 ; Rise ; C25M ; -; MOSI ; C25M ; 8.378 ; 8.378 ; Rise ; C25M ; -; RCKE ; C25M ; 9.898 ; 9.898 ; Rise ; C25M ; -; RD[*] ; C25M ; 8.702 ; 8.702 ; Rise ; C25M ; -; RD[0] ; C25M ; 10.058 ; 10.058 ; Rise ; C25M ; -; RD[1] ; C25M ; 8.785 ; 8.785 ; Rise ; C25M ; -; RD[2] ; C25M ; 9.255 ; 9.255 ; Rise ; C25M ; -; RD[3] ; C25M ; 9.249 ; 9.249 ; Rise ; C25M ; -; RD[4] ; C25M ; 8.834 ; 8.834 ; Rise ; C25M ; -; RD[5] ; C25M ; 9.259 ; 9.259 ; Rise ; C25M ; -; RD[6] ; C25M ; 8.783 ; 8.783 ; Rise ; C25M ; -; RD[7] ; C25M ; 8.702 ; 8.702 ; Rise ; C25M ; -; RDdir ; C25M ; 11.471 ; 11.471 ; Rise ; C25M ; -; SA[*] ; C25M ; 7.589 ; 7.589 ; Rise ; C25M ; -; SA[0] ; C25M ; 8.838 ; 8.838 ; Rise ; C25M ; -; SA[1] ; C25M ; 10.609 ; 10.609 ; Rise ; C25M ; -; SA[2] ; C25M ; 9.346 ; 9.346 ; Rise ; C25M ; -; SA[3] ; C25M ; 8.149 ; 8.149 ; Rise ; C25M ; -; SA[4] ; C25M ; 8.023 ; 8.023 ; Rise ; C25M ; -; SA[5] ; C25M ; 8.225 ; 8.225 ; Rise ; C25M ; -; SA[6] ; C25M ; 8.559 ; 8.559 ; Rise ; C25M ; -; SA[7] ; C25M ; 8.483 ; 8.483 ; Rise ; C25M ; -; SA[8] ; C25M ; 7.589 ; 7.589 ; Rise ; C25M ; -; SA[9] ; C25M ; 8.230 ; 8.230 ; Rise ; C25M ; -; SA[10] ; C25M ; 8.766 ; 8.766 ; Rise ; C25M ; -; SA[11] ; C25M ; 8.394 ; 8.394 ; Rise ; C25M ; -; SA[12] ; C25M ; 8.338 ; 8.338 ; Rise ; C25M ; -; SBA[*] ; C25M ; 8.474 ; 8.474 ; Rise ; C25M ; -; SBA[0] ; C25M ; 8.683 ; 8.683 ; Rise ; C25M ; -; SBA[1] ; C25M ; 8.474 ; 8.474 ; Rise ; C25M ; -; SD[*] ; C25M ; 6.942 ; 6.942 ; Rise ; C25M ; -; SD[0] ; C25M ; 8.728 ; 8.728 ; Rise ; C25M ; -; SD[1] ; C25M ; 8.231 ; 8.231 ; Rise ; C25M ; -; SD[2] ; C25M ; 8.242 ; 8.242 ; Rise ; C25M ; -; SD[3] ; C25M ; 8.828 ; 8.828 ; Rise ; C25M ; -; SD[4] ; C25M ; 10.171 ; 10.171 ; Rise ; C25M ; -; SD[5] ; C25M ; 8.719 ; 8.719 ; Rise ; C25M ; -; SD[6] ; C25M ; 6.942 ; 6.942 ; Rise ; C25M ; -; SD[7] ; C25M ; 8.113 ; 8.113 ; Rise ; C25M ; -; nCAS ; C25M ; 8.009 ; 8.009 ; Rise ; C25M ; -; nFCS ; C25M ; 9.004 ; 9.004 ; Rise ; C25M ; -; nRAS ; C25M ; 8.417 ; 8.417 ; Rise ; C25M ; -; nRCS ; C25M ; 11.091 ; 11.091 ; Rise ; C25M ; -; nRESout ; C25M ; 9.056 ; 9.056 ; Rise ; C25M ; -; nSWE ; C25M ; 8.685 ; 8.685 ; Rise ; C25M ; -; RDdir ; PHI0 ; 12.126 ; 12.126 ; Rise ; PHI0 ; -; RDdir ; PHI0 ; 12.126 ; 12.126 ; Fall ; PHI0 ; -+-----------+------------+--------+--------+------------+-----------------+ ++-----------------------------------------------------------------------+ +; Minimum Clock to Output Times ; ++-----------+------------+-------+-------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+-------+-------+------------+-----------------+ +; DQMH ; C25M ; 9.467 ; 9.467 ; Rise ; C25M ; +; DQML ; C25M ; 8.761 ; 8.761 ; Rise ; C25M ; +; FCK ; C25M ; 8.921 ; 8.921 ; Rise ; C25M ; +; MOSI ; C25M ; 7.606 ; 7.606 ; Rise ; C25M ; +; RCKE ; C25M ; 8.729 ; 8.729 ; Rise ; C25M ; +; RD[*] ; C25M ; 6.944 ; 6.944 ; Rise ; C25M ; +; RD[0] ; C25M ; 8.674 ; 8.674 ; Rise ; C25M ; +; RD[1] ; C25M ; 6.959 ; 6.959 ; Rise ; C25M ; +; RD[2] ; C25M ; 6.944 ; 6.944 ; Rise ; C25M ; +; RD[3] ; C25M ; 8.301 ; 8.301 ; Rise ; C25M ; +; RD[4] ; C25M ; 8.292 ; 8.292 ; Rise ; C25M ; +; RD[5] ; C25M ; 8.457 ; 8.457 ; Rise ; C25M ; +; RD[6] ; C25M ; 9.082 ; 9.082 ; Rise ; C25M ; +; RD[7] ; C25M ; 8.143 ; 8.143 ; Rise ; C25M ; +; RDdir ; C25M ; 8.943 ; 8.943 ; Rise ; C25M ; +; SA[*] ; C25M ; 8.077 ; 8.077 ; Rise ; C25M ; +; SA[0] ; C25M ; 8.347 ; 8.347 ; Rise ; C25M ; +; SA[1] ; C25M ; 8.098 ; 8.098 ; Rise ; C25M ; +; SA[2] ; C25M ; 8.123 ; 8.123 ; Rise ; C25M ; +; SA[3] ; C25M ; 8.213 ; 8.213 ; Rise ; C25M ; +; SA[4] ; C25M ; 9.176 ; 9.176 ; Rise ; C25M ; +; SA[5] ; C25M ; 8.811 ; 8.811 ; Rise ; C25M ; +; SA[6] ; C25M ; 8.780 ; 8.780 ; Rise ; C25M ; +; SA[7] ; C25M ; 8.738 ; 8.738 ; Rise ; C25M ; +; SA[8] ; C25M ; 8.077 ; 8.077 ; Rise ; C25M ; +; SA[9] ; C25M ; 8.361 ; 8.361 ; Rise ; C25M ; +; SA[10] ; C25M ; 8.470 ; 8.470 ; Rise ; C25M ; +; SA[11] ; C25M ; 8.498 ; 8.498 ; Rise ; C25M ; +; SA[12] ; C25M ; 8.320 ; 8.320 ; Rise ; C25M ; +; SBA[*] ; C25M ; 8.694 ; 8.694 ; Rise ; C25M ; +; SBA[0] ; C25M ; 9.367 ; 9.367 ; Rise ; C25M ; +; SBA[1] ; C25M ; 8.694 ; 8.694 ; Rise ; C25M ; +; SD[*] ; C25M ; 8.235 ; 8.235 ; Rise ; C25M ; +; SD[0] ; C25M ; 8.311 ; 8.311 ; Rise ; C25M ; +; SD[1] ; C25M ; 8.235 ; 8.235 ; Rise ; C25M ; +; SD[2] ; C25M ; 8.376 ; 8.376 ; Rise ; C25M ; +; SD[3] ; C25M ; 8.541 ; 8.541 ; Rise ; C25M ; +; SD[4] ; C25M ; 8.489 ; 8.489 ; Rise ; C25M ; +; SD[5] ; C25M ; 8.493 ; 8.493 ; Rise ; C25M ; +; SD[6] ; C25M ; 8.466 ; 8.466 ; Rise ; C25M ; +; SD[7] ; C25M ; 8.867 ; 8.867 ; Rise ; C25M ; +; nCAS ; C25M ; 6.924 ; 6.924 ; Rise ; C25M ; +; nFCS ; C25M ; 8.134 ; 8.134 ; Rise ; C25M ; +; nRAS ; C25M ; 6.944 ; 6.944 ; Rise ; C25M ; +; nRCS ; C25M ; 8.339 ; 8.339 ; Rise ; C25M ; +; nRESout ; C25M ; 8.235 ; 8.235 ; Rise ; C25M ; +; nSWE ; C25M ; 6.923 ; 6.923 ; Rise ; C25M ; +; RDdir ; PHI0 ; 9.322 ; 9.322 ; Rise ; PHI0 ; +; RDdir ; PHI0 ; 9.322 ; 9.322 ; Fall ; PHI0 ; ++-----------+------------+-------+-------+------------+-----------------+ +------------------------------------------------------+ @@ -866,44 +846,44 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +------------+-------------+--------+----+----+--------+ ; Input Port ; Output Port ; RR ; RF ; FR ; FF ; +------------+-------------+--------+----+----+--------+ -; DMAin ; DMAout ; 8.209 ; ; ; 8.209 ; -; INTin ; INTout ; 8.936 ; ; ; 8.936 ; -; nDEVSEL ; RD[0] ; 12.492 ; ; ; 12.492 ; -; nDEVSEL ; RD[1] ; 12.492 ; ; ; 12.492 ; -; nDEVSEL ; RD[2] ; 12.492 ; ; ; 12.492 ; -; nDEVSEL ; RD[3] ; 12.492 ; ; ; 12.492 ; -; nDEVSEL ; RD[4] ; 12.492 ; ; ; 12.492 ; -; nDEVSEL ; RD[5] ; 12.492 ; ; ; 12.492 ; -; nDEVSEL ; RD[6] ; 12.907 ; ; ; 12.907 ; -; nDEVSEL ; RD[7] ; 13.680 ; ; ; 13.680 ; -; nDEVSEL ; RDdir ; 15.627 ; ; ; 15.627 ; -; nIOSEL ; RD[0] ; 12.748 ; ; ; 12.748 ; -; nIOSEL ; RD[1] ; 12.748 ; ; ; 12.748 ; -; nIOSEL ; RD[2] ; 12.748 ; ; ; 12.748 ; -; nIOSEL ; RD[3] ; 12.748 ; ; ; 12.748 ; -; nIOSEL ; RD[4] ; 12.748 ; ; ; 12.748 ; -; nIOSEL ; RD[5] ; 12.748 ; ; ; 12.748 ; -; nIOSEL ; RD[6] ; 13.163 ; ; ; 13.163 ; -; nIOSEL ; RD[7] ; 13.936 ; ; ; 13.936 ; -; nIOSEL ; RDdir ; 15.883 ; ; ; 15.883 ; -; nIOSTRB ; RD[0] ; 12.388 ; ; ; 12.388 ; -; nIOSTRB ; RD[1] ; 12.388 ; ; ; 12.388 ; -; nIOSTRB ; RD[2] ; 12.388 ; ; ; 12.388 ; -; nIOSTRB ; RD[3] ; 12.388 ; ; ; 12.388 ; -; nIOSTRB ; RD[4] ; 12.388 ; ; ; 12.388 ; -; nIOSTRB ; RD[5] ; 12.388 ; ; ; 12.388 ; -; nIOSTRB ; RD[6] ; 12.803 ; ; ; 12.803 ; -; nIOSTRB ; RD[7] ; 13.576 ; ; ; 13.576 ; -; nIOSTRB ; RDdir ; 15.523 ; ; ; 15.523 ; -; nWE ; RD[0] ; 11.375 ; ; ; 11.375 ; -; nWE ; RD[1] ; 11.375 ; ; ; 11.375 ; -; nWE ; RD[2] ; 11.375 ; ; ; 11.375 ; -; nWE ; RD[3] ; 11.375 ; ; ; 11.375 ; -; nWE ; RD[4] ; 11.375 ; ; ; 11.375 ; -; nWE ; RD[5] ; 11.375 ; ; ; 11.375 ; -; nWE ; RD[6] ; 11.790 ; ; ; 11.790 ; -; nWE ; RD[7] ; 12.563 ; ; ; 12.563 ; -; nWE ; RDdir ; 14.510 ; ; ; 14.510 ; +; DMAin ; DMAout ; 8.256 ; ; ; 8.256 ; +; INTin ; INTout ; 8.887 ; ; ; 8.887 ; +; nDEVSEL ; RD[0] ; 16.962 ; ; ; 16.962 ; +; nDEVSEL ; RD[1] ; 16.962 ; ; ; 16.962 ; +; nDEVSEL ; RD[2] ; 16.962 ; ; ; 16.962 ; +; nDEVSEL ; RD[3] ; 17.492 ; ; ; 17.492 ; +; nDEVSEL ; RD[4] ; 17.492 ; ; ; 17.492 ; +; nDEVSEL ; RD[5] ; 17.492 ; ; ; 17.492 ; +; nDEVSEL ; RD[6] ; 17.492 ; ; ; 17.492 ; +; nDEVSEL ; RD[7] ; 12.941 ; ; ; 12.941 ; +; nDEVSEL ; RDdir ; 13.427 ; ; ; 13.427 ; +; nIOSEL ; RD[0] ; 16.278 ; ; ; 16.278 ; +; nIOSEL ; RD[1] ; 16.278 ; ; ; 16.278 ; +; nIOSEL ; RD[2] ; 16.278 ; ; ; 16.278 ; +; nIOSEL ; RD[3] ; 16.808 ; ; ; 16.808 ; +; nIOSEL ; RD[4] ; 16.808 ; ; ; 16.808 ; +; nIOSEL ; RD[5] ; 16.808 ; ; ; 16.808 ; +; nIOSEL ; RD[6] ; 16.808 ; ; ; 16.808 ; +; nIOSEL ; RD[7] ; 12.257 ; ; ; 12.257 ; +; nIOSEL ; RDdir ; 12.743 ; ; ; 12.743 ; +; nIOSTRB ; RD[0] ; 16.815 ; ; ; 16.815 ; +; nIOSTRB ; RD[1] ; 16.815 ; ; ; 16.815 ; +; nIOSTRB ; RD[2] ; 16.815 ; ; ; 16.815 ; +; nIOSTRB ; RD[3] ; 17.345 ; ; ; 17.345 ; +; nIOSTRB ; RD[4] ; 17.345 ; ; ; 17.345 ; +; nIOSTRB ; RD[5] ; 17.345 ; ; ; 17.345 ; +; nIOSTRB ; RD[6] ; 17.345 ; ; ; 17.345 ; +; nIOSTRB ; RD[7] ; 12.794 ; ; ; 12.794 ; +; nIOSTRB ; RDdir ; 13.280 ; ; ; 13.280 ; +; nWE ; RD[0] ; 14.902 ; ; ; 14.902 ; +; nWE ; RD[1] ; 14.902 ; ; ; 14.902 ; +; nWE ; RD[2] ; 14.902 ; ; ; 14.902 ; +; nWE ; RD[3] ; 15.432 ; ; ; 15.432 ; +; nWE ; RD[4] ; 15.432 ; ; ; 15.432 ; +; nWE ; RD[5] ; 15.432 ; ; ; 15.432 ; +; nWE ; RD[6] ; 15.432 ; ; ; 15.432 ; +; nWE ; RD[7] ; 10.881 ; ; ; 10.881 ; +; nWE ; RDdir ; 11.367 ; ; ; 11.367 ; +------------+-------------+--------+----+----+--------+ @@ -912,44 +892,44 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +------------+-------------+--------+----+----+--------+ ; Input Port ; Output Port ; RR ; RF ; FR ; FF ; +------------+-------------+--------+----+----+--------+ -; DMAin ; DMAout ; 8.209 ; ; ; 8.209 ; -; INTin ; INTout ; 8.936 ; ; ; 8.936 ; -; nDEVSEL ; RD[0] ; 12.492 ; ; ; 12.492 ; -; nDEVSEL ; RD[1] ; 12.492 ; ; ; 12.492 ; -; nDEVSEL ; RD[2] ; 12.492 ; ; ; 12.492 ; -; nDEVSEL ; RD[3] ; 12.492 ; ; ; 12.492 ; -; nDEVSEL ; RD[4] ; 12.492 ; ; ; 12.492 ; -; nDEVSEL ; RD[5] ; 12.492 ; ; ; 12.492 ; -; nDEVSEL ; RD[6] ; 12.907 ; ; ; 12.907 ; -; nDEVSEL ; RD[7] ; 13.680 ; ; ; 13.680 ; -; nDEVSEL ; RDdir ; 15.627 ; ; ; 15.627 ; -; nIOSEL ; RD[0] ; 12.748 ; ; ; 12.748 ; -; nIOSEL ; RD[1] ; 12.748 ; ; ; 12.748 ; -; nIOSEL ; RD[2] ; 12.748 ; ; ; 12.748 ; -; nIOSEL ; RD[3] ; 12.748 ; ; ; 12.748 ; -; nIOSEL ; RD[4] ; 12.748 ; ; ; 12.748 ; -; nIOSEL ; RD[5] ; 12.748 ; ; ; 12.748 ; -; nIOSEL ; RD[6] ; 13.163 ; ; ; 13.163 ; -; nIOSEL ; RD[7] ; 13.936 ; ; ; 13.936 ; -; nIOSEL ; RDdir ; 15.883 ; ; ; 15.883 ; -; nIOSTRB ; RD[0] ; 12.388 ; ; ; 12.388 ; -; nIOSTRB ; RD[1] ; 12.388 ; ; ; 12.388 ; -; nIOSTRB ; RD[2] ; 12.388 ; ; ; 12.388 ; -; nIOSTRB ; RD[3] ; 12.388 ; ; ; 12.388 ; -; nIOSTRB ; RD[4] ; 12.388 ; ; ; 12.388 ; -; nIOSTRB ; RD[5] ; 12.388 ; ; ; 12.388 ; -; nIOSTRB ; RD[6] ; 12.803 ; ; ; 12.803 ; -; nIOSTRB ; RD[7] ; 13.576 ; ; ; 13.576 ; -; nIOSTRB ; RDdir ; 15.523 ; ; ; 15.523 ; -; nWE ; RD[0] ; 11.375 ; ; ; 11.375 ; -; nWE ; RD[1] ; 11.375 ; ; ; 11.375 ; -; nWE ; RD[2] ; 11.375 ; ; ; 11.375 ; -; nWE ; RD[3] ; 11.375 ; ; ; 11.375 ; -; nWE ; RD[4] ; 11.375 ; ; ; 11.375 ; -; nWE ; RD[5] ; 11.375 ; ; ; 11.375 ; -; nWE ; RD[6] ; 11.790 ; ; ; 11.790 ; -; nWE ; RD[7] ; 12.563 ; ; ; 12.563 ; -; nWE ; RDdir ; 14.510 ; ; ; 14.510 ; +; DMAin ; DMAout ; 8.256 ; ; ; 8.256 ; +; INTin ; INTout ; 8.887 ; ; ; 8.887 ; +; nDEVSEL ; RD[0] ; 16.962 ; ; ; 16.962 ; +; nDEVSEL ; RD[1] ; 16.962 ; ; ; 16.962 ; +; nDEVSEL ; RD[2] ; 16.962 ; ; ; 16.962 ; +; nDEVSEL ; RD[3] ; 17.492 ; ; ; 17.492 ; +; nDEVSEL ; RD[4] ; 17.492 ; ; ; 17.492 ; +; nDEVSEL ; RD[5] ; 17.492 ; ; ; 17.492 ; +; nDEVSEL ; RD[6] ; 17.492 ; ; ; 17.492 ; +; nDEVSEL ; RD[7] ; 12.941 ; ; ; 12.941 ; +; nDEVSEL ; RDdir ; 13.427 ; ; ; 13.427 ; +; nIOSEL ; RD[0] ; 16.278 ; ; ; 16.278 ; +; nIOSEL ; RD[1] ; 16.278 ; ; ; 16.278 ; +; nIOSEL ; RD[2] ; 16.278 ; ; ; 16.278 ; +; nIOSEL ; RD[3] ; 16.808 ; ; ; 16.808 ; +; nIOSEL ; RD[4] ; 16.808 ; ; ; 16.808 ; +; nIOSEL ; RD[5] ; 16.808 ; ; ; 16.808 ; +; nIOSEL ; RD[6] ; 16.808 ; ; ; 16.808 ; +; nIOSEL ; RD[7] ; 12.257 ; ; ; 12.257 ; +; nIOSEL ; RDdir ; 12.743 ; ; ; 12.743 ; +; nIOSTRB ; RD[0] ; 16.815 ; ; ; 16.815 ; +; nIOSTRB ; RD[1] ; 16.815 ; ; ; 16.815 ; +; nIOSTRB ; RD[2] ; 16.815 ; ; ; 16.815 ; +; nIOSTRB ; RD[3] ; 17.345 ; ; ; 17.345 ; +; nIOSTRB ; RD[4] ; 17.345 ; ; ; 17.345 ; +; nIOSTRB ; RD[5] ; 17.345 ; ; ; 17.345 ; +; nIOSTRB ; RD[6] ; 17.345 ; ; ; 17.345 ; +; nIOSTRB ; RD[7] ; 12.794 ; ; ; 12.794 ; +; nIOSTRB ; RDdir ; 13.280 ; ; ; 13.280 ; +; nWE ; RD[0] ; 14.902 ; ; ; 14.902 ; +; nWE ; RD[1] ; 14.902 ; ; ; 14.902 ; +; nWE ; RD[2] ; 14.902 ; ; ; 14.902 ; +; nWE ; RD[3] ; 15.432 ; ; ; 15.432 ; +; nWE ; RD[4] ; 15.432 ; ; ; 15.432 ; +; nWE ; RD[5] ; 15.432 ; ; ; 15.432 ; +; nWE ; RD[6] ; 15.432 ; ; ; 15.432 ; +; nWE ; RD[7] ; 10.881 ; ; ; 10.881 ; +; nWE ; RDdir ; 11.367 ; ; ; 11.367 ; +------------+-------------+--------+----+----+--------+ @@ -958,45 +938,45 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-----------+------------+--------+------+------------+-----------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+--------+------+------------+-----------------+ -; FCK ; C25M ; 7.883 ; ; Rise ; C25M ; -; MOSI ; C25M ; 7.607 ; ; Rise ; C25M ; -; RD[*] ; C25M ; 13.735 ; ; Rise ; C25M ; -; RD[0] ; C25M ; 13.735 ; ; Rise ; C25M ; -; RD[1] ; C25M ; 13.735 ; ; Rise ; C25M ; -; RD[2] ; C25M ; 13.735 ; ; Rise ; C25M ; -; RD[3] ; C25M ; 13.735 ; ; Rise ; C25M ; -; RD[4] ; C25M ; 13.735 ; ; Rise ; C25M ; -; RD[5] ; C25M ; 13.735 ; ; Rise ; C25M ; -; RD[6] ; C25M ; 14.150 ; ; Rise ; C25M ; -; RD[7] ; C25M ; 14.923 ; ; Rise ; C25M ; -; SD[*] ; C25M ; 7.005 ; ; Rise ; C25M ; -; SD[0] ; C25M ; 7.501 ; ; Rise ; C25M ; -; SD[1] ; C25M ; 7.005 ; ; Rise ; C25M ; -; SD[2] ; C25M ; 7.091 ; ; Rise ; C25M ; -; SD[3] ; C25M ; 7.091 ; ; Rise ; C25M ; -; SD[4] ; C25M ; 7.501 ; ; Rise ; C25M ; -; SD[5] ; C25M ; 7.091 ; ; Rise ; C25M ; -; SD[6] ; C25M ; 7.091 ; ; Rise ; C25M ; -; SD[7] ; C25M ; 7.091 ; ; Rise ; C25M ; -; nFCS ; C25M ; 7.901 ; ; Rise ; C25M ; -; RD[*] ; PHI0 ; 8.991 ; ; Rise ; PHI0 ; -; RD[0] ; PHI0 ; 8.991 ; ; Rise ; PHI0 ; -; RD[1] ; PHI0 ; 8.991 ; ; Rise ; PHI0 ; -; RD[2] ; PHI0 ; 8.991 ; ; Rise ; PHI0 ; -; RD[3] ; PHI0 ; 8.991 ; ; Rise ; PHI0 ; -; RD[4] ; PHI0 ; 8.991 ; ; Rise ; PHI0 ; -; RD[5] ; PHI0 ; 8.991 ; ; Rise ; PHI0 ; -; RD[6] ; PHI0 ; 9.406 ; ; Rise ; PHI0 ; -; RD[7] ; PHI0 ; 10.179 ; ; Rise ; PHI0 ; -; RD[*] ; PHI0 ; 8.991 ; ; Fall ; PHI0 ; -; RD[0] ; PHI0 ; 8.991 ; ; Fall ; PHI0 ; -; RD[1] ; PHI0 ; 8.991 ; ; Fall ; PHI0 ; -; RD[2] ; PHI0 ; 8.991 ; ; Fall ; PHI0 ; -; RD[3] ; PHI0 ; 8.991 ; ; Fall ; PHI0 ; -; RD[4] ; PHI0 ; 8.991 ; ; Fall ; PHI0 ; -; RD[5] ; PHI0 ; 8.991 ; ; Fall ; PHI0 ; -; RD[6] ; PHI0 ; 9.406 ; ; Fall ; PHI0 ; -; RD[7] ; PHI0 ; 10.179 ; ; Fall ; PHI0 ; +; FCK ; C25M ; 6.468 ; ; Rise ; C25M ; +; MOSI ; C25M ; 8.578 ; ; Rise ; C25M ; +; RD[*] ; C25M ; 11.335 ; ; Rise ; C25M ; +; RD[0] ; C25M ; 15.356 ; ; Rise ; C25M ; +; RD[1] ; C25M ; 15.356 ; ; Rise ; C25M ; +; RD[2] ; C25M ; 15.356 ; ; Rise ; C25M ; +; RD[3] ; C25M ; 15.886 ; ; Rise ; C25M ; +; RD[4] ; C25M ; 15.886 ; ; Rise ; C25M ; +; RD[5] ; C25M ; 15.886 ; ; Rise ; C25M ; +; RD[6] ; C25M ; 15.886 ; ; Rise ; C25M ; +; RD[7] ; C25M ; 11.335 ; ; Rise ; C25M ; +; SD[*] ; C25M ; 6.976 ; ; Rise ; C25M ; +; SD[0] ; C25M ; 7.063 ; ; Rise ; C25M ; +; SD[1] ; C25M ; 6.976 ; ; Rise ; C25M ; +; SD[2] ; C25M ; 7.441 ; ; Rise ; C25M ; +; SD[3] ; C25M ; 7.441 ; ; Rise ; C25M ; +; SD[4] ; C25M ; 7.063 ; ; Rise ; C25M ; +; SD[5] ; C25M ; 7.441 ; ; Rise ; C25M ; +; SD[6] ; C25M ; 7.441 ; ; Rise ; C25M ; +; SD[7] ; C25M ; 7.441 ; ; Rise ; C25M ; +; nFCS ; C25M ; 7.200 ; ; Rise ; C25M ; +; RD[*] ; PHI0 ; 8.836 ; ; Rise ; PHI0 ; +; RD[0] ; PHI0 ; 12.857 ; ; Rise ; PHI0 ; +; RD[1] ; PHI0 ; 12.857 ; ; Rise ; PHI0 ; +; RD[2] ; PHI0 ; 12.857 ; ; Rise ; PHI0 ; +; RD[3] ; PHI0 ; 13.387 ; ; Rise ; PHI0 ; +; RD[4] ; PHI0 ; 13.387 ; ; Rise ; PHI0 ; +; RD[5] ; PHI0 ; 13.387 ; ; Rise ; PHI0 ; +; RD[6] ; PHI0 ; 13.387 ; ; Rise ; PHI0 ; +; RD[7] ; PHI0 ; 8.836 ; ; Rise ; PHI0 ; +; RD[*] ; PHI0 ; 8.836 ; ; Fall ; PHI0 ; +; RD[0] ; PHI0 ; 12.857 ; ; Fall ; PHI0 ; +; RD[1] ; PHI0 ; 12.857 ; ; Fall ; PHI0 ; +; RD[2] ; PHI0 ; 12.857 ; ; Fall ; PHI0 ; +; RD[3] ; PHI0 ; 13.387 ; ; Fall ; PHI0 ; +; RD[4] ; PHI0 ; 13.387 ; ; Fall ; PHI0 ; +; RD[5] ; PHI0 ; 13.387 ; ; Fall ; PHI0 ; +; RD[6] ; PHI0 ; 13.387 ; ; Fall ; PHI0 ; +; RD[7] ; PHI0 ; 8.836 ; ; Fall ; PHI0 ; +-----------+------------+--------+------+------------+-----------------+ @@ -1005,45 +985,45 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-----------+------------+--------+------+------------+-----------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+--------+------+------------+-----------------+ -; FCK ; C25M ; 7.883 ; ; Rise ; C25M ; -; MOSI ; C25M ; 7.607 ; ; Rise ; C25M ; -; RD[*] ; C25M ; 8.336 ; ; Rise ; C25M ; -; RD[0] ; C25M ; 8.336 ; ; Rise ; C25M ; -; RD[1] ; C25M ; 8.336 ; ; Rise ; C25M ; -; RD[2] ; C25M ; 8.336 ; ; Rise ; C25M ; -; RD[3] ; C25M ; 8.336 ; ; Rise ; C25M ; -; RD[4] ; C25M ; 8.336 ; ; Rise ; C25M ; -; RD[5] ; C25M ; 8.336 ; ; Rise ; C25M ; -; RD[6] ; C25M ; 8.751 ; ; Rise ; C25M ; -; RD[7] ; C25M ; 9.524 ; ; Rise ; C25M ; -; SD[*] ; C25M ; 7.005 ; ; Rise ; C25M ; -; SD[0] ; C25M ; 7.501 ; ; Rise ; C25M ; -; SD[1] ; C25M ; 7.005 ; ; Rise ; C25M ; -; SD[2] ; C25M ; 7.091 ; ; Rise ; C25M ; -; SD[3] ; C25M ; 7.091 ; ; Rise ; C25M ; -; SD[4] ; C25M ; 7.501 ; ; Rise ; C25M ; -; SD[5] ; C25M ; 7.091 ; ; Rise ; C25M ; -; SD[6] ; C25M ; 7.091 ; ; Rise ; C25M ; -; SD[7] ; C25M ; 7.091 ; ; Rise ; C25M ; -; nFCS ; C25M ; 7.901 ; ; Rise ; C25M ; -; RD[*] ; PHI0 ; 8.991 ; ; Rise ; PHI0 ; -; RD[0] ; PHI0 ; 8.991 ; ; Rise ; PHI0 ; -; RD[1] ; PHI0 ; 8.991 ; ; Rise ; PHI0 ; -; RD[2] ; PHI0 ; 8.991 ; ; Rise ; PHI0 ; -; RD[3] ; PHI0 ; 8.991 ; ; Rise ; PHI0 ; -; RD[4] ; PHI0 ; 8.991 ; ; Rise ; PHI0 ; -; RD[5] ; PHI0 ; 8.991 ; ; Rise ; PHI0 ; -; RD[6] ; PHI0 ; 9.406 ; ; Rise ; PHI0 ; -; RD[7] ; PHI0 ; 10.179 ; ; Rise ; PHI0 ; -; RD[*] ; PHI0 ; 8.991 ; ; Fall ; PHI0 ; -; RD[0] ; PHI0 ; 8.991 ; ; Fall ; PHI0 ; -; RD[1] ; PHI0 ; 8.991 ; ; Fall ; PHI0 ; -; RD[2] ; PHI0 ; 8.991 ; ; Fall ; PHI0 ; -; RD[3] ; PHI0 ; 8.991 ; ; Fall ; PHI0 ; -; RD[4] ; PHI0 ; 8.991 ; ; Fall ; PHI0 ; -; RD[5] ; PHI0 ; 8.991 ; ; Fall ; PHI0 ; -; RD[6] ; PHI0 ; 9.406 ; ; Fall ; PHI0 ; -; RD[7] ; PHI0 ; 10.179 ; ; Fall ; PHI0 ; +; FCK ; C25M ; 6.468 ; ; Rise ; C25M ; +; MOSI ; C25M ; 8.578 ; ; Rise ; C25M ; +; RD[*] ; C25M ; 8.457 ; ; Rise ; C25M ; +; RD[0] ; C25M ; 12.478 ; ; Rise ; C25M ; +; RD[1] ; C25M ; 12.478 ; ; Rise ; C25M ; +; RD[2] ; C25M ; 12.478 ; ; Rise ; C25M ; +; RD[3] ; C25M ; 13.008 ; ; Rise ; C25M ; +; RD[4] ; C25M ; 13.008 ; ; Rise ; C25M ; +; RD[5] ; C25M ; 13.008 ; ; Rise ; C25M ; +; RD[6] ; C25M ; 13.008 ; ; Rise ; C25M ; +; RD[7] ; C25M ; 8.457 ; ; Rise ; C25M ; +; SD[*] ; C25M ; 6.976 ; ; Rise ; C25M ; +; SD[0] ; C25M ; 7.063 ; ; Rise ; C25M ; +; SD[1] ; C25M ; 6.976 ; ; Rise ; C25M ; +; SD[2] ; C25M ; 7.441 ; ; Rise ; C25M ; +; SD[3] ; C25M ; 7.441 ; ; Rise ; C25M ; +; SD[4] ; C25M ; 7.063 ; ; Rise ; C25M ; +; SD[5] ; C25M ; 7.441 ; ; Rise ; C25M ; +; SD[6] ; C25M ; 7.441 ; ; Rise ; C25M ; +; SD[7] ; C25M ; 7.441 ; ; Rise ; C25M ; +; nFCS ; C25M ; 7.200 ; ; Rise ; C25M ; +; RD[*] ; PHI0 ; 8.836 ; ; Rise ; PHI0 ; +; RD[0] ; PHI0 ; 12.857 ; ; Rise ; PHI0 ; +; RD[1] ; PHI0 ; 12.857 ; ; Rise ; PHI0 ; +; RD[2] ; PHI0 ; 12.857 ; ; Rise ; PHI0 ; +; RD[3] ; PHI0 ; 13.387 ; ; Rise ; PHI0 ; +; RD[4] ; PHI0 ; 13.387 ; ; Rise ; PHI0 ; +; RD[5] ; PHI0 ; 13.387 ; ; Rise ; PHI0 ; +; RD[6] ; PHI0 ; 13.387 ; ; Rise ; PHI0 ; +; RD[7] ; PHI0 ; 8.836 ; ; Rise ; PHI0 ; +; RD[*] ; PHI0 ; 8.836 ; ; Fall ; PHI0 ; +; RD[0] ; PHI0 ; 12.857 ; ; Fall ; PHI0 ; +; RD[1] ; PHI0 ; 12.857 ; ; Fall ; PHI0 ; +; RD[2] ; PHI0 ; 12.857 ; ; Fall ; PHI0 ; +; RD[3] ; PHI0 ; 13.387 ; ; Fall ; PHI0 ; +; RD[4] ; PHI0 ; 13.387 ; ; Fall ; PHI0 ; +; RD[5] ; PHI0 ; 13.387 ; ; Fall ; PHI0 ; +; RD[6] ; PHI0 ; 13.387 ; ; Fall ; PHI0 ; +; RD[7] ; PHI0 ; 8.836 ; ; Fall ; PHI0 ; +-----------+------------+--------+------+------------+-----------------+ @@ -1052,45 +1032,45 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-----------+------------+-----------+-----------+------------+-----------------+ ; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; +-----------+------------+-----------+-----------+------------+-----------------+ -; FCK ; C25M ; 7.883 ; ; Rise ; C25M ; -; MOSI ; C25M ; 7.607 ; ; Rise ; C25M ; -; RD[*] ; C25M ; 13.735 ; ; Rise ; C25M ; -; RD[0] ; C25M ; 13.735 ; ; Rise ; C25M ; -; RD[1] ; C25M ; 13.735 ; ; Rise ; C25M ; -; RD[2] ; C25M ; 13.735 ; ; Rise ; C25M ; -; RD[3] ; C25M ; 13.735 ; ; Rise ; C25M ; -; RD[4] ; C25M ; 13.735 ; ; Rise ; C25M ; -; RD[5] ; C25M ; 13.735 ; ; Rise ; C25M ; -; RD[6] ; C25M ; 14.150 ; ; Rise ; C25M ; -; RD[7] ; C25M ; 14.923 ; ; Rise ; C25M ; -; SD[*] ; C25M ; 7.005 ; ; Rise ; C25M ; -; SD[0] ; C25M ; 7.501 ; ; Rise ; C25M ; -; SD[1] ; C25M ; 7.005 ; ; Rise ; C25M ; -; SD[2] ; C25M ; 7.091 ; ; Rise ; C25M ; -; SD[3] ; C25M ; 7.091 ; ; Rise ; C25M ; -; SD[4] ; C25M ; 7.501 ; ; Rise ; C25M ; -; SD[5] ; C25M ; 7.091 ; ; Rise ; C25M ; -; SD[6] ; C25M ; 7.091 ; ; Rise ; C25M ; -; SD[7] ; C25M ; 7.091 ; ; Rise ; C25M ; -; nFCS ; C25M ; 7.901 ; ; Rise ; C25M ; -; RD[*] ; PHI0 ; 8.991 ; ; Rise ; PHI0 ; -; RD[0] ; PHI0 ; 8.991 ; ; Rise ; PHI0 ; -; RD[1] ; PHI0 ; 8.991 ; ; Rise ; PHI0 ; -; RD[2] ; PHI0 ; 8.991 ; ; Rise ; PHI0 ; -; RD[3] ; PHI0 ; 8.991 ; ; Rise ; PHI0 ; -; RD[4] ; PHI0 ; 8.991 ; ; Rise ; PHI0 ; -; RD[5] ; PHI0 ; 8.991 ; ; Rise ; PHI0 ; -; RD[6] ; PHI0 ; 9.406 ; ; Rise ; PHI0 ; -; RD[7] ; PHI0 ; 10.179 ; ; Rise ; PHI0 ; -; RD[*] ; PHI0 ; 8.991 ; ; Fall ; PHI0 ; -; RD[0] ; PHI0 ; 8.991 ; ; Fall ; PHI0 ; -; RD[1] ; PHI0 ; 8.991 ; ; Fall ; PHI0 ; -; RD[2] ; PHI0 ; 8.991 ; ; Fall ; PHI0 ; -; RD[3] ; PHI0 ; 8.991 ; ; Fall ; PHI0 ; -; RD[4] ; PHI0 ; 8.991 ; ; Fall ; PHI0 ; -; RD[5] ; PHI0 ; 8.991 ; ; Fall ; PHI0 ; -; RD[6] ; PHI0 ; 9.406 ; ; Fall ; PHI0 ; -; RD[7] ; PHI0 ; 10.179 ; ; Fall ; PHI0 ; +; FCK ; C25M ; 6.468 ; ; Rise ; C25M ; +; MOSI ; C25M ; 8.578 ; ; Rise ; C25M ; +; RD[*] ; C25M ; 11.335 ; ; Rise ; C25M ; +; RD[0] ; C25M ; 15.356 ; ; Rise ; C25M ; +; RD[1] ; C25M ; 15.356 ; ; Rise ; C25M ; +; RD[2] ; C25M ; 15.356 ; ; Rise ; C25M ; +; RD[3] ; C25M ; 15.886 ; ; Rise ; C25M ; +; RD[4] ; C25M ; 15.886 ; ; Rise ; C25M ; +; RD[5] ; C25M ; 15.886 ; ; Rise ; C25M ; +; RD[6] ; C25M ; 15.886 ; ; Rise ; C25M ; +; RD[7] ; C25M ; 11.335 ; ; Rise ; C25M ; +; SD[*] ; C25M ; 6.976 ; ; Rise ; C25M ; +; SD[0] ; C25M ; 7.063 ; ; Rise ; C25M ; +; SD[1] ; C25M ; 6.976 ; ; Rise ; C25M ; +; SD[2] ; C25M ; 7.441 ; ; Rise ; C25M ; +; SD[3] ; C25M ; 7.441 ; ; Rise ; C25M ; +; SD[4] ; C25M ; 7.063 ; ; Rise ; C25M ; +; SD[5] ; C25M ; 7.441 ; ; Rise ; C25M ; +; SD[6] ; C25M ; 7.441 ; ; Rise ; C25M ; +; SD[7] ; C25M ; 7.441 ; ; Rise ; C25M ; +; nFCS ; C25M ; 7.200 ; ; Rise ; C25M ; +; RD[*] ; PHI0 ; 8.836 ; ; Rise ; PHI0 ; +; RD[0] ; PHI0 ; 12.857 ; ; Rise ; PHI0 ; +; RD[1] ; PHI0 ; 12.857 ; ; Rise ; PHI0 ; +; RD[2] ; PHI0 ; 12.857 ; ; Rise ; PHI0 ; +; RD[3] ; PHI0 ; 13.387 ; ; Rise ; PHI0 ; +; RD[4] ; PHI0 ; 13.387 ; ; Rise ; PHI0 ; +; RD[5] ; PHI0 ; 13.387 ; ; Rise ; PHI0 ; +; RD[6] ; PHI0 ; 13.387 ; ; Rise ; PHI0 ; +; RD[7] ; PHI0 ; 8.836 ; ; Rise ; PHI0 ; +; RD[*] ; PHI0 ; 8.836 ; ; Fall ; PHI0 ; +; RD[0] ; PHI0 ; 12.857 ; ; Fall ; PHI0 ; +; RD[1] ; PHI0 ; 12.857 ; ; Fall ; PHI0 ; +; RD[2] ; PHI0 ; 12.857 ; ; Fall ; PHI0 ; +; RD[3] ; PHI0 ; 13.387 ; ; Fall ; PHI0 ; +; RD[4] ; PHI0 ; 13.387 ; ; Fall ; PHI0 ; +; RD[5] ; PHI0 ; 13.387 ; ; Fall ; PHI0 ; +; RD[6] ; PHI0 ; 13.387 ; ; Fall ; PHI0 ; +; RD[7] ; PHI0 ; 8.836 ; ; Fall ; PHI0 ; +-----------+------------+-----------+-----------+------------+-----------------+ @@ -1099,45 +1079,45 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-----------+------------+-----------+-----------+------------+-----------------+ ; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; +-----------+------------+-----------+-----------+------------+-----------------+ -; FCK ; C25M ; 7.883 ; ; Rise ; C25M ; -; MOSI ; C25M ; 7.607 ; ; Rise ; C25M ; -; RD[*] ; C25M ; 8.336 ; ; Rise ; C25M ; -; RD[0] ; C25M ; 8.336 ; ; Rise ; C25M ; -; RD[1] ; C25M ; 8.336 ; ; Rise ; C25M ; -; RD[2] ; C25M ; 8.336 ; ; Rise ; C25M ; -; RD[3] ; C25M ; 8.336 ; ; Rise ; C25M ; -; RD[4] ; C25M ; 8.336 ; ; Rise ; C25M ; -; RD[5] ; C25M ; 8.336 ; ; Rise ; C25M ; -; RD[6] ; C25M ; 8.751 ; ; Rise ; C25M ; -; RD[7] ; C25M ; 9.524 ; ; Rise ; C25M ; -; SD[*] ; C25M ; 7.005 ; ; Rise ; C25M ; -; SD[0] ; C25M ; 7.501 ; ; Rise ; C25M ; -; SD[1] ; C25M ; 7.005 ; ; Rise ; C25M ; -; SD[2] ; C25M ; 7.091 ; ; Rise ; C25M ; -; SD[3] ; C25M ; 7.091 ; ; Rise ; C25M ; -; SD[4] ; C25M ; 7.501 ; ; Rise ; C25M ; -; SD[5] ; C25M ; 7.091 ; ; Rise ; C25M ; -; SD[6] ; C25M ; 7.091 ; ; Rise ; C25M ; -; SD[7] ; C25M ; 7.091 ; ; Rise ; C25M ; -; nFCS ; C25M ; 7.901 ; ; Rise ; C25M ; -; RD[*] ; PHI0 ; 8.991 ; ; Rise ; PHI0 ; -; RD[0] ; PHI0 ; 8.991 ; ; Rise ; PHI0 ; -; RD[1] ; PHI0 ; 8.991 ; ; Rise ; PHI0 ; -; RD[2] ; PHI0 ; 8.991 ; ; Rise ; PHI0 ; -; RD[3] ; PHI0 ; 8.991 ; ; Rise ; PHI0 ; -; RD[4] ; PHI0 ; 8.991 ; ; Rise ; PHI0 ; -; RD[5] ; PHI0 ; 8.991 ; ; Rise ; PHI0 ; -; RD[6] ; PHI0 ; 9.406 ; ; Rise ; PHI0 ; -; RD[7] ; PHI0 ; 10.179 ; ; Rise ; PHI0 ; -; RD[*] ; PHI0 ; 8.991 ; ; Fall ; PHI0 ; -; RD[0] ; PHI0 ; 8.991 ; ; Fall ; PHI0 ; -; RD[1] ; PHI0 ; 8.991 ; ; Fall ; PHI0 ; -; RD[2] ; PHI0 ; 8.991 ; ; Fall ; PHI0 ; -; RD[3] ; PHI0 ; 8.991 ; ; Fall ; PHI0 ; -; RD[4] ; PHI0 ; 8.991 ; ; Fall ; PHI0 ; -; RD[5] ; PHI0 ; 8.991 ; ; Fall ; PHI0 ; -; RD[6] ; PHI0 ; 9.406 ; ; Fall ; PHI0 ; -; RD[7] ; PHI0 ; 10.179 ; ; Fall ; PHI0 ; +; FCK ; C25M ; 6.468 ; ; Rise ; C25M ; +; MOSI ; C25M ; 8.578 ; ; Rise ; C25M ; +; RD[*] ; C25M ; 8.457 ; ; Rise ; C25M ; +; RD[0] ; C25M ; 12.478 ; ; Rise ; C25M ; +; RD[1] ; C25M ; 12.478 ; ; Rise ; C25M ; +; RD[2] ; C25M ; 12.478 ; ; Rise ; C25M ; +; RD[3] ; C25M ; 13.008 ; ; Rise ; C25M ; +; RD[4] ; C25M ; 13.008 ; ; Rise ; C25M ; +; RD[5] ; C25M ; 13.008 ; ; Rise ; C25M ; +; RD[6] ; C25M ; 13.008 ; ; Rise ; C25M ; +; RD[7] ; C25M ; 8.457 ; ; Rise ; C25M ; +; SD[*] ; C25M ; 6.976 ; ; Rise ; C25M ; +; SD[0] ; C25M ; 7.063 ; ; Rise ; C25M ; +; SD[1] ; C25M ; 6.976 ; ; Rise ; C25M ; +; SD[2] ; C25M ; 7.441 ; ; Rise ; C25M ; +; SD[3] ; C25M ; 7.441 ; ; Rise ; C25M ; +; SD[4] ; C25M ; 7.063 ; ; Rise ; C25M ; +; SD[5] ; C25M ; 7.441 ; ; Rise ; C25M ; +; SD[6] ; C25M ; 7.441 ; ; Rise ; C25M ; +; SD[7] ; C25M ; 7.441 ; ; Rise ; C25M ; +; nFCS ; C25M ; 7.200 ; ; Rise ; C25M ; +; RD[*] ; PHI0 ; 8.836 ; ; Rise ; PHI0 ; +; RD[0] ; PHI0 ; 12.857 ; ; Rise ; PHI0 ; +; RD[1] ; PHI0 ; 12.857 ; ; Rise ; PHI0 ; +; RD[2] ; PHI0 ; 12.857 ; ; Rise ; PHI0 ; +; RD[3] ; PHI0 ; 13.387 ; ; Rise ; PHI0 ; +; RD[4] ; PHI0 ; 13.387 ; ; Rise ; PHI0 ; +; RD[5] ; PHI0 ; 13.387 ; ; Rise ; PHI0 ; +; RD[6] ; PHI0 ; 13.387 ; ; Rise ; PHI0 ; +; RD[7] ; PHI0 ; 8.836 ; ; Rise ; PHI0 ; +; RD[*] ; PHI0 ; 8.836 ; ; Fall ; PHI0 ; +; RD[0] ; PHI0 ; 12.857 ; ; Fall ; PHI0 ; +; RD[1] ; PHI0 ; 12.857 ; ; Fall ; PHI0 ; +; RD[2] ; PHI0 ; 12.857 ; ; Fall ; PHI0 ; +; RD[3] ; PHI0 ; 13.387 ; ; Fall ; PHI0 ; +; RD[4] ; PHI0 ; 13.387 ; ; Fall ; PHI0 ; +; RD[5] ; PHI0 ; 13.387 ; ; Fall ; PHI0 ; +; RD[6] ; PHI0 ; 13.387 ; ; Fall ; PHI0 ; +; RD[7] ; PHI0 ; 8.836 ; ; Fall ; PHI0 ; +-----------+------------+-----------+-----------+------------+-----------------+ @@ -1146,9 +1126,9 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +------------+----------+----------+----------+----------+----------+ ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; +------------+----------+----------+----------+----------+----------+ -; C25M ; C25M ; 1478 ; 0 ; 0 ; 0 ; -; PHI0 ; C25M ; 91 ; 1 ; 0 ; 0 ; -; C25M ; PHI0 ; 6 ; 0 ; 0 ; 0 ; +; C25M ; C25M ; 1378 ; 0 ; 0 ; 0 ; +; PHI0 ; C25M ; 87 ; 1 ; 0 ; 0 ; +; C25M ; PHI0 ; 1 ; 0 ; 0 ; 0 ; +------------+----------+----------+----------+----------+----------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. @@ -1158,9 +1138,9 @@ Entries labeled "false path" only account for clock-to-clock false paths and not +------------+----------+----------+----------+----------+----------+ ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; +------------+----------+----------+----------+----------+----------+ -; C25M ; C25M ; 1478 ; 0 ; 0 ; 0 ; -; PHI0 ; C25M ; 91 ; 1 ; 0 ; 0 ; -; C25M ; PHI0 ; 6 ; 0 ; 0 ; 0 ; +; C25M ; C25M ; 1378 ; 0 ; 0 ; 0 ; +; PHI0 ; C25M ; 87 ; 1 ; 0 ; 0 ; +; C25M ; PHI0 ; 1 ; 0 ; 0 ; 0 ; +------------+----------+----------+----------+----------+----------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. @@ -1204,8 +1184,8 @@ No dedicated SERDES Receiver circuitry present in device or used in design +---------------------------------+-------+------+ ; Illegal Clocks ; 0 ; 0 ; ; Unconstrained Clocks ; 0 ; 0 ; -; Unconstrained Input Ports ; 44 ; 44 ; -; Unconstrained Input Port Paths ; 651 ; 651 ; +; Unconstrained Input Ports ; 42 ; 42 ; +; Unconstrained Input Port Paths ; 632 ; 632 ; ; Unconstrained Output Ports ; 45 ; 45 ; ; Unconstrained Output Port Paths ; 118 ; 118 ; +---------------------------------+-------+------+ @@ -1217,7 +1197,7 @@ No dedicated SERDES Receiver circuitry present in device or used in design Info: ******************************************************************* Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - Info: Processing started: Sun Apr 18 03:45:26 2021 + Info: Processing started: Sun Apr 18 05:55:53 2021 Info: Command: quartus_sta GR8RAM -c GR8RAM Info: qsta_default_script.tcl version: #1 Warning (20028): Parallel compilation is not licensed and has been disabled @@ -1232,24 +1212,24 @@ Info (332105): Deriving Clocks Info (332105): create_clock -period 1.000 -name PHI0 PHI0 Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON Critical Warning (332148): Timing requirements not met -Info (332146): Worst-case setup slack is -9.691 +Info (332146): Worst-case setup slack is -9.431 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== - Info (332119): -9.691 -732.295 C25M - Info (332119): -1.358 -1.358 PHI0 -Info (332146): Worst-case hold slack is 1.092 + Info (332119): -9.431 -683.489 C25M + Info (332119): -1.421 -1.421 PHI0 +Info (332146): Worst-case hold slack is 1.384 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== - Info (332119): 1.092 0.000 PHI0 - Info (332119): 1.418 0.000 C25M -Info (332146): Worst-case recovery slack is -5.009 + Info (332119): 1.384 0.000 C25M + Info (332119): 1.867 0.000 PHI0 +Info (332146): Worst-case recovery slack is -4.406 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== - Info (332119): -5.009 -150.270 C25M -Info (332146): Worst-case removal slack is 5.455 + Info (332119): -4.406 -132.180 C25M +Info (332146): Worst-case removal slack is 4.852 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== - Info (332119): 5.455 0.000 C25M + Info (332119): 4.852 0.000 C25M Info (332146): Worst-case minimum pulse width slack is -2.289 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== @@ -1260,7 +1240,7 @@ Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 3 warnings Info: Peak virtual memory: 368 megabytes - Info: Processing ended: Sun Apr 18 03:45:27 2021 + Info: Processing ended: Sun Apr 18 05:55:54 2021 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 diff --git a/cpld/output_files/GR8RAM.sta.summary b/cpld/output_files/GR8RAM.sta.summary index ed76518..15eb332 100755 --- a/cpld/output_files/GR8RAM.sta.summary +++ b/cpld/output_files/GR8RAM.sta.summary @@ -3,27 +3,27 @@ TimeQuest Timing Analyzer Summary ------------------------------------------------------------ Type : Setup 'C25M' -Slack : -9.691 -TNS : -732.295 +Slack : -9.431 +TNS : -683.489 Type : Setup 'PHI0' -Slack : -1.358 -TNS : -1.358 - -Type : Hold 'PHI0' -Slack : 1.092 -TNS : 0.000 +Slack : -1.421 +TNS : -1.421 Type : Hold 'C25M' -Slack : 1.418 +Slack : 1.384 +TNS : 0.000 + +Type : Hold 'PHI0' +Slack : 1.867 TNS : 0.000 Type : Recovery 'C25M' -Slack : -5.009 -TNS : -150.270 +Slack : -4.406 +TNS : -132.180 Type : Removal 'C25M' -Slack : 5.455 +Slack : 4.852 TNS : 0.000 Type : Minimum Pulse Width 'C25M'