From c3716ebb82e206eaa16893582675c7bae68ff7bf Mon Sep 17 00:00:00 2001 From: Zane Kaminski Date: Fri, 16 Feb 2024 20:54:16 -0500 Subject: [PATCH] Change ~ to ! where appropriate in GR8RAM.v --- cpld/GR8RAM.v | 88 ++++++++++++++-------------- cpld/output_files/GR8RAM.asm.rpt | 10 ++-- cpld/output_files/GR8RAM.done | 2 +- cpld/output_files/GR8RAM.fit.rpt | 10 ++-- cpld/output_files/GR8RAM.fit.summary | 2 +- cpld/output_files/GR8RAM.flow.rpt | 18 +++--- cpld/output_files/GR8RAM.map.rpt | 14 ++--- cpld/output_files/GR8RAM.map.summary | 2 +- cpld/output_files/GR8RAM.sta.rpt | 14 ++--- 9 files changed, 80 insertions(+), 80 deletions(-) diff --git a/cpld/GR8RAM.v b/cpld/GR8RAM.v index 41dd3b5..d8e9a51 100644 --- a/cpld/GR8RAM.v +++ b/cpld/GR8RAM.v @@ -24,7 +24,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, reg [1:0] SetFWr; reg SetFWLoaded = 0; always @(posedge C25M) begin - if (~SetFWLoaded) begin + if (!SetFWLoaded) begin SetFWLoaded <= 1; SetFWr[1:0] <= SetFW[1:0]; end @@ -35,7 +35,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, /* State counter from PHI0 rising edge */ reg [3:0] PS = 0; - wire PSStart = PS==0 && PHI0r1 && ~PHI0r2; + wire PSStart = PS==0 && PHI0r1 && !PHI0r2; always @(posedge C25M) begin if (PSStart) PS <= 1; else if (PS==0) PS <= 0; @@ -74,43 +74,43 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, end /* Apple select signals */ - wire ROMSpecRD = CXXXr && RAr[11:8]!=4'h0 && nWEr && ((RAr[11] && IOROMEN) || (~RAr[11])); + wire ROMSpecRD = CXXXr && RAr[11:8]!=4'h0 && nWEr && ((RAr[11] && IOROMEN) || (!RAr[11])); wire REGSpecSEL = CXXXr && RAr[11:8]==4'h0 && RAr[7] && REGEN; wire BankSpecSEL = REGSpecSEL && RAr[3:0]==4'hF; wire RAMRegSpecSEL = REGSpecSEL && RAr[3:0]==4'h3; - wire RAMSpecSEL = RAMRegSpecSEL && (~SetEN24bit || SetEN16MB || ~Addr[23]); + wire RAMSpecSEL = RAMRegSpecSEL && (!SetEN24bit || SetEN16MB || !Addr[23]); wire AddrHSpecSEL = REGSpecSEL && RAr[3:0]==4'h2; wire AddrMSpecSEL = REGSpecSEL && RAr[3:0]==4'h1; wire AddrLSpecSEL = REGSpecSEL && RAr[3:0]==4'h0; - wire BankSEL = REGEN && ~nDEVSEL && BankSpecSEL; - wire RAMRegSEL = ~nDEVSEL && RAMRegSpecSEL; - wire RAMSEL = ~nDEVSEL && RAMSpecSEL; - wire RAMWR = RAMSEL && ~nWEr; - wire AddrHSEL = REGEN && ~nDEVSEL && AddrHSpecSEL; - wire AddrMSEL = REGEN && ~nDEVSEL && AddrMSpecSEL; - wire AddrLSEL = REGEN && ~nDEVSEL && AddrLSpecSEL; + wire BankSEL = REGEN && !nDEVSEL && BankSpecSEL; + wire RAMRegSEL = !nDEVSEL && RAMRegSpecSEL; + wire RAMSEL = !nDEVSEL && RAMSpecSEL; + wire RAMWR = RAMSEL && !nWEr; + wire AddrHSEL = REGEN && !nDEVSEL && AddrHSpecSEL; + wire AddrMSEL = REGEN && !nDEVSEL && AddrMSpecSEL; + wire AddrLSEL = REGEN && !nDEVSEL && AddrLSpecSEL; /* IOROMEN and REGEN control */ reg IOROMEN = 0; reg REGEN = 0; reg nIOSTRBr; - wire IOROMRES = RAr[10:0]==11'h7FF && ~nIOSTRB && ~nIOSTRBr; + wire IOROMRES = RAr[10:0]==11'h7FF && !nIOSTRB && !nIOSTRBr; always @(posedge C25M, negedge nRESr) begin - if (~nRESr) REGEN <= 0; - else if (PS==8 && ~nIOSEL) REGEN <= 1; + if (!nRESr) REGEN <= 0; + else if (PS==8 && !nIOSEL) REGEN <= 1; end always @(posedge C25M) begin nIOSTRBr <= nIOSTRB; - if (~nRESr) IOROMEN <= 0; + if (!nRESr) IOROMEN <= 0; else if (PS==8 && IOROMRES) IOROMEN <= 0; - else if (PS==8 && ~nIOSEL) IOROMEN <= 1; + else if (PS==8 && !nIOSEL) IOROMEN <= 1; end /* Apple data bus */ inout [7:0] RD = RDdir ? 8'bZ : RDD[7:0]; reg [7:0] RDD; - output RDdir = ~(PHI0r2 && nWE && PHI0 && - (~nDEVSEL || ~nIOSEL || (~nIOSTRB && IOROMEN && RA[10:0]!=11'h7FF))); + output RDdir = !(PHI0r2 && nWE && PHI0 && + (!nDEVSEL || !nIOSEL || (!nIOSTRB && IOROMEN && RA[10:0]!=11'h7FF))); /* Slinky address registers */ reg [23:0] Addr = 0; @@ -118,7 +118,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, reg AddrIncM = 0; reg AddrIncH = 0; always @(posedge C25M, negedge nRESr) begin - if (~nRESr) begin + if (!nRESr) begin Addr[23:0] <= 24'h000000; AddrIncL <= 0; AddrIncM <= 0; @@ -127,23 +127,23 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, if (PS==8 && RAMRegSEL) AddrIncL <= 1; else AddrIncL <= 0; - if (PS==8 && AddrLSEL && ~nWEr) begin + if (PS==8 && AddrLSEL && !nWEr) begin Addr[7:0] <= RD[7:0]; - AddrIncM <= Addr[7] && ~RD[7]; + AddrIncM <= Addr[7] && !RD[7]; end else if (AddrIncL) begin Addr[7:0] <= Addr[7:0]+1; AddrIncM <= Addr[7:0]==8'hFF; end else AddrIncM <= 0; - if (PS==8 && AddrMSEL && ~nWEr) begin + if (PS==8 && AddrMSEL && !nWEr) begin Addr[15:8] <= RD[7:0]; - AddrIncH <= Addr[15] && ~RD[7]; + AddrIncH <= Addr[15] && !RD[7]; end else if (AddrIncM) begin Addr[15:8] <= Addr[15:8]+1; AddrIncH <= Addr[15:8]==8'hFF; end else AddrIncH <= 0; - if (PS==8 && AddrHSEL && ~nWEr) begin + if (PS==8 && AddrHSEL && !nWEr) begin Addr[23:16] <= RD[7:0]; end else if (AddrIncH) begin Addr[23:16] <= Addr[23:16]+1; @@ -154,14 +154,14 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, /* ROM bank register */ reg Bank = 0; always @(posedge C25M, negedge nRESr) begin - if (~nRESr) Bank <= 0; - else if (PS==8 && BankSEL && ~nWEr) begin + if (!nRESr) Bank <= 0; + else if (PS==8 && BankSEL && !nWEr) begin Bank <= RD[0]; end end /* SPI flash control signals */ - output nFCS = FCKOE ? ~FCS : 1'bZ; + output nFCS = FCKOE ? !FCS : 1'bZ; reg FCS = 0; output FCK = FCKOE ? FCKout : 1'bZ; reg FCKOE = 0; @@ -174,35 +174,35 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, 0: begin // NOP CKE FCKout <= 1'b1; end 1: begin // ACT - FCKout <= ~(IS==5 || IS==6); + FCKout <= !(IS==5 || IS==6); end 2: begin // RD FCKout <= 1'b1; end 3: begin // NOP CKE - FCKout <= ~(IS==5 || IS==6); + FCKout <= !(IS==5 || IS==6); end 4: begin // NOP CKE FCKout <= 1'b1; end 5: begin // NOP CKE - FCKout <= ~(IS==5 || IS==6); + FCKout <= !(IS==5 || IS==6); end 6: begin // NOP CKE FCKout <= 1'b1; end 7: begin // NOP CKE - FCKout <= ~(IS==5 || IS==6); + FCKout <= !(IS==5 || IS==6); end 8: begin // WR AP FCKout <= 1'b1; end 9: begin // NOP CKE - FCKout <= ~(IS==5); + FCKout <= !(IS==5); end 10: begin // PC all FCKout <= 1'b1; end 11: begin // AREF - FCKout <= ~(IS==5); + FCKout <= !(IS==5); end 12: begin // NOP CKE FCKout <= 1'b1; end 13: begin // NOP CKE - FCKout <= ~(IS==5); + FCKout <= !(IS==5); end 14: begin // NOP CKE FCKout <= 1'b1; end 15: begin // NOP CKE - FCKout <= ~(IS==5); + FCKout <= !(IS==5); end endcase FCS <= IS==4 || IS==5 || IS==6; @@ -352,14 +352,14 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, SDOE <= 0; end 1: begin // ACT CKE / NOP CKD (ACT) RCKE <= IS==6 || (IS==7 && (ROMSpecRD || RAMSpecSEL)); - nRCS <= ~(IS==6 || (IS==7 && (ROMSpecRD || RAMSpecSEL))); + nRCS <= !(IS==6 || (IS==7 && (ROMSpecRD || RAMSpecSEL))); nRAS <= 0; nCAS <= 1; nSWE <= 1; SDOE <= 0; end 2: begin // RD CKE / NOP CKD (RD) RCKE <= IS==7 && nWEr && (ROMSpecRD || RAMSpecSEL); - nRCS <= ~(IS==7 && nWEr && (ROMSpecRD || RAMSpecSEL)); + nRCS <= !(IS==7 && nWEr && (ROMSpecRD || RAMSpecSEL)); nRAS <= 1; nCAS <= 0; nSWE <= 1; @@ -401,7 +401,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, SDOE <= 0; end 8: begin // WR AP CKE / NOP CKD (WR AP) RCKE <= IS==6 || (RAMWR && IS==7); - nRCS <= ~(IS==6 || (RAMWR && IS==7)); + nRCS <= !(IS==6 || (RAMWR && IS==7)); nRAS <= 1; nCAS <= 0; nSWE <= 0; @@ -422,10 +422,10 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, SDOE <= 0; end 11: begin // LDM CKE / AREF CKE / NOP CKD RCKE <= IS==1 || IS==4 || IS==5 || IS==6 || (IS==7 && RefReqd); - nRCS <= ~(IS==1 || IS==4 || IS==5 || IS==6 || (IS==7 && RefReqd)); + nRCS <= !(IS==1 || IS==4 || IS==5 || IS==6 || (IS==7 && RefReqd)); nRAS <= 0; nCAS <= 0; - nSWE <= ~(IS==1); + nSWE <= !(IS==1); SDOE <= 0; end default: begin // NOP CKD RCKE <= 0; @@ -469,12 +469,12 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 }; SA[12:0] <= { 4'b0011, Addr[9:1] }; DQML <= Addr[0]; - DQMH <= ~Addr[0]; + DQMH <= !Addr[0]; end else begin SBA[1:0] <= 2'b10; SA[12:0] <= { 4'b0011, RAr[9:1]}; DQML <= RAr[0]; - DQMH <= ~RAr[0]; + DQMH <= !RAr[0]; end end 3: begin // NOP CKE DQML <= 1'b1; @@ -506,12 +506,12 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, SBA[1:0] <= 2'b10; SA[12:0] <= { 4'b0011, LS[9:1] }; DQML <= LS[0]; - DQMH <= ~LS[0]; + DQMH <= !LS[0]; end else begin SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 }; SA[12:0] <= { 4'b0011, Addr[9:1] }; DQML <= Addr[0]; - DQMH <= ~Addr[0]; + DQMH <= !Addr[0]; end end 9: begin // NOP CKE DQML <= 1'b1; diff --git a/cpld/output_files/GR8RAM.asm.rpt b/cpld/output_files/GR8RAM.asm.rpt index f2642bc..5bdfd4f 100644 --- a/cpld/output_files/GR8RAM.asm.rpt +++ b/cpld/output_files/GR8RAM.asm.rpt @@ -1,5 +1,5 @@ Assembler report for GR8RAM -Fri Feb 16 20:46:17 2024 +Fri Feb 16 20:54:00 2024 Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition @@ -38,7 +38,7 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Fri Feb 16 20:46:17 2024 ; +; Assembler Status ; Successful - Fri Feb 16 20:54:00 2024 ; ; Revision Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ; ; Family ; MAX II ; @@ -78,14 +78,14 @@ https://fpgasoftware.intel.com/eula. Info: ******************************************************************* Info: Running Quartus Prime Assembler Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition - Info: Processing started: Fri Feb 16 20:46:16 2024 + Info: Processing started: Fri Feb 16 20:53:59 2024 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (115031): Writing out detailed assembly data for power analysis Info (115030): Assembler is generating device programming files Info: Quartus Prime Assembler was successful. 0 errors, 1 warning - Info: Peak virtual memory: 13096 megabytes - Info: Processing ended: Fri Feb 16 20:46:17 2024 + Info: Peak virtual memory: 13097 megabytes + Info: Processing ended: Fri Feb 16 20:54:00 2024 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 diff --git a/cpld/output_files/GR8RAM.done b/cpld/output_files/GR8RAM.done index f733ffc..be946f0 100644 --- a/cpld/output_files/GR8RAM.done +++ b/cpld/output_files/GR8RAM.done @@ -1 +1 @@ -Fri Feb 16 20:46:20 2024 +Fri Feb 16 20:54:03 2024 diff --git a/cpld/output_files/GR8RAM.fit.rpt b/cpld/output_files/GR8RAM.fit.rpt index ca69b5b..a227abb 100644 --- a/cpld/output_files/GR8RAM.fit.rpt +++ b/cpld/output_files/GR8RAM.fit.rpt @@ -1,5 +1,5 @@ Fitter report for GR8RAM -Fri Feb 16 20:46:15 2024 +Fri Feb 16 20:53:58 2024 Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition @@ -58,7 +58,7 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------------+ ; Fitter Summary ; +-----------------------+---------------------------------------------+ -; Fitter Status ; Successful - Fri Feb 16 20:46:15 2024 ; +; Fitter Status ; Successful - Fri Feb 16 20:53:58 2024 ; ; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; ; Revision Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ; @@ -134,7 +134,7 @@ https://fpgasoftware.intel.com/eula. ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; -; Processor 2 ; 1.0% ; +; Processor 2 ; 0.8% ; ; Processors 3-4 ; 0.7% ; +----------------------------+-------------+ @@ -780,8 +780,8 @@ Warning (169174): The Reserve All Unused Pins setting has not been specified, an Info (144001): Generated suppressed messages file /Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg Info: Quartus Prime Fitter was successful. 0 errors, 4 warnings Info: Peak virtual memory: 13772 megabytes - Info: Processing ended: Fri Feb 16 20:46:15 2024 - Info: Elapsed time: 00:00:03 + Info: Processing ended: Fri Feb 16 20:53:58 2024 + Info: Elapsed time: 00:00:02 Info: Total CPU time (on all processors): 00:00:03 diff --git a/cpld/output_files/GR8RAM.fit.summary b/cpld/output_files/GR8RAM.fit.summary index 2985690..4cfb17a 100644 --- a/cpld/output_files/GR8RAM.fit.summary +++ b/cpld/output_files/GR8RAM.fit.summary @@ -1,4 +1,4 @@ -Fitter Status : Successful - Fri Feb 16 20:46:15 2024 +Fitter Status : Successful - Fri Feb 16 20:53:58 2024 Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition Revision Name : GR8RAM Top-level Entity Name : GR8RAM diff --git a/cpld/output_files/GR8RAM.flow.rpt b/cpld/output_files/GR8RAM.flow.rpt index 82db817..fe43cef 100644 --- a/cpld/output_files/GR8RAM.flow.rpt +++ b/cpld/output_files/GR8RAM.flow.rpt @@ -1,5 +1,5 @@ Flow report for GR8RAM -Fri Feb 16 20:46:19 2024 +Fri Feb 16 20:54:03 2024 Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition @@ -41,7 +41,7 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------------+ ; Flow Summary ; +-----------------------+---------------------------------------------+ -; Flow Status ; Successful - Fri Feb 16 20:46:17 2024 ; +; Flow Status ; Successful - Fri Feb 16 20:54:00 2024 ; ; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; ; Revision Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ; @@ -60,7 +60,7 @@ https://fpgasoftware.intel.com/eula. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 02/16/2024 20:45:52 ; +; Start date & time ; 02/16/2024 20:53:35 ; ; Main task ; Compilation ; ; Revision Name ; GR8RAM ; +-------------------+---------------------+ @@ -71,7 +71,7 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------+----------------------------------------+---------------+-------------+------------+ ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; +---------------------------------------+----------------------------------------+---------------+-------------+------------+ -; COMPILER_SIGNATURE_ID ; 121380219419.170813435209448 ; -- ; -- ; -- ; +; COMPILER_SIGNATURE_ID ; 121380219419.170813481504184 ; -- ; -- ; -- ; ; IOBANK_VCCIO ; -- (Not supported for targeted family) ; -- ; -- ; 1 ; ; IOBANK_VCCIO ; -- (Not supported for targeted family) ; -- ; -- ; 2 ; ; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; @@ -86,11 +86,11 @@ https://fpgasoftware.intel.com/eula. +----------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:19 ; 1.0 ; 13145 MB ; 00:00:41 ; -; Fitter ; 00:00:03 ; 1.0 ; 13772 MB ; 00:00:03 ; -; Assembler ; 00:00:01 ; 1.0 ; 13092 MB ; 00:00:01 ; -; Timing Analyzer ; 00:00:01 ; 1.0 ; 13094 MB ; 00:00:01 ; -; Total ; 00:00:24 ; -- ; -- ; 00:00:46 ; +; Analysis & Synthesis ; 00:00:20 ; 1.0 ; 13135 MB ; 00:00:43 ; +; Fitter ; 00:00:02 ; 1.0 ; 13772 MB ; 00:00:03 ; +; Assembler ; 00:00:01 ; 1.0 ; 13093 MB ; 00:00:01 ; +; Timing Analyzer ; 00:00:02 ; 1.0 ; 13090 MB ; 00:00:01 ; +; Total ; 00:00:25 ; -- ; -- ; 00:00:48 ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ diff --git a/cpld/output_files/GR8RAM.map.rpt b/cpld/output_files/GR8RAM.map.rpt index ccf51e4..05fb753 100644 --- a/cpld/output_files/GR8RAM.map.rpt +++ b/cpld/output_files/GR8RAM.map.rpt @@ -1,5 +1,5 @@ Analysis & Synthesis report for GR8RAM -Fri Feb 16 20:46:11 2024 +Fri Feb 16 20:53:55 2024 Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition @@ -46,7 +46,7 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +-----------------------------+---------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Fri Feb 16 20:46:11 2024 ; +; Analysis & Synthesis Status ; Successful - Fri Feb 16 20:53:55 2024 ; ; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; ; Revision Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ; @@ -280,7 +280,7 @@ Encoding Type: One-Hot Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition - Info: Processing started: Fri Feb 16 20:45:52 2024 + Info: Processing started: Fri Feb 16 20:53:35 2024 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected @@ -308,10 +308,10 @@ Info (21057): Implemented 333 device resources after synthesis - the final resou Info (21061): Implemented 253 logic cells Info (144001): Generated suppressed messages file /Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 14 warnings - Info: Peak virtual memory: 13145 megabytes - Info: Processing ended: Fri Feb 16 20:46:11 2024 - Info: Elapsed time: 00:00:19 - Info: Total CPU time (on all processors): 00:00:41 + Info: Peak virtual memory: 13135 megabytes + Info: Processing ended: Fri Feb 16 20:53:55 2024 + Info: Elapsed time: 00:00:20 + Info: Total CPU time (on all processors): 00:00:43 +------------------------------------------+ diff --git a/cpld/output_files/GR8RAM.map.summary b/cpld/output_files/GR8RAM.map.summary index 736b3f6..e488d89 100644 --- a/cpld/output_files/GR8RAM.map.summary +++ b/cpld/output_files/GR8RAM.map.summary @@ -1,4 +1,4 @@ -Analysis & Synthesis Status : Successful - Fri Feb 16 20:46:11 2024 +Analysis & Synthesis Status : Successful - Fri Feb 16 20:53:55 2024 Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition Revision Name : GR8RAM Top-level Entity Name : GR8RAM diff --git a/cpld/output_files/GR8RAM.sta.rpt b/cpld/output_files/GR8RAM.sta.rpt index 78369cc..2fc6021 100644 --- a/cpld/output_files/GR8RAM.sta.rpt +++ b/cpld/output_files/GR8RAM.sta.rpt @@ -1,5 +1,5 @@ Timing Analyzer report for GR8RAM -Fri Feb 16 20:46:19 2024 +Fri Feb 16 20:54:03 2024 Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition @@ -84,7 +84,7 @@ https://fpgasoftware.intel.com/eula. ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; -; Processor 2 ; 0.2% ; +; Processor 2 ; 0.0% ; +----------------------------+-------------+ @@ -93,7 +93,7 @@ https://fpgasoftware.intel.com/eula. +---------------+--------+--------------------------+ ; SDC File Path ; Status ; Read at ; +---------------+--------+--------------------------+ -; GR8RAM.sdc ; OK ; Fri Feb 16 20:46:19 2024 ; +; GR8RAM.sdc ; OK ; Fri Feb 16 20:54:03 2024 ; +---------------+--------+--------------------------+ @@ -747,7 +747,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi Info: ******************************************************************* Info: Running Quartus Prime Timing Analyzer Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition - Info: Processing started: Fri Feb 16 20:46:18 2024 + Info: Processing started: Fri Feb 16 20:54:01 2024 Info: Command: quartus_sta GR8RAM -c GR8RAM Info: qsta_default_script.tcl version: #1 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. @@ -784,9 +784,9 @@ Info (332001): The selected device family is not supported by the report_metasta Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements Info: Quartus Prime Timing Analyzer was successful. 0 errors, 1 warning - Info: Peak virtual memory: 13094 megabytes - Info: Processing ended: Fri Feb 16 20:46:19 2024 - Info: Elapsed time: 00:00:01 + Info: Peak virtual memory: 13090 megabytes + Info: Processing ended: Fri Feb 16 20:54:03 2024 + Info: Elapsed time: 00:00:02 Info: Total CPU time (on all processors): 00:00:01