Doesn't work but committing for posterity
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Zane Kaminski
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c7cd1bb11e
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c5f1e637ac
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@ -25,11 +25,11 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
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input [15:0] A; // 6502 address bus
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input nWE; // 6502 R/W
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output [10:0] RA; // DRAM/ROM address
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assign RA[10:8] = ASel ? Addr[21:19] : Addr[10:8];
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assign RA[10:8] = ColAddrSel ? Addr[21:19] : Addr[10:8];
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assign RA[7:0] = (~nIOSTRB & FullIOEN) ? Bank+1 :
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(~nIOSTRB & ~FullIOEN) ? {7'b0000001, Bank[0]} :
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(~ASel & nIOSEL & nIOSTRB) ? Addr[18:11] :
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(ASel & nIOSEL & nIOSTRB) ? Addr[7:0] : 8'h00;
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(~ColAddrSel & nIOSEL & nIOSTRB) ? Addr[18:11] :
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(ColAddrSel & nIOSEL & nIOSTRB) ? Addr[7:0] : 8'h00;
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/* Select Signals */
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wire BankSELA = A[3:0]==4'hF;
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@ -48,7 +48,8 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
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/* Data Bus Routing */
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// DRAM/ROM data bus
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wire RDOE = DBEN & ~nWE;
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inout [7:0] RD = RDOE ? D[7:0] : 8'bZ;
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inout [7:0] RD = RDOE ? RDout : 8'bZ;
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reg [7:0] RDout;
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// Apple II data bus
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wire DOE = DBEN & nWE &
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((~nDEVSEL & REGEN) | ~nIOSEL | (~nIOSTRB & IOROMEN));
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@ -62,9 +63,9 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
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output nINH = 1'bZ;
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/* DRAM and ROM Control Signals */
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output nRCS = ~((~nIOSEL | (~nIOSTRB & IOROMEN)) & CSDBEN & nRES); // ROM chip select
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output nRCS = ~((~nIOSEL | (~nIOSTRB & IOROMEN)) & CSEN); // ROM chip select
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output nROE = ~nWE; // need this for flash ROM
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output reg nRWE; // for ROM & DRAM
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output nRWE = ColAddrSel ? nWE : 1'b1; // for ROM & DRAM
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output nRAS = ~(RASr | RASf);
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output nCAS0 = ~(CAS0f | (CASr & RAMSEL & ~Addr[22])); // DRAM CAS bank 0
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output nCAS1 = ~(CAS1f | (CASr & RAMSEL & Addr[22])); // DRAM CAS bank 1
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@ -80,7 +81,7 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
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// These are combined to create the CAS outputs.
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reg CASr = 0, CAS0f = 0, CAS1f = 0;
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reg RASr = 0, RASf = 0;
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reg ASel = 0; // DRAM address multiplexer select
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reg ColAddrSel = 0; // DRAM address multiplexer select
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/* State Counters */
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reg PHI1reg = 0; // Saved PHI1 at last rising clock edge
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@ -92,9 +93,8 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
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reg REGEN = 0; // Register enable
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reg IOROMEN = 0; // IOSTRB ROM enable
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reg FullIOEN = 0; // Set to enable full IOROM space
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reg DBEN = 0; // data bus driver gating
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reg RDCSEN = 0; // ROM CS enable for reads
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reg WRCSEN = 0; // ROM CS gating for writes
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reg DBEN = 0; // Data bus driver gating
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reg CSEN = 0; // ROM CS enable gating
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// Apple II Bus Compatibiltiy Rules:
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// Synchronize to PHI0 or PHI1. (PHI1 here)
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@ -106,7 +106,8 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
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// all 3 falling edges of C7M in PHI0 (S4, S5, S6)
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// Can sample /IOSTRB at same times as /IOSEL, plus:
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// 1st rising edge of C7M in PHI0 (S3)
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/* State counters */
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always @(posedge C7M) begin
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// Synchronize state counter to S1 when just entering PHI1
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PHI1reg <= PHI1; // Save old PHI1
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@ -117,46 +118,45 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
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// Refresh counter allows DRAM refresh once every 13 cycles
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if (S==3) Ref <= (Ref[3:2]==2'b11) ? 4'h0 : Ref+1;
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// Only drive Apple II data bus after state 4 to avoid bus fight.
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// Thus we wait 1.5 7M cycles (210 ns) into PHI0 before driving.
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// Same for driving the ROM/SRAM data bus (RD).
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DBEN <= S==4 | S==5 | S==6 | S==7;
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// Similarly, only select the ROM chip starting at
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// the end of S4 for reads and the end of S5 for writes.
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// This ensures that write data is valid for
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// the entire time that the ROM is selected,
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// and minimizes power consumption for reads.
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RDCSEN <= S==4 | S==5 | S==6 | S==7;
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WRCSEN <= S==5 | S==6 | S==7;
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end
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/* State-based data bus and ROM CS gating */
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always @(posedge C7M, negedge nRES) begin
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if (~nRES) begin
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DBEN <= 0;
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CSEN <= 0;
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end else begin
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// Only drive Apple II data bus after S4 to avoid bus fight.
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// Thus we wait 1.5 7M cycles (210 ns) into PHI0 before driving.
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// Same for driving the ROM/SRAM data bus (RD).
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DBEN <= S==4 | S==5 | S==6 | S==7;
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// Similarly, only select the ROM chip starting at
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// the end of S4 for reads and the end of S5 for writes.
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// This ensures that write data is valid for
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// the entire time that the ROM is selected,
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// and minimizes power consumption.
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CSEN <= (S==4 & nWE) | S==5 | S==6 | S==7;
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end
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end
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/* State-based data bus and ROM CS gating */
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always @(posedge C7M, negedge nRES) begin
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if (~nRES) begin
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REGEN <= 0;
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IOROMEN <= 0;
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end else begin
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// Synchronize state counter to S1 when just entering PHI1
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PHI1reg <= PHI1; // Save old PHI1
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if (~PHI1) PHI0seen <= 1; // PHI0seen set in PHI0
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S <= (PHI1 & ~PHI1reg & PHI0seen) ? 4'h1 :
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S==0 ? 3'h0 :
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S==7 ? 3'h7 : S+1;
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// Refresh counter allows DRAM refresh once every 13 cycles
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if (S==3) Ref <= (Ref[3:2] == 2'b11) ? 4'h0 : Ref+1;
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// Disable IOSTRB ROM when accessing 0xCFFF.
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if (S==3 & ~nIOSTRB & A[10:0]==11'h7FF) IOROMEN <= 1'b0;
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// Registers enabled at end of S4 by any IOSEL access (Cn00-CnFF).
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// Enable registers at end of S4 when IOSEL accessed (Cn00-CnFF).
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if (S==4 & ~nIOSEL) REGEN <= 1;
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// Enable IOSTRB ROM when accessing CnXX in IOSEL ROM.
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if (S==4 & ~nIOSEL) IOROMEN <= 1'b1;
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// Disable IOSTRB ROM when accessing 0xCFFF.
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if (S==4 & ~nIOSTRB & A[10:0]==11'h7FF) IOROMEN <= 1'b0;
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end
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end
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/* Set memory-mapped registers */
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always @(negedge C7M, negedge nRES) begin
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if (~nRES) begin
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Addr <= 0;
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@ -182,6 +182,11 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
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Addr[23:16] <= Addr[23:16]+1;
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end
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// Latch 6502 write data to RD in middle of S5
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if (S==5) begin
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RDout[7:0] <= D[7:0];
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end
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// Set register in middle of S6 if accessed.
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if (S==6) begin
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if (BankWR) Bank[7:0] <= D[7:0]; // Bank
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@ -204,17 +209,14 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
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(S==4 & RAMSEL & nWE) | // Read: Early RAS
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(S==5 & RAMSEL & ~nWE); // Write: Late RAS
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// Multiplex DRAM address in at end of S4 through S6.
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ASel = (RAMSEL & nWE & S==4) | // Read: mux address early
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// Multiplex DRAM address
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ColAddrSel = (RAMSEL & nWE & S==4) | // Read: mux address early
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(RAMSEL & ~nWE & S==5); // Write: mux address late
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// Read: long, early CAS, gated later by RAMSEL
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CASr <= (RAMSEL & ~nWE & (S==5 | S==6 | S==7));
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end
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always @(negedge C7M) begin
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if (S==0 | S==1) nRWE <= 1;
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if (S==3) nRWE <= nWE;
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RASf <= (S==4 & RAMSEL & nWE) | // Read: Early RAS
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(S==5 & RAMSEL & ~nWE); // Write: Late RAS
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