diff --git a/cpld/GR8RAM.qsf b/cpld/GR8RAM.qsf index e466284..40fd6d4 100755 --- a/cpld/GR8RAM.qsf +++ b/cpld/GR8RAM.qsf @@ -72,446 +72,93 @@ set_global_assignment -name SEED 235 set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII "MINIMIZE AREA" set_global_assignment -name ROUTER_REGISTER_DUPLICATION OFF set_global_assignment -name VERILOG_FILE GR8RAM.v - +set_location_assignment PIN_1 -to RA[4] +set_location_assignment PIN_2 -to RA[5] +set_location_assignment PIN_3 -to RA[6] +set_location_assignment PIN_4 -to RA[3] +set_location_assignment PIN_5 -to nFCS +set_location_assignment PIN_6 -to RA[7] +set_location_assignment PIN_7 -to RA[8] +set_location_assignment PIN_8 -to RA[9] +set_location_assignment PIN_12 -to FCK +set_location_assignment PIN_14 -to RA[10] +set_location_assignment PIN_15 -to MOSI +set_location_assignment PIN_16 -to MISO +set_location_assignment PIN_30 -to nRESout +set_location_assignment PIN_34 -to RA[11] +set_location_assignment PIN_35 -to RA[12] +set_location_assignment PIN_36 -to RA[13] +set_location_assignment PIN_37 -to RA[14] +set_location_assignment PIN_38 -to RA[15] +set_location_assignment PIN_39 -to nIOSEL +set_location_assignment PIN_42 -to nIOSTRB +set_location_assignment PIN_40 -to nDEVSEL +set_location_assignment PIN_41 -to PHI0 +set_location_assignment PIN_43 -to nWE +set_location_assignment PIN_44 -to nRES +set_location_assignment PIN_47 -to SD[1] +set_location_assignment PIN_50 -to SD[0] +set_location_assignment PIN_51 -to SD[4] +set_location_assignment PIN_100 -to RA[0] +set_location_assignment PIN_99 -to RD[7] +set_location_assignment PIN_52 -to SD[5] +set_location_assignment PIN_54 -to SD[7] +set_location_assignment PIN_55 -to SD[3] +set_location_assignment PIN_56 -to SD[2] +set_location_assignment PIN_53 -to SD[6] +set_location_assignment PIN_57 -to DQMH +set_location_assignment PIN_58 -to nSWE +set_location_assignment PIN_62 -to nRAS +set_location_assignment PIN_61 -to nCAS +set_location_assignment PIN_64 -to C25M +set_location_assignment PIN_66 -to RCKE +set_location_assignment PIN_67 -to nRCS +set_location_assignment PIN_68 -to SA[12] +set_location_assignment PIN_69 -to SBA[0] +set_location_assignment PIN_70 -to SA[11] +set_location_assignment PIN_71 -to SBA[1] +set_location_assignment PIN_72 -to SA[9] +set_location_assignment PIN_73 -to SA[10] +set_location_assignment PIN_74 -to SA[8] +set_location_assignment PIN_75 -to SA[0] +set_location_assignment PIN_76 -to SA[4] +set_location_assignment PIN_77 -to SA[6] +set_location_assignment PIN_78 -to SA[7] +set_location_assignment PIN_81 -to SA[1] +set_location_assignment PIN_82 -to SA[2] +set_location_assignment PIN_83 -to SA[5] +set_location_assignment PIN_84 -to SA[3] +set_location_assignment PIN_85 -to DQML +set_location_assignment PIN_86 -to RD[0] +set_location_assignment PIN_87 -to RD[1] +set_location_assignment PIN_88 -to RD[2] +set_location_assignment PIN_89 -to RD[3] +set_location_assignment PIN_90 -to RD[4] +set_location_assignment PIN_91 -to RD[5] +set_location_assignment PIN_92 -to RD[6] +set_location_assignment PIN_97 -to RA[2] +set_location_assignment PIN_98 -to RA[1] +set_location_assignment PIN_96 -to SetFW[0] +set_location_assignment PIN_95 -to SetFW[1] set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 1 set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 2 - - -set_location_assignment PIN_41 -to PHI0 -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to PHI0 -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to PHI0 -set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to PHI0 -set_location_assignment PIN_43 -to nWE -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nWE -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nWE -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nWE -set_location_assignment PIN_44 -to nRES -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nRES -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to nRES -set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to nRES - -set_location_assignment PIN_96 -to SetFW[0] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SetFW[0] -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SetFW[0] -set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to SetFW[0] -set_location_assignment PIN_95 -to SetFW[1] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SetFW[1] -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SetFW[1] -set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to SetFW[1] - -set_location_assignment PIN_39 -to nIOSEL -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nIOSEL -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nIOSEL -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nIOSEL -set_location_assignment PIN_42 -to nIOSTRB -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nIOSTRB -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nIOSTRB -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nIOSTRB -set_location_assignment PIN_40 -to nDEVSEL -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nDEVSEL -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nDEVSEL -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nDEVSEL - -set_location_assignment PIN_100 -to RA[0] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RA[0] -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RA[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RA[0] -set_location_assignment PIN_98 -to RA[1] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RA[1] -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RA[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RA[1] -set_location_assignment PIN_97 -to RA[2] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RA[2] -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RA[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RA[2] -set_location_assignment PIN_4 -to RA[3] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RA[3] -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RA[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RA[3] -set_location_assignment PIN_1 -to RA[4] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RA[4] -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RA[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RA[4] -set_location_assignment PIN_2 -to RA[5] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RA[5] -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RA[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RA[5] -set_location_assignment PIN_3 -to RA[6] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RA[6] -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RA[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RA[6] -set_location_assignment PIN_6 -to RA[7] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RA[7] -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RA[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RA[7] -set_location_assignment PIN_7 -to RA[8] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RA[8] -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RA[8] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RA[8] -set_location_assignment PIN_8 -to RA[9] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RA[9] -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RA[9] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RA[9] -set_location_assignment PIN_14 -to RA[10] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RA[10] -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RA[10] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RA[10] -set_location_assignment PIN_34 -to RA[11] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RA[11] -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RA[11] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RA[11] -set_location_assignment PIN_35 -to RA[12] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RA[12] -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RA[12] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RA[12] -set_location_assignment PIN_36 -to RA[13] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RA[13] -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RA[13] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RA[13] -set_location_assignment PIN_37 -to RA[14] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RA[14] -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RA[14] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RA[14] -set_location_assignment PIN_38 -to RA[15] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RA[15] -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RA[15] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RA[15] - -set_location_assignment PIN_86 -to RD[0] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RD[0] -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to RD[0] -set_instance_assignment -name SLOW_SLEW_RATE OFF -to RD[0] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RD[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RD[0] -set_location_assignment PIN_87 -to RD[1] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RD[1] -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to RD[1] -set_instance_assignment -name SLOW_SLEW_RATE OFF -to RD[1] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RD[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RD[1] -set_location_assignment PIN_88 -to RD[2] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RD[2] -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to RD[2] -set_instance_assignment -name SLOW_SLEW_RATE OFF -to RD[2] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RD[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RD[2] -set_location_assignment PIN_89 -to RD[3] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RD[3] -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to RD[3] -set_instance_assignment -name SLOW_SLEW_RATE OFF -to RD[3] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RD[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RD[3] -set_location_assignment PIN_90 -to RD[4] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RD[4] -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to RD[4] -set_instance_assignment -name SLOW_SLEW_RATE OFF -to RD[4] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RD[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RD[4] -set_location_assignment PIN_91 -to RD[5] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RD[5] -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to RD[5] -set_instance_assignment -name SLOW_SLEW_RATE OFF -to RD[5] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RD[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RD[5] -set_location_assignment PIN_92 -to RD[6] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RD[6] -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to RD[6] -set_instance_assignment -name SLOW_SLEW_RATE OFF -to RD[6] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RD[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RD[6] -set_location_assignment PIN_99 -to RD[7] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RD[7] -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to RD[7] -set_instance_assignment -name SLOW_SLEW_RATE OFF -to RD[7] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RD[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RD[7] - -set_location_assignment PIN_19 -to RAdir -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to RAdir -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RAdir -set_instance_assignment -name SLOW_SLEW_RATE ON -to RAdir -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RAdir -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAdir -set_location_assignment PIN_17 -to RDdir -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to RDdir -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RDdir -set_instance_assignment -name SLOW_SLEW_RATE ON -to RDdir -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RDdir -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RDdir - -set_location_assignment PIN_30 -to nRESout -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nRESout -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nRESout -set_instance_assignment -name SLOW_SLEW_RATE ON -to nRESout -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRESout -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nRESout - -set_location_assignment PIN_5 -to nFCS set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nFCS set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nFCS -set_instance_assignment -name SLOW_SLEW_RATE ON -to nFCS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nFCS -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nFCS - -set_location_assignment PIN_12 -to FCK set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to FCK set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to FCK -set_instance_assignment -name SLOW_SLEW_RATE OFF -to FCK -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to FCK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FCK - -set_location_assignment PIN_15 -to MOSI set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to MOSI set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to MOSI -set_instance_assignment -name SLOW_SLEW_RATE ON -to MOSI -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MOSI -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MOSI - -set_location_assignment PIN_16 -to MISO set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to MISO -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to MISO -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MISO - -set_location_assignment PIN_64 -to C25M -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to C25M -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to C25M -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to C25M -set_location_assignment PIN_66 -to RCKE -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RCKE -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RCKE -set_instance_assignment -name SLOW_SLEW_RATE ON -to RCKE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RCKE -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RCKE -set_location_assignment PIN_67 -to nRCS -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nRCS -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nRCS -set_instance_assignment -name SLOW_SLEW_RATE ON -to nRCS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRCS -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nRCS -set_location_assignment PIN_62 -to nRAS -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nRAS -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nRAS -set_instance_assignment -name SLOW_SLEW_RATE ON -to nRAS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRAS -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nRAS -set_location_assignment PIN_61 -to nCAS -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nCAS -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nCAS -set_instance_assignment -name SLOW_SLEW_RATE ON -to nCAS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nCAS -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nCAS -set_location_assignment PIN_58 -to nSWE -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nSWE -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nSWE -set_instance_assignment -name SLOW_SLEW_RATE ON -to nSWE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSWE -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nSWE -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SBA[1] -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SBA[1] -set_instance_assignment -name SLOW_SLEW_RATE ON -to SBA[1] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SBA[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SBA[1] -set_location_assignment PIN_69 -to SBA[1] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SBA[0] -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SBA[0] -set_instance_assignment -name SLOW_SLEW_RATE ON -to SBA[0] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SBA[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SBA[0] -set_location_assignment PIN_68 -to SBA[0] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SA[12] -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SA[12] -set_instance_assignment -name SLOW_SLEW_RATE ON -to SA[12] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SA[12] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SA[12] -set_location_assignment PIN_70 -to SA[12] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SA[11] -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SA[11] -set_instance_assignment -name SLOW_SLEW_RATE ON -to SA[11] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SA[11] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SA[11] -set_location_assignment PIN_73 -to SA[11] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SA[10] -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SA[10] -set_instance_assignment -name SLOW_SLEW_RATE ON -to SA[10] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SA[10] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SA[10] -set_location_assignment PIN_72 -to SA[10] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SA[9] -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SA[9] -set_instance_assignment -name SLOW_SLEW_RATE ON -to SA[9] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SA[9] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SA[9] -set_location_assignment PIN_74 -to SA[8] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SA[8] -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SA[8] -set_instance_assignment -name SLOW_SLEW_RATE ON -to SA[8] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SA[8] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SA[8] -set_location_assignment PIN_78 -to SA[7] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SA[7] -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SA[7] -set_instance_assignment -name SLOW_SLEW_RATE ON -to SA[7] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SA[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SA[7] -set_location_assignment PIN_77 -to SA[6] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SA[6] -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SA[6] -set_instance_assignment -name SLOW_SLEW_RATE ON -to SA[6] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SA[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SA[6] -set_location_assignment PIN_83 -to SA[5] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SA[5] -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SA[5] -set_instance_assignment -name SLOW_SLEW_RATE ON -to SA[5] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SA[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SA[5] -set_location_assignment PIN_76 -to SA[4] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SA[4] -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SA[4] -set_instance_assignment -name SLOW_SLEW_RATE ON -to SA[4] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SA[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SA[4] -set_location_assignment PIN_84 -to SA[3] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SA[3] -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SA[3] -set_instance_assignment -name SLOW_SLEW_RATE ON -to SA[3] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SA[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SA[3] -set_location_assignment PIN_82 -to SA[2] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SA[2] -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SA[2] -set_instance_assignment -name SLOW_SLEW_RATE ON -to SA[2] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SA[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SA[2] -set_location_assignment PIN_81 -to SA[1] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SA[1] -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SA[1] -set_instance_assignment -name SLOW_SLEW_RATE ON -to SA[1] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SA[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SA[1] -set_location_assignment PIN_75 -to SA[0] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SA[0] -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SA[0] -set_instance_assignment -name SLOW_SLEW_RATE ON -to SA[0] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SA[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SA[0] -set_location_assignment PIN_57 -to DQMH -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to DQMH -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to DQMH -set_instance_assignment -name SLOW_SLEW_RATE ON -to DQMH -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to DQMH -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQMH -set_location_assignment PIN_85 -to DQML -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to DQML -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to DQML -set_instance_assignment -name SLOW_SLEW_RATE ON -to DQML -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to DQML -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQML - -set_location_assignment PIN_50 -to SD[0] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SD[0] -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to SD[0] -set_instance_assignment -name SLOW_SLEW_RATE ON -to SD[0] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SD[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD[0] -set_location_assignment PIN_47 -to SD[1] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SD[1] -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to SD[1] -set_instance_assignment -name SLOW_SLEW_RATE ON -to SD[1] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SD[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD[1] -set_location_assignment PIN_56 -to SD[2] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SD[2] -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to SD[2] -set_instance_assignment -name SLOW_SLEW_RATE ON -to SD[2] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SD[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD[2] -set_location_assignment PIN_55 -to SD[3] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SD[3] -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to SD[3] -set_instance_assignment -name SLOW_SLEW_RATE ON -to SD[3] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SD[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD[3] -set_location_assignment PIN_51 -to SD[4] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SD[4] -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to SD[4] -set_instance_assignment -name SLOW_SLEW_RATE ON -to SD[4] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SD[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD[4] -set_location_assignment PIN_52 -to SD[5] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SD[5] -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to SD[5] -set_instance_assignment -name SLOW_SLEW_RATE ON -to SD[5] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SD[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD[5] -set_location_assignment PIN_53 -to SD[6] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SD[6] -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to SD[6] -set_instance_assignment -name SLOW_SLEW_RATE ON -to SD[6] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SD[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD[6] -set_location_assignment PIN_54 -to SD[7] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SD[7] -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to SD[7] -set_instance_assignment -name SLOW_SLEW_RATE ON -to SD[7] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SD[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD[7] - -set_location_assignment PIN_48 -to DMAin -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to DMAin -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to DMAin -set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to DMAin -set_location_assignment PIN_49 -to INTin -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to INTin -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to INTin -set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to INTin - -set_location_assignment PIN_20 -to INTout -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to INTout -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to INTout -set_instance_assignment -name SLOW_SLEW_RATE ON -to INTout -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to INTout -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to INTout -set_location_assignment PIN_18 -to DMAout -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to DMAout -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to DMAout -set_instance_assignment -name SLOW_SLEW_RATE ON -to DMAout -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to DMAout -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DMAout - +set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to MISO set_location_assignment PIN_21 -to nDMAout -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nDMAout -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nDMAout -set_instance_assignment -name SLOW_SLEW_RATE ON -to nDMAout -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nDMAout -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nDMAout +set_location_assignment PIN_19 -to RAdir +set_location_assignment PIN_20 -to INTout set_location_assignment PIN_26 -to nNMIout -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nNMIout -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nNMIout -set_instance_assignment -name SLOW_SLEW_RATE ON -to nNMIout -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nNMIout -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nNMIout set_location_assignment PIN_27 -to nINHout -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nINHout -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nINHout -set_instance_assignment -name SLOW_SLEW_RATE ON -to nINHout -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nINHout -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nINHout set_location_assignment PIN_28 -to nRDYout -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nRDYout -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nRDYout -set_instance_assignment -name SLOW_SLEW_RATE ON -to nRDYout -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRDYout -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nRDYout set_location_assignment PIN_29 -to nIRQout -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQout -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nIRQout -set_instance_assignment -name SLOW_SLEW_RATE ON -to nIRQout -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nIRQout -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nIRQout set_location_assignment PIN_33 -to RWout -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to RWout -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RWout -set_instance_assignment -name SLOW_SLEW_RATE ON -to RWout -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RWout -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RWout \ No newline at end of file +set_location_assignment PIN_48 -to DMAin +set_location_assignment PIN_49 -to INTin +set_location_assignment PIN_17 -to RDdir +set_location_assignment PIN_18 -to DMAout \ No newline at end of file diff --git a/cpld/GR8RAM.qws b/cpld/GR8RAM.qws index 788841d..38d1f45 100755 Binary files a/cpld/GR8RAM.qws and b/cpld/GR8RAM.qws differ diff --git a/cpld/db/GR8RAM.ace_cmp.cdb b/cpld/db/GR8RAM.ace_cmp.cdb index 0bc3829..edfb26a 100755 Binary files a/cpld/db/GR8RAM.ace_cmp.cdb and b/cpld/db/GR8RAM.ace_cmp.cdb differ diff --git a/cpld/db/GR8RAM.ace_cmp.hdb b/cpld/db/GR8RAM.ace_cmp.hdb index e19621b..291e9e6 100755 Binary files a/cpld/db/GR8RAM.ace_cmp.hdb and b/cpld/db/GR8RAM.ace_cmp.hdb differ diff --git a/cpld/db/GR8RAM.asm.qmsg b/cpld/db/GR8RAM.asm.qmsg index 8ecd4f7..06f5488 100755 --- a/cpld/db/GR8RAM.asm.qmsg +++ b/cpld/db/GR8RAM.asm.qmsg @@ -1,6 +1,6 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618911782409 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618911782409 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 05:43:02 2021 " "Processing started: Tue Apr 20 05:43:02 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618911782409 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1618911782409 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1618911782409 ""} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1618911783535 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1618911783550 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "293 " "Peak virtual memory: 293 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618911784113 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 05:43:04 2021 " "Processing ended: Tue Apr 20 05:43:04 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618911784113 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618911784113 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618911784113 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1618911784113 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618906796813 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618906796829 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 04:19:56 2021 " "Processing started: Tue Apr 20 04:19:56 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618906796829 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1618906796829 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1618906796829 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1618906798235 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1618906798282 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "293 " "Peak virtual memory: 293 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618906799032 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 04:19:59 2021 " "Processing ended: Tue Apr 20 04:19:59 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618906799032 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618906799032 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618906799032 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1618906799032 ""} diff --git a/cpld/db/GR8RAM.asm.rdb b/cpld/db/GR8RAM.asm.rdb index c520216..2dcb4e1 100755 Binary files a/cpld/db/GR8RAM.asm.rdb and b/cpld/db/GR8RAM.asm.rdb differ diff --git a/cpld/db/GR8RAM.asm_labs.ddb b/cpld/db/GR8RAM.asm_labs.ddb index 0706045..8480148 100755 Binary files a/cpld/db/GR8RAM.asm_labs.ddb and b/cpld/db/GR8RAM.asm_labs.ddb differ diff --git a/cpld/db/GR8RAM.cmp.cdb b/cpld/db/GR8RAM.cmp.cdb index 43918f3..f41e376 100755 Binary files a/cpld/db/GR8RAM.cmp.cdb and b/cpld/db/GR8RAM.cmp.cdb differ diff --git a/cpld/db/GR8RAM.cmp.hdb b/cpld/db/GR8RAM.cmp.hdb index f6f056a..70fb348 100755 Binary files a/cpld/db/GR8RAM.cmp.hdb and b/cpld/db/GR8RAM.cmp.hdb differ diff --git a/cpld/db/GR8RAM.cmp.idb b/cpld/db/GR8RAM.cmp.idb index 53c2ad4..0379a24 100755 Binary files a/cpld/db/GR8RAM.cmp.idb and b/cpld/db/GR8RAM.cmp.idb differ diff --git a/cpld/db/GR8RAM.cmp.rdb b/cpld/db/GR8RAM.cmp.rdb index daab313..096f455 100755 Binary files a/cpld/db/GR8RAM.cmp.rdb and b/cpld/db/GR8RAM.cmp.rdb differ diff --git a/cpld/db/GR8RAM.cmp0.ddb b/cpld/db/GR8RAM.cmp0.ddb index 1ea12ac..443cfd1 100755 Binary files a/cpld/db/GR8RAM.cmp0.ddb and b/cpld/db/GR8RAM.cmp0.ddb differ diff --git a/cpld/db/GR8RAM.db_info b/cpld/db/GR8RAM.db_info index 98c80ef..0197121 100755 --- a/cpld/db/GR8RAM.db_info +++ b/cpld/db/GR8RAM.db_info @@ -1,3 +1,3 @@ Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition Version_Index = 302049280 -Creation_Time = Tue Apr 20 05:31:27 2021 +Creation_Time = Mon Apr 19 05:50:25 2021 diff --git a/cpld/db/GR8RAM.eco.cdb b/cpld/db/GR8RAM.eco.cdb index 6329ccc..bb73074 100755 Binary files a/cpld/db/GR8RAM.eco.cdb and b/cpld/db/GR8RAM.eco.cdb differ diff --git a/cpld/db/GR8RAM.fit.qmsg b/cpld/db/GR8RAM.fit.qmsg index ff0b3ec..5e214cc 100755 --- a/cpld/db/GR8RAM.fit.qmsg +++ b/cpld/db/GR8RAM.fit.qmsg @@ -1,42 +1,39 @@ -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1618911772581 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1618911772612 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618911773628 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618911773628 ""} -{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1618911773862 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1618911773878 ""} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618911774175 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618911774175 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618911774175 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618911774175 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618911774175 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1618911774175 ""} -{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "1 80 " "No exact pin location assignment(s) for 1 pins of 80 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[9\] " "Pin SA\[9\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[9] } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "SA\[9\]" } } } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 436 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 258 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1618911774206 ""} } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1618911774206 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1618911774346 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1618911774346 ""} -{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1618911774362 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1618911774362 ""} -{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618911774362 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618911774362 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 C25M " " 1.000 C25M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618911774362 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI0 " " 1.000 PHI0" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618911774362 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1618911774362 ""} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618911774378 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618911774378 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618911774378 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618911774393 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI0 Global clock " "Automatically promoted some destinations of signal \"PHI0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~1 " "Destination \"comb~1\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618911774393 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI0r1 " "Destination \"PHI0r1\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618911774393 ""} } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618911774393 ""} -{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI0 " "Pin \"PHI0\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI0 } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "PHI0" } } } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 461 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1618911774393 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "nRESr Global clock " "Automatically promoted signal \"nRESr\" to use Global clock" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 16 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618911774393 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618911774393 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1618911774393 ""} -{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1618911774425 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1618911774487 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1618911774487 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1618911774487 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1618911774487 ""} -{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "1 unused 3.3V 0 1 0 " "Number of I/O pins in group: 1 (unused VREF, 3.3V VCCIO, 0 input, 1 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "I/O standards used: 3.3-V LVTTL." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1618911774503 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1618911774503 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1618911774503 ""} -{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.3V 38 0 " "I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 38 total pin(s) used -- 0 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1618911774503 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use 3.3V 41 1 " "I/O bank number 2 does not use VREF pins and has 3.3V VCCIO pins. 41 total pin(s) used -- 1 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1618911774503 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1618911774503 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1618911774503 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618911774534 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1618911774971 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618911775409 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1618911775425 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1618911777237 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:02 " "Fitter placement operations ending: elapsed time is 00:00:02" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618911777237 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1618911777315 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "35 " "Router estimated average interconnect usage is 35% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "35 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 35% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 35% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 35% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1618911778081 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1618911778081 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618911778878 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.70 " "Total time spent on timing analysis during the Fitter is 0.70 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1618911778894 ""} -{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618911778894 ""} -{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1618911778925 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1618911779222 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "378 " "Peak virtual memory: 378 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618911779472 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 05:42:59 2021 " "Processing ended: Tue Apr 20 05:42:59 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618911779472 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618911779472 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:09 " "Total CPU time (on all processors): 00:00:09" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618911779472 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1618911779472 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1618906787984 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1618906788015 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618906788219 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618906788219 ""} +{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1618906788531 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1618906788562 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618906788906 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618906788906 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618906788906 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618906788906 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618906788906 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1618906788906 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1618906789062 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1618906789062 ""} +{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1618906789078 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1618906789078 ""} +{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618906789078 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618906789078 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 C25M " " 1.000 C25M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618906789078 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI0 " " 1.000 PHI0" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618906789078 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1618906789078 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618906789094 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618906789094 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618906789094 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618906789125 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI0 Global clock " "Automatically promoted some destinations of signal \"PHI0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~1 " "Destination \"comb~1\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618906789140 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI0r1 " "Destination \"PHI0r1\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618906789140 ""} } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618906789140 ""} +{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI0 " "Pin \"PHI0\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI0 } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "PHI0" } } } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 379 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1618906789140 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "nRESr Global clock " "Automatically promoted signal \"nRESr\" to use Global clock" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 16 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618906789140 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618906789140 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1618906789140 ""} +{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1618906789203 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1618906789265 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1618906789265 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1618906789281 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1618906789281 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618906789328 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1618906789531 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618906790203 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1618906790234 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1618906791859 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:02 " "Fitter placement operations ending: elapsed time is 00:00:02" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618906791859 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1618906791922 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "36 " "Router estimated average interconnect usage is 36% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "36 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 36% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 36% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 36% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1618906792469 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1618906792469 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618906793250 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.56 " "Total time spent on timing analysis during the Fitter is 0.56 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1618906793281 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618906793281 ""} +{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1618906793344 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1618906793750 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "382 " "Peak virtual memory: 382 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618906794016 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 04:19:53 2021 " "Processing ended: Tue Apr 20 04:19:53 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618906794016 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618906794016 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618906794016 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1618906794016 ""} diff --git a/cpld/db/GR8RAM.map.cdb b/cpld/db/GR8RAM.map.cdb index df86f9a..e81467b 100755 Binary files a/cpld/db/GR8RAM.map.cdb and b/cpld/db/GR8RAM.map.cdb differ diff --git a/cpld/db/GR8RAM.map.hdb b/cpld/db/GR8RAM.map.hdb index 77a5183..cbc9472 100755 Binary files a/cpld/db/GR8RAM.map.hdb and b/cpld/db/GR8RAM.map.hdb differ diff --git a/cpld/db/GR8RAM.map.qmsg b/cpld/db/GR8RAM.map.qmsg index 7dbfb1b..3b9d01c 100755 --- a/cpld/db/GR8RAM.map.qmsg +++ b/cpld/db/GR8RAM.map.qmsg @@ -1,19 +1,19 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618911761846 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618911761861 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 05:42:41 2021 " "Processing started: Tue Apr 20 05:42:41 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618911761861 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618911761861 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618911761861 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1618911764424 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(106) " "Verilog HDL warning at GR8RAM.v(106): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 106 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618911764830 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(282) " "Verilog HDL warning at GR8RAM.v(282): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 282 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618911764846 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1618911764846 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1618911764846 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1618911764971 ""} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(42) " "Verilog HDL assignment warning at GR8RAM.v(42): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 42 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618911764986 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(47) " "Verilog HDL assignment warning at GR8RAM.v(47): truncated value with size 32 to match size of target (14)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 47 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618911764986 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(130) " "Verilog HDL assignment warning at GR8RAM.v(130): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 130 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618911764986 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(138) " "Verilog HDL assignment warning at GR8RAM.v(138): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 138 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618911764986 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(145) " "Verilog HDL assignment warning at GR8RAM.v(145): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 145 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618911764986 "|GR8RAM"} -{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 -1 1618911766190 ""} -{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "nNMIout VCC " "Pin \"nNMIout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 553 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618911766533 "|GR8RAM|nNMIout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nIRQout VCC " "Pin \"nIRQout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 556 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618911766533 "|GR8RAM|nIRQout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nRDYout VCC " "Pin \"nRDYout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 555 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618911766533 "|GR8RAM|nRDYout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nINHout VCC " "Pin \"nINHout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 554 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618911766533 "|GR8RAM|nINHout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RWout VCC " "Pin \"RWout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 557 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618911766533 "|GR8RAM|RWout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nDMAout VCC " "Pin \"nDMAout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 552 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618911766533 "|GR8RAM|nDMAout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 551 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618911766533 "|GR8RAM|RAdir"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1618911766533 ""} -{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1618911767158 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "321 " "Implemented 321 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "28 " "Implemented 28 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1618911767237 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1618911767237 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1618911767237 ""} { "Info" "ICUT_CUT_TM_LCELLS" "241 " "Implemented 241 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1618911767237 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1618911767237 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1618911767596 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 13 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 13 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "301 " "Peak virtual memory: 301 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618911767799 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 05:42:47 2021 " "Processing ended: Tue Apr 20 05:42:47 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618911767799 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618911767799 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618911767799 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618911767799 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618906780187 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618906780202 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 04:19:39 2021 " "Processing started: Tue Apr 20 04:19:39 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618906780202 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618906780202 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618906780202 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1618906781718 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(106) " "Verilog HDL warning at GR8RAM.v(106): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 106 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618906781890 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(282) " "Verilog HDL warning at GR8RAM.v(282): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 282 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618906781890 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1618906781905 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1618906781905 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1618906782030 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(42) " "Verilog HDL assignment warning at GR8RAM.v(42): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 42 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618906782062 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(47) " "Verilog HDL assignment warning at GR8RAM.v(47): truncated value with size 32 to match size of target (14)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 47 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618906782062 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(130) " "Verilog HDL assignment warning at GR8RAM.v(130): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 130 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618906782062 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(138) " "Verilog HDL assignment warning at GR8RAM.v(138): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 138 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618906782062 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(145) " "Verilog HDL assignment warning at GR8RAM.v(145): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 145 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618906782062 "|GR8RAM"} +{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 -1 1618906783140 ""} +{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "nNMIout VCC " "Pin \"nNMIout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 553 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618906783406 "|GR8RAM|nNMIout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nIRQout VCC " "Pin \"nIRQout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 556 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618906783406 "|GR8RAM|nIRQout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nRDYout VCC " "Pin \"nRDYout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 555 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618906783406 "|GR8RAM|nRDYout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nINHout VCC " "Pin \"nINHout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 554 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618906783406 "|GR8RAM|nINHout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RWout VCC " "Pin \"RWout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 557 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618906783406 "|GR8RAM|RWout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nDMAout VCC " "Pin \"nDMAout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 552 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618906783406 "|GR8RAM|nDMAout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 551 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618906783406 "|GR8RAM|RAdir"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1618906783406 ""} +{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1618906783906 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "321 " "Implemented 321 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "28 " "Implemented 28 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1618906783968 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1618906783968 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1618906783968 ""} { "Info" "ICUT_CUT_TM_LCELLS" "241 " "Implemented 241 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1618906783968 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1618906783968 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1618906784124 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 13 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 13 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "301 " "Peak virtual memory: 301 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618906784281 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 04:19:44 2021 " "Processing ended: Tue Apr 20 04:19:44 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618906784281 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618906784281 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618906784281 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618906784281 ""} diff --git a/cpld/db/GR8RAM.map.rdb b/cpld/db/GR8RAM.map.rdb index 9e695bf..470a060 100755 Binary files a/cpld/db/GR8RAM.map.rdb and b/cpld/db/GR8RAM.map.rdb differ diff --git a/cpld/db/GR8RAM.pplq.rdb b/cpld/db/GR8RAM.pplq.rdb index 6619eee..723fcab 100755 Binary files a/cpld/db/GR8RAM.pplq.rdb and b/cpld/db/GR8RAM.pplq.rdb differ diff --git a/cpld/db/GR8RAM.pre_map.hdb b/cpld/db/GR8RAM.pre_map.hdb index a8e47b9..f432588 100755 Binary files a/cpld/db/GR8RAM.pre_map.hdb and b/cpld/db/GR8RAM.pre_map.hdb differ diff --git a/cpld/db/GR8RAM.root_partition.map.reg_db.cdb b/cpld/db/GR8RAM.root_partition.map.reg_db.cdb index e025fb8..01bfaa7 100755 Binary files a/cpld/db/GR8RAM.root_partition.map.reg_db.cdb and b/cpld/db/GR8RAM.root_partition.map.reg_db.cdb differ diff --git a/cpld/db/GR8RAM.routing.rdb b/cpld/db/GR8RAM.routing.rdb index 393a254..7b34f68 100755 Binary files a/cpld/db/GR8RAM.routing.rdb and b/cpld/db/GR8RAM.routing.rdb differ diff --git a/cpld/db/GR8RAM.rtlv.hdb b/cpld/db/GR8RAM.rtlv.hdb index be040ca..a6820cf 100755 Binary files a/cpld/db/GR8RAM.rtlv.hdb and b/cpld/db/GR8RAM.rtlv.hdb differ diff --git a/cpld/db/GR8RAM.rtlv_sg.cdb b/cpld/db/GR8RAM.rtlv_sg.cdb index 7731e08..272dde8 100755 Binary files a/cpld/db/GR8RAM.rtlv_sg.cdb and b/cpld/db/GR8RAM.rtlv_sg.cdb differ diff --git a/cpld/db/GR8RAM.sgdiff.cdb b/cpld/db/GR8RAM.sgdiff.cdb index 0be880c..7d0bd18 100755 Binary files a/cpld/db/GR8RAM.sgdiff.cdb and b/cpld/db/GR8RAM.sgdiff.cdb differ diff --git a/cpld/db/GR8RAM.sgdiff.hdb b/cpld/db/GR8RAM.sgdiff.hdb index 50042a9..58f1cf6 100755 Binary files a/cpld/db/GR8RAM.sgdiff.hdb and b/cpld/db/GR8RAM.sgdiff.hdb differ diff --git a/cpld/db/GR8RAM.sta.qmsg b/cpld/db/GR8RAM.sta.qmsg index 81a345b..38a0971 100755 --- a/cpld/db/GR8RAM.sta.qmsg +++ b/cpld/db/GR8RAM.sta.qmsg @@ -1,23 +1,23 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618911786832 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618911786847 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 05:43:05 2021 " "Processing started: Tue Apr 20 05:43:05 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618911786847 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618911786847 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618911786847 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1618911787035 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1618911787925 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618911788097 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618911788097 ""} -{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1618911788269 ""} -{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1618911788722 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1618911788863 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1618911788863 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C25M C25M " "create_clock -period 1.000 -name C25M C25M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618911788879 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI0 PHI0 " "create_clock -period 1.000 -name PHI0 PHI0" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618911788879 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618911788879 ""} -{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1618911788894 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1618911789019 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -9.844 " "Worst-case setup slack is -9.844" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911789050 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911789050 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.844 -724.767 C25M " " -9.844 -724.767 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911789050 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.019 -0.019 PHI0 " " -0.019 -0.019 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911789050 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618911789050 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.952 " "Worst-case hold slack is -0.952" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911789066 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911789066 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.952 -0.952 PHI0 " " -0.952 -0.952 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911789066 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.385 0.000 C25M " " 1.385 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911789066 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618911789066 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -4.389 " "Worst-case recovery slack is -4.389" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911789082 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911789082 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.389 -127.281 C25M " " -4.389 -127.281 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911789082 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618911789082 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "removal 4.835 " "Worst-case removal slack is 4.835" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911789082 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911789082 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.835 0.000 C25M " " 4.835 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911789082 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618911789082 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911789097 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911789097 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -3.000 PHI0 " " -3.000 -3.000 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911789097 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 C25M " " -2.289 -2.289 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911789097 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618911789097 ""} -{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1618911789300 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618911789472 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618911789472 ""} -{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "275 " "Peak virtual memory: 275 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618911789722 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 05:43:09 2021 " "Processing ended: Tue Apr 20 05:43:09 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618911789722 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618911789722 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618911789722 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618911789722 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618906802095 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618906802110 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 04:20:00 2021 " "Processing started: Tue Apr 20 04:20:00 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618906802110 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618906802110 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618906802110 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1618906802314 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1618906803173 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618906803329 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618906803329 ""} +{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1618906803517 ""} +{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1618906804204 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1618906804392 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1618906804407 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C25M C25M " "create_clock -period 1.000 -name C25M C25M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804407 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI0 PHI0 " "create_clock -period 1.000 -name PHI0 PHI0" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804407 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804407 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1618906804423 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1618906804595 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -9.005 " "Worst-case setup slack is -9.005" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804611 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804611 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.005 -699.357 C25M " " -9.005 -699.357 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804611 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.425 -0.425 PHI0 " " -0.425 -0.425 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804611 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618906804611 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.248 " "Worst-case hold slack is -0.248" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804642 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804642 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.248 -0.248 PHI0 " " -0.248 -0.248 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804642 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.400 0.000 C25M " " 1.400 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804642 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618906804642 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -4.412 " "Worst-case recovery slack is -4.412" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804657 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804657 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.412 -127.948 C25M " " -4.412 -127.948 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804657 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618906804657 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "removal 4.858 " "Worst-case removal slack is 4.858" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804673 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804673 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.858 0.000 C25M " " 4.858 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804673 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618906804673 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.289 " "Worst-case minimum pulse width slack is -2.289" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804673 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804673 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 C25M " " -2.289 -2.289 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804673 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI0 " " -2.289 -2.289 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804673 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618906804673 ""} +{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1618906804876 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618906804986 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618906804986 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "278 " "Peak virtual memory: 278 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618906805220 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 04:20:05 2021 " "Processing ended: Tue Apr 20 04:20:05 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618906805220 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618906805220 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618906805220 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618906805220 ""} diff --git a/cpld/db/GR8RAM.sta.rdb b/cpld/db/GR8RAM.sta.rdb index 70a705b..3578a35 100755 Binary files a/cpld/db/GR8RAM.sta.rdb and b/cpld/db/GR8RAM.sta.rdb differ diff --git a/cpld/db/GR8RAM.sta_cmp.5_slow.tdb b/cpld/db/GR8RAM.sta_cmp.5_slow.tdb index 5cafcc1..905feea 100755 Binary files a/cpld/db/GR8RAM.sta_cmp.5_slow.tdb and b/cpld/db/GR8RAM.sta_cmp.5_slow.tdb differ diff --git a/cpld/db/GR8RAM.tmw_info b/cpld/db/GR8RAM.tmw_info index 726ca6c..51a8f52 100755 --- a/cpld/db/GR8RAM.tmw_info +++ b/cpld/db/GR8RAM.tmw_info @@ -1,6 +1,6 @@ -start_full_compilation:s:00:00:32 -start_analysis_synthesis:s:00:00:10-start_full_compilation +start_full_compilation:s:00:00:28 +start_analysis_synthesis:s:00:00:07-start_full_compilation start_analysis_elaboration:s-start_full_compilation -start_fitter:s:00:00:12-start_full_compilation +start_fitter:s:00:00:10-start_full_compilation start_assembler:s:00:00:04-start_full_compilation -start_timing_analyzer:s:00:00:06-start_full_compilation +start_timing_analyzer:s:00:00:07-start_full_compilation diff --git a/cpld/db/GR8RAM.vpr.ammdb b/cpld/db/GR8RAM.vpr.ammdb index 8e5e905..c0ccc6d 100755 Binary files a/cpld/db/GR8RAM.vpr.ammdb and b/cpld/db/GR8RAM.vpr.ammdb differ diff --git a/cpld/db/prev_cmp_GR8RAM.qmsg b/cpld/db/prev_cmp_GR8RAM.qmsg index 8ed7016..857f1ce 100755 --- a/cpld/db/prev_cmp_GR8RAM.qmsg +++ b/cpld/db/prev_cmp_GR8RAM.qmsg @@ -1,98 +1,95 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618911181095 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618911181095 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 05:33:00 2021 " "Processing started: Tue Apr 20 05:33:00 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618911181095 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618911181095 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618911181095 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1618911183252 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(106) " "Verilog HDL warning at GR8RAM.v(106): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 106 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618911183548 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(282) " "Verilog HDL warning at GR8RAM.v(282): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 282 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618911183564 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1618911183564 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1618911183564 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1618911183673 ""} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(42) " "Verilog HDL assignment warning at GR8RAM.v(42): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 42 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618911183689 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(47) " "Verilog HDL assignment warning at GR8RAM.v(47): truncated value with size 32 to match size of target (14)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 47 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618911183689 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(130) " "Verilog HDL assignment warning at GR8RAM.v(130): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 130 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618911183689 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(138) " "Verilog HDL assignment warning at GR8RAM.v(138): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 138 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618911183689 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(145) " "Verilog HDL assignment warning at GR8RAM.v(145): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 145 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618911183689 "|GR8RAM"} -{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 -1 1618911185064 ""} -{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "nNMIout VCC " "Pin \"nNMIout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 553 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618911185455 "|GR8RAM|nNMIout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nIRQout VCC " "Pin \"nIRQout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 556 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618911185455 "|GR8RAM|nIRQout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nRDYout VCC " "Pin \"nRDYout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 555 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618911185455 "|GR8RAM|nRDYout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nINHout VCC " "Pin \"nINHout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 554 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618911185455 "|GR8RAM|nINHout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RWout VCC " "Pin \"RWout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 557 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618911185455 "|GR8RAM|RWout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nDMAout VCC " "Pin \"nDMAout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 552 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618911185455 "|GR8RAM|nDMAout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 551 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618911185455 "|GR8RAM|RAdir"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1618911185455 ""} -{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1618911185861 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "321 " "Implemented 321 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "28 " "Implemented 28 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1618911185908 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1618911185908 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1618911185908 ""} { "Info" "ICUT_CUT_TM_LCELLS" "241 " "Implemented 241 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1618911185908 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1618911185908 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1618911186236 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 13 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 13 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "314 " "Peak virtual memory: 314 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618911186423 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 05:33:06 2021 " "Processing ended: Tue Apr 20 05:33:06 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618911186423 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618911186423 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618911186423 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618911186423 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618911189470 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 32-bit " "Running Quartus II 32-bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618911189486 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 05:33:08 2021 " "Processing started: Tue Apr 20 05:33:08 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618911189486 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1618911189486 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1618911189486 ""} -{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1618911189689 ""} -{ "Info" "0" "" "Project = GR8RAM" { } { } 0 0 "Project = GR8RAM" 0 0 "Fitter" 0 0 1618911189689 ""} -{ "Info" "0" "" "Revision = GR8RAM" { } { } 0 0 "Revision = GR8RAM" 0 0 "Fitter" 0 0 1618911189689 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1618911190392 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1618911190408 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618911191501 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618911191501 ""} -{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1618911192033 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1618911192048 ""} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618911192470 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618911192470 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618911192470 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618911192470 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618911192470 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1618911192470 ""} -{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "1 80 " "No exact pin location assignment(s) for 1 pins of 80 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[9\] " "Pin SA\[9\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[9] } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "SA\[9\]" } } } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 436 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 258 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1618911192486 ""} } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1618911192486 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1618911192642 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1618911192642 ""} -{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1618911192642 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1618911192642 ""} -{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618911192658 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618911192658 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 C25M " " 1.000 C25M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618911192658 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI0 " " 1.000 PHI0" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618911192658 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1618911192658 ""} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618911192658 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618911192658 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618911192658 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618911192689 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI0 Global clock " "Automatically promoted some destinations of signal \"PHI0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~1 " "Destination \"comb~1\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618911192689 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI0r1 " "Destination \"PHI0r1\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618911192689 ""} } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618911192689 ""} -{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI0 " "Pin \"PHI0\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI0 } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "PHI0" } } } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 461 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1618911192689 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "nRESr Global clock " "Automatically promoted signal \"nRESr\" to use Global clock" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 16 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618911192689 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618911192689 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1618911192705 ""} -{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1618911192751 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1618911192845 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1618911192861 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1618911192861 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1618911192861 ""} -{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "1 unused 3.3V 0 1 0 " "Number of I/O pins in group: 1 (unused VREF, 3.3V VCCIO, 0 input, 1 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "I/O standards used: 3.3-V LVTTL." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1618911192876 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1618911192876 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1618911192876 ""} -{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.3V 38 0 " "I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 38 total pin(s) used -- 0 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1618911192892 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use 3.3V 41 1 " "I/O bank number 2 does not use VREF pins and has 3.3V VCCIO pins. 41 total pin(s) used -- 1 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1618911192892 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1618911192892 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1618911192892 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618911192923 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1618911193251 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618911193611 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1618911193626 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1618911195095 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618911195095 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1618911195142 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "35 " "Router estimated average interconnect usage is 35% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "35 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 35% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 35% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 35% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1618911195579 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1618911195579 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618911196642 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.53 " "Total time spent on timing analysis during the Fitter is 0.53 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1618911196673 ""} -{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618911196673 ""} -{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1618911196689 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1618911196986 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "382 " "Peak virtual memory: 382 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618911197283 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 05:33:17 2021 " "Processing ended: Tue Apr 20 05:33:17 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618911197283 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618911197283 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:09 " "Total CPU time (on all processors): 00:00:09" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618911197283 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1618911197283 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1618911200033 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618911200048 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 05:33:19 2021 " "Processing started: Tue Apr 20 05:33:19 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618911200048 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1618911200048 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1618911200048 ""} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1618911201251 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1618911201283 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "293 " "Peak virtual memory: 293 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618911201876 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 05:33:21 2021 " "Processing ended: Tue Apr 20 05:33:21 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618911201876 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618911201876 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618911201876 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1618911201876 ""} -{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1618911202783 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1618911204829 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618911204829 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 05:33:23 2021 " "Processing started: Tue Apr 20 05:33:23 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618911204829 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618911204829 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618911204829 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1618911205001 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1618911205939 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618911206126 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618911206126 ""} -{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1618911206376 ""} -{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1618911206923 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1618911207126 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1618911207142 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C25M C25M " "create_clock -period 1.000 -name C25M C25M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618911207158 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI0 PHI0 " "create_clock -period 1.000 -name PHI0 PHI0" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618911207158 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618911207158 ""} -{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1618911207173 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1618911207298 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -9.419 " "Worst-case setup slack is -9.419" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911207329 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911207329 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.419 -693.423 C25M " " -9.419 -693.423 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911207329 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.996 -0.996 PHI0 " " -0.996 -0.996 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911207329 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618911207329 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.373 " "Worst-case hold slack is -0.373" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911207345 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911207345 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.373 -0.373 PHI0 " " -0.373 -0.373 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911207345 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.394 0.000 C25M " " 1.394 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911207345 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618911207345 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -4.404 " "Worst-case recovery slack is -4.404" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911207376 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911207376 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.404 -127.716 C25M " " -4.404 -127.716 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911207376 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618911207376 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "removal 4.850 " "Worst-case removal slack is 4.850" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911207376 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911207376 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.850 0.000 C25M " " 4.850 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911207376 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618911207376 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.289 " "Worst-case minimum pulse width slack is -2.289" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911207392 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911207392 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 C25M " " -2.289 -2.289 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911207392 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI0 " " -2.289 -2.289 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911207392 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618911207392 ""} -{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1618911207642 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618911207783 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618911207783 ""} -{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "278 " "Peak virtual memory: 278 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618911208095 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 05:33:28 2021 " "Processing ended: Tue Apr 20 05:33:28 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618911208095 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618911208095 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618911208095 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618911208095 ""} -{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 19 s " "Quartus II Full Compilation was successful. 0 errors, 19 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618911209392 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618906713072 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618906713088 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 04:18:32 2021 " "Processing started: Tue Apr 20 04:18:32 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618906713088 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618906713088 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618906713088 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1618906714666 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(106) " "Verilog HDL warning at GR8RAM.v(106): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 106 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618906714838 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(282) " "Verilog HDL warning at GR8RAM.v(282): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 282 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618906714854 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1618906714854 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1618906714854 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1618906714979 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(42) " "Verilog HDL assignment warning at GR8RAM.v(42): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 42 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618906714979 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(47) " "Verilog HDL assignment warning at GR8RAM.v(47): truncated value with size 32 to match size of target (14)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 47 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618906714979 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(130) " "Verilog HDL assignment warning at GR8RAM.v(130): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 130 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618906714979 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(138) " "Verilog HDL assignment warning at GR8RAM.v(138): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 138 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618906714979 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(145) " "Verilog HDL assignment warning at GR8RAM.v(145): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 145 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618906714994 "|GR8RAM"} +{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 -1 1618906716541 ""} +{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "nNMIout VCC " "Pin \"nNMIout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 553 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618906716822 "|GR8RAM|nNMIout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nIRQout VCC " "Pin \"nIRQout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 556 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618906716822 "|GR8RAM|nIRQout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nRDYout VCC " "Pin \"nRDYout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 555 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618906716822 "|GR8RAM|nRDYout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nINHout VCC " "Pin \"nINHout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 554 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618906716822 "|GR8RAM|nINHout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RWout VCC " "Pin \"RWout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 557 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618906716822 "|GR8RAM|RWout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nDMAout VCC " "Pin \"nDMAout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 552 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618906716822 "|GR8RAM|nDMAout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 551 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618906716822 "|GR8RAM|RAdir"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1618906716822 ""} +{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1618906717276 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "321 " "Implemented 321 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "28 " "Implemented 28 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1618906717307 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1618906717307 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1618906717307 ""} { "Info" "ICUT_CUT_TM_LCELLS" "241 " "Implemented 241 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1618906717307 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1618906717307 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1618906717510 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 13 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 13 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "301 " "Peak virtual memory: 301 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618906717666 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 04:18:37 2021 " "Processing ended: Tue Apr 20 04:18:37 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618906717666 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618906717666 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618906717666 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618906717666 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618906720682 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 32-bit " "Running Quartus II 32-bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618906720698 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 04:18:39 2021 " "Processing started: Tue Apr 20 04:18:39 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618906720698 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1618906720698 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1618906720698 ""} +{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1618906720885 ""} +{ "Info" "0" "" "Project = GR8RAM" { } { } 0 0 "Project = GR8RAM" 0 0 "Fitter" 0 0 1618906720885 ""} +{ "Info" "0" "" "Revision = GR8RAM" { } { } 0 0 "Revision = GR8RAM" 0 0 "Fitter" 0 0 1618906720885 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1618906721651 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1618906721682 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618906721948 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618906721948 ""} +{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1618906722260 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1618906722307 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618906722666 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618906722666 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618906722666 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618906722666 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618906722666 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1618906722666 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1618906722838 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1618906722854 ""} +{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1618906722885 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1618906722885 ""} +{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618906722932 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618906722932 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 C25M " " 1.000 C25M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618906722932 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI0 " " 1.000 PHI0" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618906722932 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1618906722932 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618906722932 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618906722948 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618906722948 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618906722979 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI0 Global clock " "Automatically promoted some destinations of signal \"PHI0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~1 " "Destination \"comb~1\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618906722979 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI0r1 " "Destination \"PHI0r1\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618906722979 ""} } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618906722979 ""} +{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI0 " "Pin \"PHI0\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI0 } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "PHI0" } } } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 380 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1618906722979 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "nRESr Global clock " "Automatically promoted signal \"nRESr\" to use Global clock" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 16 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618906722995 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618906722995 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1618906722995 ""} +{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1618906723026 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1618906723073 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1618906723088 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1618906723088 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1618906723088 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618906723135 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1618906723307 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618906723667 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1618906723682 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1618906725120 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618906725135 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1618906725214 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "36 " "Router estimated average interconnect usage is 36% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "36 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 36% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 36% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 36% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1618906725682 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1618906725682 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618906726260 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.67 " "Total time spent on timing analysis during the Fitter is 0.67 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1618906726276 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618906726276 ""} +{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1618906726307 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1618906726589 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "382 " "Peak virtual memory: 382 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618906726823 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 04:18:46 2021 " "Processing ended: Tue Apr 20 04:18:46 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618906726823 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618906726823 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618906726823 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1618906726823 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1618906729714 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618906729714 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 04:18:49 2021 " "Processing started: Tue Apr 20 04:18:49 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618906729714 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1618906729714 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1618906729714 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1618906730948 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1618906730979 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "293 " "Peak virtual memory: 293 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618906731745 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 04:18:51 2021 " "Processing ended: Tue Apr 20 04:18:51 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618906731745 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618906731745 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618906731745 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1618906731745 ""} +{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1618906732667 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1618906734839 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618906734839 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 04:18:53 2021 " "Processing started: Tue Apr 20 04:18:53 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618906734839 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618906734839 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618906734839 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1618906735042 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1618906735948 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618906736105 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618906736105 ""} +{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1618906736308 ""} +{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1618906737074 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1618906737308 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1618906737308 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C25M C25M " "create_clock -period 1.000 -name C25M C25M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737308 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI0 PHI0 " "create_clock -period 1.000 -name PHI0 PHI0" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737308 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737308 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1618906737324 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1618906737495 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -9.005 " "Worst-case setup slack is -9.005" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737495 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737495 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.005 -699.357 C25M " " -9.005 -699.357 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737495 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.425 -0.425 PHI0 " " -0.425 -0.425 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737495 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618906737495 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.248 " "Worst-case hold slack is -0.248" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737527 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737527 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.248 -0.248 PHI0 " " -0.248 -0.248 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737527 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.400 0.000 C25M " " 1.400 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737527 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618906737527 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -4.412 " "Worst-case recovery slack is -4.412" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737542 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737542 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.412 -127.948 C25M " " -4.412 -127.948 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737542 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618906737542 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "removal 4.858 " "Worst-case removal slack is 4.858" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737558 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737558 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.858 0.000 C25M " " 4.858 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737558 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618906737558 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.289 " "Worst-case minimum pulse width slack is -2.289" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737589 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737589 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 C25M " " -2.289 -2.289 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737589 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI0 " " -2.289 -2.289 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737589 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618906737589 ""} +{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1618906738136 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618906738246 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618906738246 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "278 " "Peak virtual memory: 278 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618906738496 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 04:18:58 2021 " "Processing ended: Tue Apr 20 04:18:58 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618906738496 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618906738496 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618906738496 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618906738496 ""} +{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 18 s " "Quartus II Full Compilation was successful. 0 errors, 18 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618906739949 ""} diff --git a/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt b/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt index 001087f..0798033 100755 Binary files a/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt and b/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt differ diff --git a/cpld/output_files/GR8RAM.asm.rpt b/cpld/output_files/GR8RAM.asm.rpt index 5c5542b..609cd3a 100755 --- a/cpld/output_files/GR8RAM.asm.rpt +++ b/cpld/output_files/GR8RAM.asm.rpt @@ -1,5 +1,5 @@ Assembler report for GR8RAM -Tue Apr 20 05:43:03 2021 +Tue Apr 20 04:19:58 2021 Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition @@ -37,7 +37,7 @@ applicable agreement for further details. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Tue Apr 20 05:43:03 2021 ; +; Assembler Status ; Successful - Tue Apr 20 04:19:58 2021 ; ; Revision Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ; ; Family ; MAX II ; @@ -90,8 +90,8 @@ applicable agreement for further details. ; Option ; Setting ; +----------------+-------------------------------------------------------+ ; Device ; EPM240T100C5 ; -; JTAG usercode ; 0x0016305B ; -; Checksum ; 0x001633DB ; +; JTAG usercode ; 0x001644CE ; +; Checksum ; 0x0016484E ; +----------------+-------------------------------------------------------+ @@ -101,14 +101,14 @@ applicable agreement for further details. Info: ******************************************************************* Info: Running Quartus II 32-bit Assembler Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - Info: Processing started: Tue Apr 20 05:43:02 2021 + Info: Processing started: Tue Apr 20 04:19:56 2021 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM Info (115031): Writing out detailed assembly data for power analysis Info (115030): Assembler is generating device programming files Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings Info: Peak virtual memory: 293 megabytes - Info: Processing ended: Tue Apr 20 05:43:04 2021 - Info: Elapsed time: 00:00:02 + Info: Processing ended: Tue Apr 20 04:19:59 2021 + Info: Elapsed time: 00:00:03 Info: Total CPU time (on all processors): 00:00:02 diff --git a/cpld/output_files/GR8RAM.done b/cpld/output_files/GR8RAM.done index 511a66a..7c4faa1 100755 --- a/cpld/output_files/GR8RAM.done +++ b/cpld/output_files/GR8RAM.done @@ -1 +1 @@ -Tue Apr 20 05:43:10 2021 +Tue Apr 20 04:20:06 2021 diff --git a/cpld/output_files/GR8RAM.fit.rpt b/cpld/output_files/GR8RAM.fit.rpt index 20da58c..b4be352 100755 --- a/cpld/output_files/GR8RAM.fit.rpt +++ b/cpld/output_files/GR8RAM.fit.rpt @@ -1,5 +1,5 @@ Fitter report for GR8RAM -Tue Apr 20 05:42:59 2021 +Tue Apr 20 04:19:53 2021 Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition @@ -57,7 +57,7 @@ applicable agreement for further details. +-----------------------------------------------------------------------------+ ; Fitter Summary ; +---------------------------+-------------------------------------------------+ -; Fitter Status ; Successful - Tue Apr 20 05:42:59 2021 ; +; Fitter Status ; Successful - Tue Apr 20 04:19:53 2021 ; ; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; ; Revision Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ; @@ -128,12 +128,12 @@ applicable agreement for further details. ; Number detected on machine ; 2 ; ; Maximum allowed ; 2 ; ; ; ; -; Average used ; 1.50 ; +; Average used ; 1.20 ; ; Maximum used ; 2 ; ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; -; Processor 2 ; 50.0% ; +; Processor 2 ; 20.0% ; +----------------------------+-------------+ @@ -179,8 +179,8 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin. ; UFM blocks ; 0 / 1 ( 0 % ) ; ; Global clocks ; 3 / 4 ( 75 % ) ; ; JTAGs ; 0 / 1 ( 0 % ) ; -; Average interconnect usage (total/H/V) ; 45% / 50% / 40% ; -; Peak interconnect usage (total/H/V) ; 45% / 50% / 40% ; +; Average interconnect usage (total/H/V) ; 44% / 49% / 38% ; +; Peak interconnect usage (total/H/V) ; 44% / 49% / 38% ; ; Maximum fan-out ; 106 ; ; Highest non-global fan-out ; 45 ; ; Total fan-out ; 1050 ; @@ -188,40 +188,40 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin. +---------------------------------------------+--------------------+ -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Input Pins ; -+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+----------------------------+----------------------+ -; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Location assigned by ; -+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+----------------------------+----------------------+ -; C25M ; 64 ; 2 ; 8 ; 3 ; 4 ; 106 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; DMAin ; 48 ; 1 ; 6 ; 0 ; 0 ; 1 ; 0 ; no ; no ; yes ; Off ; 3.3V Schmitt Trigger Input ; User ; -; INTin ; 49 ; 1 ; 7 ; 0 ; 2 ; 1 ; 0 ; no ; no ; yes ; Off ; 3.3V Schmitt Trigger Input ; User ; -; MISO ; 16 ; 1 ; 1 ; 2 ; 2 ; 1 ; 0 ; no ; no ; yes ; Off ; 3.3-V LVTTL ; User ; -; PHI0 ; 41 ; 1 ; 5 ; 0 ; 1 ; 5 ; 0 ; yes ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; -; RA[0] ; 100 ; 2 ; 2 ; 5 ; 2 ; 9 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; RA[10] ; 14 ; 1 ; 1 ; 2 ; 0 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; RA[11] ; 34 ; 1 ; 3 ; 0 ; 1 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; RA[12] ; 35 ; 1 ; 3 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; RA[13] ; 36 ; 1 ; 4 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; RA[14] ; 37 ; 1 ; 4 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; RA[15] ; 38 ; 1 ; 4 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; RA[1] ; 98 ; 2 ; 2 ; 5 ; 0 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; RA[2] ; 97 ; 2 ; 3 ; 5 ; 3 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; RA[3] ; 4 ; 1 ; 1 ; 4 ; 2 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; RA[4] ; 1 ; 2 ; 2 ; 5 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; RA[5] ; 2 ; 1 ; 1 ; 4 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; RA[6] ; 3 ; 1 ; 1 ; 4 ; 1 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; RA[7] ; 6 ; 1 ; 1 ; 3 ; 0 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; RA[8] ; 7 ; 1 ; 1 ; 3 ; 1 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; RA[9] ; 8 ; 1 ; 1 ; 3 ; 2 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; SetFW[0] ; 96 ; 2 ; 3 ; 5 ; 2 ; 1 ; 0 ; no ; no ; no ; On ; 3.3V Schmitt Trigger Input ; User ; -; SetFW[1] ; 95 ; 2 ; 3 ; 5 ; 1 ; 1 ; 0 ; no ; no ; no ; On ; 3.3V Schmitt Trigger Input ; User ; -; nDEVSEL ; 40 ; 1 ; 5 ; 0 ; 2 ; 4 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; nIOSEL ; 39 ; 1 ; 5 ; 0 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; nIOSTRB ; 42 ; 1 ; 5 ; 0 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; nRES ; 44 ; 1 ; 6 ; 0 ; 2 ; 1 ; 0 ; no ; no ; yes ; Off ; 3.3V Schmitt Trigger Input ; User ; -; nWE ; 43 ; 1 ; 6 ; 0 ; 3 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+----------------------------+----------------------+ ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Location assigned by ; ++----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+ +; C25M ; 64 ; 2 ; 8 ; 3 ; 4 ; 106 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; User ; +; DMAin ; 48 ; 1 ; 6 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; +; INTin ; 49 ; 1 ; 7 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; +; MISO ; 16 ; 1 ; 1 ; 2 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; +; PHI0 ; 41 ; 1 ; 5 ; 0 ; 1 ; 5 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; User ; +; RA[0] ; 100 ; 2 ; 2 ; 5 ; 2 ; 9 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; +; RA[10] ; 14 ; 1 ; 1 ; 2 ; 0 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; +; RA[11] ; 34 ; 1 ; 3 ; 0 ; 1 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; +; RA[12] ; 35 ; 1 ; 3 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; +; RA[13] ; 36 ; 1 ; 4 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; +; RA[14] ; 37 ; 1 ; 4 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; +; RA[15] ; 38 ; 1 ; 4 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; +; RA[1] ; 98 ; 2 ; 2 ; 5 ; 0 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; +; RA[2] ; 97 ; 2 ; 3 ; 5 ; 3 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; +; RA[3] ; 4 ; 1 ; 1 ; 4 ; 2 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; +; RA[4] ; 1 ; 2 ; 2 ; 5 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; +; RA[5] ; 2 ; 1 ; 1 ; 4 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; +; RA[6] ; 3 ; 1 ; 1 ; 4 ; 1 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; +; RA[7] ; 6 ; 1 ; 1 ; 3 ; 0 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; +; RA[8] ; 7 ; 1 ; 1 ; 3 ; 1 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; +; RA[9] ; 8 ; 1 ; 1 ; 3 ; 2 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; +; SetFW[0] ; 96 ; 2 ; 3 ; 5 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; +; SetFW[1] ; 95 ; 2 ; 3 ; 5 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; +; nDEVSEL ; 40 ; 1 ; 5 ; 0 ; 2 ; 4 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; +; nIOSEL ; 39 ; 1 ; 5 ; 0 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; +; nIOSTRB ; 42 ; 1 ; 5 ; 0 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; +; nRES ; 44 ; 1 ; 6 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; +; nWE ; 43 ; 1 ; 6 ; 0 ; 3 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; ++----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+ +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ @@ -229,41 +229,41 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin. +---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ ; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ; +---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ -; DMAout ; 18 ; 1 ; 1 ; 1 ; 0 ; no ; yes ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; -; DQMH ; 57 ; 2 ; 8 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; -; DQML ; 85 ; 2 ; 5 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; -; FCK ; 12 ; 1 ; 1 ; 3 ; 3 ; no ; no ; no ; no ; yes ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; -; INTout ; 20 ; 1 ; 1 ; 1 ; 2 ; no ; yes ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; -; RAdir ; 19 ; 1 ; 1 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; -; RCKE ; 66 ; 2 ; 8 ; 3 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; -; RDdir ; 17 ; 1 ; 1 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; -; RWout ; 33 ; 1 ; 3 ; 0 ; 2 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; -; SA[0] ; 75 ; 2 ; 7 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; -; SA[10] ; 72 ; 2 ; 8 ; 4 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; -; SA[11] ; 73 ; 2 ; 8 ; 4 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; -; SA[12] ; 70 ; 2 ; 8 ; 4 ; 4 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; -; SA[1] ; 81 ; 2 ; 6 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; -; SA[2] ; 82 ; 2 ; 6 ; 5 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; -; SA[3] ; 84 ; 2 ; 6 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; -; SA[4] ; 76 ; 2 ; 7 ; 5 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; -; SA[5] ; 83 ; 2 ; 6 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; -; SA[6] ; 77 ; 2 ; 7 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; -; SA[7] ; 78 ; 2 ; 7 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; -; SA[8] ; 74 ; 2 ; 8 ; 4 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; -; SA[9] ; 71 ; 2 ; 8 ; 4 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; Fitter ; 10 pF ; - ; - ; -; SBA[0] ; 68 ; 2 ; 8 ; 3 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; -; SBA[1] ; 69 ; 2 ; 8 ; 3 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; -; nCAS ; 61 ; 2 ; 8 ; 2 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; -; nDMAout ; 21 ; 1 ; 1 ; 1 ; 3 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; -; nFCS ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; yes ; no ; no ; yes ; no ; On ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; -; nINHout ; 27 ; 1 ; 2 ; 0 ; 2 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; -; nIRQout ; 29 ; 1 ; 2 ; 0 ; 0 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; -; nNMIout ; 26 ; 1 ; 2 ; 0 ; 3 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; -; nRAS ; 62 ; 2 ; 8 ; 2 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; -; nRCS ; 67 ; 2 ; 8 ; 3 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; -; nRDYout ; 28 ; 1 ; 2 ; 0 ; 1 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; -; nRESout ; 30 ; 1 ; 3 ; 0 ; 3 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; -; nSWE ; 58 ; 2 ; 8 ; 2 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; +; DMAout ; 18 ; 1 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; +; DQMH ; 57 ; 2 ; 8 ; 2 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; +; DQML ; 85 ; 2 ; 5 ; 5 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; +; FCK ; 12 ; 1 ; 1 ; 3 ; 3 ; no ; no ; no ; no ; yes ; yes ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; +; INTout ; 20 ; 1 ; 1 ; 1 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; +; RAdir ; 19 ; 1 ; 1 ; 1 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; +; RCKE ; 66 ; 2 ; 8 ; 3 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; +; RDdir ; 17 ; 1 ; 1 ; 2 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; +; RWout ; 33 ; 1 ; 3 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; +; SA[0] ; 75 ; 2 ; 7 ; 5 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; +; SA[10] ; 73 ; 2 ; 8 ; 4 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; - ; - ; +; SA[11] ; 70 ; 2 ; 8 ; 4 ; 4 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; +; SA[12] ; 68 ; 2 ; 8 ; 3 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; +; SA[1] ; 81 ; 2 ; 6 ; 5 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; +; SA[2] ; 82 ; 2 ; 6 ; 5 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; +; SA[3] ; 84 ; 2 ; 6 ; 5 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; +; SA[4] ; 76 ; 2 ; 7 ; 5 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; +; SA[5] ; 83 ; 2 ; 6 ; 5 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; +; SA[6] ; 77 ; 2 ; 7 ; 5 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; +; SA[7] ; 78 ; 2 ; 7 ; 5 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; +; SA[8] ; 74 ; 2 ; 8 ; 4 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; +; SA[9] ; 72 ; 2 ; 8 ; 4 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; +; SBA[0] ; 69 ; 2 ; 8 ; 3 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; +; SBA[1] ; 71 ; 2 ; 8 ; 4 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; - ; - ; +; nCAS ; 61 ; 2 ; 8 ; 2 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; +; nDMAout ; 21 ; 1 ; 1 ; 1 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; +; nFCS ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; no ; no ; no ; yes ; no ; On ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; +; nINHout ; 27 ; 1 ; 2 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; +; nIRQout ; 29 ; 1 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; +; nNMIout ; 26 ; 1 ; 2 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; +; nRAS ; 62 ; 2 ; 8 ; 2 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; +; nRCS ; 67 ; 2 ; 8 ; 3 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; +; nRDYout ; 28 ; 1 ; 2 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; +; nRESout ; 30 ; 1 ; 3 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; +; nSWE ; 58 ; 2 ; 8 ; 2 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; +---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ @@ -272,23 +272,23 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin. +-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ ; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ; +-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ -; MOSI ; 15 ; 1 ; 1 ; 2 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; MOSIOE ; - ; -; RD[0] ; 86 ; 2 ; 5 ; 5 ; 1 ; 5 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~1 ; - ; -; RD[1] ; 87 ; 2 ; 5 ; 5 ; 2 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~1 ; - ; -; RD[2] ; 88 ; 2 ; 5 ; 5 ; 3 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~1 ; - ; -; RD[3] ; 89 ; 2 ; 4 ; 5 ; 0 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~1 ; - ; -; RD[4] ; 90 ; 2 ; 4 ; 5 ; 1 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~1 ; - ; -; RD[5] ; 91 ; 2 ; 4 ; 5 ; 2 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~1 ; - ; -; RD[6] ; 92 ; 2 ; 3 ; 5 ; 0 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~1 ; - ; -; RD[7] ; 99 ; 2 ; 2 ; 5 ; 1 ; 6 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~1 ; - ; -; SD[0] ; 50 ; 1 ; 7 ; 0 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; SDOE ; - ; -; SD[1] ; 47 ; 1 ; 6 ; 0 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; SDOE ; - ; -; SD[2] ; 56 ; 2 ; 8 ; 1 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; SDOE ; - ; -; SD[3] ; 55 ; 2 ; 8 ; 1 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; SDOE ; - ; -; SD[4] ; 51 ; 1 ; 7 ; 0 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; yes ; User ; 10 pF ; SDOE ; - ; -; SD[5] ; 52 ; 2 ; 8 ; 1 ; 4 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; SDOE ; - ; -; SD[6] ; 53 ; 2 ; 8 ; 1 ; 3 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; yes ; User ; 10 pF ; SDOE ; - ; -; SD[7] ; 54 ; 2 ; 8 ; 1 ; 2 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; yes ; User ; 10 pF ; SDOE ; - ; +; MOSI ; 15 ; 1 ; 1 ; 2 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; MOSIOE ; - ; +; RD[0] ; 86 ; 2 ; 5 ; 5 ; 1 ; 5 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; comb~1 ; - ; +; RD[1] ; 87 ; 2 ; 5 ; 5 ; 2 ; 4 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; comb~1 ; - ; +; RD[2] ; 88 ; 2 ; 5 ; 5 ; 3 ; 4 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; comb~1 ; - ; +; RD[3] ; 89 ; 2 ; 4 ; 5 ; 0 ; 4 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; comb~1 ; - ; +; RD[4] ; 90 ; 2 ; 4 ; 5 ; 1 ; 4 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; comb~1 ; - ; +; RD[5] ; 91 ; 2 ; 4 ; 5 ; 2 ; 4 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; comb~1 ; - ; +; RD[6] ; 92 ; 2 ; 3 ; 5 ; 0 ; 4 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; comb~1 ; - ; +; RD[7] ; 99 ; 2 ; 2 ; 5 ; 1 ; 6 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; comb~1 ; - ; +; SD[0] ; 50 ; 1 ; 7 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; SDOE ; - ; +; SD[1] ; 47 ; 1 ; 6 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; +; SD[2] ; 56 ; 2 ; 8 ; 1 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; +; SD[3] ; 55 ; 2 ; 8 ; 1 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; +; SD[4] ; 51 ; 1 ; 7 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; +; SD[5] ; 52 ; 2 ; 8 ; 1 ; 4 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; SDOE ; - ; +; SD[6] ; 53 ; 2 ; 8 ; 1 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; +; SD[7] ; 54 ; 2 ; 8 ; 1 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; +-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ @@ -302,112 +302,112 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin. +----------+-------------------+---------------+--------------+ -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; All Package Pins ; -+----------+------------+----------+----------------+--------+----------------------------+-----------+------------+-----------------+----------+--------------+ -; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; -+----------+------------+----------+----------------+--------+----------------------------+-----------+------------+-----------------+----------+--------------+ -; 1 ; 83 ; 2 ; RA[4] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 2 ; 0 ; 1 ; RA[5] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 3 ; 1 ; 1 ; RA[6] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 4 ; 2 ; 1 ; RA[3] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 5 ; 3 ; 1 ; nFCS ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ; -; 6 ; 4 ; 1 ; RA[7] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 7 ; 5 ; 1 ; RA[8] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 8 ; 6 ; 1 ; RA[9] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 9 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 10 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; -; 11 ; ; ; GNDINT ; gnd ; ; ; -- ; ; -- ; -- ; -; 12 ; 7 ; 1 ; FCK ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; yes ; Off ; -; 13 ; ; ; VCCINT ; power ; ; 2.5V/3.3V ; -- ; ; -- ; -- ; -; 14 ; 8 ; 1 ; RA[10] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 15 ; 9 ; 1 ; MOSI ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; yes ; Off ; -; 16 ; 10 ; 1 ; MISO ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; yes ; Off ; -; 17 ; 11 ; 1 ; RDdir ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ; -; 18 ; 12 ; 1 ; DMAout ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; yes ; Off ; -; 19 ; 13 ; 1 ; RAdir ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ; -; 20 ; 14 ; 1 ; INTout ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; yes ; Off ; -; 21 ; 15 ; 1 ; nDMAout ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ; -; 22 ; 16 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ; -; 23 ; 17 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ; -; 24 ; 18 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ; -; 25 ; 19 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ; -; 26 ; 20 ; 1 ; nNMIout ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ; -; 27 ; 21 ; 1 ; nINHout ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ; -; 28 ; 22 ; 1 ; nRDYout ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ; -; 29 ; 23 ; 1 ; nIRQout ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ; -; 30 ; 24 ; 1 ; nRESout ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ; -; 31 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 32 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; -; 33 ; 25 ; 1 ; RWout ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ; -; 34 ; 26 ; 1 ; RA[11] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 35 ; 27 ; 1 ; RA[12] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 36 ; 28 ; 1 ; RA[13] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 37 ; 29 ; 1 ; RA[14] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 38 ; 30 ; 1 ; RA[15] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 39 ; 31 ; 1 ; nIOSEL ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 40 ; 32 ; 1 ; nDEVSEL ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 41 ; 33 ; 1 ; PHI0 ; input ; 3.3V Schmitt Trigger Input ; ; Column I/O ; Y ; no ; Off ; -; 42 ; 34 ; 1 ; nIOSTRB ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 43 ; 35 ; 1 ; nWE ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 44 ; 36 ; 1 ; nRES ; input ; 3.3V Schmitt Trigger Input ; ; Column I/O ; Y ; yes ; Off ; -; 45 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 46 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; -; 47 ; 37 ; 1 ; SD[1] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; yes ; Off ; -; 48 ; 38 ; 1 ; DMAin ; input ; 3.3V Schmitt Trigger Input ; ; Column I/O ; Y ; yes ; Off ; -; 49 ; 39 ; 1 ; INTin ; input ; 3.3V Schmitt Trigger Input ; ; Column I/O ; Y ; yes ; Off ; -; 50 ; 40 ; 1 ; SD[0] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; yes ; Off ; -; 51 ; 41 ; 1 ; SD[4] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; yes ; Off ; -; 52 ; 42 ; 2 ; SD[5] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; yes ; Off ; -; 53 ; 43 ; 2 ; SD[6] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; yes ; Off ; -; 54 ; 44 ; 2 ; SD[7] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; yes ; Off ; -; 55 ; 45 ; 2 ; SD[3] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; yes ; Off ; -; 56 ; 46 ; 2 ; SD[2] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; yes ; Off ; -; 57 ; 47 ; 2 ; DQMH ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 58 ; 48 ; 2 ; nSWE ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 59 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 60 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; -; 61 ; 49 ; 2 ; nCAS ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 62 ; 50 ; 2 ; nRAS ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 63 ; ; ; VCCINT ; power ; ; 2.5V/3.3V ; -- ; ; -- ; -- ; -; 64 ; 51 ; 2 ; C25M ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 65 ; ; ; GNDINT ; gnd ; ; ; -- ; ; -- ; -- ; -; 66 ; 52 ; 2 ; RCKE ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 67 ; 53 ; 2 ; nRCS ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 68 ; 54 ; 2 ; SBA[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 69 ; 55 ; 2 ; SBA[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 70 ; 56 ; 2 ; SA[12] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 71 ; 57 ; 2 ; SA[9] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 72 ; 58 ; 2 ; SA[10] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 73 ; 59 ; 2 ; SA[11] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 74 ; 60 ; 2 ; SA[8] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 75 ; 61 ; 2 ; SA[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 76 ; 62 ; 2 ; SA[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 77 ; 63 ; 2 ; SA[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 78 ; 64 ; 2 ; SA[7] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 79 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; -; 80 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 81 ; 65 ; 2 ; SA[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 82 ; 66 ; 2 ; SA[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 83 ; 67 ; 2 ; SA[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 84 ; 68 ; 2 ; SA[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 85 ; 69 ; 2 ; DQML ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 86 ; 70 ; 2 ; RD[0] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; yes ; Off ; -; 87 ; 71 ; 2 ; RD[1] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; yes ; Off ; -; 88 ; 72 ; 2 ; RD[2] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; yes ; Off ; -; 89 ; 73 ; 2 ; RD[3] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; yes ; Off ; -; 90 ; 74 ; 2 ; RD[4] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; yes ; Off ; -; 91 ; 75 ; 2 ; RD[5] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; yes ; Off ; -; 92 ; 76 ; 2 ; RD[6] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; yes ; Off ; -; 93 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; -; 94 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 95 ; 77 ; 2 ; SetFW[1] ; input ; 3.3V Schmitt Trigger Input ; ; Column I/O ; Y ; no ; On ; -; 96 ; 78 ; 2 ; SetFW[0] ; input ; 3.3V Schmitt Trigger Input ; ; Column I/O ; Y ; no ; On ; -; 97 ; 79 ; 2 ; RA[2] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 98 ; 80 ; 2 ; RA[1] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 99 ; 81 ; 2 ; RD[7] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; yes ; Off ; -; 100 ; 82 ; 2 ; RA[0] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -+----------+------------+----------+----------------+--------+----------------------------+-----------+------------+-----------------+----------+--------------+ ++------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------+----------------+--------+--------------+-----------+------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------+----------------+--------+--------------+-----------+------------+-----------------+----------+--------------+ +; 1 ; 83 ; 2 ; RA[4] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 2 ; 0 ; 1 ; RA[5] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 3 ; 1 ; 1 ; RA[6] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 4 ; 2 ; 1 ; RA[3] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 5 ; 3 ; 1 ; nFCS ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ; +; 6 ; 4 ; 1 ; RA[7] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 7 ; 5 ; 1 ; RA[8] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 8 ; 6 ; 1 ; RA[9] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 9 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 10 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; +; 11 ; ; ; GNDINT ; gnd ; ; ; -- ; ; -- ; -- ; +; 12 ; 7 ; 1 ; FCK ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; yes ; Off ; +; 13 ; ; ; VCCINT ; power ; ; 2.5V/3.3V ; -- ; ; -- ; -- ; +; 14 ; 8 ; 1 ; RA[10] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 15 ; 9 ; 1 ; MOSI ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; yes ; Off ; +; 16 ; 10 ; 1 ; MISO ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 17 ; 11 ; 1 ; RDdir ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 18 ; 12 ; 1 ; DMAout ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 19 ; 13 ; 1 ; RAdir ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 20 ; 14 ; 1 ; INTout ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 21 ; 15 ; 1 ; nDMAout ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 22 ; 16 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ; +; 23 ; 17 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ; +; 24 ; 18 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ; +; 25 ; 19 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ; +; 26 ; 20 ; 1 ; nNMIout ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 27 ; 21 ; 1 ; nINHout ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 28 ; 22 ; 1 ; nRDYout ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 29 ; 23 ; 1 ; nIRQout ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 30 ; 24 ; 1 ; nRESout ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 31 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 32 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; +; 33 ; 25 ; 1 ; RWout ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 34 ; 26 ; 1 ; RA[11] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 35 ; 27 ; 1 ; RA[12] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 36 ; 28 ; 1 ; RA[13] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 37 ; 29 ; 1 ; RA[14] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 38 ; 30 ; 1 ; RA[15] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 39 ; 31 ; 1 ; nIOSEL ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 40 ; 32 ; 1 ; nDEVSEL ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 41 ; 33 ; 1 ; PHI0 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 42 ; 34 ; 1 ; nIOSTRB ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 43 ; 35 ; 1 ; nWE ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 44 ; 36 ; 1 ; nRES ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 45 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 46 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; +; 47 ; 37 ; 1 ; SD[1] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 48 ; 38 ; 1 ; DMAin ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 49 ; 39 ; 1 ; INTin ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 50 ; 40 ; 1 ; SD[0] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 51 ; 41 ; 1 ; SD[4] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 52 ; 42 ; 2 ; SD[5] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 53 ; 43 ; 2 ; SD[6] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 54 ; 44 ; 2 ; SD[7] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 55 ; 45 ; 2 ; SD[3] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 56 ; 46 ; 2 ; SD[2] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 57 ; 47 ; 2 ; DQMH ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 58 ; 48 ; 2 ; nSWE ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 59 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 60 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; +; 61 ; 49 ; 2 ; nCAS ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 62 ; 50 ; 2 ; nRAS ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 63 ; ; ; VCCINT ; power ; ; 2.5V/3.3V ; -- ; ; -- ; -- ; +; 64 ; 51 ; 2 ; C25M ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 65 ; ; ; GNDINT ; gnd ; ; ; -- ; ; -- ; -- ; +; 66 ; 52 ; 2 ; RCKE ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 67 ; 53 ; 2 ; nRCS ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 68 ; 54 ; 2 ; SA[12] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 69 ; 55 ; 2 ; SBA[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 70 ; 56 ; 2 ; SA[11] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 71 ; 57 ; 2 ; SBA[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 72 ; 58 ; 2 ; SA[9] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 73 ; 59 ; 2 ; SA[10] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 74 ; 60 ; 2 ; SA[8] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 75 ; 61 ; 2 ; SA[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 76 ; 62 ; 2 ; SA[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 77 ; 63 ; 2 ; SA[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 78 ; 64 ; 2 ; SA[7] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 79 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; +; 80 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 81 ; 65 ; 2 ; SA[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 82 ; 66 ; 2 ; SA[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 83 ; 67 ; 2 ; SA[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 84 ; 68 ; 2 ; SA[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 85 ; 69 ; 2 ; DQML ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 86 ; 70 ; 2 ; RD[0] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 87 ; 71 ; 2 ; RD[1] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 88 ; 72 ; 2 ; RD[2] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 89 ; 73 ; 2 ; RD[3] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 90 ; 74 ; 2 ; RD[4] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 91 ; 75 ; 2 ; RD[5] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 92 ; 76 ; 2 ; RD[6] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 93 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; +; 94 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 95 ; 77 ; 2 ; SetFW[1] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 96 ; 78 ; 2 ; SetFW[0] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 97 ; 79 ; 2 ; RA[2] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 98 ; 80 ; 2 ; RA[1] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 99 ; 81 ; 2 ; RD[7] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 100 ; 82 ; 2 ; RA[0] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; ++----------+------------+----------+----------------+--------+--------------+-----------+------------+-----------------+----------+--------------+ Note: Pin directions (input, output or bidir) are based on device operating in user mode. @@ -531,22 +531,22 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; +-------------+-------------+---------+---------------------------------------+--------+----------------------+------------------+ ; C25M ; PIN_64 ; 106 ; Clock ; yes ; Global Clock ; GCLK3 ; -; Decoder1~0 ; LC_X6_Y3_N7 ; 8 ; Clock enable ; no ; -- ; -- ; -; Equal2~0 ; LC_X3_Y2_N9 ; 19 ; Clock enable ; no ; -- ; -- ; -; FCKOE ; LC_X2_Y2_N4 ; 2 ; Output enable ; no ; -- ; -- ; -; IOROMRES ; LC_X2_Y3_N1 ; 1 ; Async. clear ; no ; -- ; -- ; -; MOSIOE ; LC_X2_Y2_N6 ; 1 ; Output enable ; no ; -- ; -- ; +; Decoder1~0 ; LC_X4_Y2_N5 ; 8 ; Clock enable ; no ; -- ; -- ; +; Equal2~0 ; LC_X3_Y2_N8 ; 19 ; Clock enable ; no ; -- ; -- ; +; FCKOE ; LC_X6_Y4_N4 ; 2 ; Output enable ; no ; -- ; -- ; +; IOROMRES ; LC_X2_Y3_N8 ; 1 ; Async. clear ; no ; -- ; -- ; +; MOSIOE ; LC_X6_Y4_N0 ; 1 ; Output enable ; no ; -- ; -- ; ; PHI0 ; PIN_41 ; 5 ; Clock ; yes ; Global Clock ; GCLK1 ; -; PS[0] ; LC_X3_Y2_N5 ; 44 ; Clock enable, Sync. clear, Sync. load ; no ; -- ; -- ; -; PS[2] ; LC_X3_Y2_N7 ; 26 ; Sync. clear, Sync. load ; no ; -- ; -- ; -; SDOE ; LC_X4_Y1_N7 ; 8 ; Output enable ; no ; -- ; -- ; -; SetFWLoaded ; LC_X3_Y2_N6 ; 2 ; Clock enable ; no ; -- ; -- ; -; always7~1 ; LC_X2_Y3_N5 ; 2 ; Clock enable ; no ; -- ; -- ; -; always9~2 ; LC_X4_Y2_N8 ; 8 ; Sync. load ; no ; -- ; -- ; -; always9~3 ; LC_X5_Y2_N8 ; 9 ; Sync. load ; no ; -- ; -- ; -; always9~4 ; LC_X5_Y2_N9 ; 9 ; Sync. load ; no ; -- ; -- ; -; comb~1 ; LC_X4_Y1_N3 ; 9 ; Output enable ; no ; -- ; -- ; -; nRESr ; LC_X2_Y3_N6 ; 29 ; Async. clear ; yes ; Global Clock ; GCLK2 ; +; PS[0] ; LC_X4_Y2_N2 ; 44 ; Clock enable, Sync. clear, Sync. load ; no ; -- ; -- ; +; PS[2] ; LC_X4_Y2_N7 ; 26 ; Sync. clear, Sync. load ; no ; -- ; -- ; +; SDOE ; LC_X4_Y1_N6 ; 8 ; Output enable ; no ; -- ; -- ; +; SetFWLoaded ; LC_X4_Y2_N6 ; 2 ; Clock enable ; no ; -- ; -- ; +; always7~1 ; LC_X2_Y3_N1 ; 2 ; Clock enable ; no ; -- ; -- ; +; always9~2 ; LC_X2_Y2_N9 ; 8 ; Sync. load ; no ; -- ; -- ; +; always9~3 ; LC_X2_Y1_N8 ; 9 ; Sync. load ; no ; -- ; -- ; +; always9~4 ; LC_X7_Y2_N8 ; 9 ; Sync. load ; no ; -- ; -- ; +; comb~1 ; LC_X5_Y1_N6 ; 9 ; Output enable ; no ; -- ; -- ; +; nRESr ; LC_X2_Y3_N4 ; 29 ; Async. clear ; yes ; Global Clock ; GCLK2 ; +-------------+-------------+---------+---------------------------------------+--------+----------------------+------------------+ @@ -557,7 +557,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +-------+-------------+---------+----------------------+------------------+ ; C25M ; PIN_64 ; 106 ; Global Clock ; GCLK3 ; ; PHI0 ; PIN_41 ; 5 ; Global Clock ; GCLK1 ; -; nRESr ; LC_X2_Y3_N6 ; 29 ; Global Clock ; GCLK2 ; +; nRESr ; LC_X2_Y3_N4 ; 29 ; Global Clock ; GCLK2 ; +-------+-------------+---------+----------------------+------------------+ @@ -917,13 +917,13 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +-----------------------------+--------------------+ ; Other Routing Resource Type ; Usage ; +-----------------------------+--------------------+ -; C4s ; 259 / 784 ( 33 % ) ; -; Direct links ; 56 / 888 ( 6 % ) ; +; C4s ; 234 / 784 ( 30 % ) ; +; Direct links ; 69 / 888 ( 8 % ) ; ; Global clocks ; 3 / 4 ( 75 % ) ; -; LAB clocks ; 11 / 32 ( 34 % ) ; -; LUT chains ; 35 / 216 ( 16 % ) ; -; Local interconnects ; 435 / 888 ( 49 % ) ; -; R4s ; 290 / 704 ( 41 % ) ; +; LAB clocks ; 12 / 32 ( 38 % ) ; +; LUT chains ; 39 / 216 ( 18 % ) ; +; Local interconnects ; 436 / 888 ( 49 % ) ; +; R4s ; 282 / 704 ( 40 % ) ; +-----------------------------+--------------------+ @@ -939,22 +939,23 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; 5 ; 0 ; ; 6 ; 0 ; ; 7 ; 0 ; -; 8 ; 4 ; -; 9 ; 2 ; -; 10 ; 18 ; +; 8 ; 3 ; +; 9 ; 4 ; +; 10 ; 17 ; +--------------------------------------------+------------------------------+ +-------------------------------------------------------------------+ ; LAB-wide Signals ; +------------------------------------+------------------------------+ -; LAB-wide Signals (Average = 2.04) ; Number of LABs (Total = 24) ; +; LAB-wide Signals (Average = 1.83) ; Number of LABs (Total = 24) ; +------------------------------------+------------------------------+ ; 1 Async. clear ; 7 ; ; 1 Clock ; 22 ; -; 1 Clock enable ; 7 ; -; 1 Sync. clear ; 6 ; -; 1 Sync. load ; 5 ; +; 1 Clock enable ; 6 ; +; 1 Sync. clear ; 4 ; +; 1 Sync. load ; 2 ; +; 2 Clock enables ; 1 ; ; 2 Clocks ; 2 ; +------------------------------------+------------------------------+ @@ -972,11 +973,11 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; 5 ; 0 ; ; 6 ; 0 ; ; 7 ; 0 ; -; 8 ; 4 ; -; 9 ; 2 ; +; 8 ; 3 ; +; 9 ; 4 ; ; 10 ; 12 ; -; 11 ; 4 ; -; 12 ; 1 ; +; 11 ; 2 ; +; 12 ; 2 ; ; 13 ; 0 ; ; 14 ; 0 ; ; 15 ; 1 ; @@ -986,19 +987,19 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +--------------------------------------------------------------------------------+ ; LAB Signals Sourced Out ; +-------------------------------------------------+------------------------------+ -; Number of Signals Sourced Out (Average = 7.00) ; Number of LABs (Total = 24) ; +; Number of Signals Sourced Out (Average = 6.92) ; Number of LABs (Total = 24) ; +-------------------------------------------------+------------------------------+ ; 0 ; 0 ; ; 1 ; 0 ; ; 2 ; 0 ; -; 3 ; 2 ; -; 4 ; 5 ; -; 5 ; 1 ; +; 3 ; 3 ; +; 4 ; 4 ; +; 5 ; 2 ; ; 6 ; 2 ; -; 7 ; 0 ; -; 8 ; 5 ; -; 9 ; 6 ; -; 10 ; 2 ; +; 7 ; 1 ; +; 8 ; 3 ; +; 9 ; 3 ; +; 10 ; 5 ; ; 11 ; 1 ; +-------------------------------------------------+------------------------------+ @@ -1006,31 +1007,30 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +-----------------------------------------------------------------------------+ ; LAB Distinct Inputs ; +----------------------------------------------+------------------------------+ -; Number of Distinct Inputs (Average = 15.96) ; Number of LABs (Total = 24) ; +; Number of Distinct Inputs (Average = 15.54) ; Number of LABs (Total = 24) ; +----------------------------------------------+------------------------------+ ; 0 ; 0 ; ; 1 ; 0 ; ; 2 ; 0 ; ; 3 ; 0 ; -; 4 ; 0 ; +; 4 ; 1 ; ; 5 ; 0 ; ; 6 ; 0 ; -; 7 ; 1 ; +; 7 ; 0 ; ; 8 ; 1 ; ; 9 ; 0 ; -; 10 ; 1 ; +; 10 ; 0 ; ; 11 ; 0 ; -; 12 ; 1 ; -; 13 ; 3 ; +; 12 ; 3 ; +; 13 ; 2 ; ; 14 ; 2 ; -; 15 ; 2 ; -; 16 ; 3 ; -; 17 ; 0 ; -; 18 ; 2 ; -; 19 ; 1 ; -; 20 ; 2 ; +; 15 ; 3 ; +; 16 ; 2 ; +; 17 ; 2 ; +; 18 ; 1 ; +; 19 ; 2 ; +; 20 ; 1 ; ; 21 ; 4 ; -; 22 ; 1 ; +----------------------------------------------+------------------------------+ @@ -1064,8 +1064,6 @@ Info (176444): Device migration not selected. If you intend to use device migrat Info (176445): Device EPM570T100C5 is compatible Info (176445): Device EPM570T100I5 is compatible Info (176445): Device EPM570T100A5 is compatible -Critical Warning (169085): No exact pin location assignment(s) for 1 pins of 80 total pins - Info (169086): Pin SA[9] not assigned to an exact location on the device Critical Warning (332012): Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. Info (332144): No user constrained base clocks found in the design Info (332128): Timing requirements not specified -- optimizing circuit to achieve the following default global requirements @@ -1087,32 +1085,25 @@ Info (176234): Starting register packing Info (186468): Started processing fast register assignments Info (186469): Finished processing fast register assignments Info (176235): Finished register packing -Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement - Info (176211): Number of I/O pins in group: 1 (unused VREF, 3.3V VCCIO, 0 input, 1 output, 0 bidirectional) - Info (176212): I/O standards used: 3.3-V LVTTL. -Info (176215): I/O bank details before I/O pin placement - Info (176214): Statistics of I/O banks - Info (176213): I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 38 total pin(s) used -- 0 pins available - Info (176213): I/O bank number 2 does not use VREF pins and has 3.3V VCCIO pins. 41 total pin(s) used -- 1 pins available -Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00 +Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01 Info (170189): Fitter placement preparation operations beginning -Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01 Info (170191): Fitter placement operations beginning Info (170137): Fitter placement was successful Info (170192): Fitter placement operations ending: elapsed time is 00:00:02 Info (170193): Fitter routing operations beginning -Info (170195): Router estimated average interconnect usage is 35% of the available device resources - Info (170196): Router estimated peak interconnect usage is 35% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5 +Info (170195): Router estimated average interconnect usage is 36% of the available device resources + Info (170196): Router estimated peak interconnect usage is 36% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5 Info (170194): Fitter routing operations ending: elapsed time is 00:00:01 -Info (11888): Total time spent on timing analysis during the Fitter is 0.70 seconds. +Info (11888): Total time spent on timing analysis during the Fitter is 0.56 seconds. Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00 Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'. Info (144001): Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg -Info: Quartus II 32-bit Fitter was successful. 0 errors, 4 warnings - Info: Peak virtual memory: 378 megabytes - Info: Processing ended: Tue Apr 20 05:42:59 2021 - Info: Elapsed time: 00:00:09 - Info: Total CPU time (on all processors): 00:00:09 +Info: Quartus II 32-bit Fitter was successful. 0 errors, 3 warnings + Info: Peak virtual memory: 382 megabytes + Info: Processing ended: Tue Apr 20 04:19:53 2021 + Info: Elapsed time: 00:00:08 + Info: Total CPU time (on all processors): 00:00:08 +----------------------------+ diff --git a/cpld/output_files/GR8RAM.fit.summary b/cpld/output_files/GR8RAM.fit.summary index 62a7e91..18cf322 100755 --- a/cpld/output_files/GR8RAM.fit.summary +++ b/cpld/output_files/GR8RAM.fit.summary @@ -1,4 +1,4 @@ -Fitter Status : Successful - Tue Apr 20 05:42:59 2021 +Fitter Status : Successful - Tue Apr 20 04:19:53 2021 Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition Revision Name : GR8RAM Top-level Entity Name : GR8RAM diff --git a/cpld/output_files/GR8RAM.flow.rpt b/cpld/output_files/GR8RAM.flow.rpt index fe61520..c322ed2 100755 --- a/cpld/output_files/GR8RAM.flow.rpt +++ b/cpld/output_files/GR8RAM.flow.rpt @@ -1,5 +1,5 @@ Flow report for GR8RAM -Tue Apr 20 05:43:09 2021 +Tue Apr 20 04:20:05 2021 Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition @@ -40,7 +40,7 @@ applicable agreement for further details. +-----------------------------------------------------------------------------+ ; Flow Summary ; +---------------------------+-------------------------------------------------+ -; Flow Status ; Successful - Tue Apr 20 05:43:03 2021 ; +; Flow Status ; Successful - Tue Apr 20 04:19:58 2021 ; ; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; ; Revision Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ; @@ -59,7 +59,7 @@ applicable agreement for further details. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 04/20/2021 05:42:44 ; +; Start date & time ; 04/20/2021 04:19:41 ; ; Main task ; Compilation ; ; Revision Name ; GR8RAM ; +-------------------+---------------------+ @@ -75,7 +75,7 @@ applicable agreement for further details. ; ALM_REGISTER_PACKING_EFFORT ; High ; Medium ; -- ; -- ; ; AUTO_PACKED_REGISTERS_MAXII ; Minimize Area ; Auto ; -- ; -- ; ; AUTO_RESOURCE_SHARING ; On ; Off ; -- ; -- ; -; COMPILER_SIGNATURE_ID ; 44085571633675.161891176303636 ; -- ; -- ; -- ; +; COMPILER_SIGNATURE_ID ; 44085571633675.161890678100176 ; -- ; -- ; -- ; ; FINAL_PLACEMENT_OPTIMIZATION ; Always ; Automatically ; -- ; -- ; ; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ; ; IOBANK_VCCIO ; 3.3V ; -- ; -- ; 1 ; @@ -102,11 +102,11 @@ applicable agreement for further details. +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:06 ; 1.0 ; 301 MB ; 00:00:06 ; -; Fitter ; 00:00:09 ; 1.5 ; 378 MB ; 00:00:08 ; -; Assembler ; 00:00:01 ; 1.0 ; 292 MB ; 00:00:02 ; -; TimeQuest Timing Analyzer ; 00:00:04 ; 1.0 ; 275 MB ; 00:00:04 ; -; Total ; 00:00:20 ; -- ; -- ; 00:00:20 ; +; Analysis & Synthesis ; 00:00:05 ; 1.0 ; 301 MB ; 00:00:04 ; +; Fitter ; 00:00:08 ; 1.2 ; 382 MB ; 00:00:07 ; +; Assembler ; 00:00:02 ; 1.0 ; 292 MB ; 00:00:02 ; +; TimeQuest Timing Analyzer ; 00:00:05 ; 1.0 ; 278 MB ; 00:00:04 ; +; Total ; 00:00:20 ; -- ; -- ; 00:00:17 ; +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ diff --git a/cpld/output_files/GR8RAM.map.rpt b/cpld/output_files/GR8RAM.map.rpt index 5833b8f..008860b 100755 --- a/cpld/output_files/GR8RAM.map.rpt +++ b/cpld/output_files/GR8RAM.map.rpt @@ -1,5 +1,5 @@ Analysis & Synthesis report for GR8RAM -Tue Apr 20 05:42:47 2021 +Tue Apr 20 04:19:44 2021 Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition @@ -45,7 +45,7 @@ applicable agreement for further details. +-------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +-----------------------------+-------------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Tue Apr 20 05:42:47 2021 ; +; Analysis & Synthesis Status ; Successful - Tue Apr 20 04:19:44 2021 ; ; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; ; Revision Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ; @@ -280,7 +280,7 @@ Encoding Type: Minimal Bits Info: ******************************************************************* Info: Running Quartus II 32-bit Analysis & Synthesis Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - Info: Processing started: Tue Apr 20 05:42:41 2021 + Info: Processing started: Tue Apr 20 04:19:39 2021 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected Info (12021): Found 1 design units, including 1 entities, in source file gr8ram.v @@ -309,9 +309,9 @@ Info (21057): Implemented 321 device resources after synthesis - the final resou Info (144001): Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 13 warnings Info: Peak virtual memory: 301 megabytes - Info: Processing ended: Tue Apr 20 05:42:47 2021 - Info: Elapsed time: 00:00:06 - Info: Total CPU time (on all processors): 00:00:06 + Info: Processing ended: Tue Apr 20 04:19:44 2021 + Info: Elapsed time: 00:00:05 + Info: Total CPU time (on all processors): 00:00:04 +------------------------------------------+ diff --git a/cpld/output_files/GR8RAM.map.summary b/cpld/output_files/GR8RAM.map.summary index af463eb..8eeb674 100755 --- a/cpld/output_files/GR8RAM.map.summary +++ b/cpld/output_files/GR8RAM.map.summary @@ -1,4 +1,4 @@ -Analysis & Synthesis Status : Successful - Tue Apr 20 05:42:47 2021 +Analysis & Synthesis Status : Successful - Tue Apr 20 04:19:44 2021 Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition Revision Name : GR8RAM Top-level Entity Name : GR8RAM diff --git a/cpld/output_files/GR8RAM.pin b/cpld/output_files/GR8RAM.pin index d006f6d..54ede08 100755 --- a/cpld/output_files/GR8RAM.pin +++ b/cpld/output_files/GR8RAM.pin @@ -102,15 +102,15 @@ RA[14] : 37 : input : 3.3-V LVTTL : RA[15] : 38 : input : 3.3-V LVTTL : : 1 : Y nIOSEL : 39 : input : 3.3-V LVTTL : : 1 : Y nDEVSEL : 40 : input : 3.3-V LVTTL : : 1 : Y -PHI0 : 41 : input : 3.3V Schmitt Trigger Input : : 1 : Y +PHI0 : 41 : input : 3.3-V LVTTL : : 1 : Y nIOSTRB : 42 : input : 3.3-V LVTTL : : 1 : Y nWE : 43 : input : 3.3-V LVTTL : : 1 : Y -nRES : 44 : input : 3.3V Schmitt Trigger Input : : 1 : Y +nRES : 44 : input : 3.3-V LVTTL : : 1 : Y VCCIO1 : 45 : power : : 3.3V : 1 : GNDIO : 46 : gnd : : : : SD[1] : 47 : bidir : 3.3-V LVTTL : : 1 : Y -DMAin : 48 : input : 3.3V Schmitt Trigger Input : : 1 : Y -INTin : 49 : input : 3.3V Schmitt Trigger Input : : 1 : Y +DMAin : 48 : input : 3.3-V LVTTL : : 1 : Y +INTin : 49 : input : 3.3-V LVTTL : : 1 : Y SD[0] : 50 : bidir : 3.3-V LVTTL : : 1 : Y SD[4] : 51 : bidir : 3.3-V LVTTL : : 1 : Y SD[5] : 52 : bidir : 3.3-V LVTTL : : 2 : Y @@ -129,12 +129,12 @@ C25M : 64 : input : 3.3-V LVTTL : GNDINT : 65 : gnd : : : : RCKE : 66 : output : 3.3-V LVTTL : : 2 : Y nRCS : 67 : output : 3.3-V LVTTL : : 2 : Y -SBA[0] : 68 : output : 3.3-V LVTTL : : 2 : Y -SBA[1] : 69 : output : 3.3-V LVTTL : : 2 : Y -SA[12] : 70 : output : 3.3-V LVTTL : : 2 : Y -SA[9] : 71 : output : 3.3-V LVTTL : : 2 : N -SA[10] : 72 : output : 3.3-V LVTTL : : 2 : Y -SA[11] : 73 : output : 3.3-V LVTTL : : 2 : Y +SA[12] : 68 : output : 3.3-V LVTTL : : 2 : Y +SBA[0] : 69 : output : 3.3-V LVTTL : : 2 : Y +SA[11] : 70 : output : 3.3-V LVTTL : : 2 : Y +SBA[1] : 71 : output : 3.3-V LVTTL : : 2 : Y +SA[9] : 72 : output : 3.3-V LVTTL : : 2 : Y +SA[10] : 73 : output : 3.3-V LVTTL : : 2 : Y SA[8] : 74 : output : 3.3-V LVTTL : : 2 : Y SA[0] : 75 : output : 3.3-V LVTTL : : 2 : Y SA[4] : 76 : output : 3.3-V LVTTL : : 2 : Y @@ -156,8 +156,8 @@ RD[5] : 91 : bidir : 3.3-V LVTTL : RD[6] : 92 : bidir : 3.3-V LVTTL : : 2 : Y GNDIO : 93 : gnd : : : : VCCIO2 : 94 : power : : 3.3V : 2 : -SetFW[1] : 95 : input : 3.3V Schmitt Trigger Input : : 2 : Y -SetFW[0] : 96 : input : 3.3V Schmitt Trigger Input : : 2 : Y +SetFW[1] : 95 : input : 3.3-V LVTTL : : 2 : Y +SetFW[0] : 96 : input : 3.3-V LVTTL : : 2 : Y RA[2] : 97 : input : 3.3-V LVTTL : : 2 : Y RA[1] : 98 : input : 3.3-V LVTTL : : 2 : Y RD[7] : 99 : bidir : 3.3-V LVTTL : : 2 : Y diff --git a/cpld/output_files/GR8RAM.pof b/cpld/output_files/GR8RAM.pof index f3d9d61..7723661 100755 Binary files a/cpld/output_files/GR8RAM.pof and b/cpld/output_files/GR8RAM.pof differ diff --git a/cpld/output_files/GR8RAM.sta.rpt b/cpld/output_files/GR8RAM.sta.rpt index fa7e124..2aa7fff 100755 --- a/cpld/output_files/GR8RAM.sta.rpt +++ b/cpld/output_files/GR8RAM.sta.rpt @@ -1,5 +1,5 @@ TimeQuest Timing Analyzer report for GR8RAM -Tue Apr 20 05:43:09 2021 +Tue Apr 20 04:20:05 2021 Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition @@ -22,8 +22,8 @@ Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit 14. Hold: 'C25M' 15. Recovery: 'C25M' 16. Removal: 'C25M' - 17. Minimum Pulse Width: 'PHI0' - 18. Minimum Pulse Width: 'C25M' + 17. Minimum Pulse Width: 'C25M' + 18. Minimum Pulse Width: 'PHI0' 19. Setup Times 20. Hold Times 21. Clock to Output Times @@ -104,13 +104,13 @@ applicable agreement for further details. +------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------+ -+-------------------------------------------------+ -; Fmax Summary ; -+-----------+-----------------+------------+------+ -; Fmax ; Restricted Fmax ; Clock Name ; Note ; -+-----------+-----------------+------------+------+ -; 92.22 MHz ; 92.22 MHz ; C25M ; ; -+-----------+-----------------+------------+------+ ++--------------------------------------------------+ +; Fmax Summary ; ++------------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++------------+-----------------+------------+------+ +; 103.27 MHz ; 103.27 MHz ; C25M ; ; ++------------+-----------------+------------+------+ This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. @@ -119,8 +119,8 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +-------+--------+---------------+ -; C25M ; -9.844 ; -724.767 ; -; PHI0 ; -0.019 ; -0.019 ; +; C25M ; -9.005 ; -699.357 ; +; PHI0 ; -0.425 ; -0.425 ; +-------+--------+---------------+ @@ -129,8 +129,8 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +-------+--------+---------------+ -; PHI0 ; -0.952 ; -0.952 ; -; C25M ; 1.385 ; 0.000 ; +; PHI0 ; -0.248 ; -0.248 ; +; C25M ; 1.400 ; 0.000 ; +-------+--------+---------------+ @@ -139,7 +139,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +-------+--------+---------------+ -; C25M ; -4.389 ; -127.281 ; +; C25M ; -4.412 ; -127.948 ; +-------+--------+---------------+ @@ -148,7 +148,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +-------+-------+---------------+ -; C25M ; 4.835 ; 0.000 ; +; C25M ; 4.858 ; 0.000 ; +-------+-------+---------------+ @@ -157,8 +157,8 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +-------+--------+---------------+ -; PHI0 ; -3.000 ; -3.000 ; ; C25M ; -2.289 ; -2.289 ; +; PHI0 ; -2.289 ; -2.289 ; +-------+--------+---------------+ @@ -167,106 +167,106 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +--------+----------------+----------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+----------------+----------------+--------------+-------------+--------------+------------+------------+ -; -9.844 ; IS.state_bit_1 ; SA[3]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 10.511 ; -; -9.419 ; IS.state_bit_1 ; SA[4]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 10.086 ; -; -9.377 ; IS.state_bit_1 ; SA[6]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 10.044 ; -; -9.334 ; RAMSpecSELr ; RCKE~reg0 ; PHI0 ; C25M ; 1.000 ; -3.356 ; 6.645 ; -; -9.318 ; RAMSpecSELr ; SA[0]~reg0 ; PHI0 ; C25M ; 1.000 ; -3.356 ; 6.629 ; -; -9.258 ; IS.state_bit_0 ; SA[3]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.925 ; -; -9.124 ; IS.state_bit_1 ; SA[7]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.791 ; -; -9.102 ; IS.state_bit_1 ; SA[0]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.769 ; -; -9.057 ; RAMSpecSELr ; SA[2]~reg0 ; PHI0 ; C25M ; 1.000 ; -3.356 ; 6.368 ; -; -9.052 ; RAMSpecSELr ; SA[1]~reg0 ; PHI0 ; C25M ; 1.000 ; -3.356 ; 6.363 ; -; -8.986 ; RAMSpecSELr ; SA[6]~reg0 ; PHI0 ; C25M ; 1.000 ; -3.356 ; 6.297 ; -; -8.934 ; IS.state_bit_1 ; SA[8]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.601 ; -; -8.932 ; ROMSpecRDr ; RCKE~reg0 ; PHI0 ; C25M ; 1.000 ; -3.356 ; 6.243 ; -; -8.901 ; IS.state_bit_1 ; SA[1]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.568 ; -; -8.869 ; RAMSpecSELr ; SA[3]~reg0 ; PHI0 ; C25M ; 1.000 ; -3.356 ; 6.180 ; -; -8.852 ; nWEr ; RCKE~reg0 ; PHI0 ; C25M ; 1.000 ; -3.356 ; 6.163 ; -; -8.841 ; IS.state_bit_1 ; SA[2]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.508 ; -; -8.833 ; IS.state_bit_0 ; SA[4]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.500 ; -; -8.807 ; RAMSpecSELr ; nRCS~reg0 ; PHI0 ; C25M ; 1.000 ; -3.356 ; 6.118 ; -; -8.804 ; RAMSpecSELr ; SA[5]~reg0 ; PHI0 ; C25M ; 1.000 ; -3.356 ; 6.115 ; -; -8.791 ; IS.state_bit_0 ; SA[6]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.458 ; -; -8.646 ; REGEN ; RDD[6] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.313 ; -; -8.640 ; RAMSpecSELr ; SA[7]~reg0 ; PHI0 ; C25M ; 1.000 ; -3.356 ; 5.951 ; -; -8.603 ; LS[6] ; IS.state_bit_0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.270 ; -; -8.582 ; IS.state_bit_1 ; SA[5]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.249 ; -; -8.582 ; PS[1] ; SA[1]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.249 ; -; -8.541 ; RAMSpecSELr ; SA[8]~reg0 ; PHI0 ; C25M ; 1.000 ; -3.356 ; 5.852 ; -; -8.538 ; IS.state_bit_0 ; SA[7]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.205 ; -; -8.536 ; PS[1] ; SA[0]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.203 ; -; -8.516 ; IS.state_bit_0 ; SA[0]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.183 ; -; -8.516 ; nWEr ; Addr[0] ; PHI0 ; C25M ; 1.000 ; -3.356 ; 5.827 ; -; -8.516 ; nWEr ; Addr[1] ; PHI0 ; C25M ; 1.000 ; -3.356 ; 5.827 ; -; -8.516 ; nWEr ; Addr[2] ; PHI0 ; C25M ; 1.000 ; -3.356 ; 5.827 ; -; -8.516 ; nWEr ; Addr[3] ; PHI0 ; C25M ; 1.000 ; -3.356 ; 5.827 ; -; -8.516 ; nWEr ; Addr[4] ; PHI0 ; C25M ; 1.000 ; -3.356 ; 5.827 ; -; -8.516 ; nWEr ; Addr[5] ; PHI0 ; C25M ; 1.000 ; -3.356 ; 5.827 ; -; -8.516 ; nWEr ; Addr[6] ; PHI0 ; C25M ; 1.000 ; -3.356 ; 5.827 ; -; -8.516 ; nWEr ; Addr[7] ; PHI0 ; C25M ; 1.000 ; -3.356 ; 5.827 ; -; -8.469 ; REGEN ; Addr[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.136 ; -; -8.469 ; REGEN ; Addr[1] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.136 ; -; -8.469 ; REGEN ; Addr[2] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.136 ; -; -8.469 ; REGEN ; Addr[3] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.136 ; -; -8.469 ; REGEN ; Addr[4] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.136 ; -; -8.469 ; REGEN ; Addr[5] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.136 ; -; -8.469 ; REGEN ; Addr[6] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.136 ; -; -8.469 ; REGEN ; Addr[7] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.136 ; -; -8.467 ; PS[0] ; SA[0]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.134 ; -; -8.451 ; IS.state_bit_0 ; SA[1]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.118 ; -; -8.445 ; LS[6] ; IS.state_bit_2 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.112 ; -; -8.444 ; RAMSpecSELr ; SA[4]~reg0 ; PHI0 ; C25M ; 1.000 ; -3.356 ; 5.755 ; -; -8.404 ; ROMSpecRDr ; nRCS~reg0 ; PHI0 ; C25M ; 1.000 ; -3.356 ; 5.715 ; -; -8.392 ; RAMSpecSELr ; SBA[0]~reg0 ; PHI0 ; C25M ; 1.000 ; -3.356 ; 5.703 ; -; -8.378 ; RAMSpecSELr ; SBA[1]~reg0 ; PHI0 ; C25M ; 1.000 ; -3.356 ; 5.689 ; -; -8.373 ; IS.state_bit_1 ; SBA[0]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.040 ; -; -8.348 ; IS.state_bit_0 ; SA[8]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.015 ; -; -8.305 ; RAMSpecSELr ; SA[11]~reg0 ; PHI0 ; C25M ; 1.000 ; -3.356 ; 5.616 ; -; -8.301 ; RAMSpecSELr ; SA[12]~reg0 ; PHI0 ; C25M ; 1.000 ; -3.356 ; 5.612 ; -; -8.298 ; RAMSpecSELr ; SA[9]~reg0 ; PHI0 ; C25M ; 1.000 ; -3.356 ; 5.609 ; -; -8.296 ; LS[3] ; IS.state_bit_0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.963 ; -; -8.272 ; nWEr ; nRCS~reg0 ; PHI0 ; C25M ; 1.000 ; -3.356 ; 5.583 ; -; -8.255 ; IS.state_bit_0 ; SA[2]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.922 ; -; -8.246 ; PS[1] ; Addr[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.913 ; -; -8.246 ; PS[1] ; Addr[1] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.913 ; -; -8.246 ; PS[1] ; Addr[2] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.913 ; -; -8.246 ; PS[1] ; Addr[3] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.913 ; -; -8.246 ; PS[1] ; Addr[4] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.913 ; -; -8.246 ; PS[1] ; Addr[5] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.913 ; -; -8.246 ; PS[1] ; Addr[6] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.913 ; -; -8.246 ; PS[1] ; Addr[7] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.913 ; -; -8.222 ; nWEr ; Addr[23] ; PHI0 ; C25M ; 1.000 ; -3.356 ; 5.533 ; -; -8.222 ; nWEr ; Addr[16] ; PHI0 ; C25M ; 1.000 ; -3.356 ; 5.533 ; -; -8.222 ; nWEr ; Addr[17] ; PHI0 ; C25M ; 1.000 ; -3.356 ; 5.533 ; -; -8.222 ; nWEr ; Addr[18] ; PHI0 ; C25M ; 1.000 ; -3.356 ; 5.533 ; -; -8.222 ; nWEr ; Addr[19] ; PHI0 ; C25M ; 1.000 ; -3.356 ; 5.533 ; -; -8.222 ; nWEr ; Addr[20] ; PHI0 ; C25M ; 1.000 ; -3.356 ; 5.533 ; -; -8.222 ; nWEr ; Addr[21] ; PHI0 ; C25M ; 1.000 ; -3.356 ; 5.533 ; -; -8.222 ; nWEr ; Addr[22] ; PHI0 ; C25M ; 1.000 ; -3.356 ; 5.533 ; -; -8.201 ; LS[0] ; RCKE~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.868 ; -; -8.175 ; REGEN ; Addr[23] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.842 ; -; -8.175 ; REGEN ; Addr[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.842 ; -; -8.175 ; REGEN ; Addr[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.842 ; -; -8.175 ; REGEN ; Addr[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.842 ; -; -8.175 ; REGEN ; Addr[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.842 ; -; -8.175 ; REGEN ; Addr[20] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.842 ; -; -8.175 ; REGEN ; Addr[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.842 ; -; -8.175 ; REGEN ; Addr[22] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.842 ; -; -8.156 ; IS.state_bit_1 ; RCKE~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.823 ; -; -8.147 ; PS[1] ; SA[2]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.814 ; -; -8.138 ; LS[3] ; IS.state_bit_2 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.805 ; -; -8.114 ; nWEr ; Bank ; PHI0 ; C25M ; 1.000 ; -3.356 ; 5.425 ; -; -8.098 ; nWEr ; Addr[10] ; PHI0 ; C25M ; 1.000 ; -3.356 ; 5.409 ; -; -8.098 ; nWEr ; Addr[11] ; PHI0 ; C25M ; 1.000 ; -3.356 ; 5.409 ; -; -8.098 ; nWEr ; Addr[12] ; PHI0 ; C25M ; 1.000 ; -3.356 ; 5.409 ; -; -8.098 ; nWEr ; Addr[13] ; PHI0 ; C25M ; 1.000 ; -3.356 ; 5.409 ; -; -8.098 ; nWEr ; Addr[14] ; PHI0 ; C25M ; 1.000 ; -3.356 ; 5.409 ; -; -8.098 ; nWEr ; Addr[15] ; PHI0 ; C25M ; 1.000 ; -3.356 ; 5.409 ; -; -8.098 ; nWEr ; Addr[8] ; PHI0 ; C25M ; 1.000 ; -3.356 ; 5.409 ; -; -8.098 ; nWEr ; Addr[9] ; PHI0 ; C25M ; 1.000 ; -3.356 ; 5.409 ; -; -8.095 ; LS[7] ; IS.state_bit_0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.762 ; -; -8.067 ; REGEN ; Bank ; C25M ; C25M ; 1.000 ; 0.000 ; 8.734 ; +; -9.005 ; RAMSpecSELr ; SA[8]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.894 ; +; -8.961 ; RAMSpecSELr ; SA[6]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.850 ; +; -8.953 ; RAMSpecSELr ; SA[7]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.842 ; +; -8.919 ; nWEr ; RCKE~reg0 ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.808 ; +; -8.916 ; ROMSpecRDr ; RCKE~reg0 ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.805 ; +; -8.897 ; RAMSpecSELr ; SA[2]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.786 ; +; -8.683 ; IS.state_bit_1 ; SA[8]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.350 ; +; -8.631 ; IS.state_bit_1 ; SA[7]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.298 ; +; -8.625 ; IS.state_bit_1 ; SA[6]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.292 ; +; -8.571 ; RAMSpecSELr ; RCKE~reg0 ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.460 ; +; -8.495 ; RAMSpecSELr ; SA[1]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.384 ; +; -8.451 ; LS[10] ; IS.state_bit_0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.118 ; +; -8.428 ; RAMSpecSELr ; SA[5]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.317 ; +; -8.422 ; nWEr ; Addr[0] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.311 ; +; -8.422 ; nWEr ; Addr[1] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.311 ; +; -8.422 ; nWEr ; Addr[2] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.311 ; +; -8.422 ; nWEr ; Addr[3] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.311 ; +; -8.422 ; nWEr ; Addr[4] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.311 ; +; -8.422 ; nWEr ; Addr[5] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.311 ; +; -8.422 ; nWEr ; Addr[6] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.311 ; +; -8.422 ; nWEr ; Addr[7] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.311 ; +; -8.419 ; nWEr ; Addr[10] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.308 ; +; -8.419 ; nWEr ; Addr[11] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.308 ; +; -8.419 ; nWEr ; Addr[12] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.308 ; +; -8.419 ; nWEr ; Addr[13] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.308 ; +; -8.419 ; nWEr ; Addr[14] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.308 ; +; -8.419 ; nWEr ; Addr[15] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.308 ; +; -8.419 ; nWEr ; Addr[8] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.308 ; +; -8.419 ; nWEr ; Addr[9] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.308 ; +; -8.387 ; nWEr ; AddrIncH ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.276 ; +; -8.301 ; LS[11] ; IS.state_bit_0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.968 ; +; -8.289 ; IS.state_bit_0 ; SA[8]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.956 ; +; -8.284 ; nWEr ; nRCS~reg0 ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.173 ; +; -8.265 ; RAMSpecSELr ; SA[0]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.154 ; +; -8.261 ; nWEr ; Addr[23] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.150 ; +; -8.261 ; nWEr ; Addr[16] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.150 ; +; -8.261 ; nWEr ; Addr[17] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.150 ; +; -8.261 ; nWEr ; Addr[18] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.150 ; +; -8.261 ; nWEr ; Addr[19] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.150 ; +; -8.261 ; nWEr ; Addr[20] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.150 ; +; -8.261 ; nWEr ; Addr[21] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.150 ; +; -8.261 ; nWEr ; Addr[22] ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.150 ; +; -8.245 ; ROMSpecRDr ; nRCS~reg0 ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.134 ; +; -8.237 ; IS.state_bit_0 ; SA[7]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.904 ; +; -8.231 ; IS.state_bit_0 ; SA[6]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.898 ; +; -8.226 ; RAMSpecSELr ; SA[9]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.115 ; +; -8.222 ; RAMSpecSELr ; SA[11]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.111 ; +; -8.222 ; RAMSpecSELr ; SA[12]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.778 ; 6.111 ; +; -8.177 ; IS.state_bit_1 ; SA[2]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.844 ; +; -8.116 ; LS[9] ; IS.state_bit_0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.783 ; +; -8.115 ; PS[0] ; SA[2]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.782 ; +; -8.106 ; RAMSpecSELr ; SA[4]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.778 ; 5.995 ; +; -8.104 ; RAMSpecSELr ; SA[3]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.778 ; 5.993 ; +; -7.954 ; PS[0] ; SA[0]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.621 ; +; -7.928 ; IS.state_bit_1 ; SA[5]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.595 ; +; -7.900 ; RAMSpecSELr ; nRCS~reg0 ; PHI0 ; C25M ; 1.000 ; -2.778 ; 5.789 ; +; -7.896 ; PS[1] ; IS.state_bit_1 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.563 ; +; -7.878 ; PS[1] ; IOROMEN ; C25M ; C25M ; 1.000 ; 0.000 ; 8.545 ; +; -7.844 ; LS[1] ; nRCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.511 ; +; -7.817 ; IS.state_bit_1 ; RCKE~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.484 ; +; -7.817 ; PS[1] ; RCKE~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.484 ; +; -7.804 ; REGEN ; Addr[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.471 ; +; -7.804 ; REGEN ; Addr[1] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.471 ; +; -7.804 ; REGEN ; Addr[2] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.471 ; +; -7.804 ; REGEN ; Addr[3] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.471 ; +; -7.804 ; REGEN ; Addr[4] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.471 ; +; -7.804 ; REGEN ; Addr[5] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.471 ; +; -7.804 ; REGEN ; Addr[6] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.471 ; +; -7.804 ; REGEN ; Addr[7] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.471 ; +; -7.801 ; REGEN ; Addr[10] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.468 ; +; -7.801 ; REGEN ; Addr[11] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.468 ; +; -7.801 ; REGEN ; Addr[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.468 ; +; -7.801 ; REGEN ; Addr[13] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.468 ; +; -7.801 ; REGEN ; Addr[14] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.468 ; +; -7.801 ; REGEN ; Addr[15] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.468 ; +; -7.801 ; REGEN ; Addr[8] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.468 ; +; -7.801 ; REGEN ; Addr[9] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.468 ; +; -7.785 ; LS[10] ; IS.state_bit_2 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.452 ; +; -7.783 ; IS.state_bit_0 ; SA[2]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.450 ; +; -7.775 ; IS.state_bit_1 ; SA[1]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.442 ; +; -7.769 ; REGEN ; AddrIncH ; C25M ; C25M ; 1.000 ; 0.000 ; 8.436 ; +; -7.762 ; IS.state_bit_1 ; SA[4]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.429 ; +; -7.760 ; IS.state_bit_1 ; SA[3]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.427 ; +; -7.741 ; LS[8] ; IS.state_bit_0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.408 ; +; -7.706 ; PS[3] ; SA[8]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.373 ; +; -7.704 ; LS[7] ; IS.state_bit_0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.371 ; +; -7.680 ; IS.state_bit_1 ; SA[0]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.347 ; +; -7.668 ; PS[0] ; SA[1]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.335 ; +; -7.662 ; PS[3] ; SA[6]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.329 ; +; -7.654 ; PS[3] ; SA[7]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.321 ; +; -7.645 ; PS[1] ; REGEN ; C25M ; C25M ; 1.000 ; 0.000 ; 8.312 ; +; -7.643 ; REGEN ; Addr[23] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.310 ; +; -7.643 ; REGEN ; Addr[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.310 ; +; -7.643 ; REGEN ; Addr[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.310 ; +; -7.643 ; REGEN ; Addr[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.310 ; +; -7.643 ; REGEN ; Addr[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.310 ; +; -7.643 ; REGEN ; Addr[20] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.310 ; +; -7.643 ; REGEN ; Addr[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.310 ; +; -7.643 ; REGEN ; Addr[22] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.310 ; +; -7.642 ; LS[1] ; IS.state_bit_0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.309 ; +--------+----------------+----------------+--------------+-------------+--------------+------------+------------+ @@ -275,11 +275,11 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ -; -0.019 ; Addr[23] ; RAMSpecSELr ; C25M ; PHI0 ; 1.000 ; 3.356 ; 4.042 ; -; 0.199 ; SetFWr[1] ; RAMSpecSELr ; C25M ; PHI0 ; 1.000 ; 3.356 ; 3.824 ; -; 0.240 ; REGEN ; RAMSpecSELr ; C25M ; PHI0 ; 1.000 ; 3.356 ; 3.783 ; -; 0.435 ; SetFWr[0] ; RAMSpecSELr ; C25M ; PHI0 ; 1.000 ; 3.356 ; 3.588 ; -; 1.398 ; IOROMEN ; ROMSpecRDr ; C25M ; PHI0 ; 1.000 ; 3.356 ; 2.625 ; +; -0.425 ; Addr[23] ; RAMSpecSELr ; C25M ; PHI0 ; 1.000 ; 2.778 ; 3.870 ; +; -0.265 ; REGEN ; RAMSpecSELr ; C25M ; PHI0 ; 1.000 ; 2.778 ; 3.710 ; +; 0.296 ; IOROMEN ; ROMSpecRDr ; C25M ; PHI0 ; 1.000 ; 2.778 ; 3.149 ; +; 0.609 ; SetFWr[0] ; RAMSpecSELr ; C25M ; PHI0 ; 1.000 ; 2.778 ; 2.836 ; +; 0.694 ; SetFWr[1] ; RAMSpecSELr ; C25M ; PHI0 ; 1.000 ; 2.778 ; 2.751 ; +--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ @@ -288,11 +288,11 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ -; -0.952 ; IOROMEN ; ROMSpecRDr ; C25M ; PHI0 ; 0.000 ; 3.356 ; 2.625 ; -; 0.011 ; SetFWr[0] ; RAMSpecSELr ; C25M ; PHI0 ; 0.000 ; 3.356 ; 3.588 ; -; 0.206 ; REGEN ; RAMSpecSELr ; C25M ; PHI0 ; 0.000 ; 3.356 ; 3.783 ; -; 0.247 ; SetFWr[1] ; RAMSpecSELr ; C25M ; PHI0 ; 0.000 ; 3.356 ; 3.824 ; -; 0.465 ; Addr[23] ; RAMSpecSELr ; C25M ; PHI0 ; 0.000 ; 3.356 ; 4.042 ; +; -0.248 ; SetFWr[1] ; RAMSpecSELr ; C25M ; PHI0 ; 0.000 ; 2.778 ; 2.751 ; +; -0.163 ; SetFWr[0] ; RAMSpecSELr ; C25M ; PHI0 ; 0.000 ; 2.778 ; 2.836 ; +; 0.150 ; IOROMEN ; ROMSpecRDr ; C25M ; PHI0 ; 0.000 ; 2.778 ; 3.149 ; +; 0.711 ; REGEN ; RAMSpecSELr ; C25M ; PHI0 ; 0.000 ; 2.778 ; 3.710 ; +; 0.871 ; Addr[23] ; RAMSpecSELr ; C25M ; PHI0 ; 0.000 ; 2.778 ; 3.870 ; +--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ @@ -301,106 +301,106 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+----------------+----------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +-------+----------------+----------------+--------------+-------------+--------------+------------+------------+ -; 1.385 ; WRD[0] ; WRD[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.606 ; -; 1.403 ; WRD[5] ; WRD[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.624 ; -; 1.408 ; nRESf[1] ; nRESf[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.629 ; -; 1.411 ; WRD[7] ; WRD[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.632 ; -; 1.420 ; WRD[4] ; WRD[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.641 ; -; 1.422 ; WRD[2] ; WRD[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.643 ; -; 1.528 ; PHI0 ; PHI0r1 ; PHI0 ; C25M ; 0.000 ; 3.458 ; 5.207 ; -; 1.639 ; nRESout~reg0 ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 1.860 ; -; 1.669 ; nRESf[2] ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 1.890 ; -; 1.693 ; PS[3] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.914 ; -; 1.799 ; WRD[6] ; WRD[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.020 ; -; 1.830 ; nRESf[0] ; nRESf[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.051 ; -; 1.837 ; WRD[3] ; WRD[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.058 ; -; 1.854 ; WRD[1] ; WRD[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.075 ; -; 1.929 ; nRESf[1] ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 2.150 ; -; 1.970 ; IS.state_bit_0 ; IS.state_bit_0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.191 ; -; 1.980 ; PS[2] ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.201 ; -; 1.988 ; PS[2] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.209 ; -; 2.028 ; PHI0 ; PHI0r1 ; PHI0 ; C25M ; -0.500 ; 3.458 ; 5.207 ; +; 1.400 ; WRD[7] ; WRD[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.621 ; +; 1.411 ; WRD[4] ; WRD[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.632 ; +; 1.412 ; WRD[6] ; WRD[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.633 ; +; 1.414 ; nRESf[2] ; nRESf[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.635 ; +; 1.420 ; WRD[0] ; WRD[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.641 ; +; 1.420 ; WRD[3] ; WRD[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.641 ; +; 1.640 ; nRESout~reg0 ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 1.861 ; +; 1.782 ; WRD[2] ; WRD[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.003 ; +; 1.822 ; nRESf[1] ; nRESf[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.043 ; +; 1.930 ; Addr[7] ; AddrIncM ; C25M ; C25M ; 0.000 ; 0.000 ; 2.151 ; +; 1.933 ; nRESf[2] ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 2.154 ; +; 2.063 ; LS[13] ; LS[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.284 ; +; 2.075 ; nRESf[3] ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 2.296 ; +; 2.107 ; LS[7] ; LS[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.328 ; ; 2.117 ; Addr[10] ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; ; 2.117 ; Addr[1] ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; ; 2.117 ; Addr[2] ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; -; 2.117 ; LS[4] ; LS[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; -; 2.117 ; Addr[17] ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; -; 2.117 ; Addr[18] ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; +; 2.117 ; Bank ; Bank ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; +; 2.117 ; Addr[15] ; Addr[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; +; 2.117 ; LS[8] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; +; 2.117 ; LS[9] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; ; 2.117 ; Addr[9] ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; +; 2.120 ; WRD[1] ; WRD[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.341 ; +; 2.123 ; WRD[2] ; WRD[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.344 ; +; 2.124 ; Addr[16] ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.345 ; ; 2.125 ; Addr[0] ; Addr[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.346 ; -; 2.125 ; Addr[16] ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.346 ; -; 2.126 ; Addr[23] ; Addr[23] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ; -; 2.126 ; Addr[7] ; Addr[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ; -; 2.127 ; LS[6] ; LS[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.348 ; -; 2.132 ; Addr[8] ; Addr[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.353 ; -; 2.133 ; LS[7] ; LS[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.354 ; -; 2.134 ; LS[0] ; LS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.355 ; -; 2.135 ; Addr[15] ; Addr[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.356 ; -; 2.139 ; LS[0] ; LS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.360 ; -; 2.142 ; LS[8] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.363 ; -; 2.142 ; WRD[5] ; WRD[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.363 ; -; 2.143 ; nRESf[0] ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 2.364 ; -; 2.145 ; LS[9] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.366 ; -; 2.189 ; PS[2] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.410 ; -; 2.221 ; Bank ; Bank ; C25M ; C25M ; 0.000 ; 0.000 ; 2.442 ; -; 2.221 ; LS[5] ; LS[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.442 ; -; 2.221 ; Addr[19] ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.442 ; -; 2.222 ; Addr[11] ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.443 ; -; 2.230 ; LS[2] ; LS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.451 ; -; 2.230 ; Addr[13] ; Addr[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.451 ; +; 2.126 ; LS[4] ; LS[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ; +; 2.126 ; LS[6] ; LS[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ; +; 2.126 ; Addr[17] ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ; +; 2.127 ; Addr[23] ; Addr[23] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.348 ; +; 2.127 ; Addr[18] ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.348 ; +; 2.137 ; Addr[7] ; Addr[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.358 ; +; 2.151 ; WRD[4] ; WRD[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.372 ; +; 2.155 ; nRESf[1] ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 2.376 ; +; 2.162 ; PS[2] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.383 ; +; 2.164 ; PS[3] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.385 ; +; 2.175 ; PS[3] ; nRAS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.396 ; +; 2.215 ; nRESf[0] ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 2.436 ; +; 2.222 ; Addr[19] ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.443 ; +; 2.226 ; PHI0 ; PHI0r1 ; PHI0 ; C25M ; 0.000 ; 3.458 ; 5.905 ; +; 2.228 ; AddrIncH ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.449 ; +; 2.230 ; Addr[5] ; Addr[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.451 ; ; 2.230 ; Addr[21] ; Addr[21] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.451 ; -; 2.231 ; LS[1] ; LS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; -; 2.231 ; Addr[12] ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; -; 2.231 ; LS[3] ; LS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; -; 2.231 ; Addr[14] ; Addr[14] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; +; 2.231 ; Addr[3] ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; +; 2.231 ; Addr[4] ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; +; 2.231 ; Addr[6] ; Addr[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; ; 2.231 ; Addr[20] ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; ; 2.231 ; Addr[22] ; Addr[22] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; -; 2.236 ; nRESf[3] ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 2.457 ; -; 2.239 ; LS[12] ; LS[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.460 ; -; 2.239 ; LS[13] ; LS[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.460 ; -; 2.241 ; Addr[3] ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.462 ; -; 2.249 ; Addr[6] ; Addr[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.470 ; +; 2.232 ; LS[10] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.453 ; +; 2.240 ; LS[3] ; LS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.461 ; +; 2.241 ; Addr[11] ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.462 ; +; 2.248 ; LS[12] ; LS[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.469 ; +; 2.249 ; Addr[12] ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.470 ; +; 2.249 ; LS[5] ; LS[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.470 ; ; 2.250 ; LS[11] ; LS[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.471 ; -; 2.253 ; LS[10] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.474 ; -; 2.260 ; WRD[2] ; WRD[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.481 ; -; 2.261 ; Addr[4] ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.482 ; -; 2.261 ; Addr[5] ; Addr[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.482 ; -; 2.264 ; WRD[4] ; WRD[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.485 ; -; 2.304 ; SetFWLoaded ; SetFWr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.525 ; -; 2.304 ; SetFWLoaded ; SetFWr[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.525 ; -; 2.327 ; PS[0] ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.548 ; -; 2.333 ; PS[0] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.554 ; -; 2.343 ; PS[0] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.564 ; -; 2.386 ; PS[3] ; nSWE~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.607 ; -; 2.394 ; PS[3] ; FCKout ; C25M ; C25M ; 0.000 ; 0.000 ; 2.615 ; -; 2.505 ; nRESf[2] ; nRESf[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.726 ; -; 2.511 ; Addr[15] ; AddrIncH ; C25M ; C25M ; 0.000 ; 0.000 ; 2.732 ; -; 2.603 ; PS[3] ; nCAS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.824 ; -; 2.603 ; AddrIncH ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.824 ; -; 2.665 ; IS.state_bit_1 ; IS.state_bit_0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.886 ; -; 2.679 ; WRD[3] ; WRD[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.900 ; -; 2.690 ; WRD[1] ; WRD[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.911 ; -; 2.910 ; PS[0] ; FCKout ; C25M ; C25M ; 0.000 ; 0.000 ; 3.131 ; -; 2.915 ; PS[0] ; nCAS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.136 ; +; 2.251 ; LS[2] ; LS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.472 ; +; 2.251 ; LS[0] ; LS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.472 ; +; 2.252 ; LS[0] ; LS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.473 ; +; 2.260 ; Addr[13] ; Addr[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.481 ; +; 2.262 ; Addr[14] ; Addr[14] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.483 ; +; 2.263 ; WRD[3] ; WRD[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.484 ; +; 2.267 ; WRD[0] ; WRD[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.488 ; +; 2.285 ; WRD[5] ; WRD[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.506 ; +; 2.297 ; IS.state_bit_0 ; IS.state_bit_0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.518 ; +; 2.421 ; nRESf[0] ; nRESf[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.642 ; +; 2.423 ; WRD[1] ; WRD[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.644 ; +; 2.532 ; PS[0] ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.753 ; +; 2.534 ; PS[0] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.755 ; +; 2.537 ; PS[0] ; nRAS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.758 ; +; 2.538 ; PHI0r1 ; PHI0r2 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.759 ; +; 2.545 ; PS[0] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.766 ; +; 2.559 ; Addr[2] ; RDD[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.780 ; +; 2.606 ; AddrIncL ; Addr[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.827 ; +; 2.680 ; Addr[1] ; RDD[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.901 ; +; 2.699 ; PS[2] ; nRAS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.920 ; +; 2.702 ; PS[2] ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.923 ; +; 2.703 ; PS[2] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.924 ; +; 2.726 ; PHI0 ; PHI0r1 ; PHI0 ; C25M ; -0.500 ; 3.458 ; 5.905 ; +; 2.826 ; PHI0r1 ; RCKE~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.047 ; +; 2.860 ; Addr[3] ; RDD[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.081 ; +; 2.905 ; IS.state_bit_0 ; FCS ; C25M ; C25M ; 0.000 ; 0.000 ; 3.126 ; +; 2.939 ; LS[7] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.160 ; ; 2.949 ; Addr[9] ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; +; 2.949 ; LS[9] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; ; 2.949 ; Addr[10] ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; ; 2.949 ; Addr[1] ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; ; 2.949 ; Addr[2] ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; -; 2.949 ; LS[4] ; LS[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; -; 2.949 ; Addr[17] ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; -; 2.949 ; Addr[18] ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; +; 2.949 ; LS[8] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; +; 2.956 ; Addr[16] ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.177 ; ; 2.957 ; Addr[0] ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.178 ; -; 2.957 ; Addr[16] ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.178 ; -; 2.964 ; Addr[8] ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.185 ; -; 2.965 ; LS[7] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.186 ; -; 2.974 ; LS[8] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.195 ; -; 2.977 ; LS[9] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.198 ; -; 2.983 ; PS[1] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.204 ; -; 3.014 ; PHI0r1 ; PHI0r2 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.235 ; -; 3.021 ; IS.state_bit_2 ; IS.state_bit_2 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.242 ; +; 2.958 ; LS[4] ; LS[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.179 ; +; 2.958 ; Addr[17] ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.179 ; +; 2.959 ; Addr[18] ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.180 ; +; 3.011 ; IS.state_bit_0 ; FCKOE ; C25M ; C25M ; 0.000 ; 0.000 ; 3.232 ; +; 3.014 ; IS.state_bit_0 ; MOSIOE ; C25M ; C25M ; 0.000 ; 0.000 ; 3.235 ; +; 3.050 ; LS[7] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.271 ; +; 3.060 ; LS[9] ; LS[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ; ; 3.060 ; Addr[10] ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ; ; 3.060 ; Addr[2] ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ; -; 3.060 ; LS[4] ; LS[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ; +; 3.060 ; LS[8] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ; +-------+----------------+----------------+--------------+-------------+--------------+------------+------------+ @@ -409,35 +409,35 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +--------+-----------+----------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+-----------+----------+--------------+-------------+--------------+------------+------------+ -; -4.389 ; nRESr ; Addr[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.056 ; -; -4.389 ; nRESr ; Addr[23] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.056 ; -; -4.389 ; nRESr ; Addr[10] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.056 ; -; -4.389 ; nRESr ; Addr[1] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.056 ; -; -4.389 ; nRESr ; Addr[11] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.056 ; -; -4.389 ; nRESr ; Addr[2] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.056 ; -; -4.389 ; nRESr ; Addr[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.056 ; -; -4.389 ; nRESr ; Bank ; C25M ; C25M ; 1.000 ; 0.000 ; 5.056 ; -; -4.389 ; nRESr ; Addr[3] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.056 ; -; -4.389 ; nRESr ; Addr[13] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.056 ; -; -4.389 ; nRESr ; Addr[4] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.056 ; -; -4.389 ; nRESr ; Addr[14] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.056 ; -; -4.389 ; nRESr ; Addr[5] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.056 ; -; -4.389 ; nRESr ; Addr[15] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.056 ; -; -4.389 ; nRESr ; Addr[6] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.056 ; -; -4.389 ; nRESr ; Addr[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.056 ; -; -4.389 ; nRESr ; Addr[7] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.056 ; -; -4.389 ; nRESr ; Addr[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.056 ; -; -4.389 ; nRESr ; Addr[8] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.056 ; -; -4.389 ; nRESr ; Addr[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.056 ; -; -4.389 ; nRESr ; Addr[9] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.056 ; -; -4.389 ; nRESr ; Addr[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.056 ; -; -4.389 ; nRESr ; Addr[20] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.056 ; -; -4.389 ; nRESr ; Addr[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.056 ; -; -4.389 ; nRESr ; Addr[22] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.056 ; -; -4.389 ; nRESr ; REGEN ; C25M ; C25M ; 1.000 ; 0.000 ; 5.056 ; -; -4.389 ; nRESr ; AddrIncH ; C25M ; C25M ; 1.000 ; 0.000 ; 5.056 ; -; -4.389 ; nRESr ; AddrIncM ; C25M ; C25M ; 1.000 ; 0.000 ; 5.056 ; -; -4.389 ; nRESr ; AddrIncL ; C25M ; C25M ; 1.000 ; 0.000 ; 5.056 ; +; -4.412 ; nRESr ; Addr[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; +; -4.412 ; nRESr ; Addr[23] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; +; -4.412 ; nRESr ; Addr[10] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; +; -4.412 ; nRESr ; Addr[1] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; +; -4.412 ; nRESr ; Addr[11] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; +; -4.412 ; nRESr ; Addr[2] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; +; -4.412 ; nRESr ; Addr[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; +; -4.412 ; nRESr ; Bank ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; +; -4.412 ; nRESr ; Addr[3] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; +; -4.412 ; nRESr ; Addr[13] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; +; -4.412 ; nRESr ; Addr[4] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; +; -4.412 ; nRESr ; Addr[14] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; +; -4.412 ; nRESr ; Addr[5] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; +; -4.412 ; nRESr ; Addr[15] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; +; -4.412 ; nRESr ; Addr[6] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; +; -4.412 ; nRESr ; Addr[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; +; -4.412 ; nRESr ; Addr[7] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; +; -4.412 ; nRESr ; Addr[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; +; -4.412 ; nRESr ; Addr[8] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; +; -4.412 ; nRESr ; Addr[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; +; -4.412 ; nRESr ; Addr[9] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; +; -4.412 ; nRESr ; Addr[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; +; -4.412 ; nRESr ; Addr[20] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; +; -4.412 ; nRESr ; Addr[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; +; -4.412 ; nRESr ; Addr[22] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; +; -4.412 ; nRESr ; REGEN ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; +; -4.412 ; nRESr ; AddrIncH ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; +; -4.412 ; nRESr ; AddrIncM ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; +; -4.412 ; nRESr ; AddrIncL ; C25M ; C25M ; 1.000 ; 0.000 ; 5.079 ; +--------+-----------+----------+--------------+-------------+--------------+------------+------------+ @@ -446,61 +446,38 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+-----------+----------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +-------+-----------+----------+--------------+-------------+--------------+------------+------------+ -; 4.835 ; nRESr ; Addr[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.056 ; -; 4.835 ; nRESr ; Addr[23] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.056 ; -; 4.835 ; nRESr ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.056 ; -; 4.835 ; nRESr ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.056 ; -; 4.835 ; nRESr ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.056 ; -; 4.835 ; nRESr ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.056 ; -; 4.835 ; nRESr ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.056 ; -; 4.835 ; nRESr ; Bank ; C25M ; C25M ; 0.000 ; 0.000 ; 5.056 ; -; 4.835 ; nRESr ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.056 ; -; 4.835 ; nRESr ; Addr[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.056 ; -; 4.835 ; nRESr ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.056 ; -; 4.835 ; nRESr ; Addr[14] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.056 ; -; 4.835 ; nRESr ; Addr[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.056 ; -; 4.835 ; nRESr ; Addr[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.056 ; -; 4.835 ; nRESr ; Addr[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.056 ; -; 4.835 ; nRESr ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.056 ; -; 4.835 ; nRESr ; Addr[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.056 ; -; 4.835 ; nRESr ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.056 ; -; 4.835 ; nRESr ; Addr[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.056 ; -; 4.835 ; nRESr ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.056 ; -; 4.835 ; nRESr ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.056 ; -; 4.835 ; nRESr ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.056 ; -; 4.835 ; nRESr ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.056 ; -; 4.835 ; nRESr ; Addr[21] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.056 ; -; 4.835 ; nRESr ; Addr[22] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.056 ; -; 4.835 ; nRESr ; REGEN ; C25M ; C25M ; 0.000 ; 0.000 ; 5.056 ; -; 4.835 ; nRESr ; AddrIncH ; C25M ; C25M ; 0.000 ; 0.000 ; 5.056 ; -; 4.835 ; nRESr ; AddrIncM ; C25M ; C25M ; 0.000 ; 0.000 ; 5.056 ; -; 4.835 ; nRESr ; AddrIncL ; C25M ; C25M ; 0.000 ; 0.000 ; 5.056 ; +; 4.858 ; nRESr ; Addr[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; +; 4.858 ; nRESr ; Addr[23] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; +; 4.858 ; nRESr ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; +; 4.858 ; nRESr ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; +; 4.858 ; nRESr ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; +; 4.858 ; nRESr ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; +; 4.858 ; nRESr ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; +; 4.858 ; nRESr ; Bank ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; +; 4.858 ; nRESr ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; +; 4.858 ; nRESr ; Addr[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; +; 4.858 ; nRESr ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; +; 4.858 ; nRESr ; Addr[14] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; +; 4.858 ; nRESr ; Addr[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; +; 4.858 ; nRESr ; Addr[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; +; 4.858 ; nRESr ; Addr[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; +; 4.858 ; nRESr ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; +; 4.858 ; nRESr ; Addr[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; +; 4.858 ; nRESr ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; +; 4.858 ; nRESr ; Addr[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; +; 4.858 ; nRESr ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; +; 4.858 ; nRESr ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; +; 4.858 ; nRESr ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; +; 4.858 ; nRESr ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; +; 4.858 ; nRESr ; Addr[21] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; +; 4.858 ; nRESr ; Addr[22] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; +; 4.858 ; nRESr ; REGEN ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; +; 4.858 ; nRESr ; AddrIncH ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; +; 4.858 ; nRESr ; AddrIncM ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; +; 4.858 ; nRESr ; AddrIncL ; C25M ; C25M ; 0.000 ; 0.000 ; 5.079 ; +-------+-----------+----------+--------------+-------------+--------------+------------+------------+ -+--------------------------------------------------------------------------------------------------+ -; Minimum Pulse Width: 'PHI0' ; -+--------+--------------+----------------+------------------+-------+------------+-----------------+ -; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; -+--------+--------------+----------------+------------------+-------+------------+-----------------+ -; -3.000 ; 1.000 ; 4.000 ; Port Rate ; PHI0 ; Rise ; PHI0 ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI0 ; Rise ; RAMSpecSELr ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI0 ; Rise ; RAMSpecSELr ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI0 ; Rise ; ROMSpecRDr ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI0 ; Rise ; ROMSpecRDr ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI0 ; Rise ; nWEr ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI0 ; Rise ; nWEr ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI0 ; Rise ; PHI0|combout ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI0 ; Rise ; PHI0|combout ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI0 ; Rise ; RAMSpecSELr|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI0 ; Rise ; RAMSpecSELr|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI0 ; Rise ; ROMSpecRDr|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI0 ; Rise ; ROMSpecRDr|clk ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI0 ; Rise ; nWEr|clk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI0 ; Rise ; nWEr|clk ; -+--------+--------------+----------------+------------------+-------+------------+-----------------+ - - +-------------------------------------------------------------------------------------------------+ ; Minimum Pulse Width: 'C25M' ; +--------+--------------+----------------+------------------+-------+------------+----------------+ @@ -609,70 +586,93 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +--------+--------------+----------------+------------------+-------+------------+----------------+ ++--------------------------------------------------------------------------------------------------+ +; Minimum Pulse Width: 'PHI0' ; ++--------+--------------+----------------+------------------+-------+------------+-----------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++--------+--------------+----------------+------------------+-------+------------+-----------------+ +; -2.289 ; 1.000 ; 3.289 ; Port Rate ; PHI0 ; Rise ; PHI0 ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI0 ; Rise ; RAMSpecSELr ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI0 ; Rise ; RAMSpecSELr ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI0 ; Rise ; ROMSpecRDr ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI0 ; Rise ; ROMSpecRDr ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; PHI0 ; Rise ; nWEr ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; PHI0 ; Rise ; nWEr ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI0 ; Rise ; PHI0|combout ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI0 ; Rise ; PHI0|combout ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI0 ; Rise ; RAMSpecSELr|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI0 ; Rise ; RAMSpecSELr|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI0 ; Rise ; ROMSpecRDr|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI0 ; Rise ; ROMSpecRDr|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; PHI0 ; Rise ; nWEr|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; PHI0 ; Rise ; nWEr|clk ; ++--------+--------------+----------------+------------------+-------+------------+-----------------+ + + +-------------------------------------------------------------------------+ ; Setup Times ; +-----------+------------+--------+--------+------------+-----------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+--------+--------+------------+-----------------+ -; MISO ; C25M ; 4.359 ; 4.359 ; Rise ; C25M ; -; MOSI ; C25M ; 3.815 ; 3.815 ; Rise ; C25M ; -; PHI0 ; C25M ; 2.082 ; 2.082 ; Rise ; C25M ; -; RA[*] ; C25M ; 15.080 ; 15.080 ; Rise ; C25M ; -; RA[0] ; C25M ; 11.450 ; 11.450 ; Rise ; C25M ; -; RA[1] ; C25M ; 11.872 ; 11.872 ; Rise ; C25M ; -; RA[2] ; C25M ; 12.318 ; 12.318 ; Rise ; C25M ; -; RA[3] ; C25M ; 12.512 ; 12.512 ; Rise ; C25M ; -; RA[4] ; C25M ; 4.218 ; 4.218 ; Rise ; C25M ; -; RA[5] ; C25M ; 4.095 ; 4.095 ; Rise ; C25M ; -; RA[6] ; C25M ; 7.190 ; 7.190 ; Rise ; C25M ; -; RA[7] ; C25M ; 11.083 ; 11.083 ; Rise ; C25M ; -; RA[8] ; C25M ; 14.785 ; 14.785 ; Rise ; C25M ; -; RA[9] ; C25M ; 15.080 ; 15.080 ; Rise ; C25M ; -; RA[10] ; C25M ; 14.244 ; 14.244 ; Rise ; C25M ; -; RA[11] ; C25M ; 13.759 ; 13.759 ; Rise ; C25M ; -; RA[12] ; C25M ; 13.957 ; 13.957 ; Rise ; C25M ; -; RA[13] ; C25M ; 13.581 ; 13.581 ; Rise ; C25M ; -; RA[14] ; C25M ; 14.176 ; 14.176 ; Rise ; C25M ; -; RA[15] ; C25M ; 13.840 ; 13.840 ; Rise ; C25M ; -; RD[*] ; C25M ; 6.977 ; 6.977 ; Rise ; C25M ; -; RD[0] ; C25M ; 5.107 ; 5.107 ; Rise ; C25M ; -; RD[1] ; C25M ; 4.952 ; 4.952 ; Rise ; C25M ; -; RD[2] ; C25M ; 4.030 ; 4.030 ; Rise ; C25M ; -; RD[3] ; C25M ; 4.999 ; 4.999 ; Rise ; C25M ; -; RD[4] ; C25M ; 4.626 ; 4.626 ; Rise ; C25M ; -; RD[5] ; C25M ; 4.884 ; 4.884 ; Rise ; C25M ; -; RD[6] ; C25M ; 4.342 ; 4.342 ; Rise ; C25M ; -; RD[7] ; C25M ; 6.977 ; 6.977 ; Rise ; C25M ; -; SD[*] ; C25M ; 4.986 ; 4.986 ; Rise ; C25M ; -; SD[0] ; C25M ; 4.013 ; 4.013 ; Rise ; C25M ; -; SD[1] ; C25M ; 3.828 ; 3.828 ; Rise ; C25M ; -; SD[2] ; C25M ; 4.512 ; 4.512 ; Rise ; C25M ; -; SD[3] ; C25M ; 4.986 ; 4.986 ; Rise ; C25M ; -; SD[4] ; C25M ; 3.734 ; 3.734 ; Rise ; C25M ; -; SD[5] ; C25M ; 3.155 ; 3.155 ; Rise ; C25M ; -; SD[6] ; C25M ; 3.852 ; 3.852 ; Rise ; C25M ; -; SD[7] ; C25M ; 3.130 ; 3.130 ; Rise ; C25M ; -; SetFW[*] ; C25M ; 3.137 ; 3.137 ; Rise ; C25M ; -; SetFW[0] ; C25M ; 3.081 ; 3.081 ; Rise ; C25M ; -; SetFW[1] ; C25M ; 3.137 ; 3.137 ; Rise ; C25M ; -; nDEVSEL ; C25M ; 8.929 ; 8.929 ; Rise ; C25M ; -; nIOSEL ; C25M ; 6.968 ; 6.968 ; Rise ; C25M ; -; nRES ; C25M ; 4.261 ; 4.261 ; Rise ; C25M ; -; RA[*] ; PHI0 ; 6.194 ; 6.194 ; Rise ; PHI0 ; -; RA[0] ; PHI0 ; 3.047 ; 3.047 ; Rise ; PHI0 ; -; RA[1] ; PHI0 ; 3.453 ; 3.453 ; Rise ; PHI0 ; -; RA[2] ; PHI0 ; 3.907 ; 3.907 ; Rise ; PHI0 ; -; RA[3] ; PHI0 ; 4.101 ; 4.101 ; Rise ; PHI0 ; -; RA[7] ; PHI0 ; 2.197 ; 2.197 ; Rise ; PHI0 ; -; RA[8] ; PHI0 ; 5.899 ; 5.899 ; Rise ; PHI0 ; -; RA[9] ; PHI0 ; 6.194 ; 6.194 ; Rise ; PHI0 ; -; RA[10] ; PHI0 ; 5.358 ; 5.358 ; Rise ; PHI0 ; -; RA[11] ; PHI0 ; 4.873 ; 4.873 ; Rise ; PHI0 ; -; RA[12] ; PHI0 ; 5.071 ; 5.071 ; Rise ; PHI0 ; -; RA[13] ; PHI0 ; 4.695 ; 4.695 ; Rise ; PHI0 ; -; RA[14] ; PHI0 ; 5.290 ; 5.290 ; Rise ; PHI0 ; -; RA[15] ; PHI0 ; 4.954 ; 4.954 ; Rise ; PHI0 ; -; nWE ; PHI0 ; 0.526 ; 0.526 ; Rise ; PHI0 ; +; MISO ; C25M ; 4.236 ; 4.236 ; Rise ; C25M ; +; MOSI ; C25M ; 4.174 ; 4.174 ; Rise ; C25M ; +; PHI0 ; C25M ; 2.780 ; 2.780 ; Rise ; C25M ; +; RA[*] ; C25M ; 13.704 ; 13.704 ; Rise ; C25M ; +; RA[0] ; C25M ; 9.040 ; 9.040 ; Rise ; C25M ; +; RA[1] ; C25M ; 10.111 ; 10.111 ; Rise ; C25M ; +; RA[2] ; C25M ; 11.221 ; 11.221 ; Rise ; C25M ; +; RA[3] ; C25M ; 11.322 ; 11.322 ; Rise ; C25M ; +; RA[4] ; C25M ; 6.069 ; 6.069 ; Rise ; C25M ; +; RA[5] ; C25M ; 5.790 ; 5.790 ; Rise ; C25M ; +; RA[6] ; C25M ; 7.139 ; 7.139 ; Rise ; C25M ; +; RA[7] ; C25M ; 10.088 ; 10.088 ; Rise ; C25M ; +; RA[8] ; C25M ; 13.349 ; 13.349 ; Rise ; C25M ; +; RA[9] ; C25M ; 13.704 ; 13.704 ; Rise ; C25M ; +; RA[10] ; C25M ; 12.357 ; 12.357 ; Rise ; C25M ; +; RA[11] ; C25M ; 12.145 ; 12.145 ; Rise ; C25M ; +; RA[12] ; C25M ; 12.246 ; 12.246 ; Rise ; C25M ; +; RA[13] ; C25M ; 11.874 ; 11.874 ; Rise ; C25M ; +; RA[14] ; C25M ; 12.544 ; 12.544 ; Rise ; C25M ; +; RA[15] ; C25M ; 11.995 ; 11.995 ; Rise ; C25M ; +; RD[*] ; C25M ; 6.903 ; 6.903 ; Rise ; C25M ; +; RD[0] ; C25M ; 4.401 ; 4.401 ; Rise ; C25M ; +; RD[1] ; C25M ; 4.653 ; 4.653 ; Rise ; C25M ; +; RD[2] ; C25M ; 3.968 ; 3.968 ; Rise ; C25M ; +; RD[3] ; C25M ; 4.146 ; 4.146 ; Rise ; C25M ; +; RD[4] ; C25M ; 4.101 ; 4.101 ; Rise ; C25M ; +; RD[5] ; C25M ; 4.868 ; 4.868 ; Rise ; C25M ; +; RD[6] ; C25M ; 4.516 ; 4.516 ; Rise ; C25M ; +; RD[7] ; C25M ; 6.903 ; 6.903 ; Rise ; C25M ; +; SD[*] ; C25M ; 5.643 ; 5.643 ; Rise ; C25M ; +; SD[0] ; C25M ; 4.467 ; 4.467 ; Rise ; C25M ; +; SD[1] ; C25M ; 5.643 ; 5.643 ; Rise ; C25M ; +; SD[2] ; C25M ; 3.772 ; 3.772 ; Rise ; C25M ; +; SD[3] ; C25M ; 3.824 ; 3.824 ; Rise ; C25M ; +; SD[4] ; C25M ; 4.593 ; 4.593 ; Rise ; C25M ; +; SD[5] ; C25M ; 4.266 ; 4.266 ; Rise ; C25M ; +; SD[6] ; C25M ; 3.851 ; 3.851 ; Rise ; C25M ; +; SD[7] ; C25M ; 3.789 ; 3.789 ; Rise ; C25M ; +; SetFW[*] ; C25M ; 3.175 ; 3.175 ; Rise ; C25M ; +; SetFW[0] ; C25M ; 2.614 ; 2.614 ; Rise ; C25M ; +; SetFW[1] ; C25M ; 3.175 ; 3.175 ; Rise ; C25M ; +; nDEVSEL ; C25M ; 8.361 ; 8.361 ; Rise ; C25M ; +; nIOSEL ; C25M ; 6.803 ; 6.803 ; Rise ; C25M ; +; nRES ; C25M ; 3.239 ; 3.239 ; Rise ; C25M ; +; RA[*] ; PHI0 ; 6.165 ; 6.165 ; Rise ; PHI0 ; +; RA[0] ; PHI0 ; 3.454 ; 3.454 ; Rise ; PHI0 ; +; RA[1] ; PHI0 ; 2.966 ; 2.966 ; Rise ; PHI0 ; +; RA[2] ; PHI0 ; 4.328 ; 4.328 ; Rise ; PHI0 ; +; RA[3] ; PHI0 ; 4.429 ; 4.429 ; Rise ; PHI0 ; +; RA[7] ; PHI0 ; 2.549 ; 2.549 ; Rise ; PHI0 ; +; RA[8] ; PHI0 ; 5.810 ; 5.810 ; Rise ; PHI0 ; +; RA[9] ; PHI0 ; 6.165 ; 6.165 ; Rise ; PHI0 ; +; RA[10] ; PHI0 ; 4.818 ; 4.818 ; Rise ; PHI0 ; +; RA[11] ; PHI0 ; 4.606 ; 4.606 ; Rise ; PHI0 ; +; RA[12] ; PHI0 ; 4.707 ; 4.707 ; Rise ; PHI0 ; +; RA[13] ; PHI0 ; 4.335 ; 4.335 ; Rise ; PHI0 ; +; RA[14] ; PHI0 ; 5.005 ; 5.005 ; Rise ; PHI0 ; +; RA[15] ; PHI0 ; 4.456 ; 4.456 ; Rise ; PHI0 ; +; nWE ; PHI0 ; 1.098 ; 1.098 ; Rise ; PHI0 ; +-----------+------------+--------+--------+------------+-----------------+ @@ -681,65 +681,65 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-----------+------------+--------+--------+------------+-----------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+--------+--------+------------+-----------------+ -; MISO ; C25M ; -3.805 ; -3.805 ; Rise ; C25M ; -; MOSI ; C25M ; -3.261 ; -3.261 ; Rise ; C25M ; -; PHI0 ; C25M ; -1.528 ; -1.528 ; Rise ; C25M ; -; RA[*] ; C25M ; -3.541 ; -3.541 ; Rise ; C25M ; -; RA[0] ; C25M ; -4.263 ; -4.263 ; Rise ; C25M ; -; RA[1] ; C25M ; -5.567 ; -5.567 ; Rise ; C25M ; -; RA[2] ; C25M ; -6.235 ; -6.235 ; Rise ; C25M ; -; RA[3] ; C25M ; -6.303 ; -6.303 ; Rise ; C25M ; -; RA[4] ; C25M ; -3.664 ; -3.664 ; Rise ; C25M ; -; RA[5] ; C25M ; -3.541 ; -3.541 ; Rise ; C25M ; -; RA[6] ; C25M ; -6.636 ; -6.636 ; Rise ; C25M ; -; RA[7] ; C25M ; -4.295 ; -4.295 ; Rise ; C25M ; -; RA[8] ; C25M ; -6.632 ; -6.632 ; Rise ; C25M ; -; RA[9] ; C25M ; -4.838 ; -4.838 ; Rise ; C25M ; -; RA[10] ; C25M ; -7.310 ; -7.310 ; Rise ; C25M ; -; RA[11] ; C25M ; -4.354 ; -4.354 ; Rise ; C25M ; -; RA[12] ; C25M ; -9.256 ; -9.256 ; Rise ; C25M ; -; RA[13] ; C25M ; -8.880 ; -8.880 ; Rise ; C25M ; -; RA[14] ; C25M ; -9.475 ; -9.475 ; Rise ; C25M ; -; RA[15] ; C25M ; -9.139 ; -9.139 ; Rise ; C25M ; -; RD[*] ; C25M ; -2.059 ; -2.059 ; Rise ; C25M ; -; RD[0] ; C25M ; -2.588 ; -2.588 ; Rise ; C25M ; -; RD[1] ; C25M ; -2.059 ; -2.059 ; Rise ; C25M ; -; RD[2] ; C25M ; -2.146 ; -2.146 ; Rise ; C25M ; -; RD[3] ; C25M ; -2.715 ; -2.715 ; Rise ; C25M ; -; RD[4] ; C25M ; -3.241 ; -3.241 ; Rise ; C25M ; -; RD[5] ; C25M ; -2.090 ; -2.090 ; Rise ; C25M ; -; RD[6] ; C25M ; -3.446 ; -3.446 ; Rise ; C25M ; -; RD[7] ; C25M ; -3.443 ; -3.443 ; Rise ; C25M ; -; SD[*] ; C25M ; -2.576 ; -2.576 ; Rise ; C25M ; -; SD[0] ; C25M ; -3.459 ; -3.459 ; Rise ; C25M ; -; SD[1] ; C25M ; -3.274 ; -3.274 ; Rise ; C25M ; -; SD[2] ; C25M ; -3.958 ; -3.958 ; Rise ; C25M ; -; SD[3] ; C25M ; -4.432 ; -4.432 ; Rise ; C25M ; -; SD[4] ; C25M ; -3.180 ; -3.180 ; Rise ; C25M ; -; SD[5] ; C25M ; -2.601 ; -2.601 ; Rise ; C25M ; -; SD[6] ; C25M ; -3.298 ; -3.298 ; Rise ; C25M ; -; SD[7] ; C25M ; -2.576 ; -2.576 ; Rise ; C25M ; -; SetFW[*] ; C25M ; -2.527 ; -2.527 ; Rise ; C25M ; -; SetFW[0] ; C25M ; -2.527 ; -2.527 ; Rise ; C25M ; -; SetFW[1] ; C25M ; -2.583 ; -2.583 ; Rise ; C25M ; -; nDEVSEL ; C25M ; -4.081 ; -4.081 ; Rise ; C25M ; -; nIOSEL ; C25M ; -6.322 ; -6.322 ; Rise ; C25M ; -; nRES ; C25M ; -3.707 ; -3.707 ; Rise ; C25M ; -; RA[*] ; PHI0 ; -0.307 ; -0.307 ; Rise ; PHI0 ; -; RA[0] ; PHI0 ; -2.493 ; -2.493 ; Rise ; PHI0 ; -; RA[1] ; PHI0 ; -2.899 ; -2.899 ; Rise ; PHI0 ; -; RA[2] ; PHI0 ; -3.353 ; -3.353 ; Rise ; PHI0 ; -; RA[3] ; PHI0 ; -3.547 ; -3.547 ; Rise ; PHI0 ; -; RA[7] ; PHI0 ; -1.643 ; -1.643 ; Rise ; PHI0 ; -; RA[8] ; PHI0 ; -1.451 ; -1.451 ; Rise ; PHI0 ; -; RA[9] ; PHI0 ; -1.746 ; -1.746 ; Rise ; PHI0 ; -; RA[10] ; PHI0 ; -0.910 ; -0.910 ; Rise ; PHI0 ; -; RA[11] ; PHI0 ; -0.307 ; -0.307 ; Rise ; PHI0 ; -; RA[12] ; PHI0 ; -2.613 ; -2.613 ; Rise ; PHI0 ; -; RA[13] ; PHI0 ; -2.237 ; -2.237 ; Rise ; PHI0 ; -; RA[14] ; PHI0 ; -2.832 ; -2.832 ; Rise ; PHI0 ; -; RA[15] ; PHI0 ; -2.496 ; -2.496 ; Rise ; PHI0 ; -; nWE ; PHI0 ; 0.547 ; 0.547 ; Rise ; PHI0 ; +; MISO ; C25M ; -3.682 ; -3.682 ; Rise ; C25M ; +; MOSI ; C25M ; -3.620 ; -3.620 ; Rise ; C25M ; +; PHI0 ; C25M ; -2.226 ; -2.226 ; Rise ; C25M ; +; RA[*] ; C25M ; -3.852 ; -3.852 ; Rise ; C25M ; +; RA[0] ; C25M ; -4.647 ; -4.647 ; Rise ; C25M ; +; RA[1] ; C25M ; -4.783 ; -4.783 ; Rise ; C25M ; +; RA[2] ; C25M ; -4.332 ; -4.332 ; Rise ; C25M ; +; RA[3] ; C25M ; -3.852 ; -3.852 ; Rise ; C25M ; +; RA[4] ; C25M ; -5.515 ; -5.515 ; Rise ; C25M ; +; RA[5] ; C25M ; -5.236 ; -5.236 ; Rise ; C25M ; +; RA[6] ; C25M ; -6.585 ; -6.585 ; Rise ; C25M ; +; RA[7] ; C25M ; -4.632 ; -4.632 ; Rise ; C25M ; +; RA[8] ; C25M ; -4.901 ; -4.901 ; Rise ; C25M ; +; RA[9] ; C25M ; -5.857 ; -5.857 ; Rise ; C25M ; +; RA[10] ; C25M ; -5.398 ; -5.398 ; Rise ; C25M ; +; RA[11] ; C25M ; -4.066 ; -4.066 ; Rise ; C25M ; +; RA[12] ; C25M ; -9.038 ; -9.038 ; Rise ; C25M ; +; RA[13] ; C25M ; -8.666 ; -8.666 ; Rise ; C25M ; +; RA[14] ; C25M ; -9.336 ; -9.336 ; Rise ; C25M ; +; RA[15] ; C25M ; -8.787 ; -8.787 ; Rise ; C25M ; +; RD[*] ; C25M ; -2.106 ; -2.106 ; Rise ; C25M ; +; RD[0] ; C25M ; -2.689 ; -2.689 ; Rise ; C25M ; +; RD[1] ; C25M ; -2.558 ; -2.558 ; Rise ; C25M ; +; RD[2] ; C25M ; -2.686 ; -2.686 ; Rise ; C25M ; +; RD[3] ; C25M ; -2.620 ; -2.620 ; Rise ; C25M ; +; RD[4] ; C25M ; -2.645 ; -2.645 ; Rise ; C25M ; +; RD[5] ; C25M ; -2.677 ; -2.677 ; Rise ; C25M ; +; RD[6] ; C25M ; -2.106 ; -2.106 ; Rise ; C25M ; +; RD[7] ; C25M ; -2.154 ; -2.154 ; Rise ; C25M ; +; SD[*] ; C25M ; -3.218 ; -3.218 ; Rise ; C25M ; +; SD[0] ; C25M ; -3.913 ; -3.913 ; Rise ; C25M ; +; SD[1] ; C25M ; -5.089 ; -5.089 ; Rise ; C25M ; +; SD[2] ; C25M ; -3.218 ; -3.218 ; Rise ; C25M ; +; SD[3] ; C25M ; -3.270 ; -3.270 ; Rise ; C25M ; +; SD[4] ; C25M ; -4.039 ; -4.039 ; Rise ; C25M ; +; SD[5] ; C25M ; -3.712 ; -3.712 ; Rise ; C25M ; +; SD[6] ; C25M ; -3.297 ; -3.297 ; Rise ; C25M ; +; SD[7] ; C25M ; -3.235 ; -3.235 ; Rise ; C25M ; +; SetFW[*] ; C25M ; -2.060 ; -2.060 ; Rise ; C25M ; +; SetFW[0] ; C25M ; -2.060 ; -2.060 ; Rise ; C25M ; +; SetFW[1] ; C25M ; -2.621 ; -2.621 ; Rise ; C25M ; +; nDEVSEL ; C25M ; -2.931 ; -2.931 ; Rise ; C25M ; +; nIOSEL ; C25M ; -6.016 ; -6.016 ; Rise ; C25M ; +; nRES ; C25M ; -2.685 ; -2.685 ; Rise ; C25M ; +; RA[*] ; PHI0 ; -0.955 ; -0.955 ; Rise ; PHI0 ; +; RA[0] ; PHI0 ; -2.900 ; -2.900 ; Rise ; PHI0 ; +; RA[1] ; PHI0 ; -2.412 ; -2.412 ; Rise ; PHI0 ; +; RA[2] ; PHI0 ; -3.774 ; -3.774 ; Rise ; PHI0 ; +; RA[3] ; PHI0 ; -3.875 ; -3.875 ; Rise ; PHI0 ; +; RA[7] ; PHI0 ; -1.995 ; -1.995 ; Rise ; PHI0 ; +; RA[8] ; PHI0 ; -2.159 ; -2.159 ; Rise ; PHI0 ; +; RA[9] ; PHI0 ; -2.514 ; -2.514 ; Rise ; PHI0 ; +; RA[10] ; PHI0 ; -1.167 ; -1.167 ; Rise ; PHI0 ; +; RA[11] ; PHI0 ; -0.955 ; -0.955 ; Rise ; PHI0 ; +; RA[12] ; PHI0 ; -3.055 ; -3.055 ; Rise ; PHI0 ; +; RA[13] ; PHI0 ; -2.683 ; -2.683 ; Rise ; PHI0 ; +; RA[14] ; PHI0 ; -3.353 ; -3.353 ; Rise ; PHI0 ; +; RA[15] ; PHI0 ; -2.804 ; -2.804 ; Rise ; PHI0 ; +; nWE ; PHI0 ; -0.009 ; -0.009 ; Rise ; PHI0 ; +-----------+------------+--------+--------+------------+-----------------+ @@ -748,55 +748,55 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-----------+------------+--------+--------+------------+-----------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+--------+--------+------------+-----------------+ -; DQMH ; C25M ; 19.079 ; 19.079 ; Rise ; C25M ; -; DQML ; C25M ; 17.666 ; 17.666 ; Rise ; C25M ; -; FCK ; C25M ; 9.573 ; 9.573 ; Rise ; C25M ; -; MOSI ; C25M ; 17.464 ; 17.464 ; Rise ; C25M ; -; RCKE ; C25M ; 17.995 ; 17.995 ; Rise ; C25M ; -; RD[*] ; C25M ; 9.478 ; 9.478 ; Rise ; C25M ; -; RD[0] ; C25M ; 9.116 ; 9.116 ; Rise ; C25M ; -; RD[1] ; C25M ; 8.956 ; 8.956 ; Rise ; C25M ; -; RD[2] ; C25M ; 8.970 ; 8.970 ; Rise ; C25M ; -; RD[3] ; C25M ; 9.462 ; 9.462 ; Rise ; C25M ; -; RD[4] ; C25M ; 9.055 ; 9.055 ; Rise ; C25M ; -; RD[5] ; C25M ; 9.107 ; 9.107 ; Rise ; C25M ; -; RD[6] ; C25M ; 9.478 ; 9.478 ; Rise ; C25M ; -; RD[7] ; C25M ; 9.105 ; 9.105 ; Rise ; C25M ; -; RDdir ; C25M ; 22.038 ; 22.038 ; Rise ; C25M ; -; SA[*] ; C25M ; 18.534 ; 18.534 ; Rise ; C25M ; -; SA[0] ; C25M ; 18.235 ; 18.235 ; Rise ; C25M ; -; SA[1] ; C25M ; 17.665 ; 17.665 ; Rise ; C25M ; -; SA[2] ; C25M ; 17.703 ; 17.703 ; Rise ; C25M ; -; SA[3] ; C25M ; 17.758 ; 17.758 ; Rise ; C25M ; -; SA[4] ; C25M ; 18.165 ; 18.165 ; Rise ; C25M ; -; SA[5] ; C25M ; 18.193 ; 18.193 ; Rise ; C25M ; -; SA[6] ; C25M ; 17.255 ; 17.255 ; Rise ; C25M ; -; SA[7] ; C25M ; 17.616 ; 17.616 ; Rise ; C25M ; -; SA[8] ; C25M ; 18.534 ; 18.534 ; Rise ; C25M ; -; SA[9] ; C25M ; 17.294 ; 17.294 ; Rise ; C25M ; -; SA[10] ; C25M ; 18.531 ; 18.531 ; Rise ; C25M ; -; SA[11] ; C25M ; 17.275 ; 17.275 ; Rise ; C25M ; -; SA[12] ; C25M ; 17.285 ; 17.285 ; Rise ; C25M ; -; SBA[*] ; C25M ; 19.050 ; 19.050 ; Rise ; C25M ; -; SBA[0] ; C25M ; 19.050 ; 19.050 ; Rise ; C25M ; -; SBA[1] ; C25M ; 18.578 ; 18.578 ; Rise ; C25M ; -; SD[*] ; C25M ; 17.285 ; 17.285 ; Rise ; C25M ; -; SD[0] ; C25M ; 17.285 ; 17.285 ; Rise ; C25M ; -; SD[1] ; C25M ; 17.082 ; 17.082 ; Rise ; C25M ; -; SD[2] ; C25M ; 16.619 ; 16.619 ; Rise ; C25M ; -; SD[3] ; C25M ; 16.623 ; 16.623 ; Rise ; C25M ; -; SD[4] ; C25M ; 15.968 ; 15.968 ; Rise ; C25M ; -; SD[5] ; C25M ; 16.614 ; 16.614 ; Rise ; C25M ; -; SD[6] ; C25M ; 15.995 ; 15.995 ; Rise ; C25M ; -; SD[7] ; C25M ; 15.961 ; 15.961 ; Rise ; C25M ; -; nCAS ; C25M ; 17.650 ; 17.650 ; Rise ; C25M ; -; nFCS ; C25M ; 17.380 ; 17.380 ; Rise ; C25M ; -; nRAS ; C25M ; 17.831 ; 17.831 ; Rise ; C25M ; -; nRCS ; C25M ; 17.987 ; 17.987 ; Rise ; C25M ; -; nRESout ; C25M ; 17.759 ; 17.759 ; Rise ; C25M ; -; nSWE ; C25M ; 17.935 ; 17.935 ; Rise ; C25M ; -; RDdir ; PHI0 ; 19.265 ; 19.265 ; Rise ; PHI0 ; -; RDdir ; PHI0 ; 19.265 ; 19.265 ; Fall ; PHI0 ; +; DQMH ; C25M ; 9.305 ; 9.305 ; Rise ; C25M ; +; DQML ; C25M ; 9.483 ; 9.483 ; Rise ; C25M ; +; FCK ; C25M ; 9.008 ; 9.008 ; Rise ; C25M ; +; MOSI ; C25M ; 8.844 ; 8.844 ; Rise ; C25M ; +; RCKE ; C25M ; 9.013 ; 9.013 ; Rise ; C25M ; +; RD[*] ; C25M ; 9.287 ; 9.287 ; Rise ; C25M ; +; RD[0] ; C25M ; 8.456 ; 8.456 ; Rise ; C25M ; +; RD[1] ; C25M ; 8.246 ; 8.246 ; Rise ; C25M ; +; RD[2] ; C25M ; 8.212 ; 8.212 ; Rise ; C25M ; +; RD[3] ; C25M ; 8.920 ; 8.920 ; Rise ; C25M ; +; RD[4] ; C25M ; 8.200 ; 8.200 ; Rise ; C25M ; +; RD[5] ; C25M ; 8.222 ; 8.222 ; Rise ; C25M ; +; RD[6] ; C25M ; 8.841 ; 8.841 ; Rise ; C25M ; +; RD[7] ; C25M ; 9.287 ; 9.287 ; Rise ; C25M ; +; RDdir ; C25M ; 13.847 ; 13.847 ; Rise ; C25M ; +; SA[*] ; C25M ; 9.270 ; 9.270 ; Rise ; C25M ; +; SA[0] ; C25M ; 8.917 ; 8.917 ; Rise ; C25M ; +; SA[1] ; C25M ; 8.665 ; 8.665 ; Rise ; C25M ; +; SA[2] ; C25M ; 9.270 ; 9.270 ; Rise ; C25M ; +; SA[3] ; C25M ; 8.223 ; 8.223 ; Rise ; C25M ; +; SA[4] ; C25M ; 8.244 ; 8.244 ; Rise ; C25M ; +; SA[5] ; C25M ; 8.115 ; 8.115 ; Rise ; C25M ; +; SA[6] ; C25M ; 8.104 ; 8.104 ; Rise ; C25M ; +; SA[7] ; C25M ; 8.114 ; 8.114 ; Rise ; C25M ; +; SA[8] ; C25M ; 8.229 ; 8.229 ; Rise ; C25M ; +; SA[9] ; C25M ; 8.975 ; 8.975 ; Rise ; C25M ; +; SA[10] ; C25M ; 6.951 ; 6.951 ; Rise ; C25M ; +; SA[11] ; C25M ; 8.922 ; 8.922 ; Rise ; C25M ; +; SA[12] ; C25M ; 8.773 ; 8.773 ; Rise ; C25M ; +; SBA[*] ; C25M ; 8.182 ; 8.182 ; Rise ; C25M ; +; SBA[0] ; C25M ; 8.182 ; 8.182 ; Rise ; C25M ; +; SBA[1] ; C25M ; 6.923 ; 6.923 ; Rise ; C25M ; +; SD[*] ; C25M ; 9.179 ; 9.179 ; Rise ; C25M ; +; SD[0] ; C25M ; 6.937 ; 6.937 ; Rise ; C25M ; +; SD[1] ; C25M ; 9.179 ; 9.179 ; Rise ; C25M ; +; SD[2] ; C25M ; 7.562 ; 7.562 ; Rise ; C25M ; +; SD[3] ; C25M ; 7.576 ; 7.576 ; Rise ; C25M ; +; SD[4] ; C25M ; 8.135 ; 8.135 ; Rise ; C25M ; +; SD[5] ; C25M ; 6.944 ; 6.944 ; Rise ; C25M ; +; SD[6] ; C25M ; 7.570 ; 7.570 ; Rise ; C25M ; +; SD[7] ; C25M ; 7.556 ; 7.556 ; Rise ; C25M ; +; nCAS ; C25M ; 8.431 ; 8.431 ; Rise ; C25M ; +; nFCS ; C25M ; 8.772 ; 8.772 ; Rise ; C25M ; +; nRAS ; C25M ; 8.114 ; 8.114 ; Rise ; C25M ; +; nRCS ; C25M ; 9.195 ; 9.195 ; Rise ; C25M ; +; nRESout ; C25M ; 8.037 ; 8.037 ; Rise ; C25M ; +; nSWE ; C25M ; 8.335 ; 8.335 ; Rise ; C25M ; +; RDdir ; PHI0 ; 11.354 ; 11.354 ; Rise ; PHI0 ; +; RDdir ; PHI0 ; 11.354 ; 11.354 ; Fall ; PHI0 ; +-----------+------------+--------+--------+------------+-----------------+ @@ -805,55 +805,55 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-----------+------------+--------+--------+------------+-----------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+--------+--------+------------+-----------------+ -; DQMH ; C25M ; 19.079 ; 19.079 ; Rise ; C25M ; -; DQML ; C25M ; 17.666 ; 17.666 ; Rise ; C25M ; -; FCK ; C25M ; 9.573 ; 9.573 ; Rise ; C25M ; -; MOSI ; C25M ; 17.464 ; 17.464 ; Rise ; C25M ; -; RCKE ; C25M ; 17.995 ; 17.995 ; Rise ; C25M ; -; RD[*] ; C25M ; 8.956 ; 8.956 ; Rise ; C25M ; -; RD[0] ; C25M ; 9.116 ; 9.116 ; Rise ; C25M ; -; RD[1] ; C25M ; 8.956 ; 8.956 ; Rise ; C25M ; -; RD[2] ; C25M ; 8.970 ; 8.970 ; Rise ; C25M ; -; RD[3] ; C25M ; 9.462 ; 9.462 ; Rise ; C25M ; -; RD[4] ; C25M ; 9.055 ; 9.055 ; Rise ; C25M ; -; RD[5] ; C25M ; 9.107 ; 9.107 ; Rise ; C25M ; -; RD[6] ; C25M ; 9.478 ; 9.478 ; Rise ; C25M ; -; RD[7] ; C25M ; 9.105 ; 9.105 ; Rise ; C25M ; -; RDdir ; C25M ; 20.404 ; 20.404 ; Rise ; C25M ; -; SA[*] ; C25M ; 17.255 ; 17.255 ; Rise ; C25M ; -; SA[0] ; C25M ; 18.235 ; 18.235 ; Rise ; C25M ; -; SA[1] ; C25M ; 17.665 ; 17.665 ; Rise ; C25M ; -; SA[2] ; C25M ; 17.703 ; 17.703 ; Rise ; C25M ; -; SA[3] ; C25M ; 17.758 ; 17.758 ; Rise ; C25M ; -; SA[4] ; C25M ; 18.165 ; 18.165 ; Rise ; C25M ; -; SA[5] ; C25M ; 18.193 ; 18.193 ; Rise ; C25M ; -; SA[6] ; C25M ; 17.255 ; 17.255 ; Rise ; C25M ; -; SA[7] ; C25M ; 17.616 ; 17.616 ; Rise ; C25M ; -; SA[8] ; C25M ; 18.534 ; 18.534 ; Rise ; C25M ; -; SA[9] ; C25M ; 17.294 ; 17.294 ; Rise ; C25M ; -; SA[10] ; C25M ; 18.531 ; 18.531 ; Rise ; C25M ; -; SA[11] ; C25M ; 17.275 ; 17.275 ; Rise ; C25M ; -; SA[12] ; C25M ; 17.285 ; 17.285 ; Rise ; C25M ; -; SBA[*] ; C25M ; 18.578 ; 18.578 ; Rise ; C25M ; -; SBA[0] ; C25M ; 19.050 ; 19.050 ; Rise ; C25M ; -; SBA[1] ; C25M ; 18.578 ; 18.578 ; Rise ; C25M ; -; SD[*] ; C25M ; 15.961 ; 15.961 ; Rise ; C25M ; -; SD[0] ; C25M ; 17.285 ; 17.285 ; Rise ; C25M ; -; SD[1] ; C25M ; 17.082 ; 17.082 ; Rise ; C25M ; -; SD[2] ; C25M ; 16.619 ; 16.619 ; Rise ; C25M ; -; SD[3] ; C25M ; 16.623 ; 16.623 ; Rise ; C25M ; -; SD[4] ; C25M ; 15.968 ; 15.968 ; Rise ; C25M ; -; SD[5] ; C25M ; 16.614 ; 16.614 ; Rise ; C25M ; -; SD[6] ; C25M ; 15.995 ; 15.995 ; Rise ; C25M ; -; SD[7] ; C25M ; 15.961 ; 15.961 ; Rise ; C25M ; -; nCAS ; C25M ; 17.650 ; 17.650 ; Rise ; C25M ; -; nFCS ; C25M ; 17.380 ; 17.380 ; Rise ; C25M ; -; nRAS ; C25M ; 17.831 ; 17.831 ; Rise ; C25M ; -; nRCS ; C25M ; 17.987 ; 17.987 ; Rise ; C25M ; -; nRESout ; C25M ; 17.759 ; 17.759 ; Rise ; C25M ; -; nSWE ; C25M ; 17.935 ; 17.935 ; Rise ; C25M ; -; RDdir ; PHI0 ; 19.265 ; 19.265 ; Rise ; PHI0 ; -; RDdir ; PHI0 ; 19.265 ; 19.265 ; Fall ; PHI0 ; +; DQMH ; C25M ; 9.305 ; 9.305 ; Rise ; C25M ; +; DQML ; C25M ; 9.483 ; 9.483 ; Rise ; C25M ; +; FCK ; C25M ; 9.008 ; 9.008 ; Rise ; C25M ; +; MOSI ; C25M ; 8.844 ; 8.844 ; Rise ; C25M ; +; RCKE ; C25M ; 9.013 ; 9.013 ; Rise ; C25M ; +; RD[*] ; C25M ; 8.200 ; 8.200 ; Rise ; C25M ; +; RD[0] ; C25M ; 8.456 ; 8.456 ; Rise ; C25M ; +; RD[1] ; C25M ; 8.246 ; 8.246 ; Rise ; C25M ; +; RD[2] ; C25M ; 8.212 ; 8.212 ; Rise ; C25M ; +; RD[3] ; C25M ; 8.920 ; 8.920 ; Rise ; C25M ; +; RD[4] ; C25M ; 8.200 ; 8.200 ; Rise ; C25M ; +; RD[5] ; C25M ; 8.222 ; 8.222 ; Rise ; C25M ; +; RD[6] ; C25M ; 8.841 ; 8.841 ; Rise ; C25M ; +; RD[7] ; C25M ; 9.287 ; 9.287 ; Rise ; C25M ; +; RDdir ; C25M ; 11.009 ; 11.009 ; Rise ; C25M ; +; SA[*] ; C25M ; 6.951 ; 6.951 ; Rise ; C25M ; +; SA[0] ; C25M ; 8.917 ; 8.917 ; Rise ; C25M ; +; SA[1] ; C25M ; 8.665 ; 8.665 ; Rise ; C25M ; +; SA[2] ; C25M ; 9.270 ; 9.270 ; Rise ; C25M ; +; SA[3] ; C25M ; 8.223 ; 8.223 ; Rise ; C25M ; +; SA[4] ; C25M ; 8.244 ; 8.244 ; Rise ; C25M ; +; SA[5] ; C25M ; 8.115 ; 8.115 ; Rise ; C25M ; +; SA[6] ; C25M ; 8.104 ; 8.104 ; Rise ; C25M ; +; SA[7] ; C25M ; 8.114 ; 8.114 ; Rise ; C25M ; +; SA[8] ; C25M ; 8.229 ; 8.229 ; Rise ; C25M ; +; SA[9] ; C25M ; 8.975 ; 8.975 ; Rise ; C25M ; +; SA[10] ; C25M ; 6.951 ; 6.951 ; Rise ; C25M ; +; SA[11] ; C25M ; 8.922 ; 8.922 ; Rise ; C25M ; +; SA[12] ; C25M ; 8.773 ; 8.773 ; Rise ; C25M ; +; SBA[*] ; C25M ; 6.923 ; 6.923 ; Rise ; C25M ; +; SBA[0] ; C25M ; 8.182 ; 8.182 ; Rise ; C25M ; +; SBA[1] ; C25M ; 6.923 ; 6.923 ; Rise ; C25M ; +; SD[*] ; C25M ; 6.937 ; 6.937 ; Rise ; C25M ; +; SD[0] ; C25M ; 6.937 ; 6.937 ; Rise ; C25M ; +; SD[1] ; C25M ; 9.179 ; 9.179 ; Rise ; C25M ; +; SD[2] ; C25M ; 7.562 ; 7.562 ; Rise ; C25M ; +; SD[3] ; C25M ; 7.576 ; 7.576 ; Rise ; C25M ; +; SD[4] ; C25M ; 8.135 ; 8.135 ; Rise ; C25M ; +; SD[5] ; C25M ; 6.944 ; 6.944 ; Rise ; C25M ; +; SD[6] ; C25M ; 7.570 ; 7.570 ; Rise ; C25M ; +; SD[7] ; C25M ; 7.556 ; 7.556 ; Rise ; C25M ; +; nCAS ; C25M ; 8.431 ; 8.431 ; Rise ; C25M ; +; nFCS ; C25M ; 8.772 ; 8.772 ; Rise ; C25M ; +; nRAS ; C25M ; 8.114 ; 8.114 ; Rise ; C25M ; +; nRCS ; C25M ; 9.195 ; 9.195 ; Rise ; C25M ; +; nRESout ; C25M ; 8.037 ; 8.037 ; Rise ; C25M ; +; nSWE ; C25M ; 8.335 ; 8.335 ; Rise ; C25M ; +; RDdir ; PHI0 ; 11.354 ; 11.354 ; Rise ; PHI0 ; +; RDdir ; PHI0 ; 11.354 ; 11.354 ; Fall ; PHI0 ; +-----------+------------+--------+--------+------------+-----------------+ @@ -862,44 +862,44 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +------------+-------------+--------+----+----+--------+ ; Input Port ; Output Port ; RR ; RF ; FR ; FF ; +------------+-------------+--------+----+----+--------+ -; DMAin ; DMAout ; 18.256 ; ; ; 18.256 ; -; INTin ; INTout ; 18.481 ; ; ; 18.481 ; -; nDEVSEL ; RD[0] ; 14.610 ; ; ; 14.610 ; -; nDEVSEL ; RD[1] ; 14.610 ; ; ; 14.610 ; -; nDEVSEL ; RD[2] ; 14.610 ; ; ; 14.610 ; -; nDEVSEL ; RD[3] ; 14.610 ; ; ; 14.610 ; -; nDEVSEL ; RD[4] ; 14.610 ; ; ; 14.610 ; -; nDEVSEL ; RD[5] ; 14.610 ; ; ; 14.610 ; -; nDEVSEL ; RD[6] ; 13.627 ; ; ; 13.627 ; -; nDEVSEL ; RD[7] ; 13.627 ; ; ; 13.627 ; -; nDEVSEL ; RDdir ; 23.758 ; ; ; 23.758 ; -; nIOSEL ; RD[0] ; 14.609 ; ; ; 14.609 ; -; nIOSEL ; RD[1] ; 14.609 ; ; ; 14.609 ; -; nIOSEL ; RD[2] ; 14.609 ; ; ; 14.609 ; -; nIOSEL ; RD[3] ; 14.609 ; ; ; 14.609 ; -; nIOSEL ; RD[4] ; 14.609 ; ; ; 14.609 ; -; nIOSEL ; RD[5] ; 14.609 ; ; ; 14.609 ; -; nIOSEL ; RD[6] ; 13.626 ; ; ; 13.626 ; -; nIOSEL ; RD[7] ; 13.626 ; ; ; 13.626 ; -; nIOSEL ; RDdir ; 23.757 ; ; ; 23.757 ; -; nIOSTRB ; RD[0] ; 13.321 ; ; ; 13.321 ; -; nIOSTRB ; RD[1] ; 13.321 ; ; ; 13.321 ; -; nIOSTRB ; RD[2] ; 13.321 ; ; ; 13.321 ; -; nIOSTRB ; RD[3] ; 13.321 ; ; ; 13.321 ; -; nIOSTRB ; RD[4] ; 13.321 ; ; ; 13.321 ; -; nIOSTRB ; RD[5] ; 13.321 ; ; ; 13.321 ; -; nIOSTRB ; RD[6] ; 12.338 ; ; ; 12.338 ; -; nIOSTRB ; RD[7] ; 12.338 ; ; ; 12.338 ; -; nIOSTRB ; RDdir ; 22.469 ; ; ; 22.469 ; -; nWE ; RD[0] ; 11.025 ; ; ; 11.025 ; -; nWE ; RD[1] ; 11.025 ; ; ; 11.025 ; -; nWE ; RD[2] ; 11.025 ; ; ; 11.025 ; -; nWE ; RD[3] ; 11.025 ; ; ; 11.025 ; -; nWE ; RD[4] ; 11.025 ; ; ; 11.025 ; -; nWE ; RD[5] ; 11.025 ; ; ; 11.025 ; -; nWE ; RD[6] ; 10.042 ; ; ; 10.042 ; -; nWE ; RD[7] ; 10.042 ; ; ; 10.042 ; -; nWE ; RDdir ; 20.173 ; ; ; 20.173 ; +; DMAin ; DMAout ; 8.420 ; ; ; 8.420 ; +; INTin ; INTout ; 8.852 ; ; ; 8.852 ; +; nDEVSEL ; RD[0] ; 13.908 ; ; ; 13.908 ; +; nDEVSEL ; RD[1] ; 13.908 ; ; ; 13.908 ; +; nDEVSEL ; RD[2] ; 13.908 ; ; ; 13.908 ; +; nDEVSEL ; RD[3] ; 13.908 ; ; ; 13.908 ; +; nDEVSEL ; RD[4] ; 13.908 ; ; ; 13.908 ; +; nDEVSEL ; RD[5] ; 13.908 ; ; ; 13.908 ; +; nDEVSEL ; RD[6] ; 13.954 ; ; ; 13.954 ; +; nDEVSEL ; RD[7] ; 13.954 ; ; ; 13.954 ; +; nDEVSEL ; RDdir ; 15.512 ; ; ; 15.512 ; +; nIOSEL ; RD[0] ; 13.721 ; ; ; 13.721 ; +; nIOSEL ; RD[1] ; 13.721 ; ; ; 13.721 ; +; nIOSEL ; RD[2] ; 13.721 ; ; ; 13.721 ; +; nIOSEL ; RD[3] ; 13.721 ; ; ; 13.721 ; +; nIOSEL ; RD[4] ; 13.721 ; ; ; 13.721 ; +; nIOSEL ; RD[5] ; 13.721 ; ; ; 13.721 ; +; nIOSEL ; RD[6] ; 13.767 ; ; ; 13.767 ; +; nIOSEL ; RD[7] ; 13.767 ; ; ; 13.767 ; +; nIOSEL ; RDdir ; 15.325 ; ; ; 15.325 ; +; nIOSTRB ; RD[0] ; 13.574 ; ; ; 13.574 ; +; nIOSTRB ; RD[1] ; 13.574 ; ; ; 13.574 ; +; nIOSTRB ; RD[2] ; 13.574 ; ; ; 13.574 ; +; nIOSTRB ; RD[3] ; 13.574 ; ; ; 13.574 ; +; nIOSTRB ; RD[4] ; 13.574 ; ; ; 13.574 ; +; nIOSTRB ; RD[5] ; 13.574 ; ; ; 13.574 ; +; nIOSTRB ; RD[6] ; 13.620 ; ; ; 13.620 ; +; nIOSTRB ; RD[7] ; 13.620 ; ; ; 13.620 ; +; nIOSTRB ; RDdir ; 15.178 ; ; ; 15.178 ; +; nWE ; RD[0] ; 10.209 ; ; ; 10.209 ; +; nWE ; RD[1] ; 10.209 ; ; ; 10.209 ; +; nWE ; RD[2] ; 10.209 ; ; ; 10.209 ; +; nWE ; RD[3] ; 10.209 ; ; ; 10.209 ; +; nWE ; RD[4] ; 10.209 ; ; ; 10.209 ; +; nWE ; RD[5] ; 10.209 ; ; ; 10.209 ; +; nWE ; RD[6] ; 10.255 ; ; ; 10.255 ; +; nWE ; RD[7] ; 10.255 ; ; ; 10.255 ; +; nWE ; RDdir ; 11.813 ; ; ; 11.813 ; +------------+-------------+--------+----+----+--------+ @@ -908,44 +908,44 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +------------+-------------+--------+----+----+--------+ ; Input Port ; Output Port ; RR ; RF ; FR ; FF ; +------------+-------------+--------+----+----+--------+ -; DMAin ; DMAout ; 18.256 ; ; ; 18.256 ; -; INTin ; INTout ; 18.481 ; ; ; 18.481 ; -; nDEVSEL ; RD[0] ; 14.610 ; ; ; 14.610 ; -; nDEVSEL ; RD[1] ; 14.610 ; ; ; 14.610 ; -; nDEVSEL ; RD[2] ; 14.610 ; ; ; 14.610 ; -; nDEVSEL ; RD[3] ; 14.610 ; ; ; 14.610 ; -; nDEVSEL ; RD[4] ; 14.610 ; ; ; 14.610 ; -; nDEVSEL ; RD[5] ; 14.610 ; ; ; 14.610 ; -; nDEVSEL ; RD[6] ; 13.627 ; ; ; 13.627 ; -; nDEVSEL ; RD[7] ; 13.627 ; ; ; 13.627 ; -; nDEVSEL ; RDdir ; 23.758 ; ; ; 23.758 ; -; nIOSEL ; RD[0] ; 14.609 ; ; ; 14.609 ; -; nIOSEL ; RD[1] ; 14.609 ; ; ; 14.609 ; -; nIOSEL ; RD[2] ; 14.609 ; ; ; 14.609 ; -; nIOSEL ; RD[3] ; 14.609 ; ; ; 14.609 ; -; nIOSEL ; RD[4] ; 14.609 ; ; ; 14.609 ; -; nIOSEL ; RD[5] ; 14.609 ; ; ; 14.609 ; -; nIOSEL ; RD[6] ; 13.626 ; ; ; 13.626 ; -; nIOSEL ; RD[7] ; 13.626 ; ; ; 13.626 ; -; nIOSEL ; RDdir ; 23.757 ; ; ; 23.757 ; -; nIOSTRB ; RD[0] ; 13.321 ; ; ; 13.321 ; -; nIOSTRB ; RD[1] ; 13.321 ; ; ; 13.321 ; -; nIOSTRB ; RD[2] ; 13.321 ; ; ; 13.321 ; -; nIOSTRB ; RD[3] ; 13.321 ; ; ; 13.321 ; -; nIOSTRB ; RD[4] ; 13.321 ; ; ; 13.321 ; -; nIOSTRB ; RD[5] ; 13.321 ; ; ; 13.321 ; -; nIOSTRB ; RD[6] ; 12.338 ; ; ; 12.338 ; -; nIOSTRB ; RD[7] ; 12.338 ; ; ; 12.338 ; -; nIOSTRB ; RDdir ; 22.469 ; ; ; 22.469 ; -; nWE ; RD[0] ; 11.025 ; ; ; 11.025 ; -; nWE ; RD[1] ; 11.025 ; ; ; 11.025 ; -; nWE ; RD[2] ; 11.025 ; ; ; 11.025 ; -; nWE ; RD[3] ; 11.025 ; ; ; 11.025 ; -; nWE ; RD[4] ; 11.025 ; ; ; 11.025 ; -; nWE ; RD[5] ; 11.025 ; ; ; 11.025 ; -; nWE ; RD[6] ; 10.042 ; ; ; 10.042 ; -; nWE ; RD[7] ; 10.042 ; ; ; 10.042 ; -; nWE ; RDdir ; 20.173 ; ; ; 20.173 ; +; DMAin ; DMAout ; 8.420 ; ; ; 8.420 ; +; INTin ; INTout ; 8.852 ; ; ; 8.852 ; +; nDEVSEL ; RD[0] ; 13.908 ; ; ; 13.908 ; +; nDEVSEL ; RD[1] ; 13.908 ; ; ; 13.908 ; +; nDEVSEL ; RD[2] ; 13.908 ; ; ; 13.908 ; +; nDEVSEL ; RD[3] ; 13.908 ; ; ; 13.908 ; +; nDEVSEL ; RD[4] ; 13.908 ; ; ; 13.908 ; +; nDEVSEL ; RD[5] ; 13.908 ; ; ; 13.908 ; +; nDEVSEL ; RD[6] ; 13.954 ; ; ; 13.954 ; +; nDEVSEL ; RD[7] ; 13.954 ; ; ; 13.954 ; +; nDEVSEL ; RDdir ; 15.512 ; ; ; 15.512 ; +; nIOSEL ; RD[0] ; 13.721 ; ; ; 13.721 ; +; nIOSEL ; RD[1] ; 13.721 ; ; ; 13.721 ; +; nIOSEL ; RD[2] ; 13.721 ; ; ; 13.721 ; +; nIOSEL ; RD[3] ; 13.721 ; ; ; 13.721 ; +; nIOSEL ; RD[4] ; 13.721 ; ; ; 13.721 ; +; nIOSEL ; RD[5] ; 13.721 ; ; ; 13.721 ; +; nIOSEL ; RD[6] ; 13.767 ; ; ; 13.767 ; +; nIOSEL ; RD[7] ; 13.767 ; ; ; 13.767 ; +; nIOSEL ; RDdir ; 15.325 ; ; ; 15.325 ; +; nIOSTRB ; RD[0] ; 13.574 ; ; ; 13.574 ; +; nIOSTRB ; RD[1] ; 13.574 ; ; ; 13.574 ; +; nIOSTRB ; RD[2] ; 13.574 ; ; ; 13.574 ; +; nIOSTRB ; RD[3] ; 13.574 ; ; ; 13.574 ; +; nIOSTRB ; RD[4] ; 13.574 ; ; ; 13.574 ; +; nIOSTRB ; RD[5] ; 13.574 ; ; ; 13.574 ; +; nIOSTRB ; RD[6] ; 13.620 ; ; ; 13.620 ; +; nIOSTRB ; RD[7] ; 13.620 ; ; ; 13.620 ; +; nIOSTRB ; RDdir ; 15.178 ; ; ; 15.178 ; +; nWE ; RD[0] ; 10.209 ; ; ; 10.209 ; +; nWE ; RD[1] ; 10.209 ; ; ; 10.209 ; +; nWE ; RD[2] ; 10.209 ; ; ; 10.209 ; +; nWE ; RD[3] ; 10.209 ; ; ; 10.209 ; +; nWE ; RD[4] ; 10.209 ; ; ; 10.209 ; +; nWE ; RD[5] ; 10.209 ; ; ; 10.209 ; +; nWE ; RD[6] ; 10.255 ; ; ; 10.255 ; +; nWE ; RD[7] ; 10.255 ; ; ; 10.255 ; +; nWE ; RDdir ; 11.813 ; ; ; 11.813 ; +------------+-------------+--------+----+----+--------+ @@ -954,93 +954,93 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-----------+------------+--------+------+------------+-----------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+--------+------+------------+-----------------+ -; FCK ; C25M ; 7.234 ; ; Rise ; C25M ; -; MOSI ; C25M ; 15.227 ; ; Rise ; C25M ; -; RD[*] ; C25M ; 11.907 ; ; Rise ; C25M ; -; RD[0] ; C25M ; 12.890 ; ; Rise ; C25M ; -; RD[1] ; C25M ; 12.890 ; ; Rise ; C25M ; -; RD[2] ; C25M ; 12.890 ; ; Rise ; C25M ; -; RD[3] ; C25M ; 12.890 ; ; Rise ; C25M ; -; RD[4] ; C25M ; 12.890 ; ; Rise ; C25M ; -; RD[5] ; C25M ; 12.890 ; ; Rise ; C25M ; -; RD[6] ; C25M ; 11.907 ; ; Rise ; C25M ; -; RD[7] ; C25M ; 11.907 ; ; Rise ; C25M ; -; SD[*] ; C25M ; 15.991 ; ; Rise ; C25M ; -; SD[0] ; C25M ; 16.393 ; ; Rise ; C25M ; -; SD[1] ; C25M ; 16.384 ; ; Rise ; C25M ; -; SD[2] ; C25M ; 15.991 ; ; Rise ; C25M ; -; SD[3] ; C25M ; 15.991 ; ; Rise ; C25M ; -; SD[4] ; C25M ; 16.393 ; ; Rise ; C25M ; -; SD[5] ; C25M ; 15.991 ; ; Rise ; C25M ; -; SD[6] ; C25M ; 15.991 ; ; Rise ; C25M ; -; SD[7] ; C25M ; 15.991 ; ; Rise ; C25M ; -; nFCS ; C25M ; 15.988 ; ; Rise ; C25M ; -; RD[*] ; PHI0 ; 9.134 ; ; Rise ; PHI0 ; -; RD[0] ; PHI0 ; 10.117 ; ; Rise ; PHI0 ; -; RD[1] ; PHI0 ; 10.117 ; ; Rise ; PHI0 ; -; RD[2] ; PHI0 ; 10.117 ; ; Rise ; PHI0 ; -; RD[3] ; PHI0 ; 10.117 ; ; Rise ; PHI0 ; -; RD[4] ; PHI0 ; 10.117 ; ; Rise ; PHI0 ; -; RD[5] ; PHI0 ; 10.117 ; ; Rise ; PHI0 ; -; RD[6] ; PHI0 ; 9.134 ; ; Rise ; PHI0 ; -; RD[7] ; PHI0 ; 9.134 ; ; Rise ; PHI0 ; -; RD[*] ; PHI0 ; 9.134 ; ; Fall ; PHI0 ; -; RD[0] ; PHI0 ; 10.117 ; ; Fall ; PHI0 ; -; RD[1] ; PHI0 ; 10.117 ; ; Fall ; PHI0 ; -; RD[2] ; PHI0 ; 10.117 ; ; Fall ; PHI0 ; -; RD[3] ; PHI0 ; 10.117 ; ; Fall ; PHI0 ; -; RD[4] ; PHI0 ; 10.117 ; ; Fall ; PHI0 ; -; RD[5] ; PHI0 ; 10.117 ; ; Fall ; PHI0 ; -; RD[6] ; PHI0 ; 9.134 ; ; Fall ; PHI0 ; -; RD[7] ; PHI0 ; 9.134 ; ; Fall ; PHI0 ; +; FCK ; C25M ; 7.909 ; ; Rise ; C25M ; +; MOSI ; C25M ; 8.455 ; ; Rise ; C25M ; +; RD[*] ; C25M ; 12.243 ; ; Rise ; C25M ; +; RD[0] ; C25M ; 12.243 ; ; Rise ; C25M ; +; RD[1] ; C25M ; 12.243 ; ; Rise ; C25M ; +; RD[2] ; C25M ; 12.243 ; ; Rise ; C25M ; +; RD[3] ; C25M ; 12.243 ; ; Rise ; C25M ; +; RD[4] ; C25M ; 12.243 ; ; Rise ; C25M ; +; RD[5] ; C25M ; 12.243 ; ; Rise ; C25M ; +; RD[6] ; C25M ; 12.289 ; ; Rise ; C25M ; +; RD[7] ; C25M ; 12.289 ; ; Rise ; C25M ; +; SD[*] ; C25M ; 7.014 ; ; Rise ; C25M ; +; SD[0] ; C25M ; 7.446 ; ; Rise ; C25M ; +; SD[1] ; C25M ; 7.446 ; ; Rise ; C25M ; +; SD[2] ; C25M ; 7.014 ; ; Rise ; C25M ; +; SD[3] ; C25M ; 7.014 ; ; Rise ; C25M ; +; SD[4] ; C25M ; 7.446 ; ; Rise ; C25M ; +; SD[5] ; C25M ; 7.014 ; ; Rise ; C25M ; +; SD[6] ; C25M ; 7.014 ; ; Rise ; C25M ; +; SD[7] ; C25M ; 7.014 ; ; Rise ; C25M ; +; nFCS ; C25M ; 7.116 ; ; Rise ; C25M ; +; RD[*] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; +; RD[0] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; +; RD[1] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; +; RD[2] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; +; RD[3] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; +; RD[4] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; +; RD[5] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; +; RD[6] ; PHI0 ; 9.796 ; ; Rise ; PHI0 ; +; RD[7] ; PHI0 ; 9.796 ; ; Rise ; PHI0 ; +; RD[*] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; +; RD[0] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; +; RD[1] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; +; RD[2] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; +; RD[3] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; +; RD[4] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; +; RD[5] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; +; RD[6] ; PHI0 ; 9.796 ; ; Fall ; PHI0 ; +; RD[7] ; PHI0 ; 9.796 ; ; Fall ; PHI0 ; +-----------+------------+--------+------+------------+-----------------+ -+-----------------------------------------------------------------------+ -; Minimum Output Enable Times ; -+-----------+------------+--------+------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-----------+------------+--------+------+------------+-----------------+ -; FCK ; C25M ; 7.234 ; ; Rise ; C25M ; -; MOSI ; C25M ; 15.227 ; ; Rise ; C25M ; -; RD[*] ; C25M ; 10.273 ; ; Rise ; C25M ; -; RD[0] ; C25M ; 11.256 ; ; Rise ; C25M ; -; RD[1] ; C25M ; 11.256 ; ; Rise ; C25M ; -; RD[2] ; C25M ; 11.256 ; ; Rise ; C25M ; -; RD[3] ; C25M ; 11.256 ; ; Rise ; C25M ; -; RD[4] ; C25M ; 11.256 ; ; Rise ; C25M ; -; RD[5] ; C25M ; 11.256 ; ; Rise ; C25M ; -; RD[6] ; C25M ; 10.273 ; ; Rise ; C25M ; -; RD[7] ; C25M ; 10.273 ; ; Rise ; C25M ; -; SD[*] ; C25M ; 15.991 ; ; Rise ; C25M ; -; SD[0] ; C25M ; 16.393 ; ; Rise ; C25M ; -; SD[1] ; C25M ; 16.384 ; ; Rise ; C25M ; -; SD[2] ; C25M ; 15.991 ; ; Rise ; C25M ; -; SD[3] ; C25M ; 15.991 ; ; Rise ; C25M ; -; SD[4] ; C25M ; 16.393 ; ; Rise ; C25M ; -; SD[5] ; C25M ; 15.991 ; ; Rise ; C25M ; -; SD[6] ; C25M ; 15.991 ; ; Rise ; C25M ; -; SD[7] ; C25M ; 15.991 ; ; Rise ; C25M ; -; nFCS ; C25M ; 15.988 ; ; Rise ; C25M ; -; RD[*] ; PHI0 ; 9.134 ; ; Rise ; PHI0 ; -; RD[0] ; PHI0 ; 10.117 ; ; Rise ; PHI0 ; -; RD[1] ; PHI0 ; 10.117 ; ; Rise ; PHI0 ; -; RD[2] ; PHI0 ; 10.117 ; ; Rise ; PHI0 ; -; RD[3] ; PHI0 ; 10.117 ; ; Rise ; PHI0 ; -; RD[4] ; PHI0 ; 10.117 ; ; Rise ; PHI0 ; -; RD[5] ; PHI0 ; 10.117 ; ; Rise ; PHI0 ; -; RD[6] ; PHI0 ; 9.134 ; ; Rise ; PHI0 ; -; RD[7] ; PHI0 ; 9.134 ; ; Rise ; PHI0 ; -; RD[*] ; PHI0 ; 9.134 ; ; Fall ; PHI0 ; -; RD[0] ; PHI0 ; 10.117 ; ; Fall ; PHI0 ; -; RD[1] ; PHI0 ; 10.117 ; ; Fall ; PHI0 ; -; RD[2] ; PHI0 ; 10.117 ; ; Fall ; PHI0 ; -; RD[3] ; PHI0 ; 10.117 ; ; Fall ; PHI0 ; -; RD[4] ; PHI0 ; 10.117 ; ; Fall ; PHI0 ; -; RD[5] ; PHI0 ; 10.117 ; ; Fall ; PHI0 ; -; RD[6] ; PHI0 ; 9.134 ; ; Fall ; PHI0 ; -; RD[7] ; PHI0 ; 9.134 ; ; Fall ; PHI0 ; -+-----------+------------+--------+------+------------+-----------------+ ++----------------------------------------------------------------------+ +; Minimum Output Enable Times ; ++-----------+------------+-------+------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+-------+------+------------+-----------------+ +; FCK ; C25M ; 7.909 ; ; Rise ; C25M ; +; MOSI ; C25M ; 8.455 ; ; Rise ; C25M ; +; RD[*] ; C25M ; 9.405 ; ; Rise ; C25M ; +; RD[0] ; C25M ; 9.405 ; ; Rise ; C25M ; +; RD[1] ; C25M ; 9.405 ; ; Rise ; C25M ; +; RD[2] ; C25M ; 9.405 ; ; Rise ; C25M ; +; RD[3] ; C25M ; 9.405 ; ; Rise ; C25M ; +; RD[4] ; C25M ; 9.405 ; ; Rise ; C25M ; +; RD[5] ; C25M ; 9.405 ; ; Rise ; C25M ; +; RD[6] ; C25M ; 9.451 ; ; Rise ; C25M ; +; RD[7] ; C25M ; 9.451 ; ; Rise ; C25M ; +; SD[*] ; C25M ; 7.014 ; ; Rise ; C25M ; +; SD[0] ; C25M ; 7.446 ; ; Rise ; C25M ; +; SD[1] ; C25M ; 7.446 ; ; Rise ; C25M ; +; SD[2] ; C25M ; 7.014 ; ; Rise ; C25M ; +; SD[3] ; C25M ; 7.014 ; ; Rise ; C25M ; +; SD[4] ; C25M ; 7.446 ; ; Rise ; C25M ; +; SD[5] ; C25M ; 7.014 ; ; Rise ; C25M ; +; SD[6] ; C25M ; 7.014 ; ; Rise ; C25M ; +; SD[7] ; C25M ; 7.014 ; ; Rise ; C25M ; +; nFCS ; C25M ; 7.116 ; ; Rise ; C25M ; +; RD[*] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; +; RD[0] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; +; RD[1] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; +; RD[2] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; +; RD[3] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; +; RD[4] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; +; RD[5] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; +; RD[6] ; PHI0 ; 9.796 ; ; Rise ; PHI0 ; +; RD[7] ; PHI0 ; 9.796 ; ; Rise ; PHI0 ; +; RD[*] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; +; RD[0] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; +; RD[1] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; +; RD[2] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; +; RD[3] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; +; RD[4] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; +; RD[5] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; +; RD[6] ; PHI0 ; 9.796 ; ; Fall ; PHI0 ; +; RD[7] ; PHI0 ; 9.796 ; ; Fall ; PHI0 ; ++-----------+------------+-------+------+------------+-----------------+ +-------------------------------------------------------------------------------+ @@ -1048,45 +1048,45 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-----------+------------+-----------+-----------+------------+-----------------+ ; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; +-----------+------------+-----------+-----------+------------+-----------------+ -; FCK ; C25M ; 7.234 ; ; Rise ; C25M ; -; MOSI ; C25M ; 15.227 ; ; Rise ; C25M ; -; RD[*] ; C25M ; 11.907 ; ; Rise ; C25M ; -; RD[0] ; C25M ; 12.890 ; ; Rise ; C25M ; -; RD[1] ; C25M ; 12.890 ; ; Rise ; C25M ; -; RD[2] ; C25M ; 12.890 ; ; Rise ; C25M ; -; RD[3] ; C25M ; 12.890 ; ; Rise ; C25M ; -; RD[4] ; C25M ; 12.890 ; ; Rise ; C25M ; -; RD[5] ; C25M ; 12.890 ; ; Rise ; C25M ; -; RD[6] ; C25M ; 11.907 ; ; Rise ; C25M ; -; RD[7] ; C25M ; 11.907 ; ; Rise ; C25M ; -; SD[*] ; C25M ; 15.991 ; ; Rise ; C25M ; -; SD[0] ; C25M ; 16.393 ; ; Rise ; C25M ; -; SD[1] ; C25M ; 16.384 ; ; Rise ; C25M ; -; SD[2] ; C25M ; 15.991 ; ; Rise ; C25M ; -; SD[3] ; C25M ; 15.991 ; ; Rise ; C25M ; -; SD[4] ; C25M ; 16.393 ; ; Rise ; C25M ; -; SD[5] ; C25M ; 15.991 ; ; Rise ; C25M ; -; SD[6] ; C25M ; 15.991 ; ; Rise ; C25M ; -; SD[7] ; C25M ; 15.991 ; ; Rise ; C25M ; -; nFCS ; C25M ; 15.988 ; ; Rise ; C25M ; -; RD[*] ; PHI0 ; 9.134 ; ; Rise ; PHI0 ; -; RD[0] ; PHI0 ; 10.117 ; ; Rise ; PHI0 ; -; RD[1] ; PHI0 ; 10.117 ; ; Rise ; PHI0 ; -; RD[2] ; PHI0 ; 10.117 ; ; Rise ; PHI0 ; -; RD[3] ; PHI0 ; 10.117 ; ; Rise ; PHI0 ; -; RD[4] ; PHI0 ; 10.117 ; ; Rise ; PHI0 ; -; RD[5] ; PHI0 ; 10.117 ; ; Rise ; PHI0 ; -; RD[6] ; PHI0 ; 9.134 ; ; Rise ; PHI0 ; -; RD[7] ; PHI0 ; 9.134 ; ; Rise ; PHI0 ; -; RD[*] ; PHI0 ; 9.134 ; ; Fall ; PHI0 ; -; RD[0] ; PHI0 ; 10.117 ; ; Fall ; PHI0 ; -; RD[1] ; PHI0 ; 10.117 ; ; Fall ; PHI0 ; -; RD[2] ; PHI0 ; 10.117 ; ; Fall ; PHI0 ; -; RD[3] ; PHI0 ; 10.117 ; ; Fall ; PHI0 ; -; RD[4] ; PHI0 ; 10.117 ; ; Fall ; PHI0 ; -; RD[5] ; PHI0 ; 10.117 ; ; Fall ; PHI0 ; -; RD[6] ; PHI0 ; 9.134 ; ; Fall ; PHI0 ; -; RD[7] ; PHI0 ; 9.134 ; ; Fall ; PHI0 ; +; FCK ; C25M ; 7.909 ; ; Rise ; C25M ; +; MOSI ; C25M ; 8.455 ; ; Rise ; C25M ; +; RD[*] ; C25M ; 12.243 ; ; Rise ; C25M ; +; RD[0] ; C25M ; 12.243 ; ; Rise ; C25M ; +; RD[1] ; C25M ; 12.243 ; ; Rise ; C25M ; +; RD[2] ; C25M ; 12.243 ; ; Rise ; C25M ; +; RD[3] ; C25M ; 12.243 ; ; Rise ; C25M ; +; RD[4] ; C25M ; 12.243 ; ; Rise ; C25M ; +; RD[5] ; C25M ; 12.243 ; ; Rise ; C25M ; +; RD[6] ; C25M ; 12.289 ; ; Rise ; C25M ; +; RD[7] ; C25M ; 12.289 ; ; Rise ; C25M ; +; SD[*] ; C25M ; 7.014 ; ; Rise ; C25M ; +; SD[0] ; C25M ; 7.446 ; ; Rise ; C25M ; +; SD[1] ; C25M ; 7.446 ; ; Rise ; C25M ; +; SD[2] ; C25M ; 7.014 ; ; Rise ; C25M ; +; SD[3] ; C25M ; 7.014 ; ; Rise ; C25M ; +; SD[4] ; C25M ; 7.446 ; ; Rise ; C25M ; +; SD[5] ; C25M ; 7.014 ; ; Rise ; C25M ; +; SD[6] ; C25M ; 7.014 ; ; Rise ; C25M ; +; SD[7] ; C25M ; 7.014 ; ; Rise ; C25M ; +; nFCS ; C25M ; 7.116 ; ; Rise ; C25M ; +; RD[*] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; +; RD[0] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; +; RD[1] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; +; RD[2] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; +; RD[3] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; +; RD[4] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; +; RD[5] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; +; RD[6] ; PHI0 ; 9.796 ; ; Rise ; PHI0 ; +; RD[7] ; PHI0 ; 9.796 ; ; Rise ; PHI0 ; +; RD[*] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; +; RD[0] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; +; RD[1] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; +; RD[2] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; +; RD[3] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; +; RD[4] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; +; RD[5] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; +; RD[6] ; PHI0 ; 9.796 ; ; Fall ; PHI0 ; +; RD[7] ; PHI0 ; 9.796 ; ; Fall ; PHI0 ; +-----------+------------+-----------+-----------+------------+-----------------+ @@ -1095,45 +1095,45 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-----------+------------+-----------+-----------+------------+-----------------+ ; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; +-----------+------------+-----------+-----------+------------+-----------------+ -; FCK ; C25M ; 7.234 ; ; Rise ; C25M ; -; MOSI ; C25M ; 15.227 ; ; Rise ; C25M ; -; RD[*] ; C25M ; 10.273 ; ; Rise ; C25M ; -; RD[0] ; C25M ; 11.256 ; ; Rise ; C25M ; -; RD[1] ; C25M ; 11.256 ; ; Rise ; C25M ; -; RD[2] ; C25M ; 11.256 ; ; Rise ; C25M ; -; RD[3] ; C25M ; 11.256 ; ; Rise ; C25M ; -; RD[4] ; C25M ; 11.256 ; ; Rise ; C25M ; -; RD[5] ; C25M ; 11.256 ; ; Rise ; C25M ; -; RD[6] ; C25M ; 10.273 ; ; Rise ; C25M ; -; RD[7] ; C25M ; 10.273 ; ; Rise ; C25M ; -; SD[*] ; C25M ; 15.991 ; ; Rise ; C25M ; -; SD[0] ; C25M ; 16.393 ; ; Rise ; C25M ; -; SD[1] ; C25M ; 16.384 ; ; Rise ; C25M ; -; SD[2] ; C25M ; 15.991 ; ; Rise ; C25M ; -; SD[3] ; C25M ; 15.991 ; ; Rise ; C25M ; -; SD[4] ; C25M ; 16.393 ; ; Rise ; C25M ; -; SD[5] ; C25M ; 15.991 ; ; Rise ; C25M ; -; SD[6] ; C25M ; 15.991 ; ; Rise ; C25M ; -; SD[7] ; C25M ; 15.991 ; ; Rise ; C25M ; -; nFCS ; C25M ; 15.988 ; ; Rise ; C25M ; -; RD[*] ; PHI0 ; 9.134 ; ; Rise ; PHI0 ; -; RD[0] ; PHI0 ; 10.117 ; ; Rise ; PHI0 ; -; RD[1] ; PHI0 ; 10.117 ; ; Rise ; PHI0 ; -; RD[2] ; PHI0 ; 10.117 ; ; Rise ; PHI0 ; -; RD[3] ; PHI0 ; 10.117 ; ; Rise ; PHI0 ; -; RD[4] ; PHI0 ; 10.117 ; ; Rise ; PHI0 ; -; RD[5] ; PHI0 ; 10.117 ; ; Rise ; PHI0 ; -; RD[6] ; PHI0 ; 9.134 ; ; Rise ; PHI0 ; -; RD[7] ; PHI0 ; 9.134 ; ; Rise ; PHI0 ; -; RD[*] ; PHI0 ; 9.134 ; ; Fall ; PHI0 ; -; RD[0] ; PHI0 ; 10.117 ; ; Fall ; PHI0 ; -; RD[1] ; PHI0 ; 10.117 ; ; Fall ; PHI0 ; -; RD[2] ; PHI0 ; 10.117 ; ; Fall ; PHI0 ; -; RD[3] ; PHI0 ; 10.117 ; ; Fall ; PHI0 ; -; RD[4] ; PHI0 ; 10.117 ; ; Fall ; PHI0 ; -; RD[5] ; PHI0 ; 10.117 ; ; Fall ; PHI0 ; -; RD[6] ; PHI0 ; 9.134 ; ; Fall ; PHI0 ; -; RD[7] ; PHI0 ; 9.134 ; ; Fall ; PHI0 ; +; FCK ; C25M ; 7.909 ; ; Rise ; C25M ; +; MOSI ; C25M ; 8.455 ; ; Rise ; C25M ; +; RD[*] ; C25M ; 9.405 ; ; Rise ; C25M ; +; RD[0] ; C25M ; 9.405 ; ; Rise ; C25M ; +; RD[1] ; C25M ; 9.405 ; ; Rise ; C25M ; +; RD[2] ; C25M ; 9.405 ; ; Rise ; C25M ; +; RD[3] ; C25M ; 9.405 ; ; Rise ; C25M ; +; RD[4] ; C25M ; 9.405 ; ; Rise ; C25M ; +; RD[5] ; C25M ; 9.405 ; ; Rise ; C25M ; +; RD[6] ; C25M ; 9.451 ; ; Rise ; C25M ; +; RD[7] ; C25M ; 9.451 ; ; Rise ; C25M ; +; SD[*] ; C25M ; 7.014 ; ; Rise ; C25M ; +; SD[0] ; C25M ; 7.446 ; ; Rise ; C25M ; +; SD[1] ; C25M ; 7.446 ; ; Rise ; C25M ; +; SD[2] ; C25M ; 7.014 ; ; Rise ; C25M ; +; SD[3] ; C25M ; 7.014 ; ; Rise ; C25M ; +; SD[4] ; C25M ; 7.446 ; ; Rise ; C25M ; +; SD[5] ; C25M ; 7.014 ; ; Rise ; C25M ; +; SD[6] ; C25M ; 7.014 ; ; Rise ; C25M ; +; SD[7] ; C25M ; 7.014 ; ; Rise ; C25M ; +; nFCS ; C25M ; 7.116 ; ; Rise ; C25M ; +; RD[*] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; +; RD[0] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; +; RD[1] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; +; RD[2] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; +; RD[3] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; +; RD[4] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; +; RD[5] ; PHI0 ; 9.750 ; ; Rise ; PHI0 ; +; RD[6] ; PHI0 ; 9.796 ; ; Rise ; PHI0 ; +; RD[7] ; PHI0 ; 9.796 ; ; Rise ; PHI0 ; +; RD[*] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; +; RD[0] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; +; RD[1] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; +; RD[2] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; +; RD[3] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; +; RD[4] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; +; RD[5] ; PHI0 ; 9.750 ; ; Fall ; PHI0 ; +; RD[6] ; PHI0 ; 9.796 ; ; Fall ; PHI0 ; +; RD[7] ; PHI0 ; 9.796 ; ; Fall ; PHI0 ; +-----------+------------+-----------+-----------+------------+-----------------+ @@ -1213,7 +1213,7 @@ No dedicated SERDES Receiver circuitry present in device or used in design Info: ******************************************************************* Info: Running Quartus II 32-bit TimeQuest Timing Analyzer Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - Info: Processing started: Tue Apr 20 05:43:05 2021 + Info: Processing started: Tue Apr 20 04:20:00 2021 Info: Command: quartus_sta GR8RAM -c GR8RAM Info: qsta_default_script.tcl version: #1 Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected @@ -1228,36 +1228,36 @@ Info (332105): Deriving Clocks Info (332105): create_clock -period 1.000 -name PHI0 PHI0 Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON Critical Warning (332148): Timing requirements not met -Info (332146): Worst-case setup slack is -9.844 +Info (332146): Worst-case setup slack is -9.005 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== - Info (332119): -9.844 -724.767 C25M - Info (332119): -0.019 -0.019 PHI0 -Info (332146): Worst-case hold slack is -0.952 + Info (332119): -9.005 -699.357 C25M + Info (332119): -0.425 -0.425 PHI0 +Info (332146): Worst-case hold slack is -0.248 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== - Info (332119): -0.952 -0.952 PHI0 - Info (332119): 1.385 0.000 C25M -Info (332146): Worst-case recovery slack is -4.389 + Info (332119): -0.248 -0.248 PHI0 + Info (332119): 1.400 0.000 C25M +Info (332146): Worst-case recovery slack is -4.412 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== - Info (332119): -4.389 -127.281 C25M -Info (332146): Worst-case removal slack is 4.835 + Info (332119): -4.412 -127.948 C25M +Info (332146): Worst-case removal slack is 4.858 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== - Info (332119): 4.835 0.000 C25M -Info (332146): Worst-case minimum pulse width slack is -3.000 + Info (332119): 4.858 0.000 C25M +Info (332146): Worst-case minimum pulse width slack is -2.289 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== - Info (332119): -3.000 -3.000 PHI0 Info (332119): -2.289 -2.289 C25M + Info (332119): -2.289 -2.289 PHI0 Info (332001): The selected device family is not supported by the report_metastability command. Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings - Info: Peak virtual memory: 275 megabytes - Info: Processing ended: Tue Apr 20 05:43:09 2021 - Info: Elapsed time: 00:00:04 + Info: Peak virtual memory: 278 megabytes + Info: Processing ended: Tue Apr 20 04:20:05 2021 + Info: Elapsed time: 00:00:05 Info: Total CPU time (on all processors): 00:00:04 diff --git a/cpld/output_files/GR8RAM.sta.summary b/cpld/output_files/GR8RAM.sta.summary index ff5acb0..c650a04 100755 --- a/cpld/output_files/GR8RAM.sta.summary +++ b/cpld/output_files/GR8RAM.sta.summary @@ -3,35 +3,35 @@ TimeQuest Timing Analyzer Summary ------------------------------------------------------------ Type : Setup 'C25M' -Slack : -9.844 -TNS : -724.767 +Slack : -9.005 +TNS : -699.357 Type : Setup 'PHI0' -Slack : -0.019 -TNS : -0.019 +Slack : -0.425 +TNS : -0.425 Type : Hold 'PHI0' -Slack : -0.952 -TNS : -0.952 +Slack : -0.248 +TNS : -0.248 Type : Hold 'C25M' -Slack : 1.385 +Slack : 1.400 TNS : 0.000 Type : Recovery 'C25M' -Slack : -4.389 -TNS : -127.281 +Slack : -4.412 +TNS : -127.948 Type : Removal 'C25M' -Slack : 4.835 +Slack : 4.858 TNS : 0.000 -Type : Minimum Pulse Width 'PHI0' -Slack : -3.000 -TNS : -3.000 - Type : Minimum Pulse Width 'C25M' Slack : -2.289 TNS : -2.289 +Type : Minimum Pulse Width 'PHI0' +Slack : -2.289 +TNS : -2.289 + ------------------------------------------------------------