Apple-2-HW/GR8RAM
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This commit is contained in:
Zane Kaminski 2021-04-11 15:39:19 -04:00
parent fc2e875ac2
commit d8a5dc069d
80 changed files with 77522 additions and 120239 deletions
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37
Documentation/
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@ -1,37 +0,0 @@
GR8RAM/LibraryCard flash memory map
-----------------------------
FF FFFF | |
.. .... | reserved (12 MB) |
40 0000 | |
-----------------------------
3F FFFF | |
.. .... | firmware 3 (1 MB) |
30 0000 | |
-----------------------------
2F FFFF | |
.. .... | firmware 2 (1 MB) |
20 0000 | |
-----------------------------
1F FFFF | |
.. .... | firmware 1 (1 MB) |
10 0000 | |
-----------------------------
0F FFFF | |
.. .... | firmware 0 (1 MB) |
00 0000 | |
-----------------------------
Firmware area map (X == 0, 1, 2, or 3)
-----------------------------
XF FFFF | |
.. .... | reserved (510 kB) |
X8 0800 | |
-----------------------------
X8 07FF | |
.. .... | IOSEL area (2 kB) |
X8 0000 | |
-----------------------------
X7 FFFF | |
.. .... | 256x IOSTRB area (512 kB) |
X0 0000 | |
-----------------------------

38
Documentation/Flash Map Normal file
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@ -0,0 +1,38 @@
GR8RAM flash memory map
.... -----------------------------
7FFF | |
.... | firmware 3 (8 kB) |
6000 | |
-----------------------------
5FFF | |
.... | firmware 2 (8 kB) |
4000 | |
-----------------------------
3FFF | |
.... | firmware 1 (8 kB) |
2000 | |
-----------------------------
1FFF | |
.... | firmware 0 (8 kB) |
0000 | |
-----------------------------
Firmware area map (N=$0000, $2000, $4000, $6000)
-----------------------------
N+1FFF | |
.... | IOSTRB bank 1 (2 kB) |
N+1800 | |
-----------------------------
N+17FF | |
.... | IOSEL bank 1 (2 kB) |
N+1000 | |
-----------------------------
N+0FFF | |
.... | IOSTRB bank 0 (2 kB) |
N+0800 | |
-----------------------------
N+07FF | |
.... | IOSEL bank 0 (2 kB) |
N+0000 | |
-----------------------------

45
Documentation/Registers
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@ -1,45 +0,0 @@
Addr Slinky GR8RAM TimeMachine
$0 RAddrL RAddrL RAddrL
$1 RAddrM RAddrM RAddrM
$2 RAddrH RAddrH RAddrH
$3 RData RData RData
$4 DMAAddrL
$5 DMAAddrH
$6
$7
$8
$9
$A
$B
$C
$D Readin/out Readin/out
$E Command Command
$F Bank Bank Bank
GR8RAM commands
CmdNum Description Argument
$00 SetReadinout RiNum/RoNum
$EF CFGPrgmEN don't care
$EE CFGEraseEN don't care
GR8RAM Readin
RiNum Description Data
$10 SPI flash { MOSI(1), X(6), CS(1) }
$11 SPI flash + clk pulse { MOSI(1), X(6), CS(1) }
$13 CFG flash + clk pulse { CFGDin(1), X(7) }
$20 Mode { RF/nSlinky(1), X(4), Size(3) }
$21 RAddrHH { X(7), RAddr[24](1) }
GR8RAM Readout
RoNum Description
$00 Magic $C1
$01 Card ID $00
$10 SPI flash { MISO(1), X(7) }
$20 Mode { RF/nSlinky(1), X(4), Size(3) }
TimeMachine commands
$XX DMA into Apple RAM Length
$XX DMA into Slinky RAM Length
$XX DMA into Apple RAM Length-256
$XX DMA into Slinky RAM Length-256

6
Documentation/Settings
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@ -1,6 +0,0 @@
GR8RAM Settings (not applicable to Library Card!)
Settings[15] SetValid (1 = invalid, 0 = valid)
Settings[14] SetFW (1 = RAMFactor, 0 = Slinky)
Settings[13] SetLim8M
Settings[12:0] Reserved

107
Documentation/UFM Load
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@ -1,107 +0,0 @@
UFM Load
LState ARCLK ARShft DRCLK DRShft UFM
--------------------------------------------------------------------------------
$0000 0 1 0 0
$0FBF 0 1 0 0
...
$0FC0 1 1 0 0
$0FC1 1 1 0 0
$0FC2 0 1 0 0
$0FC3 0 1 0 0
$0FC4 1 1 0 0
$0FC5 1 1 0 0
$0FC6 0 1 0 0
$0FC7 0 1 0 0
$0FC8 1 1 0 0
$0FC9 1 1 0 0
$0FCA 0 1 0 0
$0FCB 0 1 0 0
$0FCC 1 1 0 0
$0FCD 1 1 0 0
$0FCE 0 1 0 0
$0FCF 0 1 0 0
$0FD0 1 1 0 0
$0FD1 1 1 0 0
$0FD2 0 1 0 0
$0FD3 0 1 0 0
$0FD4 1 1 0 0
$0FD5 1 1 0 0
$0FD6 0 1 0 0
$0FD7 0 1 0 0
$0FD8 1 1 0 0
$0FD9 1 1 0 0
$0FDA 0 1 0 0
$0FDB 0 1 0 0
$0FDC 1 1 0 0
$0FDD 1 1 0 0
$0FDE 0 1 0 0
$0FDF 0 1 0 0
$0FE0 1 1 0 0
$0FE1 1 1 0 0
$0FE2 0 1 0 0
$0FE3 0 1 0 0
$0FE4 1 1 0 0
$0FE5 1 1 0 0
$0FE6 0 1 0 0
$0FE7 0 1 0 0
$0FE8 1 1 0 0
$0FE9 1 1 0 0
$0FEA 0 1 0 0
$0FEB 0 1 0 0
$0FEC 1 1 0 0
$0FED 1 1 0 0
$0FEE 0 1 0 0
$0FEF 0 1 0 0
$0FF0 1 1 0 0
$0FF1 1 1 0 0
$0FF2 0 1 0 0
$0FF3 0 1 0 0
$0FF4 1 1 0 0
$0FF5 1 1 0 0
$0FF6 0 1 0 0
$0FF7 0 1 0 0
$0FF8 1 1 0 0
$0FF9 1 1 0 0
$0FFA 0 1 0 0
$0FFB 0 1 0 0
$0FFC 1 1 0 0
$0FFD 1 1 0 0
$0FFE 0 1 0 0
$0FFF 0 1 0 0
$1000 0 0 1 0 parallel load into DR
$1001 0 0 1 0
$1002 0 0 0 1
$1003 0 0 0 1
$1004 0 0 1 1 SetLoaded <= Dout
$1005 0 0 1 1
$1006 0 0 0 1
$1007 0 0 0 1
$1008 0 0 1 1 latch DR[14] (SetFW)
$1009 0 0 1 1
$100A 0 0 0 1
$100B 0 0 0 1
$100C 1 0 0 1 latch DR[13] (SetLim8M)
$100D 1 0 0 1
$100E 0 0 0 0
$100F 0 0 0 0
...
$1FF0 0 0 1 0 parallel load into DR
$1FF1 0 0 1 0
$1FF2 0 0 0 1
$1FF3 0 0 0 1
$1FF4 0 0 1 1 SetLoaded <= Dout
$1FF5 0 0 1 1
$1FF6 0 0 0 1
$1FF7 0 0 0 1
$1FF8 0 0 1 1 latch DR[14] (SetFW)
$1FF9 0 0 1 1
$1FFA 0 0 0 1
$1FFB 0 0 0 1
$1FFC 1 0 0 1 latch DR[13] (SetLim8M)
$1FFD 1 0 0 1
$1FFE 0 0 0 0
$1FFF 0 0 0 0
$2000 0 0 0 0 Everything 0, set SetLoaded

25
GR8RAM-cache.lib
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@ -548,6 +548,31 @@ X 1 1 0 -100 100 U 50 50 1 1 I
ENDDRAW ENDDRAW
ENDDEF ENDDEF
# #
# Switch_SW_DIP_x02
#
DEF Switch_SW_DIP_x02 SW 0 0 Y N 1 F N
F0 "SW" 0 250 50 H V C CNN
F1 "Switch_SW_DIP_x02" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
SW?DIP?x2*
$ENDFPLIST
DRAW
C -80 0 20 0 0 0 N
C -80 100 20 0 0 0 N
C 80 0 20 0 0 0 N
C 80 100 20 0 0 0 N
S -150 200 150 -100 0 1 10 f
P 2 0 0 0 -60 5 93 46 N
P 2 0 0 0 -60 105 93 146 N
X ~ 1 -300 100 200 R 50 50 1 1 P
X ~ 2 -300 0 200 R 50 50 1 1 P
X ~ 3 300 0 200 L 50 50 1 1 P
X ~ 4 300 100 200 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# power_+12V # power_+12V
# #
DEF power_+12V #PWR 0 0 Y Y 1 F P DEF power_+12V #PWR 0 0 Y Y 1 F P

21545
GR8RAM.kicad_pcb
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1641
GR8RAM.sch
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20
cpld/GR8RAM.dpf Executable file
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@ -0,0 +1,20 @@
<?xml version="1.0" encoding="UTF-8"?>
<pin_planner>
<pin_info>
<pin name="Ddor" source="Pin Planner" >
</pin>
<pin name="SDp1[" source="Pin Planner" >
</pin>
<pin name="sa[10[" source="Pin Planner" >
</pin>
<pin name="fw[0]" source="Pin Planner" >
</pin>
</pin_info>
<buses>
</buses>
<group_file_association>
</group_file_association>
<pin_planner_file_specifies>
</pin_planner_file_specifies>
</pin_planner>

73
cpld/GR8RAM.qsf
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@ -71,4 +71,75 @@ set_global_assignment -name SYNTHESIS_SEED 123
set_global_assignment -name SEED 235 set_global_assignment -name SEED 235
set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII "MINIMIZE AREA" set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII "MINIMIZE AREA"
set_global_assignment -name ROUTER_REGISTER_DUPLICATION OFF set_global_assignment -name ROUTER_REGISTER_DUPLICATION OFF
set_global_assignment -name VERILOG_FILE GR8RAM.v set_global_assignment -name VERILOG_FILE GR8RAM.v
set_location_assignment PIN_1 -to RA[4]
set_location_assignment PIN_2 -to RA[5]
set_location_assignment PIN_3 -to RA[6]
set_location_assignment PIN_4 -to RA[3]
set_location_assignment PIN_5 -to nFCS
set_location_assignment PIN_6 -to RA[7]
set_location_assignment PIN_7 -to RA[8]
set_location_assignment PIN_8 -to RA[9]
set_location_assignment PIN_12 -to FCK
set_location_assignment PIN_14 -to RA[10]
set_location_assignment PIN_15 -to MOSI
set_location_assignment PIN_16 -to MISO
set_location_assignment PIN_17 -to Ddir
set_location_assignment PIN_30 -to nRESout
set_location_assignment PIN_34 -to RA[11]
set_location_assignment PIN_35 -to RA[12]
set_location_assignment PIN_36 -to RA[13]
set_location_assignment PIN_37 -to RA[14]
set_location_assignment PIN_38 -to RA[15]
set_location_assignment PIN_39 -to nIOSEL
set_location_assignment PIN_42 -to nIOSTRB
set_location_assignment PIN_40 -to nDEVSEL
set_location_assignment PIN_41 -to PHI0
set_location_assignment PIN_43 -to nWE
set_location_assignment PIN_44 -to nRES
set_location_assignment PIN_47 -to SD[1]
set_location_assignment PIN_50 -to SD[0]
set_location_assignment PIN_51 -to SD[4]
set_location_assignment PIN_100 -to RA[0]
set_location_assignment PIN_99 -to RD[7]
set_location_assignment PIN_52 -to SD[5]
set_location_assignment PIN_54 -to SD[7]
set_location_assignment PIN_55 -to SD[3]
set_location_assignment PIN_56 -to SD[2]
set_location_assignment PIN_53 -to SD[6]
set_location_assignment PIN_57 -to DQMH
set_location_assignment PIN_58 -to nSWE
set_location_assignment PIN_62 -to nRAS
set_location_assignment PIN_61 -to nCAS
set_location_assignment PIN_64 -to C25M
set_location_assignment PIN_66 -to RCKE
set_location_assignment PIN_67 -to nRCS
set_location_assignment PIN_68 -to SA[12]
set_location_assignment PIN_69 -to SBA[0]
set_location_assignment PIN_70 -to SA[11]
set_location_assignment PIN_71 -to SBA[1]
set_location_assignment PIN_72 -to SA[9]
set_location_assignment PIN_73 -to SA[10]
set_location_assignment PIN_74 -to SA[8]
set_location_assignment PIN_75 -to SA[0]
set_location_assignment PIN_76 -to SA[4]
set_location_assignment PIN_77 -to SA[6]
set_location_assignment PIN_78 -to SA[7]
set_location_assignment PIN_81 -to SA[1]
set_location_assignment PIN_82 -to SA[2]
set_location_assignment PIN_83 -to SA[5]
set_location_assignment PIN_84 -to SA[3]
set_location_assignment PIN_85 -to DQML
set_location_assignment PIN_86 -to RD[0]
set_location_assignment PIN_87 -to RD[1]
set_location_assignment PIN_88 -to RD[2]
set_location_assignment PIN_89 -to RD[3]
set_location_assignment PIN_90 -to RD[4]
set_location_assignment PIN_91 -to RD[5]
set_location_assignment PIN_92 -to RD[6]
set_location_assignment PIN_97 -to RA[2]
set_location_assignment PIN_98 -to RA[1]
set_location_assignment PIN_96 -to SetFW[0]
set_location_assignment PIN_95 -to SetFW[1]
set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 1
set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 2

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cpld/GR8RAM.qws
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43
cpld/GR8RAM.v
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@ -1,6 +1,6 @@
module GR8RAM(C25M, PHI0, nRES, nRESout, module GR8RAM(C25M, PHI0, nRES, nRESout,
nIOSEL, nDEVSEL, nIOSTRB, nIOSEL, nDEVSEL, nIOSTRB,
SetRF, SetLim8M, SetFW,
RA, nWE, RD, RDdir, RA, nWE, RD, RDdir,
SBA, SA, nRCS, nRAS, nCAS, nSWE, DQML, DQMH, RCKE, SD, SBA, SA, nRCS, nRAS, nCAS, nSWE, DQML, DQMH, RCKE, SD,
nFCS, FCK, MISO, MOSI); nFCS, FCK, MISO, MOSI);
@ -42,10 +42,11 @@ module GR8RAM(C25M, PHI0, nRES, nRESout,
/* Apple select signals */ /* Apple select signals */
wire ROMSpecSEL = RA[15:12]==4'hC && RA[11:8]!=4'h0; wire ROMSpecSEL = RA[15:12]==4'hC && RA[11:8]!=4'h0;
wire BankSpecSEL = RA[3:0]==4'hF; wire BankSpecSEL = RA[3:0]==4'hF;
wire RAMSpecSEL = RA[15:12]==4'hC && RA[11:8]==4'h0 && RA[7] && RA[3:0]==4'h3 && REGEN; wire REGSpecSEL = RA[15:12]==4'hC && RA[11:8]==4'h0 && RA[7] && REGEN;
wire AddrHSpecSEL = RA[3:0]==4'h2; wire RAMSpecSEL = REGSpecSEL && RA[3:0]==4'h3 && (~SetLim1M || Addr[23:20]==0) && (~SetLim8M || ~Addr[23]);
wire AddrMSpecSEL = RA[3:0]==4'h1; wire AddrHSpecSEL = REGSpecSEL && RA[3:0]==4'h2;
wire AddrLSpecSEL = RA[3:0]==4'h0; wire AddrMSpecSEL = REGSpecSEL && RA[3:0]==4'h1;
wire AddrLSpecSEL = REGSpecSEL && RA[3:0]==4'h0;
reg ROMSpecSELr, RAMSpecSELr, nWEr; reg ROMSpecSELr, RAMSpecSELr, nWEr;
wire BankSEL = REGEN && ~nDEVSEL && BankSpecSEL; wire BankSEL = REGEN && ~nDEVSEL && BankSpecSEL;
wire RAMSEL = ~nDEVSEL && RAMSpecSELr; wire RAMSEL = ~nDEVSEL && RAMSpecSELr;
@ -53,12 +54,10 @@ module GR8RAM(C25M, PHI0, nRES, nRESout,
wire AddrHSEL = REGEN && ~nDEVSEL && AddrHSpecSEL; wire AddrHSEL = REGEN && ~nDEVSEL && AddrHSpecSEL;
wire AddrMSEL = REGEN && ~nDEVSEL && AddrMSpecSEL; wire AddrMSEL = REGEN && ~nDEVSEL && AddrMSpecSEL;
wire AddrLSEL = REGEN && ~nDEVSEL && AddrLSpecSEL; wire AddrLSEL = REGEN && ~nDEVSEL && AddrLSpecSEL;
always @(posedge C25M) begin always @(posedge PHI0) begin
if (PSStart) begin ROMSpecSELr <= ROMSpecSEL;
ROMSpecSELr <= ROMSpecSEL; RAMSpecSELr <= RAMSpecSEL;
RAMSpecSELr <= RAMSpecSEL; nWEr <= nWE;
nWEr <= nWE;
end
end end
/* IOROMEN and REGEN control */ /* IOROMEN and REGEN control */
@ -174,7 +173,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout,
FCK <= ~(IS==5); FCK <= ~(IS==5);
end end
endcase endcase
FCS <= IS==5 || IS==6; FCS <= IS==4 || IS==5 || IS==6;
MOSIOE <= IS==5; MOSIOE <= IS==5;
end end
@ -183,16 +182,16 @@ module GR8RAM(C25M, PHI0, nRES, nRESout,
1, 2: begin 1, 2: begin
case (LS[2:0]) case (LS[2:0])
3'h3: MOSIout <= 1'b0; // Command bit 7 3'h3: MOSIout <= 1'b0; // Command bit 7
3'h4: MOSIout <= SetRF; // Address bit 23 3'h4: MOSIout <= 1'b0; // Address bit 23
3'h5: MOSIout <= 1'b0; // Address bit 15 3'h5: MOSIout <= 1'b0; // Address bit 15
3'h6: MOSIout <= 1'b0; // Address bit 7 3'h6: MOSIout <= 1'b0; // Address bit 7
default MOSIout <= 1'b0; default MOSIout <= 1'b0;
endcase endcase
end 3, 4: begin end 3, 4: begin
case (LS[2:0]) case (LS[2:0])
3'h3: MOSIout <= 1'b1; // Command bit 6 3'h3: MOSIout <= 1'b0; // Command bit 6
3'h4: MOSIout <= 1'b0; // Address bit 22 3'h4: MOSIout <= 1'b0; // Address bit 22
3'h5: MOSIout <= 1'b0; // Address bit 14 3'h5: MOSIout <= SetFW[1]; // Address bit 14
3'h6: MOSIout <= 1'b0; // Address bit 6 3'h6: MOSIout <= 1'b0; // Address bit 6
default MOSIout <= 1'b0; default MOSIout <= 1'b0;
endcase endcase
@ -200,13 +199,13 @@ module GR8RAM(C25M, PHI0, nRES, nRESout,
case (LS[2:0]) case (LS[2:0])
3'h3: MOSIout <= 1'b1; // Command bit 5 3'h3: MOSIout <= 1'b1; // Command bit 5
3'h4: MOSIout <= 1'b0; // Address bit 21 3'h4: MOSIout <= 1'b0; // Address bit 21
3'h5: MOSIout <= 1'b0; // Address bit 13 3'h5: MOSIout <= SetFW[0]; // Address bit 13
3'h6: MOSIout <= 1'b0; // Address bit 5 3'h6: MOSIout <= 1'b0; // Address bit 5
default MOSIout <= 1'b0; default MOSIout <= 1'b0;
endcase endcase
end 7, 8: begin end 7, 8: begin
case (LS[2:0]) case (LS[2:0])
3'h3: MOSIout <= 1'b0; // Command bit 4 3'h3: MOSIout <= 1'b1; // Command bit 4
3'h4: MOSIout <= 1'b0; // Address bit 20 3'h4: MOSIout <= 1'b0; // Address bit 20
3'h5: MOSIout <= 1'b0; // Address bit 12 3'h5: MOSIout <= 1'b0; // Address bit 12
3'h6: MOSIout <= 1'b0; // Address bit 4 3'h6: MOSIout <= 1'b0; // Address bit 4
@ -248,8 +247,10 @@ module GR8RAM(C25M, PHI0, nRES, nRESout,
endcase endcase
end end
input SetRF; input [1:0] SetFW;
input SetLim8M; wire SetRF = SetFW[1:0] != 2'b11;
wire SetLim1M = SetFW[1];
wire SetLim8M = SetFW[1:0] != 2'b00;
/* SDRAM data bus */ /* SDRAM data bus */
inout [7:0] SD = SDOE ? WRD[7:0] : 8'bZ; inout [7:0] SD = SDOE ? WRD[7:0] : 8'bZ;
@ -452,7 +453,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout,
SBA[1:0] <= { 2'b10 }; SBA[1:0] <= { 2'b10 };
SA[12:0] <= { 10'b0011000100, LS[12:10] }; SA[12:0] <= { 10'b0011000100, LS[12:10] };
end else if (RAMSpecSELr) begin end else if (RAMSpecSELr) begin
SBA[1:0] <= { 1'b0, Addr[23] && SetLim8M && SetRF }; SBA[1:0] <= { 1'b0, Addr[23] && SetRF };
SA[12:0] <= { SetRF ? Addr [22:20] : 3'b000, Addr[19:10]}; SA[12:0] <= { SetRF ? Addr [22:20] : 3'b000, Addr[19:10]};
end else begin end else begin
SBA[1:0] <= 2'b10; SBA[1:0] <= 2'b10;
@ -460,7 +461,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout,
end end
end 2: begin // RD end 2: begin // RD
if (RAMSpecSELr) begin if (RAMSpecSELr) begin
SBA[1:0] <= { 1'b0, Addr[23] && SetLim8M && SetRF }; SBA[1:0] <= { 1'b0, Addr[23] && SetRF };
SA[12:0] <= { 4'b0011, Addr[9:1] }; SA[12:0] <= { 4'b0011, Addr[9:1] };
DQML <= Addr[0]; DQML <= Addr[0];
DQMH <= ~Addr[0]; DQMH <= ~Addr[0];

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cpld/db/GR8RAM.asm.qmsg
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@ -1,6 +1,6 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616429543853 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618161759471 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616429543868 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 22 12:12:23 2021 " "Processing started: Mon Mar 22 12:12:23 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616429543868 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1616429543868 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618161759502 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 11 13:22:38 2021 " "Processing started: Sun Apr 11 13:22:38 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618161759502 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1618161759502 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1616429543868 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1618161759502 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1616429545103 ""} { "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1618161760940 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1616429545134 ""} { "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1618161760971 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "293 " "Peak virtual memory: 293 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616429545696 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 22 12:12:25 2021 " "Processing ended: Mon Mar 22 12:12:25 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616429545696 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616429545696 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616429545696 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1616429545696 ""} { "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "293 " "Peak virtual memory: 293 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618161761456 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 11 13:22:41 2021 " "Processing ended: Sun Apr 11 13:22:41 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618161761456 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618161761456 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618161761456 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1618161761456 ""}

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cpld/db/GR8RAM.db_info
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@ -1,3 +1,3 @@
Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Version_Index = 302049280 Version_Index = 302049280
Creation_Time = Mon Mar 22 01:13:17 2021 Creation_Time = Sun Apr 11 00:06:29 2021

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@ -76,9 +76,6 @@ C25M => Addr[22].CLK
C25M => Addr[23].CLK C25M => Addr[23].CLK
C25M => REGEN.CLK C25M => REGEN.CLK
C25M => IOROMEN.CLK C25M => IOROMEN.CLK
C25M => nWEr.CLK
C25M => RAMSpecSELr.CLK
C25M => ROMSpecSELr.CLK
C25M => nRESout~reg0.CLK C25M => nRESout~reg0.CLK
C25M => LS[0].CLK C25M => LS[0].CLK
C25M => LS[1].CLK C25M => LS[1].CLK
@ -100,6 +97,9 @@ C25M => PHI0r2.CLK
C25M => PHI0r1.CLK C25M => PHI0r1.CLK
C25M => IS~7.DATAIN C25M => IS~7.DATAIN
PHI0 => comb.IN1 PHI0 => comb.IN1
PHI0 => nWEr.CLK
PHI0 => RAMSpecSELr.CLK
PHI0 => ROMSpecSELr.CLK
PHI0 => PHI0r1.DATAIN PHI0 => PHI0r1.DATAIN
nRES => nRESr0.DATAIN nRES => nRESr0.DATAIN
nRESout <= nRESout~reg0.DB_MAX_OUTPUT_PORT_TYPE nRESout <= nRESout~reg0.DB_MAX_OUTPUT_PORT_TYPE
@ -110,61 +110,60 @@ nDEVSEL => RAMSEL.IN1
nDEVSEL => comb.IN1 nDEVSEL => comb.IN1
nIOSTRB => comb.IN1 nIOSTRB => comb.IN1
nIOSTRB => always5.IN1 nIOSTRB => always5.IN1
SetRF => MOSIout.DATAB SetFW[0] => Mux1.IN10
SetRF => always10.IN1 SetFW[0] => Equal18.IN1
SetRF => SA.OUTPUTSELECT SetFW[0] => Equal19.IN1
SetRF => SA.OUTPUTSELECT SetFW[1] => MOSIout.DATAB
SetRF => SA.OUTPUTSELECT SetFW[1] => comb.IN1
SetRF => SBA.IN1 SetFW[1] => Equal18.IN0
SetRF => always10.IN1 SetFW[1] => Equal19.IN0
SetLim8M => SBA.IN1
RA[0] => DQML.DATAA RA[0] => DQML.DATAA
RA[0] => Equal6.IN3 RA[0] => Equal6.IN3
RA[0] => Equal9.IN1 RA[0] => Equal9.IN1
RA[0] => Equal10.IN3 RA[0] => Equal11.IN3
RA[0] => Equal11.IN0 RA[0] => Equal12.IN0
RA[0] => Equal12.IN3 RA[0] => Equal13.IN3
RA[0] => Equal13.IN10 RA[0] => Equal14.IN10
RA[0] => DQMH.DATAA RA[0] => DQMH.DATAA
RA[1] => SA.DATAA RA[1] => SA.DATAA
RA[1] => Equal6.IN2 RA[1] => Equal6.IN2
RA[1] => Equal9.IN0 RA[1] => Equal9.IN0
RA[1] => Equal10.IN0 RA[1] => Equal11.IN0
RA[1] => Equal11.IN3 RA[1] => Equal12.IN3
RA[1] => Equal12.IN2 RA[1] => Equal13.IN2
RA[1] => Equal13.IN9 RA[1] => Equal14.IN9
RA[2] => SA.DATAA RA[2] => SA.DATAA
RA[2] => Equal6.IN1 RA[2] => Equal6.IN1
RA[2] => Equal9.IN3 RA[2] => Equal9.IN3
RA[2] => Equal10.IN2
RA[2] => Equal11.IN2 RA[2] => Equal11.IN2
RA[2] => Equal12.IN1 RA[2] => Equal12.IN2
RA[2] => Equal13.IN8 RA[2] => Equal13.IN1
RA[2] => Equal14.IN8
RA[3] => SA.DATAA RA[3] => SA.DATAA
RA[3] => Equal6.IN0 RA[3] => Equal6.IN0
RA[3] => Equal9.IN2 RA[3] => Equal9.IN2
RA[3] => Equal10.IN1
RA[3] => Equal11.IN1 RA[3] => Equal11.IN1
RA[3] => Equal12.IN0 RA[3] => Equal12.IN1
RA[3] => Equal13.IN7 RA[3] => Equal13.IN0
RA[3] => Equal14.IN7
RA[4] => SA.DATAA RA[4] => SA.DATAA
RA[4] => Equal13.IN6 RA[4] => Equal14.IN6
RA[5] => SA.DATAA RA[5] => SA.DATAA
RA[5] => Equal13.IN5 RA[5] => Equal14.IN5
RA[6] => SA.DATAA RA[6] => SA.DATAA
RA[6] => Equal13.IN4 RA[6] => Equal14.IN4
RA[7] => comb.IN1 RA[7] => comb.IN1
RA[7] => SA.DATAA RA[7] => SA.DATAA
RA[7] => Equal13.IN3 RA[7] => Equal14.IN3
RA[8] => SA.DATAA RA[8] => SA.DATAA
RA[8] => Equal8.IN3 RA[8] => Equal8.IN3
RA[8] => Equal13.IN2 RA[8] => Equal14.IN2
RA[9] => SA.DATAA RA[9] => SA.DATAA
RA[9] => Equal8.IN2 RA[9] => Equal8.IN2
RA[9] => Equal13.IN1 RA[9] => Equal14.IN1
RA[10] => SA.DATAA RA[10] => SA.DATAA
RA[10] => Equal8.IN1 RA[10] => Equal8.IN1
RA[10] => Equal13.IN0 RA[10] => Equal14.IN0
RA[11] => SA.DATAA RA[11] => SA.DATAA
RA[11] => Equal8.IN0 RA[11] => Equal8.IN0
RA[12] => Equal7.IN3 RA[12] => Equal7.IN3

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@ -1,18 +1,18 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616429527039 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618161736158 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616429527039 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 22 12:12:06 2021 " "Processing started: Mon Mar 22 12:12:06 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616429527039 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1616429527039 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618161736158 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 11 13:22:15 2021 " "Processing started: Sun Apr 11 13:22:15 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618161736158 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618161736158 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1616429527039 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618161736158 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1616429528633 ""} { "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1618161737908 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(80) " "Verilog HDL warning at GR8RAM.v(80): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 80 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1616429528805 ""} { "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(79) " "Verilog HDL warning at GR8RAM.v(79): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 79 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618161738205 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(255) " "Verilog HDL warning at GR8RAM.v(255): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 255 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1616429528805 ""} { "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(256) " "Verilog HDL warning at GR8RAM.v(256): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 256 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618161738205 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616429528805 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1616429528805 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1618161738205 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1618161738205 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1616429528914 ""} { "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1618161738314 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(20) " "Verilog HDL assignment warning at GR8RAM.v(20): truncated value with size 32 to match size of target (14)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 20 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616429528914 "|GR8RAM"} { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(20) " "Verilog HDL assignment warning at GR8RAM.v(20): truncated value with size 32 to match size of target (14)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 20 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618161738314 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(104) " "Verilog HDL assignment warning at GR8RAM.v(104): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 104 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616429528914 "|GR8RAM"} { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(103) " "Verilog HDL assignment warning at GR8RAM.v(103): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 103 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618161738314 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(112) " "Verilog HDL assignment warning at GR8RAM.v(112): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 112 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616429528914 "|GR8RAM"} { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(111) " "Verilog HDL assignment warning at GR8RAM.v(111): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 111 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618161738314 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(119) " "Verilog HDL assignment warning at GR8RAM.v(119): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 119 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616429528914 "|GR8RAM"} { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(118) " "Verilog HDL assignment warning at GR8RAM.v(118): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 118 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618161738314 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(306) " "Verilog HDL assignment warning at GR8RAM.v(306): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 306 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616429528930 "|GR8RAM"} { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(307) " "Verilog HDL assignment warning at GR8RAM.v(307): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 307 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618161738330 "|GR8RAM"}
{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 -1 1616429530336 ""} { "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 -1 1618161740127 ""}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1616429531165 ""} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1618161740877 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "304 " "Implemented 304 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "26 " "Implemented 26 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1616429531211 ""} { "Info" "ICUT_CUT_TM_OPINS" "26 " "Implemented 26 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1616429531211 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1616429531211 ""} { "Info" "ICUT_CUT_TM_LCELLS" "235 " "Implemented 235 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1616429531211 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1616429531211 ""} { "Info" "ICUT_CUT_TM_SUMMARY" "309 " "Implemented 309 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "26 " "Implemented 26 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1618161740986 ""} { "Info" "ICUT_CUT_TM_OPINS" "26 " "Implemented 26 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1618161740986 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1618161740986 ""} { "Info" "ICUT_CUT_TM_LCELLS" "240 " "Implemented 240 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1618161740986 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1618161740986 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1616429531352 ""} { "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1618161741470 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "301 " "Peak virtual memory: 301 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616429531524 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 22 12:12:11 2021 " "Processing ended: Mon Mar 22 12:12:11 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616429531524 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616429531524 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616429531524 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1616429531524 ""} { "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "301 " "Peak virtual memory: 301 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618161741799 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 11 13:22:21 2021 " "Processing ended: Sun Apr 11 13:22:21 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618161741799 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618161741799 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618161741799 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618161741799 ""}

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616429549056 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618161764909 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616429549071 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 22 12:12:27 2021 " "Processing started: Mon Mar 22 12:12:27 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616429549071 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1616429549071 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618161764925 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 11 13:22:43 2021 " "Processing started: Sun Apr 11 13:22:43 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618161764925 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618161764925 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1616429549087 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618161764925 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1616429549337 ""} { "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1618161765159 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1616429550197 ""} { "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1618161765987 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1616429550353 ""} { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618161766175 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1616429550353 ""} { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618161766175 ""}
{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1616429550525 ""} { "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1618161766331 ""}
{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1616429550962 ""} { "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1618161766815 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1616429551103 ""} { "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1618161767003 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1616429551103 ""} { "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1618161767003 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C25M C25M " "create_clock -period 1.000 -name C25M C25M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1616429551103 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1616429551103 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C25M C25M " "create_clock -period 1.000 -name C25M C25M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767018 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI0 PHI0 " "create_clock -period 1.000 -name PHI0 PHI0" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767018 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767018 ""}
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1616429551118 ""} { "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1618161767050 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1616429551243 ""} { "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1618161767331 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -9.843 " "Worst-case setup slack is -9.843" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616429551243 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616429551243 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.843 -651.483 C25M " " -9.843 -651.483 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616429551243 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1616429551243 ""} { "Info" "ISTA_WORST_CASE_SLACK" "setup -9.908 " "Worst-case setup slack is -9.908" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767393 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767393 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.908 -697.920 C25M " " -9.908 -697.920 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767393 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.302 -1.302 PHI0 " " -1.302 -1.302 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767393 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618161767393 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.395 " "Worst-case hold slack is 1.395" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616429551259 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616429551259 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.395 0.000 C25M " " 1.395 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616429551259 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1616429551259 ""} { "Info" "ISTA_WORST_CASE_SLACK" "hold 1.012 " "Worst-case hold slack is 1.012" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767409 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767409 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.012 0.000 PHI0 " " 1.012 0.000 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767409 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.288 0.000 C25M " " 1.288 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767409 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618161767409 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -4.404 " "Worst-case recovery slack is -4.404" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616429551275 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616429551275 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.404 -132.120 C25M " " -4.404 -132.120 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616429551275 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1616429551275 ""} { "Info" "ISTA_WORST_CASE_SLACK" "recovery -4.389 " "Worst-case recovery slack is -4.389" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767425 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767425 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.389 -131.670 C25M " " -4.389 -131.670 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767425 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618161767425 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 4.850 " "Worst-case removal slack is 4.850" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616429551275 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616429551275 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.850 0.000 C25M " " 4.850 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616429551275 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1616429551275 ""} { "Info" "ISTA_WORST_CASE_SLACK" "removal 4.835 " "Worst-case removal slack is 4.835" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767425 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767425 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.835 0.000 C25M " " 4.835 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767425 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618161767425 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.289 " "Worst-case minimum pulse width slack is -2.289" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616429551290 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616429551290 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 C25M " " -2.289 -2.289 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616429551290 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1616429551290 ""} { "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.289 " "Worst-case minimum pulse width slack is -2.289" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767456 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767456 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 C25M " " -2.289 -2.289 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767456 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI0 " " -2.289 -2.289 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618161767456 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618161767456 ""}
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1616429551415 ""} { "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1618161767706 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1616429551525 ""} { "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618161767815 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1616429551525 ""} { "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618161767815 ""}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "286 " "Peak virtual memory: 286 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616429551712 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 22 12:12:31 2021 " "Processing ended: Mon Mar 22 12:12:31 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616429551712 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616429551712 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616429551712 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1616429551712 ""} { "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "278 " "Peak virtual memory: 278 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618161768143 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 11 13:22:48 2021 " "Processing ended: Sun Apr 11 13:22:48 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618161768143 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618161768143 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618161768143 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618161768143 ""}

BIN
cpld/db/GR8RAM.sta.rdb
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cpld/db/GR8RAM.sta_cmp.5_slow.tdb
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8
cpld/db/GR8RAM.tmw_info
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@ -1,6 +1,6 @@
start_full_compilation:s:00:00:27 start_full_compilation:s:00:00:32
start_analysis_synthesis:s:00:00:07-start_full_compilation start_analysis_synthesis:s:00:00:07-start_full_compilation
start_analysis_elaboration:s-start_full_compilation start_analysis_elaboration:s-start_full_compilation
start_fitter:s:00:00:10-start_full_compilation start_fitter:s:00:00:12-start_full_compilation
start_assembler:s:00:00:04-start_full_compilation start_assembler:s:00:00:06-start_full_compilation
start_timing_analyzer:s:00:00:06-start_full_compilation start_timing_analyzer:s:00:00:07-start_full_compilation

BIN
cpld/db/GR8RAM.vpr.ammdb
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cpld/db/logic_util_heursitic.dat
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194
cpld/db/prev_cmp_GR8RAM.qmsg
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cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt
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16
cpld/output_files/GR8RAM.asm.rpt
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@ -1,5 +1,5 @@
Assembler report for GR8RAM Assembler report for GR8RAM
Mon Mar 22 12:12:25 2021 Sun Apr 11 13:22:41 2021
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
@ -37,7 +37,7 @@ applicable agreement for further details.
+---------------------------------------------------------------+ +---------------------------------------------------------------+
; Assembler Summary ; ; Assembler Summary ;
+-----------------------+---------------------------------------+ +-----------------------+---------------------------------------+
; Assembler Status ; Successful - Mon Mar 22 12:12:25 2021 ; ; Assembler Status ; Successful - Sun Apr 11 13:22:41 2021 ;
; Revision Name ; GR8RAM ; ; Revision Name ; GR8RAM ;
; Top-level Entity Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ;
; Family ; MAX II ; ; Family ; MAX II ;
@ -90,8 +90,8 @@ applicable agreement for further details.
; Option ; Setting ; ; Option ; Setting ;
+----------------+-------------------------------------------------------+ +----------------+-------------------------------------------------------+
; Device ; EPM240T100C5 ; ; Device ; EPM240T100C5 ;
; JTAG usercode ; 0x00166EAF ; ; JTAG usercode ; 0x00162982 ;
; Checksum ; 0x0016711F ; ; Checksum ; 0x00162E02 ;
+----------------+-------------------------------------------------------+ +----------------+-------------------------------------------------------+
@ -101,14 +101,14 @@ applicable agreement for further details.
Info: ******************************************************************* Info: *******************************************************************
Info: Running Quartus II 32-bit Assembler Info: Running Quartus II 32-bit Assembler
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Mon Mar 22 12:12:23 2021 Info: Processing started: Sun Apr 11 13:22:38 2021
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM
Info (115031): Writing out detailed assembly data for power analysis Info (115031): Writing out detailed assembly data for power analysis
Info (115030): Assembler is generating device programming files Info (115030): Assembler is generating device programming files
Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 293 megabytes Info: Peak virtual memory: 293 megabytes
Info: Processing ended: Mon Mar 22 12:12:25 2021 Info: Processing ended: Sun Apr 11 13:22:41 2021
Info: Elapsed time: 00:00:02 Info: Elapsed time: 00:00:03
Info: Total CPU time (on all processors): 00:00:02 Info: Total CPU time (on all processors): 00:00:03

2
cpld/output_files/GR8RAM.done
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@ -1 +1 @@
Mon Mar 22 12:12:32 2021 Sun Apr 11 13:22:49 2021

976
cpld/output_files/GR8RAM.fit.rpt
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4
cpld/output_files/GR8RAM.fit.summary
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@ -1,11 +1,11 @@
Fitter Status : Successful - Mon Mar 22 12:12:21 2021 Fitter Status : Successful - Sun Apr 11 13:22:34 2021
Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
Revision Name : GR8RAM Revision Name : GR8RAM
Top-level Entity Name : GR8RAM Top-level Entity Name : GR8RAM
Family : MAX II Family : MAX II
Device : EPM240T100C5 Device : EPM240T100C5
Timing Models : Final Timing Models : Final
Total logic elements : 223 / 240 ( 93 % ) Total logic elements : 227 / 240 ( 95 % )
Total pins : 69 / 80 ( 86 % ) Total pins : 69 / 80 ( 86 % )
Total virtual pins : 0 Total virtual pins : 0
UFM blocks : 0 / 1 ( 0 % ) UFM blocks : 0 / 1 ( 0 % )

22
cpld/output_files/GR8RAM.flow.rpt
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@ -1,5 +1,5 @@
Flow report for GR8RAM Flow report for GR8RAM
Mon Mar 22 12:12:31 2021 Sun Apr 11 13:22:47 2021
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
@ -40,14 +40,14 @@ applicable agreement for further details.
+-----------------------------------------------------------------------------+ +-----------------------------------------------------------------------------+
; Flow Summary ; ; Flow Summary ;
+---------------------------+-------------------------------------------------+ +---------------------------+-------------------------------------------------+
; Flow Status ; Successful - Mon Mar 22 12:12:25 2021 ; ; Flow Status ; Successful - Sun Apr 11 13:22:41 2021 ;
; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; ; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name ; GR8RAM ; ; Revision Name ; GR8RAM ;
; Top-level Entity Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ;
; Family ; MAX II ; ; Family ; MAX II ;
; Device ; EPM240T100C5 ; ; Device ; EPM240T100C5 ;
; Timing Models ; Final ; ; Timing Models ; Final ;
; Total logic elements ; 223 / 240 ( 93 % ) ; ; Total logic elements ; 227 / 240 ( 95 % ) ;
; Total pins ; 69 / 80 ( 86 % ) ; ; Total pins ; 69 / 80 ( 86 % ) ;
; Total virtual pins ; 0 ; ; Total virtual pins ; 0 ;
; UFM blocks ; 0 / 1 ( 0 % ) ; ; UFM blocks ; 0 / 1 ( 0 % ) ;
@ -59,7 +59,7 @@ applicable agreement for further details.
+-------------------+---------------------+ +-------------------+---------------------+
; Option ; Setting ; ; Option ; Setting ;
+-------------------+---------------------+ +-------------------+---------------------+
; Start date & time ; 03/22/2021 12:12:08 ; ; Start date & time ; 04/11/2021 13:22:17 ;
; Main task ; Compilation ; ; Main task ; Compilation ;
; Revision Name ; GR8RAM ; ; Revision Name ; GR8RAM ;
+-------------------+---------------------+ +-------------------+---------------------+
@ -75,9 +75,11 @@ applicable agreement for further details.
; ALM_REGISTER_PACKING_EFFORT ; High ; Medium ; -- ; -- ; ; ALM_REGISTER_PACKING_EFFORT ; High ; Medium ; -- ; -- ;
; AUTO_PACKED_REGISTERS_MAXII ; Minimize Area ; Auto ; -- ; -- ; ; AUTO_PACKED_REGISTERS_MAXII ; Minimize Area ; Auto ; -- ; -- ;
; AUTO_RESOURCE_SHARING ; On ; Off ; -- ; -- ; ; AUTO_RESOURCE_SHARING ; On ; Off ; -- ; -- ;
; COMPILER_SIGNATURE_ID ; 44085571633675.161642952802820 ; -- ; -- ; -- ; ; COMPILER_SIGNATURE_ID ; 44085571633675.161816173700648 ; -- ; -- ; -- ;
; FINAL_PLACEMENT_OPTIMIZATION ; Always ; Automatically ; -- ; -- ; ; FINAL_PLACEMENT_OPTIMIZATION ; Always ; Automatically ; -- ; -- ;
; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ; ; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ;
; IOBANK_VCCIO ; 3.3V ; -- ; -- ; 1 ;
; IOBANK_VCCIO ; 3.3V ; -- ; -- ; 2 ;
; MAXII_OPTIMIZATION_TECHNIQUE ; Area ; Balanced ; -- ; -- ; ; MAXII_OPTIMIZATION_TECHNIQUE ; Area ; Balanced ; -- ; -- ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; ; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; ; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
@ -100,11 +102,11 @@ applicable agreement for further details.
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:05 ; 1.0 ; 301 MB ; 00:00:05 ; ; Analysis & Synthesis ; 00:00:06 ; 1.0 ; 301 MB ; 00:00:06 ;
; Fitter ; 00:00:08 ; 1.5 ; 373 MB ; 00:00:08 ; ; Fitter ; 00:00:10 ; 1.4 ; 382 MB ; 00:00:09 ;
; Assembler ; 00:00:02 ; 1.0 ; 292 MB ; 00:00:02 ; ; Assembler ; 00:00:03 ; 1.0 ; 292 MB ; 00:00:03 ;
; TimeQuest Timing Analyzer ; 00:00:04 ; 1.0 ; 286 MB ; 00:00:04 ; ; TimeQuest Timing Analyzer ; 00:00:04 ; 1.0 ; 278 MB ; 00:00:04 ;
; Total ; 00:00:19 ; -- ; -- ; 00:00:19 ; ; Total ; 00:00:23 ; -- ; -- ; 00:00:22 ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +---------------------------+--------------+-------------------------+---------------------+------------------------------------+

2
cpld/output_files/GR8RAM.jdi
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@ -1,6 +1,6 @@
<sld_project_info> <sld_project_info>
<project> <project>
<hash md5_digest_80b="73ef203dd7199fdf781e"/> <hash md5_digest_80b="a474eff98051f7f4d66b"/>
</project> </project>
<file_info> <file_info>
<file device="EPM240T100C5" path="GR8RAM.sof" usercode="0xFFFFFFFF"/> <file device="EPM240T100C5" path="GR8RAM.sof" usercode="0xFFFFFFFF"/>

52
cpld/output_files/GR8RAM.map.rpt
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@ -1,5 +1,5 @@
Analysis & Synthesis report for GR8RAM Analysis & Synthesis report for GR8RAM
Mon Mar 22 12:12:11 2021 Sun Apr 11 13:22:21 2021
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
@ -45,12 +45,12 @@ applicable agreement for further details.
+-------------------------------------------------------------------------------+ +-------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ; ; Analysis & Synthesis Summary ;
+-----------------------------+-------------------------------------------------+ +-----------------------------+-------------------------------------------------+
; Analysis & Synthesis Status ; Successful - Mon Mar 22 12:12:11 2021 ; ; Analysis & Synthesis Status ; Successful - Sun Apr 11 13:22:21 2021 ;
; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; ; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name ; GR8RAM ; ; Revision Name ; GR8RAM ;
; Top-level Entity Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ;
; Family ; MAX II ; ; Family ; MAX II ;
; Total logic elements ; 235 ; ; Total logic elements ; 240 ;
; Total pins ; 69 ; ; Total pins ; 69 ;
; Total virtual pins ; 0 ; ; Total virtual pins ; 0 ;
; UFM blocks ; 0 / 1 ( 0 % ) ; ; UFM blocks ; 0 / 1 ( 0 % ) ;
@ -161,20 +161,20 @@ applicable agreement for further details.
+---------------------------------------------+-------+ +---------------------------------------------+-------+
; Resource ; Usage ; ; Resource ; Usage ;
+---------------------------------------------+-------+ +---------------------------------------------+-------+
; Total logic elements ; 235 ; ; Total logic elements ; 240 ;
; -- Combinational with no register ; 133 ; ; -- Combinational with no register ; 138 ;
; -- Register only ; 13 ; ; -- Register only ; 14 ;
; -- Combinational with a register ; 89 ; ; -- Combinational with a register ; 88 ;
; ; ; ; ; ;
; Logic element usage by number of LUT inputs ; ; ; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 122 ; ; -- 4 input functions ; 130 ;
; -- 3 input functions ; 36 ; ; -- 3 input functions ; 30 ;
; -- 2 input functions ; 64 ; ; -- 2 input functions ; 66 ;
; -- 1 input functions ; 0 ; ; -- 1 input functions ; 0 ;
; -- 0 input functions ; 0 ; ; -- 0 input functions ; 0 ;
; ; ; ; ; ;
; Logic elements by mode ; ; ; Logic elements by mode ; ;
; -- normal mode ; 202 ; ; -- normal mode ; 207 ;
; -- arithmetic mode ; 33 ; ; -- arithmetic mode ; 33 ;
; -- qfbk mode ; 0 ; ; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ; ; -- register cascade mode ; 0 ;
@ -185,9 +185,9 @@ applicable agreement for further details.
; Total logic cells in carry chains ; 37 ; ; Total logic cells in carry chains ; 37 ;
; I/O pins ; 69 ; ; I/O pins ; 69 ;
; Maximum fan-out node ; C25M ; ; Maximum fan-out node ; C25M ;
; Maximum fan-out ; 102 ; ; Maximum fan-out ; 99 ;
; Total fan-out ; 1020 ; ; Total fan-out ; 1036 ;
; Average fan-out ; 3.36 ; ; Average fan-out ; 3.35 ;
+---------------------------------------------+-------+ +---------------------------------------------+-------+
@ -196,7 +196,7 @@ applicable agreement for further details.
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+ +----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ; ; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+ +----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; |GR8RAM ; 235 (235) ; 102 ; 0 ; 69 ; 0 ; 133 (133) ; 13 (13) ; 89 (89) ; 37 (37) ; 0 (0) ; |GR8RAM ; work ; ; |GR8RAM ; 240 (240) ; 102 ; 0 ; 69 ; 0 ; 138 (138) ; 14 (14) ; 88 (88) ; 37 (37) ; 0 (0) ; |GR8RAM ; work ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+ +----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
@ -236,7 +236,7 @@ Encoding Type: Minimal Bits
; Number of registers using Synchronous Load ; 25 ; ; Number of registers using Synchronous Load ; 25 ;
; Number of registers using Asynchronous Clear ; 30 ; ; Number of registers using Asynchronous Clear ; 30 ;
; Number of registers using Asynchronous Load ; 0 ; ; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 32 ; ; Number of registers using Clock Enable ; 29 ;
; Number of registers using Preset ; 0 ; ; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+ +----------------------------------------------+-------+
@ -281,30 +281,30 @@ Encoding Type: Minimal Bits
Info: ******************************************************************* Info: *******************************************************************
Info: Running Quartus II 32-bit Analysis & Synthesis Info: Running Quartus II 32-bit Analysis & Synthesis
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Mon Mar 22 12:12:06 2021 Info: Processing started: Sun Apr 11 13:22:15 2021
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM
Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
Info (12021): Found 1 design units, including 1 entities, in source file gr8ram.v Info (12021): Found 1 design units, including 1 entities, in source file gr8ram.v
Info (12023): Found entity 1: GR8RAM Info (12023): Found entity 1: GR8RAM
Info (12127): Elaborating entity "GR8RAM" for the top level hierarchy Info (12127): Elaborating entity "GR8RAM" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(20): truncated value with size 32 to match size of target (14) Warning (10230): Verilog HDL assignment warning at GR8RAM.v(20): truncated value with size 32 to match size of target (14)
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(104): truncated value with size 32 to match size of target (8) Warning (10230): Verilog HDL assignment warning at GR8RAM.v(103): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(112): truncated value with size 32 to match size of target (8) Warning (10230): Verilog HDL assignment warning at GR8RAM.v(111): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(119): truncated value with size 32 to match size of target (8) Warning (10230): Verilog HDL assignment warning at GR8RAM.v(118): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(306): truncated value with size 32 to match size of target (4) Warning (10230): Verilog HDL assignment warning at GR8RAM.v(307): truncated value with size 32 to match size of target (4)
Info (17026): Resynthesizing 0 WYSIWYG logic cells and I/Os using "area" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched Info (17026): Resynthesizing 0 WYSIWYG logic cells and I/Os using "area" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched
Info (17049): 1 registers lost all their fanouts during netlist optimizations. Info (17049): 1 registers lost all their fanouts during netlist optimizations.
Info (21057): Implemented 304 device resources after synthesis - the final resource count might be different Info (21057): Implemented 309 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 26 input pins Info (21058): Implemented 26 input pins
Info (21059): Implemented 26 output pins Info (21059): Implemented 26 output pins
Info (21060): Implemented 17 bidirectional pins Info (21060): Implemented 17 bidirectional pins
Info (21061): Implemented 235 logic cells Info (21061): Implemented 240 logic cells
Info (144001): Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg Info (144001): Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg
Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 5 warnings Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 5 warnings
Info: Peak virtual memory: 301 megabytes Info: Peak virtual memory: 301 megabytes
Info: Processing ended: Mon Mar 22 12:12:11 2021 Info: Processing ended: Sun Apr 11 13:22:21 2021
Info: Elapsed time: 00:00:05 Info: Elapsed time: 00:00:06
Info: Total CPU time (on all processors): 00:00:05 Info: Total CPU time (on all processors): 00:00:06
+------------------------------------------+ +------------------------------------------+

4
cpld/output_files/GR8RAM.map.smsg
View File

@ -1,2 +1,2 @@
Warning (10273): Verilog HDL warning at GR8RAM.v(80): extended using "x" or "z" Warning (10273): Verilog HDL warning at GR8RAM.v(79): extended using "x" or "z"
Warning (10273): Verilog HDL warning at GR8RAM.v(255): extended using "x" or "z" Warning (10273): Verilog HDL warning at GR8RAM.v(256): extended using "x" or "z"

4
cpld/output_files/GR8RAM.map.summary
View File

@ -1,9 +1,9 @@
Analysis & Synthesis Status : Successful - Mon Mar 22 12:12:11 2021 Analysis & Synthesis Status : Successful - Sun Apr 11 13:22:21 2021
Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
Revision Name : GR8RAM Revision Name : GR8RAM
Top-level Entity Name : GR8RAM Top-level Entity Name : GR8RAM
Family : MAX II Family : MAX II
Total logic elements : 235 Total logic elements : 240
Total pins : 69 Total pins : 69
Total virtual pins : 0 Total virtual pins : 0
UFM blocks : 0 / 1 ( 0 % ) UFM blocks : 0 / 1 ( 0 % )

152
cpld/output_files/GR8RAM.pin
View File

@ -62,103 +62,103 @@ CHIP "GR8RAM" ASSIGNED TO AN: EPM240T100C5
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------
SBA[0] : 1 : output : 3.3-V LVTTL : : 2 : N RA[4] : 1 : input : 3.3-V LVTTL : : 2 : Y
nCAS : 2 : output : 3.3-V LVTTL : : 1 : N RA[5] : 2 : input : 3.3-V LVTTL : : 1 : Y
MOSI : 3 : bidir : 3.3-V LVTTL : : 1 : N RA[6] : 3 : input : 3.3-V LVTTL : : 1 : Y
nRAS : 4 : output : 3.3-V LVTTL : : 1 : N RA[3] : 4 : input : 3.3-V LVTTL : : 1 : Y
nRCS : 5 : output : 3.3-V LVTTL : : 1 : N nFCS : 5 : output : 3.3-V LVTTL : : 1 : Y
nRES : 6 : input : 3.3-V LVTTL : : 1 : N RA[7] : 6 : input : 3.3-V LVTTL : : 1 : Y
RCKE : 7 : output : 3.3-V LVTTL : : 1 : N RA[8] : 7 : input : 3.3-V LVTTL : : 1 : Y
SetLim8M : 8 : input : 3.3-V LVTTL : : 1 : N RA[9] : 8 : input : 3.3-V LVTTL : : 1 : Y
VCCIO1 : 9 : power : : 3.3V : 1 : VCCIO1 : 9 : power : : 3.3V : 1 :
GNDIO : 10 : gnd : : : : GNDIO : 10 : gnd : : : :
GNDINT : 11 : gnd : : : : GNDINT : 11 : gnd : : : :
nDEVSEL : 12 : input : 3.3-V LVTTL : : 1 : N FCK : 12 : output : 3.3-V LVTTL : : 1 : Y
VCCINT : 13 : power : : 2.5V/3.3V : : VCCINT : 13 : power : : 2.5V/3.3V : :
C25M : 14 : input : 3.3-V LVTTL : : 1 : N RA[10] : 14 : input : 3.3-V LVTTL : : 1 : Y
SD[2] : 15 : bidir : 3.3-V LVTTL : : 1 : N MOSI : 15 : bidir : 3.3-V LVTTL : : 1 : Y
RA[10] : 16 : input : 3.3-V LVTTL : : 1 : N MISO : 16 : input : 3.3-V LVTTL : : 1 : Y
SD[1] : 17 : bidir : 3.3-V LVTTL : : 1 : N RDdir : 17 : output : 3.3-V LVTTL : : 1 : N
RA[8] : 18 : input : 3.3-V LVTTL : : 1 : N GND* : 18 : : : : 1 :
RA[7] : 19 : input : 3.3-V LVTTL : : 1 : N GND* : 19 : : : : 1 :
RA[11] : 20 : input : 3.3-V LVTTL : : 1 : N GND* : 20 : : : : 1 :
RA[9] : 21 : input : 3.3-V LVTTL : : 1 : N GND* : 21 : : : : 1 :
TMS : 22 : input : : : 1 : TMS : 22 : input : : : 1 :
TDI : 23 : input : : : 1 : TDI : 23 : input : : : 1 :
TCK : 24 : input : : : 1 : TCK : 24 : input : : : 1 :
TDO : 25 : output : : : 1 : TDO : 25 : output : : : 1 :
GND* : 26 : : : : 1 : GND* : 26 : : : : 1 :
nFCS : 27 : output : 3.3-V LVTTL : : 1 : N GND* : 27 : : : : 1 :
GND* : 28 : : : : 1 : GND* : 28 : : : : 1 :
GND* : 29 : : : : 1 : GND* : 29 : : : : 1 :
SBA[1] : 30 : output : 3.3-V LVTTL : : 1 : N nRESout : 30 : output : 3.3-V LVTTL : : 1 : Y
VCCIO1 : 31 : power : : 3.3V : 1 : VCCIO1 : 31 : power : : 3.3V : 1 :
GNDIO : 32 : gnd : : : : GNDIO : 32 : gnd : : : :
SD[3] : 33 : bidir : 3.3-V LVTTL : : 1 : N GND* : 33 : : : : 1 :
SD[0] : 34 : bidir : 3.3-V LVTTL : : 1 : N RA[11] : 34 : input : 3.3-V LVTTL : : 1 : Y
SA[2] : 35 : output : 3.3-V LVTTL : : 1 : N RA[12] : 35 : input : 3.3-V LVTTL : : 1 : Y
FCK : 36 : output : 3.3-V LVTTL : : 1 : N RA[13] : 36 : input : 3.3-V LVTTL : : 1 : Y
SA[1] : 37 : output : 3.3-V LVTTL : : 1 : N RA[14] : 37 : input : 3.3-V LVTTL : : 1 : Y
SA[0] : 38 : output : 3.3-V LVTTL : : 1 : N RA[15] : 38 : input : 3.3-V LVTTL : : 1 : Y
SA[5] : 39 : output : 3.3-V LVTTL : : 1 : N nIOSEL : 39 : input : 3.3-V LVTTL : : 1 : Y
RA[6] : 40 : input : 3.3-V LVTTL : : 1 : N nDEVSEL : 40 : input : 3.3-V LVTTL : : 1 : Y
RA[4] : 41 : input : 3.3-V LVTTL : : 1 : N PHI0 : 41 : input : 3.3-V LVTTL : : 1 : Y
nIOSTRB : 42 : input : 3.3-V LVTTL : : 1 : N nIOSTRB : 42 : input : 3.3-V LVTTL : : 1 : Y
SA[3] : 43 : output : 3.3-V LVTTL : : 1 : N nWE : 43 : input : 3.3-V LVTTL : : 1 : Y
SA[6] : 44 : output : 3.3-V LVTTL : : 1 : N nRES : 44 : input : 3.3-V LVTTL : : 1 : Y
VCCIO1 : 45 : power : : 3.3V : 1 : VCCIO1 : 45 : power : : 3.3V : 1 :
GNDIO : 46 : gnd : : : : GNDIO : 46 : gnd : : : :
GND* : 47 : : : : 1 : SD[1] : 47 : bidir : 3.3-V LVTTL : : 1 : Y
SA[7] : 48 : output : 3.3-V LVTTL : : 1 : N GND* : 48 : : : : 1 :
GND* : 49 : : : : 1 : GND* : 49 : : : : 1 :
GND* : 50 : : : : 1 : SD[0] : 50 : bidir : 3.3-V LVTTL : : 1 : Y
GND* : 51 : : : : 1 : SD[4] : 51 : bidir : 3.3-V LVTTL : : 1 : Y
RD[0] : 52 : bidir : 3.3-V LVTTL : : 2 : N SD[5] : 52 : bidir : 3.3-V LVTTL : : 2 : Y
RA[3] : 53 : input : 3.3-V LVTTL : : 2 : N SD[6] : 53 : bidir : 3.3-V LVTTL : : 2 : Y
RD[3] : 54 : bidir : 3.3-V LVTTL : : 2 : N SD[7] : 54 : bidir : 3.3-V LVTTL : : 2 : Y
RDdir : 55 : output : 3.3-V LVTTL : : 2 : N SD[3] : 55 : bidir : 3.3-V LVTTL : : 2 : Y
RA[2] : 56 : input : 3.3-V LVTTL : : 2 : N SD[2] : 56 : bidir : 3.3-V LVTTL : : 2 : Y
RD[2] : 57 : bidir : 3.3-V LVTTL : : 2 : N DQMH : 57 : output : 3.3-V LVTTL : : 2 : Y
SA[8] : 58 : output : 3.3-V LVTTL : : 2 : N nSWE : 58 : output : 3.3-V LVTTL : : 2 : Y
VCCIO2 : 59 : power : : 3.3V : 2 : VCCIO2 : 59 : power : : 3.3V : 2 :
GNDIO : 60 : gnd : : : : GNDIO : 60 : gnd : : : :
RD[1] : 61 : bidir : 3.3-V LVTTL : : 2 : N nCAS : 61 : output : 3.3-V LVTTL : : 2 : Y
RA[5] : 62 : input : 3.3-V LVTTL : : 2 : N nRAS : 62 : output : 3.3-V LVTTL : : 2 : Y
VCCINT : 63 : power : : 2.5V/3.3V : : VCCINT : 63 : power : : 2.5V/3.3V : :
RA[1] : 64 : input : 3.3-V LVTTL : : 2 : N C25M : 64 : input : 3.3-V LVTTL : : 2 : Y
GNDINT : 65 : gnd : : : : GNDINT : 65 : gnd : : : :
nIOSEL : 66 : input : 3.3-V LVTTL : : 2 : N RCKE : 66 : output : 3.3-V LVTTL : : 2 : Y
RA[0] : 67 : input : 3.3-V LVTTL : : 2 : N nRCS : 67 : output : 3.3-V LVTTL : : 2 : Y
SetRF : 68 : input : 3.3-V LVTTL : : 2 : N SA[12] : 68 : output : 3.3-V LVTTL : : 2 : Y
GND* : 69 : : : : 2 : SBA[0] : 69 : output : 3.3-V LVTTL : : 2 : Y
SA[11] : 70 : output : 3.3-V LVTTL : : 2 : N SA[11] : 70 : output : 3.3-V LVTTL : : 2 : Y
SA[9] : 71 : output : 3.3-V LVTTL : : 2 : N SBA[1] : 71 : output : 3.3-V LVTTL : : 2 : Y
RA[13] : 72 : input : 3.3-V LVTTL : : 2 : N SA[9] : 72 : output : 3.3-V LVTTL : : 2 : Y
RA[12] : 73 : input : 3.3-V LVTTL : : 2 : N SA[10] : 73 : output : 3.3-V LVTTL : : 2 : Y
RA[15] : 74 : input : 3.3-V LVTTL : : 2 : N SA[8] : 74 : output : 3.3-V LVTTL : : 2 : Y
RA[14] : 75 : input : 3.3-V LVTTL : : 2 : N SA[0] : 75 : output : 3.3-V LVTTL : : 2 : Y
SA[12] : 76 : output : 3.3-V LVTTL : : 2 : N SA[4] : 76 : output : 3.3-V LVTTL : : 2 : Y
GND* : 77 : : : : 2 : SA[6] : 77 : output : 3.3-V LVTTL : : 2 : Y
GND* : 78 : : : : 2 : SA[7] : 78 : output : 3.3-V LVTTL : : 2 : Y
GNDIO : 79 : gnd : : : : GNDIO : 79 : gnd : : : :
VCCIO2 : 80 : power : : 3.3V : 2 : VCCIO2 : 80 : power : : 3.3V : 2 :
RD[5] : 81 : bidir : 3.3-V LVTTL : : 2 : N SA[1] : 81 : output : 3.3-V LVTTL : : 2 : Y
RD[6] : 82 : bidir : 3.3-V LVTTL : : 2 : N SA[2] : 82 : output : 3.3-V LVTTL : : 2 : Y
RD[7] : 83 : bidir : 3.3-V LVTTL : : 2 : N SA[5] : 83 : output : 3.3-V LVTTL : : 2 : Y
RD[4] : 84 : bidir : 3.3-V LVTTL : : 2 : N SA[3] : 84 : output : 3.3-V LVTTL : : 2 : Y
SA[10] : 85 : output : 3.3-V LVTTL : : 2 : N DQML : 85 : output : 3.3-V LVTTL : : 2 : Y
DQML : 86 : output : 3.3-V LVTTL : : 2 : N RD[0] : 86 : bidir : 3.3-V LVTTL : : 2 : Y
DQMH : 87 : output : 3.3-V LVTTL : : 2 : N RD[1] : 87 : bidir : 3.3-V LVTTL : : 2 : Y
PHI0 : 88 : input : 3.3-V LVTTL : : 2 : N RD[2] : 88 : bidir : 3.3-V LVTTL : : 2 : Y
nSWE : 89 : output : 3.3-V LVTTL : : 2 : N RD[3] : 89 : bidir : 3.3-V LVTTL : : 2 : Y
nWE : 90 : input : 3.3-V LVTTL : : 2 : N RD[4] : 90 : bidir : 3.3-V LVTTL : : 2 : Y
SA[4] : 91 : output : 3.3-V LVTTL : : 2 : N RD[5] : 91 : bidir : 3.3-V LVTTL : : 2 : Y
SD[5] : 92 : bidir : 3.3-V LVTTL : : 2 : N RD[6] : 92 : bidir : 3.3-V LVTTL : : 2 : Y
GNDIO : 93 : gnd : : : : GNDIO : 93 : gnd : : : :
VCCIO2 : 94 : power : : 3.3V : 2 : VCCIO2 : 94 : power : : 3.3V : 2 :
SD[6] : 95 : bidir : 3.3-V LVTTL : : 2 : N SetFW[1] : 95 : input : 3.3-V LVTTL : : 2 : Y
SD[4] : 96 : bidir : 3.3-V LVTTL : : 2 : N SetFW[0] : 96 : input : 3.3-V LVTTL : : 2 : Y
SD[7] : 97 : bidir : 3.3-V LVTTL : : 2 : N RA[2] : 97 : input : 3.3-V LVTTL : : 2 : Y
MISO : 98 : input : 3.3-V LVTTL : : 2 : N RA[1] : 98 : input : 3.3-V LVTTL : : 2 : Y
nRESout : 99 : output : 3.3-V LVTTL : : 2 : N RD[7] : 99 : bidir : 3.3-V LVTTL : : 2 : Y
GND* : 100 : : : : 2 : RA[0] : 100 : input : 3.3-V LVTTL : : 2 : Y

BIN
cpld/output_files/GR8RAM.pof
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Binary file not shown.

1482
cpld/output_files/GR8RAM.sta.rpt
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File diff suppressed because it is too large Load Diff

24
cpld/output_files/GR8RAM.sta.summary
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@ -3,23 +3,35 @@ TimeQuest Timing Analyzer Summary
------------------------------------------------------------ ------------------------------------------------------------
Type : Setup 'C25M' Type : Setup 'C25M'
Slack : -9.843 Slack : -9.908
TNS : -651.483 TNS : -697.920
Type : Setup 'PHI0'
Slack : -1.302
TNS : -1.302
Type : Hold 'PHI0'
Slack : 1.012
TNS : 0.000
Type : Hold 'C25M' Type : Hold 'C25M'
Slack : 1.395 Slack : 1.288
TNS : 0.000 TNS : 0.000
Type : Recovery 'C25M' Type : Recovery 'C25M'
Slack : -4.404 Slack : -4.389
TNS : -132.120 TNS : -131.670
Type : Removal 'C25M' Type : Removal 'C25M'
Slack : 4.850 Slack : 4.835
TNS : 0.000 TNS : 0.000
Type : Minimum Pulse Width 'C25M' Type : Minimum Pulse Width 'C25M'
Slack : -2.289 Slack : -2.289
TNS : -2.289 TNS : -2.289
Type : Minimum Pulse Width 'PHI0'
Slack : -2.289
TNS : -2.289
------------------------------------------------------------ ------------------------------------------------------------

33
gerber/GR8RAM-BOM.csv
View File

@ -1,38 +1,21 @@
Reference, Quantity, Value, Footprint, Datasheet, LCSC Part Reference, Quantity, Value, Footprint, Datasheet, LCSC Part
C38 C40 C41 ,3,"22n","stdpads:C_0603","~","C21122" C10 C1 C7 C2 C3 C4 C11 ,7,"10u","stdpads:C_0805","~","C15850"
C39 ,1,"1n","stdpads:C_0603","~","C1588" C31 C30 C44 C43 C42 C35 C34 C33 C32 C26 C28 C27 C25 C24 C18 C23 C22 C21 C20 C19 C16 C15 C14 C13 C12 C29 C5 ,27,"2u2","stdpads:C_0603","~","C23630"
C8 C10 C11 C1 C7 C36 C37 C5 C6 C2 C3 C4 ,12,"10u","stdpads:C_0805","~","C15850"
C9 C31 C30 C44 C43 C42 C35 C34 C33 C32 C26 C28 C27 C25 C24 C18 C23 C22 C21 C20 C19 C16 C15 C14 C13 C12 C29 ,27,"2u2","stdpads:C_0603","~","C23630"
D2 ,1,"SMBJ5.0A","stdpads:D_SMB","~","C110528"
D3 D1 ,2,"SS34","stdpads:D_SMA","~","C8678"
F1 ,1,"nSMD050-16V","stdpads:BelFuse_1206","~","C70075"
FB1 ,1,"GZ2012D101TF","stdpads:Murata_BLM21","~","C1015"
FID5 FID4 FID3 FID2 FID1 ,5,"Fiducial","stdpads:Fiducial","~" FID5 FID4 FID3 FID2 FID1 ,5,"Fiducial","stdpads:Fiducial","~"
H1 ,1," ","stdpads:PasteHole_1.1mm_PTH","~" H1 ,1," ","stdpads:PasteHole_1.1mm_PTH","~"
H6 H2 H3 H4 H5 ,5," ","stdpads:PasteHole_1.152mm_NPTH","~" H6 H2 H3 H4 H5 ,5," ","stdpads:PasteHole_1.152mm_NPTH","~"
J1 ,1,"AppleIIBus","stdpads:AppleIIBus_Edge","~" J1 ,1,"AppleIIBus","stdpads:AppleIIBus_Edge","~"
J2 J5 ,2,"JTAG","Connector:Tag-Connect_TC2050-IDC-FP_2x05_P1.27mm_Vertical","~" J2 J5 ,2,"JTAG","Connector:Tag-Connect_TC2050-IDC-FP_2x05_P1.27mm_Vertical","~"
J3 ,1,"DC in","stdpads:BOOMELE_DC-005_DC_5.5-2.0MM","~"
J4 ,1,"JTAG","Connector_IDC:IDC-Header_2x05_P2.54mm_Vertical","~" J4 ,1,"JTAG","Connector_IDC:IDC-Header_2x05_P2.54mm_Vertical","~"
Q1 ,1,"AO3401A","stdpads:SOT-23","http://www.aosmd.com/pdfs/datasheet/AO3401A.pdf","C15127" R22 R31 ,2,"33","stdpads:R_0603","~","C23140"
R10 R16 R2 R15 R4 ,5,"2k2","stdpads:R_0603","~","C4190" R28 R29 ,2,"22k","stdpads:R_0603","~","C31850"
R11 ,1,"330","stdpads:R_0603","~","C23138"
R12 ,1,"1k","stdpads:R_0805","~","C17513"
R13 ,1,"DNP","stdpads:R_0805","~"
R18 R28 R29 ,3,"22k","stdpads:R_0603","~","C31850"
R20 R21 R23 R24 R25 R26 R1 R22 R27 R31 ,10,"33","stdpads:R_0603","~","C23140"
R3 ,1,"2k7","stdpads:R_0603","~","C13167"
R6 R14 R19 R17 ,4,"1k","stdpads:R_0603","~","C21190"
R7 ,1,"820","stdpads:R_0603","~","C23253"
R8 R5 R30 ,3,"1M","stdpads:R_0603","~","C22935"
R9 ,1,"1k2","stdpads:R_0603","~","C22765"
RN2 RN3 RN1 ,3,"4x33","stdpads:R4_0402","~","C25501" RN2 RN3 RN1 ,3,"4x33","stdpads:R4_0402","~","C25501"
RN4 RN5 ,2,"4x10k","stdpads:R4_0402","~","C25725" RN5 ,1,"4x10k","stdpads:R4_0402","~","C25725"
SW1 ,1,"FW","stdpads:SW_DIP_SPSTx02_Slide_DSHP02TS_P1.27mm","~","C319052"
U1 ,1,"EPM240T100C5N","stdpads:TQFP-100_14x14mm_P0.5mm","https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/max2/max2_mii5v1.pdf","C10041" U1 ,1,"EPM240T100C5N","stdpads:TQFP-100_14x14mm_P0.5mm","https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/max2/max2_mii5v1.pdf","C10041"
U13 ,1,"25M","stdpads:Crystal_SMD_3225-4Pin_3.2x2.5mm","","C669088" U13 ,1,"25M","stdpads:Crystal_SMD_3225-4Pin_3.2x2.5mm","","C669088"
U16 U11 U12 U15 U17 U18 U19 U20 U14 U22 ,10,"74LVC1G125GW","stdpads:SOT-353","","C12519" U16 U14 ,2,"74LVC1G125GW","stdpads:SOT-353","","C12519"
U2 ,1,"W9825","stdpads:TSOP-II-54_22.2x10.16mm_P0.8mm","","C62246" U2 ,1,"W9825","stdpads:TSOP-II-54_22.2x10.16mm_P0.8mm","","C62246"
U3 ,1,"W25Q128JVSIQ","stdpads:SOIC-8_5.3mm","","C97521" U3 ,1,"W25Q128JVSIQ","stdpads:SOIC-8_5.3mm","","C164122"
U5 U6 U9 U4 ,4,"74AHC245PW","stdpads:TSSOP-20_4.4x6.5mm_P0.65mm","","C5516" U5 U6 U9 U4 ,4,"74AHC245PW","stdpads:TSSOP-20_4.4x6.5mm_P0.65mm","","C5516"
U7 U10 ,2,"LM393D","stdpads:SOIC-8_3.9mm","http://www.ti.com/lit/ds/symlink/lm393-n.pdf","C7955"
U8 ,1,"XC6206P332MR","stdpads:SOT-23","","C5446" U8 ,1,"XC6206P332MR","stdpads:SOT-23","","C5446"
Can't render this file because it has a wrong number of fields in line 10.

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570
gerber/GR8RAM-B_Mask.gbs
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@ -1,12 +1,12 @@
G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.1.5-0-10_14)* G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.1.5-0-10_14)*
G04 #@! TF.CreationDate,2021-02-17T19:07:14-05:00* G04 #@! TF.CreationDate,2021-04-11T00:58:13-04:00*
G04 #@! TF.ProjectId,GR8RAM,47523852-414d-42e6-9b69-6361645f7063,0.9* G04 #@! TF.ProjectId,GR8RAM,47523852-414d-42e6-9b69-6361645f7063,0.9*
G04 #@! TF.SameCoordinates,Original* G04 #@! TF.SameCoordinates,Original*
G04 #@! TF.FileFunction,Soldermask,Bot* G04 #@! TF.FileFunction,Soldermask,Bot*
G04 #@! TF.FilePolarity,Negative* G04 #@! TF.FilePolarity,Negative*
%FSLAX46Y46*% %FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW (5.1.5-0-10_14)) date 2021-02-17 19:07:14* G04 Created by KiCad (PCBNEW (5.1.5-0-10_14)) date 2021-04-11 00:58:13*
%MOMM*% %MOMM*%
%LPD*% %LPD*%
G04 APERTURE LIST* G04 APERTURE LIST*
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G37* G37*
G36* G36*
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G01*
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X66497542Y-119424119D01*
G37*
G36*
X61417542Y-119424119D02* X61417542Y-119424119D02*
G01* G01*
X61478067Y-119436158D01* X61478067Y-119436158D01*
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G37* G37*
G36* G36*
X63957542Y-119424119D02*
G01*
X64018067Y-119436158D01*
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X63658419Y-120304420D01*
X63581456Y-120252995D01*
X63516005Y-120187544D01*
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X63411100Y-119934280D01*
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X63957542Y-119424119D01*
G37*
G36*
X65227542Y-119424119D02* X65227542Y-119424119D02*
G01* G01*
X65288067Y-119436158D01* X65288067Y-119436158D01*
@ -1536,56 +1536,56 @@ X65197281Y-119418100D01*
X65227542Y-119424119D01* X65227542Y-119424119D01*
G37* G37*
G36* G36*
X66497542Y-119424119D02* X63957542Y-119424119D02*
G01* G01*
X66558067Y-119436158D01* X64018067Y-119436158D01*
X66643578Y-119471578D01* X64103578Y-119471578D01*
X66643581Y-119471580D01* X64103581Y-119471580D01*
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X66198419Y-120304420D01* X63658419Y-120304420D01*
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X66056005Y-120187544D01* X63516005Y-120187544D01*
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X65951100Y-119934280D01* X63411100Y-119934280D01*
X65951100Y-119841720D01* X63411100Y-119841720D01*
X65954409Y-119825086D01* X63414409Y-119825086D01*
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X65969158Y-119750933D01* X63429158Y-119750933D01*
X66004578Y-119665422D01* X63464578Y-119665422D01*
X66004580Y-119665419D01* X63464580Y-119665419D01*
X66056005Y-119588456D01* X63516005Y-119588456D01*
X66121456Y-119523005D01* X63581456Y-119523005D01*
X66198419Y-119471580D01* X63658419Y-119471580D01*
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G37* G37*
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@ -1636,56 +1636,56 @@ X60127288Y-118681500D01*
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G37* G37*
G36* G36*
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G01* G01*
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G37* G37*
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G37* G37*
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G01*
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33
gerber/GR8RAM-B_SilkS.gbo
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@ -1,12 +1,12 @@
G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.1.5-0-10_14)* G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.1.5-0-10_14)*
G04 #@! TF.CreationDate,2021-02-17T19:07:14-05:00* G04 #@! TF.CreationDate,2021-04-11T00:58:12-04:00*
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%LPD*% %LPD*%
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@ -14,14 +14,11 @@ G04 APERTURE LIST*
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4
gerber/GR8RAM-Edge_Cuts.gm1
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G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.1.5-0-10_14)* G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.1.5-0-10_14)*
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gerber/GR8RAM-F_Cu.gtl
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18436
gerber/GR8RAM-F_Mask.gts
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15998
gerber/GR8RAM-F_Paste.gtp
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18110
gerber/GR8RAM-F_SilkS.gto
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13476
gerber/GR8RAM-In1_Cu.g2
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29326
gerber/GR8RAM-In2_Cu.g3
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2
gerber/GR8RAM-bottom-pos.csv
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@ -1 +1 @@
Ref,Val,Package,MidX,MidY,Rot,Side Ref,Val,Package,PosX,PosY,Rot,Side

1 Ref Val Package MidX PosX MidY PosY Rot Side

2
gerber/GR8RAM-bottom.pos
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@ -1,4 +1,4 @@
### Module positions - created on Wednesday, February 17, 2021 at 07:07:19 PM ### ### Module positions - created on Sunday, April 11, 2021 at 12:58:18 AM ###
### Printed by Pcbnew version kicad (5.1.5-0-10_14) ### Printed by Pcbnew version kicad (5.1.5-0-10_14)
## Unit = mm, Angle = deg. ## Unit = mm, Angle = deg.
## Side : bottom ## Side : bottom

5046
gerber/GR8RAM-drl_map.ps
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gerber/GR8RAM-top-pos.csv
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@ -1,16 +1,13 @@
Ref,Val,Package,MidX,MidY,Rot,Side Ref,Val,Package,PosX,PosY,Rot,Side
"C1","10u","C_0805",136.310000,-128.270000,180.000000,top "C1","10u","C_0805",136.310000,-128.270000,180.000000,top
"C2","10u","C_0805",119.976000,-128.270000,180.000000,top "C2","10u","C_0805",119.976000,-128.270000,180.000000,top
"C3","10u","C_0805",116.244000,-128.270000,0.000000,top "C3","10u","C_0805",116.244000,-128.270000,0.000000,top
"C4","10u","C_0805",75.350000,-128.270000,180.000000,top "C4","10u","C_0805",75.350000,-128.270000,180.000000,top
"C5","10u","C_0805",100.000000,-88.350000,270.000000,top "C5","2u2","C_0603",113.650000,-90.750000,180.000000,top
"C6","10u","C_0805",142.250000,-93.600000,90.000000,top "C7","10u","C_0805",140.100000,-124.200000,90.000000,top
"C7","10u","C_0805",142.600000,-103.550000,0.000000,top "C10","10u","C_0805",132.750000,-124.200000,90.000000,top
"C8","10u","C_0805",142.600000,-105.550000,0.000000,top "C11","10u","C_0805",130.350000,-124.200000,90.000000,top
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"FB1","GZ2012D101TF","Murata_BLM21",139.550000,-94.450000,0.000000,top
"FID1","Fiducial","Fiducial",143.002000,-82.423000,270.000000,top "FID1","Fiducial","Fiducial",143.002000,-82.423000,270.000000,top
"FID2","Fiducial","Fiducial",48.133000,-93.599000,90.000000,top "FID2","Fiducial","Fiducial",48.133000,-93.599000,90.000000,top
"FID3","Fiducial","Fiducial",58.801000,-82.931000,90.000000,top "FID3","Fiducial","Fiducial",58.801000,-82.931000,90.000000,top
"FID4","Fiducial","Fiducial",143.002000,-129.540000,0.000000,top "FID4","Fiducial","Fiducial",143.002000,-129.540000,0.000000,top
"FID5","Fiducial","Fiducial",48.133000,-129.540000,0.000000,top "FID5","Fiducial","Fiducial",48.133000,-129.540000,0.000000,top
"Q1","AO3401A","SOT-23",142.800000,-109.950000,270.000000,top "R22","33","R_0603",115.800000,-124.200000,180.000000,top
"R1","33","R_0603",114.000000,-124.200000,180.000000,top
"R2","2k2","R_0603",128.950000,-113.700000,270.000000,top
"R3","2k7","R_0603",133.900000,-122.150000,180.000000,top
"R4","2k2","R_0603",133.900000,-109.600000,180.000000,top
"R5","1M","R_0603",131.100000,-120.650000,0.000000,top
"R6","1k","R_0603",133.900000,-111.050000,0.000000,top
"R7","820","R_0603",133.900000,-120.650000,0.000000,top
"R8","1M","R_0603",131.000000,-109.600000,180.000000,top
"R9","1k2","R_0603",128.850000,-110.250000,90.000000,top
"R10","2k2","R_0603",131.000000,-111.050000,0.000000,top
"R11","330","R_0603",128.850000,-107.450000,90.000000,top
"R12","1k","R_0805",136.150000,-94.650000,180.000000,top
"R13","DNP","R_0805",139.550000,-92.450000,0.000000,top
"R14","1k","R_0603",136.750000,-122.150000,180.000000,top
"R15","2k2","R_0603",138.200000,-108.850000,90.000000,top
"R16","2k2","R_0603",136.750000,-120.650000,0.000000,top
"R17","1k","R_0603",138.150000,-123.750000,180.000000,top
"R18","22k","R_0603",139.550000,-122.150000,180.000000,top
"R19","1k","R_0603",71.950000,-90.800000,90.000000,top
"R20","33","R_0603",125.200000,-124.200000,180.000000,top
"R21","33","R_0603",128.000000,-124.200000,180.000000,top
"R22","33","R_0603",116.800000,-124.200000,180.000000,top
"R23","33","R_0603",126.700000,-129.750000,180.000000,top
"R24","33","R_0603",122.400000,-124.200000,180.000000,top
"R25","33","R_0603",132.400000,-129.750000,180.000000,top
"R26","33","R_0603",129.550000,-129.750000,180.000000,top
"R27","33","R_0603",119.600000,-124.200000,180.000000,top
"R28","22k","R_0603",70.550000,-110.650000,0.000000,top "R28","22k","R_0603",70.550000,-110.650000,0.000000,top
"R29","22k","R_0603",70.550000,-112.100000,180.000000,top "R29","22k","R_0603",70.550000,-112.100000,180.000000,top
"R30","1M","R_0603",139.300000,-111.050000,0.000000,top
"R31","33","R_0603",80.950000,-108.500000,90.000000,top "R31","33","R_0603",80.950000,-108.500000,90.000000,top
"RN1","4x33","R4_0402",108.200000,-95.150000,0.000000,top "RN1","4x33","R4_0402",108.200000,-95.150000,0.000000,top
"RN2","4x33","R4_0402",108.450000,-106.250000,270.000000,top "RN2","4x33","R4_0402",108.450000,-106.250000,270.000000,top
"RN3","4x33","R4_0402",108.450000,-110.650000,270.000000,top "RN3","4x33","R4_0402",108.450000,-110.650000,270.000000,top
"RN4","4x10k","R4_0402",113.500000,-117.200000,0.000000,top "RN5","4x10k","R4_0402",69.100000,-96.450000,90.000000,top
"RN5","4x10k","R4_0402",69.250000,-96.450000,90.000000,top "SW1","FW","SW_DIP_SPSTx02_Slide_DSHP02TS_P1.27mm",135.763000,-95.885000,0.000000,top
"U1","EPM240T100C5N","TQFP-100_14x14mm_P0.5mm",94.050000,-101.400000,270.000000,top "U1","EPM240T100C5N","TQFP-100_14x14mm_P0.5mm",94.050000,-101.400000,270.000000,top
"U2","W9825","TSOP-II-54_22.2x10.16mm_P0.8mm",118.650000,-103.050000,180.000000,top "U2","W9825","TSOP-II-54_22.2x10.16mm_P0.8mm",118.650000,-103.050000,180.000000,top
"U3","W25Q128JVSIQ","SOIC-8_5.3mm",79.121000,-100.711000,180.000000,top "U3","W25Q128JVSIQ","SOIC-8_5.3mm",79.121000,-100.711000,180.000000,top
"U4","74AHC245PW","TSSOP-20_4.4x6.5mm_P0.65mm",90.225000,-122.000000,0.000000,top "U4","74AHC245PW","TSSOP-20_4.4x6.5mm_P0.65mm",90.225000,-122.000000,0.000000,top
"U5","74AHC245PW","TSSOP-20_4.4x6.5mm_P0.65mm",108.625000,-122.000000,0.000000,top "U5","74AHC245PW","TSSOP-20_4.4x6.5mm_P0.65mm",108.625000,-122.000000,0.000000,top
"U6","74AHC245PW","TSSOP-20_4.4x6.5mm_P0.65mm",81.025000,-122.000000,0.000000,top "U6","74AHC245PW","TSSOP-20_4.4x6.5mm_P0.65mm",81.025000,-122.000000,0.000000,top
"U7","LM393D","SOIC-8_3.9mm",132.457000,-115.824000,0.000000,top "U8","XC6206P332MR","SOT-23",136.250000,-124.200000,180.000000,top
"U8","XC6206P332MR","SOT-23",138.350000,-105.550000,180.000000,top
"U9","74AHC245PW","TSSOP-20_4.4x6.5mm_P0.65mm",99.425000,-122.000000,0.000000,top "U9","74AHC245PW","TSSOP-20_4.4x6.5mm_P0.65mm",99.425000,-122.000000,0.000000,top
"U10","LM393D","SOIC-8_3.9mm",138.172000,-115.824000,0.000000,top
"U11","74LVC1G125GW","SOT-353",125.050000,-121.850000,90.000000,top
"U12","74LVC1G125GW","SOT-353",127.850000,-121.850000,90.000000,top
"U13","25M","Crystal_SMD_3225-4Pin_3.2x2.5mm",107.100000,-102.500000,0.000000,top "U13","25M","Crystal_SMD_3225-4Pin_3.2x2.5mm",107.100000,-102.500000,0.000000,top
"U14","74LVC1G125GW","SOT-353",116.650000,-121.850000,90.000000,top "U14","74LVC1G125GW","SOT-353",115.650000,-121.850000,90.000000,top
"U15","74LVC1G125GW","SOT-353",126.550000,-127.450000,90.000000,top
"U16","74LVC1G125GW","SOT-353",108.200000,-98.850000,270.000000,top "U16","74LVC1G125GW","SOT-353",108.200000,-98.850000,270.000000,top
"U17","74LVC1G125GW","SOT-353",122.250000,-121.850000,90.000000,top
"U18","74LVC1G125GW","SOT-353",132.250000,-127.450000,90.000000,top
"U19","74LVC1G125GW","SOT-353",129.400000,-127.450000,90.000000,top
"U20","74LVC1G125GW","SOT-353",113.850000,-121.850000,90.000000,top
"U22","74LVC1G125GW","SOT-353",119.450000,-121.850000,90.000000,top

1 Ref Val Package MidX PosX MidY PosY Rot Side
2 C1 10u C_0805 136.310000 136.310000 -128.270000 -128.270000 180.000000 top
3 C2 10u C_0805 119.976000 119.976000 -128.270000 -128.270000 180.000000 top
4 C3 10u C_0805 116.244000 116.244000 -128.270000 -128.270000 0.000000 top
5 C4 10u C_0805 75.350000 75.350000 -128.270000 -128.270000 180.000000 top
6 C5 10u 2u2 C_0805 C_0603 100.000000 113.650000 -88.350000 -90.750000 270.000000 180.000000 top
7 C6 C7 10u C_0805 142.250000 140.100000 -93.600000 -124.200000 90.000000 top
8 C7 C10 10u C_0805 142.600000 132.750000 -103.550000 -124.200000 0.000000 90.000000 top
9 C8 C11 10u C_0805 142.600000 130.350000 -105.550000 -124.200000 0.000000 90.000000 top
10 C9 C12 2u2 C_0603 118.700000 123.650000 -117.450000 -90.750000 270.000000 180.000000 top
C10 10u C_0805 134.850000 -105.550000 90.000000 top
C11 10u C_0805 132.350000 -105.550000 90.000000 top
C12 2u2 C_0603 136.450000 -108.900000 90.000000 top
11 C13 2u2 C_0603 76.600000 76.600000 -119.800000 -119.800000 270.000000 top
12 C14 2u2 C_0603 85.800000 85.800000 -119.800000 -119.800000 270.000000 top
13 C15 2u2 C_0603 95.000000 95.000000 -119.800000 -119.800000 270.000000 top
30 C33 2u2 C_0603 110.800000 110.800000 -104.050000 -104.050000 90.000000 top
31 C34 2u2 C_0603 110.850000 110.850000 -108.700000 -108.700000 90.000000 top
32 C35 2u2 C_0603 113.650000 113.650000 -115.350000 -115.350000 180.000000 top
33 C36 C42 10u 2u2 C_0805 C_0603 132.350000 117.800000 -97.100000 -122.100000 180.000000 90.000000 top
34 C37 C43 10u 2u2 C_0805 C_0603 132.350000 104.800000 -99.600000 -112.250000 180.000000 0.000000 top
35 C38 C44 22n 2u2 C_0603 131.100000 69.000000 -122.150000 -100.650000 180.000000 270.000000 top
C39 1n C_0603 133.900000 -108.150000 0.000000 top
C40 22n C_0603 131.000000 -108.150000 0.000000 top
C41 22n C_0603 139.550000 -120.650000 0.000000 top
C42 2u2 C_0603 116.000000 -118.550000 270.000000 top
C43 2u2 C_0603 121.600000 -118.550000 270.000000 top
C44 2u2 C_0603 127.200000 -118.550000 270.000000 top
D1 SS14 D_SMA 142.000000 -99.050000 90.000000 top
D2 SMBJ5.0A D_SMB 137.400000 -99.050000 270.000000 top
D3 SS14 D_SMA 142.900000 -118.700000 270.000000 top
F1 nSMD050-16V BelFuse_1206 135.450000 -92.450000 0.000000 top
FB1 GZ2012D101TF Murata_BLM21 139.550000 -94.450000 0.000000 top
36 FID1 Fiducial Fiducial 143.002000 143.002000 -82.423000 -82.423000 270.000000 top
37 FID2 Fiducial Fiducial 48.133000 48.133000 -93.599000 -93.599000 90.000000 top
38 FID3 Fiducial Fiducial 58.801000 58.801000 -82.931000 -82.931000 90.000000 top
39 FID4 Fiducial Fiducial 143.002000 143.002000 -129.540000 -129.540000 0.000000 top
40 FID5 Fiducial Fiducial 48.133000 48.133000 -129.540000 -129.540000 0.000000 top
41 Q1 R22 AO3401A 33 SOT-23 R_0603 142.800000 115.800000 -109.950000 -124.200000 270.000000 180.000000 top
R1 33 R_0603 114.000000 -124.200000 180.000000 top
R2 2k2 R_0603 128.950000 -113.700000 270.000000 top
R3 2k7 R_0603 133.900000 -122.150000 180.000000 top
R4 2k2 R_0603 133.900000 -109.600000 180.000000 top
R5 1M R_0603 131.100000 -120.650000 0.000000 top
R6 1k R_0603 133.900000 -111.050000 0.000000 top
R7 820 R_0603 133.900000 -120.650000 0.000000 top
R8 1M R_0603 131.000000 -109.600000 180.000000 top
R9 1k2 R_0603 128.850000 -110.250000 90.000000 top
R10 2k2 R_0603 131.000000 -111.050000 0.000000 top
R11 330 R_0603 128.850000 -107.450000 90.000000 top
R12 1k R_0805 136.150000 -94.650000 180.000000 top
R13 DNP R_0805 139.550000 -92.450000 0.000000 top
R14 1k R_0603 136.750000 -122.150000 180.000000 top
R15 2k2 R_0603 138.200000 -108.850000 90.000000 top
R16 2k2 R_0603 136.750000 -120.650000 0.000000 top
R17 1k R_0603 138.150000 -123.750000 180.000000 top
R18 22k R_0603 139.550000 -122.150000 180.000000 top
R19 1k R_0603 71.950000 -90.800000 90.000000 top
R20 33 R_0603 125.200000 -124.200000 180.000000 top
R21 33 R_0603 128.000000 -124.200000 180.000000 top
R22 33 R_0603 116.800000 -124.200000 180.000000 top
R23 33 R_0603 126.700000 -129.750000 180.000000 top
R24 33 R_0603 122.400000 -124.200000 180.000000 top
R25 33 R_0603 132.400000 -129.750000 180.000000 top
R26 33 R_0603 129.550000 -129.750000 180.000000 top
R27 33 R_0603 119.600000 -124.200000 180.000000 top
42 R28 22k R_0603 70.550000 70.550000 -110.650000 -110.650000 0.000000 top
43 R29 22k R_0603 70.550000 70.550000 -112.100000 -112.100000 180.000000 top
R30 1M R_0603 139.300000 -111.050000 0.000000 top
44 R31 33 R_0603 80.950000 80.950000 -108.500000 -108.500000 90.000000 top
45 RN1 4x33 R4_0402 108.200000 108.200000 -95.150000 -95.150000 0.000000 top
46 RN2 4x33 R4_0402 108.450000 108.450000 -106.250000 -106.250000 270.000000 top
47 RN3 4x33 R4_0402 108.450000 108.450000 -110.650000 -110.650000 270.000000 top
48 RN4 RN5 4x10k R4_0402 113.500000 69.100000 -117.200000 -96.450000 0.000000 90.000000 top
49 RN5 SW1 4x10k FW R4_0402 SW_DIP_SPSTx02_Slide_DSHP02TS_P1.27mm 69.250000 135.763000 -96.450000 -95.885000 90.000000 0.000000 top
50 U1 EPM240T100C5N TQFP-100_14x14mm_P0.5mm 94.050000 94.050000 -101.400000 -101.400000 270.000000 top
51 U2 W9825 TSOP-II-54_22.2x10.16mm_P0.8mm 118.650000 118.650000 -103.050000 -103.050000 180.000000 top
52 U3 W25Q128JVSIQ SOIC-8_5.3mm 79.121000 79.121000 -100.711000 -100.711000 180.000000 top
53 U4 74AHC245PW TSSOP-20_4.4x6.5mm_P0.65mm 90.225000 90.225000 -122.000000 -122.000000 0.000000 top
54 U5 74AHC245PW TSSOP-20_4.4x6.5mm_P0.65mm 108.625000 108.625000 -122.000000 -122.000000 0.000000 top
55 U6 74AHC245PW TSSOP-20_4.4x6.5mm_P0.65mm 81.025000 81.025000 -122.000000 -122.000000 0.000000 top
56 U7 U8 LM393D XC6206P332MR SOIC-8_3.9mm SOT-23 132.457000 136.250000 -115.824000 -124.200000 0.000000 180.000000 top
U8 XC6206P332MR SOT-23 138.350000 -105.550000 180.000000 top
57 U9 74AHC245PW TSSOP-20_4.4x6.5mm_P0.65mm 99.425000 99.425000 -122.000000 -122.000000 0.000000 top
U10 LM393D SOIC-8_3.9mm 138.172000 -115.824000 0.000000 top
U11 74LVC1G125GW SOT-353 125.050000 -121.850000 90.000000 top
U12 74LVC1G125GW SOT-353 127.850000 -121.850000 90.000000 top
58 U13 25M Crystal_SMD_3225-4Pin_3.2x2.5mm 107.100000 107.100000 -102.500000 -102.500000 0.000000 top
59 U14 74LVC1G125GW SOT-353 116.650000 115.650000 -121.850000 -121.850000 90.000000 top
U15 74LVC1G125GW SOT-353 126.550000 -127.450000 90.000000 top
60 U16 74LVC1G125GW SOT-353 108.200000 108.200000 -98.850000 -98.850000 270.000000 top
U17 74LVC1G125GW SOT-353 122.250000 -121.850000 90.000000 top
U18 74LVC1G125GW SOT-353 132.250000 -127.450000 90.000000 top
U19 74LVC1G125GW SOT-353 129.400000 -127.450000 90.000000 top
U20 74LVC1G125GW SOT-353 113.850000 -121.850000 90.000000 top
U22 74LVC1G125GW SOT-353 119.450000 -121.850000 90.000000 top

174
gerber/GR8RAM-top.pos
View File

@ -1,117 +1,65 @@
### Module positions - created on Wednesday, February 17, 2021 at 07:07:19 PM ### ### Module positions - created on Sunday, April 11, 2021 at 12:58:18 AM ###
### Printed by Pcbnew version kicad (5.1.5-0-10_14) ### Printed by Pcbnew version kicad (5.1.5-0-10_14)
## Unit = mm, Angle = deg. ## Unit = mm, Angle = deg.
## Side : top ## Side : top
# Ref Val Package PosX PosY Rot Side # Ref Val Package PosX PosY Rot Side
C1 10u C_0805 136.3100 -128.2700 180.0000 top C1 10u C_0805 136.3100 -128.2700 180.0000 top
C2 10u C_0805 119.9760 -128.2700 180.0000 top C2 10u C_0805 119.9760 -128.2700 180.0000 top
C3 10u C_0805 116.2440 -128.2700 0.0000 top C3 10u C_0805 116.2440 -128.2700 0.0000 top
C4 10u C_0805 75.3500 -128.2700 180.0000 top C4 10u C_0805 75.3500 -128.2700 180.0000 top
C5 10u C_0805 100.0000 -88.3500 270.0000 top C5 2u2 C_0603 113.6500 -90.7500 180.0000 top
C6 10u C_0805 142.2500 -93.6000 90.0000 top C7 10u C_0805 140.1000 -124.2000 90.0000 top
C7 10u C_0805 142.6000 -103.5500 0.0000 top C10 10u C_0805 132.7500 -124.2000 90.0000 top
C8 10u C_0805 142.6000 -105.5500 0.0000 top C11 10u C_0805 130.3500 -124.2000 90.0000 top
C9 2u2 C_0603 118.7000 -117.4500 270.0000 top C12 2u2 C_0603 123.6500 -90.7500 180.0000 top
C10 10u C_0805 134.8500 -105.5500 90.0000 top C13 2u2 C_0603 76.6000 -119.8000 270.0000 top
C11 10u C_0805 132.3500 -105.5500 90.0000 top C14 2u2 C_0603 85.8000 -119.8000 270.0000 top
C12 2u2 C_0603 136.4500 -108.9000 90.0000 top C15 2u2 C_0603 95.0000 -119.8000 270.0000 top
C13 2u2 C_0603 76.6000 -119.8000 270.0000 top C16 2u2 C_0603 104.2000 -119.8000 270.0000 top
C14 2u2 C_0603 85.8000 -119.8000 270.0000 top C18 2u2 C_0603 82.8000 -103.5510 90.0000 top
C15 2u2 C_0603 95.0000 -119.8000 270.0000 top C19 2u2 C_0603 84.3500 -98.0000 90.0000 top
C16 2u2 C_0603 104.2000 -119.8000 270.0000 top C20 2u2 C_0603 84.3500 -100.9000 90.0000 top
C18 2u2 C_0603 82.8000 -103.5510 90.0000 top C21 2u2 C_0603 90.8000 -111.1000 0.0000 top
C19 2u2 C_0603 84.3500 -98.0000 90.0000 top C22 2u2 C_0603 97.8000 -111.1000 0.0000 top
C20 2u2 C_0603 84.3500 -100.9000 90.0000 top C23 2u2 C_0603 103.7500 -104.3000 270.0000 top
C21 2u2 C_0603 90.8000 -111.1000 0.0000 top C24 2u2 C_0603 103.7500 -100.9000 90.0000 top
C22 2u2 C_0603 97.8000 -111.1000 0.0000 top C25 2u2 C_0603 97.1500 -91.7000 180.0000 top
C23 2u2 C_0603 103.7500 -104.3000 270.0000 top C26 2u2 C_0603 90.1500 -91.7000 180.0000 top
C24 2u2 C_0603 103.7500 -100.9000 90.0000 top C27 2u2 C_0603 105.9500 -98.7500 270.0000 top
C25 2u2 C_0603 97.1500 -91.7000 180.0000 top C28 2u2 C_0603 123.6500 -115.3500 180.0000 top
C26 2u2 C_0603 90.1500 -91.7000 180.0000 top C29 2u2 C_0603 126.4500 -112.6000 270.0000 top
C27 2u2 C_0603 105.9500 -98.7500 270.0000 top C30 2u2 C_0603 126.4500 -107.8000 270.0000 top
C28 2u2 C_0603 123.6500 -115.3500 180.0000 top C31 2u2 C_0603 126.4500 -103.8000 270.0000 top
C29 2u2 C_0603 126.4500 -112.6000 270.0000 top C32 2u2 C_0603 126.4500 -93.4000 270.0000 top
C30 2u2 C_0603 126.4500 -107.8000 270.0000 top C33 2u2 C_0603 110.8000 -104.0500 90.0000 top
C31 2u2 C_0603 126.4500 -103.8000 270.0000 top C34 2u2 C_0603 110.8500 -108.7000 90.0000 top
C32 2u2 C_0603 126.4500 -93.4000 270.0000 top C35 2u2 C_0603 113.6500 -115.3500 180.0000 top
C33 2u2 C_0603 110.8000 -104.0500 90.0000 top C42 2u2 C_0603 117.8000 -122.1000 90.0000 top
C34 2u2 C_0603 110.8500 -108.7000 90.0000 top C43 2u2 C_0603 104.8000 -112.2500 0.0000 top
C35 2u2 C_0603 113.6500 -115.3500 180.0000 top C44 2u2 C_0603 69.0000 -100.6500 270.0000 top
C36 10u C_0805 132.3500 -97.1000 180.0000 top FID1 Fiducial Fiducial 143.0020 -82.4230 270.0000 top
C37 10u C_0805 132.3500 -99.6000 180.0000 top FID2 Fiducial Fiducial 48.1330 -93.5990 90.0000 top
C38 22n C_0603 131.1000 -122.1500 180.0000 top FID3 Fiducial Fiducial 58.8010 -82.9310 90.0000 top
C39 1n C_0603 133.9000 -108.1500 0.0000 top FID4 Fiducial Fiducial 143.0020 -129.5400 0.0000 top
C40 22n C_0603 131.0000 -108.1500 0.0000 top FID5 Fiducial Fiducial 48.1330 -129.5400 0.0000 top
C41 22n C_0603 139.5500 -120.6500 0.0000 top R22 33 R_0603 115.8000 -124.2000 180.0000 top
C42 2u2 C_0603 116.0000 -118.5500 270.0000 top R28 22k R_0603 70.5500 -110.6500 0.0000 top
C43 2u2 C_0603 121.6000 -118.5500 270.0000 top R29 22k R_0603 70.5500 -112.1000 180.0000 top
C44 2u2 C_0603 127.2000 -118.5500 270.0000 top R31 33 R_0603 80.9500 -108.5000 90.0000 top
D1 SS14 D_SMA 142.0000 -99.0500 90.0000 top RN1 4x33 R4_0402 108.2000 -95.1500 0.0000 top
D2 SMBJ5.0A D_SMB 137.4000 -99.0500 270.0000 top RN2 4x33 R4_0402 108.4500 -106.2500 270.0000 top
D3 SS14 D_SMA 142.9000 -118.7000 270.0000 top RN3 4x33 R4_0402 108.4500 -110.6500 270.0000 top
F1 nSMD050-16V BelFuse_1206 135.4500 -92.4500 0.0000 top RN5 4x10k R4_0402 69.1000 -96.4500 90.0000 top
FB1 GZ2012D101TF Murata_BLM21 139.5500 -94.4500 0.0000 top SW1 FW SW_DIP_SPSTx02_Slide_DSHP02TS_P1.27mm 135.7630 -95.8850 0.0000 top
FID1 Fiducial Fiducial 143.0020 -82.4230 270.0000 top U1 EPM240T100C5N TQFP-100_14x14mm_P0.5mm 94.0500 -101.4000 270.0000 top
FID2 Fiducial Fiducial 48.1330 -93.5990 90.0000 top U2 W9825 TSOP-II-54_22.2x10.16mm_P0.8mm 118.6500 -103.0500 180.0000 top
FID3 Fiducial Fiducial 58.8010 -82.9310 90.0000 top U3 W25Q128JVSIQ SOIC-8_5.3mm 79.1210 -100.7110 180.0000 top
FID4 Fiducial Fiducial 143.0020 -129.5400 0.0000 top U4 74AHC245PW TSSOP-20_4.4x6.5mm_P0.65mm 90.2250 -122.0000 0.0000 top
FID5 Fiducial Fiducial 48.1330 -129.5400 0.0000 top U5 74AHC245PW TSSOP-20_4.4x6.5mm_P0.65mm 108.6250 -122.0000 0.0000 top
Q1 AO3401A SOT-23 142.8000 -109.9500 270.0000 top U6 74AHC245PW TSSOP-20_4.4x6.5mm_P0.65mm 81.0250 -122.0000 0.0000 top
R1 33 R_0603 114.0000 -124.2000 180.0000 top U8 XC6206P332MR SOT-23 136.2500 -124.2000 180.0000 top
R2 2k2 R_0603 128.9500 -113.7000 270.0000 top U9 74AHC245PW TSSOP-20_4.4x6.5mm_P0.65mm 99.4250 -122.0000 0.0000 top
R3 2k7 R_0603 133.9000 -122.1500 180.0000 top U13 25M Crystal_SMD_3225-4Pin_3.2x2.5mm 107.1000 -102.5000 0.0000 top
R4 2k2 R_0603 133.9000 -109.6000 180.0000 top U14 74LVC1G125GW SOT-353 115.6500 -121.8500 90.0000 top
R5 1M R_0603 131.1000 -120.6500 0.0000 top U16 74LVC1G125GW SOT-353 108.2000 -98.8500 270.0000 top
R6 1k R_0603 133.9000 -111.0500 0.0000 top
R7 820 R_0603 133.9000 -120.6500 0.0000 top
R8 1M R_0603 131.0000 -109.6000 180.0000 top
R9 1k2 R_0603 128.8500 -110.2500 90.0000 top
R10 2k2 R_0603 131.0000 -111.0500 0.0000 top
R11 330 R_0603 128.8500 -107.4500 90.0000 top
R12 1k R_0805 136.1500 -94.6500 180.0000 top
R13 DNP R_0805 139.5500 -92.4500 0.0000 top
R14 1k R_0603 136.7500 -122.1500 180.0000 top
R15 2k2 R_0603 138.2000 -108.8500 90.0000 top
R16 2k2 R_0603 136.7500 -120.6500 0.0000 top
R17 1k R_0603 138.1500 -123.7500 180.0000 top
R18 22k R_0603 139.5500 -122.1500 180.0000 top
R19 1k R_0603 71.9500 -90.8000 90.0000 top
R20 33 R_0603 125.2000 -124.2000 180.0000 top
R21 33 R_0603 128.0000 -124.2000 180.0000 top
R22 33 R_0603 116.8000 -124.2000 180.0000 top
R23 33 R_0603 126.7000 -129.7500 180.0000 top
R24 33 R_0603 122.4000 -124.2000 180.0000 top
R25 33 R_0603 132.4000 -129.7500 180.0000 top
R26 33 R_0603 129.5500 -129.7500 180.0000 top
R27 33 R_0603 119.6000 -124.2000 180.0000 top
R28 22k R_0603 70.5500 -110.6500 0.0000 top
R29 22k R_0603 70.5500 -112.1000 180.0000 top
R30 1M R_0603 139.3000 -111.0500 0.0000 top
R31 33 R_0603 80.9500 -108.5000 90.0000 top
RN1 4x33 R4_0402 108.2000 -95.1500 0.0000 top
RN2 4x33 R4_0402 108.4500 -106.2500 270.0000 top
RN3 4x33 R4_0402 108.4500 -110.6500 270.0000 top
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RN5 4x10k R4_0402 69.2500 -96.4500 90.0000 top
U1 EPM240T100C5N TQFP-100_14x14mm_P0.5mm 94.0500 -101.4000 270.0000 top
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U3 W25Q128JVSIQ SOIC-8_5.3mm 79.1210 -100.7110 180.0000 top
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U5 74AHC245PW TSSOP-20_4.4x6.5mm_P0.65mm 108.6250 -122.0000 0.0000 top
U6 74AHC245PW TSSOP-20_4.4x6.5mm_P0.65mm 81.0250 -122.0000 0.0000 top
U7 LM393D SOIC-8_3.9mm 132.4570 -115.8240 0.0000 top
U8 XC6206P332MR SOT-23 138.3500 -105.5500 180.0000 top
U9 74AHC245PW TSSOP-20_4.4x6.5mm_P0.65mm 99.4250 -122.0000 0.0000 top
U10 LM393D SOIC-8_3.9mm 138.1720 -115.8240 0.0000 top
U11 74LVC1G125GW SOT-353 125.0500 -121.8500 90.0000 top
U12 74LVC1G125GW SOT-353 127.8500 -121.8500 90.0000 top
U13 25M Crystal_SMD_3225-4Pin_3.2x2.5mm 107.1000 -102.5000 0.0000 top
U14 74LVC1G125GW SOT-353 116.6500 -121.8500 90.0000 top
U15 74LVC1G125GW SOT-353 126.5500 -127.4500 90.0000 top
U16 74LVC1G125GW SOT-353 108.2000 -98.8500 270.0000 top
U17 74LVC1G125GW SOT-353 122.2500 -121.8500 90.0000 top
U18 74LVC1G125GW SOT-353 132.2500 -127.4500 90.0000 top
U19 74LVC1G125GW SOT-353 129.4000 -127.4500 90.0000 top
U20 74LVC1G125GW SOT-353 113.8500 -121.8500 90.0000 top
U22 74LVC1G125GW SOT-353 119.4500 -121.8500 90.0000 top
## End ## End

503
gerber/GR8RAM.drl
View File

@ -1,7 +1,7 @@
M48 M48
; DRILL file {KiCad (5.1.5-0-10_14)} date Wednesday, February 17, 2021 at 07:07:15 PM ; DRILL file {KiCad (5.1.5-0-10_14)} date Sunday, April 11, 2021 at 12:58:14 AM
; FORMAT={-:-/ absolute / inch / decimal} ; FORMAT={-:-/ absolute / inch / decimal}
; #@! TF.CreationDate,2021-02-17T19:07:15-05:00 ; #@! TF.CreationDate,2021-04-11T00:58:14-04:00
; #@! TF.GenerationSoftware,Kicad,Pcbnew,(5.1.5-0-10_14) ; #@! TF.GenerationSoftware,Kicad,Pcbnew,(5.1.5-0-10_14)
FMAT,2 FMAT,2
INCH INCH
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T3C0.0150 T3C0.0150
T4C0.0157 T4C0.0157
T5C0.0300 T5C0.0300
T6C0.0315 T6C0.0400
T7C0.0400 T7C0.0433
T8C0.0433 T8C0.0390
T9C0.0390 T9C0.0454
T10C0.0454 T10C0.0935
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G90 G90
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X4.9783Y-4.1496
X4.9783Y-4.1811
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X5.0039Y-3.878
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X5.0079Y-4.9508
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X5.0295Y-5.0512
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X5.0413Y-4.6437
X5.0413Y-4.6909
X5.045Y-3.175 X5.045Y-3.175
X5.045Y-3.375 X5.045Y-3.375
X5.0453Y-4.9409 X5.045Y-3.575
X5.0453Y-4.9843 X5.045Y-3.775
X5.045Y-3.975
X5.045Y-4.575
X5.045Y-4.775
X5.045Y-4.975
X5.05Y-5.17 X5.05Y-5.17
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X5.0728Y-4.3996
X5.0768Y-3.628
X5.0768Y-4.5354
X5.0807Y-4.8287
X5.1004Y-4.8091
X5.1043Y-4.9469
X5.1201Y-3.6634
X5.1201Y-4.8583
X5.1417Y-5.0512
X5.145Y-3.275 X5.145Y-3.275
X5.145Y-3.475 X5.145Y-3.475
X5.145Y-3.675
X5.145Y-3.875
X5.145Y-4.475
X5.145Y-4.675
X5.145Y-5.075
X5.15Y-5.17 X5.15Y-5.17
X5.1575Y-4.9823 X5.2Y-5.165
X5.1594Y-4.8701
X5.1614Y-4.2224
X5.1654Y-3.7106
X5.1811Y-4.9488
X5.189Y-4.4075
X5.2343Y-4.9508
X5.245Y-3.175 X5.245Y-3.175
X5.245Y-3.375 X5.245Y-3.375
X5.245Y-3.575 X5.245Y-3.575
X5.245Y-3.775
X5.245Y-3.975
X5.245Y-4.575
X5.25Y-5.17 X5.25Y-5.17
X5.2539Y-5.0512 X5.3Y-5.165
X5.275Y-4.41 X5.3Y-5.165
X5.2776Y-4.9626 X5.32Y-3.58
X5.2835Y-5.0039 X5.32Y-3.97
X5.3031Y-4.8425
X5.325Y-4.565
X5.345Y-3.275 X5.345Y-3.275
X5.345Y-3.475 X5.345Y-3.475
X5.345Y-3.675
X5.345Y-3.875
X5.345Y-4.475
X5.345Y-4.675
X5.35Y-5.17 X5.35Y-5.17
X5.3524Y-4.8425 X5.37Y-3.58
X5.372Y-4.2264 X5.37Y-3.97
X5.372Y-4.3484
X5.4055Y-4.2579
X5.4055Y-4.3169
X5.439Y-4.9665
X5.445Y-3.175 X5.445Y-3.175
X5.445Y-3.375 X5.445Y-3.375
X5.445Y-3.575 X5.445Y-3.575
X5.445Y-3.775
X5.445Y-3.975
X5.445Y-4.575
X5.445Y-4.775
X5.45Y-5.17 X5.45Y-5.17
X5.4744Y-4.2539
X5.545Y-3.475 X5.545Y-3.475
X5.5551Y-4.8504 X5.545Y-3.675
X5.5846Y-4.4114 X5.545Y-3.875
X5.545Y-4.475
X5.545Y-4.675
X5.63Y-3.175 X5.63Y-3.175
X5.63Y-5.17 X5.63Y-5.17
X5.645Y-3.375 X5.645Y-3.375
X5.647Y-3.7337 X5.645Y-3.575
X5.647Y-3.9376 X5.645Y-3.775
X5.6476Y-4.0335 X5.645Y-3.975
X5.685Y-4.0768 X5.645Y-4.175
X5.685Y-4.1555 X5.645Y-4.575
X5.645Y-4.775
X5.7Y-3.245 X5.7Y-3.245
X5.7Y-3.475 X5.7Y-3.475
X5.7Y-3.675 X5.7Y-3.675
X5.7Y-3.875 X5.7Y-3.875
X5.7Y-4.075
X5.7Y-4.275 X5.7Y-4.275
X5.7Y-4.475 X5.7Y-4.475
X5.7Y-4.475
X5.7Y-4.675 X5.7Y-4.675
X5.7Y-4.875 X5.7Y-4.875
X5.7Y-5.1 X5.7Y-5.1
T2 T2
X2.9803Y-4.6929
X2.9803Y-4.7402
X3.0157Y-4.6535
X3.0157Y-4.7795
X3.3425Y-4.7402
X3.378Y-4.7795
X3.4862Y-3.6102
X3.5118Y-4.374
X3.5256Y-3.5748
X3.5512Y-4.4094
X3.5728Y-3.5748
X3.5984Y-4.4094
X3.6378Y-4.374 X3.6378Y-4.374
X3.7047Y-4.7402
X3.7402Y-4.7795
X3.7618Y-3.6102
X3.7874Y-4.374
X3.8012Y-3.5748
X3.8268Y-4.4094
X3.8484Y-3.5748
X3.874Y-4.4094
X3.8878Y-3.6102
X3.9134Y-4.374
X4.0669Y-4.7402
X4.1024Y-4.7795
X4.1201Y-4.1358
X4.3622Y-4.0335 X4.3622Y-4.0335
X4.4114Y-3.5728
X4.4114Y-4.5413
X4.4449Y-3.6201 X4.4449Y-3.6201
X5.1398Y-4.4075 X4.4508Y-3.5374
X5.14Y-4.5225 X4.4508Y-4.5768
X5.2874Y-4.7146 X4.498Y-3.5374
X5.2894Y-4.5945 X4.498Y-3.6083
X5.3346Y-4.2579 X4.498Y-4.5059
X5.3346Y-4.315 X4.498Y-4.5768
X5.3346Y-4.372 X4.5374Y-3.5728
X5.365Y-4.5425 X4.5374Y-4.5413
X5.3652Y-4.4065 X4.8051Y-3.5728
X5.5157Y-4.5945 X4.8051Y-4.5413
X5.5157Y-4.7126 X4.8445Y-3.5374
X5.5463Y-4.6545 X4.8445Y-3.6083
X4.8445Y-4.5059
X4.8445Y-4.5768
X4.8917Y-3.5374
X4.8917Y-4.5768
X4.9311Y-3.5728
X4.9311Y-4.5413
X4.9783Y-3.6142
X4.9783Y-4.1496
X4.9783Y-4.1811
X4.9783Y-4.3701
X5.0138Y-4.4094
X5.0138Y-4.4567
T3 T3
X4.9783Y-4.311 X4.9783Y-4.311
X5.0177Y-4.0669 X5.0177Y-4.0669
@ -668,34 +673,14 @@ X5.0177Y-4.1063
T4 T4
X2.89Y-5.06 X2.89Y-5.06
X2.935Y-5.1 X2.935Y-5.1
X2.9764Y-4.7461
X3.0Y-5.1 X3.0Y-5.1
X3.0157Y-4.6496
X3.045Y-5.05 X3.045Y-5.05
X3.378Y-4.6496 X3.378Y-4.6496
X3.4823Y-3.6102
X3.5197Y-3.5709
X3.5453Y-4.4134
X3.5787Y-3.5709
X3.6043Y-4.4134
X3.7008Y-4.7461
X3.7402Y-4.6496 X3.7402Y-4.6496
X3.7402Y-4.7835
X3.7953Y-3.5709
X3.8209Y-4.4134
X3.8543Y-3.5709
X3.8799Y-4.4134
X3.8878Y-3.5118
X3.8917Y-3.6102
X3.9193Y-4.374
X3.937Y-3.5531
X4.063Y-4.7461
X4.0846Y-4.0394 X4.0846Y-4.0394
X4.1024Y-4.6496 X4.1024Y-4.6496
X4.1024Y-4.7835
X4.124Y-4.002 X4.124Y-4.002
X4.124Y-4.0768 X4.124Y-4.0768
X4.124Y-4.1417
X4.3091Y-4.0689 X4.3091Y-4.0689
X4.3642Y-4.1575 X4.3642Y-4.1575
X4.3642Y-4.2126 X4.3642Y-4.2126
@ -705,6 +690,7 @@ X4.545Y-5.1
X4.61Y-5.1 X4.61Y-5.1
X4.69Y-5.1 X4.69Y-5.1
X4.755Y-5.1 X4.755Y-5.1
X4.7975Y-5.05
X4.9783Y-3.7441 X4.9783Y-3.7441
X4.9783Y-4.0197 X4.9783Y-4.0197
X4.9783Y-4.5 X4.9783Y-4.5
@ -712,40 +698,29 @@ X5.0177Y-3.6575
X5.0177Y-3.6969 X5.0177Y-3.6969
X5.0177Y-4.2244 X5.0177Y-4.2244
X5.0177Y-4.2638 X5.0177Y-4.2638
X5.1358Y-3.8228 X5.0846Y-4.8563
X5.1358Y-3.9213 X5.0846Y-4.9154
X5.1614Y-4.1319 X5.1319Y-4.815
X5.1614Y-4.1791 X5.1319Y-4.9646
X5.187Y-3.7736 X5.1791Y-4.8642
X5.187Y-3.872 X5.1791Y-4.9154
X5.187Y-3.9705 X5.2264Y-4.815
X5.2106Y-4.0807 X5.2264Y-4.9646
X5.2343Y-3.7736 X5.2756Y-4.8622
X5.2343Y-3.872 X5.2756Y-4.9173
X5.2343Y-3.9705
X5.2598Y-4.1319
X5.2598Y-4.1791
X5.2854Y-3.7264
X5.2854Y-3.8228
X5.2854Y-3.9213
X5.29Y-5.05 X5.29Y-5.05
X5.3091Y-4.0807 X5.3228Y-4.815
X5.3228Y-4.9626
X5.335Y-5.0 X5.335Y-5.0
X5.335Y-5.1 X5.335Y-5.1
X5.3583Y-4.1181
X5.3583Y-4.1929
X5.4Y-5.0 X5.4Y-5.0
X5.445Y-5.05 X5.445Y-5.05
X5.6004Y-3.6102 X5.4685Y-4.8602
X5.6476Y-4.2047 X5.5157Y-4.815
X5.6496Y-3.6516 X5.563Y-4.8642
T5 T5
X5.3248Y-3.9783
X5.4Y-5.11 X5.4Y-5.11
X5.4094Y-4.0551 T6
X5.4941Y-3.9783
X5.6594Y-3.8209
T7
X2.425Y-3.86 X2.425Y-3.86
X2.425Y-3.96 X2.425Y-3.96
X2.425Y-4.06 X2.425Y-4.06
@ -756,22 +731,22 @@ X2.525Y-3.96
X2.525Y-4.06 X2.525Y-4.06
X2.525Y-4.16 X2.525Y-4.16
X2.525Y-4.26 X2.525Y-4.26
T8 T7
X5.53Y-5.1 X5.53Y-5.1
T8
X2.365Y-4.695
X2.665Y-4.655
X2.665Y-4.735
X2.365Y-4.695
X2.665Y-4.655
X2.665Y-4.735
T9 T9
X2.365Y-4.695
X2.665Y-4.655
X2.665Y-4.735
X2.365Y-4.695
X2.665Y-4.655
X2.665Y-4.735
T10
X1.895Y-3.785
X2.245Y-3.335
X5.63Y-5.0
X1.895Y-5.0 X1.895Y-5.0
X2.245Y-3.335
X5.53Y-3.245 X5.53Y-3.245
T11 X5.63Y-5.0
X1.895Y-3.785
T10
X2.365Y-4.595 X2.365Y-4.595
X2.365Y-4.795 X2.365Y-4.795
X2.59Y-4.595 X2.59Y-4.595
@ -780,21 +755,5 @@ X2.365Y-4.595
X2.365Y-4.795 X2.365Y-4.795
X2.59Y-4.595 X2.59Y-4.595
X2.59Y-4.795 X2.59Y-4.795
T6
G00X4.0472Y-3.4567
M15
G01X4.0472Y-3.3543
M16
G05
G00X4.1969Y-3.2165
M15
G01X4.0945Y-3.2165
M16
G05
G00X4.2835Y-3.4567
M15
G01X4.2835Y-3.3543
M16
G05
T0 T0
M30 M30