From e2d63fc8edd14a4843164c64cf09c8dcdd6ca513 Mon Sep 17 00:00:00 2001 From: Zane Kaminski Date: Wed, 21 Apr 2021 09:19:57 -0400 Subject: [PATCH] Output read data on falling edge to get more hold time --- Docs.sch | 134 ++++++++++++++++++++++++++++---------------------- cpld/GR8RAM.v | 14 ++++-- 2 files changed, 84 insertions(+), 64 deletions(-) diff --git a/Docs.sch b/Docs.sch index 60a6626..7725443 100644 --- a/Docs.sch +++ b/Docs.sch @@ -19,22 +19,14 @@ Text Notes 1450 650 2 50 ~ 0 C25M Text Notes 1450 800 2 50 ~ 0 PHI0 -Wire Wire Line - 1600 650 1600 550 -Wire Wire Line - 1700 550 1600 550 -Wire Wire Line - 1700 650 1700 550 -Wire Wire Line - 1800 650 1700 650 Wire Wire Line 1800 650 1800 550 Wire Wire Line - 1800 550 1900 550 + 1900 550 1800 550 Wire Wire Line - 1900 550 1900 650 + 1900 650 1900 550 Wire Wire Line - 1900 650 2000 650 + 2000 650 1900 650 Wire Wire Line 2000 650 2000 550 Wire Wire Line @@ -51,14 +43,14 @@ Wire Wire Line 2300 550 2300 650 Wire Wire Line 2300 650 2400 650 +Wire Wire Line + 2400 650 2400 550 Wire Wire Line 2400 550 2500 550 Wire Wire Line 2500 550 2500 650 Wire Wire Line 2500 650 2600 650 -Wire Wire Line - 2600 650 2600 550 Wire Wire Line 2600 550 2700 550 Wire Wire Line @@ -156,17 +148,7 @@ Wire Wire Line Wire Wire Line 5000 650 5000 550 Wire Wire Line - 4050 800 5650 800 -Wire Wire Line - 4000 700 4050 800 -Wire Wire Line - 1550 800 1600 800 -Wire Wire Line - 1650 700 4000 700 -Wire Wire Line - 1600 800 1650 700 -Wire Wire Line - 1600 650 1550 650 + 5000 550 5100 550 Wire Wire Line 5100 550 5100 650 Wire Wire Line @@ -174,7 +156,15 @@ Wire Wire Line Wire Wire Line 5200 650 5200 550 Wire Wire Line - 5000 550 5100 550 + 4300 800 5850 800 +Wire Wire Line + 4250 700 4300 800 +Wire Wire Line + 1600 800 1900 800 +Wire Wire Line + 1950 700 4250 700 +Wire Wire Line + 1900 800 1950 700 Wire Wire Line 5300 550 5300 650 Wire Wire Line @@ -184,11 +174,19 @@ Wire Wire Line Wire Wire Line 5200 550 5300 550 Wire Wire Line - 1550 850 2600 850 + 5500 550 5500 650 Wire Wire Line - 2600 850 2650 950 + 5500 650 5600 650 Wire Wire Line - 2650 950 4050 950 + 5600 650 5600 550 +Wire Wire Line + 5400 550 5500 550 +Wire Wire Line + 1600 850 2800 850 +Wire Wire Line + 2800 850 2850 950 +Wire Wire Line + 2850 950 4250 950 Text Notes 1450 950 2 50 ~ 0 ~DEVSEL~ Text Notes 3100 2450 0 50 ~ 0 @@ -766,47 +764,31 @@ Wire Wire Line Text Notes 1450 1400 2 50 ~ 0 PHI0r3 Wire Wire Line - 4700 1400 5650 1400 + 4900 1400 5850 1400 Wire Wire Line - 4650 1300 4700 1400 + 4850 1300 4900 1400 Wire Wire Line - 1600 1400 2250 1400 + 2450 1400 2500 1300 Wire Wire Line - 2250 1400 2300 1300 -Wire Wire Line - 2300 1300 4650 1300 + 2500 1300 4850 1300 Text Notes 1450 1250 2 50 ~ 0 PHI0r2 Wire Wire Line - 4500 1250 5650 1250 + 4700 1250 5850 1250 Wire Wire Line - 1600 1250 2050 1250 + 2250 1250 2300 1150 Wire Wire Line - 2050 1250 2100 1150 + 4300 850 5850 850 Wire Wire Line - 1600 1100 1950 1100 -Wire Wire Line - 1950 1100 2000 1000 -Text Notes 1450 1100 2 50 ~ 0 -PHI0r1 -Wire Wire Line - 4100 850 5650 850 -Wire Wire Line - 4050 950 4100 850 + 4250 950 4300 850 Wire Wire Line 3100 1750 4250 1750 Wire Wire Line 4250 1750 4300 1850 Wire Wire Line - 2100 1150 4450 1150 + 2300 1150 4650 1150 Wire Wire Line - 4450 1150 4500 1250 -Wire Wire Line - 4400 1100 5650 1100 -Wire Wire Line - 4350 1000 4400 1100 -Wire Wire Line - 2000 1000 4350 1000 + 4650 1150 4700 1250 Text Notes 5550 1550 0 50 ~ 0 0 Wire Wire Line @@ -818,15 +800,15 @@ Wire Wire Line Wire Wire Line 5500 1450 5650 1450 Wire Wire Line - 5500 550 5500 650 + 5700 550 5700 650 Wire Wire Line - 5500 650 5600 650 + 5700 650 5800 650 Wire Wire Line - 5600 650 5600 550 + 5800 650 5800 550 Wire Wire Line - 5600 550 5650 550 + 5800 550 5850 550 Wire Wire Line - 5400 550 5500 550 + 5600 550 5700 550 Text Notes 5300 2150 0 50 ~ 0 NOP Wire Wire Line @@ -1313,7 +1295,7 @@ Wire Wire Line Wire Wire Line 2500 2600 3050 2600 Wire Wire Line - 2400 550 2400 650 + 2600 550 2600 650 Wire Wire Line 4100 1550 4250 1550 Wire Wire Line @@ -1360,4 +1342,36 @@ Wire Wire Line 2500 2000 5650 2000 Text Notes 1450 1850 2 50 ~ 0 DEVSELr2 +Wire Wire Line + 2050 1100 2100 1000 +Text Notes 1450 1100 2 50 ~ 0 +PHI0r1 +Wire Wire Line + 4500 1100 5750 1100 +Wire Wire Line + 4450 1000 4500 1100 +Wire Wire Line + 2100 1000 2150 1000 +Wire Wire Line + 2100 1100 2150 1000 +Wire Wire Line + 1600 1100 2050 1100 +Connection ~ 2050 1100 +Wire Wire Line + 2050 1100 2100 1100 +Connection ~ 2150 1000 +Wire Wire Line + 2150 1000 4450 1000 +Wire Wire Line + 1600 650 1600 550 +Wire Wire Line + 1700 550 1600 550 +Wire Wire Line + 1700 650 1700 550 +Wire Wire Line + 1800 650 1700 650 +Wire Wire Line + 1600 1250 2250 1250 +Wire Wire Line + 1600 1400 2450 1400 $EndSCHEMATC diff --git a/cpld/GR8RAM.v b/cpld/GR8RAM.v index 7ddfc23..e5b5da2 100644 --- a/cpld/GR8RAM.v +++ b/cpld/GR8RAM.v @@ -296,10 +296,6 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI }; else WRD[7:0] <= RD[7:0]; end 5: begin // NOP CKE - if (AddrLSpecSEL) RDD[7:0] <= Addr[7:0]; - else if (AddrMSpecSEL) RDD[7:0] <= Addr[15:8]; - else if (AddrHSpecSEL) RDD[7:0] <= { SetEN24bit ? Addr[23:20] : 4'hF, Addr[19:16] }; - else RDD[7:0] <= SD[7:0]; end 6: begin // NOP CKE if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI }; else WRD[7:0] <= RD[7:0]; @@ -324,6 +320,16 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, endcase end + /* Apple data bus from SDRAM */ + always @(negedge C25M) begin + if (PS==5) begin + if (AddrLSpecSEL) RDD[7:0] <= Addr[7:0]; + else if (AddrMSpecSEL) RDD[7:0] <= Addr[15:8]; + else if (AddrHSpecSEL) RDD[7:0] <= { SetEN24bit ? Addr[23:20] : 4'hF, Addr[19:16] }; + else RDD[7:0] <= SD[7:0]; + end + end + /* SDRAM command */ output reg RCKE = 1; output reg nRCS = 1;