diff --git a/cpld/GR8RAM.v b/cpld/GR8RAM.v index 622fb1f..e2451ef 100644 --- a/cpld/GR8RAM.v +++ b/cpld/GR8RAM.v @@ -1,4 +1,4 @@ -module GR8RAM(C25M, PHI0, nBOD, nRES, nRESout, +module GR8RAM(C25M, PHI0, nRES, nRESout, nIOSEL, nDEVSEL, nIOSTRB, RA, nWE, RAdir, RD, RDdir, SBA, SA, nRCS, nRAS, nCAS, nSWE, DQML, DQMH, RCKE, SD, @@ -12,21 +12,11 @@ module GR8RAM(C25M, PHI0, nBOD, nRES, nRESout, always @(posedge C25M) begin PHI0r1 <= PHI0r0; PHI0r2 <= PHI0r1; end /* Reset/brown-out detect synchronized inputs */ - /* Outputs: nRESr, nBODf */ - input nRES, nBOD; + /* Outputs: nRESr */ + input nRES; reg nRESr0, nRESr; - reg nBODr0, nBODr, nBODf0, nBODf; - always @(negedge C25M) begin nBODr0 <= nBOD; nRESr0 <= nRES; end - always @(posedge C25M) begin nBODr <= nBODr0; nRESr <= nRESr0; end - always @(posedge C25M) begin - // Filter nBODr to get nBODf. Output hi when hi for $10000 cycles - if (LS[15:0]==16'hFF00) begin // When LS low-order is $FFF0 - nBODf0 <= nBODr; // "Precharge" nBODf0 - nBODf <= nBODf0; // Move computed nBODf0 into nBODf - end else if (nBODr) begin // Else AND nBODf0 with nBODr - nBODf0 <= nBODf0 && nBODr; // "Evaluate" by ANDing - end - end + always @(negedge C25M) begin nRESr0 <= nRES; end + always @(posedge C25M) begin nRESr <= nRESr0; end /* Long state counter: counts from 0 to $3FFFF */ /* Outputs: LS */ @@ -35,23 +25,9 @@ module GR8RAM(C25M, PHI0, nBOD, nRES, nRESout, /* Init state */ output reg nRESout = 0; - reg InitActv = 0; - reg InitIntr = 0; - reg SDRAMActv = 0; always @(posedge C25M) begin - if (~nBODf) begin - nRESout <= 0; - InitIntr <= 1; - end else if (~nRESr && LS[17:0]==18'h0FF00) begin - nRESout <= 0; - InitActv <= 1; - InitIntr <= 0; - end else if (LS[17:0]==18'h30002) begin - InitActv <= 0; - if (InitActv && ~InitIntr) begin - SDRAMActv <= 1; - nRESout <= 1; - end + if (LS[17:0]==18'h30002) begin + nRESout <= 1'b1; end end @@ -108,7 +84,7 @@ module GR8RAM(C25M, PHI0, nBOD, nRES, nRESout, /* Apple data bus */ inout [7:0] RD = RDdir ? 8'bZ : RDout[7:0]; reg [7:0] RDout; - output RDdir = ~(PHI0 && PHI0r2 && nWE && nRESr && + output RDdir = ~(PHI0 && PHI0r2 && nWE && ((~nDEVSEL && REGEN) || ~nIOSEL || (~nIOSTRB && IOROMEN))); /* Slinky address registers */ @@ -160,10 +136,10 @@ module GR8RAM(C25M, PHI0, nBOD, nRES, nRESout, /* SPI flash control */ always @(posedge C25M) begin - FCK <= (FCKEN && LS[0]) || (nRESr && FCKEN); + FCK <= ~nRESout && FCKEN && LS[0]; end always @(posedge C25M) begin - if (InitActv) begin + if (~nRESout) begin // Flash /CS enabled from init states $0FFB0 to $2FFFF if (LS[17:0]==18'h0FF90) FCS <= 1'b0; else if (LS[17:0]==18'h0FFA0) FCS <= 1'b1; @@ -212,7 +188,7 @@ module GR8RAM(C25M, PHI0, nBOD, nRES, nRESout, if (LS[17:0]==18'h0FF90) MOSIOE <= 1'b1; else if (LS[17:0]==18'h0FFF0) MOSIOE <= 1'b0; - end else if (nRESr) begin + end else begin //TODO: control these with Apple II FCS <= 0; FCKEN <= 0; @@ -337,34 +313,25 @@ module GR8RAM(C25M, PHI0, nBOD, nRES, nRESout, reg SDOE = 0; always @(posedge C25M) begin // Shift { MISO, MOSI } in when InitActv. When ready, synchronize RD - if (InitActv && LS[1]) WRD[7:0] <= { MISO, MOSI, WRD[5:0] }; + if (~nRESout && LS[1]) WRD[7:0] <= { MISO, MOSI, WRD[5:0] }; else if (PS==8) WRD[7:0] <= RD[7:0]; // Output data on SDRAM data bus only during init and when writing - SDOE <= InitActv || (RAMSpecWR && PS==8); + SDOE <= ~nRESout || (RAMSpecWR && PS==8); end reg [2:0] PS = 0; - wire PSStart = ~InitActv && nRESr && PS==0 && PHI0r1 && ~PHI0r2; + wire PSStart = nRESr && PS==0 && PHI0r1 && ~PHI0r2; always @(posedge C25M) begin if (PSStart) PS <= 1; else if (PS==0) PS <= 0; else PS <= PS+1; end - reg [1:0] IS = 0; - always @(posedge C25M) begin - if (InitActv) begin - if (LS[17:0]==18'h0FFAF) IS <= 1; - else if (LS[17:0]==18'h0FFBF) IS <= 2; - else if (LS[17:0]==18'h0FFFF) IS <= 3; - end else IS <= 0; - end - /* Refresh state */ reg RefReqd = 0; reg RefReady = 0; always @(posedge C25M) begin - if (LS[6:0]==7'h00) RefReqd <= SDRAMActv; // Reset RefDone every 128 C25M cycles (5.12 us) + if (LS[6:0]==7'h00) RefReqd <= 1; // Reset RefDone every 128 C25M cycles (5.12 us) else if (PS==0 && ~RefReqd) RefReqd <= 0; end @@ -440,8 +407,8 @@ module GR8RAM(C25M, PHI0, nBOD, nRES, nRESout, Amux <= 3'b001; end end else begin - // NOP CKD - RCKE <= 1'b0; + // NOP CKE + RCKE <= 1'b1; nRCS <= 1'b1; nRAS <= 1'b1; nCAS <= 1'b1; @@ -457,8 +424,8 @@ module GR8RAM(C25M, PHI0, nBOD, nRES, nRESout, nCAS <= 1'b1; nSWE <= 1'b1; end else begin - // NOP CKD - RCKE <= 1'b0; + // NOP CKE + RCKE <= 1'b1; nRCS <= 1'b1; nRAS <= 1'b1; nCAS <= 1'b1; @@ -475,8 +442,8 @@ module GR8RAM(C25M, PHI0, nBOD, nRES, nRESout, nCAS <= 1'b1; nSWE <= 1'b1; end else begin - // NOP CKD - RCKE <= 1'b0; + // NOP CKE + RCKE <= 1'b1; nRCS <= 1'b1; nRAS <= 1'b1; nCAS <= 1'b1; @@ -486,38 +453,20 @@ module GR8RAM(C25M, PHI0, nBOD, nRES, nRESout, if (ROMSpecRD) Amux <= 3'b101; else Amux <= 3'b111; end 3: begin - if (ROMSpecRD || RAMSpecRD) begin - // NOP CKE - RCKE <= 1'b1; - nRCS <= 1'b1; - nRAS <= 1'b1; - nCAS <= 1'b1; - nSWE <= 1'b1; - end else begin - // NOP CKD - RCKE <= 1'b0; - nRCS <= 1'b1; - nRAS <= 1'b1; - nCAS <= 1'b1; - nSWE <= 1'b1; - end + // NOP CKE + RCKE <= 1'b0; + nRCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nSWE <= 1'b1; Amux <= 3'b001; end 4: begin - if (RAMSpecWR && DEVSELr) begin - // NOP CKE - RCKE <= 1'b1; - nRCS <= 1'b1; - nRAS <= 1'b1; - nCAS <= 1'b1; - nSWE <= 1'b1; - end else begin - // NOP CKD - RCKE <= 1'b0; - nRCS <= 1'b1; - nRAS <= 1'b1; - nCAS <= 1'b1; - nSWE <= 1'b1; - end + // NOP CKE + RCKE <= 1'b0; + nRCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nSWE <= 1'b1; Amux <= 3'b001; end 5: begin if (RAMSpecWR && DEVSELr) begin @@ -528,8 +477,8 @@ module GR8RAM(C25M, PHI0, nBOD, nRES, nRESout, nCAS <= 1'b0; nSWE <= 1'b0; end else begin - // NOP CKD - RCKE <= 1'b0; + // NOP CKE + RCKE <= 1'b1; nRCS <= 1'b1; nRAS <= 1'b1; nCAS <= 1'b1; @@ -537,29 +486,19 @@ module GR8RAM(C25M, PHI0, nBOD, nRES, nRESout, end Amux <= 3'b111; end 6: begin - // NOP CKE if ACT'd, else CKD - RCKE <= ROMSpecRD || RAMSpecSEL; + RCKE <= 1'b1; nRCS <= 1'b1; nRAS <= 1'b1; nCAS <= 1'b1; nSWE <= 1'b1; Amux <= 3'b001; end 7: begin - if (ROMSpecRD || RAMSpecSEL) begin - // PC all CKD - RCKE <= 1'b0; - nRCS <= 1'b0; - nRAS <= 1'b0; - nCAS <= 1'b1; - nSWE <= 1'b0; - end else begin - // NOP CKD - RCKE <= 1'b0; - nRCS <= 1'b1; - nRAS <= 1'b1; - nCAS <= 1'b1; - nSWE <= 1'b1; - end + // PC all + RCKE <= 1'b1; + nRCS <= 1'b0; + nRAS <= 1'b0; + nCAS <= 1'b1; + nSWE <= 1'b0; Amux <= 3'b001; end endcase diff --git a/cpld/db/GR8RAM.(0).cnf.cdb b/cpld/db/GR8RAM.(0).cnf.cdb index e3cb276..8dab69a 100755 Binary files a/cpld/db/GR8RAM.(0).cnf.cdb and b/cpld/db/GR8RAM.(0).cnf.cdb differ diff --git a/cpld/db/GR8RAM.(0).cnf.hdb b/cpld/db/GR8RAM.(0).cnf.hdb index d532f1b..bc535ff 100755 Binary files a/cpld/db/GR8RAM.(0).cnf.hdb and b/cpld/db/GR8RAM.(0).cnf.hdb differ diff --git a/cpld/db/GR8RAM.asm.qmsg b/cpld/db/GR8RAM.asm.qmsg index aba5320..e41c033 100755 --- a/cpld/db/GR8RAM.asm.qmsg +++ b/cpld/db/GR8RAM.asm.qmsg @@ -1,6 +1,6 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616146132498 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616146132498 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 19 05:28:52 2021 " "Processing started: Fri Mar 19 05:28:52 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616146132498 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1616146132498 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1616146132498 ""} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1616146133795 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1616146133889 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "293 " "Peak virtual memory: 293 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616146134545 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 19 05:28:54 2021 " "Processing ended: Fri Mar 19 05:28:54 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616146134545 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616146134545 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616146134545 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1616146134545 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616153593678 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616153593694 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 19 07:33:13 2021 " "Processing started: Fri Mar 19 07:33:13 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616153593694 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1616153593694 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1616153593694 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1616153594788 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1616153594819 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "293 " "Peak virtual memory: 293 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616153595398 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 19 07:33:15 2021 " "Processing ended: Fri Mar 19 07:33:15 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616153595398 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616153595398 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616153595398 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1616153595398 ""} diff --git a/cpld/db/GR8RAM.asm.rdb b/cpld/db/GR8RAM.asm.rdb index dc1f18f..cb16983 100755 Binary files a/cpld/db/GR8RAM.asm.rdb and b/cpld/db/GR8RAM.asm.rdb differ diff --git a/cpld/db/GR8RAM.asm_labs.ddb b/cpld/db/GR8RAM.asm_labs.ddb new file mode 100755 index 0000000..3c1e725 Binary files /dev/null and b/cpld/db/GR8RAM.asm_labs.ddb differ diff --git a/cpld/db/GR8RAM.cmp.cdb b/cpld/db/GR8RAM.cmp.cdb index 904bc29..3d14fb7 100755 Binary files a/cpld/db/GR8RAM.cmp.cdb and b/cpld/db/GR8RAM.cmp.cdb differ diff --git a/cpld/db/GR8RAM.cmp.hdb b/cpld/db/GR8RAM.cmp.hdb index 9c31542..b8180eb 100755 Binary files a/cpld/db/GR8RAM.cmp.hdb and b/cpld/db/GR8RAM.cmp.hdb differ diff --git a/cpld/db/GR8RAM.cmp.idb b/cpld/db/GR8RAM.cmp.idb index 335d22f..d51f9c6 100755 Binary files a/cpld/db/GR8RAM.cmp.idb and b/cpld/db/GR8RAM.cmp.idb differ diff --git a/cpld/db/GR8RAM.cmp.rdb b/cpld/db/GR8RAM.cmp.rdb index 88123fa..9b0882b 100755 Binary files a/cpld/db/GR8RAM.cmp.rdb and b/cpld/db/GR8RAM.cmp.rdb differ diff --git a/cpld/db/GR8RAM.cmp0.ddb b/cpld/db/GR8RAM.cmp0.ddb new file mode 100755 index 0000000..2ffb76c Binary files /dev/null and b/cpld/db/GR8RAM.cmp0.ddb differ diff --git a/cpld/db/GR8RAM.fit.qmsg b/cpld/db/GR8RAM.fit.qmsg index e9af2d1..f68eb3e 100755 --- a/cpld/db/GR8RAM.fit.qmsg +++ b/cpld/db/GR8RAM.fit.qmsg @@ -1,57 +1,40 @@ -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1616151487348 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1616151487363 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1616151487520 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1616151487520 ""} -{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1616151487801 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1616151487832 ""} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1616151488160 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1616151488160 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1616151488160 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1616151488160 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1616151488160 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1616151488160 ""} -{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "69 69 " "No exact pin location assignment(s) for 69 pins of 69 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nRESout " "Pin nRESout not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nRESout } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 37 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nRESout } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 185 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RAdir " "Pin RAdir not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RAdir } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 77 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RAdir } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 319 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RDdir " "Pin RDdir not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RDdir } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 112 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RDdir } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 320 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SBA\[0\] " "Pin SBA\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SBA[0] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 372 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SBA[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 158 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SBA\[1\] " "Pin SBA\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SBA[1] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 372 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SBA[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 159 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[0\] " "Pin SA\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[0] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 377 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 160 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[1\] " "Pin SA\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[1] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 377 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 161 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[2\] " "Pin SA\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[2] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 377 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 162 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[3\] " "Pin SA\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[3] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 377 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 163 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[4\] " "Pin SA\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[4] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 377 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 164 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[5\] " "Pin SA\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[5] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 377 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 165 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[6\] " "Pin SA\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[6] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 377 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 166 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[7\] " "Pin SA\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[7] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 377 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 167 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[8\] " "Pin SA\[8\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[8] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 377 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 168 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[9\] " "Pin SA\[9\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[9] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 377 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 169 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[10\] " "Pin SA\[10\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[10] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 377 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 170 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[11\] " "Pin SA\[11\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[11] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 377 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 171 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[12\] " "Pin SA\[12\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[12] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 377 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 172 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nRCS " "Pin nRCS not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nRCS } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 409 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nRCS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 293 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nRAS " "Pin nRAS not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nRAS } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 410 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nRAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 295 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nCAS " "Pin nCAS not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nCAS } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 411 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nCAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 297 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nSWE " "Pin nSWE not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nSWE } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 412 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nSWE } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 299 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DQML " "Pin DQML not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { DQML } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 389 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { DQML } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 290 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DQMH " "Pin DQMH not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { DQMH } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 398 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { DQMH } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 301 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RCKE " "Pin RCKE not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RCKE } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 408 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RCKE } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 291 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nFCS " "Pin nFCS not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nFCS } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 152 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nFCS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 321 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "FCK " "Pin FCK not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { FCK } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 154 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { FCK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 213 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "MOSI " "Pin MOSI not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { MOSI } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 156 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { MOSI } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 253 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[0\] " "Pin RD\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[0] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 109 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 93 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[1\] " "Pin RD\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[1] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 109 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 92 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[2\] " "Pin RD\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[2] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 109 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 91 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[3\] " "Pin RD\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[3] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 109 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 90 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[4\] " "Pin RD\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[4] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 109 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 89 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[5\] " "Pin RD\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[5] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 109 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 88 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[6\] " "Pin RD\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[6] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 109 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 87 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[7\] " "Pin RD\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[7] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 109 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 55 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[0\] " "Pin SD\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[0] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 335 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 127 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[1\] " "Pin SD\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[1] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 335 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 126 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[2\] " "Pin SD\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[2] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 335 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 125 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[3\] " "Pin SD\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[3] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 335 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 123 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[4\] " "Pin SD\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[4] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 335 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 122 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[5\] " "Pin SD\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[5] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 335 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 121 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[6\] " "Pin SD\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[6] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 335 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 120 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[7\] " "Pin SD\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[7] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 335 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 119 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "PHI0 " "Pin PHI0 not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI0 } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 9 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 312 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nWE " "Pin nWE not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nWE } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 74 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nWE } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 318 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nDEVSEL " "Pin nDEVSEL not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nDEVSEL } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 60 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nDEVSEL } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 316 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nIOSTRB " "Pin nIOSTRB not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nIOSTRB } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 60 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nIOSTRB } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 317 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nIOSEL " "Pin nIOSEL not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nIOSEL } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 60 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nIOSEL } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 315 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "C25M " "Pin C25M not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { C25M } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 9 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { C25M } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 311 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[1\] " "Pin RA\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[1] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 73 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 143 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[10\] " "Pin RA\[10\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[10] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 73 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 152 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[2\] " "Pin RA\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[2] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 73 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 144 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[11\] " "Pin RA\[11\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[11] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 73 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 153 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[3\] " "Pin RA\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[3] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 73 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 145 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[4\] " "Pin RA\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[4] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 73 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 146 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[5\] " "Pin RA\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[5] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 73 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 147 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[6\] " "Pin RA\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[6] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 73 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 148 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[7\] " "Pin RA\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[7] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 73 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 149 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[8\] " "Pin RA\[8\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[8] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 73 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 150 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[9\] " "Pin RA\[9\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[9] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 73 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 151 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[0\] " "Pin RA\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[0] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 73 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 142 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nRES " "Pin nRES not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nRES } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 16 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nRES } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 314 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[14\] " "Pin RA\[14\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[14] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 73 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 156 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[15\] " "Pin RA\[15\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[15] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 73 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 157 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[12\] " "Pin RA\[12\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[12] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 73 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 154 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[13\] " "Pin RA\[13\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[13] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 73 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 155 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "MISO " "Pin MISO not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { MISO } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 159 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { MISO } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 322 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nBOD " "Pin nBOD not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nBOD } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 16 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nBOD } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 313 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151488176 ""} } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1616151488176 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1616151488395 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1616151488395 ""} -{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1616151488457 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1616151488457 ""} -{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1616151488457 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1616151488457 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 C25M " " 1.000 C25M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1616151488457 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1616151488457 ""} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1616151488488 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1616151488488 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1616151488520 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 14 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 14" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 9 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1616151488535 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1616151488535 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1616151488551 ""} -{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0 186391 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "Fitter" 0 -1 1616151488660 ""} -{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1616151488660 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1616151488754 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1616151488801 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1616151488832 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1616151488848 ""} -{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "68 unused 3.3V 24 28 16 " "Number of I/O pins in group: 68 (unused VREF, 3.3V VCCIO, 24 input, 28 output, 16 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "I/O standards used: 3.3-V LVTTL." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1616151488879 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1616151488879 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1616151488879 ""} -{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 1 37 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 37 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1616151488910 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 42 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 42 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1616151488910 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1616151488910 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1616151488910 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1616151488973 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1616151489223 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1616151489254 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.03 " "Total time spent on timing analysis during the Fitter is 0.03 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1616151489270 ""} -{ "Info" "IFITAPI_FITAPI_INFO_FITTER_RETRY_TIGHTER_LUT_REG_PACKING" "" "Fitter cannot place all nodes on current device -- Fitter will automatically make another fitting attempt and tightly pack logic elements" { } { } 0 170216 "Fitter cannot place all nodes on current device -- Fitter will automatically make another fitting attempt and tightly pack logic elements" 0 0 "Fitter" 0 -1 1616151489270 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1616151489270 ""} -{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Minimize Area " "Fitter is using Minimize Area packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0 186391 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "Fitter" 0 -1 1616151489270 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1616151489332 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1616151489332 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1616151489332 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1616151489332 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1616151489332 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1616151489535 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1616151489567 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.02 " "Total time spent on timing analysis during the Fitter is 0.02 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1616151489567 ""} -{ "Info" "IFITAPI_FITAPI_INFO_FITTER_RETRY_TIGHTER_LUT_REG_PACKING" "" "Fitter cannot place all nodes on current device -- Fitter will automatically make another fitting attempt and tightly pack logic elements" { } { } 0 170216 "Fitter cannot place all nodes on current device -- Fitter will automatically make another fitting attempt and tightly pack logic elements" 0 0 "Fitter" 0 -1 1616151489567 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1616151489567 ""} -{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Minimize Area with Chains " "Fitter is using Minimize Area with Chains packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0 186391 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "Fitter" 0 -1 1616151489567 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1616151489567 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1616151489567 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1616151489567 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1616151489567 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1616151489567 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1616151489863 ""} -{ "Error" "EFITAPI_FITAPI_VPR_STATUS_FAILED_TOO_MANY_BLES" "247 240 logic cell " "Design contains 247 blocks of type logic cell. However, device contains only 240." { } { { "c:/altera/13.0sp1/quartus/common/advisors/oa_resource_table.xml" "" { Advisor "Z:/Repos/GR8RAM/cpld/" "LE" } } } 0 170011 "Design contains %1!d! blocks of type %3!s!. However, device contains only %2!d!." 0 0 "Fitter" 0 -1 1616151489879 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1616151489879 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.02 " "Total time spent on timing analysis during the Fitter is 0.02 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1616151489879 ""} -{ "Error" "EFITCC_FITCC_FAIL" "" "Can't fit design in device" { } { } 0 171000 "Can't fit design in device" 0 0 "Fitter" 0 -1 1616151489973 ""} -{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1616151489973 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1616151490145 ""} -{ "Error" "EQEXE_ERROR_COUNT" "Fitter 2 s 4 s Quartus II 32-bit " "Quartus II 32-bit Fitter was unsuccessful. 2 errors, 4 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "367 " "Peak virtual memory: 367 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616151490317 ""} { "Error" "EQEXE_END_BANNER_TIME" "Fri Mar 19 06:58:10 2021 " "Processing ended: Fri Mar 19 06:58:10 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616151490317 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616151490317 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616151490317 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1616151490317 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1616153584815 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1616153584846 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1616153585049 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1616153585049 ""} +{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1616153585331 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1616153585378 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1616153585784 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1616153585784 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1616153585784 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1616153585784 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1616153585784 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1616153585784 ""} +{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "68 68 " "No exact pin location assignment(s) for 68 pins of 68 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nRESout " "Pin nRESout not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nRESout } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 27 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nRESout } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 178 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RAdir " "Pin RAdir not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RAdir } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 53 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RAdir } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 306 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RDdir " "Pin RDdir not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RDdir } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 88 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RDdir } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 307 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SBA\[0\] " "Pin SBA\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SBA[0] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 339 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SBA[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 157 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SBA\[1\] " "Pin SBA\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SBA[1] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 339 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SBA[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 158 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[0\] " "Pin SA\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[0] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 344 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 159 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[1\] " "Pin SA\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[1] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 344 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 160 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[2\] " "Pin SA\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[2] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 344 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 161 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[3\] " "Pin SA\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[3] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 344 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 162 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[4\] " "Pin SA\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[4] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 344 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 163 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[5\] " "Pin SA\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[5] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 344 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 164 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[6\] " "Pin SA\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[6] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 344 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 165 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[7\] " "Pin SA\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[7] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 344 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 166 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[8\] " "Pin SA\[8\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[8] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 344 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 167 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[9\] " "Pin SA\[9\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[9] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 344 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 168 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[10\] " "Pin SA\[10\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[10] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 344 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 169 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[11\] " "Pin SA\[11\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[11] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 344 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 170 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[12\] " "Pin SA\[12\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[12] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 344 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 171 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nRCS " "Pin nRCS not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nRCS } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 376 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nRCS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 282 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nRAS " "Pin nRAS not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nRAS } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 377 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nRAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 284 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nCAS " "Pin nCAS not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nCAS } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 378 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nCAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 286 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nSWE " "Pin nSWE not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nSWE } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 379 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nSWE } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 288 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DQML " "Pin DQML not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { DQML } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 356 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { DQML } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 279 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DQMH " "Pin DQMH not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { DQMH } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 365 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { DQMH } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 290 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RCKE " "Pin RCKE not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RCKE } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 375 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RCKE } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 280 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nFCS " "Pin nFCS not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nFCS } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 128 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nFCS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 308 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "FCK " "Pin FCK not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { FCK } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 130 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { FCK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 205 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "MOSI " "Pin MOSI not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { MOSI } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 132 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { MOSI } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 242 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[0\] " "Pin RD\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[0] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 85 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 92 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[1\] " "Pin RD\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[1] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 85 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 91 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[2\] " "Pin RD\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[2] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 85 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 90 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[3\] " "Pin RD\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[3] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 85 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 89 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[4\] " "Pin RD\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[4] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 85 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 88 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[5\] " "Pin RD\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[5] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 85 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 87 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[6\] " "Pin RD\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[6] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 85 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 86 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[7\] " "Pin RD\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[7] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 85 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 54 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[0\] " "Pin SD\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[0] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 311 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 126 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[1\] " "Pin SD\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[1] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 311 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 125 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[2\] " "Pin SD\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[2] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 311 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 124 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[3\] " "Pin SD\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[3] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 311 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 123 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[4\] " "Pin SD\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[4] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 311 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 121 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[5\] " "Pin SD\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[5] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 311 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 120 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[6\] " "Pin SD\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[6] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 311 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 119 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[7\] " "Pin SD\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[7] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 311 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 118 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "PHI0 " "Pin PHI0 not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI0 } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 9 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 300 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nWE " "Pin nWE not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nWE } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 50 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nWE } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 305 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nDEVSEL " "Pin nDEVSEL not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nDEVSEL } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 36 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nDEVSEL } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 303 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nIOSTRB " "Pin nIOSTRB not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nIOSTRB } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 36 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nIOSTRB } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 304 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nIOSEL " "Pin nIOSEL not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nIOSEL } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 36 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nIOSEL } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 302 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "C25M " "Pin C25M not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { C25M } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 9 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { C25M } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 299 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[1\] " "Pin RA\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[1] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 142 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[10\] " "Pin RA\[10\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[10] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 151 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[2\] " "Pin RA\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[2] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 143 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[11\] " "Pin RA\[11\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[11] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 152 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[3\] " "Pin RA\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[3] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 144 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[4\] " "Pin RA\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[4] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 145 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[5\] " "Pin RA\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[5] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 146 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[6\] " "Pin RA\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[6] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 147 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[7\] " "Pin RA\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[7] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 148 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[8\] " "Pin RA\[8\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[8] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 149 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[9\] " "Pin RA\[9\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[9] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 150 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[0\] " "Pin RA\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[0] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 141 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[14\] " "Pin RA\[14\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[14] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 155 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[15\] " "Pin RA\[15\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[15] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 156 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[12\] " "Pin RA\[12\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[12] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 153 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[13\] " "Pin RA\[13\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[13] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 154 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nRES " "Pin nRES not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nRES } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 16 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nRES } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 301 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "MISO " "Pin MISO not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { MISO } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 135 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { MISO } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 309 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153585800 ""} } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1616153585800 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1616153586097 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1616153586112 ""} +{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1616153586128 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1616153586128 ""} +{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1616153586128 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1616153586128 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 C25M " " 1.000 C25M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1616153586128 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1616153586128 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1616153586143 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1616153586143 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1616153586143 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 14 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 14" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 9 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1616153586159 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1616153586159 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1616153586175 ""} +{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0 186391 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "Fitter" 0 -1 1616153586222 ""} +{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1616153586222 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1616153586315 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1616153586331 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1616153586347 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1616153586362 ""} +{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "67 unused 3.3V 23 28 16 " "Number of I/O pins in group: 67 (unused VREF, 3.3V VCCIO, 23 input, 28 output, 16 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "I/O standards used: 3.3-V LVTTL." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1616153586394 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1616153586394 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1616153586394 ""} +{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 1 37 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 37 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1616153586409 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 42 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 42 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1616153586409 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1616153586409 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1616153586409 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1616153586456 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1616153586722 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1616153587050 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1616153587066 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1616153589676 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:03 " "Fitter placement operations ending: elapsed time is 00:00:03" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1616153589676 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1616153589723 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "27 " "Router estimated average interconnect usage is 27% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "27 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 27% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 27% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 27% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1616153590051 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1616153590051 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1616153590474 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.39 " "Total time spent on timing analysis during the Fitter is 0.39 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1616153590520 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1616153590520 ""} +{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1616153590552 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1616153590849 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "373 " "Peak virtual memory: 373 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616153591161 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 19 07:33:11 2021 " "Processing ended: Fri Mar 19 07:33:11 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616153591161 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616153591161 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:09 " "Total CPU time (on all processors): 00:00:09" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616153591161 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1616153591161 ""} diff --git a/cpld/db/GR8RAM.hier_info b/cpld/db/GR8RAM.hier_info index b76feff..f7b1be7 100755 --- a/cpld/db/GR8RAM.hier_info +++ b/cpld/db/GR8RAM.hier_info @@ -72,9 +72,6 @@ C25M => RACr.CLK C25M => IOSTRBr.CLK C25M => IOSELr.CLK C25M => DEVSELr.CLK -C25M => SDRAMActv.CLK -C25M => InitActv.CLK -C25M => InitIntr.CLK C25M => nRESout~reg0.CLK C25M => LS[0].CLK C25M => LS[1].CLK @@ -94,21 +91,16 @@ C25M => LS[14].CLK C25M => LS[15].CLK C25M => LS[16].CLK C25M => LS[17].CLK -C25M => nBODf.CLK -C25M => nBODf0.CLK C25M => nRESr.CLK -C25M => nBODr.CLK C25M => PHI0r2.CLK C25M => PHI0r1.CLK C25M => PHI0r0.CLK C25M => nRESr0.CLK -C25M => nBODr0.CLK C25M => IOSTRBr0.CLK C25M => IOSELr0.CLK C25M => DEVSELr0.CLK PHI0 => comb.IN1 PHI0 => PHI0r0.DATAIN -nBOD => nBODr0.DATAIN nRES => nRESr0.DATAIN nRESout <= nRESout~reg0.DB_MAX_OUTPUT_PORT_TYPE nIOSEL => comb.IN1 @@ -129,10 +121,10 @@ RA[8] => RAcur[8].DATAIN RA[9] => RAcur[9].DATAIN RA[10] => RAcur[10].DATAIN RA[11] => RAcur[11].DATAIN -RA[12] => Equal3.IN3 -RA[13] => Equal3.IN2 -RA[14] => Equal3.IN1 -RA[15] => Equal3.IN0 +RA[12] => Equal1.IN3 +RA[13] => Equal1.IN2 +RA[14] => Equal1.IN1 +RA[15] => Equal1.IN0 nWE => comb.IN1 nWE => nWEcur.DATAIN RAdir <= diff --git a/cpld/db/GR8RAM.hif b/cpld/db/GR8RAM.hif index d5775cc..64cfa8d 100755 Binary files a/cpld/db/GR8RAM.hif and b/cpld/db/GR8RAM.hif differ diff --git a/cpld/db/GR8RAM.map.cdb b/cpld/db/GR8RAM.map.cdb index d3af6de..b74821b 100755 Binary files a/cpld/db/GR8RAM.map.cdb and b/cpld/db/GR8RAM.map.cdb differ diff --git a/cpld/db/GR8RAM.map.hdb b/cpld/db/GR8RAM.map.hdb index 7ef4c5c..2370599 100755 Binary files a/cpld/db/GR8RAM.map.hdb and b/cpld/db/GR8RAM.map.hdb differ diff --git a/cpld/db/GR8RAM.map.qmsg b/cpld/db/GR8RAM.map.qmsg index b6baba4..20b9c46 100755 --- a/cpld/db/GR8RAM.map.qmsg +++ b/cpld/db/GR8RAM.map.qmsg @@ -1,32 +1,31 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616151477988 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616151478004 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 19 06:57:57 2021 " "Processing started: Fri Mar 19 06:57:57 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616151478004 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1616151478004 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1616151478004 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1616151479754 ""} -{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 72 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1616151480004 ""} -{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 188 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1616151480004 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_0ep " "Found entity 1: UFM_altufm_none_0ep" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616151480020 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616151480020 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1616151480020 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "gr8ram.v(109) " "Verilog HDL warning at gr8ram.v(109): extended using \"x\" or \"z\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 109 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1616151480270 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "gr8ram.v(335) " "Verilog HDL warning at gr8ram.v(335): extended using \"x\" or \"z\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 335 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1616151480270 ""} -{ "Warning" "WSGN_SEARCH_FILE" "gr8ram.v 1 1 " "Using design file gr8ram.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616151480285 ""} } { } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Quartus II" 0 -1 1616151480285 ""} -{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "UFMB gr8ram.v(247) " "Verilog HDL Implicit Net warning at gr8ram.v(247): created implicit net for \"UFMB\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 247 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1616151480285 ""} -{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "RTPB gr8ram.v(250) " "Verilog HDL Implicit Net warning at gr8ram.v(250): created implicit net for \"RTPB\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 250 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1616151480285 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1616151480316 ""} -{ "Warning" "WVRFX_VERI_2106_UNCONVERTED" "RDout gr8ram.v(110) " "Verilog HDL warning at gr8ram.v(110): object RDout used but never assigned" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 110 0 0 } } } 0 10858 "Verilog HDL warning at %2!s!: object %1!s! used but never assigned" 0 0 "Quartus II" 0 -1 1616151480316 "|GR8RAM"} -{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "UFMBr gr8ram.v(252) " "Verilog HDL or VHDL warning at gr8ram.v(252): object \"UFMBr\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 252 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616151480316 "|GR8RAM"} -{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "RTPBr gr8ram.v(254) " "Verilog HDL or VHDL warning at gr8ram.v(254): object \"RTPBr\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 254 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616151480316 "|GR8RAM"} -{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "IS gr8ram.v(354) " "Verilog HDL or VHDL warning at gr8ram.v(354): object \"IS\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 354 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616151480316 "|GR8RAM"} -{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "RefReady gr8ram.v(365) " "Verilog HDL or VHDL warning at gr8ram.v(365): object \"RefReady\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 365 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616151480316 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 gr8ram.v(34) " "Verilog HDL assignment warning at gr8ram.v(34): truncated value with size 32 to match size of target (18)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 34 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616151480316 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 24 gr8ram.v(124) " "Verilog HDL assignment warning at gr8ram.v(124): truncated value with size 32 to match size of target (24)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 124 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616151480316 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 gr8ram.v(128) " "Verilog HDL assignment warning at gr8ram.v(128): truncated value with size 32 to match size of target (16)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 128 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616151480316 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 gr8ram.v(133) " "Verilog HDL assignment warning at gr8ram.v(133): truncated value with size 32 to match size of target (8)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 133 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616151480332 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 gr8ram.v(351) " "Verilog HDL assignment warning at gr8ram.v(351): truncated value with size 32 to match size of target (3)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 351 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616151480348 "|GR8RAM"} -{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "RDout 0 gr8ram.v(110) " "Net \"RDout\" at gr8ram.v(110) has no driver or initial value, using a default initial value '0'" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 110 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Quartus II" 0 -1 1616151480348 "|GR8RAM"} -{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "WRD\[5..0\] 0 gr8ram.v(336) " "Net \"WRD\[5..0\]\" at gr8ram.v(336) has no driver or initial value, using a default initial value '0'" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 336 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Quartus II" 0 -1 1616151480348 "|GR8RAM"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "gr8ram.v" "UFM_inst" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 250 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1616151480457 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_0ep UFM:UFM_inst\|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component " "Elaborating entity \"UFM_altufm_none_0ep\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component\"" { } { { "UFM.v" "UFM_altufm_none_0ep_component" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 216 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1616151480488 ""} -{ "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR_HDR" "" "Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "MOSI WRD\[6\] " "Converted the fan-out from the tri-state buffer \"MOSI\" to the node \"WRD\[6\]\" into an OR gate" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 156 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1616151482051 ""} } { } 0 13046 "Tri-state node(s) do not directly drive top-level pin(s)" 0 0 "Quartus II" 0 -1 1616151482051 ""} -{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 77 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616151482410 "|GR8RAM|RAdir"} { "Warning" "WMLS_MLS_STUCK_PIN" "SBA\[0\] GND " "Pin \"SBA\[0\]\" is stuck at GND" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 372 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616151482410 "|GR8RAM|SBA[0]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1616151482410 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "351 " "Implemented 351 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "25 " "Implemented 25 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1616151482957 ""} { "Info" "ICUT_CUT_TM_OPINS" "28 " "Implemented 28 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1616151482957 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Implemented 16 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1616151482957 ""} { "Info" "ICUT_CUT_TM_LCELLS" "281 " "Implemented 281 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1616151482957 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Quartus II" 0 -1 1616151482957 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1616151482957 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1616151483223 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 20 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 20 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "301 " "Peak virtual memory: 301 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616151483426 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 19 06:58:03 2021 " "Processing ended: Fri Mar 19 06:58:03 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616151483426 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616151483426 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616151483426 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1616151483426 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616153574982 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616153574998 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 19 07:32:54 2021 " "Processing started: Fri Mar 19 07:32:54 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616153574998 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1616153574998 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1616153574998 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1616153576561 ""} +{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 72 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1616153576764 ""} +{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 188 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1616153576764 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_0ep " "Found entity 1: UFM_altufm_none_0ep" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616153576780 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616153576780 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1616153576780 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "gr8ram.v(85) " "Verilog HDL warning at gr8ram.v(85): extended using \"x\" or \"z\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 85 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1616153577046 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "gr8ram.v(311) " "Verilog HDL warning at gr8ram.v(311): extended using \"x\" or \"z\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 311 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1616153577046 ""} +{ "Warning" "WSGN_SEARCH_FILE" "gr8ram.v 1 1 " "Using design file gr8ram.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616153577061 ""} } { } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Quartus II" 0 -1 1616153577061 ""} +{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "UFMB gr8ram.v(223) " "Verilog HDL Implicit Net warning at gr8ram.v(223): created implicit net for \"UFMB\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 223 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1616153577061 ""} +{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "RTPB gr8ram.v(226) " "Verilog HDL Implicit Net warning at gr8ram.v(226): created implicit net for \"RTPB\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 226 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1616153577061 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1616153577093 ""} +{ "Warning" "WVRFX_VERI_2106_UNCONVERTED" "RDout gr8ram.v(86) " "Verilog HDL warning at gr8ram.v(86): object RDout used but never assigned" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 86 0 0 } } } 0 10858 "Verilog HDL warning at %2!s!: object %1!s! used but never assigned" 0 0 "Quartus II" 0 -1 1616153577093 "|GR8RAM"} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "UFMBr gr8ram.v(228) " "Verilog HDL or VHDL warning at gr8ram.v(228): object \"UFMBr\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 228 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616153577093 "|GR8RAM"} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "RTPBr gr8ram.v(230) " "Verilog HDL or VHDL warning at gr8ram.v(230): object \"RTPBr\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 230 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616153577093 "|GR8RAM"} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "RefReady gr8ram.v(332) " "Verilog HDL or VHDL warning at gr8ram.v(332): object \"RefReady\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 332 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616153577093 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 gr8ram.v(24) " "Verilog HDL assignment warning at gr8ram.v(24): truncated value with size 32 to match size of target (18)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 24 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616153577093 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 24 gr8ram.v(100) " "Verilog HDL assignment warning at gr8ram.v(100): truncated value with size 32 to match size of target (24)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 100 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616153577093 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 gr8ram.v(104) " "Verilog HDL assignment warning at gr8ram.v(104): truncated value with size 32 to match size of target (16)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 104 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616153577093 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 gr8ram.v(109) " "Verilog HDL assignment warning at gr8ram.v(109): truncated value with size 32 to match size of target (8)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 109 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616153577093 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 gr8ram.v(327) " "Verilog HDL assignment warning at gr8ram.v(327): truncated value with size 32 to match size of target (3)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 327 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616153577108 "|GR8RAM"} +{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "RDout 0 gr8ram.v(86) " "Net \"RDout\" at gr8ram.v(86) has no driver or initial value, using a default initial value '0'" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 86 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Quartus II" 0 -1 1616153577124 "|GR8RAM"} +{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "WRD\[5..0\] 0 gr8ram.v(312) " "Net \"WRD\[5..0\]\" at gr8ram.v(312) has no driver or initial value, using a default initial value '0'" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 312 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Quartus II" 0 -1 1616153577124 "|GR8RAM"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "gr8ram.v" "UFM_inst" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 226 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1616153577249 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_0ep UFM:UFM_inst\|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component " "Elaborating entity \"UFM_altufm_none_0ep\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component\"" { } { { "UFM.v" "UFM_altufm_none_0ep_component" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 216 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1616153577280 ""} +{ "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR_HDR" "" "Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "MOSI WRD\[6\] " "Converted the fan-out from the tri-state buffer \"MOSI\" to the node \"WRD\[6\]\" into an OR gate" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 132 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1616153578484 ""} } { } 0 13046 "Tri-state node(s) do not directly drive top-level pin(s)" 0 0 "Quartus II" 0 -1 1616153578484 ""} +{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616153578734 "|GR8RAM|RAdir"} { "Warning" "WMLS_MLS_STUCK_PIN" "SBA\[0\] GND " "Pin \"SBA\[0\]\" is stuck at GND" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 339 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616153578734 "|GR8RAM|SBA[0]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1616153578734 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "329 " "Implemented 329 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "24 " "Implemented 24 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1616153579297 ""} { "Info" "ICUT_CUT_TM_OPINS" "28 " "Implemented 28 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1616153579297 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Implemented 16 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1616153579297 ""} { "Info" "ICUT_CUT_TM_LCELLS" "260 " "Implemented 260 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1616153579297 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Quartus II" 0 -1 1616153579297 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1616153579297 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1616153579562 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 19 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 19 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "301 " "Peak virtual memory: 301 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616153579797 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 19 07:32:59 2021 " "Processing ended: Fri Mar 19 07:32:59 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616153579797 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616153579797 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616153579797 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1616153579797 ""} diff --git a/cpld/db/GR8RAM.map.rdb b/cpld/db/GR8RAM.map.rdb index 699ff40..b9c92fa 100755 Binary files a/cpld/db/GR8RAM.map.rdb and b/cpld/db/GR8RAM.map.rdb differ diff --git a/cpld/db/GR8RAM.pre_map.hdb b/cpld/db/GR8RAM.pre_map.hdb index 75c2a80..a45efbb 100755 Binary files a/cpld/db/GR8RAM.pre_map.hdb and b/cpld/db/GR8RAM.pre_map.hdb differ diff --git a/cpld/db/GR8RAM.root_partition.map.reg_db.cdb b/cpld/db/GR8RAM.root_partition.map.reg_db.cdb index 5a2f1ac..e374c49 100755 Binary files a/cpld/db/GR8RAM.root_partition.map.reg_db.cdb and b/cpld/db/GR8RAM.root_partition.map.reg_db.cdb differ diff --git a/cpld/db/GR8RAM.routing.rdb b/cpld/db/GR8RAM.routing.rdb index 2276e61..46897b8 100755 Binary files a/cpld/db/GR8RAM.routing.rdb and b/cpld/db/GR8RAM.routing.rdb differ diff --git a/cpld/db/GR8RAM.rtlv.hdb b/cpld/db/GR8RAM.rtlv.hdb index ddccba4..f2c61e9 100755 Binary files a/cpld/db/GR8RAM.rtlv.hdb and b/cpld/db/GR8RAM.rtlv.hdb differ diff --git a/cpld/db/GR8RAM.rtlv_sg.cdb b/cpld/db/GR8RAM.rtlv_sg.cdb index dfbc5cf..d558b57 100755 Binary files a/cpld/db/GR8RAM.rtlv_sg.cdb and b/cpld/db/GR8RAM.rtlv_sg.cdb differ diff --git a/cpld/db/GR8RAM.rtlv_sg_swap.cdb b/cpld/db/GR8RAM.rtlv_sg_swap.cdb index 4f228c0..2ddae33 100755 Binary files a/cpld/db/GR8RAM.rtlv_sg_swap.cdb and b/cpld/db/GR8RAM.rtlv_sg_swap.cdb differ diff --git a/cpld/db/GR8RAM.sgdiff.cdb b/cpld/db/GR8RAM.sgdiff.cdb index f6a9266..809d13f 100755 Binary files a/cpld/db/GR8RAM.sgdiff.cdb and b/cpld/db/GR8RAM.sgdiff.cdb differ diff --git a/cpld/db/GR8RAM.sgdiff.hdb b/cpld/db/GR8RAM.sgdiff.hdb index b1a9d14..3251251 100755 Binary files a/cpld/db/GR8RAM.sgdiff.hdb and b/cpld/db/GR8RAM.sgdiff.hdb differ diff --git a/cpld/db/GR8RAM.smart_action.txt b/cpld/db/GR8RAM.smart_action.txt index e04bbcf..c8e8a13 100755 --- a/cpld/db/GR8RAM.smart_action.txt +++ b/cpld/db/GR8RAM.smart_action.txt @@ -1 +1 @@ -FIT +DONE diff --git a/cpld/db/GR8RAM.sta.qmsg b/cpld/db/GR8RAM.sta.qmsg index 0fc335c..8036029 100755 --- a/cpld/db/GR8RAM.sta.qmsg +++ b/cpld/db/GR8RAM.sta.qmsg @@ -1,23 +1,23 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616146137780 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616146137811 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 19 05:28:56 2021 " "Processing started: Fri Mar 19 05:28:56 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616146137811 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1616146137811 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1616146137811 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1616146138030 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1616146138936 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1616146139139 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1616146139139 ""} -{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1616146139342 ""} -{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1616146139686 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1616146139874 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1616146139874 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1616146139889 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1616146139889 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C25M C25M " "create_clock -period 1.000 -name C25M C25M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1616146139889 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1616146139889 ""} -{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1616146139921 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1616146140030 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616146140061 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616146140061 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 ARCLK " " -99.000 -99.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616146140061 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 DRCLK " " -99.000 -99.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616146140061 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.598 -485.527 C25M " " -9.598 -485.527 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616146140061 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1616146140061 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold -16.296 " "Worst-case hold slack is -16.296" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616146140077 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616146140077 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.296 -16.296 ARCLK " " -16.296 -16.296 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616146140077 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.276 -16.276 DRCLK " " -16.276 -16.276 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616146140077 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.031 -1.031 C25M " " -1.031 -1.031 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616146140077 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1616146140077 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1616146140108 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1616146140124 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616146140139 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616146140139 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 ARCLK " " -29.500 -59.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616146140139 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 DRCLK " " -29.500 -59.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616146140139 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 C25M " " -2.289 -2.289 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616146140139 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1616146140139 ""} -{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1616146140483 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1616146140592 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1616146140592 ""} -{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "275 " "Peak virtual memory: 275 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616146140842 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 19 05:29:00 2021 " "Processing ended: Fri Mar 19 05:29:00 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616146140842 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616146140842 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616146140842 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1616146140842 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616153598352 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616153598368 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 19 07:33:17 2021 " "Processing started: Fri Mar 19 07:33:17 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616153598368 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1616153598368 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1616153598383 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1616153598555 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1616153599509 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1616153599790 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1616153599790 ""} +{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1616153600103 ""} +{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1616153600759 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1616153601103 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1616153601119 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C25M C25M " "create_clock -period 1.000 -name C25M C25M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1616153601135 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1616153601135 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1616153601197 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1616153601432 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -9.506 " "Worst-case setup slack is -9.506" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616153601447 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616153601447 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.506 -540.769 C25M " " -9.506 -540.769 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616153601447 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1616153601447 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.639 " "Worst-case hold slack is 1.639" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616153601463 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616153601463 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.639 0.000 C25M " " 1.639 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616153601463 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1616153601463 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1616153601478 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1616153601494 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.289 " "Worst-case minimum pulse width slack is -2.289" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616153601510 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616153601510 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 C25M " " -2.289 -2.289 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616153601510 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1616153601510 ""} +{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1616153601635 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1616153601901 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1616153601901 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "275 " "Peak virtual memory: 275 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616153602213 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 19 07:33:22 2021 " "Processing ended: Fri Mar 19 07:33:22 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616153602213 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616153602213 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616153602213 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1616153602213 ""} diff --git a/cpld/db/GR8RAM.sta.rdb b/cpld/db/GR8RAM.sta.rdb index de372fa..e7463ee 100755 Binary files a/cpld/db/GR8RAM.sta.rdb and b/cpld/db/GR8RAM.sta.rdb differ diff --git a/cpld/db/GR8RAM.sta_cmp.5_slow.tdb b/cpld/db/GR8RAM.sta_cmp.5_slow.tdb new file mode 100755 index 0000000..847bdbf Binary files /dev/null and b/cpld/db/GR8RAM.sta_cmp.5_slow.tdb differ diff --git a/cpld/db/GR8RAM.vpr.ammdb b/cpld/db/GR8RAM.vpr.ammdb index ead8e2a..d42d098 100755 Binary files a/cpld/db/GR8RAM.vpr.ammdb and b/cpld/db/GR8RAM.vpr.ammdb differ diff --git a/cpld/db/logic_util_heursitic.dat b/cpld/db/logic_util_heursitic.dat index e69de29..3d321f6 100755 Binary files a/cpld/db/logic_util_heursitic.dat and b/cpld/db/logic_util_heursitic.dat differ diff --git a/cpld/db/prev_cmp_GR8RAM.qmsg b/cpld/db/prev_cmp_GR8RAM.qmsg index 3ab3914..d17d7fe 100755 --- a/cpld/db/prev_cmp_GR8RAM.qmsg +++ b/cpld/db/prev_cmp_GR8RAM.qmsg @@ -1,101 +1,108 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616151256522 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616151256522 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 19 06:54:16 2021 " "Processing started: Fri Mar 19 06:54:16 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616151256522 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1616151256522 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1616151256522 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1616151258022 ""} -{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 72 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1616151258303 ""} -{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 188 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1616151258318 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_0ep " "Found entity 1: UFM_altufm_none_0ep" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616151258318 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616151258318 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1616151258318 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "gr8ram.v(109) " "Verilog HDL warning at gr8ram.v(109): extended using \"x\" or \"z\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 109 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1616151258647 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "gr8ram.v(349) " "Verilog HDL warning at gr8ram.v(349): extended using \"x\" or \"z\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 349 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1616151258662 ""} -{ "Warning" "WSGN_SEARCH_FILE" "gr8ram.v 1 1 " "Using design file gr8ram.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616151258662 ""} } { } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Quartus II" 0 -1 1616151258662 ""} -{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "UFMB gr8ram.v(261) " "Verilog HDL Implicit Net warning at gr8ram.v(261): created implicit net for \"UFMB\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 261 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1616151258662 ""} -{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "RTPB gr8ram.v(264) " "Verilog HDL Implicit Net warning at gr8ram.v(264): created implicit net for \"RTPB\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 264 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1616151258662 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1616151258709 ""} -{ "Warning" "WVRFX_VERI_2106_UNCONVERTED" "RDout gr8ram.v(110) " "Verilog HDL warning at gr8ram.v(110): object RDout used but never assigned" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 110 0 0 } } } 0 10858 "Verilog HDL warning at %2!s!: object %1!s! used but never assigned" 0 0 "Quartus II" 0 -1 1616151258709 "|GR8RAM"} -{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "UFMBr gr8ram.v(266) " "Verilog HDL or VHDL warning at gr8ram.v(266): object \"UFMBr\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 266 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616151258709 "|GR8RAM"} -{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "RTPBr gr8ram.v(268) " "Verilog HDL or VHDL warning at gr8ram.v(268): object \"RTPBr\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 268 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616151258709 "|GR8RAM"} -{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "SetLim8M gr8ram.v(273) " "Verilog HDL or VHDL warning at gr8ram.v(273): object \"SetLim8M\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 273 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616151258709 "|GR8RAM"} -{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "IS gr8ram.v(368) " "Verilog HDL or VHDL warning at gr8ram.v(368): object \"IS\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 368 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616151258709 "|GR8RAM"} -{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "RefReady gr8ram.v(379) " "Verilog HDL or VHDL warning at gr8ram.v(379): object \"RefReady\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 379 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616151258709 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 gr8ram.v(34) " "Verilog HDL assignment warning at gr8ram.v(34): truncated value with size 32 to match size of target (18)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 34 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616151258709 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 24 gr8ram.v(125) " "Verilog HDL assignment warning at gr8ram.v(125): truncated value with size 32 to match size of target (24)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 125 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616151258725 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 20 gr8ram.v(128) " "Verilog HDL assignment warning at gr8ram.v(128): truncated value with size 32 to match size of target (20)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 128 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616151258725 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 gr8ram.v(133) " "Verilog HDL assignment warning at gr8ram.v(133): truncated value with size 32 to match size of target (16)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 133 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616151258725 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 12 gr8ram.v(136) " "Verilog HDL assignment warning at gr8ram.v(136): truncated value with size 32 to match size of target (12)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 136 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616151258725 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 gr8ram.v(142) " "Verilog HDL assignment warning at gr8ram.v(142): truncated value with size 32 to match size of target (8)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 142 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616151258725 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 gr8ram.v(145) " "Verilog HDL assignment warning at gr8ram.v(145): truncated value with size 32 to match size of target (4)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 145 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616151258725 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 gr8ram.v(204) " "Verilog HDL assignment warning at gr8ram.v(204): truncated value with size 2 to match size of target (1)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 204 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616151258725 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 gr8ram.v(365) " "Verilog HDL assignment warning at gr8ram.v(365): truncated value with size 32 to match size of target (3)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 365 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616151258740 "|GR8RAM"} -{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "RDout 0 gr8ram.v(110) " "Net \"RDout\" at gr8ram.v(110) has no driver or initial value, using a default initial value '0'" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 110 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Quartus II" 0 -1 1616151258756 "|GR8RAM"} -{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "WRD\[5..0\] 0 gr8ram.v(350) " "Net \"WRD\[5..0\]\" at gr8ram.v(350) has no driver or initial value, using a default initial value '0'" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 350 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Quartus II" 0 -1 1616151258756 "|GR8RAM"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "gr8ram.v" "UFM_inst" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 264 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1616151258959 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_0ep UFM:UFM_inst\|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component " "Elaborating entity \"UFM_altufm_none_0ep\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component\"" { } { { "UFM.v" "UFM_altufm_none_0ep_component" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 216 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1616151259006 ""} -{ "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR_HDR" "" "Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "MOSI WRD\[6\] " "Converted the fan-out from the tri-state buffer \"MOSI\" to the node \"WRD\[6\]\" into an OR gate" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 170 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1616151260787 ""} } { } 0 13046 "Tri-state node(s) do not directly drive top-level pin(s)" 0 0 "Quartus II" 0 -1 1616151260787 ""} -{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 77 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616151261225 "|GR8RAM|RAdir"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1616151261225 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "384 " "Implemented 384 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "25 " "Implemented 25 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1616151261959 ""} { "Info" "ICUT_CUT_TM_OPINS" "28 " "Implemented 28 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1616151261959 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Implemented 16 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1616151261959 ""} { "Info" "ICUT_CUT_TM_LCELLS" "314 " "Implemented 314 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1616151261959 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Quartus II" 0 -1 1616151261959 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1616151261959 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1616151262256 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 24 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 24 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "301 " "Peak virtual memory: 301 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616151262506 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 19 06:54:22 2021 " "Processing ended: Fri Mar 19 06:54:22 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616151262506 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616151262506 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616151262506 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1616151262506 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616151265819 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 32-bit " "Running Quartus II 32-bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616151265834 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 19 06:54:24 2021 " "Processing started: Fri Mar 19 06:54:24 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616151265834 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1616151265834 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1616151265834 ""} -{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1616151266006 ""} -{ "Info" "0" "" "Project = GR8RAM" { } { } 0 0 "Project = GR8RAM" 0 0 "Fitter" 0 0 1616151266006 ""} -{ "Info" "0" "" "Revision = GR8RAM" { } { } 0 0 "Revision = GR8RAM" 0 0 "Fitter" 0 0 1616151266006 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1616151266647 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1616151266663 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1616151266819 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1616151266819 ""} -{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1616151267085 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1616151267116 ""} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1616151267428 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1616151267428 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1616151267428 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1616151267428 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1616151267428 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1616151267428 ""} -{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "69 69 " "No exact pin location assignment(s) for 69 pins of 69 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nRESout " "Pin nRESout not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nRESout } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 37 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nRESout } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 188 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RAdir " "Pin RAdir not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RAdir } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 77 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RAdir } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 322 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RDdir " "Pin RDdir not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RDdir } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 112 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RDdir } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 323 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SBA\[0\] " "Pin SBA\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SBA[0] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 386 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SBA[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 161 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SBA\[1\] " "Pin SBA\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SBA[1] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 386 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SBA[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 162 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[0\] " "Pin SA\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[0] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 391 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 163 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[1\] " "Pin SA\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[1] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 391 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 164 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[2\] " "Pin SA\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[2] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 391 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 165 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[3\] " "Pin SA\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[3] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 391 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 166 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[4\] " "Pin SA\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[4] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 391 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 167 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[5\] " "Pin SA\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[5] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 391 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 168 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[6\] " "Pin SA\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[6] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 391 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 169 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[7\] " "Pin SA\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[7] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 391 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 170 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[8\] " "Pin SA\[8\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[8] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 391 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 171 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[9\] " "Pin SA\[9\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[9] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 391 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 172 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[10\] " "Pin SA\[10\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[10] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 391 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 173 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[11\] " "Pin SA\[11\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[11] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 391 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 174 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[12\] " "Pin SA\[12\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[12] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 391 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 175 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nRCS " "Pin nRCS not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nRCS } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 420 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nRCS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 296 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nRAS " "Pin nRAS not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nRAS } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 421 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nRAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 298 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nCAS " "Pin nCAS not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nCAS } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 422 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nCAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 300 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nSWE " "Pin nSWE not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nSWE } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 423 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nSWE } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 302 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DQML " "Pin DQML not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { DQML } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 400 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { DQML } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 293 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DQMH " "Pin DQMH not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { DQMH } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 409 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { DQMH } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 304 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RCKE " "Pin RCKE not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RCKE } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 419 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RCKE } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 294 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nFCS " "Pin nFCS not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nFCS } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 166 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nFCS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 324 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "FCK " "Pin FCK not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { FCK } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 168 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { FCK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 219 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "MOSI " "Pin MOSI not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { MOSI } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 170 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { MOSI } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 259 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[0\] " "Pin RD\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[0] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 109 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 94 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[1\] " "Pin RD\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[1] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 109 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 93 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[2\] " "Pin RD\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[2] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 109 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 92 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[3\] " "Pin RD\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[3] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 109 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 91 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[4\] " "Pin RD\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[4] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 109 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 90 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[5\] " "Pin RD\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[5] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 109 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 89 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[6\] " "Pin RD\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[6] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 109 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 88 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[7\] " "Pin RD\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[7] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 109 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 56 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[0\] " "Pin SD\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[0] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 349 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 130 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[1\] " "Pin SD\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[1] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 349 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 129 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[2\] " "Pin SD\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[2] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 349 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 128 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[3\] " "Pin SD\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[3] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 349 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 126 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[4\] " "Pin SD\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[4] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 349 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 125 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[5\] " "Pin SD\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[5] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 349 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 124 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[6\] " "Pin SD\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[6] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 349 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 123 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[7\] " "Pin SD\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[7] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 349 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 122 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "PHI0 " "Pin PHI0 not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI0 } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 9 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 315 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nWE " "Pin nWE not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nWE } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 74 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nWE } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 321 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nDEVSEL " "Pin nDEVSEL not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nDEVSEL } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 60 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nDEVSEL } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 319 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nIOSTRB " "Pin nIOSTRB not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nIOSTRB } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 60 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nIOSTRB } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 320 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nIOSEL " "Pin nIOSEL not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nIOSEL } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 60 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nIOSEL } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 318 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "C25M " "Pin C25M not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { C25M } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 9 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { C25M } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 314 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[1\] " "Pin RA\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[1] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 73 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 146 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[10\] " "Pin RA\[10\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[10] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 73 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 155 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[2\] " "Pin RA\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[2] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 73 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 147 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[11\] " "Pin RA\[11\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[11] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 73 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 156 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[3\] " "Pin RA\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[3] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 73 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 148 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[4\] " "Pin RA\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[4] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 73 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 149 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[5\] " "Pin RA\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[5] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 73 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 150 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[6\] " "Pin RA\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[6] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 73 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 151 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[7\] " "Pin RA\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[7] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 73 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 152 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[8\] " "Pin RA\[8\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[8] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 73 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 153 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[9\] " "Pin RA\[9\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[9] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 73 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 154 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[0\] " "Pin RA\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[0] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 73 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 145 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nRES " "Pin nRES not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nRES } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 16 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nRES } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 317 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[14\] " "Pin RA\[14\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[14] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 73 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 159 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[15\] " "Pin RA\[15\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[15] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 73 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 160 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[12\] " "Pin RA\[12\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[12] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 73 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 157 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[13\] " "Pin RA\[13\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[13] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 73 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 158 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "MISO " "Pin MISO not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { MISO } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 173 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { MISO } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 325 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nBOD " "Pin nBOD not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nBOD } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 16 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nBOD } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 316 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616151267444 ""} } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1616151267444 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1616151267631 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1616151267631 ""} -{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1616151267663 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1616151267663 ""} -{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1616151267663 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1616151267663 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 C25M " " 1.000 C25M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1616151267663 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1616151267663 ""} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1616151267678 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1616151267694 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1616151267710 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 14 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 14" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 9 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1616151267772 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1616151267772 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1616151267788 ""} -{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0 186391 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "Fitter" 0 -1 1616151267866 ""} -{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1616151267866 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1616151267928 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1616151267944 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1616151267944 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1616151267944 ""} -{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "68 unused 3.3V 24 28 16 " "Number of I/O pins in group: 68 (unused VREF, 3.3V VCCIO, 24 input, 28 output, 16 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "I/O standards used: 3.3-V LVTTL." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1616151267960 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1616151267960 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1616151267960 ""} -{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 1 37 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 37 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1616151267960 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 42 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 42 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1616151267960 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1616151267960 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1616151267960 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1616151267991 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1616151268257 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1616151268288 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.02 " "Total time spent on timing analysis during the Fitter is 0.02 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1616151268288 ""} -{ "Info" "IFITAPI_FITAPI_INFO_FITTER_RETRY_TIGHTER_LUT_REG_PACKING" "" "Fitter cannot place all nodes on current device -- Fitter will automatically make another fitting attempt and tightly pack logic elements" { } { } 0 170216 "Fitter cannot place all nodes on current device -- Fitter will automatically make another fitting attempt and tightly pack logic elements" 0 0 "Fitter" 0 -1 1616151268288 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1616151268303 ""} -{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Minimize Area " "Fitter is using Minimize Area packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0 186391 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "Fitter" 0 -1 1616151268303 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1616151268366 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1616151268366 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1616151268366 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1616151268366 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1616151268366 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1616151268522 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1616151268553 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.02 " "Total time spent on timing analysis during the Fitter is 0.02 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1616151268553 ""} -{ "Info" "IFITAPI_FITAPI_INFO_FITTER_RETRY_TIGHTER_LUT_REG_PACKING" "" "Fitter cannot place all nodes on current device -- Fitter will automatically make another fitting attempt and tightly pack logic elements" { } { } 0 170216 "Fitter cannot place all nodes on current device -- Fitter will automatically make another fitting attempt and tightly pack logic elements" 0 0 "Fitter" 0 -1 1616151268553 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1616151268553 ""} -{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Minimize Area with Chains " "Fitter is using Minimize Area with Chains packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0 186391 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "Fitter" 0 -1 1616151268553 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1616151268569 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1616151268569 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1616151268569 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1616151268569 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1616151268569 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1616151268819 ""} -{ "Error" "EFITAPI_FITAPI_VPR_STATUS_FAILED_TOO_MANY_BLES" "283 240 logic cell " "Design contains 283 blocks of type logic cell. However, device contains only 240." { } { { "c:/altera/13.0sp1/quartus/common/advisors/oa_resource_table.xml" "" { Advisor "Z:/Repos/GR8RAM/cpld/" "LE" } } } 0 170011 "Design contains %1!d! blocks of type %3!s!. However, device contains only %2!d!." 0 0 "Fitter" 0 -1 1616151268835 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1616151268835 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.00 " "Total time spent on timing analysis during the Fitter is 0.00 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1616151268835 ""} -{ "Error" "EFITCC_FITCC_FAIL" "" "Can't fit design in device" { } { } 0 171000 "Can't fit design in device" 0 0 "Fitter" 0 -1 1616151268944 ""} -{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1616151268944 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1616151269132 ""} -{ "Error" "EQEXE_ERROR_COUNT" "Fitter 2 s 4 s Quartus II 32-bit " "Quartus II 32-bit Fitter was unsuccessful. 2 errors, 4 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "367 " "Peak virtual memory: 367 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616151269288 ""} { "Error" "EQEXE_END_BANNER_TIME" "Fri Mar 19 06:54:29 2021 " "Processing ended: Fri Mar 19 06:54:29 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616151269288 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616151269288 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616151269288 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1616151269288 ""} -{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 4 s 28 s " "Quartus II Full Compilation was unsuccessful. 4 errors, 28 warnings" { } { } 0 293001 "Quartus II %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1616151270444 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616153517201 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616153517201 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 19 07:31:56 2021 " "Processing started: Fri Mar 19 07:31:56 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616153517201 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1616153517201 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1616153517201 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1616153518951 ""} +{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 72 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1616153519217 ""} +{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 188 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1616153519232 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_0ep " "Found entity 1: UFM_altufm_none_0ep" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616153519232 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616153519232 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1616153519232 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "gr8ram.v(85) " "Verilog HDL warning at gr8ram.v(85): extended using \"x\" or \"z\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 85 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1616153519529 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "gr8ram.v(311) " "Verilog HDL warning at gr8ram.v(311): extended using \"x\" or \"z\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 311 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1616153519545 ""} +{ "Warning" "WSGN_SEARCH_FILE" "gr8ram.v 1 1 " "Using design file gr8ram.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616153519545 ""} } { } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Quartus II" 0 -1 1616153519545 ""} +{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "UFMB gr8ram.v(223) " "Verilog HDL Implicit Net warning at gr8ram.v(223): created implicit net for \"UFMB\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 223 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1616153519545 ""} +{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "RTPB gr8ram.v(226) " "Verilog HDL Implicit Net warning at gr8ram.v(226): created implicit net for \"RTPB\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 226 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1616153519545 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1616153519592 ""} +{ "Warning" "WVRFX_VERI_2106_UNCONVERTED" "RDout gr8ram.v(86) " "Verilog HDL warning at gr8ram.v(86): object RDout used but never assigned" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 86 0 0 } } } 0 10858 "Verilog HDL warning at %2!s!: object %1!s! used but never assigned" 0 0 "Quartus II" 0 -1 1616153519592 "|GR8RAM"} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "UFMBr gr8ram.v(228) " "Verilog HDL or VHDL warning at gr8ram.v(228): object \"UFMBr\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 228 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616153519592 "|GR8RAM"} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "RTPBr gr8ram.v(230) " "Verilog HDL or VHDL warning at gr8ram.v(230): object \"RTPBr\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 230 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616153519592 "|GR8RAM"} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "RefReady gr8ram.v(332) " "Verilog HDL or VHDL warning at gr8ram.v(332): object \"RefReady\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 332 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616153519592 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 gr8ram.v(24) " "Verilog HDL assignment warning at gr8ram.v(24): truncated value with size 32 to match size of target (18)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 24 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616153519592 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 24 gr8ram.v(100) " "Verilog HDL assignment warning at gr8ram.v(100): truncated value with size 32 to match size of target (24)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 100 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616153519592 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 gr8ram.v(104) " "Verilog HDL assignment warning at gr8ram.v(104): truncated value with size 32 to match size of target (16)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 104 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616153519592 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 gr8ram.v(109) " "Verilog HDL assignment warning at gr8ram.v(109): truncated value with size 32 to match size of target (8)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 109 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616153519592 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 gr8ram.v(327) " "Verilog HDL assignment warning at gr8ram.v(327): truncated value with size 32 to match size of target (3)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 327 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616153519607 "|GR8RAM"} +{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "RDout 0 gr8ram.v(86) " "Net \"RDout\" at gr8ram.v(86) has no driver or initial value, using a default initial value '0'" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 86 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Quartus II" 0 -1 1616153519607 "|GR8RAM"} +{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "WRD\[5..0\] 0 gr8ram.v(312) " "Net \"WRD\[5..0\]\" at gr8ram.v(312) has no driver or initial value, using a default initial value '0'" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 312 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Quartus II" 0 -1 1616153519607 "|GR8RAM"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "gr8ram.v" "UFM_inst" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 226 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1616153519779 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_0ep UFM:UFM_inst\|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component " "Elaborating entity \"UFM_altufm_none_0ep\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component\"" { } { { "UFM.v" "UFM_altufm_none_0ep_component" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 216 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1616153519811 ""} +{ "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR_HDR" "" "Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "MOSI WRD\[6\] " "Converted the fan-out from the tri-state buffer \"MOSI\" to the node \"WRD\[6\]\" into an OR gate" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 132 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1616153521326 ""} } { } 0 13046 "Tri-state node(s) do not directly drive top-level pin(s)" 0 0 "Quartus II" 0 -1 1616153521326 ""} +{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616153521670 "|GR8RAM|RAdir"} { "Warning" "WMLS_MLS_STUCK_PIN" "SBA\[0\] GND " "Pin \"SBA\[0\]\" is stuck at GND" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 339 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616153521670 "|GR8RAM|SBA[0]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1616153521670 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "329 " "Implemented 329 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "24 " "Implemented 24 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1616153522530 ""} { "Info" "ICUT_CUT_TM_OPINS" "28 " "Implemented 28 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1616153522530 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Implemented 16 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1616153522530 ""} { "Info" "ICUT_CUT_TM_LCELLS" "260 " "Implemented 260 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1616153522530 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Quartus II" 0 -1 1616153522530 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1616153522530 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1616153522936 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 19 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 19 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "301 " "Peak virtual memory: 301 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616153523358 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 19 07:32:03 2021 " "Processing ended: Fri Mar 19 07:32:03 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616153523358 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616153523358 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616153523358 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1616153523358 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616153526608 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 32-bit " "Running Quartus II 32-bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616153526624 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 19 07:32:04 2021 " "Processing started: Fri Mar 19 07:32:04 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616153526624 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1616153526624 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1616153526639 ""} +{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1616153526811 ""} +{ "Info" "0" "" "Project = GR8RAM" { } { } 0 0 "Project = GR8RAM" 0 0 "Fitter" 0 0 1616153526811 ""} +{ "Info" "0" "" "Revision = GR8RAM" { } { } 0 0 "Revision = GR8RAM" 0 0 "Fitter" 0 0 1616153526811 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1616153527530 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1616153527577 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1616153527796 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1616153527796 ""} +{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1616153528171 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1616153528218 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1616153528671 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1616153528671 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1616153528671 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1616153528671 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1616153528671 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1616153528671 ""} +{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "68 68 " "No exact pin location assignment(s) for 68 pins of 68 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nRESout " "Pin nRESout not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nRESout } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 27 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nRESout } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 178 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RAdir " "Pin RAdir not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RAdir } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 53 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RAdir } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 307 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RDdir " "Pin RDdir not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RDdir } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 88 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RDdir } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 308 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SBA\[0\] " "Pin SBA\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SBA[0] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 339 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SBA[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 157 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SBA\[1\] " "Pin SBA\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SBA[1] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 339 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SBA[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 158 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[0\] " "Pin SA\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[0] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 344 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 159 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[1\] " "Pin SA\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[1] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 344 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 160 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[2\] " "Pin SA\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[2] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 344 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 161 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[3\] " "Pin SA\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[3] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 344 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 162 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[4\] " "Pin SA\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[4] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 344 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 163 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[5\] " "Pin SA\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[5] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 344 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 164 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[6\] " "Pin SA\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[6] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 344 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 165 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[7\] " "Pin SA\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[7] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 344 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 166 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[8\] " "Pin SA\[8\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[8] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 344 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 167 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[9\] " "Pin SA\[9\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[9] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 344 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 168 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[10\] " "Pin SA\[10\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[10] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 344 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 169 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[11\] " "Pin SA\[11\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[11] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 344 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 170 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[12\] " "Pin SA\[12\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[12] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 344 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 171 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nRCS " "Pin nRCS not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nRCS } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 376 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nRCS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 282 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nRAS " "Pin nRAS not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nRAS } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 377 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nRAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 284 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nCAS " "Pin nCAS not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nCAS } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 378 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nCAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 286 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nSWE " "Pin nSWE not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nSWE } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 379 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nSWE } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 288 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DQML " "Pin DQML not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { DQML } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 356 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { DQML } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 279 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DQMH " "Pin DQMH not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { DQMH } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 365 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { DQMH } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 290 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RCKE " "Pin RCKE not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RCKE } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 375 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RCKE } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 280 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nFCS " "Pin nFCS not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nFCS } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 128 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nFCS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 309 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "FCK " "Pin FCK not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { FCK } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 130 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { FCK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 205 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "MOSI " "Pin MOSI not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { MOSI } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 132 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { MOSI } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 242 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[0\] " "Pin RD\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[0] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 85 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 92 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[1\] " "Pin RD\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[1] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 85 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 91 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[2\] " "Pin RD\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[2] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 85 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 90 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[3\] " "Pin RD\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[3] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 85 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 89 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[4\] " "Pin RD\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[4] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 85 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 88 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[5\] " "Pin RD\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[5] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 85 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 87 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[6\] " "Pin RD\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[6] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 85 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 86 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RD\[7\] " "Pin RD\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RD[7] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 85 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 54 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[0\] " "Pin SD\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[0] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 311 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 126 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[1\] " "Pin SD\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[1] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 311 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 125 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[2\] " "Pin SD\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[2] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 311 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 124 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[3\] " "Pin SD\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[3] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 311 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 123 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[4\] " "Pin SD\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[4] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 311 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 121 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[5\] " "Pin SD\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[5] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 311 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 120 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[6\] " "Pin SD\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[6] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 311 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 119 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD\[7\] " "Pin SD\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SD[7] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 311 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SD[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 118 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "PHI0 " "Pin PHI0 not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI0 } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 9 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 301 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nWE " "Pin nWE not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nWE } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 50 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nWE } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 306 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nDEVSEL " "Pin nDEVSEL not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nDEVSEL } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 36 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nDEVSEL } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 304 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nIOSTRB " "Pin nIOSTRB not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nIOSTRB } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 36 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nIOSTRB } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 305 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nIOSEL " "Pin nIOSEL not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nIOSEL } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 36 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nIOSEL } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 303 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "C25M " "Pin C25M not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { C25M } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 9 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { C25M } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 300 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[1\] " "Pin RA\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[1] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 142 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[10\] " "Pin RA\[10\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[10] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 151 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[2\] " "Pin RA\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[2] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 143 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[11\] " "Pin RA\[11\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[11] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 152 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[3\] " "Pin RA\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[3] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 144 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[4\] " "Pin RA\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[4] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 145 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[5\] " "Pin RA\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[5] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 146 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[6\] " "Pin RA\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[6] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 147 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[7\] " "Pin RA\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[7] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 148 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[8\] " "Pin RA\[8\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[8] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 149 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[9\] " "Pin RA\[9\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[9] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 150 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[0\] " "Pin RA\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[0] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 141 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[14\] " "Pin RA\[14\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[14] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 155 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[15\] " "Pin RA\[15\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[15] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 156 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[12\] " "Pin RA\[12\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[12] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 153 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RA\[13\] " "Pin RA\[13\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { RA[13] } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 49 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { RA[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 154 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "nRES " "Pin nRES not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nRES } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 16 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nRES } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 302 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "MISO " "Pin MISO not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { MISO } } } { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 135 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { MISO } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 310 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1616153528702 ""} } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1616153528702 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1616153528843 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1616153528858 ""} +{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1616153528905 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1616153528905 ""} +{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1616153528905 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1616153528905 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 C25M " " 1.000 C25M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1616153528905 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1616153528905 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1616153528921 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1616153528937 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1616153528968 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 14 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 14" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 9 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1616153528983 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1616153528983 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1616153528999 ""} +{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0 186391 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "Fitter" 0 -1 1616153529046 ""} +{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1616153529046 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1616153529108 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1616153529108 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1616153529108 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1616153529124 ""} +{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "67 unused 3.3V 23 28 16 " "Number of I/O pins in group: 67 (unused VREF, 3.3V VCCIO, 23 input, 28 output, 16 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "I/O standards used: 3.3-V LVTTL." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1616153529140 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1616153529140 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1616153529140 ""} +{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 1 37 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 37 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1616153529155 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 42 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 42 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1616153529155 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1616153529155 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1616153529155 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1616153529171 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1616153529374 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1616153529702 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1616153529734 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1616153532703 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:03 " "Fitter placement operations ending: elapsed time is 00:00:03" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1616153532718 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1616153532765 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "22 " "Router estimated average interconnect usage is 22% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "22 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 22% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 22% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 22% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1616153533140 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1616153533140 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1616153533593 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.36 " "Total time spent on timing analysis during the Fitter is 0.36 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1616153533625 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1616153533625 ""} +{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1616153533640 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1616153533921 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "373 " "Peak virtual memory: 373 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616153534203 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 19 07:32:14 2021 " "Processing ended: Fri Mar 19 07:32:14 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616153534203 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616153534203 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:09 " "Total CPU time (on all processors): 00:00:09" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616153534203 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1616153534203 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1616153537812 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616153537812 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 19 07:32:17 2021 " "Processing started: Fri Mar 19 07:32:17 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616153537812 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1616153537812 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1616153537812 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1616153539344 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1616153539360 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "293 " "Peak virtual memory: 293 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616153540016 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 19 07:32:20 2021 " "Processing ended: Fri Mar 19 07:32:20 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616153540016 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616153540016 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616153540016 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1616153540016 ""} +{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1616153540907 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1616153543094 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616153543110 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 19 07:32:21 2021 " "Processing started: Fri Mar 19 07:32:21 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616153543110 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1616153543110 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1616153543110 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1616153543297 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1616153544063 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1616153544219 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1616153544219 ""} +{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1616153544376 ""} +{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1616153544844 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1616153545032 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1616153545048 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C25M C25M " "create_clock -period 1.000 -name C25M C25M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1616153545048 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1616153545048 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1616153545079 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1616153545235 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -9.078 " "Worst-case setup slack is -9.078" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616153545266 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616153545266 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.078 -545.414 C25M " " -9.078 -545.414 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616153545266 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1616153545266 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.414 " "Worst-case hold slack is 1.414" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616153545266 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616153545266 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.414 0.000 C25M " " 1.414 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616153545266 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1616153545266 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1616153545282 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1616153545298 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.289 " "Worst-case minimum pulse width slack is -2.289" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616153545298 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616153545298 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 C25M " " -2.289 -2.289 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616153545298 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1616153545298 ""} +{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1616153545423 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1616153545579 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1616153545579 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "275 " "Peak virtual memory: 275 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616153545938 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 19 07:32:25 2021 " "Processing ended: Fri Mar 19 07:32:25 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616153545938 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616153545938 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616153545938 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1616153545938 ""} +{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 25 s " "Quartus II Full Compilation was successful. 0 errors, 25 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1616153547063 ""} diff --git a/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt b/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt index 2a57a12..f518336 100755 Binary files a/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt and b/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt differ diff --git a/cpld/output_files/GR8RAM.asm.rpt b/cpld/output_files/GR8RAM.asm.rpt index 86126fb..01eec4e 100755 --- a/cpld/output_files/GR8RAM.asm.rpt +++ b/cpld/output_files/GR8RAM.asm.rpt @@ -1,5 +1,5 @@ Assembler report for GR8RAM -Fri Mar 19 05:28:54 2021 +Fri Mar 19 07:33:15 2021 Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition @@ -37,7 +37,7 @@ applicable agreement for further details. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Fri Mar 19 05:28:54 2021 ; +; Assembler Status ; Successful - Fri Mar 19 07:33:15 2021 ; ; Revision Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ; ; Family ; MAX II ; @@ -90,8 +90,8 @@ applicable agreement for further details. ; Option ; Setting ; +----------------+-------------------------------------------------------+ ; Device ; EPM240T100C5 ; -; JTAG usercode ; 0x0016E052 ; -; Checksum ; 0x0016E4CA ; +; JTAG usercode ; 0x00164F11 ; +; Checksum ; 0x00165309 ; +----------------+-------------------------------------------------------+ @@ -101,13 +101,13 @@ applicable agreement for further details. Info: ******************************************************************* Info: Running Quartus II 32-bit Assembler Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - Info: Processing started: Fri Mar 19 05:28:52 2021 + Info: Processing started: Fri Mar 19 07:33:13 2021 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM Info (115031): Writing out detailed assembly data for power analysis Info (115030): Assembler is generating device programming files Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings Info: Peak virtual memory: 293 megabytes - Info: Processing ended: Fri Mar 19 05:28:54 2021 + Info: Processing ended: Fri Mar 19 07:33:15 2021 Info: Elapsed time: 00:00:02 Info: Total CPU time (on all processors): 00:00:02 diff --git a/cpld/output_files/GR8RAM.done b/cpld/output_files/GR8RAM.done index 5e09f4e..ac942b9 100755 --- a/cpld/output_files/GR8RAM.done +++ b/cpld/output_files/GR8RAM.done @@ -1 +1 @@ -Fri Mar 19 05:29:01 2021 +Fri Mar 19 07:33:23 2021 diff --git a/cpld/output_files/GR8RAM.fit.rpt b/cpld/output_files/GR8RAM.fit.rpt index 9f384ca..d4a1357 100755 --- a/cpld/output_files/GR8RAM.fit.rpt +++ b/cpld/output_files/GR8RAM.fit.rpt @@ -1,5 +1,5 @@ Fitter report for GR8RAM -Fri Mar 19 06:58:10 2021 +Fri Mar 19 07:33:10 2021 Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition @@ -10,21 +10,28 @@ Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit 2. Fitter Summary 3. Fitter Settings 4. Parallel Compilation - 5. Fitter Resource Usage Summary - 6. Input Pins - 7. Output Pins - 8. Bidir Pins - 9. I/O Bank Usage - 10. All Package Pins - 11. Output Pin Default Load For Reported TCO - 12. Fitter Resource Utilization by Entity - 13. Delay Chain Summary - 14. Control Signals - 15. Global & Other Fast Signals - 16. Non-Global High Fan-Out Signals - 17. Fitter Device Options - 18. Fitter Messages - 19. Fitter Suppressed Messages + 5. Pin-Out File + 6. Fitter Resource Usage Summary + 7. Input Pins + 8. Output Pins + 9. Bidir Pins + 10. I/O Bank Usage + 11. All Package Pins + 12. Output Pin Default Load For Reported TCO + 13. Fitter Resource Utilization by Entity + 14. Delay Chain Summary + 15. Control Signals + 16. Global & Other Fast Signals + 17. Non-Global High Fan-Out Signals + 18. Other Routing Usage Summary + 19. LAB Logic Elements + 20. LAB-wide Signals + 21. LAB Signals Sourced + 22. LAB Signals Sourced Out + 23. LAB Distinct Inputs + 24. Fitter Device Options + 25. Fitter Messages + 26. Fitter Suppressed Messages @@ -50,15 +57,15 @@ applicable agreement for further details. +-----------------------------------------------------------------------------+ ; Fitter Summary ; +---------------------------+-------------------------------------------------+ -; Fitter Status ; Failed - Fri Mar 19 06:58:10 2021 ; +; Fitter Status ; Successful - Fri Mar 19 07:33:10 2021 ; ; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; ; Revision Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ; ; Family ; MAX II ; ; Device ; EPM240T100C5 ; ; Timing Models ; Final ; -; Total logic elements ; 247 / 240 ( 103 % ) ; -; Total pins ; 69 / 80 ( 86 % ) ; +; Total logic elements ; 235 / 240 ( 98 % ) ; +; Total pins ; 68 / 80 ( 85 % ) ; ; Total virtual pins ; 0 ; ; UFM blocks ; 1 / 1 ( 100 % ) ; +---------------------------+-------------------------------------------------+ @@ -121,141 +128,166 @@ applicable agreement for further details. ; Number detected on machine ; 2 ; ; Maximum allowed ; 2 ; ; ; ; -; Average used ; 1.00 ; +; Average used ; 1.33 ; ; Maximum used ; 2 ; ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; -; Processor 2 ; < 0.1% ; +; Processor 2 ; 33.3% ; +----------------------------+-------------+ -+---------------------------------------------------+ -; Fitter Resource Usage Summary ; -+--------------------------------+------------------+ -; Resource ; Usage ; -+--------------------------------+------------------+ -; Total logic elements ; Not available ; -; ; ; -; Total LABs ; Not available ; -; Logic elements in carry chains ; 62 ; -; Virtual pins ; 0 ; -; I/O pins ; 69 / 80 ( 86 % ) ; -; -- Clock pins ; 0 / 4 ( 0 % ) ; -; ; ; -; Global signals ; 1 ; -; UFM blocks ; 1 / 1 ( 100 % ) ; -; Global clocks ; 1 / 4 ( 25 % ) ; -; JTAGs ; 0 / 1 ( 0 % ) ; -; Maximum fan-out ; 103 ; -; Highest non-global fan-out ; 36 ; -; Total fan-out ; 980 ; -; Average fan-out ; 3.09 ; -+--------------------------------+------------------+ ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin. -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Input Pins ; -+---------+------------+----------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+ -; Name ; Pin # ; I/O Bank ; Combinational Fan-Out ; Registered Fan-Out ; Global ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Location assigned by ; -+---------+------------+----------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+ -; C25M ; Unassigned ; -- ; 103 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; -; MISO ; Unassigned ; -- ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; -; PHI0 ; Unassigned ; -- ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; -; RA[0] ; Unassigned ; -- ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; -; RA[10] ; Unassigned ; -- ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; -; RA[11] ; Unassigned ; -- ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; -; RA[12] ; Unassigned ; -- ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; -; RA[13] ; Unassigned ; -- ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; -; RA[14] ; Unassigned ; -- ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; -; RA[15] ; Unassigned ; -- ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; -; RA[1] ; Unassigned ; -- ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; -; RA[2] ; Unassigned ; -- ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; -; RA[3] ; Unassigned ; -- ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; -; RA[4] ; Unassigned ; -- ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; -; RA[5] ; Unassigned ; -- ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; -; RA[6] ; Unassigned ; -- ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; -; RA[7] ; Unassigned ; -- ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; -; RA[8] ; Unassigned ; -- ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; -; RA[9] ; Unassigned ; -- ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; -; nBOD ; Unassigned ; -- ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; -; nDEVSEL ; Unassigned ; -- ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; -; nIOSEL ; Unassigned ; -- ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; -; nIOSTRB ; Unassigned ; -- ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; -; nRES ; Unassigned ; -- ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; -; nWE ; Unassigned ; -- ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; -+---------+------------+----------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+ ++------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++---------------------------------------------+--------------------+ +; Resource ; Usage ; ++---------------------------------------------+--------------------+ +; Total logic elements ; 235 / 240 ( 98 % ) ; +; -- Combinational with no register ; 139 ; +; -- Register only ; 4 ; +; -- Combinational with a register ; 92 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 96 ; +; -- 3 input functions ; 45 ; +; -- 2 input functions ; 80 ; +; -- 1 input functions ; 9 ; +; -- 0 input functions ; 1 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 177 ; +; -- arithmetic mode ; 58 ; +; -- qfbk mode ; 18 ; +; -- register cascade mode ; 0 ; +; -- synchronous clear/load mode ; 45 ; +; -- asynchronous clear/load mode ; 0 ; +; ; ; +; Total registers ; 96 / 240 ( 40 % ) ; +; Total LABs ; 24 / 24 ( 100 % ) ; +; Logic elements in carry chains ; 62 ; +; Virtual pins ; 0 ; +; I/O pins ; 68 / 80 ( 85 % ) ; +; -- Clock pins ; 4 / 4 ( 100 % ) ; +; ; ; +; Global signals ; 1 ; +; UFM blocks ; 1 / 1 ( 100 % ) ; +; Global clocks ; 1 / 4 ( 25 % ) ; +; JTAGs ; 0 / 1 ( 0 % ) ; +; Average interconnect usage (total/H/V) ; 34% / 42% / 26% ; +; Peak interconnect usage (total/H/V) ; 34% / 42% / 26% ; +; Maximum fan-out ; 96 ; +; Highest non-global fan-out ; 31 ; +; Total fan-out ; 948 ; +; Average fan-out ; 3.12 ; ++---------------------------------------------+--------------------+ -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Output Pins ; -+---------+------------+----------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ -; Name ; Pin # ; I/O Bank ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ; -+---------+------------+----------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ -; DQMH ; Unassigned ; -- ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; - ; - ; -; DQML ; Unassigned ; -- ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; - ; - ; -; FCK ; Unassigned ; -- ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; - ; - ; -; MOSI ; Unassigned ; -- ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; - ; - ; -; RAdir ; Unassigned ; -- ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; - ; - ; -; RCKE ; Unassigned ; -- ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; - ; - ; -; RDdir ; Unassigned ; -- ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; - ; - ; -; SA[0] ; Unassigned ; -- ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; - ; - ; -; SA[10] ; Unassigned ; -- ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; - ; - ; -; SA[11] ; Unassigned ; -- ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; - ; - ; -; SA[12] ; Unassigned ; -- ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; - ; - ; -; SA[1] ; Unassigned ; -- ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; - ; - ; -; SA[2] ; Unassigned ; -- ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; - ; - ; -; SA[3] ; Unassigned ; -- ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; - ; - ; -; SA[4] ; Unassigned ; -- ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; - ; - ; -; SA[5] ; Unassigned ; -- ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; - ; - ; -; SA[6] ; Unassigned ; -- ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; - ; - ; -; SA[7] ; Unassigned ; -- ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; - ; - ; -; SA[8] ; Unassigned ; -- ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; - ; - ; -; SA[9] ; Unassigned ; -- ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; - ; - ; -; SBA[0] ; Unassigned ; -- ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; - ; - ; -; SBA[1] ; Unassigned ; -- ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; - ; - ; -; nCAS ; Unassigned ; -- ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; - ; - ; -; nFCS ; Unassigned ; -- ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; - ; - ; -; nRAS ; Unassigned ; -- ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; - ; - ; -; nRCS ; Unassigned ; -- ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; - ; - ; -; nRESout ; Unassigned ; -- ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; - ; - ; -; nSWE ; Unassigned ; -- ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; - ; - ; -+---------+------------+----------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Location assigned by ; ++---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+ +; C25M ; 14 ; 1 ; 1 ; 2 ; 0 ; 96 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; +; MISO ; 33 ; 1 ; 3 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; +; PHI0 ; 12 ; 1 ; 1 ; 3 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; +; RA[0] ; 30 ; 1 ; 3 ; 0 ; 3 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; +; RA[10] ; 16 ; 1 ; 1 ; 2 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; +; RA[11] ; 20 ; 1 ; 1 ; 1 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; +; RA[12] ; 1 ; 2 ; 2 ; 5 ; 3 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; +; RA[13] ; 97 ; 2 ; 3 ; 5 ; 3 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; +; RA[14] ; 36 ; 1 ; 4 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; +; RA[15] ; 95 ; 2 ; 3 ; 5 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; +; RA[1] ; 92 ; 2 ; 3 ; 5 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; +; RA[2] ; 35 ; 1 ; 3 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; +; RA[3] ; 96 ; 2 ; 3 ; 5 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; +; RA[4] ; 84 ; 2 ; 6 ; 5 ; 3 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; +; RA[5] ; 81 ; 2 ; 6 ; 5 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; +; RA[6] ; 82 ; 2 ; 6 ; 5 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; +; RA[7] ; 34 ; 1 ; 3 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; +; RA[8] ; 15 ; 1 ; 1 ; 2 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; +; RA[9] ; 17 ; 1 ; 1 ; 2 ; 3 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; +; nDEVSEL ; 77 ; 2 ; 7 ; 5 ; 2 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; +; nIOSEL ; 71 ; 2 ; 8 ; 4 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; +; nIOSTRB ; 72 ; 2 ; 8 ; 4 ; 2 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; +; nRES ; 64 ; 2 ; 8 ; 3 ; 4 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; +; nWE ; 8 ; 1 ; 1 ; 3 ; 2 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; ++---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+ -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Bidir Pins ; -+-------+------------+----------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ -; Name ; Pin # ; I/O Bank ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ; -+-------+------------+----------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ -; RD[0] ; Unassigned ; -- ; 4 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; comb~2 (inverted) ; - ; -; RD[1] ; Unassigned ; -- ; 4 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; comb~2 (inverted) ; - ; -; RD[2] ; Unassigned ; -- ; 3 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; comb~2 (inverted) ; - ; -; RD[3] ; Unassigned ; -- ; 3 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; comb~2 (inverted) ; - ; -; RD[4] ; Unassigned ; -- ; 3 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; comb~2 (inverted) ; - ; -; RD[5] ; Unassigned ; -- ; 3 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; comb~2 (inverted) ; - ; -; RD[6] ; Unassigned ; -- ; 3 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; comb~2 (inverted) ; - ; -; RD[7] ; Unassigned ; -- ; 4 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; comb~2 (inverted) ; - ; -; SD[0] ; Unassigned ; -- ; 0 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; SDOE ; - ; -; SD[1] ; Unassigned ; -- ; 0 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; SDOE ; - ; -; SD[2] ; Unassigned ; -- ; 0 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; SDOE ; - ; -; SD[3] ; Unassigned ; -- ; 0 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; SDOE ; - ; -; SD[4] ; Unassigned ; -- ; 0 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; SDOE ; - ; -; SD[5] ; Unassigned ; -- ; 0 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; SDOE ; - ; -; SD[6] ; Unassigned ; -- ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; SDOE ; - ; -; SD[7] ; Unassigned ; -- ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Default ; no ; Fitter ; 10 pF ; SDOE ; - ; -+-------+------------+----------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ; ++---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ +; DQMH ; 75 ; 2 ; 7 ; 5 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; Fitter ; 10 pF ; - ; - ; +; DQML ; 76 ; 2 ; 7 ; 5 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; Fitter ; 10 pF ; - ; - ; +; FCK ; 29 ; 1 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; Fitter ; 10 pF ; - ; - ; +; MOSI ; 28 ; 1 ; 2 ; 0 ; 1 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; RAdir ; 78 ; 2 ; 7 ; 5 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; RCKE ; 66 ; 2 ; 8 ; 3 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; RDdir ; 100 ; 2 ; 2 ; 5 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; SA[0] ; 73 ; 2 ; 8 ; 4 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; SA[10] ; 62 ; 2 ; 8 ; 2 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; SA[11] ; 88 ; 2 ; 5 ; 5 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; SA[12] ; 70 ; 2 ; 8 ; 4 ; 4 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; SA[1] ; 21 ; 1 ; 1 ; 1 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; SA[2] ; 61 ; 2 ; 8 ; 2 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; SA[3] ; 39 ; 1 ; 5 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; SA[4] ; 74 ; 2 ; 8 ; 4 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; SA[5] ; 85 ; 2 ; 5 ; 5 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; SA[6] ; 83 ; 2 ; 6 ; 5 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; Fitter ; 10 pF ; - ; - ; +; SA[7] ; 19 ; 1 ; 1 ; 1 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; SA[8] ; 18 ; 1 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; SA[9] ; 67 ; 2 ; 8 ; 3 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; SBA[0] ; 43 ; 1 ; 6 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; SBA[1] ; 86 ; 2 ; 5 ; 5 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; nCAS ; 58 ; 2 ; 8 ; 2 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; nFCS ; 38 ; 1 ; 4 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; Fitter ; 10 pF ; - ; - ; +; nRAS ; 68 ; 2 ; 8 ; 3 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; nRCS ; 57 ; 2 ; 8 ; 2 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; Fitter ; 10 pF ; - ; - ; +; nRESout ; 37 ; 1 ; 4 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; nSWE ; 69 ; 2 ; 8 ; 3 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; ++---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ -+----------------------------------------------------------+ -; I/O Bank Usage ; -+----------+----------------+---------------+--------------+ -; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; -+----------+----------------+---------------+--------------+ -; 1 ; 0 / 38 ( 0 % ) ; 3.3V ; -- ; -; 2 ; 0 / 42 ( 0 % ) ; 3.3V ; -- ; -; Unknown ; 69 ; -- ; ; -+----------+----------------+---------------+--------------+ ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Bidir Pins ; ++-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ; ++-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ +; RD[0] ; 2 ; 1 ; 1 ; 4 ; 0 ; 4 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; comb~2 (inverted) ; - ; +; RD[1] ; 7 ; 1 ; 1 ; 3 ; 1 ; 4 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; comb~2 (inverted) ; - ; +; RD[2] ; 98 ; 2 ; 2 ; 5 ; 0 ; 3 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; comb~2 (inverted) ; - ; +; RD[3] ; 3 ; 1 ; 1 ; 4 ; 1 ; 3 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; comb~2 (inverted) ; - ; +; RD[4] ; 5 ; 1 ; 1 ; 4 ; 3 ; 3 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; comb~2 (inverted) ; - ; +; RD[5] ; 99 ; 2 ; 2 ; 5 ; 1 ; 3 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; comb~2 (inverted) ; - ; +; RD[6] ; 4 ; 1 ; 1 ; 4 ; 2 ; 3 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; comb~2 (inverted) ; - ; +; RD[7] ; 6 ; 1 ; 1 ; 3 ; 0 ; 4 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; comb~2 (inverted) ; - ; +; SD[0] ; 42 ; 1 ; 5 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; SDOE ; - ; +; SD[1] ; 40 ; 1 ; 5 ; 0 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; SDOE ; - ; +; SD[2] ; 53 ; 2 ; 8 ; 1 ; 3 ; 0 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; SDOE ; - ; +; SD[3] ; 51 ; 1 ; 7 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; SDOE ; - ; +; SD[4] ; 41 ; 1 ; 5 ; 0 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; SDOE ; - ; +; SD[5] ; 52 ; 2 ; 8 ; 1 ; 4 ; 0 ; 0 ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; SDOE ; - ; +; SD[6] ; 27 ; 1 ; 2 ; 0 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; Fitter ; 10 pF ; SDOE ; - ; +; SD[7] ; 26 ; 1 ; 2 ; 0 ; 3 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; Fitter ; 10 pF ; SDOE ; - ; ++-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ + + ++------------------------------------------------------------+ +; I/O Bank Usage ; ++----------+------------------+---------------+--------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; ++----------+------------------+---------------+--------------+ +; 1 ; 33 / 38 ( 87 % ) ; 3.3V ; -- ; +; 2 ; 35 / 42 ( 83 % ) ; 3.3V ; -- ; ++----------+------------------+---------------+--------------+ +------------------------------------------------------------------------------------------------------------------------------------------------+ @@ -263,49 +295,49 @@ applicable agreement for further details. +----------+------------+----------+----------------+--------+--------------+-----------+------------+-----------------+----------+--------------+ ; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; +----------+------------+----------+----------------+--------+--------------+-----------+------------+-----------------+----------+--------------+ -; 1 ; 83 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 2 ; 0 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 3 ; 1 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 4 ; 2 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 5 ; 3 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 6 ; 4 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 7 ; 5 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 8 ; 6 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 1 ; 83 ; 2 ; RA[12] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 2 ; 0 ; 1 ; RD[0] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 3 ; 1 ; 1 ; RD[3] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 4 ; 2 ; 1 ; RD[6] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 5 ; 3 ; 1 ; RD[4] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 6 ; 4 ; 1 ; RD[7] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 7 ; 5 ; 1 ; RD[1] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 8 ; 6 ; 1 ; nWE ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; ; 9 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; 10 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; ; 11 ; ; ; GNDINT ; gnd ; ; ; -- ; ; -- ; -- ; -; 12 ; 7 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 12 ; 7 ; 1 ; PHI0 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; ; 13 ; ; ; VCCINT ; power ; ; 2.5V/3.3V ; -- ; ; -- ; -- ; -; 14 ; 8 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 15 ; 9 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 16 ; 10 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 17 ; 11 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 18 ; 12 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 19 ; 13 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 20 ; 14 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 21 ; 15 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 14 ; 8 ; 1 ; C25M ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 15 ; 9 ; 1 ; RA[8] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 16 ; 10 ; 1 ; RA[10] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 17 ; 11 ; 1 ; RA[9] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 18 ; 12 ; 1 ; SA[8] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 19 ; 13 ; 1 ; SA[7] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 20 ; 14 ; 1 ; RA[11] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 21 ; 15 ; 1 ; SA[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; ; 22 ; 16 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ; ; 23 ; 17 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ; ; 24 ; 18 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ; ; 25 ; 19 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ; -; 26 ; 20 ; 1 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 27 ; 21 ; 1 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 28 ; 22 ; 1 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 29 ; 23 ; 1 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 30 ; 24 ; 1 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 26 ; 20 ; 1 ; SD[7] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 27 ; 21 ; 1 ; SD[6] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 28 ; 22 ; 1 ; MOSI ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 29 ; 23 ; 1 ; FCK ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 30 ; 24 ; 1 ; RA[0] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; ; 31 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; 32 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; -; 33 ; 25 ; 1 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 34 ; 26 ; 1 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 35 ; 27 ; 1 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 36 ; 28 ; 1 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 37 ; 29 ; 1 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 38 ; 30 ; 1 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 39 ; 31 ; 1 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 40 ; 32 ; 1 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 41 ; 33 ; 1 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 42 ; 34 ; 1 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 43 ; 35 ; 1 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 33 ; 25 ; 1 ; MISO ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 34 ; 26 ; 1 ; RA[7] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 35 ; 27 ; 1 ; RA[2] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 36 ; 28 ; 1 ; RA[14] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 37 ; 29 ; 1 ; nRESout ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 38 ; 30 ; 1 ; nFCS ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 39 ; 31 ; 1 ; SA[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 40 ; 32 ; 1 ; SD[1] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 41 ; 33 ; 1 ; SD[4] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 42 ; 34 ; 1 ; SD[0] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 43 ; 35 ; 1 ; SBA[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; ; 44 ; 36 ; 1 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; 45 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; 46 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; @@ -313,56 +345,56 @@ applicable agreement for further details. ; 48 ; 38 ; 1 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; 49 ; 39 ; 1 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; 50 ; 40 ; 1 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 51 ; 41 ; 1 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 52 ; 42 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 53 ; 43 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 51 ; 41 ; 1 ; SD[3] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 52 ; 42 ; 2 ; SD[5] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 53 ; 43 ; 2 ; SD[2] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; ; 54 ; 44 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; 55 ; 45 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; 56 ; 46 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 57 ; 47 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 58 ; 48 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 57 ; 47 ; 2 ; nRCS ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 58 ; 48 ; 2 ; nCAS ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; ; 59 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; 60 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; -; 61 ; 49 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 62 ; 50 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 61 ; 49 ; 2 ; SA[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 62 ; 50 ; 2 ; SA[10] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; ; 63 ; ; ; VCCINT ; power ; ; 2.5V/3.3V ; -- ; ; -- ; -- ; -; 64 ; 51 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 64 ; 51 ; 2 ; nRES ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; ; 65 ; ; ; GNDINT ; gnd ; ; ; -- ; ; -- ; -- ; -; 66 ; 52 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 67 ; 53 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 68 ; 54 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 69 ; 55 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 70 ; 56 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 71 ; 57 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 72 ; 58 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 73 ; 59 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 74 ; 60 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 75 ; 61 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 76 ; 62 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 77 ; 63 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 78 ; 64 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 66 ; 52 ; 2 ; RCKE ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 67 ; 53 ; 2 ; SA[9] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 68 ; 54 ; 2 ; nRAS ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 69 ; 55 ; 2 ; nSWE ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 70 ; 56 ; 2 ; SA[12] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 71 ; 57 ; 2 ; nIOSEL ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 72 ; 58 ; 2 ; nIOSTRB ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 73 ; 59 ; 2 ; SA[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 74 ; 60 ; 2 ; SA[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 75 ; 61 ; 2 ; DQMH ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 76 ; 62 ; 2 ; DQML ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 77 ; 63 ; 2 ; nDEVSEL ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 78 ; 64 ; 2 ; RAdir ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; ; 79 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; ; 80 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 81 ; 65 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 82 ; 66 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 83 ; 67 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 84 ; 68 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 85 ; 69 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 86 ; 70 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 81 ; 65 ; 2 ; RA[5] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 82 ; 66 ; 2 ; RA[6] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 83 ; 67 ; 2 ; SA[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 84 ; 68 ; 2 ; RA[4] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 85 ; 69 ; 2 ; SA[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 86 ; 70 ; 2 ; SBA[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; ; 87 ; 71 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 88 ; 72 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 88 ; 72 ; 2 ; SA[11] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; ; 89 ; 73 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; 90 ; 74 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; 91 ; 75 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 92 ; 76 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 92 ; 76 ; 2 ; RA[1] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; ; 93 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; ; 94 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 95 ; 77 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 96 ; 78 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 97 ; 79 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 98 ; 80 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 99 ; 81 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 100 ; 82 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 95 ; 77 ; 2 ; RA[15] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 96 ; 78 ; 2 ; RA[3] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 97 ; 79 ; 2 ; RA[13] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 98 ; 80 ; 2 ; RD[2] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 99 ; 81 ; 2 ; RD[5] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 100 ; 82 ; 2 ; RDdir ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +----------+------------+----------+----------------+--------+--------------+-----------+------------+-----------------+----------+--------------+ Note: Pin directions (input, output or bidir) are based on device operating in user mode. @@ -388,7 +420,7 @@ Note: User assignments will override these defaults. The user specified values a +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+ ; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ; +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+ -; |GR8RAM ; 247 (247) ; 103 ; 1 ; 69 ; 0 ; 144 (144) ; 0 (0) ; 103 (103) ; 62 (62) ; 27 (27) ; |GR8RAM ; work ; +; |GR8RAM ; 235 (235) ; 96 ; 1 ; 68 ; 0 ; 139 (139) ; 4 (4) ; 92 (92) ; 62 (62) ; 18 (18) ; |GR8RAM ; work ; ; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |GR8RAM|UFM:UFM_inst ; work ; ; |UFM_altufm_none_0ep:UFM_altufm_none_0ep_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |GR8RAM|UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component ; work ; +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+ @@ -400,31 +432,30 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +---------+----------+---------------+ ; Name ; Pin Type ; Pad to Core 0 ; +---------+----------+---------------+ -; PHI0 ; Input ; 0 ; -; nWE ; Input ; 0 ; -; nDEVSEL ; Input ; 0 ; -; nIOSTRB ; Input ; 0 ; -; nIOSEL ; Input ; 0 ; -; C25M ; Input ; 0 ; -; RA[1] ; Input ; 0 ; -; RA[10] ; Input ; 0 ; -; RA[2] ; Input ; 0 ; -; RA[11] ; Input ; 0 ; -; RA[3] ; Input ; 0 ; -; RA[4] ; Input ; 0 ; -; RA[5] ; Input ; 0 ; -; RA[6] ; Input ; 0 ; -; RA[7] ; Input ; 0 ; -; RA[8] ; Input ; 0 ; -; RA[9] ; Input ; 0 ; -; RA[0] ; Input ; 0 ; -; nRES ; Input ; 0 ; -; RA[14] ; Input ; 0 ; -; RA[15] ; Input ; 0 ; -; RA[12] ; Input ; 0 ; -; RA[13] ; Input ; 0 ; -; MISO ; Input ; 0 ; -; nBOD ; Input ; 0 ; +; PHI0 ; Input ; (1) ; +; nWE ; Input ; (1) ; +; nDEVSEL ; Input ; (1) ; +; nIOSTRB ; Input ; (1) ; +; nIOSEL ; Input ; (1) ; +; C25M ; Input ; (0) ; +; RA[1] ; Input ; (1) ; +; RA[10] ; Input ; (1) ; +; RA[2] ; Input ; (1) ; +; RA[11] ; Input ; (1) ; +; RA[3] ; Input ; (1) ; +; RA[4] ; Input ; (1) ; +; RA[5] ; Input ; (1) ; +; RA[6] ; Input ; (1) ; +; RA[7] ; Input ; (1) ; +; RA[8] ; Input ; (1) ; +; RA[9] ; Input ; (1) ; +; RA[0] ; Input ; (1) ; +; RA[14] ; Input ; (1) ; +; RA[15] ; Input ; (1) ; +; RA[12] ; Input ; (1) ; +; RA[13] ; Input ; (1) ; +; nRES ; Input ; (1) ; +; MISO ; Input ; (1) ; ; nRESout ; Output ; -- ; ; RAdir ; Output ; -- ; ; RDdir ; Output ; -- ; @@ -453,425 +484,569 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; nFCS ; Output ; -- ; ; FCK ; Output ; -- ; ; MOSI ; Output ; -- ; -; RD[0] ; Bidir ; 0 ; -; RD[1] ; Bidir ; 0 ; -; RD[2] ; Bidir ; 0 ; -; RD[3] ; Bidir ; 0 ; -; RD[4] ; Bidir ; 0 ; -; RD[5] ; Bidir ; 0 ; -; RD[6] ; Bidir ; 0 ; -; RD[7] ; Bidir ; 0 ; -; SD[0] ; Bidir ; 0 ; -; SD[1] ; Bidir ; 0 ; -; SD[2] ; Bidir ; 0 ; -; SD[3] ; Bidir ; 0 ; -; SD[4] ; Bidir ; 0 ; -; SD[5] ; Bidir ; 0 ; -; SD[6] ; Bidir ; 0 ; -; SD[7] ; Bidir ; 0 ; +; RD[0] ; Bidir ; (1) ; +; RD[1] ; Bidir ; (1) ; +; RD[2] ; Bidir ; (1) ; +; RD[3] ; Bidir ; (1) ; +; RD[4] ; Bidir ; (1) ; +; RD[5] ; Bidir ; (1) ; +; RD[6] ; Bidir ; (1) ; +; RD[7] ; Bidir ; (1) ; +; SD[0] ; Bidir ; (0) ; +; SD[1] ; Bidir ; (0) ; +; SD[2] ; Bidir ; (0) ; +; SD[3] ; Bidir ; (0) ; +; SD[4] ; Bidir ; (0) ; +; SD[5] ; Bidir ; (0) ; +; SD[6] ; Bidir ; (0) ; +; SD[7] ; Bidir ; (0) ; +---------+----------+---------------+ -+-------------------------------------------------------------------------------------------------------+ -; Control Signals ; -+-------------+------------+---------+---------------+--------+----------------------+------------------+ -; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; -+-------------+------------+---------+---------------+--------+----------------------+------------------+ -; ARCLK~6 ; Unassigned ; 2 ; Clock enable ; no ; -- ; -- ; -; Addr[0]~4 ; Unassigned ; 8 ; Clock enable ; no ; -- ; -- ; -; Addr[20]~16 ; Unassigned ; 7 ; Clock enable ; no ; -- ; -- ; -; Addr[9]~2 ; Unassigned ; 8 ; Clock enable ; no ; -- ; -- ; -; Bank[0]~1 ; Unassigned ; 2 ; Clock enable ; no ; -- ; -- ; -; C25M ; Unassigned ; 103 ; Clock ; yes ; Global Clock ; Not Available ; -; DRShift~0 ; Unassigned ; 2 ; Clock enable ; no ; -- ; -- ; -; Equal0~3 ; Unassigned ; 2 ; Clock enable ; no ; -- ; -- ; -; MOSIOE ; Unassigned ; 3 ; Output enable ; no ; -- ; -- ; -; MOSIout~4 ; Unassigned ; 2 ; Clock enable ; no ; -- ; -- ; -; PSStart~1 ; Unassigned ; 18 ; Clock enable ; no ; -- ; -- ; -; SDOE ; Unassigned ; 8 ; Output enable ; no ; -- ; -- ; -; always18~0 ; Unassigned ; 2 ; Clock enable ; no ; -- ; -- ; -; nRESr ; Unassigned ; 36 ; Sync. clear ; no ; -- ; -- ; -+-------------+------------+---------+---------------+--------+----------------------+------------------+ ++--------------------------------------------------------------------------------------------------------+ +; Control Signals ; ++-------------+-------------+---------+---------------+--------+----------------------+------------------+ +; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; ++-------------+-------------+---------+---------------+--------+----------------------+------------------+ +; ARCLK~8 ; LC_X7_Y1_N9 ; 2 ; Clock enable ; no ; -- ; -- ; +; Addr[19]~16 ; LC_X4_Y3_N1 ; 7 ; Clock enable ; no ; -- ; -- ; +; Addr[4]~4 ; LC_X4_Y3_N2 ; 8 ; Clock enable ; no ; -- ; -- ; +; Addr[8]~2 ; LC_X4_Y3_N7 ; 8 ; Clock enable ; no ; -- ; -- ; +; Bank[1]~1 ; LC_X2_Y3_N2 ; 2 ; Clock enable ; no ; -- ; -- ; +; C25M ; PIN_14 ; 96 ; Clock ; yes ; Global Clock ; GCLK1 ; +; DRCLK~3 ; LC_X7_Y1_N5 ; 2 ; Clock enable ; no ; -- ; -- ; +; MOSIOE ; LC_X3_Y1_N9 ; 3 ; Output enable ; no ; -- ; -- ; +; PSStart~1 ; LC_X7_Y3_N4 ; 16 ; Clock enable ; no ; -- ; -- ; +; SDOE ; LC_X2_Y1_N0 ; 8 ; Output enable ; no ; -- ; -- ; +; always17~0 ; LC_X2_Y1_N4 ; 2 ; Clock enable ; no ; -- ; -- ; +; nRESr ; LC_X7_Y3_N1 ; 31 ; Sync. clear ; no ; -- ; -- ; ++-------------+-------------+---------+---------------+--------+----------------------+------------------+ -+-----------------------------------------------------------------------+ -; Global & Other Fast Signals ; -+------+------------+---------+----------------------+------------------+ -; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; -+------+------------+---------+----------------------+------------------+ -; C25M ; Unassigned ; 103 ; Global Clock ; Not Available ; -+------+------------+---------+----------------------+------------------+ ++---------------------------------------------------------------------+ +; Global & Other Fast Signals ; ++------+----------+---------+----------------------+------------------+ +; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; ++------+----------+---------+----------------------+------------------+ +; C25M ; PIN_14 ; 96 ; Global Clock ; GCLK1 ; ++------+----------+---------+----------------------+------------------+ +---------------------------------+ ; Non-Global High Fan-Out Signals ; -+--------------+------------------+ -; Name ; Fan-Out ; -+--------------+------------------+ -; nRESr ; 36 ; -; Amux[1] ; 19 ; -; RAMSpecSEL~4 ; 18 ; -; PSStart~1 ; 18 ; -; Amux[0] ; 18 ; -; Amux[2] ; 17 ; -; PS[0] ; 16 ; -; RAcur[0] ; 14 ; -; PS[2] ; 13 ; -; PS[1] ; 13 ; -; Addr[20]~10 ; 11 ; -; Addr[0]~3 ; 11 ; -; always11~0 ; 11 ; -; InitActv ; 11 ; -; LS[6] ; 11 ; -; LS[1] ; 10 ; -; comb~2 ; 9 ; -; Addr[0]~4 ; 8 ; -; Addr[9]~2 ; 8 ; -; SDOE ; 8 ; -; LS[5] ; 8 ; -; LS[4] ; 8 ; -; LS[3] ; 8 ; -; Addr[20]~16 ; 7 ; -; RAMSpecSEL~1 ; 7 ; -; nWEcur ; 6 ; -; RAMSpecSEL~3 ; 6 ; -; Equal7~0 ; 6 ; -; LS[2] ; 6 ; -; LS[7] ; 6 ; -; SetLoaded ; 5 ; -; Mux1~0 ; 5 ; -; LS[0] ; 5 ; -; LS[15] ; 5 ; -; LS[14] ; 5 ; -; LS[13] ; 5 ; -; LS[12] ; 5 ; -; Equal45~1 ; 5 ; -; RD[7]~7 ; 4 ; -; RD[1]~1 ; 4 ; -; RD[0]~0 ; 4 ; -; Addr[22] ; 4 ; -; Addr[21] ; 4 ; -; Addr[20] ; 4 ; -; Addr[19] ; 4 ; -; Addr[18] ; 4 ; -; Addr[17] ; 4 ; -; Addr[16] ; 4 ; -; RACr ; 4 ; -; RAcur[1] ; 4 ; -; nBODf ; 4 ; -; LS[17] ; 4 ; -; Addr[7] ; 4 ; -; Addr[15] ; 4 ; -; RD[6]~6 ; 3 ; -; RD[5]~5 ; 3 ; -; RD[4]~4 ; 3 ; -; RD[3]~3 ; 3 ; -; RD[2]~2 ; 3 ; -; ARCLK~4 ; 3 ; -; Equal39~0 ; 3 ; -; MOSIOE ; 3 ; -; Equal12~0 ; 3 ; -; always22~1 ; 3 ; -; RefReqd ; 3 ; -; always11~1 ; 3 ; -; RAcur[2] ; 3 ; -; RAcur[3] ; 3 ; -; always6~2 ; 3 ; -; always6~1 ; 3 ; -; Equal0~2 ; 3 ; -; LS[8] ; 3 ; -; LS[11] ; 3 ; -; LS[10] ; 3 ; -; LS[9] ; 3 ; -; LS[16] ; 3 ; -; Equal44~0 ; 3 ; -; Equal0~0 ; 3 ; -; DRCLK~0 ; 3 ; -; Addr[9] ; 3 ; -; Addr[8] ; 3 ; -; Addr[14] ; 3 ; -; Addr[13] ; 3 ; -; Addr[12] ; 3 ; -; Addr[11] ; 3 ; -; Addr[10] ; 3 ; -; REGEN ; 3 ; -; nIOSEL ; 2 ; -; nIOSTRB ; 2 ; -; nDEVSEL ; 2 ; -; nWE ; 2 ; -; PHI0 ; 2 ; -; always18~0 ; 2 ; -; MOSIout~4 ; 2 ; -; SDRAMActv ; 2 ; -; Equal0~3 ; 2 ; -; Equal44~1 ; 2 ; -; ARCLK~6 ; 2 ; -; DRShift~0 ; 2 ; -; DRCLK~2 ; 2 ; -; ARCLK~1 ; 2 ; -; MOSIout ; 2 ; -; FCKEN ; 2 ; -; FCS~1 ; 2 ; -; FCKEN~2 ; 2 ; -; Equal12~1 ; 2 ; -; Mux4~0 ; 2 ; -; Mux1~3 ; 2 ; -; always22~0 ; 2 ; -; Mux1~1 ; 2 ; -; Bank[0]~1 ; 2 ; -; DEVSELr ; 2 ; -; RAcur[7] ; 2 ; -; RAMSpecSEL~2 ; 2 ; -; RAcur[10] ; 2 ; -; always10~3 ; 2 ; -; always10~0 ; 2 ; -; RAMSpecSEL~0 ; 2 ; -; IOSELr ; 2 ; -; always6~0 ; 2 ; -; ARCLK~0 ; 2 ; -; SDRAMActv~0 ; 2 ; -; InitIntr ; 2 ; -; Equal2~3 ; 2 ; -; Equal2~2 ; 2 ; -; FCS ; 2 ; -; RCKE~reg0 ; 2 ; -; DQML~1 ; 2 ; -; DQML~0 ; 2 ; -; Addr[0] ; 2 ; -; RAcur[9] ; 2 ; -; RAcur[8] ; 2 ; -; Addr[6] ; 2 ; -; Addr[5] ; 2 ; -; Addr[4] ; 2 ; -; Addr[3] ; 2 ; -; Addr[2] ; 2 ; -; Addr[1] ; 2 ; -; IOROMEN ; 2 ; -; nRESout~reg0 ; 2 ; -; nBOD ; 1 ; -; MISO ; 1 ; -; RA[13] ; 1 ; -; RA[12] ; 1 ; -; RA[15] ; 1 ; -; RA[14] ; 1 ; -; nRES ; 1 ; -; RA[0] ; 1 ; -; RA[9] ; 1 ; -; RA[8] ; 1 ; -; RA[7] ; 1 ; -; RA[6] ; 1 ; -; RA[5] ; 1 ; -; RA[4] ; 1 ; -; RA[3] ; 1 ; -; RA[11] ; 1 ; -; RA[2] ; 1 ; -; RA[10] ; 1 ; -; RA[1] ; 1 ; -; ~GND ; 1 ; -; FCKEN~4 ; 1 ; -; WRD[6] ; 1 ; -; Equal39~1 ; 1 ; -; MOSIout~2 ; 1 ; -; MOSIout~1 ; 1 ; -; MOSIout~0 ; 1 ; -; Equal44~2 ; 1 ; -; DEVSELr0 ; 1 ; -; IOSTRBr0 ; 1 ; -; IOSELr0 ; 1 ; -; ARCLK~3 ; 1 ; -; ARCLK~2 ; 1 ; -; DRShift~1 ; 1 ; -; FCS~0 ; 1 ; -; Mux0~2 ; 1 ; -; Mux0~1 ; 1 ; -; Mux0~0 ; 1 ; -; Add1~112 ; 1 ; -; Add1~110 ; 1 ; -; Mux3~0 ; 1 ; -; Mux1~5 ; 1 ; -; Mux1~2 ; 1 ; -; Add1~105 ; 1 ; -; Addr~29 ; 1 ; -; Add2~70 ; 1 ; -; Add3~30 ; 1 ; -; Add1~102 ; 1 ; -; Add1~100 ; 1 ; -; Addr~27 ; 1 ; -; Add3~27 ; 1 ; -; Add3~25 ; 1 ; -; Add2~67 ; 1 ; -; Add2~65 ; 1 ; -; Add1~97 ; 1 ; -; Add1~95 ; 1 ; -; Addr~25 ; 1 ; -; Add2~62 ; 1 ; -; Add2~60 ; 1 ; -; Add3~22 ; 1 ; -; Add3~20 ; 1 ; -; Add1~92 ; 1 ; -; Add1~90 ; 1 ; -; Addr~23 ; 1 ; -; Add3~17 ; 1 ; -; Add3~15 ; 1 ; -; Add2~57 ; 1 ; -; Add2~55 ; 1 ; -; Add1~87 ; 1 ; -; Add1~85 ; 1 ; -; Addr~21 ; 1 ; -; Add2~52 ; 1 ; -; Add2~50 ; 1 ; -; Add3~12 ; 1 ; -; Add3~10 ; 1 ; -; Add1~82 ; 1 ; -; Add1~80 ; 1 ; -; Addr~20 ; 1 ; -; Add2~47 ; 1 ; -; Add2~45 ; 1 ; -; Add1~77 ; 1 ; -; Add1~75 ; 1 ; -; Addr~18 ; 1 ; -; Add3~7 ; 1 ; -; Add3~5 ; 1 ; -; Add2~42 ; 1 ; -; Add2~40 ; 1 ; -; Add1~72 ; 1 ; -; Add1~70 ; 1 ; -; Addr~17 ; 1 ; -; Add2~37 ; 1 ; -; Add2~35 ; 1 ; -; Addr[20]~15 ; 1 ; -; Addr[20]~14 ; 1 ; -; Addr[20]~13 ; 1 ; -; Add1~67 ; 1 ; -; Add1~65 ; 1 ; -; Addr~11 ; 1 ; -; Add2~32 ; 1 ; -; Add2~30 ; 1 ; -; Add3~2 ; 1 ; -; Add3~0 ; 1 ; -; Add1~62 ; 1 ; -; Add1~60 ; 1 ; -; Add1~57 ; 1 ; -; Add1~55 ; 1 ; -; Addr~9 ; 1 ; -; Add2~27 ; 1 ; -; Add2~25 ; 1 ; -; Add1~52 ; 1 ; -; Add1~50 ; 1 ; -; Add1~47 ; 1 ; -; Add1~45 ; 1 ; -; Addr~8 ; 1 ; -; Add2~22 ; 1 ; -; Add2~20 ; 1 ; -; Add1~42 ; 1 ; -; Add1~40 ; 1 ; -; Add1~37 ; 1 ; -; Add1~35 ; 1 ; -; Add1~32 ; 1 ; -; Add1~30 ; 1 ; -; Addr~7 ; 1 ; -; Add2~17 ; 1 ; -; Add2~15 ; 1 ; -; Add1~27 ; 1 ; -; Add1~25 ; 1 ; -; Add1~22 ; 1 ; -; Add1~20 ; 1 ; -; Addr~6 ; 1 ; -; Add2~12 ; 1 ; -; Add2~10 ; 1 ; -; Add1~17 ; 1 ; -; Add1~15 ; 1 ; -; Add1~12 ; 1 ; -; Add1~10 ; 1 ; -; Addr~5 ; 1 ; -; Add2~7 ; 1 ; -; Add2~5 ; 1 ; -; Add1~7 ; 1 ; -; Add1~5 ; 1 ; -; Addr[9]~1 ; 1 ; -; Add1~2 ; 1 ; -; Add1~0 ; 1 ; -; Addr~0 ; 1 ; -; Add2~2 ; 1 ; -; Add2~0 ; 1 ; -; PHI0r1 ; 1 ; -; PSStart~0 ; 1 ; -; ROMSpecRD ; 1 ; -; RAcur[4] ; 1 ; -; always10~2 ; 1 ; -; always10~1 ; 1 ; -; Equal0~1 ; 1 ; -; LS[6]~33 ; 1 ; -; Equal2~1 ; 1 ; -; LS[8]~31 ; 1 ; -; Equal2~0 ; 1 ; -; LS[11]~29 ; 1 ; -; LS[10]~27 ; 1 ; -; LS[9]~25 ; 1 ; -; LS[16]~23 ; 1 ; -; LS[2]~21 ; 1 ; -; LS[5]~19 ; 1 ; -; LS[4]~17 ; 1 ; -; LS[7]~15 ; 1 ; -; LS[15]~13 ; 1 ; -; LS[14]~11 ; 1 ; -; LS[13]~9 ; 1 ; -; LS[12]~7 ; 1 ; -; LS[1]~3 ; 1 ; -; ARShift ; 1 ; -; ARCLK ; 1 ; -; DRShift ; 1 ; -; DRCLK ; 1 ; -; FCK~reg0 ; 1 ; -; DQMH~0 ; 1 ; -; DQML~2 ; 1 ; -; LS[3]~1 ; 1 ; -; nSWE~reg0 ; 1 ; -; nCAS~reg0 ; 1 ; -; nRAS~reg0 ; 1 ; -; nRCS~reg0 ; 1 ; -; SA~25 ; 1 ; -; SA~24 ; 1 ; -; SA~23 ; 1 ; -; SA~22 ; 1 ; -; SA~21 ; 1 ; -; SA~20 ; 1 ; -; SA~19 ; 1 ; -; SA~18 ; 1 ; -; SA~17 ; 1 ; -; SA~16 ; 1 ; -; SA~15 ; 1 ; -; RAcur[6] ; 1 ; -; SA~14 ; 1 ; -; SA~13 ; 1 ; -; RAcur[5] ; 1 ; -; SA~12 ; 1 ; -; nBODr0 ; 1 ; -; SA~11 ; 1 ; -; SA~10 ; 1 ; -; SA~9 ; 1 ; -; Bank[1] ; 1 ; -; nBODr ; 1 ; -; SA~8 ; 1 ; -; SA~7 ; 1 ; -; SA~6 ; 1 ; -; Bank[0] ; 1 ; -; WRD[7] ; 1 ; -; SA~5 ; 1 ; -; SA~4 ; 1 ; -; RAcur[11] ; 1 ; -; SA~3 ; 1 ; -; PHI0r0 ; 1 ; -; SA~2 ; 1 ; -; SA~1 ; 1 ; -; SA~0 ; 1 ; -; nBODf0 ; 1 ; -; Equal45~0 ; 1 ; -; nRESr0 ; 1 ; -; comb~1 ; 1 ; -; PHI0r2 ; 1 ; -; comb~0 ; 1 ; -+--------------+------------------+ ++-------------------+-------------+ +; Name ; Fan-Out ; ++-------------------+-------------+ +; nRESr ; 31 ; +; RAMSpecSEL~4 ; 19 ; +; Amux[1] ; 19 ; +; Amux[0] ; 18 ; +; Amux[2] ; 17 ; +; PSStart~1 ; 16 ; +; PS[1] ; 15 ; +; PS[0] ; 15 ; +; RAcur[0] ; 14 ; +; PS[2] ; 12 ; +; Addr[19]~10 ; 11 ; +; Addr[4]~3 ; 11 ; +; always10~0 ; 11 ; +; LS[1] ; 10 ; +; LS[4] ; 9 ; +; comb~2 ; 9 ; +; SDOE ; 8 ; +; Addr[4]~4 ; 8 ; +; Addr[8]~2 ; 8 ; +; LS[6] ; 8 ; +; LS[5] ; 8 ; +; nRESout~reg0 ; 8 ; +; Addr[19]~16 ; 7 ; +; LS[3] ; 7 ; +; RAMSpecSEL~1 ; 6 ; +; Equal5~0 ; 6 ; +; SetLoaded ; 5 ; +; Add1~112 ; 5 ; +; Add2~47 ; 5 ; +; nWEcur ; 5 ; +; Add1~57 ; 5 ; +; Add2~22 ; 5 ; +; Add1~42 ; 5 ; +; RAMSpecSEL~3 ; 5 ; +; Add1~2 ; 5 ; +; LS[8]~29 ; 5 ; +; LS[15] ; 5 ; +; LS[14] ; 5 ; +; LS[13] ; 5 ; +; LS[12] ; 5 ; +; LS[2] ; 5 ; +; LS[3]~1 ; 5 ; +; Equal43~1 ; 5 ; +; RD[7]~7 ; 4 ; +; RD[1]~1 ; 4 ; +; RD[0]~0 ; 4 ; +; Equal10~0 ; 4 ; +; Addr[22] ; 4 ; +; Addr[21] ; 4 ; +; Addr[20] ; 4 ; +; Addr[19] ; 4 ; +; Addr[18] ; 4 ; +; Addr[17] ; 4 ; +; Addr[16] ; 4 ; +; RAcur[1] ; 4 ; +; LS[13]~21 ; 4 ; +; LS[0] ; 4 ; +; Addr[7] ; 4 ; +; Addr[15] ; 4 ; +; RD[6]~6 ; 3 ; +; RD[5]~5 ; 3 ; +; RD[4]~4 ; 3 ; +; RD[3]~3 ; 3 ; +; RD[2]~2 ; 3 ; +; ARCLK~6 ; 3 ; +; MOSIOE ; 3 ; +; Mux0~0 ; 3 ; +; Add3~17 ; 3 ; +; Add2~57 ; 3 ; +; always10~1 ; 3 ; +; RAcur[2] ; 3 ; +; RAcur[3] ; 3 ; +; RACr ; 3 ; +; LS[10] ; 3 ; +; LS[9] ; 3 ; +; LS[8] ; 3 ; +; LS[7] ; 3 ; +; DRCLK~0 ; 3 ; +; ARCLK~0 ; 3 ; +; LS[11] ; 3 ; +; LS[17] ; 3 ; +; LS[16] ; 3 ; +; Addr[9] ; 3 ; +; Addr[8] ; 3 ; +; Addr[14] ; 3 ; +; Addr[13] ; 3 ; +; Addr[12] ; 3 ; +; Addr[11] ; 3 ; +; Addr[10] ; 3 ; +; REGEN ; 3 ; +; nIOSEL ; 2 ; +; nIOSTRB ; 2 ; +; nDEVSEL ; 2 ; +; nWE ; 2 ; +; PHI0 ; 2 ; +; always17~0 ; 2 ; +; ARCLK~8 ; 2 ; +; DRCLK~3 ; 2 ; +; DRCLK~2 ; 2 ; +; ARCLK~3 ; 2 ; +; MOSIout ; 2 ; +; FCKEN ; 2 ; +; Equal12~0 ; 2 ; +; FCS~0 ; 2 ; +; Equal10~1 ; 2 ; +; MOSIout~1 ; 2 ; +; ARCLK~2 ; 2 ; +; Mux0~4 ; 2 ; +; Mux0~3 ; 2 ; +; Mux2~0 ; 2 ; +; RefReqd ; 2 ; +; Add1~97 ; 2 ; +; Bank[1]~1 ; 2 ; +; DEVSELr ; 2 ; +; RAcur[7] ; 2 ; +; RAMSpecSEL~2 ; 2 ; +; ROMSpecRD ; 2 ; +; RAcur[10] ; 2 ; +; always9~3 ; 2 ; +; always9~0 ; 2 ; +; RAMSpecSEL~0 ; 2 ; +; IOSELr ; 2 ; +; Equal0~3 ; 2 ; +; Equal0~1 ; 2 ; +; FCS ; 2 ; +; RCKE~reg0 ; 2 ; +; DQML~1 ; 2 ; +; DQML~0 ; 2 ; +; Addr[0] ; 2 ; +; RAcur[9] ; 2 ; +; RAcur[8] ; 2 ; +; Addr[6] ; 2 ; +; Addr[5] ; 2 ; +; Addr[4] ; 2 ; +; Addr[3] ; 2 ; +; Addr[2] ; 2 ; +; Addr[1] ; 2 ; +; IOROMEN ; 2 ; +; MISO ; 1 ; +; nRES ; 1 ; +; RA[13] ; 1 ; +; RA[12] ; 1 ; +; RA[15] ; 1 ; +; RA[14] ; 1 ; +; RA[0] ; 1 ; +; RA[9] ; 1 ; +; RA[8] ; 1 ; +; RA[7] ; 1 ; +; RA[6] ; 1 ; +; RA[5] ; 1 ; +; RA[4] ; 1 ; +; RA[3] ; 1 ; +; RA[11] ; 1 ; +; RA[2] ; 1 ; +; RA[10] ; 1 ; +; RA[1] ; 1 ; +; ~GND ; 1 ; +; WRD[7] ; 1 ; +; WRD[6] ; 1 ; +; Equal37~0 ; 1 ; +; MOSIout~3 ; 1 ; +; MOSIout~2 ; 1 ; +; Equal13~0 ; 1 ; +; DEVSELr0 ; 1 ; +; nRESr0 ; 1 ; +; IOSTRBr0 ; 1 ; +; IOSELr0 ; 1 ; +; PHI0r0 ; 1 ; +; ARCLK~5 ; 1 ; +; ARCLK~4 ; 1 ; +; DRShift~0 ; 1 ; +; FCS~1 ; 1 ; +; MOSIout~0 ; 1 ; +; ARCLK~1 ; 1 ; +; Add1~110 ; 1 ; +; Mux2~1 ; 1 ; +; Equal5~1 ; 1 ; +; Mux0~2 ; 1 ; +; Mux0~1 ; 1 ; +; Add1~105 ; 1 ; +; Addr~29 ; 1 ; +; Add2~70 ; 1 ; +; Add3~30 ; 1 ; +; Add1~102COUT1_166 ; 1 ; +; Add1~102 ; 1 ; +; Add1~100 ; 1 ; +; Addr~27 ; 1 ; +; Add3~27COUT1_50 ; 1 ; +; Add3~27 ; 1 ; +; Add3~25 ; 1 ; +; Add2~67COUT1_108 ; 1 ; +; Add2~67 ; 1 ; +; Add2~65 ; 1 ; +; Add1~95 ; 1 ; +; Addr~25 ; 1 ; +; Add2~62COUT1_106 ; 1 ; +; Add2~62 ; 1 ; +; Add2~60 ; 1 ; +; Add3~22COUT1_48 ; 1 ; +; Add3~22 ; 1 ; +; Add3~20 ; 1 ; +; Add1~92COUT1_164 ; 1 ; +; Add1~92 ; 1 ; +; Add1~90 ; 1 ; +; Addr~23 ; 1 ; +; Add3~15 ; 1 ; +; Add2~55 ; 1 ; +; Add1~87COUT1_162 ; 1 ; +; Add1~87 ; 1 ; +; Add1~85 ; 1 ; +; Addr~21 ; 1 ; +; Add2~52COUT1_104 ; 1 ; +; Add2~52 ; 1 ; +; Add2~50 ; 1 ; +; Add3~12COUT1_46 ; 1 ; +; Add3~12 ; 1 ; +; Add3~10 ; 1 ; +; Add1~82COUT1_148 ; 1 ; +; Add1~82 ; 1 ; +; Add1~80 ; 1 ; +; Addr~20 ; 1 ; +; Add2~45 ; 1 ; +; Add1~77COUT1_160 ; 1 ; +; Add1~77 ; 1 ; +; Add1~75 ; 1 ; +; Addr~18 ; 1 ; +; Add3~7COUT1_44 ; 1 ; +; Add3~7 ; 1 ; +; Add3~5 ; 1 ; +; Add2~42COUT1_102 ; 1 ; +; Add2~42 ; 1 ; +; Add2~40 ; 1 ; +; Add1~72COUT1_146 ; 1 ; +; Add1~72 ; 1 ; +; Add1~70 ; 1 ; +; Addr~17 ; 1 ; +; Add2~37COUT1_88 ; 1 ; +; Add2~37 ; 1 ; +; Add2~35 ; 1 ; +; Addr[19]~15 ; 1 ; +; Addr[19]~14 ; 1 ; +; Addr[19]~13 ; 1 ; +; Add1~67COUT1_158 ; 1 ; +; Add1~67 ; 1 ; +; Add1~65 ; 1 ; +; Addr~11 ; 1 ; +; Add2~32COUT1_100 ; 1 ; +; Add2~32 ; 1 ; +; Add2~30 ; 1 ; +; Add3~2COUT1_42 ; 1 ; +; Add3~2 ; 1 ; +; Add3~0 ; 1 ; +; Add1~62COUT1_144 ; 1 ; +; Add1~62 ; 1 ; +; Add1~60 ; 1 ; +; Add1~55 ; 1 ; +; Addr~9 ; 1 ; +; Add2~27COUT1_98 ; 1 ; +; Add2~27 ; 1 ; +; Add2~25 ; 1 ; +; Add1~52COUT1_142 ; 1 ; +; Add1~52 ; 1 ; +; Add1~50 ; 1 ; +; Add1~47COUT1_156 ; 1 ; +; Add1~47 ; 1 ; +; Add1~45 ; 1 ; +; Addr~8 ; 1 ; +; Add2~20 ; 1 ; +; Add1~40 ; 1 ; +; Add1~37COUT1_140 ; 1 ; +; Add1~37 ; 1 ; +; Add1~35 ; 1 ; +; Add1~32COUT1_154 ; 1 ; +; Add1~32 ; 1 ; +; Add1~30 ; 1 ; +; Addr~7 ; 1 ; +; Add2~17COUT1_96 ; 1 ; +; Add2~17 ; 1 ; +; Add2~15 ; 1 ; +; Add1~27COUT1_138 ; 1 ; +; Add1~27 ; 1 ; +; Add1~25 ; 1 ; +; Add1~22COUT1_152 ; 1 ; +; Add1~22 ; 1 ; +; Add1~20 ; 1 ; +; Addr~6 ; 1 ; +; Add2~12COUT1_94 ; 1 ; +; Add2~12 ; 1 ; +; Add2~10 ; 1 ; +; Add1~17COUT1_136 ; 1 ; +; Add1~17 ; 1 ; +; Add1~15 ; 1 ; +; Add1~12COUT1_150 ; 1 ; +; Add1~12 ; 1 ; +; Add1~10 ; 1 ; +; Addr~5 ; 1 ; +; Add2~7COUT1_92 ; 1 ; +; Add2~7 ; 1 ; +; Add2~5 ; 1 ; +; Add1~7COUT1_134 ; 1 ; +; Add1~7 ; 1 ; +; Add1~5 ; 1 ; +; Addr[8]~1 ; 1 ; +; Add1~0 ; 1 ; +; Addr~0 ; 1 ; +; Add2~2COUT1_90 ; 1 ; +; Add2~2 ; 1 ; +; Add2~0 ; 1 ; +; PHI0r1 ; 1 ; +; PSStart~0 ; 1 ; +; RAcur[4] ; 1 ; +; always9~2 ; 1 ; +; always9~1 ; 1 ; +; Equal0~2 ; 1 ; +; LS[10]~33COUT1_64 ; 1 ; +; LS[10]~33 ; 1 ; +; LS[9]~31COUT1_62 ; 1 ; +; LS[9]~31 ; 1 ; +; LS[7]~27COUT1_60 ; 1 ; +; LS[7]~27 ; 1 ; +; LS[15]~25COUT1_72 ; 1 ; +; LS[15]~25 ; 1 ; +; LS[14]~23COUT1_70 ; 1 ; +; LS[14]~23 ; 1 ; +; LS[12]~19COUT1_68 ; 1 ; +; LS[12]~19 ; 1 ; +; LS[6]~17COUT1_58 ; 1 ; +; LS[6]~17 ; 1 ; +; LS[5]~15COUT1_56 ; 1 ; +; LS[5]~15 ; 1 ; +; LS[4]~13COUT1_54 ; 1 ; +; LS[4]~13 ; 1 ; +; LS[2]~11COUT1_52 ; 1 ; +; LS[2]~11 ; 1 ; +; Equal0~0 ; 1 ; +; LS[11]~9COUT1_66 ; 1 ; +; LS[11]~9 ; 1 ; +; LS[16]~5COUT1_74 ; 1 ; +; LS[16]~5 ; 1 ; +; LS[1]~3COUT1_50 ; 1 ; +; LS[1]~3 ; 1 ; +; ARShift ; 1 ; +; ARCLK ; 1 ; +; DRShift ; 1 ; +; DRCLK ; 1 ; +; FCK~reg0 ; 1 ; +; DQMH~0 ; 1 ; +; DQML~2 ; 1 ; +; nSWE~reg0 ; 1 ; +; nCAS~reg0 ; 1 ; +; nRAS~reg0 ; 1 ; +; nRCS~reg0 ; 1 ; +; SA~25 ; 1 ; +; SA~24 ; 1 ; +; SA~23 ; 1 ; +; SA~22 ; 1 ; +; SA~21 ; 1 ; +; SA~20 ; 1 ; +; SA~19 ; 1 ; +; SA~18 ; 1 ; +; SA~17 ; 1 ; +; SA~16 ; 1 ; +; SA~15 ; 1 ; +; RAcur[6] ; 1 ; +; SA~14 ; 1 ; +; SA~13 ; 1 ; +; RAcur[5] ; 1 ; +; SA~12 ; 1 ; +; SA~11 ; 1 ; +; SA~10 ; 1 ; +; SA~9 ; 1 ; +; Bank[1] ; 1 ; +; SA~8 ; 1 ; +; SA~7 ; 1 ; +; SA~6 ; 1 ; +; Bank[0] ; 1 ; +; SA~5 ; 1 ; +; SA~4 ; 1 ; +; RAcur[11] ; 1 ; +; SA~3 ; 1 ; +; SA~2 ; 1 ; +; SA~1 ; 1 ; +; SA~0 ; 1 ; +; Equal43~0 ; 1 ; +; PHI0r2 ; 1 ; +; comb~1 ; 1 ; +; comb~0 ; 1 ; ++-------------------+-------------+ + + ++--------------------------------------------------+ +; Other Routing Usage Summary ; ++-----------------------------+--------------------+ +; Other Routing Resource Type ; Usage ; ++-----------------------------+--------------------+ +; C4s ; 171 / 784 ( 22 % ) ; +; Direct links ; 69 / 888 ( 8 % ) ; +; Global clocks ; 1 / 4 ( 25 % ) ; +; LAB clocks ; 6 / 32 ( 19 % ) ; +; LUT chains ; 19 / 216 ( 9 % ) ; +; Local interconnects ; 400 / 888 ( 45 % ) ; +; R4s ; 245 / 704 ( 35 % ) ; ++-----------------------------+--------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Logic Elements ; ++--------------------------------------------+------------------------------+ +; Number of Logic Elements (Average = 9.79) ; Number of LABs (Total = 24) ; ++--------------------------------------------+------------------------------+ +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 1 ; +; 8 ; 0 ; +; 9 ; 2 ; +; 10 ; 21 ; ++--------------------------------------------+------------------------------+ + + ++-------------------------------------------------------------------+ +; LAB-wide Signals ; ++------------------------------------+------------------------------+ +; LAB-wide Signals (Average = 1.79) ; Number of LABs (Total = 24) ; ++------------------------------------+------------------------------+ +; 1 Clock ; 22 ; +; 1 Clock enable ; 8 ; +; 1 Sync. clear ; 10 ; +; 2 Clock enables ; 3 ; ++------------------------------------+------------------------------+ + + ++-----------------------------------------------------------------------------+ +; LAB Signals Sourced ; ++----------------------------------------------+------------------------------+ +; Number of Signals Sourced (Average = 10.50) ; Number of LABs (Total = 24) ; ++----------------------------------------------+------------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 1 ; +; 8 ; 0 ; +; 9 ; 2 ; +; 10 ; 17 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 1 ; +; 14 ; 2 ; +; 15 ; 0 ; +; 16 ; 1 ; ++----------------------------------------------+------------------------------+ + + ++--------------------------------------------------------------------------------+ +; LAB Signals Sourced Out ; ++-------------------------------------------------+------------------------------+ +; Number of Signals Sourced Out (Average = 7.63) ; Number of LABs (Total = 24) ; ++-------------------------------------------------+------------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 2 ; +; 5 ; 1 ; +; 6 ; 4 ; +; 7 ; 5 ; +; 8 ; 5 ; +; 9 ; 2 ; +; 10 ; 4 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 1 ; ++-------------------------------------------------+------------------------------+ + + ++-----------------------------------------------------------------------------+ +; LAB Distinct Inputs ; ++----------------------------------------------+------------------------------+ +; Number of Distinct Inputs (Average = 15.25) ; Number of LABs (Total = 24) ; ++----------------------------------------------+------------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 1 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 1 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 1 ; +; 11 ; 1 ; +; 12 ; 2 ; +; 13 ; 1 ; +; 14 ; 2 ; +; 15 ; 2 ; +; 16 ; 3 ; +; 17 ; 1 ; +; 18 ; 2 ; +; 19 ; 1 ; +; 20 ; 3 ; +; 21 ; 3 ; ++----------------------------------------------+------------------------------+ +-------------------------------------------------------------------------+ @@ -904,7 +1079,7 @@ Info (176444): Device migration not selected. If you intend to use device migrat Info (176445): Device EPM570T100C5 is compatible Info (176445): Device EPM570T100I5 is compatible Info (176445): Device EPM570T100A5 is compatible -Critical Warning (169085): No exact pin location assignment(s) for 69 pins of 69 total pins +Critical Warning (169085): No exact pin location assignment(s) for 68 pins of 68 total pins Info (169086): Pin nRESout not assigned to an exact location on the device Info (169086): Pin RAdir not assigned to an exact location on the device Info (169086): Pin RDdir not assigned to an exact location on the device @@ -967,13 +1142,12 @@ Critical Warning (169085): No exact pin location assignment(s) for 69 pins of 69 Info (169086): Pin RA[8] not assigned to an exact location on the device Info (169086): Pin RA[9] not assigned to an exact location on the device Info (169086): Pin RA[0] not assigned to an exact location on the device - Info (169086): Pin nRES not assigned to an exact location on the device Info (169086): Pin RA[14] not assigned to an exact location on the device Info (169086): Pin RA[15] not assigned to an exact location on the device Info (169086): Pin RA[12] not assigned to an exact location on the device Info (169086): Pin RA[13] not assigned to an exact location on the device + Info (169086): Pin nRES not assigned to an exact location on the device Info (169086): Pin MISO not assigned to an exact location on the device - Info (169086): Pin nBOD not assigned to an exact location on the device Critical Warning (332012): Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. Info (332144): No user constrained base clocks found in the design Info (332128): Timing requirements not specified -- optimizing circuit to achieve the following default global requirements @@ -991,45 +1165,31 @@ Info (186468): Started processing fast register assignments Info (186469): Finished processing fast register assignments Info (176235): Finished register packing Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement - Info (176211): Number of I/O pins in group: 68 (unused VREF, 3.3V VCCIO, 24 input, 28 output, 16 bidirectional) + Info (176211): Number of I/O pins in group: 67 (unused VREF, 3.3V VCCIO, 23 input, 28 output, 16 bidirectional) Info (176212): I/O standards used: 3.3-V LVTTL. Info (176215): I/O bank details before I/O pin placement Info (176214): Statistics of I/O banks Info (176213): I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 37 pins available Info (176213): I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 42 pins available -Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00 +Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01 Info (170189): Fitter placement preparation operations beginning Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 -Info (11888): Total time spent on timing analysis during the Fitter is 0.03 seconds. -Info (170216): Fitter cannot place all nodes on current device -- Fitter will automatically make another fitting attempt and tightly pack logic elements -Info (176234): Starting register packing -Info (186391): Fitter is using Minimize Area packing mode for logic elements with Auto setting for Auto Packed Registers logic option -Info (186468): Started processing fast register assignments -Info (186469): Finished processing fast register assignments -Info (176235): Finished register packing -Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00 -Info (170189): Fitter placement preparation operations beginning -Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 -Info (11888): Total time spent on timing analysis during the Fitter is 0.02 seconds. -Info (170216): Fitter cannot place all nodes on current device -- Fitter will automatically make another fitting attempt and tightly pack logic elements -Info (176234): Starting register packing -Info (186391): Fitter is using Minimize Area with Chains packing mode for logic elements with Auto setting for Auto Packed Registers logic option -Info (186468): Started processing fast register assignments -Info (186469): Finished processing fast register assignments -Info (176235): Finished register packing -Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00 -Info (170189): Fitter placement preparation operations beginning -Error (170011): Design contains 247 blocks of type logic cell. However, device contains only 240. -Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 -Info (11888): Total time spent on timing analysis during the Fitter is 0.02 seconds. -Error (171000): Can't fit design in device +Info (170191): Fitter placement operations beginning +Info (170137): Fitter placement was successful +Info (170192): Fitter placement operations ending: elapsed time is 00:00:03 +Info (170193): Fitter routing operations beginning +Info (170195): Router estimated average interconnect usage is 27% of the available device resources + Info (170196): Router estimated peak interconnect usage is 27% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5 +Info (170194): Fitter routing operations ending: elapsed time is 00:00:01 +Info (11888): Total time spent on timing analysis during the Fitter is 0.39 seconds. +Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00 Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'. Info (144001): Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg -Error: Quartus II 32-bit Fitter was unsuccessful. 2 errors, 4 warnings - Error: Peak virtual memory: 367 megabytes - Error: Processing ended: Fri Mar 19 06:58:10 2021 - Error: Elapsed time: 00:00:05 - Error: Total CPU time (on all processors): 00:00:05 +Info: Quartus II 32-bit Fitter was successful. 0 errors, 4 warnings + Info: Peak virtual memory: 373 megabytes + Info: Processing ended: Fri Mar 19 07:33:11 2021 + Info: Elapsed time: 00:00:10 + Info: Total CPU time (on all processors): 00:00:09 +----------------------------+ diff --git a/cpld/output_files/GR8RAM.fit.smsg b/cpld/output_files/GR8RAM.fit.smsg index 9b1e01f..6df10d8 100755 --- a/cpld/output_files/GR8RAM.fit.smsg +++ b/cpld/output_files/GR8RAM.fit.smsg @@ -2,5 +2,3 @@ Extra Info (176273): Performing register packing on registers with non-logic cel Extra Info (176274): Completed register packing on registers with non-logic cell location assignments Extra Info (176244): Moving registers into LUTs to improve timing and density Extra Info (176245): Finished moving registers into LUTs: elapsed time is 00:00:00 -Extra Info (176245): Finished moving registers into LUTs: elapsed time is 00:00:00 -Extra Info (176245): Finished moving registers into LUTs: elapsed time is 00:00:00 diff --git a/cpld/output_files/GR8RAM.fit.summary b/cpld/output_files/GR8RAM.fit.summary index 0f65cab..c11276c 100755 --- a/cpld/output_files/GR8RAM.fit.summary +++ b/cpld/output_files/GR8RAM.fit.summary @@ -1,11 +1,11 @@ -Fitter Status : Failed - Fri Mar 19 06:58:10 2021 +Fitter Status : Successful - Fri Mar 19 07:33:10 2021 Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition Revision Name : GR8RAM Top-level Entity Name : GR8RAM Family : MAX II Device : EPM240T100C5 Timing Models : Final -Total logic elements : 247 / 240 ( 103 % ) -Total pins : 69 / 80 ( 86 % ) +Total logic elements : 235 / 240 ( 98 % ) +Total pins : 68 / 80 ( 85 % ) Total virtual pins : 0 UFM blocks : 1 / 1 ( 100 % ) diff --git a/cpld/output_files/GR8RAM.flow.rpt b/cpld/output_files/GR8RAM.flow.rpt index b34702e..4563710 100755 --- a/cpld/output_files/GR8RAM.flow.rpt +++ b/cpld/output_files/GR8RAM.flow.rpt @@ -1,5 +1,5 @@ Flow report for GR8RAM -Fri Mar 19 06:58:10 2021 +Fri Mar 19 07:33:22 2021 Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition @@ -40,15 +40,15 @@ applicable agreement for further details. +-----------------------------------------------------------------------------+ ; Flow Summary ; +---------------------------+-------------------------------------------------+ -; Flow Status ; Flow Failed - Fri Mar 19 06:58:10 2021 ; +; Flow Status ; Successful - Fri Mar 19 07:33:15 2021 ; ; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; ; Revision Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ; ; Family ; MAX II ; ; Device ; EPM240T100C5 ; ; Timing Models ; Final ; -; Total logic elements ; 247 / 240 ( 103 % ) ; -; Total pins ; 69 / 80 ( 86 % ) ; +; Total logic elements ; 235 / 240 ( 98 % ) ; +; Total pins ; 68 / 80 ( 85 % ) ; ; Total virtual pins ; 0 ; ; UFM blocks ; 1 / 1 ( 100 % ) ; +---------------------------+-------------------------------------------------+ @@ -59,7 +59,7 @@ applicable agreement for further details. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 03/19/2021 06:57:59 ; +; Start date & time ; 03/19/2021 07:32:56 ; ; Main task ; Compilation ; ; Revision Name ; GR8RAM ; +-------------------+---------------------+ @@ -70,7 +70,7 @@ applicable agreement for further details. +---------------------------------------+--------------------------------+---------------+-------------+------------+ ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; +---------------------------------------+--------------------------------+---------------+-------------+------------+ -; COMPILER_SIGNATURE_ID ; 44085571633675.161615147901060 ; -- ; -- ; -- ; +; COMPILER_SIGNATURE_ID ; 44085571633675.161615357603936 ; -- ; -- ; -- ; ; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ; ; IP_TOOL_NAME ; ALTUFM_NONE ; -- ; -- ; -- ; ; IP_TOOL_VERSION ; 13.0 ; -- ; -- ; -- ; @@ -83,25 +83,29 @@ applicable agreement for further details. +---------------------------------------+--------------------------------+---------------+-------------+------------+ -+--------------------------------------------------------------------------------------------------------------------------+ -; Flow Elapsed Time ; -+----------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; -+----------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:06 ; 1.0 ; 301 MB ; 00:00:05 ; -; Fitter ; 00:00:05 ; 1.0 ; 367 MB ; 00:00:05 ; -; Total ; 00:00:11 ; -- ; -- ; 00:00:10 ; -+----------------------+--------------+-------------------------+---------------------+------------------------------------+ ++-------------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:05 ; 1.0 ; 301 MB ; 00:00:05 ; +; Fitter ; 00:00:09 ; 1.3 ; 373 MB ; 00:00:08 ; +; Assembler ; 00:00:02 ; 1.0 ; 292 MB ; 00:00:02 ; +; TimeQuest Timing Analyzer ; 00:00:04 ; 1.0 ; 275 MB ; 00:00:05 ; +; Total ; 00:00:20 ; -- ; -- ; 00:00:20 ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ -+------------------------------------------------------------------------------------+ -; Flow OS Summary ; -+----------------------+------------------+------------+------------+----------------+ -; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; -+----------------------+------------------+------------+------------+----------------+ -; Analysis & Synthesis ; zane-c8bbf8aef2 ; Windows XP ; 5.1 ; i686 ; -; Fitter ; zane-c8bbf8aef2 ; Windows XP ; 5.1 ; i686 ; -+----------------------+------------------+------------+------------+----------------+ ++-----------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++---------------------------+------------------+------------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++---------------------------+------------------+------------+------------+----------------+ +; Analysis & Synthesis ; zane-c8bbf8aef2 ; Windows XP ; 5.1 ; i686 ; +; Fitter ; zane-c8bbf8aef2 ; Windows XP ; 5.1 ; i686 ; +; Assembler ; zane-c8bbf8aef2 ; Windows XP ; 5.1 ; i686 ; +; TimeQuest Timing Analyzer ; zane-c8bbf8aef2 ; Windows XP ; 5.1 ; i686 ; ++---------------------------+------------------+------------+------------+----------------+ ------------ @@ -109,6 +113,8 @@ applicable agreement for further details. ------------ quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM +quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM +quartus_sta GR8RAM -c GR8RAM diff --git a/cpld/output_files/GR8RAM.jdi b/cpld/output_files/GR8RAM.jdi index 2e52d7d..c9b4840 100755 --- a/cpld/output_files/GR8RAM.jdi +++ b/cpld/output_files/GR8RAM.jdi @@ -1,6 +1,6 @@ - + diff --git a/cpld/output_files/GR8RAM.map.rpt b/cpld/output_files/GR8RAM.map.rpt index f52674d..8ee9a02 100755 --- a/cpld/output_files/GR8RAM.map.rpt +++ b/cpld/output_files/GR8RAM.map.rpt @@ -1,5 +1,5 @@ Analysis & Synthesis report for GR8RAM -Fri Mar 19 06:58:03 2021 +Fri Mar 19 07:32:59 2021 Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition @@ -47,13 +47,13 @@ applicable agreement for further details. +-------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +-----------------------------+-------------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Fri Mar 19 06:58:03 2021 ; +; Analysis & Synthesis Status ; Successful - Fri Mar 19 07:32:59 2021 ; ; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; ; Revision Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ; ; Family ; MAX II ; -; Total logic elements ; 281 ; -; Total pins ; 69 ; +; Total logic elements ; 260 ; +; Total pins ; 68 ; ; Total virtual pins ; 0 ; ; UFM blocks ; 1 / 1 ( 100 % ) ; +-----------------------------+-------------------------------------------------+ @@ -164,34 +164,34 @@ applicable agreement for further details. +---------------------------------------------+-------+ ; Resource ; Usage ; +---------------------------------------------+-------+ -; Total logic elements ; 281 ; -; -- Combinational with no register ; 178 ; -; -- Register only ; 34 ; -; -- Combinational with a register ; 69 ; +; Total logic elements ; 260 ; +; -- Combinational with no register ; 164 ; +; -- Register only ; 29 ; +; -- Combinational with a register ; 67 ; ; ; ; ; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 106 ; -; -- 3 input functions ; 52 ; +; -- 4 input functions ; 96 ; +; -- 3 input functions ; 45 ; ; -- 2 input functions ; 80 ; -; -- 1 input functions ; 8 ; +; -- 1 input functions ; 9 ; ; -- 0 input functions ; 1 ; ; ; ; ; Logic elements by mode ; ; -; -- normal mode ; 223 ; +; -- normal mode ; 202 ; ; -- arithmetic mode ; 58 ; ; -- qfbk mode ; 0 ; ; -- register cascade mode ; 0 ; ; -- synchronous clear/load mode ; 25 ; ; -- asynchronous clear/load mode ; 0 ; ; ; ; -; Total registers ; 103 ; +; Total registers ; 96 ; ; Total logic cells in carry chains ; 62 ; -; I/O pins ; 69 ; +; I/O pins ; 68 ; ; UFM blocks ; 1 ; ; Maximum fan-out node ; C25M ; -; Maximum fan-out ; 103 ; -; Total fan-out ; 1009 ; -; Average fan-out ; 2.87 ; +; Maximum fan-out ; 96 ; +; Total fan-out ; 933 ; +; Average fan-out ; 2.84 ; +---------------------------------------------+-------+ @@ -200,7 +200,7 @@ applicable agreement for further details. +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+ ; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ; +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+ -; |GR8RAM ; 281 (281) ; 103 ; 1 ; 69 ; 0 ; 178 (178) ; 34 (34) ; 69 (69) ; 62 (62) ; 0 (0) ; |GR8RAM ; work ; +; |GR8RAM ; 260 (260) ; 96 ; 1 ; 68 ; 0 ; 164 (164) ; 29 (29) ; 67 (67) ; 62 (62) ; 0 (0) ; |GR8RAM ; work ; ; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |GR8RAM|UFM:UFM_inst ; work ; ; |UFM_altufm_none_0ep:UFM_altufm_none_0ep_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |GR8RAM|UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component ; work ; +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+ @@ -243,12 +243,12 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +----------------------------------------------+-------+ ; Statistic ; Value ; +----------------------------------------------+-------+ -; Total registers ; 103 ; +; Total registers ; 96 ; ; Number of registers using Synchronous Clear ; 25 ; ; Number of registers using Synchronous Load ; 0 ; ; Number of registers using Asynchronous Clear ; 0 ; ; Number of registers using Asynchronous Load ; 0 ; -; Number of registers using Clock Enable ; 49 ; +; Number of registers using Clock Enable ; 45 ; ; Number of registers using Preset ; 0 ; +----------------------------------------------+-------+ @@ -272,12 +272,12 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ ; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ -; 3:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; Yes ; |GR8RAM|PS[2] ; -; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |GR8RAM|Bank[0] ; -; 5:1 ; 8 bits ; 24 LEs ; 16 LEs ; 8 LEs ; Yes ; |GR8RAM|Addr[0] ; -; 7:1 ; 8 bits ; 32 LEs ; 16 LEs ; 16 LEs ; Yes ; |GR8RAM|Addr[9] ; -; 13:1 ; 2 bits ; 16 LEs ; 12 LEs ; 4 LEs ; Yes ; |GR8RAM|DRShift ; -; 9:1 ; 8 bits ; 48 LEs ; 24 LEs ; 24 LEs ; Yes ; |GR8RAM|Addr[20] ; +; 3:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; Yes ; |GR8RAM|PS[0] ; +; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |GR8RAM|Bank[1] ; +; 5:1 ; 8 bits ; 24 LEs ; 16 LEs ; 8 LEs ; Yes ; |GR8RAM|Addr[4] ; +; 7:1 ; 8 bits ; 32 LEs ; 16 LEs ; 16 LEs ; Yes ; |GR8RAM|Addr[8] ; +; 13:1 ; 2 bits ; 16 LEs ; 12 LEs ; 4 LEs ; Yes ; |GR8RAM|DRCLK ; +; 9:1 ; 8 bits ; 48 LEs ; 24 LEs ; 24 LEs ; Yes ; |GR8RAM|Addr[19] ; ; 8:1 ; 2 bits ; 10 LEs ; 6 LEs ; 4 LEs ; No ; |GR8RAM|SA ; ; 8:1 ; 5 bits ; 25 LEs ; 15 LEs ; 10 LEs ; No ; |GR8RAM|SA ; ; 8:1 ; 4 bits ; 20 LEs ; 12 LEs ; 8 LEs ; No ; |GR8RAM|SA ; @@ -304,7 +304,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi Info: ******************************************************************* Info: Running Quartus II 32-bit Analysis & Synthesis Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - Info: Processing started: Fri Mar 19 06:57:57 2021 + Info: Processing started: Fri Mar 19 07:32:54 2021 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected Info (12021): Found 2 design units, including 2 entities, in source file ufm.v @@ -312,21 +312,20 @@ Info (12021): Found 2 design units, including 2 entities, in source file ufm.v Info (12023): Found entity 2: UFM Warning (12125): Using design file gr8ram.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info (12023): Found entity 1: GR8RAM -Warning (10236): Verilog HDL Implicit Net warning at gr8ram.v(247): created implicit net for "UFMB" -Warning (10236): Verilog HDL Implicit Net warning at gr8ram.v(250): created implicit net for "RTPB" +Warning (10236): Verilog HDL Implicit Net warning at gr8ram.v(223): created implicit net for "UFMB" +Warning (10236): Verilog HDL Implicit Net warning at gr8ram.v(226): created implicit net for "RTPB" Info (12127): Elaborating entity "GR8RAM" for the top level hierarchy -Warning (10858): Verilog HDL warning at gr8ram.v(110): object RDout used but never assigned -Warning (10036): Verilog HDL or VHDL warning at gr8ram.v(252): object "UFMBr" assigned a value but never read -Warning (10036): Verilog HDL or VHDL warning at gr8ram.v(254): object "RTPBr" assigned a value but never read -Warning (10036): Verilog HDL or VHDL warning at gr8ram.v(354): object "IS" assigned a value but never read -Warning (10036): Verilog HDL or VHDL warning at gr8ram.v(365): object "RefReady" assigned a value but never read -Warning (10230): Verilog HDL assignment warning at gr8ram.v(34): truncated value with size 32 to match size of target (18) -Warning (10230): Verilog HDL assignment warning at gr8ram.v(124): truncated value with size 32 to match size of target (24) -Warning (10230): Verilog HDL assignment warning at gr8ram.v(128): truncated value with size 32 to match size of target (16) -Warning (10230): Verilog HDL assignment warning at gr8ram.v(133): truncated value with size 32 to match size of target (8) -Warning (10230): Verilog HDL assignment warning at gr8ram.v(351): truncated value with size 32 to match size of target (3) -Warning (10030): Net "RDout" at gr8ram.v(110) has no driver or initial value, using a default initial value '0' -Warning (10030): Net "WRD[5..0]" at gr8ram.v(336) has no driver or initial value, using a default initial value '0' +Warning (10858): Verilog HDL warning at gr8ram.v(86): object RDout used but never assigned +Warning (10036): Verilog HDL or VHDL warning at gr8ram.v(228): object "UFMBr" assigned a value but never read +Warning (10036): Verilog HDL or VHDL warning at gr8ram.v(230): object "RTPBr" assigned a value but never read +Warning (10036): Verilog HDL or VHDL warning at gr8ram.v(332): object "RefReady" assigned a value but never read +Warning (10230): Verilog HDL assignment warning at gr8ram.v(24): truncated value with size 32 to match size of target (18) +Warning (10230): Verilog HDL assignment warning at gr8ram.v(100): truncated value with size 32 to match size of target (24) +Warning (10230): Verilog HDL assignment warning at gr8ram.v(104): truncated value with size 32 to match size of target (16) +Warning (10230): Verilog HDL assignment warning at gr8ram.v(109): truncated value with size 32 to match size of target (8) +Warning (10230): Verilog HDL assignment warning at gr8ram.v(327): truncated value with size 32 to match size of target (3) +Warning (10030): Net "RDout" at gr8ram.v(86) has no driver or initial value, using a default initial value '0' +Warning (10030): Net "WRD[5..0]" at gr8ram.v(312) has no driver or initial value, using a default initial value '0' Info (12128): Elaborating entity "UFM" for hierarchy "UFM:UFM_inst" Info (12128): Elaborating entity "UFM_altufm_none_0ep" for hierarchy "UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component" Warning (13046): Tri-state node(s) do not directly drive top-level pin(s) @@ -334,18 +333,18 @@ Warning (13046): Tri-state node(s) do not directly drive top-level pin(s) Warning (13024): Output pins are stuck at VCC or GND Warning (13410): Pin "RAdir" is stuck at VCC Warning (13410): Pin "SBA[0]" is stuck at GND -Info (21057): Implemented 351 device resources after synthesis - the final resource count might be different - Info (21058): Implemented 25 input pins +Info (21057): Implemented 329 device resources after synthesis - the final resource count might be different + Info (21058): Implemented 24 input pins Info (21059): Implemented 28 output pins Info (21060): Implemented 16 bidirectional pins - Info (21061): Implemented 281 logic cells + Info (21061): Implemented 260 logic cells Info (21070): Implemented 1 User Flash Memory blocks Info (144001): Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg -Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 20 warnings +Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 19 warnings Info: Peak virtual memory: 301 megabytes - Info: Processing ended: Fri Mar 19 06:58:03 2021 - Info: Elapsed time: 00:00:06 - Info: Total CPU time (on all processors): 00:00:06 + Info: Processing ended: Fri Mar 19 07:32:59 2021 + Info: Elapsed time: 00:00:05 + Info: Total CPU time (on all processors): 00:00:05 +------------------------------------------+ diff --git a/cpld/output_files/GR8RAM.map.smsg b/cpld/output_files/GR8RAM.map.smsg index 1ce30d3..a19806b 100755 --- a/cpld/output_files/GR8RAM.map.smsg +++ b/cpld/output_files/GR8RAM.map.smsg @@ -1,4 +1,4 @@ Warning (10463): Verilog HDL Declaration warning at UFM.v(72): "program" is SystemVerilog-2005 keyword Warning (10463): Verilog HDL Declaration warning at UFM.v(188): "program" is SystemVerilog-2005 keyword -Warning (10273): Verilog HDL warning at gr8ram.v(109): extended using "x" or "z" -Warning (10273): Verilog HDL warning at gr8ram.v(335): extended using "x" or "z" +Warning (10273): Verilog HDL warning at gr8ram.v(85): extended using "x" or "z" +Warning (10273): Verilog HDL warning at gr8ram.v(311): extended using "x" or "z" diff --git a/cpld/output_files/GR8RAM.map.summary b/cpld/output_files/GR8RAM.map.summary index c323180..da0abaa 100755 --- a/cpld/output_files/GR8RAM.map.summary +++ b/cpld/output_files/GR8RAM.map.summary @@ -1,9 +1,9 @@ -Analysis & Synthesis Status : Successful - Fri Mar 19 06:58:03 2021 +Analysis & Synthesis Status : Successful - Fri Mar 19 07:32:59 2021 Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition Revision Name : GR8RAM Top-level Entity Name : GR8RAM Family : MAX II -Total logic elements : 281 -Total pins : 69 +Total logic elements : 260 +Total pins : 68 Total virtual pins : 0 UFM blocks : 1 / 1 ( 100 % ) diff --git a/cpld/output_files/GR8RAM.pin b/cpld/output_files/GR8RAM.pin new file mode 100755 index 0000000..b748cdf --- /dev/null +++ b/cpld/output_files/GR8RAM.pin @@ -0,0 +1,164 @@ + -- Copyright (C) 1991-2013 Altera Corporation + -- Your use of Altera Corporation's design tools, logic functions + -- and other software and tools, and its AMPP partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Altera Program License + -- Subscription Agreement, Altera MegaCore Function License + -- Agreement, or other applicable license agreement, including, + -- without limitation, that your use is for the sole purpose of + -- programming logic devices manufactured by Altera and sold by + -- Altera or its authorized distributors. Please refer to the + -- applicable agreement for further details. + -- + -- This is a Quartus II output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus II input file. This file cannot be used + -- to make Quartus II pin assignments - for instructions on how to make pin + -- assignments, please see Quartus II help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (2.5V/3.3V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 1: 3.3V + -- Bank 2: 3.3V + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +CHIP "GR8RAM" ASSIGNED TO AN: EPM240T100C5 + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +RA[12] : 1 : input : 3.3-V LVTTL : : 2 : N +RD[0] : 2 : bidir : 3.3-V LVTTL : : 1 : N +RD[3] : 3 : bidir : 3.3-V LVTTL : : 1 : N +RD[6] : 4 : bidir : 3.3-V LVTTL : : 1 : N +RD[4] : 5 : bidir : 3.3-V LVTTL : : 1 : N +RD[7] : 6 : bidir : 3.3-V LVTTL : : 1 : N +RD[1] : 7 : bidir : 3.3-V LVTTL : : 1 : N +nWE : 8 : input : 3.3-V LVTTL : : 1 : N +VCCIO1 : 9 : power : : 3.3V : 1 : +GNDIO : 10 : gnd : : : : +GNDINT : 11 : gnd : : : : +PHI0 : 12 : input : 3.3-V LVTTL : : 1 : N +VCCINT : 13 : power : : 2.5V/3.3V : : +C25M : 14 : input : 3.3-V LVTTL : : 1 : N +RA[8] : 15 : input : 3.3-V LVTTL : : 1 : N +RA[10] : 16 : input : 3.3-V LVTTL : : 1 : N +RA[9] : 17 : input : 3.3-V LVTTL : : 1 : N +SA[8] : 18 : output : 3.3-V LVTTL : : 1 : N +SA[7] : 19 : output : 3.3-V LVTTL : : 1 : N +RA[11] : 20 : input : 3.3-V LVTTL : : 1 : N +SA[1] : 21 : output : 3.3-V LVTTL : : 1 : N +TMS : 22 : input : : : 1 : +TDI : 23 : input : : : 1 : +TCK : 24 : input : : : 1 : +TDO : 25 : output : : : 1 : +SD[7] : 26 : bidir : 3.3-V LVTTL : : 1 : N +SD[6] : 27 : bidir : 3.3-V LVTTL : : 1 : N +MOSI : 28 : output : 3.3-V LVTTL : : 1 : N +FCK : 29 : output : 3.3-V LVTTL : : 1 : N +RA[0] : 30 : input : 3.3-V LVTTL : : 1 : N +VCCIO1 : 31 : power : : 3.3V : 1 : +GNDIO : 32 : gnd : : : : +MISO : 33 : input : 3.3-V LVTTL : : 1 : N +RA[7] : 34 : input : 3.3-V LVTTL : : 1 : N +RA[2] : 35 : input : 3.3-V LVTTL : : 1 : N +RA[14] : 36 : input : 3.3-V LVTTL : : 1 : N +nRESout : 37 : output : 3.3-V LVTTL : : 1 : N +nFCS : 38 : output : 3.3-V LVTTL : : 1 : N +SA[3] : 39 : output : 3.3-V LVTTL : : 1 : N +SD[1] : 40 : bidir : 3.3-V LVTTL : : 1 : N +SD[4] : 41 : bidir : 3.3-V LVTTL : : 1 : N +SD[0] : 42 : bidir : 3.3-V LVTTL : : 1 : N +SBA[0] : 43 : output : 3.3-V LVTTL : : 1 : N +GND* : 44 : : : : 1 : +VCCIO1 : 45 : power : : 3.3V : 1 : +GNDIO : 46 : gnd : : : : +GND* : 47 : : : : 1 : +GND* : 48 : : : : 1 : +GND* : 49 : : : : 1 : +GND* : 50 : : : : 1 : +SD[3] : 51 : bidir : 3.3-V LVTTL : : 1 : N +SD[5] : 52 : bidir : 3.3-V LVTTL : : 2 : N +SD[2] : 53 : bidir : 3.3-V LVTTL : : 2 : N +GND* : 54 : : : : 2 : +GND* : 55 : : : : 2 : +GND* : 56 : : : : 2 : +nRCS : 57 : output : 3.3-V LVTTL : : 2 : N +nCAS : 58 : output : 3.3-V LVTTL : : 2 : N +VCCIO2 : 59 : power : : 3.3V : 2 : +GNDIO : 60 : gnd : : : : +SA[2] : 61 : output : 3.3-V LVTTL : : 2 : N +SA[10] : 62 : output : 3.3-V LVTTL : : 2 : N +VCCINT : 63 : power : : 2.5V/3.3V : : +nRES : 64 : input : 3.3-V LVTTL : : 2 : N +GNDINT : 65 : gnd : : : : +RCKE : 66 : output : 3.3-V LVTTL : : 2 : N +SA[9] : 67 : output : 3.3-V LVTTL : : 2 : N +nRAS : 68 : output : 3.3-V LVTTL : : 2 : N +nSWE : 69 : output : 3.3-V LVTTL : : 2 : N +SA[12] : 70 : output : 3.3-V LVTTL : : 2 : N +nIOSEL : 71 : input : 3.3-V LVTTL : : 2 : N +nIOSTRB : 72 : input : 3.3-V LVTTL : : 2 : N +SA[0] : 73 : output : 3.3-V LVTTL : : 2 : N +SA[4] : 74 : output : 3.3-V LVTTL : : 2 : N +DQMH : 75 : output : 3.3-V LVTTL : : 2 : N +DQML : 76 : output : 3.3-V LVTTL : : 2 : N +nDEVSEL : 77 : input : 3.3-V LVTTL : : 2 : N +RAdir : 78 : output : 3.3-V LVTTL : : 2 : N +GNDIO : 79 : gnd : : : : +VCCIO2 : 80 : power : : 3.3V : 2 : +RA[5] : 81 : input : 3.3-V LVTTL : : 2 : N +RA[6] : 82 : input : 3.3-V LVTTL : : 2 : N +SA[6] : 83 : output : 3.3-V LVTTL : : 2 : N +RA[4] : 84 : input : 3.3-V LVTTL : : 2 : N +SA[5] : 85 : output : 3.3-V LVTTL : : 2 : N +SBA[1] : 86 : output : 3.3-V LVTTL : : 2 : N +GND* : 87 : : : : 2 : +SA[11] : 88 : output : 3.3-V LVTTL : : 2 : N +GND* : 89 : : : : 2 : +GND* : 90 : : : : 2 : +GND* : 91 : : : : 2 : +RA[1] : 92 : input : 3.3-V LVTTL : : 2 : N +GNDIO : 93 : gnd : : : : +VCCIO2 : 94 : power : : 3.3V : 2 : +RA[15] : 95 : input : 3.3-V LVTTL : : 2 : N +RA[3] : 96 : input : 3.3-V LVTTL : : 2 : N +RA[13] : 97 : input : 3.3-V LVTTL : : 2 : N +RD[2] : 98 : bidir : 3.3-V LVTTL : : 2 : N +RD[5] : 99 : bidir : 3.3-V LVTTL : : 2 : N +RDdir : 100 : output : 3.3-V LVTTL : : 2 : N diff --git a/cpld/output_files/GR8RAM.pof b/cpld/output_files/GR8RAM.pof index 8b0bc60..2934233 100755 Binary files a/cpld/output_files/GR8RAM.pof and b/cpld/output_files/GR8RAM.pof differ diff --git a/cpld/output_files/GR8RAM.sta.rpt b/cpld/output_files/GR8RAM.sta.rpt index 58b5fbf..97bbf14 100755 --- a/cpld/output_files/GR8RAM.sta.rpt +++ b/cpld/output_files/GR8RAM.sta.rpt @@ -1,5 +1,5 @@ TimeQuest Timing Analyzer report for GR8RAM -Fri Mar 19 05:29:00 2021 +Fri Mar 19 07:33:22 2021 Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition @@ -16,31 +16,25 @@ Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit 8. Recovery Summary 9. Removal Summary 10. Minimum Pulse Width Summary - 11. Setup: 'ARCLK' - 12. Setup: 'DRCLK' - 13. Setup: 'C25M' - 14. Hold: 'ARCLK' - 15. Hold: 'DRCLK' - 16. Hold: 'C25M' - 17. Minimum Pulse Width: 'ARCLK' - 18. Minimum Pulse Width: 'DRCLK' - 19. Minimum Pulse Width: 'C25M' - 20. Setup Times - 21. Hold Times - 22. Clock to Output Times - 23. Minimum Clock to Output Times - 24. Propagation Delay - 25. Minimum Propagation Delay - 26. Output Enable Times - 27. Minimum Output Enable Times - 28. Output Disable Times - 29. Minimum Output Disable Times - 30. Setup Transfers - 31. Hold Transfers - 32. Report TCCS - 33. Report RSKM - 34. Unconstrained Paths - 35. TimeQuest Timing Analyzer Messages + 11. Setup: 'C25M' + 12. Hold: 'C25M' + 13. Minimum Pulse Width: 'C25M' + 14. Setup Times + 15. Hold Times + 16. Clock to Output Times + 17. Minimum Clock to Output Times + 18. Propagation Delay + 19. Minimum Propagation Delay + 20. Output Enable Times + 21. Minimum Output Enable Times + 22. Output Disable Times + 23. Minimum Output Disable Times + 24. Setup Transfers + 25. Hold Transfers + 26. Report TCCS + 27. Report RSKM + 28. Unconstrained Paths + 29. TimeQuest Timing Analyzer Messages @@ -93,15 +87,13 @@ applicable agreement for further details. +----------------------------+-------------+ -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Clocks ; -+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+ -; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; -+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+ -; ARCLK ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { ARCLK } ; -; C25M ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { C25M } ; -; DRCLK ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { DRCLK } ; -+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+ ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clocks ; ++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------+ +; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; ++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------+ +; C25M ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { C25M } ; ++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------+ +-------------------------------------------------+ @@ -109,33 +101,27 @@ applicable agreement for further details. +-----------+-----------------+------------+------+ ; Fmax ; Restricted Fmax ; Clock Name ; Note ; +-----------+-----------------+------------+------+ -; 10.0 MHz ; 10.0 MHz ; ARCLK ; ; -; 10.0 MHz ; 10.0 MHz ; DRCLK ; ; -; 94.36 MHz ; 94.36 MHz ; C25M ; ; +; 95.18 MHz ; 95.18 MHz ; C25M ; ; +-----------+-----------------+------------+------+ This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. -+---------------------------------+ -; Setup Summary ; -+-------+---------+---------------+ -; Clock ; Slack ; End Point TNS ; -+-------+---------+---------------+ -; ARCLK ; -99.000 ; -99.000 ; -; DRCLK ; -99.000 ; -99.000 ; -; C25M ; -9.598 ; -485.527 ; -+-------+---------+---------------+ ++--------------------------------+ +; Setup Summary ; ++-------+--------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-------+--------+---------------+ +; C25M ; -9.506 ; -540.769 ; ++-------+--------+---------------+ -+---------------------------------+ -; Hold Summary ; -+-------+---------+---------------+ -; Clock ; Slack ; End Point TNS ; -+-------+---------+---------------+ -; ARCLK ; -16.296 ; -16.296 ; -; DRCLK ; -16.276 ; -16.276 ; -; C25M ; -1.031 ; -1.031 ; -+-------+---------+---------------+ ++-------------------------------+ +; Hold Summary ; ++-------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-------+-------+---------------+ +; C25M ; 1.639 ; 0.000 ; ++-------+-------+---------------+ -------------------- @@ -150,407 +136,337 @@ No paths to report. No paths to report. -+---------------------------------+ -; Minimum Pulse Width Summary ; -+-------+---------+---------------+ -; Clock ; Slack ; End Point TNS ; -+-------+---------+---------------+ -; ARCLK ; -29.500 ; -59.000 ; -; DRCLK ; -29.500 ; -59.000 ; -; C25M ; -2.289 ; -2.289 ; -+-------+---------+---------------+ ++--------------------------------+ +; Minimum Pulse Width Summary ; ++-------+--------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-------+--------+---------------+ +; C25M ; -2.289 ; -2.289 ; ++-------+--------+---------------+ -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Setup: 'ARCLK' ; -+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -; -99.000 ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK ; ARCLK ; 1.000 ; 0.000 ; 80.000 ; -; -22.704 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C25M ; ARCLK ; 1.000 ; -2.175 ; 1.529 ; -+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ++------------------------------------------------------------------------------------------------------+ +; Setup: 'C25M' ; ++--------+-----------+-----------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+-----------+-----------+--------------+-------------+--------------+------------+------------+ +; -9.506 ; RAcur[2] ; Addr[11] ; C25M ; C25M ; 1.000 ; 0.000 ; 10.173 ; +; -9.506 ; RAcur[2] ; Addr[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 10.173 ; +; -9.506 ; RAcur[2] ; Addr[14] ; C25M ; C25M ; 1.000 ; 0.000 ; 10.173 ; +; -9.475 ; RAcur[8] ; Addr[20] ; C25M ; C25M ; 1.000 ; 0.000 ; 10.142 ; +; -9.425 ; RAcur[2] ; Addr[20] ; C25M ; C25M ; 1.000 ; 0.000 ; 10.092 ; +; -9.310 ; RAcur[11] ; Addr[20] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.977 ; +; -9.290 ; RAcur[8] ; Addr[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.957 ; +; -9.281 ; RAcur[0] ; Addr[11] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.948 ; +; -9.281 ; RAcur[0] ; Addr[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.948 ; +; -9.281 ; RAcur[0] ; Addr[14] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.948 ; +; -9.247 ; RAcur[8] ; Addr[11] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.914 ; +; -9.247 ; RAcur[8] ; Addr[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.914 ; +; -9.247 ; RAcur[8] ; Addr[14] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.914 ; +; -9.241 ; RAcur[0] ; nRCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.908 ; +; -9.240 ; RAcur[2] ; Addr[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.907 ; +; -9.207 ; RAcur[2] ; Addr[8] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.874 ; +; -9.207 ; RAcur[2] ; Addr[9] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.874 ; +; -9.207 ; RAcur[8] ; nRCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.874 ; +; -9.139 ; RAcur[2] ; Addr[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.806 ; +; -9.125 ; RAcur[11] ; Addr[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.792 ; +; -9.082 ; RAcur[11] ; Addr[11] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.749 ; +; -9.082 ; RAcur[11] ; Addr[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.749 ; +; -9.082 ; RAcur[11] ; Addr[14] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.749 ; +; -9.069 ; RAcur[2] ; Addr[13] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.736 ; +; -9.042 ; RAcur[11] ; nRCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.709 ; +; -9.038 ; RAcur[8] ; Addr[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.705 ; +; -9.008 ; RAcur[0] ; Addr[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.675 ; +; -9.008 ; RAcur[0] ; Addr[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.675 ; +; -9.008 ; RAcur[0] ; Addr[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.675 ; +; -9.007 ; RAcur[0] ; Addr[20] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.674 ; +; -8.982 ; RAcur[0] ; Addr[8] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.649 ; +; -8.982 ; RAcur[0] ; Addr[9] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.649 ; +; -8.978 ; RAcur[8] ; Addr[2] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.645 ; +; -8.978 ; RAcur[8] ; Addr[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.645 ; +; -8.974 ; RAcur[8] ; Addr[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.641 ; +; -8.974 ; RAcur[8] ; Addr[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.641 ; +; -8.974 ; RAcur[8] ; Addr[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.641 ; +; -8.948 ; RAcur[8] ; Addr[8] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.615 ; +; -8.948 ; RAcur[8] ; Addr[9] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.615 ; +; -8.928 ; RAcur[2] ; Addr[2] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.595 ; +; -8.928 ; RAcur[2] ; Addr[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.595 ; +; -8.910 ; RAcur[0] ; Addr[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.577 ; +; -8.873 ; RAcur[11] ; Addr[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.540 ; +; -8.844 ; RAcur[0] ; Addr[13] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.511 ; +; -8.843 ; RAcur[0] ; Addr[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.510 ; +; -8.838 ; RAcur[0] ; Addr[2] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.505 ; +; -8.819 ; RAcur[2] ; Addr[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.486 ; +; -8.813 ; RAcur[11] ; Addr[2] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.480 ; +; -8.813 ; RAcur[11] ; Addr[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.480 ; +; -8.810 ; RAcur[8] ; Addr[13] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.477 ; +; -8.809 ; RAcur[11] ; Addr[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.476 ; +; -8.809 ; RAcur[11] ; Addr[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.476 ; +; -8.809 ; RAcur[11] ; Addr[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.476 ; +; -8.789 ; RAcur[0] ; Addr[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.456 ; +; -8.783 ; RAcur[11] ; Addr[8] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.450 ; +; -8.783 ; RAcur[11] ; Addr[9] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.450 ; +; -8.781 ; RAcur[9] ; Addr[20] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.448 ; +; -8.771 ; RAcur[2] ; Addr[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.438 ; +; -8.750 ; RAcur[0] ; Addr[22] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.417 ; +; -8.716 ; RAcur[8] ; Addr[22] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.383 ; +; -8.649 ; nWEcur ; Addr[11] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.316 ; +; -8.649 ; nWEcur ; Addr[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.316 ; +; -8.649 ; nWEcur ; Addr[14] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.316 ; +; -8.645 ; RAcur[11] ; Addr[13] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.312 ; +; -8.623 ; RAcur[2] ; Addr[15] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.290 ; +; -8.596 ; RAcur[9] ; Addr[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.263 ; +; -8.592 ; RAcur[2] ; Addr[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.259 ; +; -8.587 ; RAcur[8] ; Addr[3] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.254 ; +; -8.587 ; RAcur[8] ; Addr[5] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.254 ; +; -8.568 ; nWEcur ; Addr[20] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.235 ; +; -8.553 ; RAcur[9] ; Addr[11] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.220 ; +; -8.553 ; RAcur[9] ; Addr[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.220 ; +; -8.553 ; RAcur[9] ; Addr[14] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.220 ; +; -8.551 ; RAcur[11] ; Addr[22] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.218 ; +; -8.541 ; RAcur[2] ; Addr[22] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.208 ; +; -8.540 ; RAcur[0] ; Addr[5] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.207 ; +; -8.539 ; RAcur[0] ; Addr[3] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.206 ; +; -8.537 ; RAcur[2] ; Addr[3] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.204 ; +; -8.537 ; RAcur[2] ; Addr[5] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.204 ; +; -8.518 ; RAcur[3] ; Addr[11] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.185 ; +; -8.518 ; RAcur[3] ; Addr[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.185 ; +; -8.518 ; RAcur[3] ; Addr[14] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.185 ; +; -8.513 ; RAcur[9] ; nRCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.180 ; +; -8.498 ; REGEN ; Addr[11] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.165 ; +; -8.498 ; REGEN ; Addr[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.165 ; +; -8.498 ; REGEN ; Addr[14] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.165 ; +; -8.478 ; RAcur[3] ; nRCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.145 ; +; -8.422 ; RAcur[1] ; Addr[11] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.089 ; +; -8.422 ; RAcur[1] ; Addr[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.089 ; +; -8.422 ; RAcur[1] ; Addr[14] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.089 ; +; -8.422 ; RAcur[11] ; Addr[3] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.089 ; +; -8.422 ; RAcur[11] ; Addr[5] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.089 ; +; -8.383 ; nWEcur ; Addr[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.050 ; +; -8.366 ; RAcur[0] ; nRAS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.033 ; +; -8.350 ; nWEcur ; Addr[8] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.017 ; +; -8.350 ; nWEcur ; Addr[9] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.017 ; +; -8.344 ; RAcur[9] ; Addr[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.011 ; +; -8.341 ; RAcur[1] ; Addr[20] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.008 ; +; -8.332 ; RAcur[8] ; nRAS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.999 ; +; -8.296 ; Addr[11] ; Addr[14] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.963 ; ++--------+-----------+-----------+--------------+-------------+--------------+------------+------------+ -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Setup: 'DRCLK' ; -+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -; -99.000 ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|wire_maxii_ufm_block1_drdout ; DRCLK ; DRCLK ; 1.000 ; 0.000 ; 80.000 ; -; -22.724 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|wire_maxii_ufm_block1_drdout ; C25M ; DRCLK ; 1.000 ; -2.195 ; 1.529 ; -+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ++-----------------------------------------------------------------------------------------------------------+ +; Hold: 'C25M' ; ++-------+--------------+--------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+--------------+--------------+--------------+-------------+--------------+------------+------------+ +; 1.639 ; RefReqd ; RefReqd ; C25M ; C25M ; 0.000 ; 0.000 ; 1.860 ; +; 1.649 ; LS[0] ; LS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.870 ; +; 1.658 ; LS[17] ; LS[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.879 ; +; 1.667 ; nRESout~reg0 ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 1.888 ; +; 1.715 ; PS[0] ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.936 ; +; 1.947 ; IOSELr ; REGEN ; C25M ; C25M ; 0.000 ; 0.000 ; 2.168 ; +; 1.947 ; nRESr0 ; nRESr ; C25M ; C25M ; -0.500 ; 0.000 ; 1.668 ; +; 1.989 ; PS[1] ; PS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.210 ; +; 2.015 ; PS[1] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.236 ; +; 2.108 ; LS[6] ; LS[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.329 ; +; 2.112 ; MOSIout ; WRD[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.333 ; +; 2.116 ; LS[9] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.337 ; +; 2.117 ; LS[16] ; LS[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; +; 2.117 ; LS[11] ; LS[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; +; 2.117 ; LS[10] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; +; 2.117 ; MOSIOE ; MOSIOE ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; +; 2.126 ; LS[1] ; LS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ; +; 2.135 ; LS[8] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.356 ; +; 2.149 ; IOSELr ; IOROMEN ; C25M ; C25M ; 0.000 ; 0.000 ; 2.370 ; +; 2.158 ; PS[2] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.379 ; +; 2.164 ; IOSELr0 ; IOSELr ; C25M ; C25M ; -0.500 ; 0.000 ; 1.885 ; +; 2.172 ; PS[2] ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.393 ; +; 2.223 ; PHI0r1 ; PHI0r2 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.444 ; +; 2.230 ; FCS ; FCS ; C25M ; C25M ; 0.000 ; 0.000 ; 2.451 ; +; 2.230 ; LS[4] ; LS[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.451 ; +; 2.231 ; LS[3] ; LS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; +; 2.231 ; LS[2] ; LS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; +; 2.231 ; LS[5] ; LS[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; +; 2.234 ; IOROMEN ; IOROMEN ; C25M ; C25M ; 0.000 ; 0.000 ; 2.455 ; +; 2.240 ; LS[7] ; LS[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.461 ; +; 2.241 ; LS[12] ; LS[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.462 ; +; 2.243 ; PS[0] ; Amux[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.464 ; +; 2.249 ; PS[0] ; RCKE~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.470 ; +; 2.249 ; LS[13] ; LS[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.470 ; +; 2.254 ; PS[0] ; nSWE~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.475 ; +; 2.260 ; LS[15] ; LS[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.481 ; +; 2.261 ; LS[14] ; LS[14] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.482 ; +; 2.295 ; PS[0] ; PS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.516 ; +; 2.308 ; PS[0] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.529 ; +; 2.321 ; MOSIOE ; WRD[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.542 ; +; 2.328 ; PS[1] ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.549 ; +; 2.381 ; nRESout~reg0 ; SDOE ; C25M ; C25M ; 0.000 ; 0.000 ; 2.602 ; +; 2.384 ; PHI0r1 ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.605 ; +; 2.386 ; nRESout~reg0 ; FCK~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.607 ; +; 2.555 ; LS[12] ; ARShift ; C25M ; C25M ; 0.000 ; 0.000 ; 2.776 ; +; 2.584 ; FCKEN ; FCK~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.805 ; +; 2.625 ; LS[0] ; FCK~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.846 ; +; 2.674 ; nRESout~reg0 ; MOSIOE ; C25M ; C25M ; 0.000 ; 0.000 ; 2.895 ; +; 2.713 ; SetLoaded ; DRShift ; C25M ; C25M ; 0.000 ; 0.000 ; 2.934 ; +; 2.715 ; PS[1] ; nCAS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.936 ; +; 2.718 ; PS[1] ; Amux[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.939 ; +; 2.723 ; PS[1] ; RCKE~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.944 ; +; 2.726 ; PS[1] ; nSWE~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.947 ; +; 2.752 ; LS[1] ; DRCLK ; C25M ; C25M ; 0.000 ; 0.000 ; 2.973 ; +; 2.765 ; PS[2] ; nSWE~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.986 ; +; 2.770 ; PS[2] ; RCKE~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.991 ; +; 2.773 ; PS[2] ; Amux[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.994 ; +; 2.888 ; PS[0] ; Amux[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.109 ; +; 2.940 ; LS[6] ; LS[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.161 ; +; 2.948 ; LS[9] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.169 ; +; 2.949 ; LS[11] ; LS[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; +; 2.949 ; LS[16] ; LS[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; +; 2.949 ; LS[10] ; LS[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; +; 2.958 ; LS[1] ; LS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.179 ; +; 3.034 ; PS[2] ; Amux[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.255 ; +; 3.051 ; LS[6] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.272 ; +; 3.059 ; LS[9] ; LS[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.280 ; +; 3.060 ; REGEN ; REGEN ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ; +; 3.060 ; LS[11] ; LS[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ; +; 3.060 ; LS[10] ; LS[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ; +; 3.069 ; LS[1] ; LS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.290 ; +; 3.112 ; DEVSELr0 ; DEVSELr ; C25M ; C25M ; -0.500 ; 0.000 ; 2.833 ; +; 3.128 ; Addr[5] ; Addr[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.349 ; +; 3.129 ; LS[12] ; ARCLK ; C25M ; C25M ; 0.000 ; 0.000 ; 3.350 ; +; 3.145 ; nRESout~reg0 ; FCKEN ; C25M ; C25M ; 0.000 ; 0.000 ; 3.366 ; +; 3.170 ; LS[4] ; LS[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.391 ; +; 3.170 ; LS[9] ; LS[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.391 ; +; 3.171 ; LS[5] ; LS[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.392 ; +; 3.171 ; LS[10] ; LS[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.392 ; +; 3.171 ; LS[2] ; LS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.392 ; +; 3.180 ; LS[7] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.401 ; +; 3.181 ; LS[12] ; LS[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.402 ; +; 3.191 ; LS[15] ; ARShift ; C25M ; C25M ; 0.000 ; 0.000 ; 3.412 ; +; 3.192 ; PS[1] ; Amux[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.413 ; +; 3.195 ; PS[1] ; Amux[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.416 ; +; 3.200 ; LS[15] ; LS[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.421 ; +; 3.201 ; LS[0] ; LS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.422 ; +; 3.201 ; LS[14] ; LS[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.422 ; +; 3.219 ; LS[1] ; ARCLK ; C25M ; C25M ; 0.000 ; 0.000 ; 3.440 ; +; 3.229 ; SetLoaded ; ARShift ; C25M ; C25M ; 0.000 ; 0.000 ; 3.450 ; +; 3.267 ; LS[1] ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.488 ; +; 3.281 ; LS[4] ; LS[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.502 ; +; 3.281 ; LS[9] ; LS[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.502 ; +; 3.282 ; LS[5] ; LS[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.503 ; +; 3.286 ; SetLoaded ; DRCLK ; C25M ; C25M ; 0.000 ; 0.000 ; 3.507 ; +; 3.290 ; LS[12] ; DRCLK ; C25M ; C25M ; 0.000 ; 0.000 ; 3.511 ; +; 3.306 ; nRESr ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.527 ; +; 3.311 ; LS[15] ; LS[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.532 ; +; 3.312 ; LS[14] ; LS[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.533 ; +; 3.324 ; LS[14] ; ARShift ; C25M ; C25M ; 0.000 ; 0.000 ; 3.545 ; ++-------+--------------+--------------+--------------+-------------+--------------+------------+------------+ -+---------------------------------------------------------------------------------------------------------+ -; Setup: 'C25M' ; -+--------+-----------+--------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+--------+-----------+--------------+--------------+-------------+--------------+------------+------------+ -; -9.598 ; RAcur[8] ; nRCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 10.265 ; -; -9.515 ; RAcur[8] ; RCKE~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 10.182 ; -; -9.377 ; RAcur[10] ; nRCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 10.044 ; -; -9.338 ; RAcur[8] ; nRAS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 10.005 ; -; -9.294 ; RAcur[10] ; RCKE~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.961 ; -; -9.232 ; RACr ; nRCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.899 ; -; -9.149 ; RACr ; RCKE~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.816 ; -; -9.117 ; RAcur[10] ; nRAS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.784 ; -; -9.117 ; RAcur[1] ; nRCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.784 ; -; -9.095 ; RAcur[9] ; nRCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.762 ; -; -9.034 ; RAcur[1] ; RCKE~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.701 ; -; -9.012 ; RAcur[9] ; RCKE~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.679 ; -; -8.972 ; RACr ; nRAS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.639 ; -; -8.879 ; LS[10] ; MOSIout ; C25M ; C25M ; 1.000 ; 0.000 ; 9.546 ; -; -8.857 ; RAcur[1] ; nRAS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.524 ; -; -8.835 ; RAcur[9] ; nRAS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.502 ; -; -8.807 ; LS[15] ; MOSIout ; C25M ; C25M ; 1.000 ; 0.000 ; 9.474 ; -; -8.710 ; LS[11] ; MOSIout ; C25M ; C25M ; 1.000 ; 0.000 ; 9.377 ; -; -8.657 ; LS[13] ; MOSIout ; C25M ; C25M ; 1.000 ; 0.000 ; 9.324 ; -; -8.578 ; RAcur[0] ; nRCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.245 ; -; -8.564 ; LS[9] ; MOSIout ; C25M ; C25M ; 1.000 ; 0.000 ; 9.231 ; -; -8.497 ; LS[12] ; MOSIout ; C25M ; C25M ; 1.000 ; 0.000 ; 9.164 ; -; -8.495 ; RAcur[0] ; RCKE~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.162 ; -; -8.486 ; LS[2] ; nRAS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.153 ; -; -8.462 ; LS[3] ; MOSIout ; C25M ; C25M ; 1.000 ; 0.000 ; 9.129 ; -; -8.318 ; RAcur[0] ; nRAS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.985 ; -; -8.310 ; LS[17] ; FCKEN ; C25M ; C25M ; 1.000 ; 0.000 ; 8.977 ; -; -8.276 ; RAcur[8] ; nCAS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.943 ; -; -8.260 ; InitActv ; nRCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.927 ; -; -8.200 ; LS[1] ; nRAS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.867 ; -; -8.195 ; PS[1] ; nRCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.862 ; -; -8.178 ; LS[10] ; IS[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.845 ; -; -8.174 ; LS[10] ; IS[1] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.841 ; -; -8.171 ; RAcur[11] ; nRCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.838 ; -; -8.166 ; LS[10] ; FCKEN ; C25M ; C25M ; 1.000 ; 0.000 ; 8.833 ; -; -8.124 ; LS[14] ; MOSIout ; C25M ; C25M ; 1.000 ; 0.000 ; 8.791 ; -; -8.106 ; LS[15] ; IS[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.773 ; -; -8.102 ; LS[15] ; IS[1] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.769 ; -; -8.088 ; RAcur[11] ; RCKE~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.755 ; -; -8.055 ; RAcur[10] ; nCAS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.722 ; -; -8.054 ; LS[2] ; MOSIout ; C25M ; C25M ; 1.000 ; 0.000 ; 8.721 ; -; -8.027 ; RAcur[7] ; nRCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.694 ; -; -8.009 ; LS[11] ; IS[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.676 ; -; -8.005 ; LS[11] ; IS[1] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.672 ; -; -7.996 ; LS[0] ; FCS ; C25M ; C25M ; 1.000 ; 0.000 ; 8.663 ; -; -7.980 ; LS[0] ; FCKEN ; C25M ; C25M ; 1.000 ; 0.000 ; 8.647 ; -; -7.973 ; LS[16] ; FCKEN ; C25M ; C25M ; 1.000 ; 0.000 ; 8.640 ; -; -7.956 ; LS[13] ; IS[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.623 ; -; -7.952 ; LS[13] ; IS[1] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.619 ; -; -7.950 ; LS[10] ; FCS ; C25M ; C25M ; 1.000 ; 0.000 ; 8.617 ; -; -7.944 ; RAcur[7] ; RCKE~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.611 ; -; -7.942 ; IS[0] ; nRCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.609 ; -; -7.933 ; LS[10] ; ARCLK ; C25M ; C25M ; 1.000 ; 0.000 ; 8.600 ; -; -7.911 ; RAcur[11] ; nRAS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.578 ; -; -7.910 ; RACr ; nCAS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.577 ; -; -7.905 ; LS[15] ; FCKEN ; C25M ; C25M ; 1.000 ; 0.000 ; 8.572 ; -; -7.889 ; RAcur[2] ; nRCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.556 ; -; -7.878 ; LS[15] ; FCS ; C25M ; C25M ; 1.000 ; 0.000 ; 8.545 ; -; -7.863 ; LS[9] ; IS[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.530 ; -; -7.859 ; LS[9] ; IS[1] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.526 ; -; -7.842 ; nWEcur ; RCKE~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.509 ; -; -7.817 ; LS[5] ; FCKEN ; C25M ; C25M ; 1.000 ; 0.000 ; 8.484 ; -; -7.813 ; PS[3] ; RCKE~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.480 ; -; -7.812 ; LS[8] ; MOSIout ; C25M ; C25M ; 1.000 ; 0.000 ; 8.479 ; -; -7.808 ; LS[11] ; FCKEN ; C25M ; C25M ; 1.000 ; 0.000 ; 8.475 ; -; -7.806 ; RAcur[2] ; RCKE~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.473 ; -; -7.800 ; LS[2] ; nRCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.467 ; -; -7.796 ; LS[12] ; IS[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.463 ; -; -7.795 ; LS[17] ; MOSIout ; C25M ; C25M ; 1.000 ; 0.000 ; 8.462 ; -; -7.795 ; RAcur[1] ; nCAS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.462 ; -; -7.792 ; LS[12] ; IS[1] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.459 ; -; -7.786 ; PHI0r2 ; nRCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.453 ; -; -7.781 ; LS[11] ; FCS ; C25M ; C25M ; 1.000 ; 0.000 ; 8.448 ; -; -7.773 ; RAcur[9] ; nCAS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.440 ; -; -7.767 ; RAcur[7] ; nRAS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.434 ; -; -7.765 ; LS[4] ; MOSIout ; C25M ; C25M ; 1.000 ; 0.000 ; 8.432 ; -; -7.764 ; LS[11] ; ARCLK ; C25M ; C25M ; 1.000 ; 0.000 ; 8.431 ; -; -7.755 ; LS[13] ; FCKEN ; C25M ; C25M ; 1.000 ; 0.000 ; 8.422 ; -; -7.736 ; LS[17] ; nRESout~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.403 ; -; -7.728 ; LS[13] ; FCS ; C25M ; C25M ; 1.000 ; 0.000 ; 8.395 ; -; -7.704 ; PS[3] ; IOROMEN ; C25M ; C25M ; 1.000 ; 0.000 ; 8.371 ; -; -7.704 ; LS[9] ; FCKEN ; C25M ; C25M ; 1.000 ; 0.000 ; 8.371 ; -; -7.698 ; PS[3] ; REGEN ; C25M ; C25M ; 1.000 ; 0.000 ; 8.365 ; -; -7.691 ; LS[6] ; MOSIout ; C25M ; C25M ; 1.000 ; 0.000 ; 8.358 ; -; -7.677 ; InitActv ; nRAS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.344 ; -; -7.672 ; LS[2] ; FCS ; C25M ; C25M ; 1.000 ; 0.000 ; 8.339 ; -; -7.662 ; PS[2] ; nRCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.329 ; -; -7.656 ; LS[2] ; FCKEN ; C25M ; C25M ; 1.000 ; 0.000 ; 8.323 ; -; -7.635 ; LS[9] ; FCS ; C25M ; C25M ; 1.000 ; 0.000 ; 8.302 ; -; -7.631 ; LS[10] ; SetFW[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.298 ; -; -7.631 ; LS[10] ; SetFW[1] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.298 ; -; -7.629 ; RAcur[2] ; nRAS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.296 ; -; -7.629 ; PHI0r1 ; nRCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.296 ; -; -7.622 ; LS[0] ; MOSIOE ; C25M ; C25M ; 1.000 ; 0.000 ; 8.289 ; -; -7.618 ; LS[9] ; ARCLK ; C25M ; C25M ; 1.000 ; 0.000 ; 8.285 ; -; -7.612 ; PS[1] ; nRAS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.279 ; -; -7.612 ; LS[10] ; MOSIOE ; C25M ; C25M ; 1.000 ; 0.000 ; 8.279 ; -; -7.608 ; LS[0] ; nBODf ; C25M ; C25M ; 1.000 ; 0.000 ; 8.275 ; -; -7.595 ; LS[12] ; FCKEN ; C25M ; C25M ; 1.000 ; 0.000 ; 8.262 ; -; -7.592 ; LS[10] ; nRESout~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.259 ; -+--------+-----------+--------------+--------------+-------------+--------------+------------+------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Hold: 'ARCLK' ; -+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -; -16.296 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C25M ; ARCLK ; 0.000 ; -2.175 ; 1.529 ; -; 60.000 ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK ; ARCLK ; 0.000 ; 0.000 ; 80.000 ; -+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Hold: 'DRCLK' ; -+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -; -16.276 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|wire_maxii_ufm_block1_drdout ; C25M ; DRCLK ; 0.000 ; -2.195 ; 1.529 ; -; 60.000 ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|wire_maxii_ufm_block1_drdout ; DRCLK ; DRCLK ; 0.000 ; 0.000 ; 80.000 ; -+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ - - -+------------------------------------------------------------------------------------------------------------+ -; Hold: 'C25M' ; -+--------+--------------+--------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+--------+--------------+--------------+--------------+-------------+--------------+------------+------------+ -; -1.031 ; ARCLK ; ARCLK ; ARCLK ; C25M ; 0.000 ; 3.348 ; 2.914 ; -; -0.531 ; ARCLK ; ARCLK ; ARCLK ; C25M ; -0.500 ; 3.348 ; 2.914 ; -; 1.646 ; IOSELr ; IOROMEN ; C25M ; C25M ; 0.000 ; 0.000 ; 1.867 ; -; 1.661 ; FCKEN ; FCK~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 1.882 ; -; 1.670 ; LS[17] ; LS[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.891 ; -; 1.687 ; PS[2] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.908 ; -; 1.787 ; PHI0r1 ; PHI0r2 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.008 ; -; 1.877 ; nBODr0 ; nBODr ; C25M ; C25M ; -0.500 ; 0.000 ; 1.598 ; -; 1.886 ; IOSELr0 ; IOSELr ; C25M ; C25M ; -0.500 ; 0.000 ; 1.607 ; -; 1.980 ; PS[0] ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.201 ; -; 2.009 ; SetLoaded ; ARShift ; C25M ; C25M ; 0.000 ; 0.000 ; 2.230 ; -; 2.027 ; SetLoaded ; DRShift ; C25M ; C25M ; 0.000 ; 0.000 ; 2.248 ; -; 2.055 ; IOSELr ; REGEN ; C25M ; C25M ; 0.000 ; 0.000 ; 2.276 ; -; 2.065 ; nBODf0 ; nBODf ; C25M ; C25M ; 0.000 ; 0.000 ; 2.286 ; -; 2.081 ; SDRAMActv ; RefReqd ; C25M ; C25M ; 0.000 ; 0.000 ; 2.302 ; -; 2.108 ; LS[6] ; LS[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.329 ; -; 2.120 ; nBODf ; InitActv ; C25M ; C25M ; 0.000 ; 0.000 ; 2.341 ; -; 2.125 ; LS[9] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.346 ; -; 2.126 ; LS[1] ; LS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ; -; 2.126 ; MOSIOE ; MOSIOE ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ; -; 2.135 ; InitIntr ; InitIntr ; C25M ; C25M ; 0.000 ; 0.000 ; 2.356 ; -; 2.137 ; LS[8] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.358 ; -; 2.137 ; LS[16] ; LS[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.358 ; -; 2.143 ; LS[10] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.364 ; -; 2.145 ; LS[11] ; LS[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.366 ; -; 2.152 ; PS[1] ; PS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.373 ; -; 2.212 ; nRESout~reg0 ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.433 ; -; 2.212 ; FCS ; FCS ; C25M ; C25M ; 0.000 ; 0.000 ; 2.433 ; -; 2.221 ; LS[7] ; LS[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.442 ; -; 2.221 ; LS[2] ; LS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.442 ; -; 2.230 ; LS[12] ; LS[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.451 ; -; 2.230 ; LS[14] ; LS[14] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.451 ; -; 2.230 ; LS[4] ; LS[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.451 ; -; 2.230 ; InitActv ; InitActv ; C25M ; C25M ; 0.000 ; 0.000 ; 2.451 ; -; 2.230 ; RefReqd ; RefReqd ; C25M ; C25M ; 0.000 ; 0.000 ; 2.451 ; -; 2.230 ; SetFW[0] ; SetFW[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.451 ; -; 2.231 ; LS[15] ; LS[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; -; 2.231 ; LS[13] ; LS[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; -; 2.231 ; LS[5] ; LS[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; -; 2.231 ; LS[3] ; LS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; -; 2.232 ; IOROMEN ; IOROMEN ; C25M ; C25M ; 0.000 ; 0.000 ; 2.453 ; -; 2.241 ; IS[1] ; IS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.462 ; -; 2.250 ; nCAS~reg0 ; nCAS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.471 ; -; 2.317 ; PS[0] ; PS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.538 ; -; 2.339 ; SetLoaded ; SetLoaded ; C25M ; C25M ; 0.000 ; 0.000 ; 2.560 ; -; 2.345 ; SetLoaded ; DRCLK ; C25M ; C25M ; 0.000 ; 0.000 ; 2.566 ; -; 2.349 ; SetLoaded ; ARCLK ; C25M ; C25M ; 0.000 ; 0.000 ; 2.570 ; -; 2.357 ; nBODf ; InitIntr ; C25M ; C25M ; 0.000 ; 0.000 ; 2.578 ; -; 2.362 ; nBODf ; SDRAMActv ; C25M ; C25M ; 0.000 ; 0.000 ; 2.583 ; -; 2.380 ; nRESr ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.601 ; -; 2.411 ; LS[0] ; LS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.632 ; -; 2.570 ; nBODf ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.791 ; -; 2.581 ; PS[3] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.802 ; -; 2.659 ; REGEN ; REGEN ; C25M ; C25M ; 0.000 ; 0.000 ; 2.880 ; -; 2.669 ; SDRAMActv ; SDRAMActv ; C25M ; C25M ; 0.000 ; 0.000 ; 2.890 ; -; 2.715 ; InitIntr ; SDRAMActv ; C25M ; C25M ; 0.000 ; 0.000 ; 2.936 ; -; 2.804 ; nBODr ; nBODf0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.025 ; -; 2.932 ; PS[1] ; nCAS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.153 ; -; 2.940 ; LS[6] ; LS[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.161 ; -; 2.957 ; LS[9] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.178 ; -; 2.958 ; LS[1] ; LS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.179 ; -; 2.969 ; LS[16] ; LS[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.190 ; -; 2.973 ; LS[5] ; RefReqd ; C25M ; C25M ; 0.000 ; 0.000 ; 3.194 ; -; 2.975 ; LS[10] ; LS[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.196 ; -; 2.977 ; LS[11] ; LS[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.198 ; -; 2.977 ; InitActv ; SDRAMActv ; C25M ; C25M ; 0.000 ; 0.000 ; 3.198 ; -; 3.012 ; PHI0r0 ; PHI0r1 ; C25M ; C25M ; -0.500 ; 0.000 ; 2.733 ; -; 3.051 ; LS[6] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.272 ; -; 3.057 ; DEVSELr0 ; DEVSELr ; C25M ; C25M ; -0.500 ; 0.000 ; 2.778 ; -; 3.068 ; LS[9] ; LS[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.289 ; -; 3.069 ; LS[1] ; LS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.290 ; -; 3.080 ; PS[2] ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.301 ; -; 3.086 ; LS[10] ; LS[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.307 ; -; 3.088 ; LS[11] ; LS[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.309 ; -; 3.119 ; nRESr ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.340 ; -; 3.126 ; nRESr ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.347 ; -; 3.128 ; nRESr ; PS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.349 ; -; 3.145 ; InitIntr ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.366 ; -; 3.160 ; PS[3] ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.381 ; -; 3.161 ; LS[7] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.382 ; -; 3.161 ; LS[2] ; LS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.382 ; -; 3.167 ; nRAS~reg0 ; nRAS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.388 ; -; 3.170 ; LS[14] ; LS[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.391 ; -; 3.170 ; LS[4] ; LS[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.391 ; -; 3.170 ; LS[12] ; LS[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.391 ; -; 3.171 ; LS[5] ; LS[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.392 ; -; 3.171 ; LS[15] ; LS[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.392 ; -; 3.179 ; LS[9] ; LS[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.400 ; -; 3.197 ; LS[10] ; LS[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.418 ; -; 3.281 ; LS[4] ; LS[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.502 ; -; 3.281 ; LS[14] ; LS[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.502 ; -; 3.282 ; LS[5] ; LS[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.503 ; -; 3.282 ; LS[15] ; LS[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.503 ; -; 3.290 ; LS[9] ; LS[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.511 ; -; 3.316 ; FCKEN ; FCKEN ; C25M ; C25M ; 0.000 ; 0.000 ; 3.537 ; -; 3.361 ; LS[1] ; WRD[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.582 ; -; 3.363 ; PS[2] ; RCKE~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.584 ; -; 3.384 ; LS[0] ; LS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.605 ; -; 3.392 ; LS[4] ; LS[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.613 ; -; 3.392 ; LS[14] ; LS[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.613 ; -+--------+--------------+--------------+--------------+-------------+--------------+------------+------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Minimum Pulse Width: 'ARCLK' ; -+---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------------------+ -; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; -+---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------------------+ -; -29.500 ; 0.500 ; 30.000 ; High Pulse Width ; ARCLK ; Rise ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; -; -29.500 ; 0.500 ; 30.000 ; Low Pulse Width ; ARCLK ; Rise ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; ARCLK ; Rise ; ARCLK|regout ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; ARCLK ; Rise ; ARCLK|regout ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; ARCLK ; Rise ; UFM_inst|UFM_altufm_none_0ep_component|maxii_ufm_block1|arclk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; ARCLK ; Rise ; UFM_inst|UFM_altufm_none_0ep_component|maxii_ufm_block1|arclk ; -+---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Minimum Pulse Width: 'DRCLK' ; -+---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------+ -; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; -+---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------+ -; -29.500 ; 0.500 ; 30.000 ; High Pulse Width ; DRCLK ; Rise ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|wire_maxii_ufm_block1_drdout ; -; -29.500 ; 0.500 ; 30.000 ; Low Pulse Width ; DRCLK ; Rise ; UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component|wire_maxii_ufm_block1_drdout ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; DRCLK ; Rise ; DRCLK|regout ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; DRCLK ; Rise ; DRCLK|regout ; -; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; DRCLK ; Rise ; UFM_inst|UFM_altufm_none_0ep_component|maxii_ufm_block1|drclk ; -; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; DRCLK ; Rise ; UFM_inst|UFM_altufm_none_0ep_component|maxii_ufm_block1|drclk ; -+---------+--------------+----------------+------------------+-------+------------+---------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------+ -; Minimum Pulse Width: 'C25M' ; -+--------+--------------+----------------+------------------+-------+------------+-----------+ -; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; -+--------+--------------+----------------+------------------+-------+------------+-----------+ -; -2.289 ; 1.000 ; 3.289 ; Port Rate ; C25M ; Rise ; C25M ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; ARCLK ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; ARCLK ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; ARShift ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; ARShift ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; DEVSELr ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; DEVSELr ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Fall ; DEVSELr0 ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Fall ; DEVSELr0 ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; DRCLK ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; DRCLK ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; DRShift ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; DRShift ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; FCKEN ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; FCKEN ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; FCK~reg0 ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; FCK~reg0 ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; FCS ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; FCS ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; IOROMEN ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; IOROMEN ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; IOSELr ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; IOSELr ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Fall ; IOSELr0 ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Fall ; IOSELr0 ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; IOSTRBr ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; IOSTRBr ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Fall ; IOSTRBr0 ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Fall ; IOSTRBr0 ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; IS[0] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; IS[0] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; IS[1] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; IS[1] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; InitActv ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; InitActv ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; InitIntr ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; InitIntr ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[0] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[0] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[10] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[10] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[11] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[11] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[12] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[12] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[13] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[13] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[14] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[14] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[15] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[15] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[16] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[16] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[17] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[17] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[1] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[1] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[2] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[2] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[3] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[3] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[4] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[4] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[5] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[5] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[6] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[6] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[7] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[7] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[8] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[8] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[9] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[9] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; MOSIOE ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; MOSIOE ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; MOSIout ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; MOSIout ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Fall ; PHI0r0 ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Fall ; PHI0r0 ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; PHI0r1 ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; PHI0r1 ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; PHI0r2 ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; PHI0r2 ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; PS[0] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; PS[0] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; PS[1] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; PS[1] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; PS[2] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; PS[2] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; PS[3] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; PS[3] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; RACr ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; RACr ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; RAcur[0] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; RAcur[0] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; RAcur[10] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; RAcur[10] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; RAcur[11] ; -; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; RAcur[11] ; -; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; RAcur[1] ; -+--------+--------------+----------------+------------------+-------+------------+-----------+ ++-------------------------------------------------------------------------------------------+ +; Minimum Pulse Width: 'C25M' ; ++--------+--------------+----------------+------------------+-------+------------+----------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++--------+--------------+----------------+------------------+-------+------------+----------+ +; -2.289 ; 1.000 ; 3.289 ; Port Rate ; C25M ; Rise ; C25M ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; ARCLK ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; ARCLK ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; ARShift ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; ARShift ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[0] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[0] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[10] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[10] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[11] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[11] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[12] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[12] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[13] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[13] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[14] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[14] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[15] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[15] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[16] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[16] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[17] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[17] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[18] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[18] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[19] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[19] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[1] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[1] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[20] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[20] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[21] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[21] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[22] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[22] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[2] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[2] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[3] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[3] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[4] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[4] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[5] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[5] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[6] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[6] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[7] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[7] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[8] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[8] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Addr[9] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Addr[9] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Amux[0] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Amux[0] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Amux[1] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Amux[1] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Amux[2] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Amux[2] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Bank[0] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Bank[0] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; Bank[1] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; Bank[1] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; DEVSELr ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; DEVSELr ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Fall ; DEVSELr0 ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Fall ; DEVSELr0 ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; DRCLK ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; DRCLK ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; DRShift ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; DRShift ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; FCKEN ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; FCKEN ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; FCK~reg0 ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; FCK~reg0 ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; FCS ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; FCS ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; IOROMEN ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; IOROMEN ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; IOSELr ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; IOSELr ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Fall ; IOSELr0 ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Fall ; IOSELr0 ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; IOSTRBr ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; IOSTRBr ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Fall ; IOSTRBr0 ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Fall ; IOSTRBr0 ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[0] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[0] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[10] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[10] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[11] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[11] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[12] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[12] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[13] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[13] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[14] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[14] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[15] ; +; 0.234 ; 0.500 ; 0.266 ; Low Pulse Width ; C25M ; Rise ; LS[15] ; +; 0.234 ; 0.500 ; 0.266 ; High Pulse Width ; C25M ; Rise ; LS[16] ; ++--------+--------------+----------------+------------------+-------+------------+----------+ +-----------------------------------------------------------------------+ @@ -558,40 +474,39 @@ No paths to report. +-----------+------------+-------+-------+------------+-----------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+-------+-------+------------+-----------------+ -; MISO ; C25M ; 3.547 ; 3.547 ; Rise ; C25M ; -; RA[*] ; C25M ; 3.862 ; 3.862 ; Rise ; C25M ; -; RA[0] ; C25M ; 2.127 ; 2.127 ; Rise ; C25M ; -; RA[1] ; C25M ; 2.953 ; 2.953 ; Rise ; C25M ; -; RA[2] ; C25M ; 2.929 ; 2.929 ; Rise ; C25M ; -; RA[3] ; C25M ; 2.446 ; 2.446 ; Rise ; C25M ; -; RA[4] ; C25M ; 1.926 ; 1.926 ; Rise ; C25M ; -; RA[5] ; C25M ; 1.793 ; 1.793 ; Rise ; C25M ; -; RA[6] ; C25M ; 2.659 ; 2.659 ; Rise ; C25M ; -; RA[7] ; C25M ; 1.849 ; 1.849 ; Rise ; C25M ; -; RA[8] ; C25M ; 2.684 ; 2.684 ; Rise ; C25M ; -; RA[9] ; C25M ; 2.694 ; 2.694 ; Rise ; C25M ; -; RA[10] ; C25M ; 2.926 ; 2.926 ; Rise ; C25M ; -; RA[11] ; C25M ; 2.456 ; 2.456 ; Rise ; C25M ; -; RA[12] ; C25M ; 3.512 ; 3.512 ; Rise ; C25M ; -; RA[13] ; C25M ; 3.862 ; 3.862 ; Rise ; C25M ; -; RA[14] ; C25M ; 2.029 ; 2.029 ; Rise ; C25M ; -; RA[15] ; C25M ; 3.701 ; 3.701 ; Rise ; C25M ; -; RD[*] ; C25M ; 4.042 ; 4.042 ; Rise ; C25M ; -; RD[0] ; C25M ; 2.631 ; 2.631 ; Rise ; C25M ; -; RD[1] ; C25M ; 2.789 ; 2.789 ; Rise ; C25M ; -; RD[2] ; C25M ; 1.817 ; 1.817 ; Rise ; C25M ; -; RD[3] ; C25M ; 2.669 ; 2.669 ; Rise ; C25M ; -; RD[4] ; C25M ; 2.027 ; 2.027 ; Rise ; C25M ; -; RD[5] ; C25M ; 1.833 ; 1.833 ; Rise ; C25M ; -; RD[6] ; C25M ; 4.042 ; 4.042 ; Rise ; C25M ; -; RD[7] ; C25M ; 2.990 ; 2.990 ; Rise ; C25M ; -; nWE ; C25M ; 2.526 ; 2.526 ; Rise ; C25M ; -; PHI0 ; C25M ; 2.666 ; 2.666 ; Fall ; C25M ; -; nBOD ; C25M ; 2.626 ; 2.626 ; Fall ; C25M ; -; nDEVSEL ; C25M ; 2.111 ; 2.111 ; Fall ; C25M ; -; nIOSEL ; C25M ; 2.125 ; 2.125 ; Fall ; C25M ; -; nIOSTRB ; C25M ; 2.393 ; 2.393 ; Fall ; C25M ; -; nRES ; C25M ; 2.421 ; 2.421 ; Fall ; C25M ; +; MISO ; C25M ; 2.730 ; 2.730 ; Rise ; C25M ; +; RA[*] ; C25M ; 4.937 ; 4.937 ; Rise ; C25M ; +; RA[0] ; C25M ; 2.787 ; 2.787 ; Rise ; C25M ; +; RA[1] ; C25M ; 2.712 ; 2.712 ; Rise ; C25M ; +; RA[2] ; C25M ; 3.301 ; 3.301 ; Rise ; C25M ; +; RA[3] ; C25M ; 2.682 ; 2.682 ; Rise ; C25M ; +; RA[4] ; C25M ; 2.473 ; 2.473 ; Rise ; C25M ; +; RA[5] ; C25M ; 2.473 ; 2.473 ; Rise ; C25M ; +; RA[6] ; C25M ; 2.746 ; 2.746 ; Rise ; C25M ; +; RA[7] ; C25M ; 4.349 ; 4.349 ; Rise ; C25M ; +; RA[8] ; C25M ; 1.883 ; 1.883 ; Rise ; C25M ; +; RA[9] ; C25M ; 2.487 ; 2.487 ; Rise ; C25M ; +; RA[10] ; C25M ; 1.880 ; 1.880 ; Rise ; C25M ; +; RA[11] ; C25M ; 2.745 ; 2.745 ; Rise ; C25M ; +; RA[12] ; C25M ; 4.937 ; 4.937 ; Rise ; C25M ; +; RA[13] ; C25M ; 3.478 ; 3.478 ; Rise ; C25M ; +; RA[14] ; C25M ; 3.854 ; 3.854 ; Rise ; C25M ; +; RA[15] ; C25M ; 4.767 ; 4.767 ; Rise ; C25M ; +; RD[*] ; C25M ; 8.623 ; 8.623 ; Rise ; C25M ; +; RD[0] ; C25M ; 4.967 ; 4.967 ; Rise ; C25M ; +; RD[1] ; C25M ; 5.394 ; 5.394 ; Rise ; C25M ; +; RD[2] ; C25M ; 8.623 ; 8.623 ; Rise ; C25M ; +; RD[3] ; C25M ; 4.531 ; 4.531 ; Rise ; C25M ; +; RD[4] ; C25M ; 6.378 ; 6.378 ; Rise ; C25M ; +; RD[5] ; C25M ; 5.642 ; 5.642 ; Rise ; C25M ; +; RD[6] ; C25M ; 4.500 ; 4.500 ; Rise ; C25M ; +; RD[7] ; C25M ; 8.385 ; 8.385 ; Rise ; C25M ; +; nWE ; C25M ; 2.477 ; 2.477 ; Rise ; C25M ; +; PHI0 ; C25M ; 2.525 ; 2.525 ; Fall ; C25M ; +; nDEVSEL ; C25M ; 3.234 ; 3.234 ; Fall ; C25M ; +; nIOSEL ; C25M ; 2.372 ; 2.372 ; Fall ; C25M ; +; nIOSTRB ; C25M ; 3.449 ; 3.449 ; Fall ; C25M ; +; nRES ; C25M ; 2.075 ; 2.075 ; Fall ; C25M ; +-----------+------------+-------+-------+------------+-----------------+ @@ -600,40 +515,39 @@ No paths to report. +-----------+------------+--------+--------+------------+-----------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+--------+--------+------------+-----------------+ -; MISO ; C25M ; -2.993 ; -2.993 ; Rise ; C25M ; -; RA[*] ; C25M ; -1.239 ; -1.239 ; Rise ; C25M ; -; RA[0] ; C25M ; -1.573 ; -1.573 ; Rise ; C25M ; -; RA[1] ; C25M ; -2.399 ; -2.399 ; Rise ; C25M ; -; RA[2] ; C25M ; -2.375 ; -2.375 ; Rise ; C25M ; -; RA[3] ; C25M ; -1.892 ; -1.892 ; Rise ; C25M ; -; RA[4] ; C25M ; -1.372 ; -1.372 ; Rise ; C25M ; -; RA[5] ; C25M ; -1.239 ; -1.239 ; Rise ; C25M ; -; RA[6] ; C25M ; -2.105 ; -2.105 ; Rise ; C25M ; -; RA[7] ; C25M ; -1.295 ; -1.295 ; Rise ; C25M ; -; RA[8] ; C25M ; -2.130 ; -2.130 ; Rise ; C25M ; -; RA[9] ; C25M ; -2.140 ; -2.140 ; Rise ; C25M ; -; RA[10] ; C25M ; -2.372 ; -2.372 ; Rise ; C25M ; -; RA[11] ; C25M ; -1.902 ; -1.902 ; Rise ; C25M ; -; RA[12] ; C25M ; -2.958 ; -2.958 ; Rise ; C25M ; -; RA[13] ; C25M ; -3.308 ; -3.308 ; Rise ; C25M ; -; RA[14] ; C25M ; -1.475 ; -1.475 ; Rise ; C25M ; -; RA[15] ; C25M ; -3.147 ; -3.147 ; Rise ; C25M ; -; RD[*] ; C25M ; -1.263 ; -1.263 ; Rise ; C25M ; -; RD[0] ; C25M ; -2.077 ; -2.077 ; Rise ; C25M ; -; RD[1] ; C25M ; -2.235 ; -2.235 ; Rise ; C25M ; -; RD[2] ; C25M ; -1.263 ; -1.263 ; Rise ; C25M ; -; RD[3] ; C25M ; -2.115 ; -2.115 ; Rise ; C25M ; -; RD[4] ; C25M ; -1.473 ; -1.473 ; Rise ; C25M ; -; RD[5] ; C25M ; -1.279 ; -1.279 ; Rise ; C25M ; -; RD[6] ; C25M ; -3.488 ; -3.488 ; Rise ; C25M ; -; RD[7] ; C25M ; -2.436 ; -2.436 ; Rise ; C25M ; -; nWE ; C25M ; -1.972 ; -1.972 ; Rise ; C25M ; -; PHI0 ; C25M ; -2.112 ; -2.112 ; Fall ; C25M ; -; nBOD ; C25M ; -2.072 ; -2.072 ; Fall ; C25M ; -; nDEVSEL ; C25M ; -1.557 ; -1.557 ; Fall ; C25M ; -; nIOSEL ; C25M ; -1.571 ; -1.571 ; Fall ; C25M ; -; nIOSTRB ; C25M ; -1.839 ; -1.839 ; Fall ; C25M ; -; nRES ; C25M ; -1.867 ; -1.867 ; Fall ; C25M ; +; MISO ; C25M ; -2.176 ; -2.176 ; Rise ; C25M ; +; RA[*] ; C25M ; -1.326 ; -1.326 ; Rise ; C25M ; +; RA[0] ; C25M ; -2.233 ; -2.233 ; Rise ; C25M ; +; RA[1] ; C25M ; -2.158 ; -2.158 ; Rise ; C25M ; +; RA[2] ; C25M ; -2.747 ; -2.747 ; Rise ; C25M ; +; RA[3] ; C25M ; -2.128 ; -2.128 ; Rise ; C25M ; +; RA[4] ; C25M ; -1.919 ; -1.919 ; Rise ; C25M ; +; RA[5] ; C25M ; -1.919 ; -1.919 ; Rise ; C25M ; +; RA[6] ; C25M ; -2.192 ; -2.192 ; Rise ; C25M ; +; RA[7] ; C25M ; -3.795 ; -3.795 ; Rise ; C25M ; +; RA[8] ; C25M ; -1.329 ; -1.329 ; Rise ; C25M ; +; RA[9] ; C25M ; -1.933 ; -1.933 ; Rise ; C25M ; +; RA[10] ; C25M ; -1.326 ; -1.326 ; Rise ; C25M ; +; RA[11] ; C25M ; -2.191 ; -2.191 ; Rise ; C25M ; +; RA[12] ; C25M ; -4.383 ; -4.383 ; Rise ; C25M ; +; RA[13] ; C25M ; -2.924 ; -2.924 ; Rise ; C25M ; +; RA[14] ; C25M ; -3.300 ; -3.300 ; Rise ; C25M ; +; RA[15] ; C25M ; -4.213 ; -4.213 ; Rise ; C25M ; +; RD[*] ; C25M ; -2.174 ; -2.174 ; Rise ; C25M ; +; RD[0] ; C25M ; -2.174 ; -2.174 ; Rise ; C25M ; +; RD[1] ; C25M ; -2.540 ; -2.540 ; Rise ; C25M ; +; RD[2] ; C25M ; -2.456 ; -2.456 ; Rise ; C25M ; +; RD[3] ; C25M ; -2.232 ; -2.232 ; Rise ; C25M ; +; RD[4] ; C25M ; -3.100 ; -3.100 ; Rise ; C25M ; +; RD[5] ; C25M ; -2.977 ; -2.977 ; Rise ; C25M ; +; RD[6] ; C25M ; -3.098 ; -3.098 ; Rise ; C25M ; +; RD[7] ; C25M ; -3.202 ; -3.202 ; Rise ; C25M ; +; nWE ; C25M ; -1.923 ; -1.923 ; Rise ; C25M ; +; PHI0 ; C25M ; -1.971 ; -1.971 ; Fall ; C25M ; +; nDEVSEL ; C25M ; -2.680 ; -2.680 ; Fall ; C25M ; +; nIOSEL ; C25M ; -1.818 ; -1.818 ; Fall ; C25M ; +; nIOSTRB ; C25M ; -2.895 ; -2.895 ; Fall ; C25M ; +; nRES ; C25M ; -1.521 ; -1.521 ; Fall ; C25M ; +-----------+------------+--------+--------+------------+-----------------+ @@ -642,34 +556,52 @@ No paths to report. +-----------+------------+--------+--------+------------+-----------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+--------+--------+------------+-----------------+ -; FCK ; C25M ; 6.814 ; 6.814 ; Rise ; C25M ; -; MOSI ; C25M ; 9.054 ; 9.054 ; Rise ; C25M ; -; RCKE ; C25M ; 8.111 ; 8.111 ; Rise ; C25M ; -; RD[*] ; C25M ; 14.025 ; 14.025 ; Rise ; C25M ; -; RD[0] ; C25M ; 13.989 ; 13.989 ; Rise ; C25M ; -; RD[1] ; C25M ; 13.989 ; 13.989 ; Rise ; C25M ; -; RD[2] ; C25M ; 14.025 ; 14.025 ; Rise ; C25M ; -; RD[3] ; C25M ; 13.564 ; 13.564 ; Rise ; C25M ; -; RD[4] ; C25M ; 14.025 ; 14.025 ; Rise ; C25M ; -; RD[5] ; C25M ; 14.025 ; 14.025 ; Rise ; C25M ; -; RD[6] ; C25M ; 13.564 ; 13.564 ; Rise ; C25M ; -; RD[7] ; C25M ; 14.005 ; 14.005 ; Rise ; C25M ; -; RDdir ; C25M ; 13.564 ; 13.564 ; Rise ; C25M ; -; SD[*] ; C25M ; 8.201 ; 8.201 ; Rise ; C25M ; -; SD[0] ; C25M ; 8.201 ; 8.201 ; Rise ; C25M ; -; SD[1] ; C25M ; 8.097 ; 8.097 ; Rise ; C25M ; -; SD[2] ; C25M ; 8.090 ; 8.090 ; Rise ; C25M ; -; SD[3] ; C25M ; 8.137 ; 8.137 ; Rise ; C25M ; -; SD[4] ; C25M ; 8.111 ; 8.111 ; Rise ; C25M ; -; SD[5] ; C25M ; 8.101 ; 8.101 ; Rise ; C25M ; -; SD[6] ; C25M ; 6.820 ; 6.820 ; Rise ; C25M ; -; SD[7] ; C25M ; 6.820 ; 6.820 ; Rise ; C25M ; -; nCAS ; C25M ; 8.703 ; 8.703 ; Rise ; C25M ; -; nFCS ; C25M ; 8.534 ; 8.534 ; Rise ; C25M ; -; nRAS ; C25M ; 8.131 ; 8.131 ; Rise ; C25M ; -; nRCS ; C25M ; 6.859 ; 6.859 ; Rise ; C25M ; -; nRESout ; C25M ; 7.478 ; 7.478 ; Rise ; C25M ; -; nSWE ; C25M ; 6.827 ; 6.827 ; Rise ; C25M ; +; DQMH ; C25M ; 12.172 ; 12.172 ; Rise ; C25M ; +; DQML ; C25M ; 12.191 ; 12.191 ; Rise ; C25M ; +; FCK ; C25M ; 6.853 ; 6.853 ; Rise ; C25M ; +; MOSI ; C25M ; 7.987 ; 7.987 ; Rise ; C25M ; +; RCKE ; C25M ; 7.918 ; 7.918 ; Rise ; C25M ; +; RD[*] ; C25M ; 13.512 ; 13.512 ; Rise ; C25M ; +; RD[0] ; C25M ; 13.512 ; 13.512 ; Rise ; C25M ; +; RD[1] ; C25M ; 12.527 ; 12.527 ; Rise ; C25M ; +; RD[2] ; C25M ; 13.043 ; 13.043 ; Rise ; C25M ; +; RD[3] ; C25M ; 13.512 ; 13.512 ; Rise ; C25M ; +; RD[4] ; C25M ; 13.512 ; 13.512 ; Rise ; C25M ; +; RD[5] ; C25M ; 13.043 ; 13.043 ; Rise ; C25M ; +; RD[6] ; C25M ; 13.512 ; 13.512 ; Rise ; C25M ; +; RD[7] ; C25M ; 12.527 ; 12.527 ; Rise ; C25M ; +; RDdir ; C25M ; 13.043 ; 13.043 ; Rise ; C25M ; +; SA[*] ; C25M ; 16.756 ; 16.756 ; Rise ; C25M ; +; SA[0] ; C25M ; 16.756 ; 16.756 ; Rise ; C25M ; +; SA[1] ; C25M ; 13.973 ; 13.973 ; Rise ; C25M ; +; SA[2] ; C25M ; 16.541 ; 16.541 ; Rise ; C25M ; +; SA[3] ; C25M ; 15.322 ; 15.322 ; Rise ; C25M ; +; SA[4] ; C25M ; 15.597 ; 15.597 ; Rise ; C25M ; +; SA[5] ; C25M ; 13.493 ; 13.493 ; Rise ; C25M ; +; SA[6] ; C25M ; 12.412 ; 12.412 ; Rise ; C25M ; +; SA[7] ; C25M ; 13.879 ; 13.879 ; Rise ; C25M ; +; SA[8] ; C25M ; 14.066 ; 14.066 ; Rise ; C25M ; +; SA[9] ; C25M ; 12.811 ; 12.811 ; Rise ; C25M ; +; SA[10] ; C25M ; 13.571 ; 13.571 ; Rise ; C25M ; +; SA[11] ; C25M ; 13.522 ; 13.522 ; Rise ; C25M ; +; SA[12] ; C25M ; 11.810 ; 11.810 ; Rise ; C25M ; +; SBA[*] ; C25M ; 11.477 ; 11.477 ; Rise ; C25M ; +; SBA[1] ; C25M ; 11.477 ; 11.477 ; Rise ; C25M ; +; SD[*] ; C25M ; 9.110 ; 9.110 ; Rise ; C25M ; +; SD[0] ; C25M ; 8.588 ; 8.588 ; Rise ; C25M ; +; SD[1] ; C25M ; 8.588 ; 8.588 ; Rise ; C25M ; +; SD[2] ; C25M ; 8.688 ; 8.688 ; Rise ; C25M ; +; SD[3] ; C25M ; 9.110 ; 9.110 ; Rise ; C25M ; +; SD[4] ; C25M ; 8.588 ; 8.588 ; Rise ; C25M ; +; SD[5] ; C25M ; 8.688 ; 8.688 ; Rise ; C25M ; +; SD[6] ; C25M ; 6.847 ; 6.847 ; Rise ; C25M ; +; SD[7] ; C25M ; 6.848 ; 6.848 ; Rise ; C25M ; +; nCAS ; C25M ; 8.531 ; 8.531 ; Rise ; C25M ; +; nFCS ; C25M ; 6.820 ; 6.820 ; Rise ; C25M ; +; nRAS ; C25M ; 8.122 ; 8.122 ; Rise ; C25M ; +; nRCS ; C25M ; 6.813 ; 6.813 ; Rise ; C25M ; +; nRESout ; C25M ; 9.088 ; 9.088 ; Rise ; C25M ; +; nSWE ; C25M ; 7.886 ; 7.886 ; Rise ; C25M ; +-----------+------------+--------+--------+------------+-----------------+ @@ -678,34 +610,52 @@ No paths to report. +-----------+------------+--------+--------+------------+-----------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+--------+--------+------------+-----------------+ -; FCK ; C25M ; 6.814 ; 6.814 ; Rise ; C25M ; -; MOSI ; C25M ; 9.054 ; 9.054 ; Rise ; C25M ; -; RCKE ; C25M ; 8.111 ; 8.111 ; Rise ; C25M ; -; RD[*] ; C25M ; 10.614 ; 10.614 ; Rise ; C25M ; -; RD[0] ; C25M ; 11.039 ; 11.039 ; Rise ; C25M ; -; RD[1] ; C25M ; 11.039 ; 11.039 ; Rise ; C25M ; -; RD[2] ; C25M ; 11.075 ; 11.075 ; Rise ; C25M ; -; RD[3] ; C25M ; 10.614 ; 10.614 ; Rise ; C25M ; -; RD[4] ; C25M ; 11.075 ; 11.075 ; Rise ; C25M ; -; RD[5] ; C25M ; 11.075 ; 11.075 ; Rise ; C25M ; -; RD[6] ; C25M ; 10.614 ; 10.614 ; Rise ; C25M ; -; RD[7] ; C25M ; 11.055 ; 11.055 ; Rise ; C25M ; -; RDdir ; C25M ; 10.614 ; 10.614 ; Rise ; C25M ; -; SD[*] ; C25M ; 6.820 ; 6.820 ; Rise ; C25M ; -; SD[0] ; C25M ; 8.201 ; 8.201 ; Rise ; C25M ; -; SD[1] ; C25M ; 8.097 ; 8.097 ; Rise ; C25M ; -; SD[2] ; C25M ; 8.090 ; 8.090 ; Rise ; C25M ; -; SD[3] ; C25M ; 8.137 ; 8.137 ; Rise ; C25M ; -; SD[4] ; C25M ; 8.111 ; 8.111 ; Rise ; C25M ; -; SD[5] ; C25M ; 8.101 ; 8.101 ; Rise ; C25M ; -; SD[6] ; C25M ; 6.820 ; 6.820 ; Rise ; C25M ; -; SD[7] ; C25M ; 6.820 ; 6.820 ; Rise ; C25M ; -; nCAS ; C25M ; 8.703 ; 8.703 ; Rise ; C25M ; -; nFCS ; C25M ; 8.534 ; 8.534 ; Rise ; C25M ; -; nRAS ; C25M ; 8.131 ; 8.131 ; Rise ; C25M ; -; nRCS ; C25M ; 6.859 ; 6.859 ; Rise ; C25M ; -; nRESout ; C25M ; 7.478 ; 7.478 ; Rise ; C25M ; -; nSWE ; C25M ; 6.827 ; 6.827 ; Rise ; C25M ; +; DQMH ; C25M ; 9.531 ; 9.531 ; Rise ; C25M ; +; DQML ; C25M ; 9.550 ; 9.550 ; Rise ; C25M ; +; FCK ; C25M ; 6.853 ; 6.853 ; Rise ; C25M ; +; MOSI ; C25M ; 7.987 ; 7.987 ; Rise ; C25M ; +; RCKE ; C25M ; 7.918 ; 7.918 ; Rise ; C25M ; +; RD[*] ; C25M ; 9.051 ; 9.051 ; Rise ; C25M ; +; RD[0] ; C25M ; 10.036 ; 10.036 ; Rise ; C25M ; +; RD[1] ; C25M ; 9.051 ; 9.051 ; Rise ; C25M ; +; RD[2] ; C25M ; 9.567 ; 9.567 ; Rise ; C25M ; +; RD[3] ; C25M ; 10.036 ; 10.036 ; Rise ; C25M ; +; RD[4] ; C25M ; 10.036 ; 10.036 ; Rise ; C25M ; +; RD[5] ; C25M ; 9.567 ; 9.567 ; Rise ; C25M ; +; RD[6] ; C25M ; 10.036 ; 10.036 ; Rise ; C25M ; +; RD[7] ; C25M ; 9.051 ; 9.051 ; Rise ; C25M ; +; RDdir ; C25M ; 9.567 ; 9.567 ; Rise ; C25M ; +; SA[*] ; C25M ; 9.091 ; 9.091 ; Rise ; C25M ; +; SA[0] ; C25M ; 11.423 ; 11.423 ; Rise ; C25M ; +; SA[1] ; C25M ; 10.716 ; 10.716 ; Rise ; C25M ; +; SA[2] ; C25M ; 12.021 ; 12.021 ; Rise ; C25M ; +; SA[3] ; C25M ; 11.889 ; 11.889 ; Rise ; C25M ; +; SA[4] ; C25M ; 10.185 ; 10.185 ; Rise ; C25M ; +; SA[5] ; C25M ; 10.027 ; 10.027 ; Rise ; C25M ; +; SA[6] ; C25M ; 9.091 ; 9.091 ; Rise ; C25M ; +; SA[7] ; C25M ; 10.026 ; 10.026 ; Rise ; C25M ; +; SA[8] ; C25M ; 10.534 ; 10.534 ; Rise ; C25M ; +; SA[9] ; C25M ; 9.380 ; 9.380 ; Rise ; C25M ; +; SA[10] ; C25M ; 10.249 ; 10.249 ; Rise ; C25M ; +; SA[11] ; C25M ; 10.200 ; 10.200 ; Rise ; C25M ; +; SA[12] ; C25M ; 10.171 ; 10.171 ; Rise ; C25M ; +; SBA[*] ; C25M ; 10.707 ; 10.707 ; Rise ; C25M ; +; SBA[1] ; C25M ; 10.707 ; 10.707 ; Rise ; C25M ; +; SD[*] ; C25M ; 6.847 ; 6.847 ; Rise ; C25M ; +; SD[0] ; C25M ; 8.588 ; 8.588 ; Rise ; C25M ; +; SD[1] ; C25M ; 8.588 ; 8.588 ; Rise ; C25M ; +; SD[2] ; C25M ; 8.688 ; 8.688 ; Rise ; C25M ; +; SD[3] ; C25M ; 9.110 ; 9.110 ; Rise ; C25M ; +; SD[4] ; C25M ; 8.588 ; 8.588 ; Rise ; C25M ; +; SD[5] ; C25M ; 8.688 ; 8.688 ; Rise ; C25M ; +; SD[6] ; C25M ; 6.847 ; 6.847 ; Rise ; C25M ; +; SD[7] ; C25M ; 6.848 ; 6.848 ; Rise ; C25M ; +; nCAS ; C25M ; 8.531 ; 8.531 ; Rise ; C25M ; +; nFCS ; C25M ; 6.820 ; 6.820 ; Rise ; C25M ; +; nRAS ; C25M ; 8.122 ; 8.122 ; Rise ; C25M ; +; nRCS ; C25M ; 6.813 ; 6.813 ; Rise ; C25M ; +; nRESout ; C25M ; 9.088 ; 9.088 ; Rise ; C25M ; +; nSWE ; C25M ; 7.886 ; 7.886 ; Rise ; C25M ; +-----------+------------+--------+--------+------------+-----------------+ @@ -714,51 +664,51 @@ No paths to report. +------------+-------------+--------+----+----+--------+ ; Input Port ; Output Port ; RR ; RF ; FR ; FF ; +------------+-------------+--------+----+----+--------+ -; PHI0 ; RD[0] ; 13.206 ; ; ; 13.206 ; -; PHI0 ; RD[1] ; 13.206 ; ; ; 13.206 ; -; PHI0 ; RD[2] ; 13.242 ; ; ; 13.242 ; -; PHI0 ; RD[3] ; 12.781 ; ; ; 12.781 ; -; PHI0 ; RD[4] ; 13.242 ; ; ; 13.242 ; -; PHI0 ; RD[5] ; 13.242 ; ; ; 13.242 ; -; PHI0 ; RD[6] ; 12.781 ; ; ; 12.781 ; -; PHI0 ; RD[7] ; 13.222 ; ; ; 13.222 ; -; PHI0 ; RDdir ; 12.781 ; ; ; 12.781 ; -; nDEVSEL ; RD[0] ; 11.475 ; ; ; 11.475 ; -; nDEVSEL ; RD[1] ; 11.475 ; ; ; 11.475 ; -; nDEVSEL ; RD[2] ; 11.511 ; ; ; 11.511 ; -; nDEVSEL ; RD[3] ; 11.050 ; ; ; 11.050 ; -; nDEVSEL ; RD[4] ; 11.511 ; ; ; 11.511 ; -; nDEVSEL ; RD[5] ; 11.511 ; ; ; 11.511 ; -; nDEVSEL ; RD[6] ; 11.050 ; ; ; 11.050 ; -; nDEVSEL ; RD[7] ; 11.491 ; ; ; 11.491 ; -; nDEVSEL ; RDdir ; 11.050 ; ; ; 11.050 ; -; nIOSEL ; RD[0] ; 10.201 ; ; ; 10.201 ; -; nIOSEL ; RD[1] ; 10.201 ; ; ; 10.201 ; -; nIOSEL ; RD[2] ; 10.237 ; ; ; 10.237 ; -; nIOSEL ; RD[3] ; 9.776 ; ; ; 9.776 ; -; nIOSEL ; RD[4] ; 10.237 ; ; ; 10.237 ; -; nIOSEL ; RD[5] ; 10.237 ; ; ; 10.237 ; -; nIOSEL ; RD[6] ; 9.776 ; ; ; 9.776 ; -; nIOSEL ; RD[7] ; 10.217 ; ; ; 10.217 ; -; nIOSEL ; RDdir ; 9.776 ; ; ; 9.776 ; -; nIOSTRB ; RD[0] ; 11.644 ; ; ; 11.644 ; -; nIOSTRB ; RD[1] ; 11.644 ; ; ; 11.644 ; -; nIOSTRB ; RD[2] ; 11.680 ; ; ; 11.680 ; -; nIOSTRB ; RD[3] ; 11.219 ; ; ; 11.219 ; -; nIOSTRB ; RD[4] ; 11.680 ; ; ; 11.680 ; -; nIOSTRB ; RD[5] ; 11.680 ; ; ; 11.680 ; -; nIOSTRB ; RD[6] ; 11.219 ; ; ; 11.219 ; -; nIOSTRB ; RD[7] ; 11.660 ; ; ; 11.660 ; -; nIOSTRB ; RDdir ; 11.219 ; ; ; 11.219 ; -; nWE ; RD[0] ; 14.484 ; ; ; 14.484 ; -; nWE ; RD[1] ; 14.484 ; ; ; 14.484 ; -; nWE ; RD[2] ; 14.520 ; ; ; 14.520 ; -; nWE ; RD[3] ; 14.059 ; ; ; 14.059 ; -; nWE ; RD[4] ; 14.520 ; ; ; 14.520 ; -; nWE ; RD[5] ; 14.520 ; ; ; 14.520 ; -; nWE ; RD[6] ; 14.059 ; ; ; 14.059 ; -; nWE ; RD[7] ; 14.500 ; ; ; 14.500 ; -; nWE ; RDdir ; 14.059 ; ; ; 14.059 ; +; PHI0 ; RD[0] ; 14.757 ; ; ; 14.757 ; +; PHI0 ; RD[1] ; 13.772 ; ; ; 13.772 ; +; PHI0 ; RD[2] ; 14.288 ; ; ; 14.288 ; +; PHI0 ; RD[3] ; 14.757 ; ; ; 14.757 ; +; PHI0 ; RD[4] ; 14.757 ; ; ; 14.757 ; +; PHI0 ; RD[5] ; 14.288 ; ; ; 14.288 ; +; PHI0 ; RD[6] ; 14.757 ; ; ; 14.757 ; +; PHI0 ; RD[7] ; 13.772 ; ; ; 13.772 ; +; PHI0 ; RDdir ; 14.288 ; ; ; 14.288 ; +; nDEVSEL ; RD[0] ; 13.880 ; ; ; 13.880 ; +; nDEVSEL ; RD[1] ; 12.895 ; ; ; 12.895 ; +; nDEVSEL ; RD[2] ; 13.411 ; ; ; 13.411 ; +; nDEVSEL ; RD[3] ; 13.880 ; ; ; 13.880 ; +; nDEVSEL ; RD[4] ; 13.880 ; ; ; 13.880 ; +; nDEVSEL ; RD[5] ; 13.411 ; ; ; 13.411 ; +; nDEVSEL ; RD[6] ; 13.880 ; ; ; 13.880 ; +; nDEVSEL ; RD[7] ; 12.895 ; ; ; 12.895 ; +; nDEVSEL ; RDdir ; 13.411 ; ; ; 13.411 ; +; nIOSEL ; RD[0] ; 11.646 ; ; ; 11.646 ; +; nIOSEL ; RD[1] ; 10.661 ; ; ; 10.661 ; +; nIOSEL ; RD[2] ; 11.177 ; ; ; 11.177 ; +; nIOSEL ; RD[3] ; 11.646 ; ; ; 11.646 ; +; nIOSEL ; RD[4] ; 11.646 ; ; ; 11.646 ; +; nIOSEL ; RD[5] ; 11.177 ; ; ; 11.177 ; +; nIOSEL ; RD[6] ; 11.646 ; ; ; 11.646 ; +; nIOSEL ; RD[7] ; 10.661 ; ; ; 10.661 ; +; nIOSEL ; RDdir ; 11.177 ; ; ; 11.177 ; +; nIOSTRB ; RD[0] ; 12.844 ; ; ; 12.844 ; +; nIOSTRB ; RD[1] ; 11.859 ; ; ; 11.859 ; +; nIOSTRB ; RD[2] ; 12.375 ; ; ; 12.375 ; +; nIOSTRB ; RD[3] ; 12.844 ; ; ; 12.844 ; +; nIOSTRB ; RD[4] ; 12.844 ; ; ; 12.844 ; +; nIOSTRB ; RD[5] ; 12.375 ; ; ; 12.375 ; +; nIOSTRB ; RD[6] ; 12.844 ; ; ; 12.844 ; +; nIOSTRB ; RD[7] ; 11.859 ; ; ; 11.859 ; +; nIOSTRB ; RDdir ; 12.375 ; ; ; 12.375 ; +; nWE ; RD[0] ; 13.939 ; ; ; 13.939 ; +; nWE ; RD[1] ; 12.954 ; ; ; 12.954 ; +; nWE ; RD[2] ; 13.470 ; ; ; 13.470 ; +; nWE ; RD[3] ; 13.939 ; ; ; 13.939 ; +; nWE ; RD[4] ; 13.939 ; ; ; 13.939 ; +; nWE ; RD[5] ; 13.470 ; ; ; 13.470 ; +; nWE ; RD[6] ; 13.939 ; ; ; 13.939 ; +; nWE ; RD[7] ; 12.954 ; ; ; 12.954 ; +; nWE ; RDdir ; 13.470 ; ; ; 13.470 ; +------------+-------------+--------+----+----+--------+ @@ -767,51 +717,51 @@ No paths to report. +------------+-------------+--------+----+----+--------+ ; Input Port ; Output Port ; RR ; RF ; FR ; FF ; +------------+-------------+--------+----+----+--------+ -; PHI0 ; RD[0] ; 13.206 ; ; ; 13.206 ; -; PHI0 ; RD[1] ; 13.206 ; ; ; 13.206 ; -; PHI0 ; RD[2] ; 13.242 ; ; ; 13.242 ; -; PHI0 ; RD[3] ; 12.781 ; ; ; 12.781 ; -; PHI0 ; RD[4] ; 13.242 ; ; ; 13.242 ; -; PHI0 ; RD[5] ; 13.242 ; ; ; 13.242 ; -; PHI0 ; RD[6] ; 12.781 ; ; ; 12.781 ; -; PHI0 ; RD[7] ; 13.222 ; ; ; 13.222 ; -; PHI0 ; RDdir ; 12.781 ; ; ; 12.781 ; -; nDEVSEL ; RD[0] ; 11.475 ; ; ; 11.475 ; -; nDEVSEL ; RD[1] ; 11.475 ; ; ; 11.475 ; -; nDEVSEL ; RD[2] ; 11.511 ; ; ; 11.511 ; -; nDEVSEL ; RD[3] ; 11.050 ; ; ; 11.050 ; -; nDEVSEL ; RD[4] ; 11.511 ; ; ; 11.511 ; -; nDEVSEL ; RD[5] ; 11.511 ; ; ; 11.511 ; -; nDEVSEL ; RD[6] ; 11.050 ; ; ; 11.050 ; -; nDEVSEL ; RD[7] ; 11.491 ; ; ; 11.491 ; -; nDEVSEL ; RDdir ; 11.050 ; ; ; 11.050 ; -; nIOSEL ; RD[0] ; 10.201 ; ; ; 10.201 ; -; nIOSEL ; RD[1] ; 10.201 ; ; ; 10.201 ; -; nIOSEL ; RD[2] ; 10.237 ; ; ; 10.237 ; -; nIOSEL ; RD[3] ; 9.776 ; ; ; 9.776 ; -; nIOSEL ; RD[4] ; 10.237 ; ; ; 10.237 ; -; nIOSEL ; RD[5] ; 10.237 ; ; ; 10.237 ; -; nIOSEL ; RD[6] ; 9.776 ; ; ; 9.776 ; -; nIOSEL ; RD[7] ; 10.217 ; ; ; 10.217 ; -; nIOSEL ; RDdir ; 9.776 ; ; ; 9.776 ; -; nIOSTRB ; RD[0] ; 11.644 ; ; ; 11.644 ; -; nIOSTRB ; RD[1] ; 11.644 ; ; ; 11.644 ; -; nIOSTRB ; RD[2] ; 11.680 ; ; ; 11.680 ; -; nIOSTRB ; RD[3] ; 11.219 ; ; ; 11.219 ; -; nIOSTRB ; RD[4] ; 11.680 ; ; ; 11.680 ; -; nIOSTRB ; RD[5] ; 11.680 ; ; ; 11.680 ; -; nIOSTRB ; RD[6] ; 11.219 ; ; ; 11.219 ; -; nIOSTRB ; RD[7] ; 11.660 ; ; ; 11.660 ; -; nIOSTRB ; RDdir ; 11.219 ; ; ; 11.219 ; -; nWE ; RD[0] ; 14.484 ; ; ; 14.484 ; -; nWE ; RD[1] ; 14.484 ; ; ; 14.484 ; -; nWE ; RD[2] ; 14.520 ; ; ; 14.520 ; -; nWE ; RD[3] ; 14.059 ; ; ; 14.059 ; -; nWE ; RD[4] ; 14.520 ; ; ; 14.520 ; -; nWE ; RD[5] ; 14.520 ; ; ; 14.520 ; -; nWE ; RD[6] ; 14.059 ; ; ; 14.059 ; -; nWE ; RD[7] ; 14.500 ; ; ; 14.500 ; -; nWE ; RDdir ; 14.059 ; ; ; 14.059 ; +; PHI0 ; RD[0] ; 14.757 ; ; ; 14.757 ; +; PHI0 ; RD[1] ; 13.772 ; ; ; 13.772 ; +; PHI0 ; RD[2] ; 14.288 ; ; ; 14.288 ; +; PHI0 ; RD[3] ; 14.757 ; ; ; 14.757 ; +; PHI0 ; RD[4] ; 14.757 ; ; ; 14.757 ; +; PHI0 ; RD[5] ; 14.288 ; ; ; 14.288 ; +; PHI0 ; RD[6] ; 14.757 ; ; ; 14.757 ; +; PHI0 ; RD[7] ; 13.772 ; ; ; 13.772 ; +; PHI0 ; RDdir ; 14.288 ; ; ; 14.288 ; +; nDEVSEL ; RD[0] ; 13.880 ; ; ; 13.880 ; +; nDEVSEL ; RD[1] ; 12.895 ; ; ; 12.895 ; +; nDEVSEL ; RD[2] ; 13.411 ; ; ; 13.411 ; +; nDEVSEL ; RD[3] ; 13.880 ; ; ; 13.880 ; +; nDEVSEL ; RD[4] ; 13.880 ; ; ; 13.880 ; +; nDEVSEL ; RD[5] ; 13.411 ; ; ; 13.411 ; +; nDEVSEL ; RD[6] ; 13.880 ; ; ; 13.880 ; +; nDEVSEL ; RD[7] ; 12.895 ; ; ; 12.895 ; +; nDEVSEL ; RDdir ; 13.411 ; ; ; 13.411 ; +; nIOSEL ; RD[0] ; 11.646 ; ; ; 11.646 ; +; nIOSEL ; RD[1] ; 10.661 ; ; ; 10.661 ; +; nIOSEL ; RD[2] ; 11.177 ; ; ; 11.177 ; +; nIOSEL ; RD[3] ; 11.646 ; ; ; 11.646 ; +; nIOSEL ; RD[4] ; 11.646 ; ; ; 11.646 ; +; nIOSEL ; RD[5] ; 11.177 ; ; ; 11.177 ; +; nIOSEL ; RD[6] ; 11.646 ; ; ; 11.646 ; +; nIOSEL ; RD[7] ; 10.661 ; ; ; 10.661 ; +; nIOSEL ; RDdir ; 11.177 ; ; ; 11.177 ; +; nIOSTRB ; RD[0] ; 12.844 ; ; ; 12.844 ; +; nIOSTRB ; RD[1] ; 11.859 ; ; ; 11.859 ; +; nIOSTRB ; RD[2] ; 12.375 ; ; ; 12.375 ; +; nIOSTRB ; RD[3] ; 12.844 ; ; ; 12.844 ; +; nIOSTRB ; RD[4] ; 12.844 ; ; ; 12.844 ; +; nIOSTRB ; RD[5] ; 12.375 ; ; ; 12.375 ; +; nIOSTRB ; RD[6] ; 12.844 ; ; ; 12.844 ; +; nIOSTRB ; RD[7] ; 11.859 ; ; ; 11.859 ; +; nIOSTRB ; RDdir ; 12.375 ; ; ; 12.375 ; +; nWE ; RD[0] ; 13.939 ; ; ; 13.939 ; +; nWE ; RD[1] ; 12.954 ; ; ; 12.954 ; +; nWE ; RD[2] ; 13.470 ; ; ; 13.470 ; +; nWE ; RD[3] ; 13.939 ; ; ; 13.939 ; +; nWE ; RD[4] ; 13.939 ; ; ; 13.939 ; +; nWE ; RD[5] ; 13.470 ; ; ; 13.470 ; +; nWE ; RD[6] ; 13.939 ; ; ; 13.939 ; +; nWE ; RD[7] ; 12.954 ; ; ; 12.954 ; +; nWE ; RDdir ; 13.470 ; ; ; 13.470 ; +------------+-------------+--------+----+----+--------+ @@ -820,16 +770,10 @@ No paths to report. +-----------+------------+-------+------+------------+-----------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+-------+------+------------+-----------------+ -; MOSI ; C25M ; 8.354 ; ; Rise ; C25M ; -; SD[*] ; C25M ; 6.777 ; ; Rise ; C25M ; -; SD[0] ; C25M ; 7.423 ; ; Rise ; C25M ; -; SD[1] ; C25M ; 6.983 ; ; Rise ; C25M ; -; SD[2] ; C25M ; 6.983 ; ; Rise ; C25M ; -; SD[3] ; C25M ; 7.423 ; ; Rise ; C25M ; -; SD[4] ; C25M ; 6.983 ; ; Rise ; C25M ; -; SD[5] ; C25M ; 6.983 ; ; Rise ; C25M ; -; SD[6] ; C25M ; 6.777 ; ; Rise ; C25M ; -; SD[7] ; C25M ; 6.777 ; ; Rise ; C25M ; +; MOSI ; C25M ; 6.777 ; ; Rise ; C25M ; +; SD[*] ; C25M ; 6.957 ; ; Rise ; C25M ; +; SD[6] ; C25M ; 6.957 ; ; Rise ; C25M ; +; SD[7] ; C25M ; 6.957 ; ; Rise ; C25M ; +-----------+------------+-------+------+------------+-----------------+ @@ -838,16 +782,10 @@ No paths to report. +-----------+------------+-------+------+------------+-----------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+-------+------+------------+-----------------+ -; MOSI ; C25M ; 8.354 ; ; Rise ; C25M ; -; SD[*] ; C25M ; 6.777 ; ; Rise ; C25M ; -; SD[0] ; C25M ; 7.423 ; ; Rise ; C25M ; -; SD[1] ; C25M ; 6.983 ; ; Rise ; C25M ; -; SD[2] ; C25M ; 6.983 ; ; Rise ; C25M ; -; SD[3] ; C25M ; 7.423 ; ; Rise ; C25M ; -; SD[4] ; C25M ; 6.983 ; ; Rise ; C25M ; -; SD[5] ; C25M ; 6.983 ; ; Rise ; C25M ; -; SD[6] ; C25M ; 6.777 ; ; Rise ; C25M ; -; SD[7] ; C25M ; 6.777 ; ; Rise ; C25M ; +; MOSI ; C25M ; 6.777 ; ; Rise ; C25M ; +; SD[*] ; C25M ; 6.957 ; ; Rise ; C25M ; +; SD[6] ; C25M ; 6.957 ; ; Rise ; C25M ; +; SD[7] ; C25M ; 6.957 ; ; Rise ; C25M ; +-----------+------------+-------+------+------------+-----------------+ @@ -856,16 +794,10 @@ No paths to report. +-----------+------------+-----------+-----------+------------+-----------------+ ; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; +-----------+------------+-----------+-----------+------------+-----------------+ -; MOSI ; C25M ; 8.354 ; ; Rise ; C25M ; -; SD[*] ; C25M ; 6.777 ; ; Rise ; C25M ; -; SD[0] ; C25M ; 7.423 ; ; Rise ; C25M ; -; SD[1] ; C25M ; 6.983 ; ; Rise ; C25M ; -; SD[2] ; C25M ; 6.983 ; ; Rise ; C25M ; -; SD[3] ; C25M ; 7.423 ; ; Rise ; C25M ; -; SD[4] ; C25M ; 6.983 ; ; Rise ; C25M ; -; SD[5] ; C25M ; 6.983 ; ; Rise ; C25M ; -; SD[6] ; C25M ; 6.777 ; ; Rise ; C25M ; -; SD[7] ; C25M ; 6.777 ; ; Rise ; C25M ; +; MOSI ; C25M ; 6.777 ; ; Rise ; C25M ; +; SD[*] ; C25M ; 6.957 ; ; Rise ; C25M ; +; SD[6] ; C25M ; 6.957 ; ; Rise ; C25M ; +; SD[7] ; C25M ; 6.957 ; ; Rise ; C25M ; +-----------+------------+-----------+-----------+------------+-----------------+ @@ -874,16 +806,10 @@ No paths to report. +-----------+------------+-----------+-----------+------------+-----------------+ ; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; +-----------+------------+-----------+-----------+------------+-----------------+ -; MOSI ; C25M ; 8.354 ; ; Rise ; C25M ; -; SD[*] ; C25M ; 6.777 ; ; Rise ; C25M ; -; SD[0] ; C25M ; 7.423 ; ; Rise ; C25M ; -; SD[1] ; C25M ; 6.983 ; ; Rise ; C25M ; -; SD[2] ; C25M ; 6.983 ; ; Rise ; C25M ; -; SD[3] ; C25M ; 7.423 ; ; Rise ; C25M ; -; SD[4] ; C25M ; 6.983 ; ; Rise ; C25M ; -; SD[5] ; C25M ; 6.983 ; ; Rise ; C25M ; -; SD[6] ; C25M ; 6.777 ; ; Rise ; C25M ; -; SD[7] ; C25M ; 6.777 ; ; Rise ; C25M ; +; MOSI ; C25M ; 6.777 ; ; Rise ; C25M ; +; SD[*] ; C25M ; 6.957 ; ; Rise ; C25M ; +; SD[6] ; C25M ; 6.957 ; ; Rise ; C25M ; +; SD[7] ; C25M ; 6.957 ; ; Rise ; C25M ; +-----------+------------+-----------+-----------+------------+-----------------+ @@ -892,13 +818,7 @@ No paths to report. +------------+----------+----------+----------+----------+----------+ ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; +------------+----------+----------+----------+----------+----------+ -; ARCLK ; ARCLK ; 1 ; 0 ; 0 ; 0 ; -; C25M ; ARCLK ; 1 ; 0 ; 0 ; 0 ; -; ARCLK ; C25M ; 1 ; 1 ; 0 ; 0 ; -; C25M ; C25M ; 1653 ; 6 ; 0 ; 0 ; -; DRCLK ; C25M ; 3 ; 0 ; 0 ; 0 ; -; C25M ; DRCLK ; 1 ; 0 ; 0 ; 0 ; -; DRCLK ; DRCLK ; 1 ; 0 ; 0 ; 0 ; +; C25M ; C25M ; 2664 ; 5 ; 0 ; 0 ; +------------+----------+----------+----------+----------+----------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. @@ -908,13 +828,7 @@ Entries labeled "false path" only account for clock-to-clock false paths and not +------------+----------+----------+----------+----------+----------+ ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; +------------+----------+----------+----------+----------+----------+ -; ARCLK ; ARCLK ; 1 ; 0 ; 0 ; 0 ; -; C25M ; ARCLK ; 1 ; 0 ; 0 ; 0 ; -; ARCLK ; C25M ; 1 ; 1 ; 0 ; 0 ; -; C25M ; C25M ; 1653 ; 6 ; 0 ; 0 ; -; DRCLK ; C25M ; 3 ; 0 ; 0 ; 0 ; -; C25M ; DRCLK ; 1 ; 0 ; 0 ; 0 ; -; DRCLK ; DRCLK ; 1 ; 0 ; 0 ; 0 ; +; C25M ; C25M ; 2664 ; 5 ; 0 ; 0 ; +------------+----------+----------+----------+----------+----------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. @@ -938,10 +852,10 @@ No dedicated SERDES Receiver circuitry present in device or used in design +---------------------------------+-------+------+ ; Illegal Clocks ; 0 ; 0 ; ; Unconstrained Clocks ; 0 ; 0 ; -; Unconstrained Input Ports ; 32 ; 32 ; -; Unconstrained Input Port Paths ; 77 ; 77 ; -; Unconstrained Output Ports ; 26 ; 26 ; -; Unconstrained Output Port Paths ; 107 ; 107 ; +; Unconstrained Input Ports ; 31 ; 31 ; +; Unconstrained Input Port Paths ; 107 ; 107 ; +; Unconstrained Output Ports ; 42 ; 42 ; +; Unconstrained Output Port Paths ; 181 ; 181 ; +---------------------------------+-------+------+ @@ -951,7 +865,7 @@ No dedicated SERDES Receiver circuitry present in device or used in design Info: ******************************************************************* Info: Running Quartus II 32-bit TimeQuest Timing Analyzer Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - Info: Processing started: Fri Mar 19 05:28:56 2021 + Info: Processing started: Fri Mar 19 07:33:17 2021 Info: Command: quartus_sta GR8RAM -c GR8RAM Info: qsta_default_script.tcl version: #1 Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected @@ -962,38 +876,30 @@ Info (306005): Delay annotation completed successfully Critical Warning (332012): Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" Info (332105): Deriving Clocks - Info (332105): create_clock -period 1.000 -name DRCLK DRCLK - Info (332105): create_clock -period 1.000 -name ARCLK ARCLK Info (332105): create_clock -period 1.000 -name C25M C25M Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON Critical Warning (332148): Timing requirements not met -Info (332146): Worst-case setup slack is -99.000 +Info (332146): Worst-case setup slack is -9.506 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== - Info (332119): -99.000 -99.000 ARCLK - Info (332119): -99.000 -99.000 DRCLK - Info (332119): -9.598 -485.527 C25M -Info (332146): Worst-case hold slack is -16.296 + Info (332119): -9.506 -540.769 C25M +Info (332146): Worst-case hold slack is 1.639 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== - Info (332119): -16.296 -16.296 ARCLK - Info (332119): -16.276 -16.276 DRCLK - Info (332119): -1.031 -1.031 C25M + Info (332119): 1.639 0.000 C25M Info (332140): No Recovery paths to report Info (332140): No Removal paths to report -Info (332146): Worst-case minimum pulse width slack is -29.500 +Info (332146): Worst-case minimum pulse width slack is -2.289 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== - Info (332119): -29.500 -59.000 ARCLK - Info (332119): -29.500 -59.000 DRCLK Info (332119): -2.289 -2.289 C25M Info (332001): The selected device family is not supported by the report_metastability command. Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings Info: Peak virtual memory: 275 megabytes - Info: Processing ended: Fri Mar 19 05:29:00 2021 - Info: Elapsed time: 00:00:04 - Info: Total CPU time (on all processors): 00:00:04 + Info: Processing ended: Fri Mar 19 07:33:22 2021 + Info: Elapsed time: 00:00:05 + Info: Total CPU time (on all processors): 00:00:05 diff --git a/cpld/output_files/GR8RAM.sta.summary b/cpld/output_files/GR8RAM.sta.summary index 1161093..1567b0c 100755 --- a/cpld/output_files/GR8RAM.sta.summary +++ b/cpld/output_files/GR8RAM.sta.summary @@ -2,37 +2,13 @@ TimeQuest Timing Analyzer Summary ------------------------------------------------------------ -Type : Setup 'ARCLK' -Slack : -99.000 -TNS : -99.000 - -Type : Setup 'DRCLK' -Slack : -99.000 -TNS : -99.000 - Type : Setup 'C25M' -Slack : -9.598 -TNS : -485.527 - -Type : Hold 'ARCLK' -Slack : -16.296 -TNS : -16.296 - -Type : Hold 'DRCLK' -Slack : -16.276 -TNS : -16.276 +Slack : -9.506 +TNS : -540.769 Type : Hold 'C25M' -Slack : -1.031 -TNS : -1.031 - -Type : Minimum Pulse Width 'ARCLK' -Slack : -29.500 -TNS : -59.000 - -Type : Minimum Pulse Width 'DRCLK' -Slack : -29.500 -TNS : -59.000 +Slack : 1.639 +TNS : 0.000 Type : Minimum Pulse Width 'C25M' Slack : -2.289