From e66f57ce88c9d967de05e3cf26a0d25c0f9423f9 Mon Sep 17 00:00:00 2001 From: Zane Kaminski Date: Tue, 28 Mar 2023 11:27:48 -0400 Subject: [PATCH] Revert "Add SPI control" This reverts commit 5de2b603177d94b5cb340a33f64a02f338c39fbd. --- cpld/GR8RAM.v | 64 +++++++++++++++++++++++++++------------------------ 1 file changed, 34 insertions(+), 30 deletions(-) diff --git a/cpld/GR8RAM.v b/cpld/GR8RAM.v index 870ace1..41dd3b5 100644 --- a/cpld/GR8RAM.v +++ b/cpld/GR8RAM.v @@ -21,9 +21,17 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, /* Firmware select */ input [1:0] SetFW; - wire [1:0] SetROM = 2'b00; - wire SetEN16MB = 0; - wire SetEN24bit = 1; + reg [1:0] SetFWr; + reg SetFWLoaded = 0; + always @(posedge C25M) begin + if (~SetFWLoaded) begin + SetFWLoaded <= 1; + SetFWr[1:0] <= SetFW[1:0]; + end + end + wire [1:0] SetROM = ~SetFWr[1:0]; + wire SetEN16MB = SetROM[1:0]==2'b11; + wire SetEN24bit = SetROM[1]; /* State counter from PHI0 rising edge */ reg [3:0] PS = 0; @@ -69,8 +77,6 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, wire ROMSpecRD = CXXXr && RAr[11:8]!=4'h0 && nWEr && ((RAr[11] && IOROMEN) || (~RAr[11])); wire REGSpecSEL = CXXXr && RAr[11:8]==4'h0 && RAr[7] && REGEN; wire BankSpecSEL = REGSpecSEL && RAr[3:0]==4'hF; - wire SPITX1SpecSEL = REGSpecSEL && RAr[3:0]==4'hD; - wire SPITX0SpecSEL = REGSpecSEL && RAr[3:0]==4'hC; wire RAMRegSpecSEL = REGSpecSEL && RAr[3:0]==4'h3; wire RAMSpecSEL = RAMRegSpecSEL && (~SetEN24bit || SetEN16MB || ~Addr[23]); wire AddrHSpecSEL = REGSpecSEL && RAr[3:0]==4'h2; @@ -147,19 +153,18 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, /* ROM bank register */ reg Bank = 0; - reg RestoreDone = 0; always @(posedge C25M, negedge nRESr) begin if (~nRESr) Bank <= 0; else if (PS==8 && BankSEL && ~nWEr) begin - if (!RestoreDone) begin - RestoreDone <= RD[1:0]==2'b11; - end else Bank <= RD[0]; + Bank <= RD[0]; end end - + /* SPI flash control signals */ - output reg nFCS = 1; - output FCK = FCKout; + output nFCS = FCKOE ? ~FCS : 1'bZ; + reg FCS = 0; + output FCK = FCKOE ? FCKout : 1'bZ; + reg FCKOE = 0; reg FCKout = 0; inout MOSI = MOSIOE ? MOSIout : 1'bZ; reg MOSIOE = 0; @@ -181,7 +186,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, end 6: begin // NOP CKE FCKout <= 1'b1; end 7: begin // NOP CKE - FCKout <= ~(IS==5 || IS==6 || (!nDEVSEL && RestoreDone && (SPITX0SpecSEL || SPITX1SpecSEL))); + FCKout <= ~(IS==5 || IS==6); end 8: begin // WR AP FCKout <= 1'b1; end 9: begin // NOP CKE @@ -200,9 +205,9 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, FCKout <= ~(IS==5); end endcase - - nFCS <= !(IS==4 || IS==5 || IS==6 || Bank); - MOSIOE <= IS==5 || IS==7; + FCS <= IS==4 || IS==5 || IS==6; + MOSIOE <= IS==5; + FCKOE <= IS==1 || IS==4 || IS==5 || IS==6 || IS==7; end /* SPI flash MOSI control */ @@ -213,7 +218,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, case (LS[2:0]) 3'h3: MOSIout <= 1'b0; // Command bit 7 3'h4: MOSIout <= 1'b0; // Address bit 23 - 3'h5: MOSIout <= 1'b1; // Address bit 15 + 3'h5: MOSIout <= 1'b0; // Address bit 15 3'h6: MOSIout <= 1'b0; // Address bit 7 default MOSIout <= 1'b0; endcase @@ -234,13 +239,13 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, default MOSIout <= 1'b0; endcase end 7: begin - if (nRES) case (LS[2:0]) - 3'h3: MOSIout <= 1'b1; // Command bit 4 - 3'h4: MOSIout <= 1'b0; // Address bit 20 - 3'h5: MOSIout <= 1'b0; // Address bit 12 - 3'h6: MOSIout <= 1'b0; // Address bit 4 - default MOSIout <= 1'b0; - endcase else MOSIout <= RAr[0]; + case (LS[2:0]) + 3'h3: MOSIout <= 1'b1; // Command bit 4 + 3'h4: MOSIout <= 1'b0; // Address bit 20 + 3'h5: MOSIout <= 1'b0; // Address bit 12 + 3'h6: MOSIout <= 1'b0; // Address bit 4 + default MOSIout <= 1'b0; + endcase end 9: begin case (LS[2:0]) 3'h3: MOSIout <= 1'b1; // Command bit 3 @@ -325,7 +330,6 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, if (AddrLSpecSEL) RDD[7:0] <= Addr[7:0]; else if (AddrMSpecSEL) RDD[7:0] <= Addr[15:8]; else if (AddrHSpecSEL) RDD[7:0] <= { SetEN24bit ? Addr[23:20] : 4'hF, Addr[19:16] }; - else if (BankSpecSEL) RDD[7:0] <= { MISO, 7'h7F }; else RDD[7:0] <= SD[7:0]; end end @@ -450,19 +454,19 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, DQML <= 1'b1; DQMH <= 1'b1; if (IS==6) begin - SBA[1:0] <= 2'b10; + SBA[1:0] <= { 2'b10 }; SA[12:0] <= { 10'b0011000100, LS[12:10] }; end else if (RAMSpecSEL) begin - SBA[1:0] <= { 1'b0, 1'b0 }; + SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 }; SA[12:10] <= SetEN24bit ? Addr[22:20] : 3'b000; SA[9:0] <= Addr[19:10]; end else begin SBA[1:0] <= 2'b10; - SA[12:0] <= { 10'b0011000100, RestoreDone ? (nIOSEL ? 1'b0 : Bank) : 1'b1, RAr[11:10] }; + SA[12:0] <= { 10'b0011000100, Bank, RAr[11:10] }; end end 2: begin // RD if (RAMSpecSEL) begin - SBA[1:0] <= 2'b00; + SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 }; SA[12:0] <= { 4'b0011, Addr[9:1] }; DQML <= Addr[0]; DQMH <= ~Addr[0]; @@ -504,7 +508,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, DQML <= LS[0]; DQMH <= ~LS[0]; end else begin - SBA[1:0] <= 2'b00; + SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 }; SA[12:0] <= { 4'b0011, Addr[9:1] }; DQML <= Addr[0]; DQMH <= ~Addr[0];