CPLD firmware compiles

Docs.sch

@@ -14,46 +14,14 @@ Comment2 ""
 Comment3 ""
 Comment4 ""
 $EndDescr
-Wire Wire Line
-	8850 2250 8850 2350
-Wire Wire Line
-	9450 1950 9450 2050
-Wire Wire Line
-	4650 1950 4650 2050
-Wire Wire Line
-	4050 2350 4050 2250
-Text Notes 800  2050 2    50   ~ 0
-Acc~CAS~
-Wire Wire Line
-	3150 1900 2550 1900
-Wire Bus Line
-	4300 950  4300 1600
-Wire Bus Line
-	4900 950  4900 1600
-Text Notes 4300 1700 0    40   ~ 0
-Allow CS, OE, WE
-Text Notes 3700 1750 0    40   ~ 0
-Latch addr. attr.\nSwitch ext. ROM
-Text Notes 800  2350 2    50   ~ 0
-~RAS~
-Text Notes 800  1900 2    50   ~ 0
-Ref~CAS~
 Text Notes 1500 1100 0    40   ~ 0
 S7
 Text Notes 6600 850  0    104  ~ 0
 Video Access
 Text Notes 8600 850  0    100  ~ 0
 6502 CPU Access
-Wire Bus Line
-	5500 950  5500 1600
 Text Notes 5700 1100 0    40   ~ 0
 S7
-Wire Wire Line
-	3450 1150 6150 1150
-Wire Wire Line
-	3450 1400 6150 1400
-Wire Wire Line
-	4650 1550 6150 1550
 Wire Wire Line
 	5800 1000 5800 1100
 Wire Wire Line
@@ -71,17 +39,13 @@ Wire Wire Line
 Wire Wire Line
 	5800 1100 6100 1100
 Wire Wire Line
-	6150 1550 6150 1450
+	6100 1550 6150 1450
 Wire Wire Line
-	6150 1400 6150 1300
+	6100 1400 6150 1300
 Wire Wire Line
-	6150 1150 6150 1250
-Wire Bus Line
-	6100 850  6100 1700
-Text Notes 6100 1700 0    40   ~ 0
-Latch WR data
+	6100 1150 6150 1250
 Text Notes 6300 1100 0    40   ~ 0
-S8
+S7
 Wire Wire Line
 	10300 1100 10300 1000
 Wire Wire Line
@@ -90,8 +54,6 @@ Wire Wire Line
 	10000 1000 10000 1100
 Wire Wire Line
 	9700 1000 10000 1000
-Wire Wire Line
-	9700 1100 9700 1000
 Wire Wire Line
 	9400 1100 9700 1100
 Wire Wire Line
@@ -133,19 +95,19 @@ Wire Wire Line
 Wire Wire Line
 	7600 1000 7600 1100
 Wire Wire Line
-	10350 1550 9450 1550
+	10300 1550 9450 1550
 Wire Wire Line
-	8250 1450 9450 1450
+	8250 1450 9400 1450
 Wire Wire Line
-	7350 1550 8250 1550
+	7350 1550 8200 1550
 Wire Wire Line
-	8250 1450 8250 1550
+	8250 1450 8200 1550
 Wire Wire Line
-	10350 1550 10350 1450
+	10300 1550 10350 1450
 Wire Wire Line
-	9450 1450 9450 1550
+	9400 1450 9450 1550
 Wire Wire Line
-	7350 1450 7350 1550
+	7300 1450 7350 1550
 Wire Wire Line
 	7300 1000 7600 1000
 Text Notes 6900 1100 0    40   ~ 0
@@ -153,71 +115,27 @@ S1
 Text Notes 7500 1100 0    40   ~ 0
 S2
 Wire Wire Line
-	10350 1400 10350 1300
+	10300 1400 10350 1300
 Wire Wire Line
-	8250 1400 10350 1400
+	8250 1400 10300 1400
 Wire Wire Line
-	8250 1300 8250 1400
+	8200 1300 8250 1400
 Wire Wire Line
-	10350 1150 10350 1250
+	10300 1150 10350 1250
 Wire Wire Line
-	8250 1150 10350 1150
+	8250 1150 10300 1150
 Wire Wire Line
-	8250 1250 8250 1150
-Wire Bus Line
-	8200 850  8200 1700
-Wire Bus Line
-	6700 950  6700 1600
-Wire Bus Line
-	7300 950  7300 1600
-Wire Bus Line
-	7900 950  7900 1600
-Wire Bus Line
-	8500 950  8500 1600
-Wire Bus Line
-	9100 950  9100 1600
-Wire Bus Line
-	9700 950  9700 1600
-Wire Bus Line
-	10300 850  10300 1700
+	8200 1250 8250 1150
 Text Notes 8100 1100 0    40   ~ 0
 S3
-Text Notes 9100 1700 0    40   ~ 0
-Allow CS, OE, WE
 Text Notes 8700 1100 0    40   ~ 0
 S4
 Text Notes 9300 1100 0    40   ~ 0
 S5
 Text Notes 9900 1100 0    40   ~ 0
 S6
-Text Notes 8500 1750 0    40   ~ 0
-Latch addr. attr.\nSwitch ext. ROM
-Text Notes 6700 1750 0    40   ~ 0
-Disallow CS, OE, WE\nIncrement addr. if attr.
 Wire Wire Line
-	6150 1250 8250 1250
-Wire Wire Line
-	6150 1300 8250 1300
-Wire Wire Line
-	6150 1450 7350 1450
-Wire Bus Line
-	1300 850  1300 1700
-Wire Wire Line
-	7350 1800 7350 1900
-Wire Wire Line
-	3150 1900 3150 1800
-Wire Wire Line
-	2550 1800 2550 1900
-Wire Wire Line
-	3450 2350 3450 2250
-Wire Wire Line
-	2850 2350 3450 2350
-Wire Wire Line
-	2850 2250 2850 2350
-Text Notes 1900 1750 0    40   ~ 0
-Disallow CS, OE, WE\nIncrement addr. if attr.
-Text Notes 1300 1650 0    40   ~ 0
-Latch WR data
+	6150 1250 8200 1250
 Text Notes 5100 1100 0    40   ~ 0
 S6
 Text Notes 4500 1100 0    40   ~ 0
@@ -228,40 +146,12 @@ Text Notes 1800 850  0    104  ~ 0
 Video Access
 Text Notes 3300 1100 0    40   ~ 0
 S3
-Wire Bus Line
-	3700 950  3700 1600
-Wire Bus Line
-	3100 950  3100 1600
-Wire Bus Line
-	2500 950  2500 1600
-Wire Bus Line
-	1900 950  1900 1600
-Wire Bus Line
-	3400 850  3400 1700
-Wire Wire Line
-	900  1550 1350 1550
-Wire Wire Line
-	1350 1400 900  1400
-Wire Wire Line
-	900  1150 1350 1150
 Text Notes 800  1250 2    50   ~ 0
 PHI0
-Wire Wire Line
-	1350 1150 1350 1250
-Wire Wire Line
-	1350 1250 3450 1250
-Wire Wire Line
-	3450 1250 3450 1150
 Text Notes 3850 850  0    100  ~ 0
 6502 CPU Access (long)
 Text Notes 800  1400 2    50   ~ 0
 PHI1
-Wire Wire Line
-	1350 1400 1350 1300
-Wire Wire Line
-	1350 1300 3450 1300
-Wire Wire Line
-	3450 1300 3450 1400
 Text Notes 900  1100 0    40   ~ 0
 S6
 Text Notes 2700 1100 0    40   ~ 0
@@ -270,22 +160,8 @@ Text Notes 2100 1100 0    40   ~ 0
 S1
 Wire Wire Line
 	2500 1000 2800 1000
-Wire Wire Line
-	1350 1450 1350 1550
-Wire Wire Line
-	2550 1450 1350 1450
-Wire Wire Line
-	2550 1450 2550 1550
 Text Notes 800  1550 2    50   ~ 0
-Q3
-Wire Wire Line
-	4650 1450 4650 1550
-Wire Wire Line
-	3450 1450 3450 1550
-Wire Wire Line
-	2550 1550 3450 1550
-Wire Wire Line
-	3450 1450 4650 1450
+~DEVSEL~
 Wire Wire Line
 	1000 1100 1300 1100
 Wire Wire Line
@@ -346,138 +222,6 @@ Wire Wire Line
 	4900 1000 5200 1000
 Wire Wire Line
 	5200 1000 5200 1100
-Wire Wire Line
-	9700 2400 9750 2500
-Wire Wire Line
-	9700 2500 9750 2400
-Wire Wire Line
-	9150 2500 9700 2500
-Wire Wire Line
-	9150 2400 9700 2400
-Wire Wire Line
-	9100 2500 9150 2400
-Wire Wire Line
-	9100 2400 9150 2500
-Wire Wire Line
-	9100 2500 4950 2500
-Wire Wire Line
-	4950 2400 9100 2400
-Wire Wire Line
-	4900 2400 4950 2500
-Wire Wire Line
-	4900 2500 4950 2400
-Wire Wire Line
-	4350 2500 4900 2500
-Wire Wire Line
-	4350 2400 4900 2400
-Wire Wire Line
-	4300 2500 4350 2400
-Wire Wire Line
-	4300 2400 4350 2500
-Wire Wire Line
-	900  2400 4300 2400
-Wire Wire Line
-	4300 2500 900  2500
-Text Notes 800  2500 2    50   ~ 0
-RA
-Wire Wire Line
-	2250 2050 2250 1950
-Wire Wire Line
-	2250 1950 4650 1950
-Wire Wire Line
-	5250 2350 5250 2250
-Wire Wire Line
-	5250 2250 8850 2250
-Wire Wire Line
-	1050 2350 1050 2250
-Wire Wire Line
-	1050 2250 2850 2250
-Wire Wire Line
-	900  2350 1050 2350
-Wire Wire Line
-	8850 2350 10050 2350
-Wire Wire Line
-	10050 2350 10050 2250
-Wire Wire Line
-	3450 2250 4050 2250
-Wire Wire Line
-	7950 1900 7950 1800
-Wire Wire Line
-	7950 1900 7350 1900
-Wire Wire Line
-	9450 2100 9450 2200
-Wire Wire Line
-	4650 2100 4650 2200
-Text Notes 800  2200 2    50   ~ 0
-~CAS~
-Wire Wire Line
-	2250 2200 2250 2100
-Wire Wire Line
-	3150 2200 3150 2100
-Wire Wire Line
-	2550 2100 2550 2200
-Wire Wire Line
-	2250 2100 2550 2100
-Wire Wire Line
-	7350 2100 7350 2200
-Wire Wire Line
-	7950 2200 7950 2100
-Wire Wire Line
-	7950 2200 7350 2200
-Wire Wire Line
-	7950 2100 9450 2100
-Wire Wire Line
-	4650 2200 6150 2200
-Wire Wire Line
-	6150 2200 6150 2100
-Wire Wire Line
-	6150 2100 7350 2100
-Wire Wire Line
-	9450 2200 10350 2200
-Wire Wire Line
-	10350 2200 10350 2100
-Wire Wire Line
-	4650 2050 6450 2050
-Wire Wire Line
-	6450 2050 6450 1950
-Wire Wire Line
-	6450 1950 9450 1950
-Wire Wire Line
-	900  2200 2250 2200
-Wire Wire Line
-	900  2050 2250 2050
-Wire Wire Line
-	3150 1800 7350 1800
-Wire Wire Line
-	900  1800 2550 1800
-Wire Wire Line
-	3150 2100 4650 2100
-Wire Wire Line
-	2550 2200 3150 2200
-Wire Wire Line
-	4050 2350 5250 2350
-Text Notes 4550 3800 0    50   ~ 0
-CSEN = S4 | S5 | S6 | S7 @ C7M\nRCS =  (IOSEL  | (IOSTRB & IOROMEN)) & CSEN\nR~OE~ = ~R~W\n\nRWE = ~R~W & (DEVSEL | IOSEL | IOSTRB)\n\nRAS = (RAMSEL & (S4 | S5)) | S2 @ ~C7M~\nRefCAS = S1 @ C7M\nAccCAS = RAMSEL & (S5 | S6 | S7) @ ~C7M~\nCAS0 = (RefCAS) | (AccCAS & ~Addr[22]~ & DEVSEL)\nCAS1 = (RefCAS) | (AccCAS & Addr[22] & DEVSEL)
-Text Notes 1300 2850 0    100  ~ 0
-State Synchronization
-Text Notes 4500 2850 0    100  ~ 0
-ROM / DRAM Control
-Text Notes 7150 2850 0    100  ~ 0
-Address Bus Routing
-Wire Wire Line
-	10350 2100 10400 2100
-Wire Wire Line
-	7950 1800 10400 1800
-Wire Wire Line
-	10050 2250 10400 2250
-Wire Wire Line
-	9450 2050 10400 2050
-Wire Wire Line
-	10400 2400 9750 2400
-Wire Wire Line
-	9750 2500 10400 2500
-Text Notes 10000 1750 0    40   ~ 0
-Latch WR data
 Wire Wire Line
 	10300 1000 10400 1000
 Wire Wire Line
@@ -486,20 +230,577 @@ Wire Wire Line
 	10350 1300 10400 1300
 Wire Wire Line
 	10350 1450 10400 1450
-Text Notes 7200 4650 0    50   ~ 0
-RD[7:0] = (~DEVSEL~ | R~W~) ? 8’bZ : D[7:0]\nD[7:0] = (~CSEN~ | ~DEVSEL~ | ~R~W) ? 8’bZ :\n          AddrHSEL ? {1’b1, Addr[22:16]} : \n          AddrMSEL ? Addr[15:8] : \n          AddrLSEL ? Addr[7:0] : \n          RD[7:0]
-Text Notes 7150 4100 0    100  ~ 0
+Wire Wire Line
+	1350 1300 3400 1300
+Wire Wire Line
+	1300 1400 1350 1300
+Wire Wire Line
+	1350 1250 3400 1250
+Wire Wire Line
+	1300 1150 1350 1250
+Wire Wire Line
+	900  1150 1300 1150
+Wire Wire Line
+	1300 1400 900  1400
+Wire Wire Line
+	3400 1300 3450 1400
+Wire Wire Line
+	3400 1250 3450 1150
+Wire Wire Line
+	3450 1400 6100 1400
+Wire Wire Line
+	3450 1150 6100 1150
+Wire Wire Line
+	9700 1100 9700 1000
+Text Notes 900  3500 0    100  ~ 0
+State Synchronization
+Text Notes 7050 3500 0    100  ~ 0
+Address Bus Routing
+Wire Wire Line
+	1600 1850 1650 1750
+Wire Wire Line
+	1600 1750 1650 1850
+Text Notes 800  1850 2    50   ~ 0
+A
+Wire Wire Line
+	6400 1750 6450 1850
+Wire Wire Line
+	6400 1850 6450 1750
+Wire Wire Line
+	1600 1750 900  1750
+Wire Wire Line
+	900  1850 1600 1850
+Wire Wire Line
+	1650 1750 6400 1750
+Wire Wire Line
+	6450 1750 10400 1750
+Wire Wire Line
+	6450 1850 10400 1850
+Text Notes 800  2000 2    50   ~ 0
+D (wr)
+Wire Wire Line
+	4800 1900 4750 1950
+Wire Wire Line
+	4800 2000 4750 1950
+Wire Wire Line
+	4750 1950 1650 1950
+Wire Wire Line
+	4800 1900 6400 1900
+Wire Wire Line
+	4800 2000 6400 2000
+Wire Wire Line
+	9600 1900 9550 1950
+Wire Wire Line
+	9600 2000 9550 1950
+Wire Wire Line
+	1600 1900 1650 1950
+Wire Wire Line
+	1600 2000 1650 1950
+Wire Wire Line
+	9600 1900 10400 1900
+Wire Wire Line
+	9600 2000 10400 2000
+Text Notes 800  2150 2    50   ~ 0
+D (rd)
+Wire Wire Line
+	5050 2050 5000 2100
+Wire Wire Line
+	5050 2150 5000 2100
+Wire Wire Line
+	6400 2050 6450 2100
+Wire Wire Line
+	6400 2150 6450 2100
+Wire Wire Line
+	5000 2100 1650 2100
+Wire Wire Line
+	5050 2050 6400 2050
+Wire Wire Line
+	5050 2150 6400 2150
+Wire Wire Line
+	1600 2050 1650 2100
+Wire Wire Line
+	1600 2150 1650 2100
+Wire Wire Line
+	1600 2050 900  2050
+Wire Wire Line
+	1600 2150 900  2150
+Wire Wire Line
+	9850 2050 10400 2050
+Wire Wire Line
+	9850 2150 10400 2150
+Wire Wire Line
+	6450 2100 9800 2100
+Wire Wire Line
+	9850 2150 9800 2100
+Wire Wire Line
+	9850 2050 9800 2100
+Wire Wire Line
+	6450 1950 9550 1950
+Wire Wire Line
+	6400 2000 6450 1950
+Wire Wire Line
+	6400 1900 6450 1950
+Wire Wire Line
+	6150 1300 8200 1300
+Text Notes 3650 3900 0    100  ~ 0
+ROM / DRAM Control
+Text Notes 3650 3550 0    100  ~ 0
+Refresh Skip Counter
+Text Notes 3700 3650 0    50   ~ 0
+Ref[3:0] = ~S1~ ? Ref[3:0] : Ref[3:2]==3 ? 0 : Ref[3:0]+1 @ ~C7M~
+Text Notes 950  4850 0    50   ~ 0
+BankSEL = A==XXXF & DEVSEL & REGEN\nRAMSEL = A==XXX3 & DEVSEL & REGEN\nRAMSELreg = S3 ? RAMSEL : RAMSELreg;\nAddrHSEL = A==XXX2 & DEVSEL & REGEN\nAddrMSEL = A==XXX1 & DEVSEL & REGEN\nAddrLSEL = A==XXX0 & DEVSEL & REGEN\n\nREGEN = (IOSEL & S3) ? 1 : REGEN @ C7M\nIOROMEN = (A==XXFF & IOSTRB & S3) ? 0 :\n            (A==XX00 & IOSEL & S3) ? 1 :\n            IOROMEN @ C7M
+Text Notes 900  3900 0    100  ~ 0
+Select Signals
+Text Notes 950  3700 0    50   ~ 0
+PHI0reg = PHI0 @ C7M\nS[3:0] = (~PHI0~ & PHI0reg) ? 1 : S0 ? 0 : S+1 @ C7M
+Wire Wire Line
+	1650 1850 6400 1850
+Text Notes 800  3050 2    50   ~ 0
+RA
+Text Notes 800  2750 2    50   ~ 0
+~CAS~
+Wire Wire Line
+	2550 2750 3100 2750
+Wire Wire Line
+	2500 2650 2550 2750
+Wire Wire Line
+	3100 2750 3150 2650
+Wire Wire Line
+	1300 2750 1350 2650
+Wire Wire Line
+	7900 2750 7350 2750
+Wire Wire Line
+	7900 2750 7950 2650
+Wire Wire Line
+	7300 2650 7350 2750
+Wire Wire Line
+	5500 2950 5550 3050
+Wire Wire Line
+	5500 3050 5550 2950
+Wire Wire Line
+	9100 3050 9150 2950
+Wire Wire Line
+	9100 2950 9150 3050
+Wire Wire Line
+	9400 2650 9450 2750
+Wire Wire Line
+	4300 2950 4350 3050
+Wire Wire Line
+	4300 3050 4350 2950
+Wire Wire Line
+	10300 3050 10350 2950
+Wire Wire Line
+	10300 2950 10350 3050
+Wire Wire Line
+	9150 2950 10300 2950
+Wire Wire Line
+	9150 3050 10300 3050
+Wire Wire Line
+	1300 3050 1350 2950
+Wire Wire Line
+	1300 2950 1350 3050
+Wire Wire Line
+	1300 2950 900  2950
+Wire Wire Line
+	1300 3050 900  3050
+Wire Wire Line
+	4600 2650 4650 2750
+Wire Wire Line
+	4900 2650 4950 2750
+Wire Wire Line
+	10300 2750 10350 2650
+Wire Wire Line
+	900  2750 1300 2750
+Wire Wire Line
+	9700 2650 9750 2750
+Wire Wire Line
+	10350 2950 10400 2950
+Wire Wire Line
+	10350 3050 10400 3050
+Wire Wire Line
+	5550 2950 9100 2950
+Wire Wire Line
+	5550 3050 9100 3050
+Wire Wire Line
+	4350 2950 5500 2950
+Wire Wire Line
+	4350 3050 5500 3050
+Wire Wire Line
+	4300 3050 1350 3050
+Wire Wire Line
+	1350 2950 4300 2950
+Text Notes 800  2600 2    50   ~ 0
+~CAS~f
+Wire Wire Line
+	9400 2500 9450 2600
+Wire Wire Line
+	4600 2500 4650 2600
+Wire Wire Line
+	5200 2500 5250 2600
+Wire Wire Line
+	6400 2600 6450 2500
+Wire Wire Line
+	10000 2500 10050 2600
+Text Notes 800  2450 2    50   ~ 0
+~CAS~r
+Wire Wire Line
+	3100 2450 3150 2350
+Wire Wire Line
+	7900 2450 7350 2450
+Wire Wire Line
+	7900 2450 7950 2350
+Wire Wire Line
+	7300 2350 7350 2450
+Wire Wire Line
+	9700 2350 9750 2450
+Wire Wire Line
+	4900 2350 4950 2450
+Wire Wire Line
+	5500 2450 5550 2350
+Wire Wire Line
+	10300 2450 10350 2350
+Wire Wire Line
+	4950 2450 5500 2450
+Wire Wire Line
+	2200 2600 2250 2500
+Wire Wire Line
+	900  2600 2200 2600
+Wire Wire Line
+	9750 2450 10300 2450
+Wire Wire Line
+	6100 2750 6150 2650
+Wire Wire Line
+	1600 1900 900  1900
+Wire Wire Line
+	1600 2000 900  2000
+Wire Wire Line
+	1350 1450 1300 1550
+Wire Wire Line
+	4650 2600 5250 2600
+Wire Wire Line
+	9450 2600 10050 2600
+Wire Wire Line
+	4650 2750 4950 2750
+Wire Wire Line
+	9450 2750 9750 2750
+Wire Wire Line
+	2500 2350 2550 2450
+Wire Wire Line
+	2550 2450 3100 2450
+Wire Wire Line
+	4050 2900 4900 2900
+Wire Wire Line
+	10000 2900 10050 2800
+Wire Wire Line
+	8850 2900 8800 2800
+Wire Wire Line
+	5200 2900 5250 2800
+Wire Wire Line
+	4050 2900 4000 2800
+Wire Wire Line
+	3400 2900 3450 2800
+Wire Wire Line
+	2850 2900 3400 2900
+Wire Wire Line
+	2800 2800 2850 2900
+Wire Wire Line
+	8200 2900 8250 2800
+Wire Wire Line
+	7650 2900 8200 2900
+Wire Wire Line
+	7600 2800 7650 2900
+Wire Wire Line
+	900  2900 1000 2900
+Wire Wire Line
+	1000 2900 1050 2800
+Text Notes 800  2900 2    50   ~ 0
+~RAS~
+Wire Wire Line
+	900  2500 2250 2500
+Text Notes 7100 3800 0    50   ~ 0
+RA[10:8] = (RAMSEL & (S4 | S5)) ? Addr[10:8] : Addr[21:19] @ C7M\nRA[7:1] = RAMSEL ? (S4 ? Addr[7:1] : Addr[18:12]) : Bank[6:0] @ C7M\nRA[0] = RAMSEL ? (S4 ? Addr[0] : Addr[11]) : A[11] @ C7M
+Wire Wire Line
+	8850 2900 9700 2900
+Text Notes 3700 4850 0    50   ~ 0
+DBEN = ~S2~ & ~S3~ @ C7M\nRCS = IOSEL  | (IOSTRB & IOROMEN)\nROE = R~W~\nRWE = ~R~W & (DEVSEL | IOSEL | IOSTRB)\n\nCASr = (S1 & Ref[3:0]==0) | (S5 & RAMSEL) @ C7M\nCASf = ((S5 & R~W~) | S6 | S7) & RAMSEL @ ~C7M~\n\nRASf = (S4 & RAMSEL) | (S5 & RAMSEL & ~R~W) | (S2 & Ref[3:0]==0) @ ~C7M~\nCAS0 = CASr | (CASf & DEVSEL & ~Addr[22]~)\nCAS1 = CASr | (CASf & DEVSEL & Addr[22])
+Text Notes 7100 5200 0    50   ~ 0
+RD[7:0] = (~R~W & ~RES~) ? D[7:0]: 8’bZ\nD[7:0] = (DBEN & R~W~ & ~RES~ & (DEVSEL | IOSEL | (IOSTRB & ROMEN))) ?\n           AddrHSEL ? {1’b1, Addr[22:16]} : \n           AddrMSEL ? Addr[15:8] : \n           AddrLSEL ? Addr[7:0] : \n           RD[7:0] : 8’bZ
+Text Notes 7100 4500 0    50   ~ 0
+Bank[6:0] = (S6 & BankSEL & ~R~W) ? D[6:0] : Bank[6:0] @ C7M\nAddr[22:16] = (S6 & AddrHSEL & ~R~W) ? D[6:0] : Addr[22:16] @ C7M\nAddr[15:8] = (S6 & AddrMSEL & ~R~W) ? D[7:0] : Addr[15:8] @ C7M\nAddr[7:0] = (S6 & AddrLSEL & ~R~W) ? D[7:0] : Addr[7:0] @ C7M\nif (S1 & RAMSELreg) Addr[22:0]++ @ C7M
+Text Notes 7050 4700 0    100  ~ 0
 Data Bus Routing
-Text Notes 7200 3850 0    50   ~ 0
-Addr[22:16] = (S6 & AddrHSEL & ~R~W) ? D[6:0] : Addr[22:16] @ C7M\nAddr[15:8] = (S6 if AddrMSEL & ~R~W) ? D[7:0] : Addr[15:8] @ C7M\nAddr[7:0] = (S6 if AddrLSEL & ~R~W) ? D[7:0] : Addr[7:0] @ C7M\nif (RAMSEL & S1) Addr[22:0]++ @ C7M\nBank[6:0] = (S6 & BANKREG & ~R~W) ? D[7:0] : Bank[7:0] @ C7M
-Text Notes 7150 3400 0    100  ~ 0
+Text Notes 7050 4050 0    100  ~ 0
 6502-Accessible Registers
-Text Notes 7200 3150 0    50   ~ 0
-RA[10:8] = S4 ? Addr[10:8] : Addr[21:19] @ C7M\nRA[7:1] = RAMSEL ? (S4 ? Addr[7:1] : Addr[18:12]) : Bank[6:0] @ C7M\nRA[0] =  RAMSEL ? (S4 ? Addr[0] : Addr[11]) : A[11] @ C7M
-Text Notes 1350 4250 0    50   ~ 0
-BankSEL = S3 ? (A==XXXF & DEVSEL & REGEN) : BankSEL @ C7M\nRAMSEL = S3 ? (A==XXX3 & DEVSEL & REGEN) : RAMSEL @ C7M\nAddrHSEL = S3 ? (A==XXX2 & DEVSEL & REGEN) : AddrHSEL @ C7M\nAddrMSEL = S3 ? (A==XXX1 & DEVSEL & REGEN) : AddrMSEL @ C7M\nAddrLSEL = S3 ? (A==XXX0 & DEVSEL & REGEN) : AddrLSEL @ C7M\n\nREGEN = (IOSEL & S3) ? 1 : REGEN @ C7M\nIOROMEN = (A==XXFF & IOSTRB & S3) ? 0 :\n            (A==XX00 & IOSEL & S3) ? 1 :\n            IOROMEN @ C7M
-Text Notes 1300 3400 0    100  ~ 0
-Select signals (registered)
-Text Notes 1350 3150 0    50   ~ 0
-PHI0reg = PHI0 @ C7M\nS[3:0] = (~PHI0~ & PHI0reg) ? 1 : \n          (S==0) ? 0 : S+1 @ C7M
+Wire Wire Line
+	4900 2900 4950 2800
+Wire Wire Line
+	9700 2900 9750 2800
+Wire Wire Line
+	900  2350 2500 2350
+Wire Wire Line
+	900  2650 1350 2650
+Wire Wire Line
+	900  2800 1050 2800
+Wire Wire Line
+	900  1550 1300 1550
+Wire Wire Line
+	3400 1450 3450 1550
+Wire Wire Line
+	3900 1450 3950 1550
+Wire Wire Line
+	6350 1550 6400 1450
+Wire Wire Line
+	3450 1550 6100 1550
+Wire Wire Line
+	6100 1550 6350 1550
+Wire Wire Line
+	6150 1450 7300 1450
+Wire Wire Line
+	3550 6050 3450 6150
+Wire Wire Line
+	3300 6450 3400 6350
+Wire Wire Line
+	3600 6600 3700 6500
+Wire Notes Line
+	3500 5950 3500 6750
+Text Notes 2750 6100 0    40   ~ 0
+7 MHz
+Text Notes 2750 6400 0    40   ~ 0
+1 MHz (IIgs)
+Text Notes 2750 6550 0    40   ~ 0
+1 MHz (IIe)
+Wire Wire Line
+	3450 6300 3550 6200
+Text Notes 2750 6250 0    40   ~ 0
+1 MHz (//, //+)
+Wire Wire Line
+	2700 6450 3300 6450
+Wire Wire Line
+	2700 6600 3600 6600
+Wire Wire Line
+	4250 6150 4150 6050
+Wire Wire Line
+	3550 6050 4150 6050
+Wire Wire Line
+	3550 6200 4350 6200
+Wire Wire Line
+	4250 6150 4350 6150
+Wire Wire Line
+	3400 6350 4350 6350
+Wire Wire Line
+	3700 6500 4350 6500
+Wire Wire Line
+	2700 6300 3450 6300
+Wire Wire Line
+	2700 6150 3450 6150
+Connection ~ 1050 2800
+Wire Wire Line
+	1050 2800 2800 2800
+Connection ~ 1350 2650
+Wire Wire Line
+	1350 2650 2500 2650
+Connection ~ 1650 1950
+Connection ~ 1650 2100
+Connection ~ 2250 2500
+Wire Wire Line
+	2250 2500 4600 2500
+Connection ~ 2500 2350
+Wire Wire Line
+	2500 2350 3150 2350
+Connection ~ 2500 2650
+Wire Wire Line
+	2500 2650 3150 2650
+Connection ~ 2800 2800
+Wire Wire Line
+	2800 2800 3450 2800
+Connection ~ 3150 2350
+Wire Wire Line
+	3150 2350 4900 2350
+Connection ~ 3150 2650
+Wire Wire Line
+	3150 2650 4600 2650
+Connection ~ 3450 2800
+Wire Wire Line
+	3450 2800 4000 2800
+Connection ~ 4000 2800
+Wire Wire Line
+	4000 2800 4950 2800
+Connection ~ 4600 2500
+Wire Wire Line
+	4600 2500 5200 2500
+Connection ~ 4600 2650
+Wire Wire Line
+	4600 2650 4900 2650
+Connection ~ 4750 1950
+Connection ~ 4900 2350
+Wire Wire Line
+	4900 2350 5550 2350
+Connection ~ 4900 2650
+Wire Wire Line
+	4900 2650 6150 2650
+Connection ~ 4900 2900
+Wire Wire Line
+	4900 2900 5200 2900
+Connection ~ 4950 2750
+Wire Wire Line
+	4950 2750 6100 2750
+Connection ~ 4950 2800
+Wire Wire Line
+	4950 2800 5250 2800
+Connection ~ 5000 2100
+Connection ~ 5200 2500
+Wire Wire Line
+	5200 2500 6450 2500
+Connection ~ 5250 2600
+Wire Wire Line
+	5250 2600 6400 2600
+Connection ~ 5250 2800
+Wire Wire Line
+	5250 2800 7600 2800
+Connection ~ 5550 2350
+Wire Wire Line
+	5550 2350 7300 2350
+Connection ~ 6100 1550
+Wire Bus Line
+	6100 1550 6100 2250
+Connection ~ 6150 2650
+Wire Wire Line
+	6150 2650 7300 2650
+Connection ~ 6450 1950
+Connection ~ 6450 2100
+Connection ~ 6450 2500
+Wire Wire Line
+	6450 2500 9400 2500
+Connection ~ 7300 2350
+Wire Wire Line
+	7300 2350 7950 2350
+Connection ~ 7300 2650
+Wire Wire Line
+	7300 2650 7950 2650
+Connection ~ 7600 2800
+Wire Wire Line
+	7600 2800 8250 2800
+Connection ~ 7950 2350
+Wire Wire Line
+	7950 2350 9700 2350
+Connection ~ 7950 2650
+Wire Wire Line
+	7950 2650 9400 2650
+Connection ~ 8250 2800
+Wire Wire Line
+	8250 2800 8800 2800
+Connection ~ 8800 2800
+Wire Wire Line
+	8800 2800 9750 2800
+Connection ~ 9400 2500
+Wire Wire Line
+	9400 2500 10000 2500
+Connection ~ 9400 2650
+Wire Wire Line
+	9400 2650 9700 2650
+Connection ~ 9550 1950
+Connection ~ 9700 2350
+Wire Wire Line
+	9700 2350 10350 2350
+Connection ~ 9700 2650
+Wire Wire Line
+	9700 2650 10350 2650
+Connection ~ 9700 2900
+Wire Wire Line
+	9700 2900 10000 2900
+Connection ~ 9750 2750
+Wire Wire Line
+	9750 2750 10300 2750
+Connection ~ 9750 2800
+Wire Wire Line
+	9750 2800 10050 2800
+Connection ~ 9800 2100
+Connection ~ 10000 2500
+Wire Wire Line
+	10000 2500 10400 2500
+Connection ~ 10050 2600
+Wire Wire Line
+	10050 2600 10400 2600
+Connection ~ 10050 2800
+Wire Wire Line
+	10050 2800 10400 2800
+Connection ~ 10350 2350
+Wire Wire Line
+	10350 2350 10400 2350
+Connection ~ 10350 2650
+Wire Wire Line
+	10350 2650 10400 2650
+Wire Wire Line
+	1350 1450 3400 1450
+Wire Bus Line
+	7900 950  7900 2200
+Wire Bus Line
+	8500 950  8500 2200
+Wire Bus Line
+	9100 950  9100 2200
+Wire Bus Line
+	9700 950  9700 2200
+Wire Bus Line
+	10300 850  10300 2250
+Wire Bus Line
+	8200 850  8200 2250
+Wire Bus Line
+	7300 950  7300 2200
+Wire Bus Line
+	6700 950  6700 2200
+Wire Bus Line
+	6100 850  6100 1550
+Wire Bus Line
+	5500 950  5500 2200
+Wire Bus Line
+	3700 950  3700 2200
+Wire Bus Line
+	4300 950  4300 2200
+Wire Bus Line
+	4900 950  4900 2200
+Wire Bus Line
+	3100 950  3100 2200
+Wire Bus Line
+	1300 850  1300 2250
+Wire Bus Line
+	1900 950  1900 2200
+Wire Bus Line
+	2500 950  2500 2200
+Wire Wire Line
+	3400 1450 3900 1450
+Wire Bus Line
+	3400 850  3400 2250
+Text Notes 800  1700 2    50   ~ 0
+PHI0
+Wire Wire Line
+	3400 1700 3450 1600
+Wire Wire Line
+	6600 1600 6650 1700
+Wire Wire Line
+	3450 1600 6150 1600
+Wire Wire Line
+	6150 1600 6200 1700
+Wire Wire Line
+	6200 1700 6650 1700
+Wire Wire Line
+	3400 1700 1350 1700
+Wire Wire Line
+	1350 1700 1300 1600
+Wire Wire Line
+	900  1600 1300 1600
+Wire Wire Line
+	6650 1700 8200 1700
+Connection ~ 6650 1700
+Wire Wire Line
+	8200 1700 8250 1600
+Wire Wire Line
+	8250 1600 10300 1600
+Connection ~ 6150 1600
+Wire Wire Line
+	6150 1600 6600 1600
+Wire Wire Line
+	10400 1650 10450 1650
+Wire Wire Line
+	10350 1550 10400 1650
 $EndSCHEMATC

GR8RAM.sch

@@ -1211,7 +1211,7 @@ L Device:R_Small R4
 U 1 1 5DA6CBE2
 P 1300 6450
 F 0 "R4" V 1150 6450 50  0000 C CNN
-F 1 "100" V 1250 6450 50  0000 C BNN
+F 1 "1" V 1250 6450 50  0000 C BNN
 F 2 "stdpads:R_0805" H 1300 6450 50  0001 C CNN
 F 3 "~" H 1300 6450 50  0001 C CNN
 	1    1300 6450
@@ -1395,8 +1395,6 @@ F 3 "" H 3300 3650 50  0001 C CNN
 	1    3450 3450
 	1    0    0    -1  
 $EndComp
-NoConn ~ 2700 3250
-NoConn ~ 2700 3350
 NoConn ~ 2700 3950
 $Comp
 L Mechanical:Fiducial FID1
@@ -2218,4 +2216,8 @@ Wire Bus Line
 	8900 1900 8900 5850
 Wire Bus Line
 	7300 1900 7300 5850
+Text Label 2700 3350 2    50   ~ 0
+C7Mout
+Text Label 2700 3250 2    50   ~ 0
+PHI1out
 $EndSCHEMATC

cpld/GR8RAM.qpf

@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 32-bit
+# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+# Date created = 02:27:57  August 06, 2019
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.0"
+DATE = "02:27:57  August 06, 2019"
+
+# Revisions
+
+PROJECT_REVISION = "GR8RAM"

cpld/GR8RAM.qsf

@@ -0,0 +1,158 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 32-bit
+# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+# Date created = 02:27:57  August 06, 2019
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		GR8RAM_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY MAX7000S
+set_global_assignment -name DEVICE "EPM7128SLC84-15"
+set_global_assignment -name TOP_LEVEL_ENTITY GR8RAM
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "02:27:57  AUGUST 06, 2019"
+set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name DEVICE_FILTER_PACKAGE PLCC
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 84
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 15
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name VERILOG_FILE GR8RAM.v
+set_global_assignment -name MAX7000_DEVICE_IO_STANDARD TTL
+set_location_assignment PIN_1 -to nRES
+set_location_assignment PIN_75 -to A[0]
+set_location_assignment PIN_77 -to A[2]
+set_location_assignment PIN_79 -to A[3]
+set_location_assignment PIN_80 -to A[4]
+set_location_assignment PIN_81 -to A[5]
+set_location_assignment PIN_83 -to C7M
+set_location_assignment PIN_84 -to C7M_2
+set_location_assignment PIN_4 -to A[6]
+set_location_assignment PIN_5 -to A[7]
+set_location_assignment PIN_9 -to A[8]
+set_location_assignment PIN_10 -to A[9]
+set_location_assignment PIN_11 -to A[10]
+set_location_assignment PIN_12 -to A[11]
+set_location_assignment PIN_15 -to A[12]
+set_location_assignment PIN_6 -to Q3
+set_location_assignment PIN_16 -to A[13]
+set_location_assignment PIN_17 -to A[14]
+set_location_assignment PIN_18 -to A[15]
+set_location_assignment PIN_20 -to nWE
+set_location_assignment PIN_21 -to nDEVSEL
+set_location_assignment PIN_22 -to nINH
+set_location_assignment PIN_24 -to nIOSTRB
+set_location_assignment PIN_25 -to D[7]
+set_location_assignment PIN_27 -to D[6]
+set_location_assignment PIN_28 -to D[5]
+set_location_assignment PIN_29 -to D[4]
+set_location_assignment PIN_33 -to D[3]
+set_location_assignment PIN_34 -to D[2]
+set_location_assignment PIN_35 -to D[1]
+set_location_assignment PIN_36 -to D[0]
+set_location_assignment PIN_39 -to nCAS0
+set_location_assignment PIN_40 -to nCAS1
+set_location_assignment PIN_41 -to nRCS
+set_location_assignment PIN_44 -to MODE
+set_location_assignment PIN_45 -to nROE
+set_location_assignment PIN_46 -to RA[9]
+set_location_assignment PIN_48 -to RA[10]
+set_location_assignment PIN_49 -to RA[3]
+set_location_assignment PIN_50 -to RA[2]
+set_location_assignment PIN_51 -to RA[5]
+set_location_assignment PIN_52 -to RA[0]
+set_location_assignment PIN_54 -to RA[1]
+set_location_assignment PIN_55 -to RA[4]
+set_location_assignment PIN_56 -to RA[7]
+set_location_assignment PIN_57 -to RA[6]
+set_location_assignment PIN_58 -to RA[8]
+set_location_assignment PIN_60 -to nRAS
+set_location_assignment PIN_61 -to RD[7]
+set_location_assignment PIN_63 -to RD[5]
+set_location_assignment PIN_64 -to RD[6]
+set_location_assignment PIN_65 -to RD[4]
+set_location_assignment PIN_67 -to nRWE
+set_location_assignment PIN_68 -to RD[3]
+set_location_assignment PIN_69 -to RD[2]
+set_location_assignment PIN_70 -to RD[1]
+set_location_assignment PIN_73 -to RD[0]
+set_location_assignment PIN_74 -to nIOSEL
+set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
+set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
+set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING "PACK ALL IO REGISTERS"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
+set_global_assignment -name AUTO_LCELL_INSERTION ON
+set_global_assignment -name AUTO_PARALLEL_EXPANDERS ON
+set_global_assignment -name AUTO_RESOURCE_SHARING ON
+set_global_assignment -name SYNTH_MESSAGE_LEVEL HIGH
+set_global_assignment -name SLOW_SLEW_RATE ON
+set_global_assignment -name ALM_REGISTER_PACKING_EFFORT HIGH
+set_global_assignment -name ECO_OPTIMIZE_TIMING ON
+set_global_assignment -name ECO_REGENERATE_REPORT ON
+set_location_assignment LC1 -to Addr[0]
+set_location_assignment LC2 -to Addr[1]
+set_location_assignment LC3 -to Addr[2]
+set_location_assignment LC4 -to Addr[3]
+set_location_assignment LC5 -to Addr[4]
+set_location_assignment LC6 -to Addr[5]
+set_location_assignment LC7 -to Addr[6]
+set_location_assignment LC8 -to Addr[7]
+set_location_assignment LC9 -to Addr[8]
+set_location_assignment LC10 -to Addr[9]
+set_location_assignment LC11 -to Addr[10]
+set_location_assignment LC12 -to Addr[11]
+set_location_assignment LC13 -to Addr[12]
+set_location_assignment LC14 -to Addr[13]
+set_location_assignment LC15 -to Addr[14]
+set_location_assignment LC16 -to Addr[15]
+set_global_assignment -name PARALLEL_SYNTHESIS OFF
+set_global_assignment -name STATE_MACHINE_PROCESSING "USER-ENCODED"
+set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS OFF
+set_location_assignment LC128 -to Addr[22]
+set_location_assignment LC122 -to Addr[19]
+set_location_assignment LC124 -to Addr[20]
+set_location_assignment LC120 -to Addr[17]
+set_location_assignment LC118 -to Addr[16]
+set_location_assignment LC126 -to Addr[21]
+set_location_assignment PIN_76 -to A[1]
+set_location_assignment PIN_8 -to PHI0in
+set_location_assignment PIN_2 -to PHI1in
+set_location_assignment LC127 -to PHI1b7_MC
+set_location_assignment LC125 -to PHI1b6_MC
+set_location_assignment LC123 -to PHI1b5_MC
+set_location_assignment LC121 -to PHI1b4_MC
+set_location_assignment PIN_31 -to C7Mout
+set_location_assignment PIN_30 -to PHI1out

cpld/GR8RAM.v

@@ -0,0 +1,192 @@
+module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, MODE,
+			  A, RA, nWE, D, RD, nINH,
+			  nDEVSEL, nIOSEL, nIOSTRB,
+			  nRAS, nCAS0, nCAS1, nRCS, nROE, nRWE,
+			  C7Mout, PHI1out);
+
+	/* Clock, Reset, Mode */
+	input C7M, C7M_2, Q3, PHI0in, PHI1in; // Clock inputs
+	input nRES, MODE; // Reset, mode
+
+	/* PHI1 Delay */
+	wire [6:0] PHI1b;
+	wire PHI1;
+	LCELL PHI1b0_MC (.in(PHI1in), .out(PHI1b[0]));
+	LCELL PHI1b1_MC (.in(PHI1b[0]), .out(PHI1b[1]));
+	LCELL PHI1b2_MC (.in(PHI1b[1]), .out(PHI1b[2]));
+	LCELL PHI1b3_MC (.in(PHI1b[2]), .out(PHI1b[3]));
+	LCELL PHI1b4_MC (.in(PHI1b[3]), .out(PHI1b[4]));
+	LCELL PHI1b5_MC (.in(PHI1b[4]), .out(PHI1b[5]));
+	LCELL PHI1b6_MC (.in(PHI1b[5]), .out(PHI1b[6]));
+	LCELL PHI1b7_MC (.in(PHI1b[6] & PHI1in), .out(PHI1));
+	output C7Mout = C7M_2;
+	output PHI1out = PHI1;
+
+	/* Address Bus, etc. */
+	input nDEVSEL, nIOSEL, nIOSTRB; // Card select signals
+	input [15:0] A; // 6502 address bus
+	input nWE; // 6502 R/W
+	output [10:0] RA; // DRAM/ROM address
+	assign RA[10:8] = ASel ? Addr[10:8] : Addr[21:19];
+	assign RA[7:1] = ~nDEVSEL ? (ASel ? Addr[7:1] : Addr[18:12]) : Bank[6:0];
+	assign RA[0] = ~nDEVSEL ? (ASel ? Addr[0] : Addr[11]) : A[11];
+
+	/* Data Bus Routing */
+	// DRAM/ROM data bus
+	wire RDOE = nRES | (CSDBEN & (~nWE | (nDEVSEL & nIOSEL & nIOSTRB)));
+	inout [7:0] RD = RDOE ? D[7:0] : 8'bZ;
+	// Apple II data bus
+	wire DOE = nRES & CSDBEN & nWE & 
+		((~nDEVSEL & REGEN) | ~nIOSEL | (~nIOSTRB & IOROMEN));
+	wire [7:0] Dout = (nDEVSEL | RAMSELA) ? RD[7:0] :
+        AddrHSELA ? {1'b1, Addr[22:16]} : 
+        AddrMSELA ? Addr[15:8] : 
+        AddrLSELA ? Addr[7:0] : 8'h00;
+	inout [7:0] D = DOE ? Dout : 8'bZ;
+	
+	/* Inhibit output */
+	wire AROMSEL;
+	LCELL AROMSEL_MC (.in((A[15:12]==4'hD | A[15:12]==4'hE | A[15:12]==4'hF) & nWE & ~MODE), .out(AROMSEL));
+	output nINH = AROMSEL ? 1'b0 : 1'bZ;
+
+	/* DRAM and ROM Control Signals */
+	output nRCS = ~((~nIOSEL | (~nIOSTRB & IOROMEN)) & CSDBEN); // ROM chip select
+	output nROE = ~nWE; // need this for flash ROM
+	output nRWE = ~(~nWE & (~nDEVSEL | ~nIOSEL | ~nIOSTRB)); // for ROM & DRAM
+	output nRAS = ~(RASr | RASf);
+	output nCAS0 = ~(CASr | (CASf & ~nDEVSEL & ~Addr[22])); // DRAM CAS bank 0
+	output nCAS1 = ~(CASr | (CASf & ~nDEVSEL & Addr[22])); // DRAM CAS bank 1
+
+  	/* 6502-accessible Registers */
+	reg [6:0] Bank = 7'h00; // Bank register for ROM access
+	reg [22:0] Addr = 23'h00000; // RAM address register
+
+	/* CAS rising/falling edge components */
+	// These are combined to create the CAS outputs.
+	reg CASr = 1'b0;
+	reg CASf = 1'b0;
+	reg RASr = 1'b0;
+	reg RASf = 1'b0;
+
+	/* State Counters */
+	reg PHI1reg = 1'b0; // Saved PHI1 at last rising clock edge
+	reg PHI0seen = 1'b0; // Have we seen PHI0 since reset?
+	reg [2:0] S = 3'h0; // State counter
+	reg [3:0] Ref = 4'h0; // Refresh skip counter
+
+	/* Select Signals */
+	reg RAMSELreg = 1'b0; // RAMSEL registered at end of S4
+	wire BankSELA = A[3:0]==4'hF;
+	wire RAMSELA = A[3:0]==4'h3;
+	wire AddrHSELA = A[3:0]==4'h2;
+	wire AddrMSELA = A[3:0]==4'h1;
+	wire AddrLSELA = A[3:0]==4'h0;
+	LCELL BankWR_MC (.in(BankSELA & ~nWE & ~nDEVSEL & REGEN), .out(BankWR));
+	wire BankWR; // Bank reg. at Cn0F
+	wire RAMSEL = RAMSELA & ~nDEVSEL & REGEN; // RAM data reg. at Cn03
+	wire AddrHWR = AddrHSELA & ~nWE & ~nDEVSEL & REGEN; // Addr. hi reg. at Cn02
+	wire AddrMWR = AddrMSELA & ~nWE & ~nDEVSEL & REGEN; // Addr. mid reg. at Cn01
+	wire AddrLWR = AddrLSELA & ~nWE & ~nDEVSEL & REGEN; // Addr. lo reg. at Cn00
+
+	/* Misc. */
+	reg REGEN = 0; // Register enable
+	reg IOROMEN = 0; // IOSTRB ROM enable
+	reg CSDBEN = 0; // ROM CS, data bus driver gating
+	reg ASel = 0; // DRAM address multiplexer select
+
+	// Apple II Bus Compatibiltiy Rules:
+	// Synchronize to PHI0 or PHI1. (PHI1 here)
+	// PHI1's edge may be -20ns,+10ns relative to C7M.
+	// Delay the rising edge of PHI1 to get enough hold time:
+	// 		PHI1modified = PHI1 & PHI1delayed;
+	// Only sample /DEVSEL, /IOSEL at these times:
+	// 		2nd and 3rd rising edge of C7M in PHI0 (S4, S5)
+	//		all 3 falling edges of C7M in PHI0 (S4, S5, S6)
+	// Can sample /IOSTRB at same times as /IOSEL, plus:
+	//		1st rising edge of C7M in PHI0 (S3)
+
+	always @(posedge C7M, negedge nRES) begin
+		if (~nRES) begin // Reset
+			PHI1reg <= 1'b0;
+			PHI0seen <= 1'b0;
+			S <= 3'h0;
+			Ref <= 3'b000;
+			REGEN <= 1'b0;
+			IOROMEN <= 1'b0;
+			CSDBEN <= 1'b0;
+			Addr <= 23'h000000;
+			Bank <= 7'h00;
+			RAMSELreg <= 1'b0;
+		end else begin
+			// Synchronize state counter to S1 when just entering PHI1
+			PHI1reg <= PHI1; // Save old PHI1
+			if (~PHI1) PHI0seen <= 1; // PHI0seen set in PHI0
+			S <= (PHI1 & ~PHI1reg & PHI0seen) ? 4'h1 : 
+				S==0 ? 3'h0 :
+				S==7 ? 3'h7 : S+1;
+			
+			// Refresh counter allows DRAM refresh once every 13 cycles
+			if (S==3) Ref <= (Ref[3:2] == 2'b11) ? 4'h0 : Ref+1;
+
+			// Disable IOSTRB ROM when accessing 0xCFFF.
+			if (S==3 & ~nIOSTRB & A[10:0]==11'h7FF) IOROMEN <= 1'b0;
+
+			// Registers enabled at end of S4 by any IOSEL access (Cn00-CnFF).
+			if (S==4 & ~nIOSEL) REGEN <= 1;
+
+			// Enable IOSTRB ROM when accessing 0xCn00 in IOSEL ROM.
+			if (S==4 & ~nIOSEL /* & A[7:0]==8'h00 */) IOROMEN <= 1'b1;
+
+			// Register RAM "register" selected at end of S4.
+			if (S==4) RAMSELreg <= RAMSEL;
+
+			// Only drive Apple II data bus after state 4 to avoid bus fight.
+			// Thus we wait 1.5 7M cycles (210 ns) into PHI0 before driving.
+			// Same for driving the ROM/SRAM data bus (RD).
+			// Similarly, only select the ROM chip starting at the end of S4.
+			// This provides address setup time for write operations and 
+			// minimizes power consumption.
+			CSDBEN <= S[2]; /*S==4 | S==5 | S==6 | S==7 */
+
+			// Increment address register after RAM access,
+			// otherwise set register during S6 if accessed.
+			if (S==1 & RAMSELreg) Addr <= Addr+1; // RAMSELreg refers to prev.
+			else if (S==6) begin
+				if (AddrHWR) Addr[22:16] <= D[6:0]; // Addr hi
+				if (AddrMWR) Addr[15:8] <= D[7:0]; // Addr mid
+				if (AddrLWR) Addr[7:0] <= D[7:0]; // Addr lo
+				if (BankWR) Bank[6:0] <= D[6:0]; // Bank
+			end
+		end
+	end
+
+	/* DRAM RAS/CAS */
+	always @(posedge C7M, negedge nRES) begin
+		if (~nRES) begin RASr <= 1'b0; CASr <= 1'b0; ASel <= 1'b0;
+		end else begin
+			// RAS already asserted in middle of S4,
+			// so hold RAS through S5
+			RASr <= (S==4 & RAMSEL);
+
+			// Multiplex DRAM address in at end of S4 through S5 end.
+			ASel = RAMSEL & S[2] & ~S[1]; /*(S==4 | S==5)*/
+
+			// Refresh at end of S1 (i.e. through S2) 
+			// CAS whenever RAM seleced
+			CASr <= (S==1 & Ref==0) | (S==5 & RAMSEL);
+		end
+	end
+	always @(negedge C7M_2, negedge nRES) begin
+		if (~nRES) begin RASf <= 1'b0; CASf <= 1'b0;
+		end else begin
+			// Refresh in S2
+			// Row activate in S4 when accessing RAM
+			// Hold RAS in S5 when not doing late CAS for write.
+			RASf <= (S==2 & Ref==0) | ((S==4 | (S==5 & ~nWE) & RAMSEL));
+
+			// CASf gated by nDEVSEL; no need to predicate on RAMSEL.
+			// Early CAS in S5 for read operations.
+			CASf <= (S==5 & nWE) | (S==6) | (S==7);
+		end
+	end
+endmodule

cpld/db/GR8RAM.asm.qmsg

@@ -0,0 +1,5 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567306420769 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567306420769 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Aug 31 22:53:40 2019 " "Processing started: Sat Aug 31 22:53:40 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567306420769 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1567306420769 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1567306420769 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1567306422534 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "277 " "Peak virtual memory: 277 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567306423003 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 31 22:53:43 2019 " "Processing ended: Sat Aug 31 22:53:43 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567306423003 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567306423003 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567306423003 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1567306423003 ""}

cpld/db/GR8RAM.cmp.logdb

@@ -0,0 +1 @@
+v1

cpld/db/GR8RAM.db_info

@@ -0,0 +1,3 @@
+Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+Version_Index = 302049280
+Creation_Time = Sat Aug 31 21:50:24 2019

cpld/db/GR8RAM.fit 2.qmsg

@@ -0,0 +1,3 @@
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1566710684975 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1566710684990 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "287 " "Peak virtual memory: 287 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1566710685506 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 25 01:24:45 2019 " "Processing ended: Sun Aug 25 01:24:45 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1566710685506 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1566710685506 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1566710685506 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1566710685506 ""}

cpld/db/GR8RAM.fit 3.qmsg

@@ -0,0 +1,3 @@
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1566710988914 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1566710988930 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "287 " "Peak virtual memory: 287 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1566710989446 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 25 01:29:49 2019 " "Processing ended: Sun Aug 25 01:29:49 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1566710989446 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1566710989446 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1566710989446 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1566710989446 ""}

cpld/db/GR8RAM.fit 4.qmsg

@@ -0,0 +1,5 @@
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1566711499269 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1566711499284 ""}
+{ "Error" "EF7K_LAB_TOO_MANY_SEXP" "15 LAB_A 3 " "Can't place 15 sharable expanders in LAB LAB_A because the LAB can contain only 3 sharable expanders" {  } {  } 0 163057 "Can't place %1!d! sharable expanders in LAB %2!s! because the LAB can contain only %3!d! sharable expanders" 0 0 "Fitter" 0 -1 1566711499362 ""}
+{ "Error" "EF7K_FIT_FAIL" "" "Cannot find fit." {  } {  } 0 163000 "Cannot find fit." 0 0 "Fitter" 0 -1 1566711499362 ""}
+{ "Error" "EQEXE_ERROR_COUNT" "Fitter 2 s 1  Quartus II 32-bit " "Quartus II 32-bit Fitter was unsuccessful. 2 errors, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "287 " "Peak virtual memory: 287 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1566711499753 ""} { "Error" "EQEXE_END_BANNER_TIME" "Sun Aug 25 01:38:19 2019 " "Processing ended: Sun Aug 25 01:38:19 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1566711499753 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1566711499753 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1566711499753 ""}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1566711499753 ""}

cpld/db/GR8RAM.fit 5.qmsg

@@ -0,0 +1,3 @@
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1566712873057 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1566712873088 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "287 " "Peak virtual memory: 287 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1566712873807 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 25 02:01:13 2019 " "Processing ended: Sun Aug 25 02:01:13 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1566712873807 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1566712873807 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1566712873807 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1566712873807 ""}

cpld/db/GR8RAM.fit 6.qmsg

@@ -0,0 +1,3 @@
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1566713553094 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1566713553110 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "287 " "Peak virtual memory: 287 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1566713553610 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 25 02:12:33 2019 " "Processing ended: Sun Aug 25 02:12:33 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1566713553610 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1566713553610 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1566713553610 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1566713553610 ""}

cpld/db/GR8RAM.fit 7.qmsg

@@ -0,0 +1,3 @@
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1566716030143 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1566716030190 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "287 " "Peak virtual memory: 287 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1566716031347 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 25 02:53:51 2019 " "Processing ended: Sun Aug 25 02:53:51 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1566716031347 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1566716031347 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1566716031347 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1566716031347 ""}

cpld/db/GR8RAM.fit 8.qmsg

@@ -0,0 +1,3 @@
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1566718076312 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1566718076344 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "287 " "Peak virtual memory: 287 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1566718077453 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 25 03:27:57 2019 " "Processing ended: Sun Aug 25 03:27:57 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1566718077453 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1566718077453 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1566718077453 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1566718077453 ""}

cpld/db/GR8RAM.fit.qmsg

@@ -0,0 +1,4 @@
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1567306416644 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1567306416878 ""}
+{ "Warning" "WF7K_INCONSISTENT_MC_PIN_LOCATION" "PHI1b7_MC LC127 PHI1out PIN_30 " "Can't place macrocell \"PHI1b7_MC\" assigned to LC127 and node \"PHI1out\" assigned to PIN_30 -- ignoring macrocell assignment" {  } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 23 -1 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 21 0 0 } }  } 0 163058 "Can't place macrocell \"%1!s!\" assigned to %2!s! and node \"%3!s!\" assigned to %4!s! -- ignoring macrocell assignment" 0 0 "Fitter" 0 -1 1567306417144 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "287 " "Peak virtual memory: 287 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567306418425 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 31 22:53:38 2019 " "Processing ended: Sat Aug 31 22:53:38 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567306418425 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567306418425 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567306418425 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1567306418425 ""}

cpld/db/GR8RAM.hier_info

@@ -0,0 +1,152 @@
+|GR8RAM
+C7M => CASr.CLK
+C7M => RASr.CLK
+C7M => ASel.CLK
+C7M => RAMSELreg.CLK
+C7M => Bank[0].CLK
+C7M => Bank[1].CLK
+C7M => Bank[2].CLK
+C7M => Bank[3].CLK
+C7M => Bank[4].CLK
+C7M => Bank[5].CLK
+C7M => Bank[6].CLK
+C7M => Addr[0].CLK
+C7M => Addr[1].CLK
+C7M => Addr[2].CLK
+C7M => Addr[3].CLK
+C7M => Addr[4].CLK
+C7M => Addr[5].CLK
+C7M => Addr[6].CLK
+C7M => Addr[7].CLK
+C7M => Addr[8].CLK
+C7M => Addr[9].CLK
+C7M => Addr[10].CLK
+C7M => Addr[11].CLK
+C7M => Addr[12].CLK
+C7M => Addr[13].CLK
+C7M => Addr[14].CLK
+C7M => Addr[15].CLK
+C7M => Addr[16].CLK
+C7M => Addr[17].CLK
+C7M => Addr[18].CLK
+C7M => Addr[19].CLK
+C7M => Addr[20].CLK
+C7M => Addr[21].CLK
+C7M => Addr[22].CLK
+C7M => CSDBEN.CLK
+C7M => IOROMEN.CLK
+C7M => REGEN.CLK
+C7M => Ref[0].CLK
+C7M => Ref[1].CLK
+C7M => Ref[2].CLK
+C7M => Ref[3].CLK
+C7M => S[0].CLK
+C7M => S[1].CLK
+C7M => S[2].CLK
+C7M => PHI0seen.CLK
+C7M => PHI1reg.CLK
+C7M_2 => always2.IN0
+C7M_2 => C7Mout.DATAIN
+Q3 => ~NO_FANOUT~
+PHI0in => ~NO_FANOUT~
+PHI1in => comb.IN0
+PHI1in => PHI1b0_MC.DATAIN
+nRES => RDOE.IN1
+nRES => comb.IN0
+nRES => always0.IN0
+MODE => comb.IN0
+A[0] => Equal3.IN7
+A[0] => Equal4.IN7
+A[0] => Equal5.IN7
+A[0] => Equal6.IN7
+A[0] => Equal7.IN7
+A[0] => Equal12.IN21
+A[1] => Equal3.IN6
+A[1] => Equal4.IN6
+A[1] => Equal5.IN6
+A[1] => Equal6.IN6
+A[1] => Equal7.IN6
+A[1] => Equal12.IN20
+A[2] => Equal3.IN5
+A[2] => Equal4.IN5
+A[2] => Equal5.IN5
+A[2] => Equal6.IN5
+A[2] => Equal7.IN5
+A[2] => Equal12.IN19
+A[3] => Equal3.IN4
+A[3] => Equal4.IN4
+A[3] => Equal5.IN4
+A[3] => Equal6.IN4
+A[3] => Equal7.IN4
+A[3] => Equal12.IN18
+A[4] => Equal12.IN17
+A[5] => Equal12.IN16
+A[6] => Equal12.IN15
+A[7] => Equal12.IN14
+A[8] => Equal12.IN13
+A[9] => Equal12.IN12
+A[10] => Equal12.IN11
+A[11] => RA.DATAA
+A[12] => Equal0.IN7
+A[12] => Equal1.IN7
+A[12] => Equal2.IN7
+A[13] => Equal0.IN6
+A[13] => Equal1.IN6
+A[13] => Equal2.IN6
+A[14] => Equal0.IN5
+A[14] => Equal1.IN5
+A[14] => Equal2.IN5
+A[15] => Equal0.IN4
+A[15] => Equal1.IN4
+A[15] => Equal2.IN4
+RA[0] <= RA.DB_MAX_OUTPUT_PORT_TYPE
+RA[1] <= RA.DB_MAX_OUTPUT_PORT_TYPE
+RA[2] <= RA.DB_MAX_OUTPUT_PORT_TYPE
+RA[3] <= RA.DB_MAX_OUTPUT_PORT_TYPE
+RA[4] <= RA.DB_MAX_OUTPUT_PORT_TYPE
+RA[5] <= RA.DB_MAX_OUTPUT_PORT_TYPE
+RA[6] <= RA.DB_MAX_OUTPUT_PORT_TYPE
+RA[7] <= RA.DB_MAX_OUTPUT_PORT_TYPE
+RA[8] <= RA.DB_MAX_OUTPUT_PORT_TYPE
+RA[9] <= RA.DB_MAX_OUTPUT_PORT_TYPE
+RA[10] <= RA.DB_MAX_OUTPUT_PORT_TYPE
+nWE => comb.IN0
+nWE => comb.IN1
+nWE => comb.IN1
+nWE => comb.IN0
+nWE => CASf.IN1
+D[0] <> D[0]
+D[1] <> D[1]
+D[2] <> D[2]
+D[3] <> D[3]
+D[4] <> D[4]
+D[5] <> D[5]
+D[6] <> D[6]
+D[7] <> D[7]
+RD[0] <> RD[0]
+RD[1] <> RD[1]
+RD[2] <> RD[2]
+RD[3] <> RD[3]
+RD[4] <> RD[4]
+RD[5] <> RD[5]
+RD[6] <> RD[6]
+RD[7] <> RD[7]
+nINH <= nINH.DB_MAX_OUTPUT_PORT_TYPE
+nDEVSEL => RA.IN0
+nDEVSEL => comb.IN0
+nDEVSEL => comb.IN0
+nDEVSEL => comb.IN0
+nIOSEL => comb.IN1
+nIOSEL => comb.IN0
+nIOSTRB => comb.IN1
+nIOSTRB => comb.IN0
+nRAS <= comb.DB_MAX_OUTPUT_PORT_TYPE
+nCAS0 <= comb.DB_MAX_OUTPUT_PORT_TYPE
+nCAS1 <= comb.DB_MAX_OUTPUT_PORT_TYPE
+nRCS <= comb.DB_MAX_OUTPUT_PORT_TYPE
+nROE <= comb.DB_MAX_OUTPUT_PORT_TYPE
+nRWE <= comb.DB_MAX_OUTPUT_PORT_TYPE
+C7Mout <= C7M_2.DB_MAX_OUTPUT_PORT_TYPE
+PHI1out <= PHI1b7_MC.DB_MAX_OUTPUT_PORT_TYPE
+
+

cpld/db/GR8RAM.lpc.html

@@ -0,0 +1,18 @@
+<TABLE>
+<TR  bgcolor="#C0C0C0">
+<TH>Hierarchy</TH>
+<TH>Input</TH>
+<TH>Constant Input</TH>
+<TH>Unused Input</TH>
+<TH>Floating Input</TH>
+<TH>Output</TH>
+<TH>Constant Output</TH>
+<TH>Unused Output</TH>
+<TH>Floating Output</TH>
+<TH>Bidir</TH>
+<TH>Constant Bidir</TH>
+<TH>Unused Bidir</TH>
+<TH>Input only Bidir</TH>
+<TH>Output only Bidir</TH>
+</TR>
+</TABLE>

cpld/db/GR8RAM.lpc.txt

@@ -0,0 +1,5 @@
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates                                                                                                                                                                                     ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+