From eca42a01619d187b96680cb6f1ccf2ba2a1f5d45 Mon Sep 17 00:00:00 2001 From: Zane Kaminski Date: Tue, 28 Feb 2023 11:20:35 -0500 Subject: [PATCH] Update GR8RAM.qsf --- cpld2/GR8RAM.qsf | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/cpld2/GR8RAM.qsf b/cpld2/GR8RAM.qsf index aa58bea..e2e3f88 100644 --- a/cpld2/GR8RAM.qsf +++ b/cpld2/GR8RAM.qsf @@ -57,7 +57,8 @@ set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity -set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scanset_location_assignment PIN_2 -to RA[5] +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan +set_location_assignment PIN_2 -to RA[5] set_location_assignment PIN_3 -to RA[6] set_location_assignment PIN_4 -to RA[3] set_location_assignment PIN_5 -to nFCS