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Added transfer counters

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Zane Kaminski
2020-02-26 03:34:33 -05:00
parent fe0a092924
commit ef9b5852fb
1 changed files with 4 additions and 0 deletions
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cpld/GR8RAM.v
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@@ -72,6 +72,10 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
/* Increment Control */ /* Increment Control */
reg IncAddrL = 0, IncAddrM = 0, IncAddrH = 0; reg IncAddrL = 0, IncAddrM = 0, IncAddrH = 0;
/* Transfer Counters */
reg [15:0] TCnt = 0;
reg [15:0] Dest = 0;
/* CAS rising/falling edge components */ /* CAS rising/falling edge components */
// These are combined to create the CAS outputs. // These are combined to create the CAS outputs.