diff --git a/cpld/GR8RAM.qws b/cpld/GR8RAM.qws new file mode 100755 index 0000000..28bd7ed Binary files /dev/null and b/cpld/GR8RAM.qws differ diff --git a/cpld/GR8RAM.v b/cpld/GR8RAM.v index f0e5eb4..bccb1db 100644 --- a/cpld/GR8RAM.v +++ b/cpld/GR8RAM.v @@ -10,19 +10,6 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, reg PHI0r1, PHI0r2; always @(posedge C25M) begin PHI0r1 <= PHI0; PHI0r2 <= PHI0r1; end - /* Unused Pins */ - output RAdir = 1; - input INTin; - output INTout = INTin; - input DMAin; - output DMAout = DMAin; - output nDMAout = 1; - output nNMIout = 1; - output nINHout = 1; - output nRDYout = 1; - output nIRQout = 1; - output RWout = 1; - /* Reset/brown-out detect synchronized inputs */ input nRES; reg nRESr0, nRESr; @@ -56,13 +43,15 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, wire ROMSpecRD = RA[15:12]==4'hC && RA[11:8]!=4'h0 && nWE && ((RA[11] && IOROMEN) || (~RA[11])); wire REGSpecSEL = RA[15:12]==4'hC && RA[11:8]==4'h0 && RA[7] && REGEN; wire BankSpecSEL = REGSpecSEL && RA[3:0]==4'hF; - wire RAMSpecSEL = REGSpecSEL && RA[3:0]==4'h3; + wire RAMRegSpecSEL = REGSpecSEL && RA[3:0]==4'h3; + wire RAMSpecSEL = RAMRegSpecSEL && (~SetEN24bit || SetEN16MB || ~Addr[23]); wire AddrHSpecSEL = REGSpecSEL && RA[3:0]==4'h2; wire AddrMSpecSEL = REGSpecSEL && RA[3:0]==4'h1; wire AddrLSpecSEL = REGSpecSEL && RA[3:0]==4'h0; reg ROMSpecRDr, RAMSpecSELr, nWEr; wire BankSEL = REGEN && ~nDEVSEL && BankSpecSEL; wire RAMSEL = ~nDEVSEL && RAMSpecSELr; + wire RAMRegSEL = ~nDEVSEL && RAMRegSpecSEL; wire RAMWR = RAMSEL && ~nWEr; wire AddrHSEL = REGEN && ~nDEVSEL && AddrHSpecSEL; wire AddrMSEL = REGEN && ~nDEVSEL && AddrMSpecSEL; @@ -76,16 +65,14 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, /* IOROMEN and REGEN control */ reg IOROMEN = 0; reg REGEN = 0; + wire IOROMRES = ~nRES || (RA[10:0]==11'h7FF && ~nIOSTRB); + always @(posedge C25M, posedge IOROMRES) begin + if (IOROMRES) IOROMEN <= 0; + else if (PS==8 && ~nIOSEL) IOROMEN <= 1; + end always @(posedge C25M, negedge nRESr) begin - if (~nRESr) begin - IOROMEN <= 0; - REGEN <= 0; - end else if (PS==8 && ~nIOSTRB && RA[10:0]==11'h7FF) begin - IOROMEN <= 0; - end else if (PS==8 && ~nIOSEL) begin - IOROMEN <= 1; - REGEN <= 1; - end + if (~nRESr) REGEN <= 0; + else if (PS==8 && ~nIOSEL) REGEN <= 1; end /* Apple data bus */ @@ -106,7 +93,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, AddrIncM <= 0; AddrIncH <= 0; end else begin - if (PS==8 && RAMSEL) AddrIncL <= 1; + if (PS==8 && RAMRegSEL) AddrIncL <= 1; else AddrIncL <= 0; if (PS==8 && AddrLSEL && ~nWEr) begin @@ -264,10 +251,9 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, end input [1:0] SetFW; - wire [1:0] SetROM = 2'b01; - wire SetRF = SetFW[1:0] != 2'b11; - wire SetLim1M = SetFW[1]; - wire SetLim8M = SetFW[1:0] != 2'b00; + wire [1:0] SetROM = 2'b11;//~SetFW[1:0]; + wire SetEN16MB = SetROM[1:0]==2'b11; + wire SetEN24bit = SetROM[1]; /* SDRAM data bus */ inout [7:0] SD = SDOE ? WRD[7:0] : 8'bZ; @@ -289,8 +275,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, end 5: begin // NOP CKE if (AddrLSpecSEL) RDD[7:0] <= Addr[7:0]; else if (AddrMSpecSEL) RDD[7:0] <= Addr[15:8]; - else if (AddrHSpecSEL) RDD[7:0] <= Addr[23:16]; - else if (AddrHSpecSEL) RDD[7:0] <= {4'hF, Addr[19:16]}; + else if (AddrHSpecSEL) RDD[7:0] <= { SetEN24bit ? Addr[23:20] : 4'hF, Addr[19:16] }; else RDD[7:0] <= SD[7:0]; end 6: begin // NOP CKE if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI }; @@ -445,15 +430,16 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, SBA[1:0] <= { 2'b10 }; SA[12:0] <= { 10'b0011000100, LS[12:10] }; end else if (RAMSpecSELr) begin - SBA[1:0] <= { 1'b0, Addr[23] }; - SA[12:0] <= Addr [22:10]; + SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 }; + SA[12:10] <= SetEN24bit ? Addr[22:20] : 3'b000; + SA[9:0] <= Addr[19:10]; end else begin SBA[1:0] <= 2'b10; SA[12:0] <= { 10'b0011000100, Bank, RA[11:10] }; end end 2: begin // RD if (RAMSpecSELr) begin - SBA[1:0] <= { 1'b0, Addr[23] }; + SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 }; SA[12:0] <= { 4'b0011, Addr[9:1] }; DQML <= Addr[0]; DQMH <= ~Addr[0]; @@ -495,7 +481,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, DQML <= LS[0]; DQMH <= ~LS[0]; end else begin - SBA[1:0] <= { 1'b0, Addr[23] }; + SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 }; SA[12:0] <= { 4'b0011, Addr[9:1] }; DQML <= Addr[0]; DQMH <= ~Addr[0]; @@ -538,4 +524,18 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW, end endcase end + + /* DMA/INT in/out */ + input INTin, DMAin; + output INTout = INTin; + output DMAout = DMAin; + + /* Unused Pins */ + output RAdir = 1; + output nDMAout = 1; + output nNMIout = 1; + output nINHout = 1; + output nRDYout = 1; + output nIRQout = 1; + output RWout = 1; endmodule diff --git a/cpld/db/GR8RAM.(0).cnf.cdb b/cpld/db/GR8RAM.(0).cnf.cdb index 20bb6f9..23709ce 100755 Binary files a/cpld/db/GR8RAM.(0).cnf.cdb and b/cpld/db/GR8RAM.(0).cnf.cdb differ diff --git a/cpld/db/GR8RAM.(0).cnf.hdb b/cpld/db/GR8RAM.(0).cnf.hdb index 8837f5f..2ddf8ec 100755 Binary files a/cpld/db/GR8RAM.(0).cnf.hdb and b/cpld/db/GR8RAM.(0).cnf.hdb differ diff --git a/cpld/db/GR8RAM.asm.qmsg b/cpld/db/GR8RAM.asm.qmsg index aefe606..381f231 100755 --- a/cpld/db/GR8RAM.asm.qmsg +++ b/cpld/db/GR8RAM.asm.qmsg @@ -1,6 +1,6 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618741636703 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618741636718 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 18 06:27:16 2021 " "Processing started: Sun Apr 18 06:27:16 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618741636718 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1618741636718 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1618741636718 ""} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1618741637999 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1618741638015 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "293 " "Peak virtual memory: 293 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618741638531 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 18 06:27:18 2021 " "Processing ended: Sun Apr 18 06:27:18 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618741638531 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618741638531 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618741638531 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1618741638531 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618810037113 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618810037113 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Apr 19 01:27:16 2021 " "Processing started: Mon Apr 19 01:27:16 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618810037113 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1618810037113 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1618810037113 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1618810038270 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1618810038285 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "293 " "Peak virtual memory: 293 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618810038786 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 19 01:27:18 2021 " "Processing ended: Mon Apr 19 01:27:18 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618810038786 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618810038786 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618810038786 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1618810038786 ""} diff --git a/cpld/db/GR8RAM.asm.rdb b/cpld/db/GR8RAM.asm.rdb index 7360c69..63807fb 100755 Binary files a/cpld/db/GR8RAM.asm.rdb and b/cpld/db/GR8RAM.asm.rdb differ diff --git a/cpld/db/GR8RAM.asm_labs.ddb b/cpld/db/GR8RAM.asm_labs.ddb index 5ee7720..5ee9452 100755 Binary files a/cpld/db/GR8RAM.asm_labs.ddb and b/cpld/db/GR8RAM.asm_labs.ddb differ diff --git a/cpld/db/GR8RAM.cmp.cdb b/cpld/db/GR8RAM.cmp.cdb index 08c8459..e60a210 100755 Binary files a/cpld/db/GR8RAM.cmp.cdb and b/cpld/db/GR8RAM.cmp.cdb differ diff --git a/cpld/db/GR8RAM.cmp.hdb b/cpld/db/GR8RAM.cmp.hdb index aa22cae..9b8cf56 100755 Binary files a/cpld/db/GR8RAM.cmp.hdb and b/cpld/db/GR8RAM.cmp.hdb differ diff --git a/cpld/db/GR8RAM.cmp.idb b/cpld/db/GR8RAM.cmp.idb index 267102c..0bcd05a 100755 Binary files a/cpld/db/GR8RAM.cmp.idb and b/cpld/db/GR8RAM.cmp.idb differ diff --git a/cpld/db/GR8RAM.cmp.rdb b/cpld/db/GR8RAM.cmp.rdb index de1cac3..e3e658d 100755 Binary files a/cpld/db/GR8RAM.cmp.rdb and b/cpld/db/GR8RAM.cmp.rdb differ diff --git a/cpld/db/GR8RAM.cmp0.ddb b/cpld/db/GR8RAM.cmp0.ddb index 411b0b6..f52ca5a 100755 Binary files a/cpld/db/GR8RAM.cmp0.ddb and b/cpld/db/GR8RAM.cmp0.ddb differ diff --git a/cpld/db/GR8RAM.fit.qmsg b/cpld/db/GR8RAM.fit.qmsg index 6bd934d..34105c7 100755 --- a/cpld/db/GR8RAM.fit.qmsg +++ b/cpld/db/GR8RAM.fit.qmsg @@ -1,39 +1,39 @@ -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1618741628453 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1618741628468 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618741628671 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618741628671 ""} -{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1618741628984 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1618741629015 ""} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618741629343 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618741629343 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618741629343 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618741629343 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618741629343 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1618741629343 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1618741629531 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1618741629531 ""} -{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1618741629562 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1618741629562 ""} -{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618741629562 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618741629562 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 C25M " " 1.000 C25M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618741629562 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI0 " " 1.000 PHI0" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618741629562 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1618741629562 ""} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618741629562 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618741629578 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618741629578 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618741629625 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI0 Global clock " "Automatically promoted some destinations of signal \"PHI0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~1 " "Destination \"comb~1\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618741629625 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI0r1 " "Destination \"PHI0r1\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 11 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618741629625 ""} } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618741629625 ""} -{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI0 " "Pin \"PHI0\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI0 } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "PHI0" } } } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 368 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1618741629625 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "nRESr Global clock " "Automatically promoted signal \"nRESr\" to use Global clock" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 29 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618741629625 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618741629625 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1618741629640 ""} -{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1618741629703 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1618741629781 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1618741629781 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1618741629781 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1618741629781 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618741629828 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1618741630000 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618741630359 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1618741630375 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1618741632140 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:02 " "Fitter placement operations ending: elapsed time is 00:00:02" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618741632140 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1618741632203 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "33 " "Router estimated average interconnect usage is 33% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "33 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 33% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 33% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 33% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1618741632718 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1618741632718 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618741633390 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.75 " "Total time spent on timing analysis during the Fitter is 0.75 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1618741633406 ""} -{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618741633406 ""} -{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1618741633453 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1618741633843 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "382 " "Peak virtual memory: 382 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618741634140 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 18 06:27:14 2021 " "Processing ended: Sun Apr 18 06:27:14 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618741634140 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618741634140 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618741634140 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1618741634140 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1618810028160 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1618810028175 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618810028331 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618810028331 ""} +{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1618810028597 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1618810028628 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618810028972 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618810028972 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618810028972 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618810028972 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618810028972 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1618810028972 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1618810029144 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1618810029144 ""} +{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1618810029175 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1618810029175 ""} +{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618810029175 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618810029175 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 C25M " " 1.000 C25M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618810029175 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI0 " " 1.000 PHI0" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618810029175 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1618810029175 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618810029175 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618810029191 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618810029191 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618810029207 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI0 Global clock " "Automatically promoted some destinations of signal \"PHI0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~1 " "Destination \"comb~1\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618810029207 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI0r1 " "Destination \"PHI0r1\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618810029207 ""} } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618810029207 ""} +{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI0 " "Pin \"PHI0\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI0 } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "PHI0" } } } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 371 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1618810029207 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "nRESr Global clock " "Automatically promoted signal \"nRESr\" to use Global clock" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 15 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618810029207 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618810029222 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1618810029222 ""} +{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1618810029253 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1618810029316 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1618810029332 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1618810029332 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1618810029332 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618810029363 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1618810030394 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618810030754 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1618810030769 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1618810031988 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618810031988 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1618810032051 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "35 " "Router estimated average interconnect usage is 35% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "35 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 35% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 35% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 35% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1618810032816 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1618810032816 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618810033519 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.53 " "Total time spent on timing analysis during the Fitter is 0.53 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1618810033551 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618810033551 ""} +{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1618810033598 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1618810034223 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "372 " "Peak virtual memory: 372 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618810034441 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 19 01:27:14 2021 " "Processing ended: Mon Apr 19 01:27:14 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618810034441 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618810034441 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:09 " "Total CPU time (on all processors): 00:00:09" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618810034441 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1618810034441 ""} diff --git a/cpld/db/GR8RAM.hier_info b/cpld/db/GR8RAM.hier_info index a69869f..69887d7 100755 --- a/cpld/db/GR8RAM.hier_info +++ b/cpld/db/GR8RAM.hier_info @@ -103,54 +103,47 @@ PHI0 => RAMSpecSELr.CLK PHI0 => ROMSpecRDr.CLK PHI0 => PHI0r1.DATAIN nRES => nRESr0.DATAIN +nRES => IOROMRES.IN1 nRESout <= nRESout~reg0.DB_MAX_OUTPUT_PORT_TYPE SetFW[0] => ~NO_FANOUT~ SetFW[1] => ~NO_FANOUT~ -RAdir <= INTin => INTout.DATAIN INTout <= INTin.DB_MAX_OUTPUT_PORT_TYPE DMAin => DMAout.DATAIN DMAout <= DMAin.DB_MAX_OUTPUT_PORT_TYPE -nDMAout <= nNMIout <= nIRQout <= nRDYout <= nINHout <= RWout <= -nIOSEL => comb.IN0 -nIOSEL => always5.IN1 -nDEVSEL => comb.IN1 -nDEVSEL => RAMSEL.IN1 -nDEVSEL => comb.IN1 -nIOSTRB => comb.IN1 -nIOSTRB => always5.IN1 +nDMAout <= RA[0] => DQML.DATAA RA[0] => Equal8.IN3 -RA[0] => Equal9.IN1 -RA[0] => Equal10.IN3 -RA[0] => Equal11.IN0 +RA[0] => Equal9.IN3 +RA[0] => Equal10.IN2 +RA[0] => Equal11.IN3 RA[0] => Equal12.IN3 RA[0] => Equal13.IN10 RA[0] => DQMH.DATAA RA[1] => SA.DATAA RA[1] => Equal8.IN2 -RA[1] => Equal9.IN0 -RA[1] => Equal10.IN0 -RA[1] => Equal11.IN3 +RA[1] => Equal9.IN2 +RA[1] => Equal10.IN3 +RA[1] => Equal11.IN2 RA[1] => Equal12.IN2 RA[1] => Equal13.IN9 RA[2] => SA.DATAA RA[2] => Equal8.IN1 -RA[2] => Equal9.IN3 -RA[2] => Equal10.IN2 -RA[2] => Equal11.IN2 +RA[2] => Equal9.IN1 +RA[2] => Equal10.IN1 +RA[2] => Equal11.IN1 RA[2] => Equal12.IN1 RA[2] => Equal13.IN8 RA[3] => SA.DATAA RA[3] => Equal8.IN0 -RA[3] => Equal9.IN2 -RA[3] => Equal10.IN1 -RA[3] => Equal11.IN1 +RA[3] => Equal9.IN0 +RA[3] => Equal10.IN0 +RA[3] => Equal11.IN0 RA[3] => Equal12.IN0 RA[3] => Equal13.IN7 RA[4] => SA.DATAA @@ -175,10 +168,10 @@ RA[11] => comb.IN1 RA[11] => SA.DATAA RA[11] => comb.IN1 RA[11] => Equal7.IN0 -RA[12] => Equal6.IN3 -RA[13] => Equal6.IN2 -RA[14] => Equal6.IN1 -RA[15] => Equal6.IN0 +RA[12] => Equal6.IN1 +RA[13] => Equal6.IN0 +RA[14] => Equal6.IN3 +RA[15] => Equal6.IN2 nWE => comb.IN1 nWE => comb.IN1 nWE => nWEr.DATAIN @@ -190,7 +183,16 @@ RD[4] <> RD[4] RD[5] <> RD[5] RD[6] <> RD[6] RD[7] <> RD[7] +RAdir <= RDdir <= comb.DB_MAX_OUTPUT_PORT_TYPE +nIOSEL => comb.IN0 +nIOSEL => always5.IN1 +nDEVSEL => comb.IN1 +nDEVSEL => RAMSEL.IN1 +nDEVSEL => comb.IN1 +nDEVSEL => RAMRegSEL.IN1 +nIOSTRB => comb.IN1 +nIOSTRB => comb.IN1 SBA[0] <= SBA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE SBA[1] <= SBA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE SA[0] <= SA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE diff --git a/cpld/db/GR8RAM.hif b/cpld/db/GR8RAM.hif index 0b0d4e5..a16b34c 100755 Binary files a/cpld/db/GR8RAM.hif and b/cpld/db/GR8RAM.hif differ diff --git a/cpld/db/GR8RAM.map.cdb b/cpld/db/GR8RAM.map.cdb index cb8354c..57548e3 100755 Binary files a/cpld/db/GR8RAM.map.cdb and b/cpld/db/GR8RAM.map.cdb differ diff --git a/cpld/db/GR8RAM.map.hdb b/cpld/db/GR8RAM.map.hdb index ba5d00f..67a001c 100755 Binary files a/cpld/db/GR8RAM.map.hdb and b/cpld/db/GR8RAM.map.hdb differ diff --git a/cpld/db/GR8RAM.map.qmsg b/cpld/db/GR8RAM.map.qmsg index 3d13ed4..597a4d0 100755 --- a/cpld/db/GR8RAM.map.qmsg +++ b/cpld/db/GR8RAM.map.qmsg @@ -1,23 +1,20 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618741619843 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618741619843 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 18 06:26:59 2021 " "Processing started: Sun Apr 18 06:26:59 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618741619843 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618741619843 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618741619843 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1618741621546 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(93) " "Verilog HDL warning at GR8RAM.v(93): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 93 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618741621734 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(274) " "Verilog HDL warning at GR8RAM.v(274): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 274 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618741621734 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1618741621749 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1618741621749 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1618741621859 ""} -{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "SetRF GR8RAM.v(269) " "Verilog HDL or VHDL warning at GR8RAM.v(269): object \"SetRF\" assigned a value but never read" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 269 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1618741621874 "|GR8RAM"} -{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "SetLim1M GR8RAM.v(270) " "Verilog HDL or VHDL warning at GR8RAM.v(270): object \"SetLim1M\" assigned a value but never read" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 270 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1618741621874 "|GR8RAM"} -{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "SetLim8M GR8RAM.v(271) " "Verilog HDL or VHDL warning at GR8RAM.v(271): object \"SetLim8M\" assigned a value but never read" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 271 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1618741621874 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(34) " "Verilog HDL assignment warning at GR8RAM.v(34): truncated value with size 32 to match size of target (14)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 34 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618741621874 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(117) " "Verilog HDL assignment warning at GR8RAM.v(117): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 117 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618741621874 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(125) " "Verilog HDL assignment warning at GR8RAM.v(125): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 125 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618741621874 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(132) " "Verilog HDL assignment warning at GR8RAM.v(132): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 132 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618741621874 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(325) " "Verilog HDL assignment warning at GR8RAM.v(325): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 325 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618741621890 "|GR8RAM"} -{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 -1 1618741623234 ""} -{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 15 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618741623562 "|GR8RAM|RAdir"} { "Warning" "WMLS_MLS_STUCK_PIN" "nDMAout VCC " "Pin \"nDMAout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 20 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618741623562 "|GR8RAM|nDMAout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nNMIout VCC " "Pin \"nNMIout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 21 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618741623562 "|GR8RAM|nNMIout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nIRQout VCC " "Pin \"nIRQout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 24 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618741623562 "|GR8RAM|nIRQout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nRDYout VCC " "Pin \"nRDYout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618741623562 "|GR8RAM|nRDYout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nINHout VCC " "Pin \"nINHout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 22 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618741623562 "|GR8RAM|nINHout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RWout VCC " "Pin \"RWout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618741623562 "|GR8RAM|RWout"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1618741623562 ""} -{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1618741624078 ""} -{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SetFW\[0\] " "No output dependent on input pin \"SetFW\[0\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 267 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1618741624109 "|GR8RAM|SetFW[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SetFW\[1\] " "No output dependent on input pin \"SetFW\[1\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 267 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1618741624109 "|GR8RAM|SetFW[1]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1618741624109 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "308 " "Implemented 308 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "28 " "Implemented 28 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1618741624109 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1618741624109 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1618741624109 ""} { "Info" "ICUT_CUT_TM_LCELLS" "228 " "Implemented 228 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1618741624109 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1618741624109 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1618741624343 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 19 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 19 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "301 " "Peak virtual memory: 301 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618741624500 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 18 06:27:04 2021 " "Processing ended: Sun Apr 18 06:27:04 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618741624500 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618741624500 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618741624500 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618741624500 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618810019690 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618810019690 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Apr 19 01:26:59 2021 " "Processing started: Mon Apr 19 01:26:59 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618810019690 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618810019690 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618810019690 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1618810021253 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(79) " "Verilog HDL warning at GR8RAM.v(79): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 79 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618810021425 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(259) " "Verilog HDL warning at GR8RAM.v(259): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 259 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618810021425 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1618810021440 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1618810021440 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1618810021550 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(20) " "Verilog HDL assignment warning at GR8RAM.v(20): truncated value with size 32 to match size of target (14)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 20 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618810021565 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(103) " "Verilog HDL assignment warning at GR8RAM.v(103): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 103 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618810021565 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(111) " "Verilog HDL assignment warning at GR8RAM.v(111): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 111 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618810021565 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(118) " "Verilog HDL assignment warning at GR8RAM.v(118): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 118 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618810021565 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(309) " "Verilog HDL assignment warning at GR8RAM.v(309): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 309 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618810021565 "|GR8RAM"} +{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 -1 1618810022925 ""} +{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "nNMIout VCC " "Pin \"nNMIout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 536 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618810023222 "|GR8RAM|nNMIout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nIRQout VCC " "Pin \"nIRQout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 539 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618810023222 "|GR8RAM|nIRQout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nRDYout VCC " "Pin \"nRDYout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 538 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618810023222 "|GR8RAM|nRDYout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nINHout VCC " "Pin \"nINHout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 537 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618810023222 "|GR8RAM|nINHout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RWout VCC " "Pin \"RWout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 540 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618810023222 "|GR8RAM|RWout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nDMAout VCC " "Pin \"nDMAout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 535 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618810023222 "|GR8RAM|nDMAout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 534 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618810023222 "|GR8RAM|RAdir"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1618810023222 ""} +{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1618810023737 ""} +{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SetFW\[0\] " "No output dependent on input pin \"SetFW\[0\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 253 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1618810023784 "|GR8RAM|SetFW[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SetFW\[1\] " "No output dependent on input pin \"SetFW\[1\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 253 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1618810023784 "|GR8RAM|SetFW[1]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1618810023784 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "309 " "Implemented 309 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "28 " "Implemented 28 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1618810023784 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1618810023784 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1618810023784 ""} { "Info" "ICUT_CUT_TM_LCELLS" "229 " "Implemented 229 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1618810023784 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1618810023784 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1618810024034 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 16 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 16 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "301 " "Peak virtual memory: 301 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618810024253 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 19 01:27:04 2021 " "Processing ended: Mon Apr 19 01:27:04 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618810024253 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618810024253 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618810024253 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618810024253 ""} diff --git a/cpld/db/GR8RAM.map.rdb b/cpld/db/GR8RAM.map.rdb index 5c4fec3..476c9ee 100755 Binary files a/cpld/db/GR8RAM.map.rdb and b/cpld/db/GR8RAM.map.rdb differ diff --git a/cpld/db/GR8RAM.pre_map.hdb b/cpld/db/GR8RAM.pre_map.hdb index 1c0005d..83c3677 100755 Binary files a/cpld/db/GR8RAM.pre_map.hdb and b/cpld/db/GR8RAM.pre_map.hdb differ diff --git a/cpld/db/GR8RAM.quiproj.3044.rdr.flock b/cpld/db/GR8RAM.quiproj.3044.rdr.flock deleted file mode 100755 index e69de29..0000000 diff --git a/cpld/db/GR8RAM.root_partition.map.reg_db.cdb b/cpld/db/GR8RAM.root_partition.map.reg_db.cdb index f54bb14..40014bc 100755 Binary files a/cpld/db/GR8RAM.root_partition.map.reg_db.cdb and b/cpld/db/GR8RAM.root_partition.map.reg_db.cdb differ diff --git a/cpld/db/GR8RAM.routing.rdb b/cpld/db/GR8RAM.routing.rdb index 42275c3..5c2267c 100755 Binary files a/cpld/db/GR8RAM.routing.rdb and b/cpld/db/GR8RAM.routing.rdb differ diff --git a/cpld/db/GR8RAM.rtlv.hdb b/cpld/db/GR8RAM.rtlv.hdb index 948b74a..1f4af35 100755 Binary files a/cpld/db/GR8RAM.rtlv.hdb and b/cpld/db/GR8RAM.rtlv.hdb differ diff --git a/cpld/db/GR8RAM.rtlv_sg.cdb b/cpld/db/GR8RAM.rtlv_sg.cdb index 331a4da..1eb59c7 100755 Binary files a/cpld/db/GR8RAM.rtlv_sg.cdb and b/cpld/db/GR8RAM.rtlv_sg.cdb differ diff --git a/cpld/db/GR8RAM.sgdiff.cdb b/cpld/db/GR8RAM.sgdiff.cdb index 00eb44a..affd34e 100755 Binary files a/cpld/db/GR8RAM.sgdiff.cdb and b/cpld/db/GR8RAM.sgdiff.cdb differ diff --git a/cpld/db/GR8RAM.sgdiff.hdb b/cpld/db/GR8RAM.sgdiff.hdb index f3fcdcc..a1588e2 100755 Binary files a/cpld/db/GR8RAM.sgdiff.hdb and b/cpld/db/GR8RAM.sgdiff.hdb differ diff --git a/cpld/db/GR8RAM.sta.qmsg b/cpld/db/GR8RAM.sta.qmsg index cfd60b5..040c775 100755 --- a/cpld/db/GR8RAM.sta.qmsg +++ b/cpld/db/GR8RAM.sta.qmsg @@ -1,23 +1,23 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618741641484 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618741641499 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 18 06:27:20 2021 " "Processing started: Sun Apr 18 06:27:20 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618741641499 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618741641499 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618741641499 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1618741641703 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1618741642546 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618741642749 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618741642749 ""} -{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1618741642937 ""} -{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1618741643562 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1618741643749 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1618741643749 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C25M C25M " "create_clock -period 1.000 -name C25M C25M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618741643749 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI0 PHI0 " "create_clock -period 1.000 -name PHI0 PHI0" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618741643749 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618741643749 ""} -{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1618741643781 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1618741643874 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -9.035 " "Worst-case setup slack is -9.035" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618741643890 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618741643890 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.035 -651.992 C25M " " -9.035 -651.992 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618741643890 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.356 0.000 PHI0 " " 0.356 0.000 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618741643890 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618741643890 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.263 " "Worst-case hold slack is -0.263" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618741643906 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618741643906 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.263 -0.263 PHI0 " " -0.263 -0.263 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618741643906 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.391 0.000 C25M " " 1.391 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618741643906 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618741643906 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -4.406 " "Worst-case recovery slack is -4.406" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618741643921 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618741643921 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.406 -132.180 C25M " " -4.406 -132.180 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618741643921 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618741643921 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "removal 4.852 " "Worst-case removal slack is 4.852" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618741643937 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618741643937 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.852 0.000 C25M " " 4.852 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618741643937 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618741643937 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.289 " "Worst-case minimum pulse width slack is -2.289" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618741643953 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618741643953 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 C25M " " -2.289 -2.289 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618741643953 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI0 " " -2.289 -2.289 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618741643953 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618741643953 ""} -{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1618741644156 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618741644312 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618741644312 ""} -{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "276 " "Peak virtual memory: 276 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618741644578 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 18 06:27:24 2021 " "Processing ended: Sun Apr 18 06:27:24 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618741644578 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618741644578 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618741644578 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618741644578 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618810041817 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618810041817 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Apr 19 01:27:20 2021 " "Processing started: Mon Apr 19 01:27:20 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618810041817 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618810041817 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618810041817 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1618810042020 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1618810042786 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618810042958 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618810042958 ""} +{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1618810043145 ""} +{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1618810043645 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1618810043802 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1618810043817 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C25M C25M " "create_clock -period 1.000 -name C25M C25M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618810043817 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI0 PHI0 " "create_clock -period 1.000 -name PHI0 PHI0" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618810043817 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618810043817 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1618810043833 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1618810043942 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -9.468 " "Worst-case setup slack is -9.468" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618810043958 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618810043958 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.468 -696.810 C25M " " -9.468 -696.810 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618810043958 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.212 0.000 PHI0 " " 0.212 0.000 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618810043958 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618810043958 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.265 " "Worst-case hold slack is -0.265" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618810043973 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618810043973 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.265 -0.265 PHI0 " " -0.265 -0.265 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618810043973 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.374 0.000 C25M " " 1.374 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618810043973 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618810043973 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -4.404 " "Worst-case recovery slack is -4.404" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618810043989 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618810043989 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.404 -127.716 C25M " " -4.404 -127.716 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618810043989 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618810043989 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "removal 4.850 " "Worst-case removal slack is 4.850" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618810044005 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618810044005 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.850 0.000 C25M " " 4.850 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618810044005 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618810044005 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.289 " "Worst-case minimum pulse width slack is -2.289" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618810044020 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618810044020 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 C25M " " -2.289 -2.289 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618810044020 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI0 " " -2.289 -2.289 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618810044020 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618810044020 ""} +{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1618810044317 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618810044442 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618810044442 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "283 " "Peak virtual memory: 283 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618810044786 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 19 01:27:24 2021 " "Processing ended: Mon Apr 19 01:27:24 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618810044786 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618810044786 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618810044786 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618810044786 ""} diff --git a/cpld/db/GR8RAM.sta.rdb b/cpld/db/GR8RAM.sta.rdb index e73b492..c8a53e9 100755 Binary files a/cpld/db/GR8RAM.sta.rdb and b/cpld/db/GR8RAM.sta.rdb differ diff --git a/cpld/db/GR8RAM.sta_cmp.5_slow.tdb b/cpld/db/GR8RAM.sta_cmp.5_slow.tdb index f3715cc..b4b7569 100755 Binary files a/cpld/db/GR8RAM.sta_cmp.5_slow.tdb and b/cpld/db/GR8RAM.sta_cmp.5_slow.tdb differ diff --git a/cpld/db/GR8RAM.tmw_info b/cpld/db/GR8RAM.tmw_info index fa9643e..05b4338 100755 --- a/cpld/db/GR8RAM.tmw_info +++ b/cpld/db/GR8RAM.tmw_info @@ -1,6 +1,6 @@ -start_full_compilation:s:00:00:32 -start_analysis_synthesis:s:00:00:07-start_full_compilation +start_full_compilation:s:00:00:28 +start_analysis_synthesis:s:00:00:08-start_full_compilation start_analysis_elaboration:s-start_full_compilation -start_fitter:s:00:00:12-start_full_compilation -start_assembler:s:00:00:06-start_full_compilation -start_timing_analyzer:s:00:00:07-start_full_compilation +start_fitter:s:00:00:10-start_full_compilation +start_assembler:s:00:00:04-start_full_compilation +start_timing_analyzer:s:00:00:06-start_full_compilation diff --git a/cpld/db/GR8RAM.vpr.ammdb b/cpld/db/GR8RAM.vpr.ammdb index ce5a0ae..b472823 100755 Binary files a/cpld/db/GR8RAM.vpr.ammdb and b/cpld/db/GR8RAM.vpr.ammdb differ diff --git a/cpld/db/logic_util_heursitic.dat b/cpld/db/logic_util_heursitic.dat index 5c5d8ec..04ce9a9 100755 Binary files a/cpld/db/logic_util_heursitic.dat and b/cpld/db/logic_util_heursitic.dat differ diff --git a/cpld/db/prev_cmp_GR8RAM.qmsg b/cpld/db/prev_cmp_GR8RAM.qmsg index 483f3d7..245b754 100755 --- a/cpld/db/prev_cmp_GR8RAM.qmsg +++ b/cpld/db/prev_cmp_GR8RAM.qmsg @@ -1,99 +1,96 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618741509217 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618741509217 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 18 06:25:08 2021 " "Processing started: Sun Apr 18 06:25:08 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618741509217 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618741509217 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618741509217 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1618741510935 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(93) " "Verilog HDL warning at GR8RAM.v(93): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 93 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618741511107 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(274) " "Verilog HDL warning at GR8RAM.v(274): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 274 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618741511107 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1618741511123 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1618741511123 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1618741511232 ""} -{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "SetRF GR8RAM.v(269) " "Verilog HDL or VHDL warning at GR8RAM.v(269): object \"SetRF\" assigned a value but never read" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 269 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1618741511248 "|GR8RAM"} -{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "SetLim1M GR8RAM.v(270) " "Verilog HDL or VHDL warning at GR8RAM.v(270): object \"SetLim1M\" assigned a value but never read" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 270 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1618741511248 "|GR8RAM"} -{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "SetLim8M GR8RAM.v(271) " "Verilog HDL or VHDL warning at GR8RAM.v(271): object \"SetLim8M\" assigned a value but never read" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 271 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1618741511248 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(34) " "Verilog HDL assignment warning at GR8RAM.v(34): truncated value with size 32 to match size of target (14)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 34 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618741511248 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(117) " "Verilog HDL assignment warning at GR8RAM.v(117): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 117 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618741511248 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(125) " "Verilog HDL assignment warning at GR8RAM.v(125): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 125 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618741511248 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(132) " "Verilog HDL assignment warning at GR8RAM.v(132): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 132 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618741511248 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(325) " "Verilog HDL assignment warning at GR8RAM.v(325): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 325 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618741511248 "|GR8RAM"} -{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 -1 1618741512795 ""} -{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 15 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618741513123 "|GR8RAM|RAdir"} { "Warning" "WMLS_MLS_STUCK_PIN" "nDMAout VCC " "Pin \"nDMAout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 20 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618741513123 "|GR8RAM|nDMAout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nNMIout VCC " "Pin \"nNMIout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 21 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618741513123 "|GR8RAM|nNMIout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nIRQout VCC " "Pin \"nIRQout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 24 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618741513123 "|GR8RAM|nIRQout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nRDYout VCC " "Pin \"nRDYout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 23 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618741513123 "|GR8RAM|nRDYout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nINHout VCC " "Pin \"nINHout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 22 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618741513123 "|GR8RAM|nINHout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RWout VCC " "Pin \"RWout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 25 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618741513123 "|GR8RAM|RWout"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1618741513123 ""} -{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1618741513842 ""} -{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SetFW\[0\] " "No output dependent on input pin \"SetFW\[0\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 267 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1618741513889 "|GR8RAM|SetFW[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SetFW\[1\] " "No output dependent on input pin \"SetFW\[1\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 267 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1618741513889 "|GR8RAM|SetFW[1]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1618741513889 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "309 " "Implemented 309 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "28 " "Implemented 28 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1618741513889 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1618741513889 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1618741513889 ""} { "Info" "ICUT_CUT_TM_LCELLS" "229 " "Implemented 229 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1618741513889 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1618741513889 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1618741514092 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 19 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 19 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "301 " "Peak virtual memory: 301 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618741514217 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 18 06:25:14 2021 " "Processing ended: Sun Apr 18 06:25:14 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618741514217 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618741514217 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618741514217 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618741514217 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618741517420 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 32-bit " "Running Quartus II 32-bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618741517435 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 18 06:25:15 2021 " "Processing started: Sun Apr 18 06:25:15 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618741517435 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1618741517435 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1618741517435 ""} -{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1618741517654 ""} -{ "Info" "0" "" "Project = GR8RAM" { } { } 0 0 "Project = GR8RAM" 0 0 "Fitter" 0 0 1618741517654 ""} -{ "Info" "0" "" "Revision = GR8RAM" { } { } 0 0 "Revision = GR8RAM" 0 0 "Fitter" 0 0 1618741517654 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1618741518217 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1618741518232 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618741518420 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618741518420 ""} -{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1618741518764 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1618741518795 ""} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618741519123 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618741519123 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618741519123 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618741519123 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618741519123 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1618741519123 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1618741519264 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1618741519264 ""} -{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1618741519279 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1618741519279 ""} -{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618741519279 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618741519279 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 C25M " " 1.000 C25M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618741519279 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI0 " " 1.000 PHI0" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618741519279 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1618741519279 ""} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618741519279 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618741519279 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618741519295 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618741519326 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI0 Global clock " "Automatically promoted some destinations of signal \"PHI0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~1 " "Destination \"comb~1\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618741519326 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI0r1 " "Destination \"PHI0r1\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 11 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618741519326 ""} } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618741519326 ""} -{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI0 " "Pin \"PHI0\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI0 } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "PHI0" } } } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 367 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1618741519326 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "nRESr Global clock " "Automatically promoted signal \"nRESr\" to use Global clock" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 29 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618741519326 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618741519342 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1618741519342 ""} -{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1618741519373 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1618741519435 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1618741519451 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1618741519451 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1618741519451 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618741519514 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1618741519748 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618741520139 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1618741520154 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1618741521451 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618741521451 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1618741521529 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "31 " "Router estimated average interconnect usage is 31% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "31 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 31% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 31% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 31% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1618741521982 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1618741521982 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618741522592 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.55 " "Total time spent on timing analysis during the Fitter is 0.55 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1618741522607 ""} -{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618741522607 ""} -{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1618741522639 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1618741522904 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "372 " "Peak virtual memory: 372 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618741523139 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 18 06:25:23 2021 " "Processing ended: Sun Apr 18 06:25:23 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618741523139 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618741523139 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618741523139 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1618741523139 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1618741526014 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618741526014 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 18 06:25:25 2021 " "Processing started: Sun Apr 18 06:25:25 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618741526014 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1618741526014 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1618741526014 ""} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1618741527170 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1618741527201 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "293 " "Peak virtual memory: 293 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618741527732 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 18 06:25:27 2021 " "Processing ended: Sun Apr 18 06:25:27 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618741527732 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618741527732 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618741527732 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1618741527732 ""} -{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1618741528467 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1618741530717 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618741530717 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 18 06:25:29 2021 " "Processing started: Sun Apr 18 06:25:29 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618741530717 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618741530717 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618741530732 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1618741530920 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1618741531904 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618741532138 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618741532138 ""} -{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1618741532342 ""} -{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1618741532920 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1618741533045 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1618741533045 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C25M C25M " "create_clock -period 1.000 -name C25M C25M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618741533045 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI0 PHI0 " "create_clock -period 1.000 -name PHI0 PHI0" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618741533045 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618741533045 ""} -{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1618741533076 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1618741533201 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -9.001 " "Worst-case setup slack is -9.001" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618741533217 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618741533217 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.001 -621.699 C25M " " -9.001 -621.699 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618741533217 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.279 0.000 PHI0 " " 0.279 0.000 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618741533217 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618741533217 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.567 " "Worst-case hold slack is -0.567" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618741533232 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618741533232 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.567 -0.567 PHI0 " " -0.567 -0.567 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618741533232 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.390 0.000 C25M " " 1.390 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618741533232 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618741533232 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -5.009 " "Worst-case recovery slack is -5.009" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618741533232 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618741533232 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.009 -150.270 C25M " " -5.009 -150.270 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618741533232 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618741533232 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "removal 5.455 " "Worst-case removal slack is 5.455" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618741533248 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618741533248 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 5.455 0.000 C25M " " 5.455 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618741533248 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618741533248 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.289 " "Worst-case minimum pulse width slack is -2.289" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618741533263 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618741533263 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 C25M " " -2.289 -2.289 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618741533263 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI0 " " -2.289 -2.289 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618741533263 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618741533263 ""} -{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1618741533607 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618741533717 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618741533717 ""} -{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "283 " "Peak virtual memory: 283 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618741533967 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 18 06:25:33 2021 " "Processing ended: Sun Apr 18 06:25:33 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618741533967 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618741533967 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618741533967 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618741533967 ""} -{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 24 s " "Quartus II Full Compilation was successful. 0 errors, 24 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618741535451 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618809604705 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618809604705 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Apr 19 01:20:04 2021 " "Processing started: Mon Apr 19 01:20:04 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618809604705 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618809604705 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618809604705 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1618809606627 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(79) " "Verilog HDL warning at GR8RAM.v(79): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 79 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618809606924 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(259) " "Verilog HDL warning at GR8RAM.v(259): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 259 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618809606924 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1618809606939 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1618809606939 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1618809607064 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(20) " "Verilog HDL assignment warning at GR8RAM.v(20): truncated value with size 32 to match size of target (14)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 20 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618809607064 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(103) " "Verilog HDL assignment warning at GR8RAM.v(103): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 103 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618809607064 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(111) " "Verilog HDL assignment warning at GR8RAM.v(111): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 111 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618809607064 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(118) " "Verilog HDL assignment warning at GR8RAM.v(118): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 118 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618809607064 "|GR8RAM"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(309) " "Verilog HDL assignment warning at GR8RAM.v(309): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 309 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618809607064 "|GR8RAM"} +{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 -1 1618809608674 ""} +{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "nNMIout VCC " "Pin \"nNMIout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 536 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618809609002 "|GR8RAM|nNMIout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nIRQout VCC " "Pin \"nIRQout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 539 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618809609002 "|GR8RAM|nIRQout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nRDYout VCC " "Pin \"nRDYout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 538 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618809609002 "|GR8RAM|nRDYout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nINHout VCC " "Pin \"nINHout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 537 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618809609002 "|GR8RAM|nINHout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RWout VCC " "Pin \"RWout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 540 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618809609002 "|GR8RAM|RWout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nDMAout VCC " "Pin \"nDMAout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 535 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618809609002 "|GR8RAM|nDMAout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 534 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618809609002 "|GR8RAM|RAdir"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1618809609002 ""} +{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1618809610173 ""} +{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SetFW\[0\] " "No output dependent on input pin \"SetFW\[0\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 253 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1618809610220 "|GR8RAM|SetFW[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SetFW\[1\] " "No output dependent on input pin \"SetFW\[1\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 253 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1618809610220 "|GR8RAM|SetFW[1]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1618809610220 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "309 " "Implemented 309 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "28 " "Implemented 28 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1618809610236 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1618809610236 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1618809610236 ""} { "Info" "ICUT_CUT_TM_LCELLS" "229 " "Implemented 229 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1618809610236 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1618809610236 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1618809610455 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 16 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 16 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "301 " "Peak virtual memory: 301 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618809610595 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 19 01:20:10 2021 " "Processing ended: Mon Apr 19 01:20:10 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618809610595 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618809610595 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618809610595 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618809610595 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618809613704 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 32-bit " "Running Quartus II 32-bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618809613720 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Apr 19 01:20:12 2021 " "Processing started: Mon Apr 19 01:20:12 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618809613720 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1618809613720 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1618809613720 ""} +{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1618809613876 ""} +{ "Info" "0" "" "Project = GR8RAM" { } { } 0 0 "Project = GR8RAM" 0 0 "Fitter" 0 0 1618809613876 ""} +{ "Info" "0" "" "Revision = GR8RAM" { } { } 0 0 "Revision = GR8RAM" 0 0 "Fitter" 0 0 1618809613876 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1618809614454 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1618809614486 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618809614657 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618809614657 ""} +{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1618809614923 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1618809614954 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618809615251 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618809615251 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618809615251 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618809615251 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618809615251 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1618809615251 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1618809615376 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1618809615392 ""} +{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1618809615392 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1618809615392 ""} +{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618809615407 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618809615407 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 C25M " " 1.000 C25M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618809615407 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI0 " " 1.000 PHI0" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618809615407 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1618809615407 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618809615407 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618809615407 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618809615407 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618809615439 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI0 Global clock " "Automatically promoted some destinations of signal \"PHI0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~1 " "Destination \"comb~1\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618809615439 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI0r1 " "Destination \"PHI0r1\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618809615439 ""} } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618809615439 ""} +{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI0 " "Pin \"PHI0\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI0 } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "PHI0" } } } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 372 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1618809615439 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "nRESr Global clock " "Automatically promoted signal \"nRESr\" to use Global clock" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 15 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618809615439 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618809615439 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1618809615439 ""} +{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1618809615470 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1618809615517 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1618809615517 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1618809615517 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1618809615517 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618809615548 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1618809615970 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618809616298 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1618809616313 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1618809617485 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618809617485 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1618809617548 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "35 " "Router estimated average interconnect usage is 35% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "35 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 35% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 35% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 35% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1618809618266 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1618809618266 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618809618923 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.58 " "Total time spent on timing analysis during the Fitter is 0.58 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1618809618938 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618809618954 ""} +{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1618809618985 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1618809619391 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "378 " "Peak virtual memory: 378 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618809619579 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 19 01:20:19 2021 " "Processing ended: Mon Apr 19 01:20:19 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618809619579 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618809619579 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618809619579 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1618809619579 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1618809622188 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618809622188 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Apr 19 01:20:21 2021 " "Processing started: Mon Apr 19 01:20:21 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618809622188 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1618809622188 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1618809622188 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1618809623282 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1618809623313 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "293 " "Peak virtual memory: 293 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618809623813 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 19 01:20:23 2021 " "Processing ended: Mon Apr 19 01:20:23 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618809623813 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618809623813 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618809623813 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1618809623813 ""} +{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1618809624578 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1618809628937 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618809629016 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Apr 19 01:20:26 2021 " "Processing started: Mon Apr 19 01:20:26 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618809629016 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618809629016 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618809629141 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1618809630109 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1618809632281 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618809632593 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618809632593 ""} +{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1618809632843 ""} +{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1618809633593 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1618809633812 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1618809633828 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C25M C25M " "create_clock -period 1.000 -name C25M C25M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618809633828 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI0 PHI0 " "create_clock -period 1.000 -name PHI0 PHI0" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618809633828 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618809633828 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1618809633843 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1618809634000 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -9.468 " "Worst-case setup slack is -9.468" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618809634046 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618809634046 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.468 -696.810 C25M " " -9.468 -696.810 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618809634046 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.212 0.000 PHI0 " " 0.212 0.000 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618809634046 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618809634046 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.265 " "Worst-case hold slack is -0.265" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618809634062 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618809634062 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.265 -0.265 PHI0 " " -0.265 -0.265 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618809634062 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.374 0.000 C25M " " 1.374 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618809634062 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618809634062 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -4.404 " "Worst-case recovery slack is -4.404" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618809634078 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618809634078 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.404 -127.716 C25M " " -4.404 -127.716 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618809634078 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618809634078 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "removal 4.850 " "Worst-case removal slack is 4.850" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618809634093 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618809634093 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.850 0.000 C25M " " 4.850 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618809634093 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618809634093 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.289 " "Worst-case minimum pulse width slack is -2.289" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618809634140 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618809634140 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 C25M " " -2.289 -2.289 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618809634140 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI0 " " -2.289 -2.289 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618809634140 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618809634140 ""} +{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1618809634921 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618809635265 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618809635265 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "283 " "Peak virtual memory: 283 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618809635624 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 19 01:20:35 2021 " "Processing ended: Mon Apr 19 01:20:35 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618809635624 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618809635624 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618809635624 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618809635624 ""} +{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 21 s " "Quartus II Full Compilation was successful. 0 errors, 21 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618809636734 ""} diff --git a/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt b/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt index 67e161c..741c2ff 100755 Binary files a/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt and b/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt differ diff --git a/cpld/output_files/GR8RAM.asm.rpt b/cpld/output_files/GR8RAM.asm.rpt index a62ea71..9f44fdf 100755 --- a/cpld/output_files/GR8RAM.asm.rpt +++ b/cpld/output_files/GR8RAM.asm.rpt @@ -1,5 +1,5 @@ Assembler report for GR8RAM -Sun Apr 18 06:27:18 2021 +Mon Apr 19 01:27:18 2021 Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition @@ -37,7 +37,7 @@ applicable agreement for further details. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Sun Apr 18 06:27:18 2021 ; +; Assembler Status ; Successful - Mon Apr 19 01:27:18 2021 ; ; Revision Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ; ; Family ; MAX II ; @@ -90,8 +90,8 @@ applicable agreement for further details. ; Option ; Setting ; +----------------+-------------------------------------------------------+ ; Device ; EPM240T100C5 ; -; JTAG usercode ; 0x00164904 ; -; Checksum ; 0x00164E04 ; +; JTAG usercode ; 0x00163FE1 ; +; Checksum ; 0x001642D1 ; +----------------+-------------------------------------------------------+ @@ -101,13 +101,13 @@ applicable agreement for further details. Info: ******************************************************************* Info: Running Quartus II 32-bit Assembler Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - Info: Processing started: Sun Apr 18 06:27:16 2021 + Info: Processing started: Mon Apr 19 01:27:16 2021 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM Info (115031): Writing out detailed assembly data for power analysis Info (115030): Assembler is generating device programming files Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings Info: Peak virtual memory: 293 megabytes - Info: Processing ended: Sun Apr 18 06:27:18 2021 + Info: Processing ended: Mon Apr 19 01:27:18 2021 Info: Elapsed time: 00:00:02 Info: Total CPU time (on all processors): 00:00:02 diff --git a/cpld/output_files/GR8RAM.done b/cpld/output_files/GR8RAM.done index 3476d7f..cf64c93 100755 --- a/cpld/output_files/GR8RAM.done +++ b/cpld/output_files/GR8RAM.done @@ -1 +1 @@ -Sun Apr 18 06:27:25 2021 +Mon Apr 19 01:27:26 2021 diff --git a/cpld/output_files/GR8RAM.fit.rpt b/cpld/output_files/GR8RAM.fit.rpt index f0cf313..1338016 100755 --- a/cpld/output_files/GR8RAM.fit.rpt +++ b/cpld/output_files/GR8RAM.fit.rpt @@ -1,5 +1,5 @@ Fitter report for GR8RAM -Sun Apr 18 06:27:13 2021 +Mon Apr 19 01:27:14 2021 Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition @@ -59,7 +59,7 @@ applicable agreement for further details. +-----------------------------------------------------------------------------+ ; Fitter Summary ; +---------------------------+-------------------------------------------------+ -; Fitter Status ; Successful - Sun Apr 18 06:27:13 2021 ; +; Fitter Status ; Successful - Mon Apr 19 01:27:14 2021 ; ; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; ; Revision Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ; @@ -130,12 +130,11 @@ applicable agreement for further details. ; Number detected on machine ; 2 ; ; Maximum allowed ; 2 ; ; ; ; -; Average used ; 1.20 ; +; Average used ; 2.00 ; ; Maximum used ; 2 ; ; ; ; ; Usage by Processor ; % Time Used ; -; Processor 1 ; 100.0% ; -; Processor 2 ; 20.0% ; +; Processors 1-2 ; 100.0% ; +----------------------------+-------------+ @@ -156,11 +155,11 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin. ; -- Combinational with a register ; 102 ; ; ; ; ; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 122 ; -; -- 3 input functions ; 37 ; -; -- 2 input functions ; 62 ; +; -- 4 input functions ; 123 ; +; -- 3 input functions ; 27 ; +; -- 2 input functions ; 69 ; ; -- 1 input functions ; 0 ; -; -- 0 input functions ; 0 ; +; -- 0 input functions ; 2 ; ; ; ; ; Logic elements by mode ; ; ; -- normal mode ; 189 ; @@ -181,12 +180,12 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin. ; UFM blocks ; 0 / 1 ( 0 % ) ; ; Global clocks ; 3 / 4 ( 75 % ) ; ; JTAGs ; 0 / 1 ( 0 % ) ; -; Average interconnect usage (total/H/V) ; 41% / 46% / 36% ; -; Peak interconnect usage (total/H/V) ; 41% / 46% / 36% ; +; Average interconnect usage (total/H/V) ; 45% / 51% / 38% ; +; Peak interconnect usage (total/H/V) ; 45% / 51% / 38% ; ; Maximum fan-out ; 100 ; -; Highest non-global fan-out ; 48 ; -; Total fan-out ; 1035 ; -; Average fan-out ; 3.43 ; +; Highest non-global fan-out ; 47 ; +; Total fan-out ; 1023 ; +; Average fan-out ; 3.39 ; +---------------------------------------------+--------------------+ @@ -219,7 +218,7 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin. ; SetFW[0] ; 96 ; 2 ; 3 ; 5 ; 2 ; 0 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; ; SetFW[1] ; 95 ; 2 ; 3 ; 5 ; 1 ; 0 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; ; nDEVSEL ; 40 ; 1 ; 5 ; 0 ; 2 ; 4 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; -; nIOSEL ; 39 ; 1 ; 5 ; 0 ; 3 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; +; nIOSEL ; 39 ; 1 ; 5 ; 0 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; ; nIOSTRB ; 42 ; 1 ; 5 ; 0 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; ; nRES ; 44 ; 1 ; 6 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; ; nWE ; 43 ; 1 ; 6 ; 0 ; 3 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; @@ -261,7 +260,7 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin. ; nINHout ; 27 ; 1 ; 2 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; ; nIRQout ; 29 ; 1 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; ; nNMIout ; 26 ; 1 ; 2 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; -; nRAS ; 62 ; 2 ; 8 ; 2 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; - ; - ; +; nRAS ; 62 ; 2 ; 8 ; 2 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; ; nRCS ; 67 ; 2 ; 8 ; 3 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; ; nRDYout ; 28 ; 1 ; 2 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; ; nRESout ; 30 ; 1 ; 3 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; @@ -283,14 +282,14 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin. ; RD[5] ; 91 ; 2 ; 4 ; 5 ; 2 ; 4 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; comb~1 ; - ; ; RD[6] ; 92 ; 2 ; 3 ; 5 ; 0 ; 4 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; comb~1 ; - ; ; RD[7] ; 99 ; 2 ; 2 ; 5 ; 1 ; 6 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; comb~1 ; - ; -; SD[0] ; 50 ; 1 ; 7 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; SDOE ; - ; +; SD[0] ; 50 ; 1 ; 7 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; ; SD[1] ; 47 ; 1 ; 6 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; ; SD[2] ; 56 ; 2 ; 8 ; 1 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; -; SD[3] ; 55 ; 2 ; 8 ; 1 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; SDOE ; - ; +; SD[3] ; 55 ; 2 ; 8 ; 1 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; ; SD[4] ; 51 ; 1 ; 7 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; -; SD[5] ; 52 ; 2 ; 8 ; 1 ; 4 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; SDOE ; - ; +; SD[5] ; 52 ; 2 ; 8 ; 1 ; 4 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; ; SD[6] ; 53 ; 2 ; 8 ; 1 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; -; SD[7] ; 54 ; 2 ; 8 ; 1 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; +; SD[7] ; 54 ; 2 ; 8 ; 1 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; SDOE ; - ; +-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ @@ -465,23 +464,23 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; RA[8] ; Input ; (1) ; ; RA[9] ; Input ; (1) ; ; RA[10] ; Input ; (1) ; +; nRES ; Input ; (1) ; ; RA[11] ; Input ; (1) ; ; RA[14] ; Input ; (1) ; ; RA[15] ; Input ; (1) ; ; RA[12] ; Input ; (1) ; ; RA[13] ; Input ; (1) ; -; nRES ; Input ; (1) ; ; MISO ; Input ; (1) ; ; nRESout ; Output ; -- ; -; RAdir ; Output ; -- ; ; INTout ; Output ; -- ; ; DMAout ; Output ; -- ; -; nDMAout ; Output ; -- ; ; nNMIout ; Output ; -- ; ; nIRQout ; Output ; -- ; ; nRDYout ; Output ; -- ; ; nINHout ; Output ; -- ; ; RWout ; Output ; -- ; +; nDMAout ; Output ; -- ; +; RAdir ; Output ; -- ; ; RDdir ; Output ; -- ; ; SBA[0] ; Output ; -- ; ; SBA[1] ; Output ; -- ; @@ -533,19 +532,21 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; +------------+-------------+---------+---------------------------------------+--------+----------------------+------------------+ ; C25M ; PIN_64 ; 100 ; Clock ; yes ; Global Clock ; GCLK3 ; -; Decoder1~0 ; LC_X4_Y1_N2 ; 8 ; Clock enable ; no ; -- ; -- ; -; Equal0~0 ; LC_X5_Y2_N8 ; 19 ; Clock enable ; no ; -- ; -- ; -; FCKOE ; LC_X2_Y4_N8 ; 2 ; Output enable ; no ; -- ; -- ; -; MOSIOE ; LC_X2_Y4_N9 ; 1 ; Output enable ; no ; -- ; -- ; +; Decoder1~0 ; LC_X6_Y1_N8 ; 8 ; Clock enable ; no ; -- ; -- ; +; Equal0~0 ; LC_X5_Y2_N9 ; 19 ; Clock enable ; no ; -- ; -- ; +; FCKOE ; LC_X3_Y4_N7 ; 2 ; Output enable ; no ; -- ; -- ; +; IOROMRES ; LC_X2_Y3_N6 ; 1 ; Async. clear ; no ; -- ; -- ; +; MOSIOE ; LC_X3_Y4_N6 ; 1 ; Output enable ; no ; -- ; -- ; ; PHI0 ; PIN_41 ; 5 ; Clock ; yes ; Global Clock ; GCLK1 ; -; PS[0] ; LC_X6_Y2_N8 ; 47 ; Clock enable, Sync. clear, Sync. load ; no ; -- ; -- ; -; PS[2] ; LC_X6_Y2_N6 ; 27 ; Sync. clear, Sync. load ; no ; -- ; -- ; -; SDOE ; LC_X5_Y4_N6 ; 8 ; Output enable ; no ; -- ; -- ; -; always6~2 ; LC_X5_Y4_N7 ; 8 ; Sync. load ; no ; -- ; -- ; -; always6~3 ; LC_X4_Y4_N9 ; 9 ; Sync. load ; no ; -- ; -- ; -; always6~4 ; LC_X5_Y4_N9 ; 9 ; Sync. load ; no ; -- ; -- ; -; comb~1 ; LC_X5_Y2_N3 ; 9 ; Output enable ; no ; -- ; -- ; -; nRESr ; LC_X2_Y3_N3 ; 30 ; Async. clear ; yes ; Global Clock ; GCLK2 ; +; PS[0] ; LC_X4_Y3_N6 ; 46 ; Clock enable, Sync. clear, Sync. load ; no ; -- ; -- ; +; PS[2] ; LC_X3_Y3_N5 ; 29 ; Sync. clear, Sync. load ; no ; -- ; -- ; +; SDOE ; LC_X5_Y1_N6 ; 8 ; Output enable ; no ; -- ; -- ; +; always5~1 ; LC_X2_Y3_N9 ; 2 ; Clock enable ; no ; -- ; -- ; +; always7~2 ; LC_X2_Y3_N2 ; 8 ; Sync. load ; no ; -- ; -- ; +; always7~3 ; LC_X2_Y3_N5 ; 9 ; Sync. load ; no ; -- ; -- ; +; always7~4 ; LC_X2_Y3_N1 ; 9 ; Sync. load ; no ; -- ; -- ; +; comb~1 ; LC_X4_Y1_N8 ; 9 ; Output enable ; no ; -- ; -- ; +; nRESr ; LC_X2_Y3_N9 ; 29 ; Async. clear ; yes ; Global Clock ; GCLK2 ; +------------+-------------+---------+---------------------------------------+--------+----------------------+------------------+ @@ -556,7 +557,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +-------+-------------+---------+----------------------+------------------+ ; C25M ; PIN_64 ; 100 ; Global Clock ; GCLK3 ; ; PHI0 ; PIN_41 ; 5 ; Global Clock ; GCLK1 ; -; nRESr ; LC_X2_Y3_N3 ; 30 ; Global Clock ; GCLK2 ; +; nRESr ; LC_X2_Y3_N9 ; 29 ; Global Clock ; GCLK2 ; +-------+-------------+---------+----------------------+------------------+ @@ -565,40 +566,39 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +---------------------+-----------+ ; Name ; Fan-Out ; +---------------------+-----------+ -; PS[0] ; 48 ; -; PS[1] ; 32 ; -; PS[3] ; 29 ; -; PS[2] ; 27 ; -; IS.state_bit_0 ; 21 ; +; PS[0] ; 47 ; +; PS[1] ; 33 ; +; PS[2] ; 29 ; +; PS[3] ; 28 ; +; IS.state_bit_0 ; 20 ; ; Equal0~0 ; 19 ; -; RAMSpecSELr ; 19 ; -; IS.state_bit_1 ; 18 ; -; IS.110~0 ; 16 ; +; IS.110~0 ; 17 ; +; IS.state_bit_1 ; 17 ; ; LS[0] ; 13 ; ; RDD[1]~18 ; 12 ; ; AddrMSpecSEL ; 12 ; -; always6~4 ; 9 ; -; always6~3 ; 9 ; +; RAMSpecSELr ; 11 ; +; always7~4 ; 9 ; +; always7~3 ; 9 ; ; comb~1 ; 9 ; ; RA[0] ; 8 ; ; Decoder1~0 ; 8 ; ; SDOE ; 8 ; -; always6~2 ; 8 ; +; always7~2 ; 8 ; ; IS.state_bit_2 ; 8 ; -; SA[2]~8 ; 8 ; +; SA[7]~8 ; 8 ; ; LS[2] ; 8 ; ; RA[1] ; 7 ; ; RD[7]~7 ; 6 ; -; SA[8]~15 ; 6 ; -; SA[8]~10 ; 6 ; -; SA[8]~9 ; 6 ; +; SA[7]~16 ; 6 ; +; Equal18~0 ; 6 ; +; SA[7]~10 ; 6 ; +; SA[7]~9 ; 6 ; ; LS[1] ; 6 ; -; Equal16~0 ; 6 ; ; RD[0]~0 ; 5 ; ; RA[3] ; 5 ; ; RA[2] ; 5 ; ; Addr[0] ; 5 ; -; Equal17~0 ; 5 ; ; LS[6]~17 ; 5 ; ; LS[1]~3 ; 5 ; ; Mux14~6 ; 5 ; @@ -609,9 +609,9 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; RD[2]~2 ; 4 ; ; RD[1]~1 ; 4 ; ; nDEVSEL ; 4 ; -; always6~1 ; 4 ; -; always6~0 ; 4 ; -; RAMSpecSEL~0 ; 4 ; +; always7~6 ; 4 ; +; REGSpecSEL~1 ; 4 ; +; RAMRegSpecSEL~0 ; 4 ; ; LS[13] ; 4 ; ; Equal1~2 ; 4 ; ; nRCS~1 ; 4 ; @@ -634,14 +634,14 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; Addr[1] ; 4 ; ; Addr[10] ; 4 ; ; Addr[23] ; 4 ; +; always5~0 ; 4 ; ; RA[11] ; 3 ; ; RA[10] ; 3 ; ; RA[9] ; 3 ; ; RA[8] ; 3 ; ; RA[7] ; 3 ; ; nWE ; 3 ; -; nIOSEL ; 3 ; -; SA[2]~14 ; 3 ; +; SA[2]~15 ; 3 ; ; WRD[5] ; 3 ; ; WRD[4] ; 3 ; ; WRD[3] ; 3 ; @@ -651,6 +651,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; Equal2~0 ; 3 ; ; Equal3~0 ; 3 ; ; Equal1~3 ; 3 ; +; Equal18~1 ; 3 ; ; IS.111~0 ; 3 ; ; Addr[22] ; 3 ; ; Addr[21] ; 3 ; @@ -672,37 +673,36 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; SA[2]~5 ; 3 ; ; LS[10] ; 3 ; ; SA[2]~4 ; 3 ; -; IOROMEN ; 3 ; ; RA[6] ; 2 ; ; RA[5] ; 2 ; ; RA[4] ; 2 ; +; nIOSEL ; 2 ; ; nIOSTRB ; 2 ; ; WRD[7] ; 2 ; ; WRD[6] ; 2 ; ; AddrIncL ; 2 ; ; AddrIncM ; 2 ; -; REGEN ; 2 ; ; Equal7~0 ; 2 ; ; REGSpecSEL~0 ; 2 ; ; IS.state_bit_1~3 ; 2 ; ; IS.state_bit_1~0 ; 2 ; ; Equal3~1 ; 2 ; ; FCKOE ; 2 ; -; PHI0r1 ; 2 ; -; Selector1~1 ; 2 ; +; PS~0 ; 2 ; ; DQMH~0 ; 2 ; ; Mux12~2 ; 2 ; ; nRCS~3 ; 2 ; ; ROMSpecRDr ; 2 ; ; nRCS~2 ; 2 ; ; nWEr ; 2 ; +; SA[2]~12 ; 2 ; ; Bank ; 2 ; ; LS[11]~5 ; 2 ; ; SA[2]~6 ; 2 ; ; Mux14~4 ; 2 ; -; always5~3 ; 2 ; -; always5~0 ; 2 ; -; PHI0r2 ; 2 ; +; always5~1 ; 2 ; +; comb~2 ; 2 ; +; IOROMEN ; 2 ; ; nRESout~reg0 ; 2 ; ; MOSI~0 ; 1 ; ; SD[7]~7 ; 1 ; @@ -714,17 +714,16 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; SD[1]~1 ; 1 ; ; SD[0]~0 ; 1 ; ; MISO ; 1 ; -; nRES ; 1 ; ; RA[13] ; 1 ; ; RA[12] ; 1 ; ; RA[15] ; 1 ; ; RA[14] ; 1 ; +; nRES ; 1 ; ; DMAin ; 1 ; ; INTin ; 1 ; ; Mux14~7 ; 1 ; ; Mux2~1 ; 1 ; ; Mux2~0 ; 1 ; -; Decoder0~0 ; 1 ; ; RDD~16 ; 1 ; ; RDD~14 ; 1 ; ; RDD~12 ; 1 ; @@ -755,6 +754,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; IS.state_bit_2~0 ; 1 ; ; Equal1~4 ; 1 ; ; AddrIncH ; 1 ; +; RAMRegSpecSEL ; 1 ; +; REGEN ; 1 ; ; IS.state_bit_1~2 ; 1 ; ; IS.state_bit_1~1 ; 1 ; ; IS.state_bit_0~5 ; 1 ; @@ -767,7 +768,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; Mux11~4 ; 1 ; ; Mux11~3 ; 1 ; ; Mux11~2 ; 1 ; -; PS~0 ; 1 ; +; PHI0r1 ; 1 ; ; Mux11~1 ; 1 ; ; Mux11~0 ; 1 ; ; Selector2~0 ; 1 ; @@ -784,7 +785,6 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; Addr[22]~45 ; 1 ; ; Addr[21]~43COUT1_76 ; 1 ; ; Addr[21]~43 ; 1 ; -; Mux15~1 ; 1 ; ; Mux15~0 ; 1 ; ; Addr[19]~39COUT1_74 ; 1 ; ; Addr[19]~39 ; 1 ; @@ -866,10 +866,11 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; Addr[10]~3COUT1_84 ; 1 ; ; Addr[10]~3 ; 1 ; ; Mux13~0 ; 1 ; -; nRESr0 ; 1 ; ; Mux14~5 ; 1 ; -; always5~2 ; 1 ; -; always5~1 ; 1 ; +; nRESr0 ; 1 ; +; IOROMRES ; 1 ; +; comb~4 ; 1 ; +; comb~3 ; 1 ; ; RCKE~reg0 ; 1 ; ; DQMH~reg0 ; 1 ; ; DQML~reg0 ; 1 ; @@ -892,6 +893,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; SA[0]~reg0 ; 1 ; ; SBA[1]~reg0 ; 1 ; ; SBA[0]~reg0 ; 1 ; +; PHI0r2 ; 1 ; ; comb~0 ; 1 ; +---------------------+-----------+ @@ -901,13 +903,13 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +-----------------------------+--------------------+ ; Other Routing Resource Type ; Usage ; +-----------------------------+--------------------+ -; C4s ; 224 / 784 ( 29 % ) ; -; Direct links ; 68 / 888 ( 8 % ) ; +; C4s ; 248 / 784 ( 32 % ) ; +; Direct links ; 55 / 888 ( 6 % ) ; ; Global clocks ; 3 / 4 ( 75 % ) ; ; LAB clocks ; 12 / 32 ( 38 % ) ; -; LUT chains ; 35 / 216 ( 16 % ) ; -; Local interconnects ; 421 / 888 ( 47 % ) ; -; R4s ; 266 / 704 ( 38 % ) ; +; LUT chains ; 27 / 216 ( 13 % ) ; +; Local interconnects ; 429 / 888 ( 48 % ) ; +; R4s ; 300 / 704 ( 43 % ) ; +-----------------------------+--------------------+ @@ -921,32 +923,32 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; 3 ; 0 ; ; 4 ; 1 ; ; 5 ; 0 ; -; 6 ; 1 ; +; 6 ; 2 ; ; 7 ; 0 ; -; 8 ; 3 ; +; 8 ; 1 ; ; 9 ; 2 ; -; 10 ; 17 ; +; 10 ; 18 ; +--------------------------------------------+------------------------------+ +-------------------------------------------------------------------+ ; LAB-wide Signals ; +------------------------------------+------------------------------+ -; LAB-wide Signals (Average = 1.88) ; Number of LABs (Total = 24) ; +; LAB-wide Signals (Average = 1.96) ; Number of LABs (Total = 24) ; +------------------------------------+------------------------------+ ; 1 Async. clear ; 7 ; -; 1 Clock ; 20 ; -; 1 Clock enable ; 5 ; +; 1 Clock ; 22 ; +; 1 Clock enable ; 7 ; ; 1 Sync. clear ; 5 ; -; 1 Sync. load ; 5 ; -; 2 Clocks ; 3 ; +; 1 Sync. load ; 4 ; +; 2 Clocks ; 2 ; +------------------------------------+------------------------------+ +----------------------------------------------------------------------------+ ; LAB Signals Sourced ; +---------------------------------------------+------------------------------+ -; Number of Signals Sourced (Average = 9.50) ; Number of LABs (Total = 24) ; +; Number of Signals Sourced (Average = 9.54) ; Number of LABs (Total = 24) ; +---------------------------------------------+------------------------------+ ; 0 ; 0 ; ; 1 ; 0 ; @@ -954,62 +956,64 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; 3 ; 0 ; ; 4 ; 1 ; ; 5 ; 0 ; -; 6 ; 1 ; +; 6 ; 2 ; ; 7 ; 0 ; -; 8 ; 3 ; +; 8 ; 1 ; ; 9 ; 2 ; -; 10 ; 13 ; +; 10 ; 14 ; ; 11 ; 2 ; -; 12 ; 2 ; +; 12 ; 1 ; +; 13 ; 1 ; +---------------------------------------------+------------------------------+ +--------------------------------------------------------------------------------+ ; LAB Signals Sourced Out ; +-------------------------------------------------+------------------------------+ -; Number of Signals Sourced Out (Average = 6.63) ; Number of LABs (Total = 24) ; +; Number of Signals Sourced Out (Average = 6.79) ; Number of LABs (Total = 24) ; +-------------------------------------------------+------------------------------+ ; 0 ; 0 ; ; 1 ; 0 ; -; 2 ; 3 ; -; 3 ; 2 ; -; 4 ; 1 ; -; 5 ; 2 ; -; 6 ; 3 ; -; 7 ; 2 ; -; 8 ; 3 ; +; 2 ; 1 ; +; 3 ; 1 ; +; 4 ; 4 ; +; 5 ; 3 ; +; 6 ; 2 ; +; 7 ; 3 ; +; 8 ; 2 ; ; 9 ; 4 ; ; 10 ; 3 ; -; 11 ; 1 ; +; 11 ; 0 ; +; 12 ; 1 ; +-------------------------------------------------+------------------------------+ +-----------------------------------------------------------------------------+ ; LAB Distinct Inputs ; +----------------------------------------------+------------------------------+ -; Number of Distinct Inputs (Average = 15.17) ; Number of LABs (Total = 24) ; +; Number of Distinct Inputs (Average = 15.38) ; Number of LABs (Total = 24) ; +----------------------------------------------+------------------------------+ ; 0 ; 0 ; ; 1 ; 0 ; ; 2 ; 0 ; -; 3 ; 1 ; -; 4 ; 0 ; +; 3 ; 0 ; +; 4 ; 1 ; ; 5 ; 0 ; ; 6 ; 0 ; ; 7 ; 0 ; ; 8 ; 2 ; ; 9 ; 0 ; -; 10 ; 1 ; -; 11 ; 0 ; +; 10 ; 0 ; +; 11 ; 2 ; ; 12 ; 3 ; -; 13 ; 4 ; -; 14 ; 1 ; -; 15 ; 0 ; -; 16 ; 1 ; -; 17 ; 1 ; -; 18 ; 1 ; -; 19 ; 3 ; -; 20 ; 2 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 2 ; +; 16 ; 3 ; +; 17 ; 2 ; +; 18 ; 2 ; +; 19 ; 2 ; +; 20 ; 1 ; ; 21 ; 3 ; ; 22 ; 1 ; +----------------------------------------------+------------------------------+ @@ -1044,7 +1048,7 @@ This will disable optimization of problematic paths and expose them for further +-----------------+----------------------+-------------------+ ; Source Register ; Destination Register ; Delay Added in ns ; +-----------------+----------------------+-------------------+ -; PHI0 ; PHI0r1 ; 0.547 ; +; PHI0 ; PHI0r1 ; 0.507 ; +-----------------+----------------------+-------------------+ Note: This table only shows the top 1 path(s) that have the largest delay added for hold. @@ -1085,25 +1089,25 @@ Info (176234): Starting register packing Info (186468): Started processing fast register assignments Info (186469): Finished processing fast register assignments Info (176235): Finished register packing -Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00 +Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01 Info (170189): Fitter placement preparation operations beginning Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 Info (170191): Fitter placement operations beginning Info (170137): Fitter placement was successful -Info (170192): Fitter placement operations ending: elapsed time is 00:00:02 +Info (170192): Fitter placement operations ending: elapsed time is 00:00:01 Info (170193): Fitter routing operations beginning -Info (170195): Router estimated average interconnect usage is 33% of the available device resources - Info (170196): Router estimated peak interconnect usage is 33% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5 +Info (170195): Router estimated average interconnect usage is 35% of the available device resources + Info (170196): Router estimated peak interconnect usage is 35% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5 Info (170194): Fitter routing operations ending: elapsed time is 00:00:01 -Info (11888): Total time spent on timing analysis during the Fitter is 0.75 seconds. +Info (11888): Total time spent on timing analysis during the Fitter is 0.53 seconds. Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00 Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'. Info (144001): Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg Info: Quartus II 32-bit Fitter was successful. 0 errors, 3 warnings - Info: Peak virtual memory: 382 megabytes - Info: Processing ended: Sun Apr 18 06:27:14 2021 + Info: Peak virtual memory: 372 megabytes + Info: Processing ended: Mon Apr 19 01:27:14 2021 Info: Elapsed time: 00:00:09 - Info: Total CPU time (on all processors): 00:00:08 + Info: Total CPU time (on all processors): 00:00:09 +----------------------------+ diff --git a/cpld/output_files/GR8RAM.fit.summary b/cpld/output_files/GR8RAM.fit.summary index da15082..75b2259 100755 --- a/cpld/output_files/GR8RAM.fit.summary +++ b/cpld/output_files/GR8RAM.fit.summary @@ -1,4 +1,4 @@ -Fitter Status : Successful - Sun Apr 18 06:27:13 2021 +Fitter Status : Successful - Mon Apr 19 01:27:14 2021 Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition Revision Name : GR8RAM Top-level Entity Name : GR8RAM diff --git a/cpld/output_files/GR8RAM.flow.rpt b/cpld/output_files/GR8RAM.flow.rpt index d23772d..b05c4f8 100755 --- a/cpld/output_files/GR8RAM.flow.rpt +++ b/cpld/output_files/GR8RAM.flow.rpt @@ -1,5 +1,5 @@ Flow report for GR8RAM -Sun Apr 18 06:27:24 2021 +Mon Apr 19 01:27:24 2021 Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition @@ -40,7 +40,7 @@ applicable agreement for further details. +-----------------------------------------------------------------------------+ ; Flow Summary ; +---------------------------+-------------------------------------------------+ -; Flow Status ; Successful - Sun Apr 18 06:27:18 2021 ; +; Flow Status ; Successful - Mon Apr 19 01:27:18 2021 ; ; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; ; Revision Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ; @@ -59,7 +59,7 @@ applicable agreement for further details. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 04/18/2021 06:27:01 ; +; Start date & time ; 04/19/2021 01:27:01 ; ; Main task ; Compilation ; ; Revision Name ; GR8RAM ; +-------------------+---------------------+ @@ -75,7 +75,7 @@ applicable agreement for further details. ; ALM_REGISTER_PACKING_EFFORT ; High ; Medium ; -- ; -- ; ; AUTO_PACKED_REGISTERS_MAXII ; Minimize Area ; Auto ; -- ; -- ; ; AUTO_RESOURCE_SHARING ; On ; Off ; -- ; -- ; -; COMPILER_SIGNATURE_ID ; 44085571633675.161874162103584 ; -- ; -- ; -- ; +; COMPILER_SIGNATURE_ID ; 44085571633675.161881002002548 ; -- ; -- ; -- ; ; FINAL_PLACEMENT_OPTIMIZATION ; Always ; Automatically ; -- ; -- ; ; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ; ; IOBANK_VCCIO ; 3.3V ; -- ; -- ; 1 ; @@ -102,11 +102,11 @@ applicable agreement for further details. +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:05 ; 1.0 ; 301 MB ; 00:00:05 ; -; Fitter ; 00:00:08 ; 1.2 ; 382 MB ; 00:00:08 ; +; Analysis & Synthesis ; 00:00:04 ; 1.0 ; 301 MB ; 00:00:04 ; +; Fitter ; 00:00:09 ; 2.0 ; 372 MB ; 00:00:08 ; ; Assembler ; 00:00:02 ; 1.0 ; 292 MB ; 00:00:02 ; -; TimeQuest Timing Analyzer ; 00:00:04 ; 1.0 ; 276 MB ; 00:00:04 ; -; Total ; 00:00:19 ; -- ; -- ; 00:00:19 ; +; TimeQuest Timing Analyzer ; 00:00:04 ; 1.0 ; 283 MB ; 00:00:04 ; +; Total ; 00:00:19 ; -- ; -- ; 00:00:18 ; +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ diff --git a/cpld/output_files/GR8RAM.jdi b/cpld/output_files/GR8RAM.jdi index 73a190b..7b766c8 100755 --- a/cpld/output_files/GR8RAM.jdi +++ b/cpld/output_files/GR8RAM.jdi @@ -1,6 +1,6 @@ - + diff --git a/cpld/output_files/GR8RAM.map.rpt b/cpld/output_files/GR8RAM.map.rpt index 648ddda..e165956 100755 --- a/cpld/output_files/GR8RAM.map.rpt +++ b/cpld/output_files/GR8RAM.map.rpt @@ -1,5 +1,5 @@ Analysis & Synthesis report for GR8RAM -Sun Apr 18 06:27:04 2021 +Mon Apr 19 01:27:04 2021 Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition @@ -45,12 +45,12 @@ applicable agreement for further details. +-------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +-----------------------------+-------------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Sun Apr 18 06:27:04 2021 ; +; Analysis & Synthesis Status ; Successful - Mon Apr 19 01:27:03 2021 ; ; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; ; Revision Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ; ; Family ; MAX II ; -; Total logic elements ; 228 ; +; Total logic elements ; 229 ; ; Total pins ; 80 ; ; Total virtual pins ; 0 ; ; UFM blocks ; 0 / 1 ( 0 % ) ; @@ -161,20 +161,20 @@ applicable agreement for further details. +---------------------------------------------+-------+ ; Resource ; Usage ; +---------------------------------------------+-------+ -; Total logic elements ; 228 ; -; -- Combinational with no register ; 125 ; -; -- Register only ; 7 ; -; -- Combinational with a register ; 96 ; +; Total logic elements ; 229 ; +; -- Combinational with no register ; 126 ; +; -- Register only ; 8 ; +; -- Combinational with a register ; 95 ; ; ; ; ; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 122 ; -; -- 3 input functions ; 37 ; -; -- 2 input functions ; 62 ; +; -- 4 input functions ; 123 ; +; -- 3 input functions ; 27 ; +; -- 2 input functions ; 69 ; ; -- 1 input functions ; 0 ; -; -- 0 input functions ; 0 ; +; -- 0 input functions ; 2 ; ; ; ; ; Logic elements by mode ; ; -; -- normal mode ; 195 ; +; -- normal mode ; 196 ; ; -- arithmetic mode ; 33 ; ; -- qfbk mode ; 0 ; ; -- register cascade mode ; 0 ; @@ -186,8 +186,8 @@ applicable agreement for further details. ; I/O pins ; 80 ; ; Maximum fan-out node ; C25M ; ; Maximum fan-out ; 100 ; -; Total fan-out ; 1024 ; -; Average fan-out ; 3.32 ; +; Total fan-out ; 1015 ; +; Average fan-out ; 3.28 ; +---------------------------------------------+-------+ @@ -196,7 +196,7 @@ applicable agreement for further details. +----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+ ; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ; +----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+ -; |GR8RAM ; 228 (228) ; 103 ; 0 ; 80 ; 0 ; 125 (125) ; 7 (7) ; 96 (96) ; 37 (37) ; 0 (0) ; |GR8RAM ; work ; +; |GR8RAM ; 229 (229) ; 103 ; 0 ; 80 ; 0 ; 126 (126) ; 8 (8) ; 95 (95) ; 37 (37) ; 0 (0) ; |GR8RAM ; work ; +----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. @@ -236,7 +236,7 @@ Encoding Type: Minimal Bits ; Number of registers using Synchronous Load ; 33 ; ; Number of registers using Asynchronous Clear ; 30 ; ; Number of registers using Asynchronous Load ; 0 ; -; Number of registers using Clock Enable ; 22 ; +; Number of registers using Clock Enable ; 24 ; ; Number of registers using Preset ; 0 ; +----------------------------------------------+-------+ @@ -263,8 +263,8 @@ Encoding Type: Minimal Bits ; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ ; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |GR8RAM|PS[1] ; -; 4:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |GR8RAM|SA[11]~reg0 ; -; 20:1 ; 6 bits ; 78 LEs ; 24 LEs ; 54 LEs ; Yes ; |GR8RAM|SA[8]~reg0 ; +; 4:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |GR8RAM|SA[9]~reg0 ; +; 20:1 ; 6 bits ; 78 LEs ; 24 LEs ; 54 LEs ; Yes ; |GR8RAM|SA[7]~reg0 ; ; 20:1 ; 3 bits ; 39 LEs ; 18 LEs ; 21 LEs ; Yes ; |GR8RAM|SA[2]~reg0 ; ; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |GR8RAM|WRD[7] ; ; 4:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |GR8RAM|RDD[1] ; @@ -279,42 +279,39 @@ Encoding Type: Minimal Bits Info: ******************************************************************* Info: Running Quartus II 32-bit Analysis & Synthesis Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - Info: Processing started: Sun Apr 18 06:26:59 2021 + Info: Processing started: Mon Apr 19 01:26:59 2021 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected Info (12021): Found 1 design units, including 1 entities, in source file gr8ram.v Info (12023): Found entity 1: GR8RAM Info (12127): Elaborating entity "GR8RAM" for the top level hierarchy -Warning (10036): Verilog HDL or VHDL warning at GR8RAM.v(269): object "SetRF" assigned a value but never read -Warning (10036): Verilog HDL or VHDL warning at GR8RAM.v(270): object "SetLim1M" assigned a value but never read -Warning (10036): Verilog HDL or VHDL warning at GR8RAM.v(271): object "SetLim8M" assigned a value but never read -Warning (10230): Verilog HDL assignment warning at GR8RAM.v(34): truncated value with size 32 to match size of target (14) -Warning (10230): Verilog HDL assignment warning at GR8RAM.v(117): truncated value with size 32 to match size of target (8) -Warning (10230): Verilog HDL assignment warning at GR8RAM.v(125): truncated value with size 32 to match size of target (8) -Warning (10230): Verilog HDL assignment warning at GR8RAM.v(132): truncated value with size 32 to match size of target (8) -Warning (10230): Verilog HDL assignment warning at GR8RAM.v(325): truncated value with size 32 to match size of target (4) +Warning (10230): Verilog HDL assignment warning at GR8RAM.v(20): truncated value with size 32 to match size of target (14) +Warning (10230): Verilog HDL assignment warning at GR8RAM.v(103): truncated value with size 32 to match size of target (8) +Warning (10230): Verilog HDL assignment warning at GR8RAM.v(111): truncated value with size 32 to match size of target (8) +Warning (10230): Verilog HDL assignment warning at GR8RAM.v(118): truncated value with size 32 to match size of target (8) +Warning (10230): Verilog HDL assignment warning at GR8RAM.v(309): truncated value with size 32 to match size of target (4) Info (17026): Resynthesizing 0 WYSIWYG logic cells and I/Os using "area" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched Warning (13024): Output pins are stuck at VCC or GND - Warning (13410): Pin "RAdir" is stuck at VCC - Warning (13410): Pin "nDMAout" is stuck at VCC Warning (13410): Pin "nNMIout" is stuck at VCC Warning (13410): Pin "nIRQout" is stuck at VCC Warning (13410): Pin "nRDYout" is stuck at VCC Warning (13410): Pin "nINHout" is stuck at VCC Warning (13410): Pin "RWout" is stuck at VCC + Warning (13410): Pin "nDMAout" is stuck at VCC + Warning (13410): Pin "RAdir" is stuck at VCC Info (17049): 1 registers lost all their fanouts during netlist optimizations. Warning (21074): Design contains 2 input pin(s) that do not drive logic Warning (15610): No output dependent on input pin "SetFW[0]" Warning (15610): No output dependent on input pin "SetFW[1]" -Info (21057): Implemented 308 device resources after synthesis - the final resource count might be different +Info (21057): Implemented 309 device resources after synthesis - the final resource count might be different Info (21058): Implemented 28 input pins Info (21059): Implemented 35 output pins Info (21060): Implemented 17 bidirectional pins - Info (21061): Implemented 228 logic cells + Info (21061): Implemented 229 logic cells Info (144001): Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg -Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 19 warnings +Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 16 warnings Info: Peak virtual memory: 301 megabytes - Info: Processing ended: Sun Apr 18 06:27:04 2021 + Info: Processing ended: Mon Apr 19 01:27:04 2021 Info: Elapsed time: 00:00:05 Info: Total CPU time (on all processors): 00:00:05 diff --git a/cpld/output_files/GR8RAM.map.smsg b/cpld/output_files/GR8RAM.map.smsg index 26e8737..f40de6b 100755 --- a/cpld/output_files/GR8RAM.map.smsg +++ b/cpld/output_files/GR8RAM.map.smsg @@ -1,2 +1,2 @@ -Warning (10273): Verilog HDL warning at GR8RAM.v(93): extended using "x" or "z" -Warning (10273): Verilog HDL warning at GR8RAM.v(274): extended using "x" or "z" +Warning (10273): Verilog HDL warning at GR8RAM.v(79): extended using "x" or "z" +Warning (10273): Verilog HDL warning at GR8RAM.v(259): extended using "x" or "z" diff --git a/cpld/output_files/GR8RAM.map.summary b/cpld/output_files/GR8RAM.map.summary index 4cc6e47..fb1c00f 100755 --- a/cpld/output_files/GR8RAM.map.summary +++ b/cpld/output_files/GR8RAM.map.summary @@ -1,9 +1,9 @@ -Analysis & Synthesis Status : Successful - Sun Apr 18 06:27:04 2021 +Analysis & Synthesis Status : Successful - Mon Apr 19 01:27:03 2021 Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition Revision Name : GR8RAM Top-level Entity Name : GR8RAM Family : MAX II -Total logic elements : 228 +Total logic elements : 229 Total pins : 80 Total virtual pins : 0 UFM blocks : 0 / 1 ( 0 % ) diff --git a/cpld/output_files/GR8RAM.pof b/cpld/output_files/GR8RAM.pof index 0a71b63..0872853 100755 Binary files a/cpld/output_files/GR8RAM.pof and b/cpld/output_files/GR8RAM.pof differ diff --git a/cpld/output_files/GR8RAM.sta.rpt b/cpld/output_files/GR8RAM.sta.rpt index bbe6bdd..96d55fa 100755 --- a/cpld/output_files/GR8RAM.sta.rpt +++ b/cpld/output_files/GR8RAM.sta.rpt @@ -1,5 +1,5 @@ TimeQuest Timing Analyzer report for GR8RAM -Sun Apr 18 06:27:24 2021 +Mon Apr 19 01:27:24 2021 Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition @@ -86,11 +86,11 @@ applicable agreement for further details. ; Maximum allowed ; 2 ; ; ; ; ; Average used ; 1.00 ; -; Maximum used ; 1 ; +; Maximum used ; 2 ; ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; -; Processor 2 ; 0.0% ; +; Processor 2 ; < 0.1% ; +----------------------------+-------------+ @@ -109,7 +109,7 @@ applicable agreement for further details. +------------+-----------------+------------+------+ ; Fmax ; Restricted Fmax ; Clock Name ; Note ; +------------+-----------------+------------+------+ -; 102.16 MHz ; 102.16 MHz ; C25M ; ; +; 100.46 MHz ; 100.46 MHz ; C25M ; ; +------------+-----------------+------------+------+ This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. @@ -119,8 +119,8 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +-------+--------+---------------+ -; C25M ; -9.035 ; -651.992 ; -; PHI0 ; 0.356 ; 0.000 ; +; C25M ; -9.468 ; -696.810 ; +; PHI0 ; 0.212 ; 0.000 ; +-------+--------+---------------+ @@ -129,8 +129,8 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +-------+--------+---------------+ -; PHI0 ; -0.263 ; -0.263 ; -; C25M ; 1.391 ; 0.000 ; +; PHI0 ; -0.265 ; -0.265 ; +; C25M ; 1.374 ; 0.000 ; +-------+--------+---------------+ @@ -139,7 +139,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +-------+--------+---------------+ -; C25M ; -4.406 ; -132.180 ; +; C25M ; -4.404 ; -127.716 ; +-------+--------+---------------+ @@ -148,7 +148,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +-------+-------+---------------+ -; C25M ; 4.852 ; 0.000 ; +; C25M ; 4.850 ; 0.000 ; +-------+-------+---------------+ @@ -167,106 +167,106 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +--------+----------------+----------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+----------------+----------------+--------------+-------------+--------------+------------+------------+ -; -9.035 ; RAMSpecSELr ; SA[5]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.911 ; -; -8.936 ; RAMSpecSELr ; RCKE~reg0 ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.812 ; -; -8.789 ; LS[9] ; IS.state_bit_0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.456 ; -; -8.787 ; RAMSpecSELr ; SA[1]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.663 ; -; -8.764 ; LS[11] ; IS.state_bit_0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.431 ; -; -8.734 ; RAMSpecSELr ; nRCS~reg0 ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.610 ; -; -8.648 ; LS[7] ; IS.state_bit_0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.315 ; -; -8.607 ; LS[8] ; IS.state_bit_0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.274 ; -; -8.582 ; LS[1] ; IS.state_bit_0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.249 ; -; -8.524 ; RAMSpecSELr ; SA[6]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.400 ; -; -8.511 ; nWEr ; Addr[10] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.387 ; -; -8.511 ; nWEr ; Addr[11] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.387 ; -; -8.511 ; nWEr ; Addr[12] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.387 ; -; -8.511 ; nWEr ; Addr[13] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.387 ; -; -8.511 ; nWEr ; Addr[14] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.387 ; -; -8.511 ; nWEr ; Addr[15] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.387 ; -; -8.511 ; nWEr ; Addr[8] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.387 ; -; -8.511 ; nWEr ; Addr[9] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.387 ; -; -8.417 ; LS[6] ; IS.state_bit_0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.084 ; -; -8.409 ; nWEr ; Addr[0] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.285 ; -; -8.409 ; nWEr ; Addr[1] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.285 ; -; -8.409 ; nWEr ; Addr[2] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.285 ; -; -8.409 ; nWEr ; Addr[3] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.285 ; -; -8.409 ; nWEr ; Addr[4] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.285 ; -; -8.409 ; nWEr ; Addr[5] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.285 ; -; -8.409 ; nWEr ; Addr[6] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.285 ; -; -8.409 ; nWEr ; Addr[7] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.285 ; -; -8.392 ; IS.state_bit_1 ; SA[1]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.059 ; -; -8.315 ; PS[2] ; RCKE~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.982 ; -; -8.304 ; LS[3] ; IS.state_bit_0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.971 ; -; -8.297 ; RAMSpecSELr ; SA[7]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.173 ; -; -8.288 ; RAMSpecSELr ; SA[8]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.164 ; -; -8.254 ; RAMSpecSELr ; SA[0]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.130 ; -; -8.218 ; PS[2] ; Addr[10] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.885 ; -; -8.218 ; PS[2] ; Addr[11] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.885 ; -; -8.218 ; PS[2] ; Addr[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.885 ; -; -8.218 ; PS[2] ; Addr[13] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.885 ; -; -8.218 ; PS[2] ; Addr[14] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.885 ; -; -8.218 ; PS[2] ; Addr[15] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.885 ; -; -8.218 ; PS[2] ; Addr[8] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.885 ; -; -8.218 ; PS[2] ; Addr[9] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.885 ; -; -8.198 ; IS.state_bit_1 ; SA[0]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.865 ; -; -8.156 ; ROMSpecRDr ; RCKE~reg0 ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.032 ; -; -8.116 ; PS[2] ; Addr[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.783 ; -; -8.116 ; PS[2] ; Addr[1] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.783 ; -; -8.116 ; PS[2] ; Addr[2] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.783 ; -; -8.116 ; PS[2] ; Addr[3] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.783 ; -; -8.116 ; PS[2] ; Addr[4] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.783 ; -; -8.116 ; PS[2] ; Addr[5] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.783 ; -; -8.116 ; PS[2] ; Addr[6] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.783 ; -; -8.116 ; PS[2] ; Addr[7] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.783 ; -; -8.100 ; nWEr ; Addr[23] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 5.976 ; -; -8.100 ; nWEr ; Addr[16] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 5.976 ; -; -8.100 ; nWEr ; Addr[17] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 5.976 ; -; -8.100 ; nWEr ; Addr[18] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 5.976 ; -; -8.100 ; nWEr ; Addr[19] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 5.976 ; -; -8.100 ; nWEr ; Addr[20] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 5.976 ; -; -8.100 ; nWEr ; Addr[21] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 5.976 ; -; -8.100 ; nWEr ; Addr[22] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 5.976 ; -; -8.062 ; RAMSpecSELr ; SA[3]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.791 ; 5.938 ; -; -8.061 ; PS[3] ; Addr[10] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.728 ; -; -8.061 ; PS[3] ; Addr[11] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.728 ; -; -8.061 ; PS[3] ; Addr[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.728 ; -; -8.061 ; PS[3] ; Addr[13] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.728 ; -; -8.061 ; PS[3] ; Addr[14] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.728 ; -; -8.061 ; PS[3] ; Addr[15] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.728 ; -; -8.061 ; PS[3] ; Addr[8] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.728 ; -; -8.061 ; PS[3] ; Addr[9] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.728 ; -; -8.060 ; LS[10] ; IS.state_bit_0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.727 ; -; -8.059 ; RAMSpecSELr ; SA[4]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.791 ; 5.935 ; -; -8.039 ; IS.state_bit_1 ; SA[5]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.706 ; -; -8.034 ; LS[9] ; IS.state_bit_1 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.701 ; -; -8.026 ; IS.state_bit_0 ; SA[5]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.693 ; -; -8.009 ; LS[11] ; IS.state_bit_1 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.676 ; -; -8.004 ; PS[1] ; RCKE~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.671 ; -; -7.983 ; IS.state_bit_0 ; SA[1]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.650 ; -; -7.981 ; RAMSpecSELr ; SA[2]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.791 ; 5.857 ; -; -7.969 ; LS[9] ; IS.state_bit_2 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.636 ; -; -7.959 ; PS[3] ; Addr[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.626 ; -; -7.959 ; PS[3] ; Addr[1] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.626 ; -; -7.959 ; PS[3] ; Addr[2] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.626 ; -; -7.959 ; PS[3] ; Addr[3] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.626 ; -; -7.959 ; PS[3] ; Addr[4] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.626 ; -; -7.959 ; PS[3] ; Addr[5] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.626 ; -; -7.959 ; PS[3] ; Addr[6] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.626 ; -; -7.959 ; PS[3] ; Addr[7] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.626 ; -; -7.944 ; LS[11] ; IS.state_bit_2 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.611 ; -; -7.893 ; LS[7] ; IS.state_bit_1 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.560 ; -; -7.880 ; PS[1] ; Addr[10] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.547 ; -; -7.880 ; PS[1] ; Addr[11] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.547 ; -; -7.880 ; PS[1] ; Addr[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.547 ; -; -7.880 ; PS[1] ; Addr[13] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.547 ; -; -7.880 ; PS[1] ; Addr[14] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.547 ; -; -7.880 ; PS[1] ; Addr[15] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.547 ; -; -7.880 ; PS[1] ; Addr[8] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.547 ; -; -7.880 ; PS[1] ; Addr[9] ; C25M ; C25M ; 1.000 ; 0.000 ; 8.547 ; -; -7.863 ; IS.state_bit_0 ; nRCS~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.530 ; -; -7.852 ; LS[8] ; IS.state_bit_1 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.519 ; -; -7.830 ; LS[13] ; IS.state_bit_0 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.497 ; -; -7.828 ; LS[7] ; IS.state_bit_2 ; C25M ; C25M ; 1.000 ; 0.000 ; 8.495 ; +; -9.468 ; RAMSpecSELr ; SA[1]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.791 ; 7.344 ; +; -9.201 ; RAMSpecSELr ; RCKE~reg0 ; PHI0 ; C25M ; 1.000 ; -2.791 ; 7.077 ; +; -9.122 ; nWEr ; Addr[0] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.998 ; +; -9.122 ; nWEr ; Addr[1] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.998 ; +; -9.122 ; nWEr ; Addr[2] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.998 ; +; -9.122 ; nWEr ; Addr[3] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.998 ; +; -9.122 ; nWEr ; Addr[4] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.998 ; +; -9.122 ; nWEr ; Addr[5] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.998 ; +; -9.122 ; nWEr ; Addr[6] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.998 ; +; -9.122 ; nWEr ; Addr[7] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.998 ; +; -9.097 ; RAMSpecSELr ; SA[0]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.973 ; +; -9.073 ; nWEr ; RCKE~reg0 ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.949 ; +; -9.028 ; nWEr ; Addr[23] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.904 ; +; -9.028 ; nWEr ; Addr[16] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.904 ; +; -9.028 ; nWEr ; Addr[17] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.904 ; +; -9.028 ; nWEr ; Addr[18] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.904 ; +; -9.028 ; nWEr ; Addr[19] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.904 ; +; -9.028 ; nWEr ; Addr[20] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.904 ; +; -9.028 ; nWEr ; Addr[21] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.904 ; +; -9.028 ; nWEr ; Addr[22] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.904 ; +; -8.999 ; RAMSpecSELr ; SA[7]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.875 ; +; -8.954 ; PS[0] ; SA[2]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.621 ; +; -8.925 ; nWEr ; Addr[10] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.801 ; +; -8.925 ; nWEr ; Addr[11] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.801 ; +; -8.925 ; nWEr ; Addr[12] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.801 ; +; -8.925 ; nWEr ; Addr[13] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.801 ; +; -8.925 ; nWEr ; Addr[14] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.801 ; +; -8.925 ; nWEr ; Addr[15] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.801 ; +; -8.925 ; nWEr ; Addr[8] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.801 ; +; -8.925 ; nWEr ; Addr[9] ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.801 ; +; -8.873 ; RAMSpecSELr ; SA[5]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.749 ; +; -8.872 ; PS[0] ; Addr[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.539 ; +; -8.872 ; PS[0] ; Addr[1] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.539 ; +; -8.872 ; PS[0] ; Addr[2] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.539 ; +; -8.872 ; PS[0] ; Addr[3] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.539 ; +; -8.872 ; PS[0] ; Addr[4] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.539 ; +; -8.872 ; PS[0] ; Addr[5] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.539 ; +; -8.872 ; PS[0] ; Addr[6] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.539 ; +; -8.872 ; PS[0] ; Addr[7] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.539 ; +; -8.795 ; RAMSpecSELr ; SA[8]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.671 ; +; -8.778 ; PS[0] ; Addr[23] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.445 ; +; -8.778 ; PS[0] ; Addr[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.445 ; +; -8.778 ; PS[0] ; Addr[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.445 ; +; -8.778 ; PS[0] ; Addr[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.445 ; +; -8.778 ; PS[0] ; Addr[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.445 ; +; -8.778 ; PS[0] ; Addr[20] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.445 ; +; -8.778 ; PS[0] ; Addr[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.445 ; +; -8.778 ; PS[0] ; Addr[22] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.445 ; +; -8.765 ; nWEr ; nRCS~reg0 ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.641 ; +; -8.729 ; ROMSpecRDr ; RCKE~reg0 ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.605 ; +; -8.728 ; PS[1] ; IS.state_bit_2 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.395 ; +; -8.675 ; PS[0] ; Addr[10] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.342 ; +; -8.675 ; PS[0] ; Addr[11] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.342 ; +; -8.675 ; PS[0] ; Addr[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.342 ; +; -8.675 ; PS[0] ; Addr[13] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.342 ; +; -8.675 ; PS[0] ; Addr[14] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.342 ; +; -8.675 ; PS[0] ; Addr[15] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.342 ; +; -8.675 ; PS[0] ; Addr[8] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.342 ; +; -8.675 ; PS[0] ; Addr[9] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.342 ; +; -8.610 ; PS[2] ; Addr[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.277 ; +; -8.610 ; PS[2] ; Addr[1] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.277 ; +; -8.610 ; PS[2] ; Addr[2] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.277 ; +; -8.610 ; PS[2] ; Addr[3] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.277 ; +; -8.610 ; PS[2] ; Addr[4] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.277 ; +; -8.610 ; PS[2] ; Addr[5] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.277 ; +; -8.610 ; PS[2] ; Addr[6] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.277 ; +; -8.610 ; PS[2] ; Addr[7] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.277 ; +; -8.590 ; RAMSpecSELr ; SA[6]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.466 ; +; -8.589 ; RAMSpecSELr ; SA[4]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.465 ; +; -8.579 ; RAMSpecSELr ; SA[3]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.455 ; +; -8.559 ; RAMSpecSELr ; SA[2]~reg0 ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.435 ; +; -8.516 ; PS[2] ; Addr[23] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.183 ; +; -8.516 ; PS[2] ; Addr[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.183 ; +; -8.516 ; PS[2] ; Addr[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.183 ; +; -8.516 ; PS[2] ; Addr[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.183 ; +; -8.516 ; PS[2] ; Addr[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.183 ; +; -8.516 ; PS[2] ; Addr[20] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.183 ; +; -8.516 ; PS[2] ; Addr[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.183 ; +; -8.516 ; PS[2] ; Addr[22] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.183 ; +; -8.469 ; RAMSpecSELr ; nRCS~reg0 ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.345 ; +; -8.461 ; PS[1] ; Addr[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.128 ; +; -8.461 ; PS[1] ; Addr[1] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.128 ; +; -8.461 ; PS[1] ; Addr[2] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.128 ; +; -8.461 ; PS[1] ; Addr[3] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.128 ; +; -8.461 ; PS[1] ; Addr[4] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.128 ; +; -8.461 ; PS[1] ; Addr[5] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.128 ; +; -8.461 ; PS[1] ; Addr[6] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.128 ; +; -8.461 ; PS[1] ; Addr[7] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.128 ; +; -8.413 ; PS[2] ; Addr[10] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.080 ; +; -8.413 ; PS[2] ; Addr[11] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.080 ; +; -8.413 ; PS[2] ; Addr[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.080 ; +; -8.413 ; PS[2] ; Addr[13] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.080 ; +; -8.413 ; PS[2] ; Addr[14] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.080 ; +; -8.413 ; PS[2] ; Addr[15] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.080 ; +; -8.413 ; PS[2] ; Addr[8] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.080 ; +; -8.413 ; PS[2] ; Addr[9] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.080 ; +; -8.403 ; IS.state_bit_0 ; SA[1]~reg0 ; C25M ; C25M ; 1.000 ; 0.000 ; 9.070 ; +; -8.384 ; nWEr ; SDOE ; PHI0 ; C25M ; 1.000 ; -2.791 ; 6.260 ; +; -8.367 ; PS[1] ; Addr[23] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.034 ; +; -8.367 ; PS[1] ; Addr[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 9.034 ; +--------+----------------+----------------+--------------+-------------+--------------+------------+------------+ @@ -275,8 +275,8 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+-----------+-------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +-------+-----------+-------------+--------------+-------------+--------------+------------+------------+ -; 0.356 ; REGEN ; RAMSpecSELr ; C25M ; PHI0 ; 1.000 ; 2.791 ; 3.102 ; -; 0.709 ; IOROMEN ; ROMSpecRDr ; C25M ; PHI0 ; 1.000 ; 2.791 ; 2.749 ; +; 0.212 ; REGEN ; RAMSpecSELr ; C25M ; PHI0 ; 1.000 ; 2.791 ; 3.246 ; +; 0.711 ; IOROMEN ; ROMSpecRDr ; C25M ; PHI0 ; 1.000 ; 2.791 ; 2.747 ; +-------+-----------+-------------+--------------+-------------+--------------+------------+------------+ @@ -285,8 +285,8 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ -; -0.263 ; IOROMEN ; ROMSpecRDr ; C25M ; PHI0 ; 0.000 ; 2.791 ; 2.749 ; -; 0.090 ; REGEN ; RAMSpecSELr ; C25M ; PHI0 ; 0.000 ; 2.791 ; 3.102 ; +; -0.265 ; IOROMEN ; ROMSpecRDr ; C25M ; PHI0 ; 0.000 ; 2.791 ; 2.747 ; +; 0.234 ; REGEN ; RAMSpecSELr ; C25M ; PHI0 ; 0.000 ; 2.791 ; 3.246 ; +--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ @@ -295,106 +295,106 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+----------------+----------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +-------+----------------+----------------+--------------+-------------+--------------+------------+------------+ -; 1.391 ; nRESr0 ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 1.612 ; -; 1.401 ; WRD[7] ; WRD[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.622 ; -; 1.402 ; WRD[6] ; WRD[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.623 ; -; 1.404 ; WRD[2] ; WRD[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.625 ; -; 1.413 ; WRD[0] ; WRD[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.634 ; -; 1.453 ; PHI0 ; PHI0r1 ; PHI0 ; C25M ; 0.000 ; 3.458 ; 5.132 ; -; 1.639 ; nRESout~reg0 ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 1.860 ; -; 1.796 ; WRD[4] ; WRD[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.017 ; -; 1.800 ; WRD[3] ; WRD[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.021 ; -; 1.828 ; PHI0r1 ; PHI0r2 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.049 ; +; 1.374 ; WRD[6] ; WRD[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.595 ; +; 1.375 ; WRD[7] ; WRD[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.596 ; +; 1.396 ; nRESr0 ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 1.617 ; +; 1.518 ; PHI0 ; PHI0r1 ; PHI0 ; C25M ; 0.000 ; 3.458 ; 5.197 ; +; 1.653 ; WRD[0] ; WRD[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.874 ; +; 1.653 ; WRD[5] ; WRD[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.874 ; +; 1.654 ; WRD[2] ; WRD[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.875 ; +; 1.657 ; nRESout~reg0 ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 1.878 ; +; 1.693 ; PS[1] ; PS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.914 ; +; 1.768 ; WRD[2] ; WRD[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.989 ; +; 1.783 ; PHI0r1 ; PHI0r2 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.004 ; +; 1.827 ; WRD[5] ; WRD[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.048 ; +; 1.836 ; WRD[3] ; WRD[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.057 ; ; 1.837 ; WRD[1] ; WRD[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.058 ; -; 1.919 ; IOROMEN ; IOROMEN ; C25M ; C25M ; 0.000 ; 0.000 ; 2.140 ; -; 1.950 ; LS[0] ; LS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.171 ; -; 1.953 ; PHI0 ; PHI0r1 ; PHI0 ; C25M ; -0.500 ; 3.458 ; 5.132 ; -; 2.063 ; LS[13] ; LS[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.284 ; +; 1.942 ; PS[2] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.163 ; +; 2.004 ; IS.state_bit_0 ; IS.state_bit_0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.225 ; +; 2.018 ; PHI0 ; PHI0r1 ; PHI0 ; C25M ; -0.500 ; 3.458 ; 5.197 ; +; 2.084 ; LS[13] ; LS[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.305 ; ; 2.107 ; LS[7] ; LS[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.328 ; -; 2.109 ; WRD[4] ; WRD[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.330 ; +; 2.117 ; Addr[10] ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; ; 2.117 ; Addr[1] ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; ; 2.117 ; Addr[2] ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; -; 2.124 ; Addr[8] ; Addr[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.345 ; -; 2.125 ; Addr[16] ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.346 ; -; 2.126 ; Addr[23] ; Addr[23] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ; +; 2.117 ; Addr[9] ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; +; 2.121 ; WRD[3] ; WRD[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.342 ; +; 2.124 ; Addr[16] ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.345 ; +; 2.125 ; Addr[8] ; Addr[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.346 ; ; 2.126 ; Bank ; Bank ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ; +; 2.126 ; LS[4] ; LS[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ; +; 2.126 ; Addr[15] ; Addr[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ; ; 2.126 ; Addr[17] ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ; ; 2.126 ; Addr[18] ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ; -; 2.126 ; LS[9] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ; -; 2.127 ; Addr[15] ; Addr[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.348 ; -; 2.134 ; LS[8] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.355 ; -; 2.135 ; LS[6] ; LS[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.356 ; -; 2.140 ; WRD[2] ; WRD[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.361 ; +; 2.127 ; Addr[23] ; Addr[23] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.348 ; +; 2.131 ; PS[2] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.352 ; +; 2.135 ; Addr[7] ; Addr[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.356 ; +; 2.137 ; PS[3] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.358 ; ; 2.142 ; Addr[0] ; Addr[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.363 ; -; 2.143 ; Addr[9] ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.364 ; -; 2.145 ; Addr[10] ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.366 ; -; 2.145 ; Addr[7] ; Addr[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.366 ; -; 2.146 ; Addr[7] ; AddrIncM ; C25M ; C25M ; 0.000 ; 0.000 ; 2.367 ; -; 2.158 ; LS[4] ; LS[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.379 ; -; 2.169 ; LS[0] ; LS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.390 ; -; 2.203 ; PS[1] ; SA[10]~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.424 ; -; 2.221 ; Addr[3] ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.442 ; -; 2.222 ; Addr[19] ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.443 ; -; 2.228 ; AddrIncH ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.449 ; -; 2.230 ; LS[12] ; LS[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.451 ; -; 2.230 ; Addr[5] ; Addr[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.451 ; +; 2.144 ; LS[6] ; LS[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.365 ; +; 2.144 ; LS[8] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.365 ; +; 2.144 ; LS[9] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.365 ; +; 2.144 ; LS[0] ; LS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.365 ; +; 2.147 ; LS[0] ; LS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.368 ; +; 2.165 ; PS[1] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.386 ; +; 2.212 ; Addr[19] ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.433 ; +; 2.213 ; WRD[4] ; WRD[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.434 ; ; 2.230 ; Addr[21] ; Addr[21] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.451 ; -; 2.231 ; Addr[4] ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; -; 2.231 ; Addr[6] ; Addr[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; ; 2.231 ; Addr[20] ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; ; 2.231 ; Addr[22] ; Addr[22] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; -; 2.232 ; LS[10] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.453 ; +; 2.232 ; Addr[11] ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.453 ; ; 2.232 ; LS[5] ; LS[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.453 ; -; 2.233 ; WRD[5] ; WRD[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.454 ; -; 2.235 ; WRD[3] ; WRD[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.456 ; -; 2.241 ; Addr[11] ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.462 ; -; 2.243 ; LS[11] ; LS[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.464 ; -; 2.246 ; WRD[5] ; WRD[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.467 ; +; 2.241 ; Addr[3] ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.462 ; +; 2.248 ; LS[12] ; LS[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.469 ; ; 2.249 ; Addr[14] ; Addr[14] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.470 ; -; 2.249 ; REGEN ; REGEN ; C25M ; C25M ; 0.000 ; 0.000 ; 2.470 ; +; 2.249 ; Addr[5] ; Addr[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.470 ; +; 2.250 ; LS[11] ; LS[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.471 ; ; 2.251 ; LS[2] ; LS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.472 ; -; 2.251 ; WRD[0] ; WRD[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.472 ; +; 2.251 ; Addr[6] ; Addr[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.472 ; ; 2.252 ; LS[1] ; LS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.473 ; +; 2.253 ; LS[10] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.474 ; ; 2.261 ; Addr[12] ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.482 ; ; 2.261 ; Addr[13] ; Addr[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.482 ; -; 2.327 ; PS[1] ; PS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.548 ; -; 2.331 ; PS[1] ; nCAS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.552 ; -; 2.346 ; PS[1] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.567 ; -; 2.346 ; PS[1] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.567 ; -; 2.388 ; Addr[2] ; RDD[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.609 ; -; 2.485 ; Addr[15] ; AddrIncH ; C25M ; C25M ; 0.000 ; 0.000 ; 2.706 ; -; 2.559 ; LS[3] ; LS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.780 ; -; 2.589 ; PHI0r2 ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.810 ; -; 2.645 ; AddrIncL ; Addr[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.866 ; -; 2.661 ; PS[2] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.882 ; -; 2.673 ; WRD[1] ; WRD[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.894 ; -; 2.677 ; Addr[1] ; RDD[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.898 ; -; 2.688 ; IS.state_bit_1 ; IS.state_bit_0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.909 ; -; 2.739 ; PS[0] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.960 ; -; 2.749 ; PS[0] ; nCAS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.970 ; -; 2.750 ; PS[0] ; PS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.971 ; -; 2.763 ; PS[1] ; nRAS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.984 ; -; 2.891 ; PS[0] ; MOSIout ; C25M ; C25M ; 0.000 ; 0.000 ; 3.112 ; -; 2.910 ; IS.state_bit_2 ; FCS ; C25M ; C25M ; 0.000 ; 0.000 ; 3.131 ; -; 2.914 ; IS.state_bit_2 ; FCKOE ; C25M ; C25M ; 0.000 ; 0.000 ; 3.135 ; -; 2.915 ; IS.state_bit_2 ; MOSIOE ; C25M ; C25M ; 0.000 ; 0.000 ; 3.136 ; +; 2.269 ; WRD[4] ; WRD[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.490 ; +; 2.280 ; PS[0] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.501 ; +; 2.325 ; IS.state_bit_1 ; IS.state_bit_0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.546 ; +; 2.350 ; WRD[0] ; WRD[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.571 ; +; 2.529 ; Addr[12] ; RDD[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.750 ; +; 2.545 ; PS[0] ; PS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.766 ; +; 2.551 ; Addr[4] ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.772 ; +; 2.621 ; PS[0] ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.842 ; +; 2.627 ; LS[3] ; LS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.848 ; +; 2.675 ; WRD[1] ; WRD[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.896 ; +; 2.701 ; PS[2] ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.922 ; +; 2.751 ; IS.state_bit_1 ; IS.state_bit_1 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.972 ; +; 2.848 ; PS[0] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.069 ; ; 2.939 ; LS[7] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.160 ; +; 2.949 ; Addr[9] ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; +; 2.949 ; Addr[10] ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; ; 2.949 ; Addr[1] ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; ; 2.949 ; Addr[2] ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; -; 2.956 ; Addr[8] ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.177 ; -; 2.957 ; Addr[16] ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.178 ; -; 2.958 ; LS[9] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.179 ; +; 2.956 ; Addr[16] ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.177 ; +; 2.957 ; Addr[8] ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.178 ; +; 2.958 ; LS[4] ; LS[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.179 ; ; 2.958 ; Addr[17] ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.179 ; ; 2.958 ; Addr[18] ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.179 ; -; 2.966 ; LS[8] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.187 ; -; 2.969 ; Addr[4] ; RDD[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.190 ; +; 2.964 ; PS[2] ; SA[5]~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.185 ; ; 2.974 ; Addr[0] ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.195 ; -; 2.975 ; Addr[9] ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.196 ; -; 2.977 ; Addr[10] ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.198 ; -; 2.990 ; LS[4] ; LS[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.211 ; -; 3.028 ; Addr[0] ; RDD[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.249 ; -; 3.045 ; Addr[5] ; RDD[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.266 ; +; 2.976 ; LS[9] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.197 ; +; 2.976 ; LS[8] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.197 ; ; 3.050 ; LS[7] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.271 ; +; 3.060 ; Addr[10] ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ; +; 3.060 ; Addr[2] ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ; +; 3.060 ; Addr[9] ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ; +; 3.060 ; Addr[1] ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ; +; 3.067 ; Addr[16] ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.288 ; +; 3.068 ; Addr[8] ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.289 ; +; 3.069 ; LS[4] ; LS[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.290 ; +; 3.069 ; Addr[18] ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.290 ; +; 3.069 ; Addr[17] ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.290 ; +; 3.085 ; Addr[0] ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.306 ; +; 3.087 ; LS[9] ; LS[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.308 ; +; 3.087 ; LS[8] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.308 ; +-------+----------------+----------------+--------------+-------------+--------------+------------+------------+ @@ -403,36 +403,35 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +--------+-----------+----------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+-----------+----------+--------------+-------------+--------------+------------+------------+ -; -4.406 ; nRESr ; IOROMEN ; C25M ; C25M ; 1.000 ; 0.000 ; 5.073 ; -; -4.406 ; nRESr ; Addr[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.073 ; -; -4.406 ; nRESr ; Addr[23] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.073 ; -; -4.406 ; nRESr ; Addr[10] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.073 ; -; -4.406 ; nRESr ; Addr[1] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.073 ; -; -4.406 ; nRESr ; Addr[11] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.073 ; -; -4.406 ; nRESr ; Addr[2] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.073 ; -; -4.406 ; nRESr ; Addr[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.073 ; -; -4.406 ; nRESr ; Bank ; C25M ; C25M ; 1.000 ; 0.000 ; 5.073 ; -; -4.406 ; nRESr ; Addr[3] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.073 ; -; -4.406 ; nRESr ; Addr[13] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.073 ; -; -4.406 ; nRESr ; Addr[4] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.073 ; -; -4.406 ; nRESr ; Addr[14] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.073 ; -; -4.406 ; nRESr ; Addr[5] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.073 ; -; -4.406 ; nRESr ; Addr[15] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.073 ; -; -4.406 ; nRESr ; Addr[6] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.073 ; -; -4.406 ; nRESr ; Addr[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.073 ; -; -4.406 ; nRESr ; Addr[7] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.073 ; -; -4.406 ; nRESr ; Addr[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.073 ; -; -4.406 ; nRESr ; Addr[8] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.073 ; -; -4.406 ; nRESr ; Addr[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.073 ; -; -4.406 ; nRESr ; Addr[9] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.073 ; -; -4.406 ; nRESr ; Addr[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.073 ; -; -4.406 ; nRESr ; Addr[20] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.073 ; -; -4.406 ; nRESr ; Addr[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.073 ; -; -4.406 ; nRESr ; Addr[22] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.073 ; -; -4.406 ; nRESr ; REGEN ; C25M ; C25M ; 1.000 ; 0.000 ; 5.073 ; -; -4.406 ; nRESr ; AddrIncH ; C25M ; C25M ; 1.000 ; 0.000 ; 5.073 ; -; -4.406 ; nRESr ; AddrIncM ; C25M ; C25M ; 1.000 ; 0.000 ; 5.073 ; -; -4.406 ; nRESr ; AddrIncL ; C25M ; C25M ; 1.000 ; 0.000 ; 5.073 ; +; -4.404 ; nRESr ; Addr[0] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.071 ; +; -4.404 ; nRESr ; Addr[23] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.071 ; +; -4.404 ; nRESr ; Addr[10] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.071 ; +; -4.404 ; nRESr ; Addr[1] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.071 ; +; -4.404 ; nRESr ; Addr[11] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.071 ; +; -4.404 ; nRESr ; Addr[2] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.071 ; +; -4.404 ; nRESr ; Addr[12] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.071 ; +; -4.404 ; nRESr ; Bank ; C25M ; C25M ; 1.000 ; 0.000 ; 5.071 ; +; -4.404 ; nRESr ; Addr[3] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.071 ; +; -4.404 ; nRESr ; Addr[13] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.071 ; +; -4.404 ; nRESr ; Addr[4] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.071 ; +; -4.404 ; nRESr ; Addr[14] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.071 ; +; -4.404 ; nRESr ; Addr[5] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.071 ; +; -4.404 ; nRESr ; Addr[15] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.071 ; +; -4.404 ; nRESr ; Addr[6] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.071 ; +; -4.404 ; nRESr ; Addr[16] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.071 ; +; -4.404 ; nRESr ; Addr[7] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.071 ; +; -4.404 ; nRESr ; Addr[17] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.071 ; +; -4.404 ; nRESr ; Addr[8] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.071 ; +; -4.404 ; nRESr ; Addr[18] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.071 ; +; -4.404 ; nRESr ; Addr[9] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.071 ; +; -4.404 ; nRESr ; Addr[19] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.071 ; +; -4.404 ; nRESr ; Addr[20] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.071 ; +; -4.404 ; nRESr ; Addr[21] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.071 ; +; -4.404 ; nRESr ; Addr[22] ; C25M ; C25M ; 1.000 ; 0.000 ; 5.071 ; +; -4.404 ; nRESr ; REGEN ; C25M ; C25M ; 1.000 ; 0.000 ; 5.071 ; +; -4.404 ; nRESr ; AddrIncH ; C25M ; C25M ; 1.000 ; 0.000 ; 5.071 ; +; -4.404 ; nRESr ; AddrIncM ; C25M ; C25M ; 1.000 ; 0.000 ; 5.071 ; +; -4.404 ; nRESr ; AddrIncL ; C25M ; C25M ; 1.000 ; 0.000 ; 5.071 ; +--------+-----------+----------+--------------+-------------+--------------+------------+------------+ @@ -441,36 +440,35 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+-----------+----------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +-------+-----------+----------+--------------+-------------+--------------+------------+------------+ -; 4.852 ; nRESr ; IOROMEN ; C25M ; C25M ; 0.000 ; 0.000 ; 5.073 ; -; 4.852 ; nRESr ; Addr[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.073 ; -; 4.852 ; nRESr ; Addr[23] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.073 ; -; 4.852 ; nRESr ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.073 ; -; 4.852 ; nRESr ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.073 ; -; 4.852 ; nRESr ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.073 ; -; 4.852 ; nRESr ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.073 ; -; 4.852 ; nRESr ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.073 ; -; 4.852 ; nRESr ; Bank ; C25M ; C25M ; 0.000 ; 0.000 ; 5.073 ; -; 4.852 ; nRESr ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.073 ; -; 4.852 ; nRESr ; Addr[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.073 ; -; 4.852 ; nRESr ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.073 ; -; 4.852 ; nRESr ; Addr[14] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.073 ; -; 4.852 ; nRESr ; Addr[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.073 ; -; 4.852 ; nRESr ; Addr[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.073 ; -; 4.852 ; nRESr ; Addr[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.073 ; -; 4.852 ; nRESr ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.073 ; -; 4.852 ; nRESr ; Addr[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.073 ; -; 4.852 ; nRESr ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.073 ; -; 4.852 ; nRESr ; Addr[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.073 ; -; 4.852 ; nRESr ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.073 ; -; 4.852 ; nRESr ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.073 ; -; 4.852 ; nRESr ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.073 ; -; 4.852 ; nRESr ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.073 ; -; 4.852 ; nRESr ; Addr[21] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.073 ; -; 4.852 ; nRESr ; Addr[22] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.073 ; -; 4.852 ; nRESr ; REGEN ; C25M ; C25M ; 0.000 ; 0.000 ; 5.073 ; -; 4.852 ; nRESr ; AddrIncH ; C25M ; C25M ; 0.000 ; 0.000 ; 5.073 ; -; 4.852 ; nRESr ; AddrIncM ; C25M ; C25M ; 0.000 ; 0.000 ; 5.073 ; -; 4.852 ; nRESr ; AddrIncL ; C25M ; C25M ; 0.000 ; 0.000 ; 5.073 ; +; 4.850 ; nRESr ; Addr[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.071 ; +; 4.850 ; nRESr ; Addr[23] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.071 ; +; 4.850 ; nRESr ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.071 ; +; 4.850 ; nRESr ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.071 ; +; 4.850 ; nRESr ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.071 ; +; 4.850 ; nRESr ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.071 ; +; 4.850 ; nRESr ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.071 ; +; 4.850 ; nRESr ; Bank ; C25M ; C25M ; 0.000 ; 0.000 ; 5.071 ; +; 4.850 ; nRESr ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.071 ; +; 4.850 ; nRESr ; Addr[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.071 ; +; 4.850 ; nRESr ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.071 ; +; 4.850 ; nRESr ; Addr[14] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.071 ; +; 4.850 ; nRESr ; Addr[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.071 ; +; 4.850 ; nRESr ; Addr[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.071 ; +; 4.850 ; nRESr ; Addr[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.071 ; +; 4.850 ; nRESr ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.071 ; +; 4.850 ; nRESr ; Addr[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.071 ; +; 4.850 ; nRESr ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.071 ; +; 4.850 ; nRESr ; Addr[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.071 ; +; 4.850 ; nRESr ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.071 ; +; 4.850 ; nRESr ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.071 ; +; 4.850 ; nRESr ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.071 ; +; 4.850 ; nRESr ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.071 ; +; 4.850 ; nRESr ; Addr[21] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.071 ; +; 4.850 ; nRESr ; Addr[22] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.071 ; +; 4.850 ; nRESr ; REGEN ; C25M ; C25M ; 0.000 ; 0.000 ; 5.071 ; +; 4.850 ; nRESr ; AddrIncH ; C25M ; C25M ; 0.000 ; 0.000 ; 5.071 ; +; 4.850 ; nRESr ; AddrIncM ; C25M ; C25M ; 0.000 ; 0.000 ; 5.071 ; +; 4.850 ; nRESr ; AddrIncL ; C25M ; C25M ; 0.000 ; 0.000 ; 5.071 ; +-------+-----------+----------+--------------+-------------+--------------+------------+------------+ @@ -610,63 +608,62 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-----------+------------+--------+--------+------------+-----------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+--------+--------+------------+-----------------+ -; MISO ; C25M ; 4.086 ; 4.086 ; Rise ; C25M ; -; MOSI ; C25M ; 4.156 ; 4.156 ; Rise ; C25M ; -; PHI0 ; C25M ; 2.007 ; 2.007 ; Rise ; C25M ; -; RA[*] ; C25M ; 13.145 ; 13.145 ; Rise ; C25M ; -; RA[0] ; C25M ; 8.916 ; 8.916 ; Rise ; C25M ; -; RA[1] ; C25M ; 8.770 ; 8.770 ; Rise ; C25M ; -; RA[2] ; C25M ; 9.694 ; 9.694 ; Rise ; C25M ; -; RA[3] ; C25M ; 10.921 ; 10.921 ; Rise ; C25M ; -; RA[4] ; C25M ; 8.022 ; 8.022 ; Rise ; C25M ; -; RA[5] ; C25M ; 9.447 ; 9.447 ; Rise ; C25M ; -; RA[6] ; C25M ; 7.054 ; 7.054 ; Rise ; C25M ; -; RA[7] ; C25M ; 11.195 ; 11.195 ; Rise ; C25M ; -; RA[8] ; C25M ; 12.820 ; 12.820 ; Rise ; C25M ; -; RA[9] ; C25M ; 13.145 ; 13.145 ; Rise ; C25M ; -; RA[10] ; C25M ; 12.352 ; 12.352 ; Rise ; C25M ; -; RA[11] ; C25M ; 12.575 ; 12.575 ; Rise ; C25M ; -; RA[12] ; C25M ; 10.684 ; 10.684 ; Rise ; C25M ; -; RA[13] ; C25M ; 11.303 ; 11.303 ; Rise ; C25M ; -; RA[14] ; C25M ; 11.601 ; 11.601 ; Rise ; C25M ; -; RA[15] ; C25M ; 11.467 ; 11.467 ; Rise ; C25M ; -; RD[*] ; C25M ; 6.155 ; 6.155 ; Rise ; C25M ; -; RD[0] ; C25M ; 3.995 ; 3.995 ; Rise ; C25M ; -; RD[1] ; C25M ; 4.067 ; 4.067 ; Rise ; C25M ; -; RD[2] ; C25M ; 4.049 ; 4.049 ; Rise ; C25M ; -; RD[3] ; C25M ; 4.540 ; 4.540 ; Rise ; C25M ; -; RD[4] ; C25M ; 4.083 ; 4.083 ; Rise ; C25M ; -; RD[5] ; C25M ; 4.258 ; 4.258 ; Rise ; C25M ; -; RD[6] ; C25M ; 4.044 ; 4.044 ; Rise ; C25M ; -; RD[7] ; C25M ; 6.155 ; 6.155 ; Rise ; C25M ; -; SD[*] ; C25M ; 6.456 ; 6.456 ; Rise ; C25M ; -; SD[0] ; C25M ; 4.006 ; 4.006 ; Rise ; C25M ; -; SD[1] ; C25M ; 4.019 ; 4.019 ; Rise ; C25M ; -; SD[2] ; C25M ; 3.688 ; 3.688 ; Rise ; C25M ; -; SD[3] ; C25M ; 5.362 ; 5.362 ; Rise ; C25M ; -; SD[4] ; C25M ; 6.456 ; 6.456 ; Rise ; C25M ; -; SD[5] ; C25M ; 5.261 ; 5.261 ; Rise ; C25M ; -; SD[6] ; C25M ; 4.435 ; 4.435 ; Rise ; C25M ; -; SD[7] ; C25M ; 4.250 ; 4.250 ; Rise ; C25M ; -; nDEVSEL ; C25M ; 7.656 ; 7.656 ; Rise ; C25M ; -; nIOSEL ; C25M ; 4.029 ; 4.029 ; Rise ; C25M ; -; nIOSTRB ; C25M ; 7.314 ; 7.314 ; Rise ; C25M ; -; nRES ; C25M ; 4.265 ; 4.265 ; Rise ; C25M ; -; RA[*] ; PHI0 ; 5.399 ; 5.399 ; Rise ; PHI0 ; -; RA[0] ; PHI0 ; 1.137 ; 1.137 ; Rise ; PHI0 ; -; RA[1] ; PHI0 ; 1.471 ; 1.471 ; Rise ; PHI0 ; -; RA[2] ; PHI0 ; 3.056 ; 3.056 ; Rise ; PHI0 ; -; RA[3] ; PHI0 ; 4.283 ; 4.283 ; Rise ; PHI0 ; -; RA[7] ; PHI0 ; 3.449 ; 3.449 ; Rise ; PHI0 ; -; RA[8] ; PHI0 ; 5.074 ; 5.074 ; Rise ; PHI0 ; -; RA[9] ; PHI0 ; 5.399 ; 5.399 ; Rise ; PHI0 ; -; RA[10] ; PHI0 ; 4.606 ; 4.606 ; Rise ; PHI0 ; -; RA[11] ; PHI0 ; 4.829 ; 4.829 ; Rise ; PHI0 ; -; RA[12] ; PHI0 ; 3.556 ; 3.556 ; Rise ; PHI0 ; -; RA[13] ; PHI0 ; 4.175 ; 4.175 ; Rise ; PHI0 ; -; RA[14] ; PHI0 ; 4.473 ; 4.473 ; Rise ; PHI0 ; -; RA[15] ; PHI0 ; 4.339 ; 4.339 ; Rise ; PHI0 ; -; nWE ; PHI0 ; 1.302 ; 1.302 ; Rise ; PHI0 ; +; MISO ; C25M ; 4.861 ; 4.861 ; Rise ; C25M ; +; MOSI ; C25M ; 5.054 ; 5.054 ; Rise ; C25M ; +; PHI0 ; C25M ; 2.072 ; 2.072 ; Rise ; C25M ; +; RA[*] ; C25M ; 13.938 ; 13.938 ; Rise ; C25M ; +; RA[0] ; C25M ; 8.513 ; 8.513 ; Rise ; C25M ; +; RA[1] ; C25M ; 8.082 ; 8.082 ; Rise ; C25M ; +; RA[2] ; C25M ; 8.927 ; 8.927 ; Rise ; C25M ; +; RA[3] ; C25M ; 9.459 ; 9.459 ; Rise ; C25M ; +; RA[4] ; C25M ; 6.718 ; 6.718 ; Rise ; C25M ; +; RA[5] ; C25M ; 8.293 ; 8.293 ; Rise ; C25M ; +; RA[6] ; C25M ; 6.561 ; 6.561 ; Rise ; C25M ; +; RA[7] ; C25M ; 11.859 ; 11.859 ; Rise ; C25M ; +; RA[8] ; C25M ; 12.000 ; 12.000 ; Rise ; C25M ; +; RA[9] ; C25M ; 12.068 ; 12.068 ; Rise ; C25M ; +; RA[10] ; C25M ; 13.578 ; 13.578 ; Rise ; C25M ; +; RA[11] ; C25M ; 13.170 ; 13.170 ; Rise ; C25M ; +; RA[12] ; C25M ; 13.525 ; 13.525 ; Rise ; C25M ; +; RA[13] ; C25M ; 13.254 ; 13.254 ; Rise ; C25M ; +; RA[14] ; C25M ; 13.903 ; 13.903 ; Rise ; C25M ; +; RA[15] ; C25M ; 13.938 ; 13.938 ; Rise ; C25M ; +; RD[*] ; C25M ; 6.255 ; 6.255 ; Rise ; C25M ; +; RD[0] ; C25M ; 5.390 ; 5.390 ; Rise ; C25M ; +; RD[1] ; C25M ; 5.017 ; 5.017 ; Rise ; C25M ; +; RD[2] ; C25M ; 4.088 ; 4.088 ; Rise ; C25M ; +; RD[3] ; C25M ; 4.968 ; 4.968 ; Rise ; C25M ; +; RD[4] ; C25M ; 4.673 ; 4.673 ; Rise ; C25M ; +; RD[5] ; C25M ; 5.287 ; 5.287 ; Rise ; C25M ; +; RD[6] ; C25M ; 3.485 ; 3.485 ; Rise ; C25M ; +; RD[7] ; C25M ; 6.255 ; 6.255 ; Rise ; C25M ; +; SD[*] ; C25M ; 7.093 ; 7.093 ; Rise ; C25M ; +; SD[0] ; C25M ; 5.171 ; 5.171 ; Rise ; C25M ; +; SD[1] ; C25M ; 4.574 ; 4.574 ; Rise ; C25M ; +; SD[2] ; C25M ; 3.868 ; 3.868 ; Rise ; C25M ; +; SD[3] ; C25M ; 7.093 ; 7.093 ; Rise ; C25M ; +; SD[4] ; C25M ; 5.421 ; 5.421 ; Rise ; C25M ; +; SD[5] ; C25M ; 4.486 ; 4.486 ; Rise ; C25M ; +; SD[6] ; C25M ; 5.447 ; 5.447 ; Rise ; C25M ; +; SD[7] ; C25M ; 4.770 ; 4.770 ; Rise ; C25M ; +; nDEVSEL ; C25M ; 9.132 ; 9.132 ; Rise ; C25M ; +; nIOSEL ; C25M ; 7.291 ; 7.291 ; Rise ; C25M ; +; nRES ; C25M ; 3.835 ; 3.835 ; Rise ; C25M ; +; RA[*] ; PHI0 ; 5.752 ; 5.752 ; Rise ; PHI0 ; +; RA[0] ; PHI0 ; 2.416 ; 2.416 ; Rise ; PHI0 ; +; RA[1] ; PHI0 ; 1.738 ; 1.738 ; Rise ; PHI0 ; +; RA[2] ; PHI0 ; 2.742 ; 2.742 ; Rise ; PHI0 ; +; RA[3] ; PHI0 ; 3.681 ; 3.681 ; Rise ; PHI0 ; +; RA[7] ; PHI0 ; 3.673 ; 3.673 ; Rise ; PHI0 ; +; RA[8] ; PHI0 ; 3.814 ; 3.814 ; Rise ; PHI0 ; +; RA[9] ; PHI0 ; 3.882 ; 3.882 ; Rise ; PHI0 ; +; RA[10] ; PHI0 ; 5.392 ; 5.392 ; Rise ; PHI0 ; +; RA[11] ; PHI0 ; 4.984 ; 4.984 ; Rise ; PHI0 ; +; RA[12] ; PHI0 ; 5.339 ; 5.339 ; Rise ; PHI0 ; +; RA[13] ; PHI0 ; 5.068 ; 5.068 ; Rise ; PHI0 ; +; RA[14] ; PHI0 ; 5.717 ; 5.717 ; Rise ; PHI0 ; +; RA[15] ; PHI0 ; 5.752 ; 5.752 ; Rise ; PHI0 ; +; nWE ; PHI0 ; 1.031 ; 1.031 ; Rise ; PHI0 ; +-----------+------------+--------+--------+------------+-----------------+ @@ -675,63 +672,62 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-----------+------------+--------+--------+------------+-----------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+--------+--------+------------+-----------------+ -; MISO ; C25M ; -3.532 ; -3.532 ; Rise ; C25M ; -; MOSI ; C25M ; -3.602 ; -3.602 ; Rise ; C25M ; -; PHI0 ; C25M ; -1.453 ; -1.453 ; Rise ; C25M ; -; RA[*] ; C25M ; -3.814 ; -3.814 ; Rise ; C25M ; -; RA[0] ; C25M ; -4.347 ; -4.347 ; Rise ; C25M ; -; RA[1] ; C25M ; -3.814 ; -3.814 ; Rise ; C25M ; -; RA[2] ; C25M ; -3.955 ; -3.955 ; Rise ; C25M ; -; RA[3] ; C25M ; -6.045 ; -6.045 ; Rise ; C25M ; -; RA[4] ; C25M ; -5.238 ; -5.238 ; Rise ; C25M ; -; RA[5] ; C25M ; -6.852 ; -6.852 ; Rise ; C25M ; -; RA[6] ; C25M ; -6.391 ; -6.391 ; Rise ; C25M ; -; RA[7] ; C25M ; -5.654 ; -5.654 ; Rise ; C25M ; -; RA[8] ; C25M ; -5.683 ; -5.683 ; Rise ; C25M ; -; RA[9] ; C25M ; -5.667 ; -5.667 ; Rise ; C25M ; -; RA[10] ; C25M ; -5.110 ; -5.110 ; Rise ; C25M ; -; RA[11] ; C25M ; -4.902 ; -4.902 ; Rise ; C25M ; -; RA[12] ; C25M ; -7.857 ; -7.857 ; Rise ; C25M ; -; RA[13] ; C25M ; -8.476 ; -8.476 ; Rise ; C25M ; -; RA[14] ; C25M ; -8.774 ; -8.774 ; Rise ; C25M ; -; RA[15] ; C25M ; -8.640 ; -8.640 ; Rise ; C25M ; -; RD[*] ; C25M ; -1.834 ; -1.834 ; Rise ; C25M ; -; RD[0] ; C25M ; -2.186 ; -2.186 ; Rise ; C25M ; -; RD[1] ; C25M ; -2.114 ; -2.114 ; Rise ; C25M ; -; RD[2] ; C25M ; -2.096 ; -2.096 ; Rise ; C25M ; -; RD[3] ; C25M ; -2.111 ; -2.111 ; Rise ; C25M ; -; RD[4] ; C25M ; -2.085 ; -2.085 ; Rise ; C25M ; -; RD[5] ; C25M ; -2.079 ; -2.079 ; Rise ; C25M ; -; RD[6] ; C25M ; -1.861 ; -1.861 ; Rise ; C25M ; -; RD[7] ; C25M ; -1.834 ; -1.834 ; Rise ; C25M ; -; SD[*] ; C25M ; -3.134 ; -3.134 ; Rise ; C25M ; -; SD[0] ; C25M ; -3.452 ; -3.452 ; Rise ; C25M ; -; SD[1] ; C25M ; -3.465 ; -3.465 ; Rise ; C25M ; -; SD[2] ; C25M ; -3.134 ; -3.134 ; Rise ; C25M ; -; SD[3] ; C25M ; -4.808 ; -4.808 ; Rise ; C25M ; -; SD[4] ; C25M ; -5.902 ; -5.902 ; Rise ; C25M ; -; SD[5] ; C25M ; -4.707 ; -4.707 ; Rise ; C25M ; -; SD[6] ; C25M ; -3.881 ; -3.881 ; Rise ; C25M ; -; SD[7] ; C25M ; -3.696 ; -3.696 ; Rise ; C25M ; -; nDEVSEL ; C25M ; -2.655 ; -2.655 ; Rise ; C25M ; -; nIOSEL ; C25M ; -2.809 ; -2.809 ; Rise ; C25M ; -; nIOSTRB ; C25M ; -6.729 ; -6.729 ; Rise ; C25M ; -; nRES ; C25M ; -3.711 ; -3.711 ; Rise ; C25M ; -; RA[*] ; PHI0 ; -0.515 ; -0.515 ; Rise ; PHI0 ; -; RA[0] ; PHI0 ; -0.583 ; -0.583 ; Rise ; PHI0 ; -; RA[1] ; PHI0 ; -0.917 ; -0.917 ; Rise ; PHI0 ; -; RA[2] ; PHI0 ; -2.502 ; -2.502 ; Rise ; PHI0 ; -; RA[3] ; PHI0 ; -3.729 ; -3.729 ; Rise ; PHI0 ; -; RA[7] ; PHI0 ; -2.895 ; -2.895 ; Rise ; PHI0 ; -; RA[8] ; PHI0 ; -2.728 ; -2.728 ; Rise ; PHI0 ; -; RA[9] ; PHI0 ; -3.053 ; -3.053 ; Rise ; PHI0 ; -; RA[10] ; PHI0 ; -2.260 ; -2.260 ; Rise ; PHI0 ; -; RA[11] ; PHI0 ; -0.515 ; -0.515 ; Rise ; PHI0 ; -; RA[12] ; PHI0 ; -2.384 ; -2.384 ; Rise ; PHI0 ; -; RA[13] ; PHI0 ; -3.003 ; -3.003 ; Rise ; PHI0 ; -; RA[14] ; PHI0 ; -3.301 ; -3.301 ; Rise ; PHI0 ; -; RA[15] ; PHI0 ; -3.167 ; -3.167 ; Rise ; PHI0 ; -; nWE ; PHI0 ; 0.063 ; 0.063 ; Rise ; PHI0 ; +; MISO ; C25M ; -4.307 ; -4.307 ; Rise ; C25M ; +; MOSI ; C25M ; -4.500 ; -4.500 ; Rise ; C25M ; +; PHI0 ; C25M ; -1.518 ; -1.518 ; Rise ; C25M ; +; RA[*] ; C25M ; -4.651 ; -4.651 ; Rise ; C25M ; +; RA[0] ; C25M ; -4.868 ; -4.868 ; Rise ; C25M ; +; RA[1] ; C25M ; -4.755 ; -4.755 ; Rise ; C25M ; +; RA[2] ; C25M ; -4.651 ; -4.651 ; Rise ; C25M ; +; RA[3] ; C25M ; -5.587 ; -5.587 ; Rise ; C25M ; +; RA[4] ; C25M ; -6.164 ; -6.164 ; Rise ; C25M ; +; RA[5] ; C25M ; -7.739 ; -7.739 ; Rise ; C25M ; +; RA[6] ; C25M ; -6.007 ; -6.007 ; Rise ; C25M ; +; RA[7] ; C25M ; -7.911 ; -7.911 ; Rise ; C25M ; +; RA[8] ; C25M ; -5.340 ; -5.340 ; Rise ; C25M ; +; RA[9] ; C25M ; -5.100 ; -5.100 ; Rise ; C25M ; +; RA[10] ; C25M ; -5.525 ; -5.525 ; Rise ; C25M ; +; RA[11] ; C25M ; -6.207 ; -6.207 ; Rise ; C25M ; +; RA[12] ; C25M ; -9.577 ; -9.577 ; Rise ; C25M ; +; RA[13] ; C25M ; -9.306 ; -9.306 ; Rise ; C25M ; +; RA[14] ; C25M ; -9.955 ; -9.955 ; Rise ; C25M ; +; RA[15] ; C25M ; -9.990 ; -9.990 ; Rise ; C25M ; +; RD[*] ; C25M ; -2.060 ; -2.060 ; Rise ; C25M ; +; RD[0] ; C25M ; -2.698 ; -2.698 ; Rise ; C25M ; +; RD[1] ; C25M ; -2.624 ; -2.624 ; Rise ; C25M ; +; RD[2] ; C25M ; -2.734 ; -2.734 ; Rise ; C25M ; +; RD[3] ; C25M ; -2.609 ; -2.609 ; Rise ; C25M ; +; RD[4] ; C25M ; -2.625 ; -2.625 ; Rise ; C25M ; +; RD[5] ; C25M ; -2.663 ; -2.663 ; Rise ; C25M ; +; RD[6] ; C25M ; -2.060 ; -2.060 ; Rise ; C25M ; +; RD[7] ; C25M ; -2.167 ; -2.167 ; Rise ; C25M ; +; SD[*] ; C25M ; -3.314 ; -3.314 ; Rise ; C25M ; +; SD[0] ; C25M ; -4.617 ; -4.617 ; Rise ; C25M ; +; SD[1] ; C25M ; -4.020 ; -4.020 ; Rise ; C25M ; +; SD[2] ; C25M ; -3.314 ; -3.314 ; Rise ; C25M ; +; SD[3] ; C25M ; -6.539 ; -6.539 ; Rise ; C25M ; +; SD[4] ; C25M ; -4.867 ; -4.867 ; Rise ; C25M ; +; SD[5] ; C25M ; -3.932 ; -3.932 ; Rise ; C25M ; +; SD[6] ; C25M ; -4.893 ; -4.893 ; Rise ; C25M ; +; SD[7] ; C25M ; -4.216 ; -4.216 ; Rise ; C25M ; +; nDEVSEL ; C25M ; -3.398 ; -3.398 ; Rise ; C25M ; +; nIOSEL ; C25M ; -6.712 ; -6.712 ; Rise ; C25M ; +; nRES ; C25M ; -3.281 ; -3.281 ; Rise ; C25M ; +; RA[*] ; PHI0 ; -1.124 ; -1.124 ; Rise ; PHI0 ; +; RA[0] ; PHI0 ; -1.862 ; -1.862 ; Rise ; PHI0 ; +; RA[1] ; PHI0 ; -1.184 ; -1.184 ; Rise ; PHI0 ; +; RA[2] ; PHI0 ; -2.188 ; -2.188 ; Rise ; PHI0 ; +; RA[3] ; PHI0 ; -3.127 ; -3.127 ; Rise ; PHI0 ; +; RA[7] ; PHI0 ; -3.119 ; -3.119 ; Rise ; PHI0 ; +; RA[8] ; PHI0 ; -1.376 ; -1.376 ; Rise ; PHI0 ; +; RA[9] ; PHI0 ; -1.444 ; -1.444 ; Rise ; PHI0 ; +; RA[10] ; PHI0 ; -2.954 ; -2.954 ; Rise ; PHI0 ; +; RA[11] ; PHI0 ; -1.124 ; -1.124 ; Rise ; PHI0 ; +; RA[12] ; PHI0 ; -3.628 ; -3.628 ; Rise ; PHI0 ; +; RA[13] ; PHI0 ; -3.357 ; -3.357 ; Rise ; PHI0 ; +; RA[14] ; PHI0 ; -4.006 ; -4.006 ; Rise ; PHI0 ; +; RA[15] ; PHI0 ; -4.041 ; -4.041 ; Rise ; PHI0 ; +; nWE ; PHI0 ; 0.091 ; 0.091 ; Rise ; PHI0 ; +-----------+------------+--------+--------+------------+-----------------+ @@ -740,113 +736,113 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-----------+------------+--------+--------+------------+-----------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+--------+--------+------------+-----------------+ -; DQMH ; C25M ; 8.310 ; 8.310 ; Rise ; C25M ; -; DQML ; C25M ; 9.180 ; 9.180 ; Rise ; C25M ; -; FCK ; C25M ; 7.598 ; 7.598 ; Rise ; C25M ; -; MOSI ; C25M ; 8.176 ; 8.176 ; Rise ; C25M ; -; RCKE ; C25M ; 9.862 ; 9.862 ; Rise ; C25M ; -; RD[*] ; C25M ; 9.363 ; 9.363 ; Rise ; C25M ; -; RD[0] ; C25M ; 9.246 ; 9.246 ; Rise ; C25M ; -; RD[1] ; C25M ; 8.959 ; 8.959 ; Rise ; C25M ; -; RD[2] ; C25M ; 8.827 ; 8.827 ; Rise ; C25M ; -; RD[3] ; C25M ; 8.971 ; 8.971 ; Rise ; C25M ; -; RD[4] ; C25M ; 8.952 ; 8.952 ; Rise ; C25M ; -; RD[5] ; C25M ; 9.363 ; 9.363 ; Rise ; C25M ; -; RD[6] ; C25M ; 8.359 ; 8.359 ; Rise ; C25M ; -; RD[7] ; C25M ; 8.563 ; 8.563 ; Rise ; C25M ; -; RDdir ; C25M ; 13.177 ; 13.177 ; Rise ; C25M ; -; SA[*] ; C25M ; 9.935 ; 9.935 ; Rise ; C25M ; -; SA[0] ; C25M ; 8.125 ; 8.125 ; Rise ; C25M ; -; SA[1] ; C25M ; 8.251 ; 8.251 ; Rise ; C25M ; -; SA[2] ; C25M ; 8.098 ; 8.098 ; Rise ; C25M ; -; SA[3] ; C25M ; 9.041 ; 9.041 ; Rise ; C25M ; -; SA[4] ; C25M ; 8.815 ; 8.815 ; Rise ; C25M ; -; SA[5] ; C25M ; 8.336 ; 8.336 ; Rise ; C25M ; -; SA[6] ; C25M ; 8.314 ; 8.314 ; Rise ; C25M ; -; SA[7] ; C25M ; 8.312 ; 8.312 ; Rise ; C25M ; -; SA[8] ; C25M ; 8.938 ; 8.938 ; Rise ; C25M ; -; SA[9] ; C25M ; 9.480 ; 9.480 ; Rise ; C25M ; -; SA[10] ; C25M ; 8.331 ; 8.331 ; Rise ; C25M ; -; SA[11] ; C25M ; 9.935 ; 9.935 ; Rise ; C25M ; -; SA[12] ; C25M ; 8.717 ; 8.717 ; Rise ; C25M ; -; SBA[*] ; C25M ; 8.878 ; 8.878 ; Rise ; C25M ; -; SBA[0] ; C25M ; 8.878 ; 8.878 ; Rise ; C25M ; -; SBA[1] ; C25M ; 8.389 ; 8.389 ; Rise ; C25M ; -; SD[*] ; C25M ; 8.159 ; 8.159 ; Rise ; C25M ; -; SD[0] ; C25M ; 6.937 ; 6.937 ; Rise ; C25M ; -; SD[1] ; C25M ; 8.052 ; 8.052 ; Rise ; C25M ; -; SD[2] ; C25M ; 8.159 ; 8.159 ; Rise ; C25M ; -; SD[3] ; C25M ; 6.924 ; 6.924 ; Rise ; C25M ; -; SD[4] ; C25M ; 8.143 ; 8.143 ; Rise ; C25M ; -; SD[5] ; C25M ; 6.944 ; 6.944 ; Rise ; C25M ; -; SD[6] ; C25M ; 7.570 ; 7.570 ; Rise ; C25M ; -; SD[7] ; C25M ; 7.576 ; 7.576 ; Rise ; C25M ; -; nCAS ; C25M ; 8.009 ; 8.009 ; Rise ; C25M ; -; nFCS ; C25M ; 7.588 ; 7.588 ; Rise ; C25M ; -; nRAS ; C25M ; 6.944 ; 6.944 ; Rise ; C25M ; -; nRCS ; C25M ; 8.737 ; 8.737 ; Rise ; C25M ; -; nRESout ; C25M ; 8.496 ; 8.496 ; Rise ; C25M ; -; nSWE ; C25M ; 8.362 ; 8.362 ; Rise ; C25M ; -; RDdir ; PHI0 ; 8.885 ; 8.885 ; Rise ; PHI0 ; -; RDdir ; PHI0 ; 8.885 ; 8.885 ; Fall ; PHI0 ; +; DQMH ; C25M ; 8.306 ; 8.306 ; Rise ; C25M ; +; DQML ; C25M ; 8.935 ; 8.935 ; Rise ; C25M ; +; FCK ; C25M ; 8.986 ; 8.986 ; Rise ; C25M ; +; MOSI ; C25M ; 8.773 ; 8.773 ; Rise ; C25M ; +; RCKE ; C25M ; 9.311 ; 9.311 ; Rise ; C25M ; +; RD[*] ; C25M ; 9.599 ; 9.599 ; Rise ; C25M ; +; RD[0] ; C25M ; 8.289 ; 8.289 ; Rise ; C25M ; +; RD[1] ; C25M ; 8.191 ; 8.191 ; Rise ; C25M ; +; RD[2] ; C25M ; 8.316 ; 8.316 ; Rise ; C25M ; +; RD[3] ; C25M ; 9.599 ; 9.599 ; Rise ; C25M ; +; RD[4] ; C25M ; 8.790 ; 8.790 ; Rise ; C25M ; +; RD[5] ; C25M ; 8.643 ; 8.643 ; Rise ; C25M ; +; RD[6] ; C25M ; 8.747 ; 8.747 ; Rise ; C25M ; +; RD[7] ; C25M ; 8.857 ; 8.857 ; Rise ; C25M ; +; RDdir ; C25M ; 14.351 ; 14.351 ; Rise ; C25M ; +; SA[*] ; C25M ; 8.845 ; 8.845 ; Rise ; C25M ; +; SA[0] ; C25M ; 8.193 ; 8.193 ; Rise ; C25M ; +; SA[1] ; C25M ; 8.141 ; 8.141 ; Rise ; C25M ; +; SA[2] ; C25M ; 8.105 ; 8.105 ; Rise ; C25M ; +; SA[3] ; C25M ; 8.558 ; 8.558 ; Rise ; C25M ; +; SA[4] ; C25M ; 8.552 ; 8.552 ; Rise ; C25M ; +; SA[5] ; C25M ; 8.678 ; 8.678 ; Rise ; C25M ; +; SA[6] ; C25M ; 8.540 ; 8.540 ; Rise ; C25M ; +; SA[7] ; C25M ; 8.566 ; 8.566 ; Rise ; C25M ; +; SA[8] ; C25M ; 8.225 ; 8.225 ; Rise ; C25M ; +; SA[9] ; C25M ; 8.043 ; 8.043 ; Rise ; C25M ; +; SA[10] ; C25M ; 8.058 ; 8.058 ; Rise ; C25M ; +; SA[11] ; C25M ; 7.991 ; 7.991 ; Rise ; C25M ; +; SA[12] ; C25M ; 8.845 ; 8.845 ; Rise ; C25M ; +; SBA[*] ; C25M ; 8.866 ; 8.866 ; Rise ; C25M ; +; SBA[0] ; C25M ; 8.821 ; 8.821 ; Rise ; C25M ; +; SBA[1] ; C25M ; 8.866 ; 8.866 ; Rise ; C25M ; +; SD[*] ; C25M ; 8.494 ; 8.494 ; Rise ; C25M ; +; SD[0] ; C25M ; 8.488 ; 8.488 ; Rise ; C25M ; +; SD[1] ; C25M ; 8.053 ; 8.053 ; Rise ; C25M ; +; SD[2] ; C25M ; 8.494 ; 8.494 ; Rise ; C25M ; +; SD[3] ; C25M ; 7.584 ; 7.584 ; Rise ; C25M ; +; SD[4] ; C25M ; 8.442 ; 8.442 ; Rise ; C25M ; +; SD[5] ; C25M ; 7.562 ; 7.562 ; Rise ; C25M ; +; SD[6] ; C25M ; 8.445 ; 8.445 ; Rise ; C25M ; +; SD[7] ; C25M ; 6.950 ; 6.950 ; Rise ; C25M ; +; nCAS ; C25M ; 8.325 ; 8.325 ; Rise ; C25M ; +; nFCS ; C25M ; 8.074 ; 8.074 ; Rise ; C25M ; +; nRAS ; C25M ; 8.416 ; 8.416 ; Rise ; C25M ; +; nRCS ; C25M ; 10.070 ; 10.070 ; Rise ; C25M ; +; nRESout ; C25M ; 8.766 ; 8.766 ; Rise ; C25M ; +; nSWE ; C25M ; 9.380 ; 9.380 ; Rise ; C25M ; +; RDdir ; PHI0 ; 10.495 ; 10.495 ; Rise ; PHI0 ; +; RDdir ; PHI0 ; 10.495 ; 10.495 ; Fall ; PHI0 ; +-----------+------------+--------+--------+------------+-----------------+ -+-----------------------------------------------------------------------+ -; Minimum Clock to Output Times ; -+-----------+------------+-------+-------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-----------+------------+-------+-------+------------+-----------------+ -; DQMH ; C25M ; 8.310 ; 8.310 ; Rise ; C25M ; -; DQML ; C25M ; 9.180 ; 9.180 ; Rise ; C25M ; -; FCK ; C25M ; 7.598 ; 7.598 ; Rise ; C25M ; -; MOSI ; C25M ; 8.176 ; 8.176 ; Rise ; C25M ; -; RCKE ; C25M ; 9.862 ; 9.862 ; Rise ; C25M ; -; RD[*] ; C25M ; 8.359 ; 8.359 ; Rise ; C25M ; -; RD[0] ; C25M ; 9.246 ; 9.246 ; Rise ; C25M ; -; RD[1] ; C25M ; 8.959 ; 8.959 ; Rise ; C25M ; -; RD[2] ; C25M ; 8.827 ; 8.827 ; Rise ; C25M ; -; RD[3] ; C25M ; 8.971 ; 8.971 ; Rise ; C25M ; -; RD[4] ; C25M ; 8.952 ; 8.952 ; Rise ; C25M ; -; RD[5] ; C25M ; 9.363 ; 9.363 ; Rise ; C25M ; -; RD[6] ; C25M ; 8.359 ; 8.359 ; Rise ; C25M ; -; RD[7] ; C25M ; 8.563 ; 8.563 ; Rise ; C25M ; -; RDdir ; C25M ; 8.609 ; 8.609 ; Rise ; C25M ; -; SA[*] ; C25M ; 8.098 ; 8.098 ; Rise ; C25M ; -; SA[0] ; C25M ; 8.125 ; 8.125 ; Rise ; C25M ; -; SA[1] ; C25M ; 8.251 ; 8.251 ; Rise ; C25M ; -; SA[2] ; C25M ; 8.098 ; 8.098 ; Rise ; C25M ; -; SA[3] ; C25M ; 9.041 ; 9.041 ; Rise ; C25M ; -; SA[4] ; C25M ; 8.815 ; 8.815 ; Rise ; C25M ; -; SA[5] ; C25M ; 8.336 ; 8.336 ; Rise ; C25M ; -; SA[6] ; C25M ; 8.314 ; 8.314 ; Rise ; C25M ; -; SA[7] ; C25M ; 8.312 ; 8.312 ; Rise ; C25M ; -; SA[8] ; C25M ; 8.938 ; 8.938 ; Rise ; C25M ; -; SA[9] ; C25M ; 9.480 ; 9.480 ; Rise ; C25M ; -; SA[10] ; C25M ; 8.331 ; 8.331 ; Rise ; C25M ; -; SA[11] ; C25M ; 9.935 ; 9.935 ; Rise ; C25M ; -; SA[12] ; C25M ; 8.717 ; 8.717 ; Rise ; C25M ; -; SBA[*] ; C25M ; 8.389 ; 8.389 ; Rise ; C25M ; -; SBA[0] ; C25M ; 8.878 ; 8.878 ; Rise ; C25M ; -; SBA[1] ; C25M ; 8.389 ; 8.389 ; Rise ; C25M ; -; SD[*] ; C25M ; 6.924 ; 6.924 ; Rise ; C25M ; -; SD[0] ; C25M ; 6.937 ; 6.937 ; Rise ; C25M ; -; SD[1] ; C25M ; 8.052 ; 8.052 ; Rise ; C25M ; -; SD[2] ; C25M ; 8.159 ; 8.159 ; Rise ; C25M ; -; SD[3] ; C25M ; 6.924 ; 6.924 ; Rise ; C25M ; -; SD[4] ; C25M ; 8.143 ; 8.143 ; Rise ; C25M ; -; SD[5] ; C25M ; 6.944 ; 6.944 ; Rise ; C25M ; -; SD[6] ; C25M ; 7.570 ; 7.570 ; Rise ; C25M ; -; SD[7] ; C25M ; 7.576 ; 7.576 ; Rise ; C25M ; -; nCAS ; C25M ; 8.009 ; 8.009 ; Rise ; C25M ; -; nFCS ; C25M ; 7.588 ; 7.588 ; Rise ; C25M ; -; nRAS ; C25M ; 6.944 ; 6.944 ; Rise ; C25M ; -; nRCS ; C25M ; 8.737 ; 8.737 ; Rise ; C25M ; -; nRESout ; C25M ; 8.496 ; 8.496 ; Rise ; C25M ; -; nSWE ; C25M ; 8.362 ; 8.362 ; Rise ; C25M ; -; RDdir ; PHI0 ; 8.885 ; 8.885 ; Rise ; PHI0 ; -; RDdir ; PHI0 ; 8.885 ; 8.885 ; Fall ; PHI0 ; -+-----------+------------+-------+-------+------------+-----------------+ ++-------------------------------------------------------------------------+ +; Minimum Clock to Output Times ; ++-----------+------------+--------+--------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+--------+--------+------------+-----------------+ +; DQMH ; C25M ; 8.306 ; 8.306 ; Rise ; C25M ; +; DQML ; C25M ; 8.935 ; 8.935 ; Rise ; C25M ; +; FCK ; C25M ; 8.986 ; 8.986 ; Rise ; C25M ; +; MOSI ; C25M ; 8.773 ; 8.773 ; Rise ; C25M ; +; RCKE ; C25M ; 9.311 ; 9.311 ; Rise ; C25M ; +; RD[*] ; C25M ; 8.191 ; 8.191 ; Rise ; C25M ; +; RD[0] ; C25M ; 8.289 ; 8.289 ; Rise ; C25M ; +; RD[1] ; C25M ; 8.191 ; 8.191 ; Rise ; C25M ; +; RD[2] ; C25M ; 8.316 ; 8.316 ; Rise ; C25M ; +; RD[3] ; C25M ; 9.599 ; 9.599 ; Rise ; C25M ; +; RD[4] ; C25M ; 8.790 ; 8.790 ; Rise ; C25M ; +; RD[5] ; C25M ; 8.643 ; 8.643 ; Rise ; C25M ; +; RD[6] ; C25M ; 8.747 ; 8.747 ; Rise ; C25M ; +; RD[7] ; C25M ; 8.857 ; 8.857 ; Rise ; C25M ; +; RDdir ; C25M ; 9.747 ; 9.747 ; Rise ; C25M ; +; SA[*] ; C25M ; 7.991 ; 7.991 ; Rise ; C25M ; +; SA[0] ; C25M ; 8.193 ; 8.193 ; Rise ; C25M ; +; SA[1] ; C25M ; 8.141 ; 8.141 ; Rise ; C25M ; +; SA[2] ; C25M ; 8.105 ; 8.105 ; Rise ; C25M ; +; SA[3] ; C25M ; 8.558 ; 8.558 ; Rise ; C25M ; +; SA[4] ; C25M ; 8.552 ; 8.552 ; Rise ; C25M ; +; SA[5] ; C25M ; 8.678 ; 8.678 ; Rise ; C25M ; +; SA[6] ; C25M ; 8.540 ; 8.540 ; Rise ; C25M ; +; SA[7] ; C25M ; 8.566 ; 8.566 ; Rise ; C25M ; +; SA[8] ; C25M ; 8.225 ; 8.225 ; Rise ; C25M ; +; SA[9] ; C25M ; 8.043 ; 8.043 ; Rise ; C25M ; +; SA[10] ; C25M ; 8.058 ; 8.058 ; Rise ; C25M ; +; SA[11] ; C25M ; 7.991 ; 7.991 ; Rise ; C25M ; +; SA[12] ; C25M ; 8.845 ; 8.845 ; Rise ; C25M ; +; SBA[*] ; C25M ; 8.821 ; 8.821 ; Rise ; C25M ; +; SBA[0] ; C25M ; 8.821 ; 8.821 ; Rise ; C25M ; +; SBA[1] ; C25M ; 8.866 ; 8.866 ; Rise ; C25M ; +; SD[*] ; C25M ; 6.950 ; 6.950 ; Rise ; C25M ; +; SD[0] ; C25M ; 8.488 ; 8.488 ; Rise ; C25M ; +; SD[1] ; C25M ; 8.053 ; 8.053 ; Rise ; C25M ; +; SD[2] ; C25M ; 8.494 ; 8.494 ; Rise ; C25M ; +; SD[3] ; C25M ; 7.584 ; 7.584 ; Rise ; C25M ; +; SD[4] ; C25M ; 8.442 ; 8.442 ; Rise ; C25M ; +; SD[5] ; C25M ; 7.562 ; 7.562 ; Rise ; C25M ; +; SD[6] ; C25M ; 8.445 ; 8.445 ; Rise ; C25M ; +; SD[7] ; C25M ; 6.950 ; 6.950 ; Rise ; C25M ; +; nCAS ; C25M ; 8.325 ; 8.325 ; Rise ; C25M ; +; nFCS ; C25M ; 8.074 ; 8.074 ; Rise ; C25M ; +; nRAS ; C25M ; 8.416 ; 8.416 ; Rise ; C25M ; +; nRCS ; C25M ; 10.070 ; 10.070 ; Rise ; C25M ; +; nRESout ; C25M ; 8.766 ; 8.766 ; Rise ; C25M ; +; nSWE ; C25M ; 9.380 ; 9.380 ; Rise ; C25M ; +; RDdir ; PHI0 ; 10.495 ; 10.495 ; Rise ; PHI0 ; +; RDdir ; PHI0 ; 10.495 ; 10.495 ; Fall ; PHI0 ; ++-----------+------------+--------+--------+------------+-----------------+ +------------------------------------------------------+ @@ -854,44 +850,44 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +------------+-------------+--------+----+----+--------+ ; Input Port ; Output Port ; RR ; RF ; FR ; FF ; +------------+-------------+--------+----+----+--------+ -; DMAin ; DMAout ; 8.665 ; ; ; 8.665 ; -; INTin ; INTout ; 8.886 ; ; ; 8.886 ; -; nDEVSEL ; RD[0] ; 10.928 ; ; ; 10.928 ; -; nDEVSEL ; RD[1] ; 10.928 ; ; ; 10.928 ; -; nDEVSEL ; RD[2] ; 10.928 ; ; ; 10.928 ; -; nDEVSEL ; RD[3] ; 10.928 ; ; ; 10.928 ; -; nDEVSEL ; RD[4] ; 10.928 ; ; ; 10.928 ; -; nDEVSEL ; RD[5] ; 10.928 ; ; ; 10.928 ; -; nDEVSEL ; RD[6] ; 11.984 ; ; ; 11.984 ; -; nDEVSEL ; RD[7] ; 12.044 ; ; ; 12.044 ; -; nDEVSEL ; RDdir ; 11.832 ; ; ; 11.832 ; -; nIOSEL ; RD[0] ; 11.235 ; ; ; 11.235 ; -; nIOSEL ; RD[1] ; 11.235 ; ; ; 11.235 ; -; nIOSEL ; RD[2] ; 11.235 ; ; ; 11.235 ; -; nIOSEL ; RD[3] ; 11.235 ; ; ; 11.235 ; -; nIOSEL ; RD[4] ; 11.235 ; ; ; 11.235 ; -; nIOSEL ; RD[5] ; 11.235 ; ; ; 11.235 ; -; nIOSEL ; RD[6] ; 12.291 ; ; ; 12.291 ; -; nIOSEL ; RD[7] ; 12.351 ; ; ; 12.351 ; -; nIOSEL ; RDdir ; 12.139 ; ; ; 12.139 ; -; nIOSTRB ; RD[0] ; 11.109 ; ; ; 11.109 ; -; nIOSTRB ; RD[1] ; 11.109 ; ; ; 11.109 ; -; nIOSTRB ; RD[2] ; 11.109 ; ; ; 11.109 ; -; nIOSTRB ; RD[3] ; 11.109 ; ; ; 11.109 ; -; nIOSTRB ; RD[4] ; 11.109 ; ; ; 11.109 ; -; nIOSTRB ; RD[5] ; 11.109 ; ; ; 11.109 ; -; nIOSTRB ; RD[6] ; 12.165 ; ; ; 12.165 ; -; nIOSTRB ; RD[7] ; 12.225 ; ; ; 12.225 ; -; nIOSTRB ; RDdir ; 12.013 ; ; ; 12.013 ; -; nWE ; RD[0] ; 10.077 ; ; ; 10.077 ; -; nWE ; RD[1] ; 10.077 ; ; ; 10.077 ; -; nWE ; RD[2] ; 10.077 ; ; ; 10.077 ; -; nWE ; RD[3] ; 10.077 ; ; ; 10.077 ; -; nWE ; RD[4] ; 10.077 ; ; ; 10.077 ; -; nWE ; RD[5] ; 10.077 ; ; ; 10.077 ; -; nWE ; RD[6] ; 11.133 ; ; ; 11.133 ; -; nWE ; RD[7] ; 11.193 ; ; ; 11.193 ; -; nWE ; RDdir ; 10.981 ; ; ; 10.981 ; +; DMAin ; DMAout ; 8.238 ; ; ; 8.238 ; +; INTin ; INTout ; 9.741 ; ; ; 9.741 ; +; nDEVSEL ; RD[0] ; 13.931 ; ; ; 13.931 ; +; nDEVSEL ; RD[1] ; 13.931 ; ; ; 13.931 ; +; nDEVSEL ; RD[2] ; 13.931 ; ; ; 13.931 ; +; nDEVSEL ; RD[3] ; 13.932 ; ; ; 13.932 ; +; nDEVSEL ; RD[4] ; 13.932 ; ; ; 13.932 ; +; nDEVSEL ; RD[5] ; 13.932 ; ; ; 13.932 ; +; nDEVSEL ; RD[6] ; 13.367 ; ; ; 13.367 ; +; nDEVSEL ; RD[7] ; 13.367 ; ; ; 13.367 ; +; nDEVSEL ; RDdir ; 14.924 ; ; ; 14.924 ; +; nIOSEL ; RD[0] ; 13.917 ; ; ; 13.917 ; +; nIOSEL ; RD[1] ; 13.917 ; ; ; 13.917 ; +; nIOSEL ; RD[2] ; 13.917 ; ; ; 13.917 ; +; nIOSEL ; RD[3] ; 13.918 ; ; ; 13.918 ; +; nIOSEL ; RD[4] ; 13.918 ; ; ; 13.918 ; +; nIOSEL ; RD[5] ; 13.918 ; ; ; 13.918 ; +; nIOSEL ; RD[6] ; 13.353 ; ; ; 13.353 ; +; nIOSEL ; RD[7] ; 13.353 ; ; ; 13.353 ; +; nIOSEL ; RDdir ; 14.910 ; ; ; 14.910 ; +; nIOSTRB ; RD[0] ; 13.766 ; ; ; 13.766 ; +; nIOSTRB ; RD[1] ; 13.766 ; ; ; 13.766 ; +; nIOSTRB ; RD[2] ; 13.766 ; ; ; 13.766 ; +; nIOSTRB ; RD[3] ; 13.767 ; ; ; 13.767 ; +; nIOSTRB ; RD[4] ; 13.767 ; ; ; 13.767 ; +; nIOSTRB ; RD[5] ; 13.767 ; ; ; 13.767 ; +; nIOSTRB ; RD[6] ; 13.202 ; ; ; 13.202 ; +; nIOSTRB ; RD[7] ; 13.202 ; ; ; 13.202 ; +; nIOSTRB ; RDdir ; 14.759 ; ; ; 14.759 ; +; nWE ; RD[0] ; 11.850 ; ; ; 11.850 ; +; nWE ; RD[1] ; 11.850 ; ; ; 11.850 ; +; nWE ; RD[2] ; 11.850 ; ; ; 11.850 ; +; nWE ; RD[3] ; 11.851 ; ; ; 11.851 ; +; nWE ; RD[4] ; 11.851 ; ; ; 11.851 ; +; nWE ; RD[5] ; 11.851 ; ; ; 11.851 ; +; nWE ; RD[6] ; 11.286 ; ; ; 11.286 ; +; nWE ; RD[7] ; 11.286 ; ; ; 11.286 ; +; nWE ; RDdir ; 12.843 ; ; ; 12.843 ; +------------+-------------+--------+----+----+--------+ @@ -900,44 +896,44 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +------------+-------------+--------+----+----+--------+ ; Input Port ; Output Port ; RR ; RF ; FR ; FF ; +------------+-------------+--------+----+----+--------+ -; DMAin ; DMAout ; 8.665 ; ; ; 8.665 ; -; INTin ; INTout ; 8.886 ; ; ; 8.886 ; -; nDEVSEL ; RD[0] ; 10.928 ; ; ; 10.928 ; -; nDEVSEL ; RD[1] ; 10.928 ; ; ; 10.928 ; -; nDEVSEL ; RD[2] ; 10.928 ; ; ; 10.928 ; -; nDEVSEL ; RD[3] ; 10.928 ; ; ; 10.928 ; -; nDEVSEL ; RD[4] ; 10.928 ; ; ; 10.928 ; -; nDEVSEL ; RD[5] ; 10.928 ; ; ; 10.928 ; -; nDEVSEL ; RD[6] ; 11.984 ; ; ; 11.984 ; -; nDEVSEL ; RD[7] ; 12.044 ; ; ; 12.044 ; -; nDEVSEL ; RDdir ; 11.832 ; ; ; 11.832 ; -; nIOSEL ; RD[0] ; 11.235 ; ; ; 11.235 ; -; nIOSEL ; RD[1] ; 11.235 ; ; ; 11.235 ; -; nIOSEL ; RD[2] ; 11.235 ; ; ; 11.235 ; -; nIOSEL ; RD[3] ; 11.235 ; ; ; 11.235 ; -; nIOSEL ; RD[4] ; 11.235 ; ; ; 11.235 ; -; nIOSEL ; RD[5] ; 11.235 ; ; ; 11.235 ; -; nIOSEL ; RD[6] ; 12.291 ; ; ; 12.291 ; -; nIOSEL ; RD[7] ; 12.351 ; ; ; 12.351 ; -; nIOSEL ; RDdir ; 12.139 ; ; ; 12.139 ; -; nIOSTRB ; RD[0] ; 11.109 ; ; ; 11.109 ; -; nIOSTRB ; RD[1] ; 11.109 ; ; ; 11.109 ; -; nIOSTRB ; RD[2] ; 11.109 ; ; ; 11.109 ; -; nIOSTRB ; RD[3] ; 11.109 ; ; ; 11.109 ; -; nIOSTRB ; RD[4] ; 11.109 ; ; ; 11.109 ; -; nIOSTRB ; RD[5] ; 11.109 ; ; ; 11.109 ; -; nIOSTRB ; RD[6] ; 12.165 ; ; ; 12.165 ; -; nIOSTRB ; RD[7] ; 12.225 ; ; ; 12.225 ; -; nIOSTRB ; RDdir ; 12.013 ; ; ; 12.013 ; -; nWE ; RD[0] ; 10.077 ; ; ; 10.077 ; -; nWE ; RD[1] ; 10.077 ; ; ; 10.077 ; -; nWE ; RD[2] ; 10.077 ; ; ; 10.077 ; -; nWE ; RD[3] ; 10.077 ; ; ; 10.077 ; -; nWE ; RD[4] ; 10.077 ; ; ; 10.077 ; -; nWE ; RD[5] ; 10.077 ; ; ; 10.077 ; -; nWE ; RD[6] ; 11.133 ; ; ; 11.133 ; -; nWE ; RD[7] ; 11.193 ; ; ; 11.193 ; -; nWE ; RDdir ; 10.981 ; ; ; 10.981 ; +; DMAin ; DMAout ; 8.238 ; ; ; 8.238 ; +; INTin ; INTout ; 9.741 ; ; ; 9.741 ; +; nDEVSEL ; RD[0] ; 13.931 ; ; ; 13.931 ; +; nDEVSEL ; RD[1] ; 13.931 ; ; ; 13.931 ; +; nDEVSEL ; RD[2] ; 13.931 ; ; ; 13.931 ; +; nDEVSEL ; RD[3] ; 13.932 ; ; ; 13.932 ; +; nDEVSEL ; RD[4] ; 13.932 ; ; ; 13.932 ; +; nDEVSEL ; RD[5] ; 13.932 ; ; ; 13.932 ; +; nDEVSEL ; RD[6] ; 13.367 ; ; ; 13.367 ; +; nDEVSEL ; RD[7] ; 13.367 ; ; ; 13.367 ; +; nDEVSEL ; RDdir ; 14.924 ; ; ; 14.924 ; +; nIOSEL ; RD[0] ; 13.917 ; ; ; 13.917 ; +; nIOSEL ; RD[1] ; 13.917 ; ; ; 13.917 ; +; nIOSEL ; RD[2] ; 13.917 ; ; ; 13.917 ; +; nIOSEL ; RD[3] ; 13.918 ; ; ; 13.918 ; +; nIOSEL ; RD[4] ; 13.918 ; ; ; 13.918 ; +; nIOSEL ; RD[5] ; 13.918 ; ; ; 13.918 ; +; nIOSEL ; RD[6] ; 13.353 ; ; ; 13.353 ; +; nIOSEL ; RD[7] ; 13.353 ; ; ; 13.353 ; +; nIOSEL ; RDdir ; 14.910 ; ; ; 14.910 ; +; nIOSTRB ; RD[0] ; 13.766 ; ; ; 13.766 ; +; nIOSTRB ; RD[1] ; 13.766 ; ; ; 13.766 ; +; nIOSTRB ; RD[2] ; 13.766 ; ; ; 13.766 ; +; nIOSTRB ; RD[3] ; 13.767 ; ; ; 13.767 ; +; nIOSTRB ; RD[4] ; 13.767 ; ; ; 13.767 ; +; nIOSTRB ; RD[5] ; 13.767 ; ; ; 13.767 ; +; nIOSTRB ; RD[6] ; 13.202 ; ; ; 13.202 ; +; nIOSTRB ; RD[7] ; 13.202 ; ; ; 13.202 ; +; nIOSTRB ; RDdir ; 14.759 ; ; ; 14.759 ; +; nWE ; RD[0] ; 11.850 ; ; ; 11.850 ; +; nWE ; RD[1] ; 11.850 ; ; ; 11.850 ; +; nWE ; RD[2] ; 11.850 ; ; ; 11.850 ; +; nWE ; RD[3] ; 11.851 ; ; ; 11.851 ; +; nWE ; RD[4] ; 11.851 ; ; ; 11.851 ; +; nWE ; RD[5] ; 11.851 ; ; ; 11.851 ; +; nWE ; RD[6] ; 11.286 ; ; ; 11.286 ; +; nWE ; RD[7] ; 11.286 ; ; ; 11.286 ; +; nWE ; RDdir ; 12.843 ; ; ; 12.843 ; +------------+-------------+--------+----+----+--------+ @@ -946,45 +942,45 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-----------+------------+--------+------+------------+-----------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+--------+------+------------+-----------------+ -; FCK ; C25M ; 8.570 ; ; Rise ; C25M ; -; MOSI ; C25M ; 7.307 ; ; Rise ; C25M ; -; RD[*] ; C25M ; 12.273 ; ; Rise ; C25M ; -; RD[0] ; C25M ; 12.273 ; ; Rise ; C25M ; -; RD[1] ; C25M ; 12.273 ; ; Rise ; C25M ; -; RD[2] ; C25M ; 12.273 ; ; Rise ; C25M ; -; RD[3] ; C25M ; 12.273 ; ; Rise ; C25M ; -; RD[4] ; C25M ; 12.273 ; ; Rise ; C25M ; -; RD[5] ; C25M ; 12.273 ; ; Rise ; C25M ; -; RD[6] ; C25M ; 13.329 ; ; Rise ; C25M ; -; RD[7] ; C25M ; 13.389 ; ; Rise ; C25M ; -; SD[*] ; C25M ; 7.697 ; ; Rise ; C25M ; -; SD[0] ; C25M ; 7.697 ; ; Rise ; C25M ; -; SD[1] ; C25M ; 8.085 ; ; Rise ; C25M ; -; SD[2] ; C25M ; 7.716 ; ; Rise ; C25M ; -; SD[3] ; C25M ; 7.716 ; ; Rise ; C25M ; -; SD[4] ; C25M ; 7.697 ; ; Rise ; C25M ; -; SD[5] ; C25M ; 7.716 ; ; Rise ; C25M ; -; SD[6] ; C25M ; 7.716 ; ; Rise ; C25M ; -; SD[7] ; C25M ; 7.716 ; ; Rise ; C25M ; -; nFCS ; C25M ; 6.445 ; ; Rise ; C25M ; -; RD[*] ; PHI0 ; 7.981 ; ; Rise ; PHI0 ; -; RD[0] ; PHI0 ; 7.981 ; ; Rise ; PHI0 ; -; RD[1] ; PHI0 ; 7.981 ; ; Rise ; PHI0 ; -; RD[2] ; PHI0 ; 7.981 ; ; Rise ; PHI0 ; -; RD[3] ; PHI0 ; 7.981 ; ; Rise ; PHI0 ; -; RD[4] ; PHI0 ; 7.981 ; ; Rise ; PHI0 ; -; RD[5] ; PHI0 ; 7.981 ; ; Rise ; PHI0 ; -; RD[6] ; PHI0 ; 9.037 ; ; Rise ; PHI0 ; -; RD[7] ; PHI0 ; 9.097 ; ; Rise ; PHI0 ; -; RD[*] ; PHI0 ; 7.981 ; ; Fall ; PHI0 ; -; RD[0] ; PHI0 ; 7.981 ; ; Fall ; PHI0 ; -; RD[1] ; PHI0 ; 7.981 ; ; Fall ; PHI0 ; -; RD[2] ; PHI0 ; 7.981 ; ; Fall ; PHI0 ; -; RD[3] ; PHI0 ; 7.981 ; ; Fall ; PHI0 ; -; RD[4] ; PHI0 ; 7.981 ; ; Fall ; PHI0 ; -; RD[5] ; PHI0 ; 7.981 ; ; Fall ; PHI0 ; -; RD[6] ; PHI0 ; 9.037 ; ; Fall ; PHI0 ; -; RD[7] ; PHI0 ; 9.097 ; ; Fall ; PHI0 ; +; FCK ; C25M ; 7.684 ; ; Rise ; C25M ; +; MOSI ; C25M ; 7.765 ; ; Rise ; C25M ; +; RD[*] ; C25M ; 12.794 ; ; Rise ; C25M ; +; RD[0] ; C25M ; 13.358 ; ; Rise ; C25M ; +; RD[1] ; C25M ; 13.358 ; ; Rise ; C25M ; +; RD[2] ; C25M ; 13.358 ; ; Rise ; C25M ; +; RD[3] ; C25M ; 13.359 ; ; Rise ; C25M ; +; RD[4] ; C25M ; 13.359 ; ; Rise ; C25M ; +; RD[5] ; C25M ; 13.359 ; ; Rise ; C25M ; +; RD[6] ; C25M ; 12.794 ; ; Rise ; C25M ; +; RD[7] ; C25M ; 12.794 ; ; Rise ; C25M ; +; SD[*] ; C25M ; 6.992 ; ; Rise ; C25M ; +; SD[0] ; C25M ; 7.401 ; ; Rise ; C25M ; +; SD[1] ; C25M ; 7.009 ; ; Rise ; C25M ; +; SD[2] ; C25M ; 6.992 ; ; Rise ; C25M ; +; SD[3] ; C25M ; 6.992 ; ; Rise ; C25M ; +; SD[4] ; C25M ; 7.401 ; ; Rise ; C25M ; +; SD[5] ; C25M ; 6.992 ; ; Rise ; C25M ; +; SD[6] ; C25M ; 6.992 ; ; Rise ; C25M ; +; SD[7] ; C25M ; 6.992 ; ; Rise ; C25M ; +; nFCS ; C25M ; 7.093 ; ; Rise ; C25M ; +; RD[*] ; PHI0 ; 8.938 ; ; Rise ; PHI0 ; +; RD[0] ; PHI0 ; 9.502 ; ; Rise ; PHI0 ; +; RD[1] ; PHI0 ; 9.502 ; ; Rise ; PHI0 ; +; RD[2] ; PHI0 ; 9.502 ; ; Rise ; PHI0 ; +; RD[3] ; PHI0 ; 9.503 ; ; Rise ; PHI0 ; +; RD[4] ; PHI0 ; 9.503 ; ; Rise ; PHI0 ; +; RD[5] ; PHI0 ; 9.503 ; ; Rise ; PHI0 ; +; RD[6] ; PHI0 ; 8.938 ; ; Rise ; PHI0 ; +; RD[7] ; PHI0 ; 8.938 ; ; Rise ; PHI0 ; +; RD[*] ; PHI0 ; 8.938 ; ; Fall ; PHI0 ; +; RD[0] ; PHI0 ; 9.502 ; ; Fall ; PHI0 ; +; RD[1] ; PHI0 ; 9.502 ; ; Fall ; PHI0 ; +; RD[2] ; PHI0 ; 9.502 ; ; Fall ; PHI0 ; +; RD[3] ; PHI0 ; 9.503 ; ; Fall ; PHI0 ; +; RD[4] ; PHI0 ; 9.503 ; ; Fall ; PHI0 ; +; RD[5] ; PHI0 ; 9.503 ; ; Fall ; PHI0 ; +; RD[6] ; PHI0 ; 8.938 ; ; Fall ; PHI0 ; +; RD[7] ; PHI0 ; 8.938 ; ; Fall ; PHI0 ; +-----------+------------+--------+------+------------+-----------------+ @@ -993,45 +989,45 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-----------+------------+-------+------+------------+-----------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+-------+------+------------+-----------------+ -; FCK ; C25M ; 8.570 ; ; Rise ; C25M ; -; MOSI ; C25M ; 7.307 ; ; Rise ; C25M ; -; RD[*] ; C25M ; 7.705 ; ; Rise ; C25M ; -; RD[0] ; C25M ; 7.705 ; ; Rise ; C25M ; -; RD[1] ; C25M ; 7.705 ; ; Rise ; C25M ; -; RD[2] ; C25M ; 7.705 ; ; Rise ; C25M ; -; RD[3] ; C25M ; 7.705 ; ; Rise ; C25M ; -; RD[4] ; C25M ; 7.705 ; ; Rise ; C25M ; -; RD[5] ; C25M ; 7.705 ; ; Rise ; C25M ; -; RD[6] ; C25M ; 8.761 ; ; Rise ; C25M ; -; RD[7] ; C25M ; 8.821 ; ; Rise ; C25M ; -; SD[*] ; C25M ; 7.697 ; ; Rise ; C25M ; -; SD[0] ; C25M ; 7.697 ; ; Rise ; C25M ; -; SD[1] ; C25M ; 8.085 ; ; Rise ; C25M ; -; SD[2] ; C25M ; 7.716 ; ; Rise ; C25M ; -; SD[3] ; C25M ; 7.716 ; ; Rise ; C25M ; -; SD[4] ; C25M ; 7.697 ; ; Rise ; C25M ; -; SD[5] ; C25M ; 7.716 ; ; Rise ; C25M ; -; SD[6] ; C25M ; 7.716 ; ; Rise ; C25M ; -; SD[7] ; C25M ; 7.716 ; ; Rise ; C25M ; -; nFCS ; C25M ; 6.445 ; ; Rise ; C25M ; -; RD[*] ; PHI0 ; 7.981 ; ; Rise ; PHI0 ; -; RD[0] ; PHI0 ; 7.981 ; ; Rise ; PHI0 ; -; RD[1] ; PHI0 ; 7.981 ; ; Rise ; PHI0 ; -; RD[2] ; PHI0 ; 7.981 ; ; Rise ; PHI0 ; -; RD[3] ; PHI0 ; 7.981 ; ; Rise ; PHI0 ; -; RD[4] ; PHI0 ; 7.981 ; ; Rise ; PHI0 ; -; RD[5] ; PHI0 ; 7.981 ; ; Rise ; PHI0 ; -; RD[6] ; PHI0 ; 9.037 ; ; Rise ; PHI0 ; -; RD[7] ; PHI0 ; 9.097 ; ; Rise ; PHI0 ; -; RD[*] ; PHI0 ; 7.981 ; ; Fall ; PHI0 ; -; RD[0] ; PHI0 ; 7.981 ; ; Fall ; PHI0 ; -; RD[1] ; PHI0 ; 7.981 ; ; Fall ; PHI0 ; -; RD[2] ; PHI0 ; 7.981 ; ; Fall ; PHI0 ; -; RD[3] ; PHI0 ; 7.981 ; ; Fall ; PHI0 ; -; RD[4] ; PHI0 ; 7.981 ; ; Fall ; PHI0 ; -; RD[5] ; PHI0 ; 7.981 ; ; Fall ; PHI0 ; -; RD[6] ; PHI0 ; 9.037 ; ; Fall ; PHI0 ; -; RD[7] ; PHI0 ; 9.097 ; ; Fall ; PHI0 ; +; FCK ; C25M ; 7.684 ; ; Rise ; C25M ; +; MOSI ; C25M ; 7.765 ; ; Rise ; C25M ; +; RD[*] ; C25M ; 8.190 ; ; Rise ; C25M ; +; RD[0] ; C25M ; 8.754 ; ; Rise ; C25M ; +; RD[1] ; C25M ; 8.754 ; ; Rise ; C25M ; +; RD[2] ; C25M ; 8.754 ; ; Rise ; C25M ; +; RD[3] ; C25M ; 8.755 ; ; Rise ; C25M ; +; RD[4] ; C25M ; 8.755 ; ; Rise ; C25M ; +; RD[5] ; C25M ; 8.755 ; ; Rise ; C25M ; +; RD[6] ; C25M ; 8.190 ; ; Rise ; C25M ; +; RD[7] ; C25M ; 8.190 ; ; Rise ; C25M ; +; SD[*] ; C25M ; 6.992 ; ; Rise ; C25M ; +; SD[0] ; C25M ; 7.401 ; ; Rise ; C25M ; +; SD[1] ; C25M ; 7.009 ; ; Rise ; C25M ; +; SD[2] ; C25M ; 6.992 ; ; Rise ; C25M ; +; SD[3] ; C25M ; 6.992 ; ; Rise ; C25M ; +; SD[4] ; C25M ; 7.401 ; ; Rise ; C25M ; +; SD[5] ; C25M ; 6.992 ; ; Rise ; C25M ; +; SD[6] ; C25M ; 6.992 ; ; Rise ; C25M ; +; SD[7] ; C25M ; 6.992 ; ; Rise ; C25M ; +; nFCS ; C25M ; 7.093 ; ; Rise ; C25M ; +; RD[*] ; PHI0 ; 8.938 ; ; Rise ; PHI0 ; +; RD[0] ; PHI0 ; 9.502 ; ; Rise ; PHI0 ; +; RD[1] ; PHI0 ; 9.502 ; ; Rise ; PHI0 ; +; RD[2] ; PHI0 ; 9.502 ; ; Rise ; PHI0 ; +; RD[3] ; PHI0 ; 9.503 ; ; Rise ; PHI0 ; +; RD[4] ; PHI0 ; 9.503 ; ; Rise ; PHI0 ; +; RD[5] ; PHI0 ; 9.503 ; ; Rise ; PHI0 ; +; RD[6] ; PHI0 ; 8.938 ; ; Rise ; PHI0 ; +; RD[7] ; PHI0 ; 8.938 ; ; Rise ; PHI0 ; +; RD[*] ; PHI0 ; 8.938 ; ; Fall ; PHI0 ; +; RD[0] ; PHI0 ; 9.502 ; ; Fall ; PHI0 ; +; RD[1] ; PHI0 ; 9.502 ; ; Fall ; PHI0 ; +; RD[2] ; PHI0 ; 9.502 ; ; Fall ; PHI0 ; +; RD[3] ; PHI0 ; 9.503 ; ; Fall ; PHI0 ; +; RD[4] ; PHI0 ; 9.503 ; ; Fall ; PHI0 ; +; RD[5] ; PHI0 ; 9.503 ; ; Fall ; PHI0 ; +; RD[6] ; PHI0 ; 8.938 ; ; Fall ; PHI0 ; +; RD[7] ; PHI0 ; 8.938 ; ; Fall ; PHI0 ; +-----------+------------+-------+------+------------+-----------------+ @@ -1040,45 +1036,45 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-----------+------------+-----------+-----------+------------+-----------------+ ; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; +-----------+------------+-----------+-----------+------------+-----------------+ -; FCK ; C25M ; 8.570 ; ; Rise ; C25M ; -; MOSI ; C25M ; 7.307 ; ; Rise ; C25M ; -; RD[*] ; C25M ; 12.273 ; ; Rise ; C25M ; -; RD[0] ; C25M ; 12.273 ; ; Rise ; C25M ; -; RD[1] ; C25M ; 12.273 ; ; Rise ; C25M ; -; RD[2] ; C25M ; 12.273 ; ; Rise ; C25M ; -; RD[3] ; C25M ; 12.273 ; ; Rise ; C25M ; -; RD[4] ; C25M ; 12.273 ; ; Rise ; C25M ; -; RD[5] ; C25M ; 12.273 ; ; Rise ; C25M ; -; RD[6] ; C25M ; 13.329 ; ; Rise ; C25M ; -; RD[7] ; C25M ; 13.389 ; ; Rise ; C25M ; -; SD[*] ; C25M ; 7.697 ; ; Rise ; C25M ; -; SD[0] ; C25M ; 7.697 ; ; Rise ; C25M ; -; SD[1] ; C25M ; 8.085 ; ; Rise ; C25M ; -; SD[2] ; C25M ; 7.716 ; ; Rise ; C25M ; -; SD[3] ; C25M ; 7.716 ; ; Rise ; C25M ; -; SD[4] ; C25M ; 7.697 ; ; Rise ; C25M ; -; SD[5] ; C25M ; 7.716 ; ; Rise ; C25M ; -; SD[6] ; C25M ; 7.716 ; ; Rise ; C25M ; -; SD[7] ; C25M ; 7.716 ; ; Rise ; C25M ; -; nFCS ; C25M ; 6.445 ; ; Rise ; C25M ; -; RD[*] ; PHI0 ; 7.981 ; ; Rise ; PHI0 ; -; RD[0] ; PHI0 ; 7.981 ; ; Rise ; PHI0 ; -; RD[1] ; PHI0 ; 7.981 ; ; Rise ; PHI0 ; -; RD[2] ; PHI0 ; 7.981 ; ; Rise ; PHI0 ; -; RD[3] ; PHI0 ; 7.981 ; ; Rise ; PHI0 ; -; RD[4] ; PHI0 ; 7.981 ; ; Rise ; PHI0 ; -; RD[5] ; PHI0 ; 7.981 ; ; Rise ; PHI0 ; -; RD[6] ; PHI0 ; 9.037 ; ; Rise ; PHI0 ; -; RD[7] ; PHI0 ; 9.097 ; ; Rise ; PHI0 ; -; RD[*] ; PHI0 ; 7.981 ; ; Fall ; PHI0 ; -; RD[0] ; PHI0 ; 7.981 ; ; Fall ; PHI0 ; -; RD[1] ; PHI0 ; 7.981 ; ; Fall ; PHI0 ; -; RD[2] ; PHI0 ; 7.981 ; ; Fall ; PHI0 ; -; RD[3] ; PHI0 ; 7.981 ; ; Fall ; PHI0 ; -; RD[4] ; PHI0 ; 7.981 ; ; Fall ; PHI0 ; -; RD[5] ; PHI0 ; 7.981 ; ; Fall ; PHI0 ; -; RD[6] ; PHI0 ; 9.037 ; ; Fall ; PHI0 ; -; RD[7] ; PHI0 ; 9.097 ; ; Fall ; PHI0 ; +; FCK ; C25M ; 7.684 ; ; Rise ; C25M ; +; MOSI ; C25M ; 7.765 ; ; Rise ; C25M ; +; RD[*] ; C25M ; 12.794 ; ; Rise ; C25M ; +; RD[0] ; C25M ; 13.358 ; ; Rise ; C25M ; +; RD[1] ; C25M ; 13.358 ; ; Rise ; C25M ; +; RD[2] ; C25M ; 13.358 ; ; Rise ; C25M ; +; RD[3] ; C25M ; 13.359 ; ; Rise ; C25M ; +; RD[4] ; C25M ; 13.359 ; ; Rise ; C25M ; +; RD[5] ; C25M ; 13.359 ; ; Rise ; C25M ; +; RD[6] ; C25M ; 12.794 ; ; Rise ; C25M ; +; RD[7] ; C25M ; 12.794 ; ; Rise ; C25M ; +; SD[*] ; C25M ; 6.992 ; ; Rise ; C25M ; +; SD[0] ; C25M ; 7.401 ; ; Rise ; C25M ; +; SD[1] ; C25M ; 7.009 ; ; Rise ; C25M ; +; SD[2] ; C25M ; 6.992 ; ; Rise ; C25M ; +; SD[3] ; C25M ; 6.992 ; ; Rise ; C25M ; +; SD[4] ; C25M ; 7.401 ; ; Rise ; C25M ; +; SD[5] ; C25M ; 6.992 ; ; Rise ; C25M ; +; SD[6] ; C25M ; 6.992 ; ; Rise ; C25M ; +; SD[7] ; C25M ; 6.992 ; ; Rise ; C25M ; +; nFCS ; C25M ; 7.093 ; ; Rise ; C25M ; +; RD[*] ; PHI0 ; 8.938 ; ; Rise ; PHI0 ; +; RD[0] ; PHI0 ; 9.502 ; ; Rise ; PHI0 ; +; RD[1] ; PHI0 ; 9.502 ; ; Rise ; PHI0 ; +; RD[2] ; PHI0 ; 9.502 ; ; Rise ; PHI0 ; +; RD[3] ; PHI0 ; 9.503 ; ; Rise ; PHI0 ; +; RD[4] ; PHI0 ; 9.503 ; ; Rise ; PHI0 ; +; RD[5] ; PHI0 ; 9.503 ; ; Rise ; PHI0 ; +; RD[6] ; PHI0 ; 8.938 ; ; Rise ; PHI0 ; +; RD[7] ; PHI0 ; 8.938 ; ; Rise ; PHI0 ; +; RD[*] ; PHI0 ; 8.938 ; ; Fall ; PHI0 ; +; RD[0] ; PHI0 ; 9.502 ; ; Fall ; PHI0 ; +; RD[1] ; PHI0 ; 9.502 ; ; Fall ; PHI0 ; +; RD[2] ; PHI0 ; 9.502 ; ; Fall ; PHI0 ; +; RD[3] ; PHI0 ; 9.503 ; ; Fall ; PHI0 ; +; RD[4] ; PHI0 ; 9.503 ; ; Fall ; PHI0 ; +; RD[5] ; PHI0 ; 9.503 ; ; Fall ; PHI0 ; +; RD[6] ; PHI0 ; 8.938 ; ; Fall ; PHI0 ; +; RD[7] ; PHI0 ; 8.938 ; ; Fall ; PHI0 ; +-----------+------------+-----------+-----------+------------+-----------------+ @@ -1087,45 +1083,45 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-----------+------------+-----------+-----------+------------+-----------------+ ; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; +-----------+------------+-----------+-----------+------------+-----------------+ -; FCK ; C25M ; 8.570 ; ; Rise ; C25M ; -; MOSI ; C25M ; 7.307 ; ; Rise ; C25M ; -; RD[*] ; C25M ; 7.705 ; ; Rise ; C25M ; -; RD[0] ; C25M ; 7.705 ; ; Rise ; C25M ; -; RD[1] ; C25M ; 7.705 ; ; Rise ; C25M ; -; RD[2] ; C25M ; 7.705 ; ; Rise ; C25M ; -; RD[3] ; C25M ; 7.705 ; ; Rise ; C25M ; -; RD[4] ; C25M ; 7.705 ; ; Rise ; C25M ; -; RD[5] ; C25M ; 7.705 ; ; Rise ; C25M ; -; RD[6] ; C25M ; 8.761 ; ; Rise ; C25M ; -; RD[7] ; C25M ; 8.821 ; ; Rise ; C25M ; -; SD[*] ; C25M ; 7.697 ; ; Rise ; C25M ; -; SD[0] ; C25M ; 7.697 ; ; Rise ; C25M ; -; SD[1] ; C25M ; 8.085 ; ; Rise ; C25M ; -; SD[2] ; C25M ; 7.716 ; ; Rise ; C25M ; -; SD[3] ; C25M ; 7.716 ; ; Rise ; C25M ; -; SD[4] ; C25M ; 7.697 ; ; Rise ; C25M ; -; SD[5] ; C25M ; 7.716 ; ; Rise ; C25M ; -; SD[6] ; C25M ; 7.716 ; ; Rise ; C25M ; -; SD[7] ; C25M ; 7.716 ; ; Rise ; C25M ; -; nFCS ; C25M ; 6.445 ; ; Rise ; C25M ; -; RD[*] ; PHI0 ; 7.981 ; ; Rise ; PHI0 ; -; RD[0] ; PHI0 ; 7.981 ; ; Rise ; PHI0 ; -; RD[1] ; PHI0 ; 7.981 ; ; Rise ; PHI0 ; -; RD[2] ; PHI0 ; 7.981 ; ; Rise ; PHI0 ; -; RD[3] ; PHI0 ; 7.981 ; ; Rise ; PHI0 ; -; RD[4] ; PHI0 ; 7.981 ; ; Rise ; PHI0 ; -; RD[5] ; PHI0 ; 7.981 ; ; Rise ; PHI0 ; -; RD[6] ; PHI0 ; 9.037 ; ; Rise ; PHI0 ; -; RD[7] ; PHI0 ; 9.097 ; ; Rise ; PHI0 ; -; RD[*] ; PHI0 ; 7.981 ; ; Fall ; PHI0 ; -; RD[0] ; PHI0 ; 7.981 ; ; Fall ; PHI0 ; -; RD[1] ; PHI0 ; 7.981 ; ; Fall ; PHI0 ; -; RD[2] ; PHI0 ; 7.981 ; ; Fall ; PHI0 ; -; RD[3] ; PHI0 ; 7.981 ; ; Fall ; PHI0 ; -; RD[4] ; PHI0 ; 7.981 ; ; Fall ; PHI0 ; -; RD[5] ; PHI0 ; 7.981 ; ; Fall ; PHI0 ; -; RD[6] ; PHI0 ; 9.037 ; ; Fall ; PHI0 ; -; RD[7] ; PHI0 ; 9.097 ; ; Fall ; PHI0 ; +; FCK ; C25M ; 7.684 ; ; Rise ; C25M ; +; MOSI ; C25M ; 7.765 ; ; Rise ; C25M ; +; RD[*] ; C25M ; 8.190 ; ; Rise ; C25M ; +; RD[0] ; C25M ; 8.754 ; ; Rise ; C25M ; +; RD[1] ; C25M ; 8.754 ; ; Rise ; C25M ; +; RD[2] ; C25M ; 8.754 ; ; Rise ; C25M ; +; RD[3] ; C25M ; 8.755 ; ; Rise ; C25M ; +; RD[4] ; C25M ; 8.755 ; ; Rise ; C25M ; +; RD[5] ; C25M ; 8.755 ; ; Rise ; C25M ; +; RD[6] ; C25M ; 8.190 ; ; Rise ; C25M ; +; RD[7] ; C25M ; 8.190 ; ; Rise ; C25M ; +; SD[*] ; C25M ; 6.992 ; ; Rise ; C25M ; +; SD[0] ; C25M ; 7.401 ; ; Rise ; C25M ; +; SD[1] ; C25M ; 7.009 ; ; Rise ; C25M ; +; SD[2] ; C25M ; 6.992 ; ; Rise ; C25M ; +; SD[3] ; C25M ; 6.992 ; ; Rise ; C25M ; +; SD[4] ; C25M ; 7.401 ; ; Rise ; C25M ; +; SD[5] ; C25M ; 6.992 ; ; Rise ; C25M ; +; SD[6] ; C25M ; 6.992 ; ; Rise ; C25M ; +; SD[7] ; C25M ; 6.992 ; ; Rise ; C25M ; +; nFCS ; C25M ; 7.093 ; ; Rise ; C25M ; +; RD[*] ; PHI0 ; 8.938 ; ; Rise ; PHI0 ; +; RD[0] ; PHI0 ; 9.502 ; ; Rise ; PHI0 ; +; RD[1] ; PHI0 ; 9.502 ; ; Rise ; PHI0 ; +; RD[2] ; PHI0 ; 9.502 ; ; Rise ; PHI0 ; +; RD[3] ; PHI0 ; 9.503 ; ; Rise ; PHI0 ; +; RD[4] ; PHI0 ; 9.503 ; ; Rise ; PHI0 ; +; RD[5] ; PHI0 ; 9.503 ; ; Rise ; PHI0 ; +; RD[6] ; PHI0 ; 8.938 ; ; Rise ; PHI0 ; +; RD[7] ; PHI0 ; 8.938 ; ; Rise ; PHI0 ; +; RD[*] ; PHI0 ; 8.938 ; ; Fall ; PHI0 ; +; RD[0] ; PHI0 ; 9.502 ; ; Fall ; PHI0 ; +; RD[1] ; PHI0 ; 9.502 ; ; Fall ; PHI0 ; +; RD[2] ; PHI0 ; 9.502 ; ; Fall ; PHI0 ; +; RD[3] ; PHI0 ; 9.503 ; ; Fall ; PHI0 ; +; RD[4] ; PHI0 ; 9.503 ; ; Fall ; PHI0 ; +; RD[5] ; PHI0 ; 9.503 ; ; Fall ; PHI0 ; +; RD[6] ; PHI0 ; 8.938 ; ; Fall ; PHI0 ; +; RD[7] ; PHI0 ; 8.938 ; ; Fall ; PHI0 ; +-----------+------------+-----------+-----------+------------+-----------------+ @@ -1134,8 +1130,8 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +------------+----------+----------+----------+----------+----------+ ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; +------------+----------+----------+----------+----------+----------+ -; C25M ; C25M ; 1371 ; 0 ; 0 ; 0 ; -; PHI0 ; C25M ; 85 ; 1 ; 0 ; 0 ; +; C25M ; C25M ; 1369 ; 0 ; 0 ; 0 ; +; PHI0 ; C25M ; 84 ; 1 ; 0 ; 0 ; ; C25M ; PHI0 ; 2 ; 0 ; 0 ; 0 ; +------------+----------+----------+----------+----------+----------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. @@ -1146,8 +1142,8 @@ Entries labeled "false path" only account for clock-to-clock false paths and not +------------+----------+----------+----------+----------+----------+ ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; +------------+----------+----------+----------+----------+----------+ -; C25M ; C25M ; 1371 ; 0 ; 0 ; 0 ; -; PHI0 ; C25M ; 85 ; 1 ; 0 ; 0 ; +; C25M ; C25M ; 1369 ; 0 ; 0 ; 0 ; +; PHI0 ; C25M ; 84 ; 1 ; 0 ; 0 ; ; C25M ; PHI0 ; 2 ; 0 ; 0 ; 0 ; +------------+----------+----------+----------+----------+----------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. @@ -1158,7 +1154,7 @@ Entries labeled "false path" only account for clock-to-clock false paths and not +------------+----------+----------+----------+----------+----------+ ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; +------------+----------+----------+----------+----------+----------+ -; C25M ; C25M ; 30 ; 0 ; 0 ; 0 ; +; C25M ; C25M ; 29 ; 0 ; 0 ; 0 ; +------------+----------+----------+----------+----------+----------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. @@ -1168,7 +1164,7 @@ Entries labeled "false path" only account for clock-to-clock false paths and not +------------+----------+----------+----------+----------+----------+ ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; +------------+----------+----------+----------+----------+----------+ -; C25M ; C25M ; 30 ; 0 ; 0 ; 0 ; +; C25M ; C25M ; 29 ; 0 ; 0 ; 0 ; +------------+----------+----------+----------+----------+----------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. @@ -1193,7 +1189,7 @@ No dedicated SERDES Receiver circuitry present in device or used in design ; Illegal Clocks ; 0 ; 0 ; ; Unconstrained Clocks ; 0 ; 0 ; ; Unconstrained Input Ports ; 42 ; 42 ; -; Unconstrained Input Port Paths ; 641 ; 641 ; +; Unconstrained Input Port Paths ; 643 ; 643 ; ; Unconstrained Output Ports ; 45 ; 45 ; ; Unconstrained Output Port Paths ; 118 ; 118 ; +---------------------------------+-------+------+ @@ -1205,7 +1201,7 @@ No dedicated SERDES Receiver circuitry present in device or used in design Info: ******************************************************************* Info: Running Quartus II 32-bit TimeQuest Timing Analyzer Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - Info: Processing started: Sun Apr 18 06:27:20 2021 + Info: Processing started: Mon Apr 19 01:27:20 2021 Info: Command: quartus_sta GR8RAM -c GR8RAM Info: qsta_default_script.tcl version: #1 Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected @@ -1220,24 +1216,24 @@ Info (332105): Deriving Clocks Info (332105): create_clock -period 1.000 -name PHI0 PHI0 Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON Critical Warning (332148): Timing requirements not met -Info (332146): Worst-case setup slack is -9.035 +Info (332146): Worst-case setup slack is -9.468 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== - Info (332119): -9.035 -651.992 C25M - Info (332119): 0.356 0.000 PHI0 -Info (332146): Worst-case hold slack is -0.263 + Info (332119): -9.468 -696.810 C25M + Info (332119): 0.212 0.000 PHI0 +Info (332146): Worst-case hold slack is -0.265 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== - Info (332119): -0.263 -0.263 PHI0 - Info (332119): 1.391 0.000 C25M -Info (332146): Worst-case recovery slack is -4.406 + Info (332119): -0.265 -0.265 PHI0 + Info (332119): 1.374 0.000 C25M +Info (332146): Worst-case recovery slack is -4.404 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== - Info (332119): -4.406 -132.180 C25M -Info (332146): Worst-case removal slack is 4.852 + Info (332119): -4.404 -127.716 C25M +Info (332146): Worst-case removal slack is 4.850 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== - Info (332119): 4.852 0.000 C25M + Info (332119): 4.850 0.000 C25M Info (332146): Worst-case minimum pulse width slack is -2.289 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== @@ -1247,8 +1243,8 @@ Info (332001): The selected device family is not supported by the report_metasta Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings - Info: Peak virtual memory: 276 megabytes - Info: Processing ended: Sun Apr 18 06:27:24 2021 + Info: Peak virtual memory: 283 megabytes + Info: Processing ended: Mon Apr 19 01:27:24 2021 Info: Elapsed time: 00:00:04 Info: Total CPU time (on all processors): 00:00:04 diff --git a/cpld/output_files/GR8RAM.sta.summary b/cpld/output_files/GR8RAM.sta.summary index 8110278..353f12e 100755 --- a/cpld/output_files/GR8RAM.sta.summary +++ b/cpld/output_files/GR8RAM.sta.summary @@ -3,27 +3,27 @@ TimeQuest Timing Analyzer Summary ------------------------------------------------------------ Type : Setup 'C25M' -Slack : -9.035 -TNS : -651.992 +Slack : -9.468 +TNS : -696.810 Type : Setup 'PHI0' -Slack : 0.356 +Slack : 0.212 TNS : 0.000 Type : Hold 'PHI0' -Slack : -0.263 -TNS : -0.263 +Slack : -0.265 +TNS : -0.265 Type : Hold 'C25M' -Slack : 1.391 +Slack : 1.374 TNS : 0.000 Type : Recovery 'C25M' -Slack : -4.406 -TNS : -132.180 +Slack : -4.404 +TNS : -127.716 Type : Removal 'C25M' -Slack : 4.852 +Slack : 4.850 TNS : 0.000 Type : Minimum Pulse Width 'C25M'