From f347a27f89382ff6b9ff8d0788b8e1abe655f1e2 Mon Sep 17 00:00:00 2001 From: Zane Kaminski Date: Fri, 16 Feb 2024 20:43:29 -0500 Subject: [PATCH] Create new quartus project --- cpld/GR8RAM.qpf | 31 ++++++++++++++++++++++++++++++ cpld/GR8RAM.qsf | 49 ++++++++++++++++++++++-------------------------- cpld/GR8RAM.qws | Bin 0 -> 48 bytes 3 files changed, 53 insertions(+), 27 deletions(-) create mode 100644 cpld/GR8RAM.qpf create mode 100644 cpld/GR8RAM.qws diff --git a/cpld/GR8RAM.qpf b/cpld/GR8RAM.qpf new file mode 100644 index 0000000..0ba958e --- /dev/null +++ b/cpld/GR8RAM.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2019 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition +# Date created = 20:42:53 February 16, 2024 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "19.1" +DATE = "20:42:53 February 16, 2024" + +# Revisions + +PROJECT_REVISION = "GR8RAM" diff --git a/cpld/GR8RAM.qsf b/cpld/GR8RAM.qsf index e2e3f88..d44ef3f 100644 --- a/cpld/GR8RAM.qsf +++ b/cpld/GR8RAM.qsf @@ -1,24 +1,25 @@ # -------------------------------------------------------------------------- # # -# Copyright (C) 1991-2013 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic +# Copyright (C) 2019 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic # functions, and any output files from any of the foregoing # (including device programming or simulation files), and any # associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. # # -------------------------------------------------------------------------- # # -# Quartus II 32-bit -# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition -# Date created = 13:41:40 March 15, 2021 +# Quartus Prime +# Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition +# Date created = 20:36:06 February 16, 2024 # # -------------------------------------------------------------------------- # # @@ -30,7 +31,7 @@ # assignment_defaults.qdf # # 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software +# file is updated automatically by the Quartus Prime software # and any changes you make may be lost or overwritten. # # -------------------------------------------------------------------------- # @@ -39,9 +40,11 @@ set_global_assignment -name FAMILY "MAX II" set_global_assignment -name DEVICE EPM240T100C5 set_global_assignment -name TOP_LEVEL_ENTITY GR8RAM -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 22.1STD.0 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:15:44 FEBRUARY 28, 2023" -set_global_assignment -name LAST_QUARTUS_VERSION "22.1std.0 Lite Edition" +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 19.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:36:06 FEBRUARY 16, 2024" +set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition" +set_global_assignment -name SDC_FILE GR8RAM.sdc +set_global_assignment -name VERILOG_FILE GR8RAM.v set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 @@ -50,14 +53,7 @@ set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100 set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 5 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1" set_global_assignment -name POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR 3.3V -set_global_assignment -name EDA_SIMULATION_TOOL "Questa Intel FPGA (Verilog)" -set_global_assignment -name EDA_NETLIST_WRITER_OUTPUT_DIR simulation/questa -section_id eda_simulation -set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation -set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation -set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing -set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol -set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity -set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan + set_location_assignment PIN_2 -to RA[5] set_location_assignment PIN_3 -to RA[6] set_location_assignment PIN_4 -to RA[3] @@ -253,5 +249,4 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SD set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SD set_instance_assignment -name SLOW_SLEW_RATE ON -to SD -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SD -set_global_assignment -name SDC_FILE GR8RAM.sdc \ No newline at end of file +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SD \ No newline at end of file diff --git a/cpld/GR8RAM.qws b/cpld/GR8RAM.qws new file mode 100644 index 0000000000000000000000000000000000000000..63563b76eda4b19c3f4f321afd3f1b7df67b8d5e GIT binary patch literal 48 ocmZ?JV1NM`h8%`OhGK>ihIoc@hJ1!1hHN0O04SEskP1@-0GYrBX8-^I literal 0 HcmV?d00001