diff --git a/cpld/GR8RAM.qpf b/cpld/GR8RAM.qpf deleted file mode 100755 index cd70607..0000000 --- a/cpld/GR8RAM.qpf +++ /dev/null @@ -1,30 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2013 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 32-bit -# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition -# Date created = 02:27:57 August 06, 2019 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "13.0" -DATE = "02:27:57 August 06, 2019" - -# Revisions - -PROJECT_REVISION = "GR8RAM" diff --git a/cpld/GR8RAM.qsf b/cpld/GR8RAM.qsf deleted file mode 100644 index 9a29f0e..0000000 --- a/cpld/GR8RAM.qsf +++ /dev/null @@ -1,165 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2013 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 32-bit -# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition -# Date created = 02:27:57 August 06, 2019 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# GR8RAM_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - -set_global_assignment -name FAMILY MAX7000S -set_global_assignment -name DEVICE "EPM7128SLC84-15" -set_global_assignment -name TOP_LEVEL_ENTITY GR8RAM -set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" -set_global_assignment -name PROJECT_CREATION_TIME_DATE "02:27:57 AUGUST 06, 2019" -set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name DEVICE_FILTER_PACKAGE PLCC -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 84 -set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 15 -set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1" -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name VERILOG_FILE GR8RAM.v -set_global_assignment -name MAX7000_DEVICE_IO_STANDARD TTL -set_location_assignment PIN_1 -to nRES -set_location_assignment PIN_75 -to A[0] -set_location_assignment PIN_77 -to A[2] -set_location_assignment PIN_79 -to A[3] -set_location_assignment PIN_80 -to A[4] -set_location_assignment PIN_81 -to A[5] -set_location_assignment PIN_83 -to C7M -set_location_assignment PIN_84 -to C7M_2 -set_location_assignment PIN_4 -to A[6] -set_location_assignment PIN_5 -to A[7] -set_location_assignment PIN_9 -to A[8] -set_location_assignment PIN_10 -to A[9] -set_location_assignment PIN_11 -to A[10] -set_location_assignment PIN_12 -to A[11] -set_location_assignment PIN_15 -to A[12] -set_location_assignment PIN_6 -to Q3 -set_location_assignment PIN_16 -to A[13] -set_location_assignment PIN_17 -to A[14] -set_location_assignment PIN_18 -to A[15] -set_location_assignment PIN_20 -to nWE -set_location_assignment PIN_21 -to nDEVSEL -set_location_assignment PIN_22 -to nINH -set_location_assignment PIN_24 -to nIOSTRB -set_location_assignment PIN_25 -to D[7] -set_location_assignment PIN_27 -to D[6] -set_location_assignment PIN_28 -to D[5] -set_location_assignment PIN_29 -to D[4] -set_location_assignment PIN_33 -to D[3] -set_location_assignment PIN_34 -to D[2] -set_location_assignment PIN_35 -to D[1] -set_location_assignment PIN_36 -to D[0] -set_location_assignment PIN_39 -to nCAS0 -set_location_assignment PIN_40 -to nCAS1 -set_location_assignment PIN_41 -to nRCS -set_location_assignment PIN_45 -to nROE -set_location_assignment PIN_46 -to RA[9] -set_location_assignment PIN_48 -to RA[10] -set_location_assignment PIN_49 -to RA[3] -set_location_assignment PIN_50 -to RA[2] -set_location_assignment PIN_51 -to RA[5] -set_location_assignment PIN_52 -to RA[0] -set_location_assignment PIN_54 -to RA[1] -set_location_assignment PIN_55 -to RA[4] -set_location_assignment PIN_56 -to RA[7] -set_location_assignment PIN_57 -to RA[6] -set_location_assignment PIN_58 -to RA[8] -set_location_assignment PIN_60 -to nRAS -set_location_assignment PIN_61 -to RD[7] -set_location_assignment PIN_63 -to RD[5] -set_location_assignment PIN_64 -to RD[6] -set_location_assignment PIN_65 -to RD[4] -set_location_assignment PIN_67 -to nRWE -set_location_assignment PIN_68 -to RD[3] -set_location_assignment PIN_69 -to RD[2] -set_location_assignment PIN_70 -to RD[1] -set_location_assignment PIN_73 -to RD[0] -set_location_assignment PIN_74 -to nIOSEL -set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF -set_global_assignment -name FITTER_EFFORT "STANDARD FIT" -set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING "PACK ALL IO REGISTERS" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF -set_global_assignment -name AUTO_LCELL_INSERTION OFF -set_global_assignment -name AUTO_PARALLEL_EXPANDERS OFF -set_global_assignment -name AUTO_RESOURCE_SHARING OFF -set_global_assignment -name SYNTH_MESSAGE_LEVEL HIGH -set_global_assignment -name SLOW_SLEW_RATE ON -set_global_assignment -name ALM_REGISTER_PACKING_EFFORT HIGH -set_global_assignment -name ECO_OPTIMIZE_TIMING ON -set_global_assignment -name ECO_REGENERATE_REPORT ON -set_location_assignment LC1 -to Addr[0] -set_location_assignment LC2 -to Addr[1] -set_location_assignment LC3 -to Addr[2] -set_location_assignment LC4 -to Addr[3] -set_location_assignment LC5 -to Addr[4] -set_location_assignment LC6 -to Addr[5] -set_location_assignment LC7 -to Addr[6] -set_location_assignment LC8 -to Addr[7] -set_location_assignment LC9 -to Addr[8] -set_location_assignment LC10 -to Addr[9] -set_location_assignment LC11 -to Addr[10] -set_location_assignment LC12 -to Addr[11] -set_location_assignment LC13 -to Addr[12] -set_location_assignment LC14 -to Addr[13] -set_location_assignment LC15 -to Addr[14] -set_location_assignment LC16 -to Addr[15] -set_global_assignment -name PARALLEL_SYNTHESIS OFF -set_global_assignment -name STATE_MACHINE_PROCESSING "USER-ENCODED" -set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS OFF -set_location_assignment PIN_76 -to A[1] -set_location_assignment PIN_8 -to PHI0in -set_location_assignment PIN_2 -to PHI1in -set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES OFF -set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES OFF -set_global_assignment -name PRE_MAPPING_RESYNTHESIS ON -set_global_assignment -name AUTO_TURBO_BIT OFF -set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b1_MC -set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b2_MC -set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b3_MC -set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b4_MC -set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b5_MC -set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b6_MC -set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b7_MC -set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b8_MC -set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b9_MC -set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI0seen -set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1reg -set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to S -set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b0_MC -set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to IOROMEN -set_location_assignment PIN_44 -to nMode -set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to RAMSEL_MC \ No newline at end of file diff --git a/cpld/GR8RAM.qws b/cpld/GR8RAM.qws deleted file mode 100755 index 2149711..0000000 Binary files a/cpld/GR8RAM.qws and /dev/null differ diff --git a/cpld/GR8RAM.v b/cpld/GR8RAM.v deleted file mode 100755 index af9b0bc..0000000 --- a/cpld/GR8RAM.v +++ /dev/null @@ -1,374 +0,0 @@ -module GR8RAM(C25M, PHI0, nPBOD, nBOD, nRES, - nIOSEL, nDEVSEL, nIOSTRB, - RA, nWEin, nWEout, Adir, - RD, Ddir, - DMAin, DMAout, INTin, INTout, - nDMA, nRDY, nNMI, nIRQ, nINH, nRESout - SBA, SA, nRCS, nRAS, nCAS, nSWE, DQML, DQMH, RCKE, SD, - nFCS, FCK, MISO, MOSI); - - /* Clock signals */ - input C25M, PHI0; - reg PHI0r1, PHI0r2, PHI0r3; - always @(negedge C25M) begin PHI0r1 <= PHI0; end - always @(posedge C25M) begin - PHI0r2 <= PHI0r1; PHI0r3 <= PHI0r2; - end - - /* Reset/brown-out detect inputs */ - input nRES, nPBOD, nBOD; - reg PBODr1, PBODr2, BODr1, BODr2, RESr1, RESr2; - always @(negedge C25M) begin - PBODr1 <= ~nPBOD; BODr1 <= ~nBOD; RESr1 <= ~nRES; - end - always @(posedge C25M) begin - PBODr2 <= PBODr1; BODr2 <= BODr1; RESr2 <= RESr1; - end - - /* Apple IO area select signals */ - input nIOSEL, nDEVSEL, nIOSTRB; - reg DEVSELr1, DEVSELr2; - always @(negedge C25M) begin DEVSELr1 <= ~nDEVSEL; end - always @(posedge C25M) begin DEVSELr2 <= DEVSELr1; end - - /* DMA/IRQ daisy chain */ - input DMAin, INTin; - output DMAout = DMAin; - output INTout = INTin; - - /* Apple open-drain outputs */ - output nDMA = 1; - output nRDY = 1; - output nNMI = 1; - output nIRQ = 1; - output nINH = 1; - output nRESout = 0; - - /* Apple address bus */ - input [15:0] RA; - input nWEin; - output RAdir = 1; - output nWEout = 1; - reg [15:0] RAr1; reg nWEr1; - reg [15:0] RAr2; reg nWEr2; - reg [15:0] RAcur; reg nWEcur; - always @(negedge C25M) begin RAr1 <= RA; nWEr1 <= nWE; end - always @(posedge C25M) begin RAr2 <= RAr1; nWEr2 <= nWEr1; end - always @(posedge C25M) begin - if (S==0 && ~PHI0r2) begin - RAcur <= RAr2; - nWEcur <= nWER2; - end - end - - /* Apple select signals */ - wire ROMSpecSEL = RAcur[15:12]==4'hC && RAcur[11:8]!=4'h0; - wire ROMSpecRD = ROMSpecSEL && nWE; - wire RAMSpecSEL = RAcur[15:12]==4'hC && RAcur[11:8]==4'h0 && RAcur[7] && RAcur[7:4]!=4'h8 && RAcur[3:0]==4'h3; - wire RAMSpecRD = RAMSpecSEL && nWE; - wire RAMSpecWR = RAMSpecSEL && ~nWE; - wire SpecRD = ROMSpecRD || RAMSpecRD; - reg RAMRD = 0, RAMWR = 0; - always @(posedge C25M) begin - if (S==5) begin - RAMRD <= RAMSpecRD && DEVSELr2; - RAMWR <= RAMSpecWR && DEVSELr2; - end else if (S==0) begin - RAMRD <= 0; - RAMWR <= 0; - end - end - - /* Apple data bus */ - inout [7:0] RD = RDdir ? 8'bZ : RDout[7:0]; - reg RDdir = 1; - reg [7:0] RDout; - - /* SDRAM data bus */ - inout [7:0] SD = SDOE ? RD[7:0] : 8'bZ; - reg SDOE = 0; - - /* SDRAM address/command */ - output reg [1:0] SBA; - output reg [12:0] SA; - output reg RCKE = 1; - output reg nRCS = 1; - output reg nRAS = 1; - output reg nCAS = 1; - output reg nSWE = 1; - output reg DQMH = 1; - output reg DQML = 1; - - /* SPI flash */ - output reg nFCS = 1; - output reg FCK = 0; - output reg MOSI = MOSIOE ? MOSIout : 1'bZ; - reg MOSIOE = 0; - reg MOSIout; - input MISO; - - /* State counters */ - reg [24:0] FS = 0; - always @(posedge C25M) begin FS <= FS+1; end - reg [2:0] S = 0; - always @(posedge C25M) begin - if (S==0 && PHI0r2 && ~PHI0r3 && ~RESr2 && ~BODr2) S <= 1; - else if (S==0) S <= 0; - else S <= S+1; - end - - /* Refresh state */ - reg RefReady = 0; - reg RefDone = 0; - always @(posedge C25M) begin RefReady <= S==0; end - always @(posedge C25M) begin - if (FS[6:0]==7'h00) RefDone <= 0; - else (S==0 && RefReady && RCKE && ~(PHI0r2 && ~PHI0r3)) RefDone <= 1; - end - - /* Slinky registers */ - reg [24:0] Addr; - wire AddrHSpecSEL = RAcur[3:0]==4'h2; - wire AddrMSpecSEL = RAcur[3:0]==4'h1; - wire AddrLSpecSEL = RAcur[3:0]==4'h0; - always @(posedge C25M) begin - if (S==7 && DEVSELr2) begin - if (AddrHSpecSEL || AddrMSpecSEL || AddrLSpecSEL) begin - Addr[24] <= 1'b0; - end - - if (AddrHSpecSEL) begin - Addr[23:16] <= RD[7:0]; - end else if (RAMRD || RAMWR || - (AddrMSpecSEL && Addr[15] && ~RD[7]) || - (AddrLSpecSEL && Addr[7] && ~RD[7] && Addr[15:8]==8'hFF)) begin - Addr[23:16] <= Addr[23:16]+1; - end - - if (AddrMSpecSEL) begin - Addr[15:8] <= RD[7:0]; - end else if (RAMRD || RAMWR || - (AddrLSpecSEL && Addr[7] && ~RD[7])) begin - Addr[15:8] <= Addr[15:8]+1; - end - - if (AddrLSpecSEL) begin - Addr[7:0] <= RD[7:0]; - end else if (RAMRD || RAMWR) begin - Addr[7:0] <= Addr[7:0]+1; - end - end - end - - always @(posedge C25M) begin - if (S==0) begin - if ((PHI0r2 && ~PHI0r3 && ~RESr2 && ~BODr2 && SpecRD) || - (~RefReady && ~RefDone)) begin - // NOP cken - RCKE <= 1'b1; - nRCS <= 1'b1; - nRAS <= 1'b1; - nCAS <= 1'b1; - nSWE <= 1'b1; - DQMH <= 1'b1; - DQML <= 1'b1; - end else if (RefReady && ~RefDone && RCKE && - ~(PHI0r2 && ~PHI0r3)) begin - // AREF - RCKE <= 1'b1; - nRCS <= 1'b0; - nRAS <= 1'b0; - nCAS <= 1'b0; - nSWE <= 1'b1; - DQMH <= 1'b1; - DQML <= 1'b1; - end else begin - // NOP ckdis - RCKE <= 1'b0; - nRCS <= 1'b1; - nRAS <= 1'b1; - nCAS <= 1'b1; - nSWE <= 1'b1; - DQMH <= 1'b1; - DQML <= 1'b1; - end - end else if (S==4'h1) begin - if (SpecRD) begin - // ACT - RCKE <= 1'b1; - nRCS <= 1'b0; - nRAS <= 1'b0; - nCAS <= 1'b1; - nSWE <= 1'b1; - DQMH <= 1'b1; - DQML <= 1'b1; - - if (RAMSpecRD) begin - RBA[1] <= Addr[24]; - RBA[0] <= Addr[23]; - RA[12:0] <= Addr[22:10]; - end else begin - RBA[1] <= 1'b1; - RBA[0] <= 1'b0; - RA[12:10] <= 3'b000; - RA[9:2] <= Bank[7:0]; - RA[1:0] <= RAcur[11:10]; - end - end else begin - // NOP ckdis - RCKE <= 1'b0; - nRCS <= 1'b1; - nRAS <= 1'b1; - nCAS <= 1'b1; - nSWE <= 1'b1; - DQMH <= 1'b1; - DQML <= 1'b1; - end - end else if (S==4'h2) begin - if (SpecRD) begin - // RD auto-PC - RCKE <= 1'b1; - nRCS <= 1'b0; - nRAS <= 1'b1; - nCAS <= 1'b0; - nSWE <= 1'b1; - - A[12:11] <= 1'b0; // don't care - A[10] <= 1'b1; // auto-precharge - A[9] <= 1'b0; // don't care - if (RAMSpecRD) begin - RBA[1] <= Addr[24]; - RBA[0] <= Addr[23]; - RA[8:0] <= Addr[9:1]; - DQMH <= ~Addr[0]; - DQML <= Addr[0]; - end else /* ROMSpecRD */ begin - RBA[1] <= 1'b1; - RBA[0] <= 1'b0; - RA[8:0] <= RAcur[9:1]; - DQMH <= ~RAcur[0]; - DQML <= RAcur[0]; - end - end else begin - // NOP ckdis - RCKE <= 1'b0; - nRCS <= 1'b1; - nRAS <= 1'b1; - nCAS <= 1'b1; - nSWE <= 1'b1; - DQMH <= 1'b1; - DQML <= 1'b1; - end - end else if (S==4'h3) begin - if (SpecRD) begin - // NOP cken - RCKE <= 1'b1; - nRCS <= 1'b1; - nRAS <= 1'b1; - nCAS <= 1'b1; - nSWE <= 1'b1; - DQMH <= 1'b1; - DQML <= 1'b1; - end else begin - // NOP ckdis - RCKE <= 1'b0; - nRCS <= 1'b1; - nRAS <= 1'b1; - nCAS <= 1'b1; - nSWE <= 1'b1; - DQMH <= 1'b1; - DQML <= 1'b1; - end - end else if (S==4'h4) begin - if (RAMSpecWR) begin - // NOP cken - RCKE <= 1'b1; - nRCS <= 1'b1; - nRAS <= 1'b1; - nCAS <= 1'b1; - nSWE <= 1'b1; - DQMH <= 1'b1; - DQML <= 1'b1; - end else begin - // NOP ckdis - RCKE <= 1'b0; - nRCS <= 1'b1; - nRAS <= 1'b1; - nCAS <= 1'b1; - nSWE <= 1'b1; - DQMH <= 1'b1; - DQML <= 1'b1; - end - end else if (S==4'h5) begin - if (RAMSpecWR && DEVSELr2) begin - // ACT - RCKE <= 1'b1; - nRCS <= 1'b0; - nRAS <= 1'b0; - nCAS <= 1'b1; - nSWE <= 1'b1; - DQMH <= 1'b1; - DQML <= 1'b1; - - BA[1] <= Addr[24]; - BA[0] <= Addr[23]; - A[12:0] <= Addr[22:10]; - end else begin - // NOP ckdis - RCKE <= 1'b0; - nRCS <= 1'b1; - nRAS <= 1'b1; - nCAS <= 1'b1; - nSWE <= 1'b1; - DQMH <= 1'b1; - DQML <= 1'b1; - end - end else if (s==4'h6) begin - if (RAMWR) begin - // WR auto-PC - RCKE <= 1'b1; - nRCS <= 1'b0; - nRAS <= 1'b1; - nCAS <= 1'b0; - nSWE <= 1'b0; - - BA[1] <= Addr[24]; - BA[0] <= Addr[23]; - A[12:11] <= 1'b0; // don't care - A[10] <= 1'b1; // auto-precharge - A[9:0] <= Addr[9:0]; - DQMH <= ~Addr[10]; - DQML <= Addr[10]; - end else begin - // NOP ckdis - RCKE <= 1'b0; - nRCS <= 1'b1; - nRAS <= 1'b1; - nCAS <= 1'b1; - nSWE <= 1'b1; - DQMH <= 1'b1; - DQML <= 1'b1; - end - end else if (S==4'h7) begin - if (RAMSpecWR) begin - // NOP cken - RCKE <= 1'b1; - nRCS <= 1'b1; - nRAS <= 1'b1; - nCAS <= 1'b1; - nSWE <= 1'b1; - DQMH <= 1'b1; - DQML <= 1'b1; - end else begin - // NOP ckdis - RCKE <= 1'b0; - nRCS <= 1'b1; - nRAS <= 1'b1; - nCAS <= 1'b1; - nSWE <= 1'b1; - DQMH <= 1'b1; - DQML <= 1'b1; - end - end - end -endmodule diff --git a/cpld/db/GR8RAM.(0).cnf.cdb b/cpld/db/GR8RAM.(0).cnf.cdb deleted file mode 100755 index 2f6f7e1..0000000 Binary files a/cpld/db/GR8RAM.(0).cnf.cdb and /dev/null differ diff --git a/cpld/db/GR8RAM.(0).cnf.hdb b/cpld/db/GR8RAM.(0).cnf.hdb deleted file mode 100755 index f90561c..0000000 Binary files a/cpld/db/GR8RAM.(0).cnf.hdb and /dev/null differ diff --git a/cpld/db/GR8RAM.(1).cnf.cdb b/cpld/db/GR8RAM.(1).cnf.cdb deleted file mode 100755 index 95f04d0..0000000 Binary files a/cpld/db/GR8RAM.(1).cnf.cdb and /dev/null differ diff --git a/cpld/db/GR8RAM.(1).cnf.hdb b/cpld/db/GR8RAM.(1).cnf.hdb deleted file mode 100755 index dcda520..0000000 Binary files a/cpld/db/GR8RAM.(1).cnf.hdb and /dev/null differ diff --git a/cpld/db/GR8RAM.(2).cnf.cdb b/cpld/db/GR8RAM.(2).cnf.cdb deleted file mode 100755 index 84c3ccf..0000000 Binary files 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b/cpld/db/GR8RAM.(5).cnf.cdb deleted file mode 100755 index 45fbfc7..0000000 Binary files a/cpld/db/GR8RAM.(5).cnf.cdb and /dev/null differ diff --git a/cpld/db/GR8RAM.(5).cnf.hdb b/cpld/db/GR8RAM.(5).cnf.hdb deleted file mode 100755 index 6cae88f..0000000 Binary files a/cpld/db/GR8RAM.(5).cnf.hdb and /dev/null differ diff --git a/cpld/db/GR8RAM.(6).cnf.cdb b/cpld/db/GR8RAM.(6).cnf.cdb deleted file mode 100755 index 9be7ad2..0000000 Binary files a/cpld/db/GR8RAM.(6).cnf.cdb and /dev/null differ diff --git a/cpld/db/GR8RAM.(6).cnf.hdb b/cpld/db/GR8RAM.(6).cnf.hdb deleted file mode 100755 index 82a8084..0000000 Binary files a/cpld/db/GR8RAM.(6).cnf.hdb and /dev/null differ diff --git a/cpld/db/GR8RAM.(7).cnf.cdb b/cpld/db/GR8RAM.(7).cnf.cdb deleted file mode 100755 index f3b3544..0000000 Binary files a/cpld/db/GR8RAM.(7).cnf.cdb and /dev/null differ diff --git a/cpld/db/GR8RAM.(7).cnf.hdb b/cpld/db/GR8RAM.(7).cnf.hdb deleted file mode 100755 index 76e8cba..0000000 Binary files a/cpld/db/GR8RAM.(7).cnf.hdb and /dev/null differ diff --git a/cpld/db/GR8RAM.(8).cnf.cdb b/cpld/db/GR8RAM.(8).cnf.cdb deleted file mode 100755 index 68b1097..0000000 Binary files a/cpld/db/GR8RAM.(8).cnf.cdb and /dev/null differ diff --git a/cpld/db/GR8RAM.(8).cnf.hdb b/cpld/db/GR8RAM.(8).cnf.hdb deleted file mode 100755 index 71408d2..0000000 Binary files a/cpld/db/GR8RAM.(8).cnf.hdb and /dev/null differ diff --git a/cpld/db/GR8RAM.(9).cnf.cdb b/cpld/db/GR8RAM.(9).cnf.cdb deleted file mode 100644 index 54f286d..0000000 Binary files a/cpld/db/GR8RAM.(9).cnf.cdb and /dev/null differ diff --git a/cpld/db/GR8RAM.(9).cnf.hdb b/cpld/db/GR8RAM.(9).cnf.hdb deleted file mode 100644 index 74f352b..0000000 Binary files a/cpld/db/GR8RAM.(9).cnf.hdb and /dev/null differ diff --git a/cpld/db/GR8RAM.ace_cmp.cdb b/cpld/db/GR8RAM.ace_cmp.cdb deleted file mode 100755 index daa5866..0000000 Binary files a/cpld/db/GR8RAM.ace_cmp.cdb and /dev/null differ diff --git a/cpld/db/GR8RAM.ace_cmp.hdb b/cpld/db/GR8RAM.ace_cmp.hdb deleted file mode 100755 index 141b6d6..0000000 Binary files a/cpld/db/GR8RAM.ace_cmp.hdb and /dev/null differ diff --git a/cpld/db/GR8RAM.asm 2.rdb b/cpld/db/GR8RAM.asm 2.rdb deleted file mode 100755 index 7c2e933..0000000 Binary files a/cpld/db/GR8RAM.asm 2.rdb and /dev/null differ diff --git a/cpld/db/GR8RAM.asm 3.rdb b/cpld/db/GR8RAM.asm 3.rdb deleted file mode 100755 index 2383ca3..0000000 Binary files a/cpld/db/GR8RAM.asm 3.rdb and /dev/null differ diff --git a/cpld/db/GR8RAM.asm 4.rdb b/cpld/db/GR8RAM.asm 4.rdb deleted file mode 100755 index 81be8dd..0000000 Binary files a/cpld/db/GR8RAM.asm 4.rdb and /dev/null differ diff --git a/cpld/db/GR8RAM.asm.qmsg b/cpld/db/GR8RAM.asm.qmsg deleted file mode 100755 index 58abdc9..0000000 --- a/cpld/db/GR8RAM.asm.qmsg +++ /dev/null @@ -1,5 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1581829847188 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1581829847188 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Feb 16 00:10:47 2020 " "Processing started: Sun Feb 16 00:10:47 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1581829847188 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1581829847188 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1581829847188 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1581829847318 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4522 " "Peak virtual memory: 4522 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1581829847468 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Feb 16 00:10:47 2020 " "Processing ended: Sun Feb 16 00:10:47 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1581829847468 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1581829847468 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1581829847468 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1581829847468 ""} diff --git a/cpld/db/GR8RAM.asm.rdb b/cpld/db/GR8RAM.asm.rdb deleted file mode 100755 index 3b7d572..0000000 Binary files a/cpld/db/GR8RAM.asm.rdb and /dev/null differ diff --git a/cpld/db/GR8RAM.atom.rvd b/cpld/db/GR8RAM.atom.rvd deleted file mode 100755 index 844d7be..0000000 Binary files a/cpld/db/GR8RAM.atom.rvd and /dev/null differ diff --git a/cpld/db/GR8RAM.cmp 10.rdb b/cpld/db/GR8RAM.cmp 10.rdb deleted file mode 100644 index 004b0f3..0000000 Binary files a/cpld/db/GR8RAM.cmp 10.rdb and /dev/null differ diff --git a/cpld/db/GR8RAM.cmp 11.rdb b/cpld/db/GR8RAM.cmp 11.rdb deleted file mode 100644 index 79b4348..0000000 Binary files a/cpld/db/GR8RAM.cmp 11.rdb and /dev/null differ diff --git a/cpld/db/GR8RAM.cmp 12.rdb b/cpld/db/GR8RAM.cmp 12.rdb deleted file mode 100755 index 3659ab0..0000000 Binary files a/cpld/db/GR8RAM.cmp 12.rdb and /dev/null differ diff --git a/cpld/db/GR8RAM.cmp 13.rdb b/cpld/db/GR8RAM.cmp 13.rdb deleted file mode 100644 index 34b5618..0000000 Binary files a/cpld/db/GR8RAM.cmp 13.rdb and /dev/null differ diff --git a/cpld/db/GR8RAM.cmp 14.rdb b/cpld/db/GR8RAM.cmp 14.rdb deleted file mode 100755 index c9a83ac..0000000 Binary files a/cpld/db/GR8RAM.cmp 14.rdb and /dev/null differ diff --git a/cpld/db/GR8RAM.cmp 15.rdb b/cpld/db/GR8RAM.cmp 15.rdb deleted file mode 100755 index 01429b1..0000000 Binary files a/cpld/db/GR8RAM.cmp 15.rdb and /dev/null differ diff --git a/cpld/db/GR8RAM.cmp 16.rdb b/cpld/db/GR8RAM.cmp 16.rdb deleted file mode 100755 index e59881f..0000000 Binary files a/cpld/db/GR8RAM.cmp 16.rdb and /dev/null differ diff --git a/cpld/db/GR8RAM.cmp 17.rdb b/cpld/db/GR8RAM.cmp 17.rdb deleted file mode 100755 index 785178f..0000000 Binary files a/cpld/db/GR8RAM.cmp 17.rdb and /dev/null differ diff --git a/cpld/db/GR8RAM.cmp 18.rdb b/cpld/db/GR8RAM.cmp 18.rdb deleted file mode 100755 index df3f31f..0000000 Binary files a/cpld/db/GR8RAM.cmp 18.rdb and /dev/null differ diff --git a/cpld/db/GR8RAM.cmp 19.rdb b/cpld/db/GR8RAM.cmp 19.rdb deleted file mode 100755 index 7b14356..0000000 Binary files a/cpld/db/GR8RAM.cmp 19.rdb and /dev/null differ diff --git a/cpld/db/GR8RAM.cmp 2.cdb b/cpld/db/GR8RAM.cmp 2.cdb deleted file mode 100755 index 8ef05ef..0000000 Binary files a/cpld/db/GR8RAM.cmp 2.cdb and /dev/null differ diff --git a/cpld/db/GR8RAM.cmp 2.hdb b/cpld/db/GR8RAM.cmp 2.hdb deleted file mode 100755 index cdcd139..0000000 Binary files a/cpld/db/GR8RAM.cmp 2.hdb and /dev/null differ diff --git a/cpld/db/GR8RAM.cmp 2.rdb b/cpld/db/GR8RAM.cmp 2.rdb deleted file mode 100755 index 580b050..0000000 Binary files a/cpld/db/GR8RAM.cmp 2.rdb and /dev/null differ diff --git a/cpld/db/GR8RAM.cmp 20.rdb b/cpld/db/GR8RAM.cmp 20.rdb deleted file mode 100755 index 4cc4711..0000000 Binary files a/cpld/db/GR8RAM.cmp 20.rdb and /dev/null differ diff --git a/cpld/db/GR8RAM.cmp 21.rdb b/cpld/db/GR8RAM.cmp 21.rdb deleted file mode 100755 index 9c8134b..0000000 Binary files a/cpld/db/GR8RAM.cmp 21.rdb and /dev/null differ diff --git a/cpld/db/GR8RAM.cmp 22.rdb b/cpld/db/GR8RAM.cmp 22.rdb deleted file mode 100755 index 803d184..0000000 Binary files a/cpld/db/GR8RAM.cmp 22.rdb and /dev/null differ diff --git a/cpld/db/GR8RAM.cmp 23.rdb b/cpld/db/GR8RAM.cmp 23.rdb deleted file mode 100755 index 3c1230c..0000000 Binary files a/cpld/db/GR8RAM.cmp 23.rdb and /dev/null differ diff --git a/cpld/db/GR8RAM.cmp 24.rdb b/cpld/db/GR8RAM.cmp 24.rdb deleted file mode 100755 index ce90391..0000000 Binary files a/cpld/db/GR8RAM.cmp 24.rdb and /dev/null differ diff --git a/cpld/db/GR8RAM.cmp 25.rdb b/cpld/db/GR8RAM.cmp 25.rdb deleted file mode 100755 index e319932..0000000 Binary files a/cpld/db/GR8RAM.cmp 25.rdb and /dev/null differ diff --git a/cpld/db/GR8RAM.cmp 26.rdb b/cpld/db/GR8RAM.cmp 26.rdb deleted file mode 100755 index 3c4f6d0..0000000 Binary files a/cpld/db/GR8RAM.cmp 26.rdb and /dev/null differ diff --git a/cpld/db/GR8RAM.cmp 3.cdb b/cpld/db/GR8RAM.cmp 3.cdb deleted file mode 100755 index 143a3e1..0000000 Binary files a/cpld/db/GR8RAM.cmp 3.cdb and /dev/null differ diff --git a/cpld/db/GR8RAM.cmp 3.hdb b/cpld/db/GR8RAM.cmp 3.hdb deleted file mode 100755 index 8237568..0000000 Binary files a/cpld/db/GR8RAM.cmp 3.hdb and /dev/null differ diff --git a/cpld/db/GR8RAM.cmp 3.rdb b/cpld/db/GR8RAM.cmp 3.rdb deleted file mode 100644 index 5793425..0000000 Binary files a/cpld/db/GR8RAM.cmp 3.rdb and /dev/null differ diff --git a/cpld/db/GR8RAM.cmp 4.rdb b/cpld/db/GR8RAM.cmp 4.rdb deleted file mode 100644 index db295dc..0000000 Binary files a/cpld/db/GR8RAM.cmp 4.rdb and /dev/null differ diff --git a/cpld/db/GR8RAM.cmp 5.rdb b/cpld/db/GR8RAM.cmp 5.rdb deleted file mode 100644 index ec74efa..0000000 Binary files a/cpld/db/GR8RAM.cmp 5.rdb and /dev/null differ diff --git a/cpld/db/GR8RAM.cmp 6.rdb b/cpld/db/GR8RAM.cmp 6.rdb deleted file mode 100644 index 3de1f30..0000000 Binary files a/cpld/db/GR8RAM.cmp 6.rdb and /dev/null differ diff --git a/cpld/db/GR8RAM.cmp 7.rdb b/cpld/db/GR8RAM.cmp 7.rdb deleted file mode 100755 index 08da666..0000000 Binary files a/cpld/db/GR8RAM.cmp 7.rdb and /dev/null differ diff --git a/cpld/db/GR8RAM.cmp 8.rdb b/cpld/db/GR8RAM.cmp 8.rdb deleted file mode 100755 index 98b2200..0000000 Binary files a/cpld/db/GR8RAM.cmp 8.rdb and /dev/null differ diff --git a/cpld/db/GR8RAM.cmp 9.rdb b/cpld/db/GR8RAM.cmp 9.rdb deleted file mode 100755 index b6372fe..0000000 Binary files a/cpld/db/GR8RAM.cmp 9.rdb and /dev/null differ diff --git a/cpld/db/GR8RAM.cmp.cdb b/cpld/db/GR8RAM.cmp.cdb deleted file mode 100755 index 39572f8..0000000 Binary files a/cpld/db/GR8RAM.cmp.cdb and /dev/null differ diff --git a/cpld/db/GR8RAM.cmp.hdb b/cpld/db/GR8RAM.cmp.hdb deleted file mode 100755 index e890ff0..0000000 Binary files a/cpld/db/GR8RAM.cmp.hdb and /dev/null differ diff --git a/cpld/db/GR8RAM.cmp.logdb b/cpld/db/GR8RAM.cmp.logdb deleted file mode 100755 index 626799f..0000000 --- a/cpld/db/GR8RAM.cmp.logdb +++ /dev/null @@ -1 +0,0 @@ -v1 diff --git a/cpld/db/GR8RAM.cmp.rdb b/cpld/db/GR8RAM.cmp.rdb deleted file mode 100755 index 814c148..0000000 Binary files a/cpld/db/GR8RAM.cmp.rdb and /dev/null differ diff --git a/cpld/db/GR8RAM.cmp0.ddb b/cpld/db/GR8RAM.cmp0.ddb deleted file mode 100755 index 8040c67..0000000 Binary files a/cpld/db/GR8RAM.cmp0.ddb and /dev/null differ diff --git a/cpld/db/GR8RAM.db_info b/cpld/db/GR8RAM.db_info deleted file mode 100755 index 2c5c586..0000000 --- a/cpld/db/GR8RAM.db_info +++ /dev/null @@ -1,3 +0,0 @@ -Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition -Version_Index = 302049280 -Creation_Time = Sat Feb 15 22:14:18 2020 diff --git a/cpld/db/GR8RAM.eco.cdb b/cpld/db/GR8RAM.eco.cdb deleted file mode 100755 index 325d843..0000000 Binary files a/cpld/db/GR8RAM.eco.cdb and /dev/null differ diff --git a/cpld/db/GR8RAM.fit 2.qmsg b/cpld/db/GR8RAM.fit 2.qmsg deleted file mode 100755 index 3742887..0000000 --- a/cpld/db/GR8RAM.fit 2.qmsg +++ /dev/null @@ -1,3 +0,0 @@ -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1566710684975 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1566710684990 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "287 " "Peak virtual memory: 287 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1566710685506 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 25 01:24:45 2019 " "Processing ended: Sun Aug 25 01:24:45 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1566710685506 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1566710685506 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1566710685506 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1566710685506 ""} diff --git a/cpld/db/GR8RAM.fit 3.qmsg b/cpld/db/GR8RAM.fit 3.qmsg deleted file mode 100755 index a20175b..0000000 --- a/cpld/db/GR8RAM.fit 3.qmsg +++ /dev/null @@ -1,3 +0,0 @@ -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1566710988914 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1566710988930 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "287 " "Peak virtual memory: 287 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1566710989446 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 25 01:29:49 2019 " "Processing ended: Sun Aug 25 01:29:49 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1566710989446 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1566710989446 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1566710989446 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1566710989446 ""} diff --git a/cpld/db/GR8RAM.fit 4.qmsg b/cpld/db/GR8RAM.fit 4.qmsg deleted file mode 100755 index 5daba28..0000000 --- a/cpld/db/GR8RAM.fit 4.qmsg +++ /dev/null @@ -1,5 +0,0 @@ -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1566711499269 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1566711499284 ""} -{ "Error" "EF7K_LAB_TOO_MANY_SEXP" "15 LAB_A 3 " "Can't place 15 sharable expanders in LAB LAB_A because the LAB can contain only 3 sharable expanders" { } { } 0 163057 "Can't place %1!d! sharable expanders in LAB %2!s! because the LAB can contain only %3!d! sharable expanders" 0 0 "Fitter" 0 -1 1566711499362 ""} -{ "Error" "EF7K_FIT_FAIL" "" "Cannot find fit." { } { } 0 163000 "Cannot find fit." 0 0 "Fitter" 0 -1 1566711499362 ""} -{ "Error" "EQEXE_ERROR_COUNT" "Fitter 2 s 1 Quartus II 32-bit " "Quartus II 32-bit Fitter was unsuccessful. 2 errors, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "287 " "Peak virtual memory: 287 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1566711499753 ""} { "Error" "EQEXE_END_BANNER_TIME" "Sun Aug 25 01:38:19 2019 " "Processing ended: Sun Aug 25 01:38:19 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1566711499753 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1566711499753 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1566711499753 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1566711499753 ""} diff --git a/cpld/db/GR8RAM.fit 5.qmsg b/cpld/db/GR8RAM.fit 5.qmsg deleted file mode 100755 index 8df64d3..0000000 --- a/cpld/db/GR8RAM.fit 5.qmsg +++ /dev/null @@ -1,3 +0,0 @@ -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1566712873057 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1566712873088 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "287 " "Peak virtual memory: 287 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1566712873807 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 25 02:01:13 2019 " "Processing ended: Sun Aug 25 02:01:13 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1566712873807 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1566712873807 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1566712873807 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1566712873807 ""} diff --git a/cpld/db/GR8RAM.fit 6.qmsg b/cpld/db/GR8RAM.fit 6.qmsg deleted file mode 100755 index ce3ccbe..0000000 --- a/cpld/db/GR8RAM.fit 6.qmsg +++ /dev/null @@ -1,3 +0,0 @@ -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1566713553094 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1566713553110 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "287 " "Peak virtual memory: 287 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1566713553610 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 25 02:12:33 2019 " "Processing ended: Sun Aug 25 02:12:33 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1566713553610 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1566713553610 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1566713553610 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1566713553610 ""} diff --git a/cpld/db/GR8RAM.fit 7.qmsg b/cpld/db/GR8RAM.fit 7.qmsg deleted file mode 100755 index c10d17e..0000000 --- a/cpld/db/GR8RAM.fit 7.qmsg +++ /dev/null @@ -1,3 +0,0 @@ -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1566716030143 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1566716030190 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "287 " "Peak virtual memory: 287 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1566716031347 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 25 02:53:51 2019 " "Processing ended: Sun Aug 25 02:53:51 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1566716031347 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1566716031347 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1566716031347 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1566716031347 ""} diff --git a/cpld/db/GR8RAM.fit 8.qmsg b/cpld/db/GR8RAM.fit 8.qmsg deleted file mode 100755 index a8f6c9b..0000000 --- a/cpld/db/GR8RAM.fit 8.qmsg +++ /dev/null @@ -1,3 +0,0 @@ -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1566718076312 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1566718076344 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "287 " "Peak virtual memory: 287 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1566718077453 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 25 03:27:57 2019 " "Processing ended: Sun Aug 25 03:27:57 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1566718077453 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1566718077453 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1566718077453 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1566718077453 ""} diff --git a/cpld/db/GR8RAM.fit.qmsg b/cpld/db/GR8RAM.fit.qmsg deleted file mode 100755 index 42a54a6..0000000 --- a/cpld/db/GR8RAM.fit.qmsg +++ /dev/null @@ -1,3 +0,0 @@ -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1581829846147 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1581829846157 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4708 " "Peak virtual memory: 4708 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1581829846367 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Feb 16 00:10:46 2020 " "Processing ended: Sun Feb 16 00:10:46 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1581829846367 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1581829846367 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1581829846367 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1581829846367 ""} diff --git a/cpld/db/GR8RAM.hier_info b/cpld/db/GR8RAM.hier_info deleted file mode 100755 index 24402df..0000000 --- a/cpld/db/GR8RAM.hier_info +++ /dev/null @@ -1,129 +0,0 @@ -|GR8RAM -C7M => always3.IN0 -C7M => CASr.CLK -C7M => CASel.CLK -C7M => RASr.CLK -C7M => IOROMEN.CLK -C7M => REGEN.CLK -C7M => CSEN.CLK -C7M => DBEN.CLK -C7M => Ref[0].CLK -C7M => Ref[1].CLK -C7M => Ref[2].CLK -C7M => Ref[3].CLK -C7M => S[0].CLK -C7M => S[1].CLK -C7M => S[2].CLK -C7M => PHI0seen.CLK -C7M => PHI1reg.CLK -C7M_2 => ~NO_FANOUT~ -Q3 => ~NO_FANOUT~ -PHI0in => ~NO_FANOUT~ -PHI1in => comb.IN0 -PHI1in => PHI1b0_MC.DATAIN -nRES => always1.IN0 -nMode => ~NO_FANOUT~ -A[0] => Equal0.IN7 -A[0] => Equal1.IN7 -A[0] => Equal2.IN7 -A[0] => Equal3.IN7 -A[0] => Equal4.IN7 -A[0] => Equal5.IN7 -A[0] => Equal13.IN21 -A[1] => Equal0.IN6 -A[1] => Equal1.IN6 -A[1] => Equal2.IN6 -A[1] => Equal3.IN6 -A[1] => Equal4.IN6 -A[1] => Equal5.IN6 -A[1] => Equal13.IN20 -A[2] => Equal0.IN5 -A[2] => Equal1.IN5 -A[2] => Equal2.IN5 -A[2] => Equal3.IN5 -A[2] => Equal4.IN5 -A[2] => Equal5.IN5 -A[2] => Equal13.IN19 -A[3] => Equal0.IN4 -A[3] => Equal1.IN4 -A[3] => Equal2.IN4 -A[3] => Equal3.IN4 -A[3] => Equal4.IN4 -A[3] => Equal5.IN4 -A[3] => Equal13.IN18 -A[4] => Equal13.IN17 -A[5] => Equal13.IN16 -A[6] => Equal13.IN15 -A[7] => Equal13.IN14 -A[8] => Equal13.IN13 -A[9] => Equal13.IN12 -A[10] => Equal13.IN11 -A[11] => ~NO_FANOUT~ -A[12] => ~NO_FANOUT~ -A[13] => ~NO_FANOUT~ -A[14] => ~NO_FANOUT~ -A[15] => ~NO_FANOUT~ -RA[0] <= RA.DB_MAX_OUTPUT_PORT_TYPE -RA[1] <= RA.DB_MAX_OUTPUT_PORT_TYPE -RA[2] <= RA.DB_MAX_OUTPUT_PORT_TYPE -RA[3] <= RA.DB_MAX_OUTPUT_PORT_TYPE -RA[4] <= RA.DB_MAX_OUTPUT_PORT_TYPE -RA[5] <= RA.DB_MAX_OUTPUT_PORT_TYPE -RA[6] <= RA.DB_MAX_OUTPUT_PORT_TYPE -RA[7] <= RA.DB_MAX_OUTPUT_PORT_TYPE -RA[8] <= RA.DB_MAX_OUTPUT_PORT_TYPE -RA[9] <= RA.DB_MAX_OUTPUT_PORT_TYPE -RA[10] <= RA.DB_MAX_OUTPUT_PORT_TYPE -nWE => comb.IN0 -nWE => comb.IN0 -nWE => comb.IN0 -nWE => comb.IN0 -nWE => comb.IN0 -nWE => comb.IN0 -nWE => comb.IN0 -nWE => comb.DATAB -nWE => CSEN.IN1 -nWE => RASr.IN1 -nWE => CASel.IN0 -nWE => CASr.IN1 -nWE => CAS0f.IN1 -nWE => CAS1f.IN1 -D[0] <> D[0] -D[1] <> D[1] -D[2] <> D[2] -D[3] <> D[3] -D[4] <> D[4] -D[5] <> D[5] -D[6] <> D[6] -D[7] <> D[7] -RD[0] <> RD[0] -RD[1] <> RD[1] -RD[2] <> RD[2] -RD[3] <> RD[3] -RD[4] <> RD[4] -RD[5] <> RD[5] -RD[6] <> RD[6] -RD[7] <> RD[7] -nDEVSEL => comb.IN0 -nDEVSEL => comb.IN0 -nDEVSEL => comb.IN0 -nDEVSEL => comb.IN0 -nDEVSEL => comb.IN0 -nDEVSEL => comb.IN0 -nDEVSEL => comb.IN0 -nDEVSEL => comb.IN0 -nIOSEL => RA.IN1 -nIOSEL => RA.IN0 -nIOSEL => comb.IN0 -nIOSTRB => RA.IN0 -nIOSTRB => RA.IN1 -nIOSTRB => RA.IN1 -nINH <= nINH.DB_MAX_OUTPUT_PORT_TYPE -nRAS <= comb.DB_MAX_OUTPUT_PORT_TYPE -nCAS0 <= comb.DB_MAX_OUTPUT_PORT_TYPE -nCAS1 <= comb.DB_MAX_OUTPUT_PORT_TYPE -nRCS <= comb.DB_MAX_OUTPUT_PORT_TYPE -nROE <= comb.DB_MAX_OUTPUT_PORT_TYPE -nRWE <= comb.DB_MAX_OUTPUT_PORT_TYPE - - diff --git a/cpld/db/GR8RAM.hif b/cpld/db/GR8RAM.hif deleted file mode 100755 index 6a6bfe1..0000000 Binary files a/cpld/db/GR8RAM.hif and /dev/null differ diff --git a/cpld/db/GR8RAM.ipinfo b/cpld/db/GR8RAM.ipinfo deleted file mode 100755 index fa2304d..0000000 Binary files a/cpld/db/GR8RAM.ipinfo and /dev/null differ diff --git a/cpld/db/GR8RAM.lpc.html b/cpld/db/GR8RAM.lpc.html deleted file mode 100755 index fbc5ab5..0000000 --- a/cpld/db/GR8RAM.lpc.html +++ /dev/null @@ -1,18 +0,0 @@ - - - - - - - - - - - - - - - - - -
HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
diff --git a/cpld/db/GR8RAM.lpc.rdb b/cpld/db/GR8RAM.lpc.rdb deleted file mode 100755 index adf8589..0000000 Binary files a/cpld/db/GR8RAM.lpc.rdb and /dev/null differ diff --git a/cpld/db/GR8RAM.lpc.txt b/cpld/db/GR8RAM.lpc.txt deleted file mode 100755 index a463804..0000000 --- a/cpld/db/GR8RAM.lpc.txt +++ /dev/null @@ -1,5 +0,0 @@ -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Legal Partition Candidates ; -+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ -; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; -+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ diff --git a/cpld/db/GR8RAM.map 2.cdb b/cpld/db/GR8RAM.map 2.cdb deleted file mode 100755 index 7d5677e..0000000 Binary files a/cpld/db/GR8RAM.map 2.cdb and /dev/null differ diff --git a/cpld/db/GR8RAM.map 2.hdb b/cpld/db/GR8RAM.map 2.hdb deleted file mode 100755 index 4083b4d..0000000 Binary files a/cpld/db/GR8RAM.map 2.hdb and /dev/null differ diff --git a/cpld/db/GR8RAM.map 2.rdb b/cpld/db/GR8RAM.map 2.rdb deleted file mode 100755 index 78120b1..0000000 Binary files a/cpld/db/GR8RAM.map 2.rdb and /dev/null differ diff --git a/cpld/db/GR8RAM.map 3.cdb b/cpld/db/GR8RAM.map 3.cdb deleted file mode 100755 index 9d8240d..0000000 Binary files a/cpld/db/GR8RAM.map 3.cdb and /dev/null differ diff --git a/cpld/db/GR8RAM.map 3.hdb b/cpld/db/GR8RAM.map 3.hdb deleted file mode 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b/cpld/db/GR8RAM.map 5.hdb deleted file mode 100755 index 9bbd0ec..0000000 Binary files a/cpld/db/GR8RAM.map 5.hdb and /dev/null differ diff --git a/cpld/db/GR8RAM.map 5.rdb b/cpld/db/GR8RAM.map 5.rdb deleted file mode 100755 index da78e09..0000000 Binary files a/cpld/db/GR8RAM.map 5.rdb and /dev/null differ diff --git a/cpld/db/GR8RAM.map 6.cdb b/cpld/db/GR8RAM.map 6.cdb deleted file mode 100755 index 5e1eb2a..0000000 Binary files a/cpld/db/GR8RAM.map 6.cdb and /dev/null differ diff --git a/cpld/db/GR8RAM.map 6.hdb b/cpld/db/GR8RAM.map 6.hdb deleted file mode 100755 index 296325c..0000000 Binary files a/cpld/db/GR8RAM.map 6.hdb and /dev/null differ diff --git a/cpld/db/GR8RAM.map 6.rdb b/cpld/db/GR8RAM.map 6.rdb deleted file mode 100755 index 5dcbc49..0000000 Binary files a/cpld/db/GR8RAM.map 6.rdb and /dev/null differ diff --git a/cpld/db/GR8RAM.map 7.cdb b/cpld/db/GR8RAM.map 7.cdb deleted file mode 100755 index 89d2c70..0000000 Binary files a/cpld/db/GR8RAM.map 7.cdb and /dev/null differ diff --git a/cpld/db/GR8RAM.map 7.hdb b/cpld/db/GR8RAM.map 7.hdb deleted file mode 100755 index d5b3e70..0000000 Binary files a/cpld/db/GR8RAM.map 7.hdb and /dev/null differ diff --git a/cpld/db/GR8RAM.map 8.hdb b/cpld/db/GR8RAM.map 8.hdb deleted file mode 100755 index f7df467..0000000 Binary files a/cpld/db/GR8RAM.map 8.hdb and /dev/null differ diff --git a/cpld/db/GR8RAM.map 9.hdb b/cpld/db/GR8RAM.map 9.hdb deleted file mode 100755 index e3c0c39..0000000 Binary files a/cpld/db/GR8RAM.map 9.hdb and /dev/null differ diff --git a/cpld/db/GR8RAM.map.cdb b/cpld/db/GR8RAM.map.cdb deleted file mode 100755 index 72f0e87..0000000 Binary files a/cpld/db/GR8RAM.map.cdb and /dev/null differ diff --git a/cpld/db/GR8RAM.map.hdb b/cpld/db/GR8RAM.map.hdb deleted file mode 100755 index 04a5486..0000000 Binary files a/cpld/db/GR8RAM.map.hdb and /dev/null differ diff --git a/cpld/db/GR8RAM.map.logdb b/cpld/db/GR8RAM.map.logdb deleted file mode 100755 index 626799f..0000000 --- a/cpld/db/GR8RAM.map.logdb +++ /dev/null @@ -1 +0,0 @@ -v1 diff --git a/cpld/db/GR8RAM.map.qmsg b/cpld/db/GR8RAM.map.qmsg deleted file mode 100755 index b557bd6..0000000 --- a/cpld/db/GR8RAM.map.qmsg +++ /dev/null @@ -1,33 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1581829844214 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1581829844214 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Feb 16 00:10:44 2020 " "Processing started: Sun Feb 16 00:10:44 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1581829844214 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1581829844214 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1581829844214 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1581829844423 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(52) " "Verilog HDL warning at GR8RAM.v(52): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 52 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1581829844453 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(60) " "Verilog HDL warning at GR8RAM.v(60): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 60 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1581829844453 ""} -{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "GR8RAM.v(200) " "Verilog HDL information at GR8RAM.v(200): always construct contains both blocking and non-blocking assignments" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 200 0 0 } } } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Quartus II" 0 -1 1581829844453 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1581829844453 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1581829844453 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1581829844488 ""} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(30) " "Verilog HDL assignment warning at GR8RAM.v(30): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1581829844493 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 GR8RAM.v(115) " "Verilog HDL assignment warning at GR8RAM.v(115): truncated value with size 32 to match size of target (3)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 115 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1581829844493 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(120) " "Verilog HDL assignment warning at GR8RAM.v(120): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 120 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1581829844493 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(169) " "Verilog HDL assignment warning at GR8RAM.v(169): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 169 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1581829844493 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(174) " "Verilog HDL assignment warning at GR8RAM.v(174): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 174 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1581829844493 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(180) " "Verilog HDL assignment warning at GR8RAM.v(180): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 180 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1581829844493 "|GR8RAM"} -{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "Ref_rtl_0 4 " "Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"Ref_rtl_0\"" { } { } 0 19001 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581829844565 ""} } { } 0 19000 "Inferred %1!d! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1581829844565 ""} -{ "Info" "ILPMS_INFERENCING_SUMMARY" "4 " "Inferred 4 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add0 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add0\"" { } { { "GR8RAM.v" "Add0" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581829844565 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add4 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add4\"" { } { { "GR8RAM.v" "Add4" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581829844565 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add3 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add3\"" { } { { "GR8RAM.v" "Add3" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 169 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581829844565 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add5 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add5\"" { } { { "GR8RAM.v" "Add5" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 180 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581829844565 ""} } { } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1581829844565 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter:Ref_rtl_0 " "Elaborated megafunction instantiation \"lpm_counter:Ref_rtl_0\"" { } { } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581829844593 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_counter:Ref_rtl_0 " "Instantiated megafunction \"lpm_counter:Ref_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 4 " "Parameter \"LPM_WIDTH\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1581829844593 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION UP " "Parameter \"LPM_DIRECTION\" = \"UP\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1581829844593 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_COUNTER " "Parameter \"LPM_TYPE\" = \"LPM_COUNTER\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1581829844593 ""} } { } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1581829844593 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581829844613 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add0 " "Instantiated megafunction \"lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 8 " "Parameter \"LPM_WIDTH\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1581829844613 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Parameter \"LPM_DIRECTION\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1581829844613 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1581829844613 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1581829844613 ""} } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1581829844613 ""} -{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\] lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 260 9 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1581829844623 ""} -{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 86 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1581829844633 ""} -{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 178 5 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1581829844633 ""} -{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|look_add:look_ahead_unit lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|look_add:look_ahead_unit\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 263 4 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1581829844653 ""} -{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:result_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1581829844663 ""} -{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 270 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1581829844665 ""} -{ "Info" "IMLS_MLS_IGNORED_SUMMARY" "32 " "Ignored 32 buffer(s)" { { "Info" "IMLS_MLS_IGNORED_SOFT" "32 " "Ignored 32 SOFT buffer(s)" { } { } 0 13019 "Ignored %1!d! SOFT buffer(s)" 0 0 "Quartus II" 0 -1 1581829844723 ""} } { } 0 13014 "Ignored %1!d! buffer(s)" 0 0 "Quartus II" 0 -1 1581829844723 ""} -{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "C7M " "Promoted clock signal driven by pin \"C7M\" to global clock signal" { } { } 0 280014 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0 "Quartus II" 0 -1 1581829844823 ""} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "nRES " "Promoted clear signal driven by pin \"nRES\" to global clear signal" { } { } 0 280015 "Promoted clear signal driven by pin \"%1!s!\" to global clear signal" 0 0 "Quartus II" 0 -1 1581829844823 ""} } { } 0 280013 "Promoted pin-driven signal(s) to global signal" 0 0 "Quartus II" 0 -1 1581829844823 ""} -{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "9 " "Design contains 9 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "C7M_2 " "No output dependent on input pin \"C7M_2\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581829845013 "|GR8RAM|C7M_2"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "Q3 " "No output dependent on input pin \"Q3\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581829845013 "|GR8RAM|Q3"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "PHI0in " "No output dependent on input pin \"PHI0in\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581829845013 "|GR8RAM|PHI0in"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "nMode " "No output dependent on input pin \"nMode\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 8 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581829845013 "|GR8RAM|nMode"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[11\] " "No output dependent on input pin \"A\[11\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581829845013 "|GR8RAM|A[11]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[12\] " "No output dependent on input pin \"A\[12\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581829845013 "|GR8RAM|A[12]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[13\] " "No output dependent on input pin \"A\[13\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581829845013 "|GR8RAM|A[13]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[14\] " "No output dependent on input pin \"A\[14\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581829845013 "|GR8RAM|A[14]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[15\] " "No output dependent on input pin \"A\[15\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581829845013 "|GR8RAM|A[15]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1581829845013 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "169 " "Implemented 169 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "27 " "Implemented 27 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1581829845013 ""} { "Info" "ICUT_CUT_TM_OPINS" "18 " "Implemented 18 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1581829845013 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Implemented 16 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1581829845013 ""} { "Info" "ICUT_CUT_TM_MCELLS" "107 " "Implemented 107 macrocells" { } { } 0 21063 "Implemented %1!d! macrocells" 0 0 "Quartus II" 0 -1 1581829845013 ""} { "Info" "ICUT_CUT_TM_SEXPS" "1 " "Implemented 1 shareable expanders" { } { } 0 21073 "Implemented %1!d! shareable expanders" 0 0 "Quartus II" 0 -1 1581829845013 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1581829845013 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1581829845053 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 17 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 17 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4587 " "Peak virtual memory: 4587 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1581829845103 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Feb 16 00:10:45 2020 " "Processing ended: Sun Feb 16 00:10:45 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1581829845103 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1581829845103 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1581829845103 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1581829845103 ""} diff --git a/cpld/db/GR8RAM.map.rdb b/cpld/db/GR8RAM.map.rdb deleted file mode 100755 index 0255b6b..0000000 Binary files a/cpld/db/GR8RAM.map.rdb and /dev/null differ diff --git a/cpld/db/GR8RAM.pplq.rdb b/cpld/db/GR8RAM.pplq.rdb deleted file mode 100755 index 6619eee..0000000 Binary files a/cpld/db/GR8RAM.pplq.rdb and /dev/null differ diff --git a/cpld/db/GR8RAM.pre_map.hdb b/cpld/db/GR8RAM.pre_map.hdb deleted file mode 100755 index 926f4f2..0000000 Binary files a/cpld/db/GR8RAM.pre_map.hdb and /dev/null differ diff --git a/cpld/db/GR8RAM.pti_db_list.ddb b/cpld/db/GR8RAM.pti_db_list.ddb deleted file mode 100755 index 89aa9b4..0000000 Binary files a/cpld/db/GR8RAM.pti_db_list.ddb and /dev/null differ diff --git a/cpld/db/GR8RAM.qns b/cpld/db/GR8RAM.qns deleted file mode 100755 index d0fe046..0000000 --- a/cpld/db/GR8RAM.qns +++ /dev/null @@ -1 +0,0 @@ -GR8RAM/done diff --git a/cpld/db/GR8RAM.root_partition.map.reg_db.cdb b/cpld/db/GR8RAM.root_partition.map.reg_db.cdb deleted file mode 100755 index ecea7f4..0000000 Binary files a/cpld/db/GR8RAM.root_partition.map.reg_db.cdb and /dev/null differ diff --git a/cpld/db/GR8RAM.rpp.qmsg b/cpld/db/GR8RAM.rpp.qmsg deleted file mode 100755 index 09d4634..0000000 --- a/cpld/db/GR8RAM.rpp.qmsg +++ /dev/null @@ -1,4 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1565586122544 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Netlist Viewers Preprocess Quartus II 32-bit " "Running Quartus II 32-bit Netlist Viewers Preprocess" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1565586122560 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Aug 12 01:02:02 2019 " "Processing started: Mon Aug 12 01:02:02 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1565586122560 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1565586122560 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_rpp GR8RAM -c GR8RAM --netlist_type=atom " "Command: quartus_rpp GR8RAM -c GR8RAM --netlist_type=atom" { } { } 0 0 "Command: %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1565586122560 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Netlist Viewers Preprocess 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Netlist Viewers Preprocess was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "199 " "Peak virtual memory: 199 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1565586123513 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Aug 12 01:02:03 2019 " "Processing ended: Mon Aug 12 01:02:03 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1565586123513 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1565586123513 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1565586123513 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1565586123513 ""} diff --git a/cpld/db/GR8RAM.rtlv.hdb b/cpld/db/GR8RAM.rtlv.hdb deleted file mode 100755 index 55bee7f..0000000 Binary files a/cpld/db/GR8RAM.rtlv.hdb and /dev/null differ diff --git a/cpld/db/GR8RAM.rtlv_sg.cdb b/cpld/db/GR8RAM.rtlv_sg.cdb deleted file mode 100755 index b79ce10..0000000 Binary files a/cpld/db/GR8RAM.rtlv_sg.cdb and /dev/null differ diff --git a/cpld/db/GR8RAM.rtlv_sg_swap.cdb b/cpld/db/GR8RAM.rtlv_sg_swap.cdb deleted file mode 100755 index bf4c983..0000000 Binary files a/cpld/db/GR8RAM.rtlv_sg_swap.cdb and /dev/null differ diff --git a/cpld/db/GR8RAM.sgate.rvd b/cpld/db/GR8RAM.sgate.rvd deleted file mode 100755 index 761f282..0000000 Binary files a/cpld/db/GR8RAM.sgate.rvd and /dev/null differ diff --git a/cpld/db/GR8RAM.sgate_sm.rvd b/cpld/db/GR8RAM.sgate_sm.rvd deleted file mode 100755 index 9731e5d..0000000 Binary files a/cpld/db/GR8RAM.sgate_sm.rvd and /dev/null differ diff --git a/cpld/db/GR8RAM.sgdiff.cdb b/cpld/db/GR8RAM.sgdiff.cdb deleted file mode 100755 index 0b16d8a..0000000 Binary files a/cpld/db/GR8RAM.sgdiff.cdb and /dev/null differ diff --git a/cpld/db/GR8RAM.sgdiff.hdb b/cpld/db/GR8RAM.sgdiff.hdb deleted file mode 100755 index 2cdd614..0000000 Binary files a/cpld/db/GR8RAM.sgdiff.hdb and /dev/null differ diff --git a/cpld/db/GR8RAM.sld_design_entry.sci b/cpld/db/GR8RAM.sld_design_entry.sci deleted file mode 100755 index 1d6d60f..0000000 Binary files a/cpld/db/GR8RAM.sld_design_entry.sci and /dev/null differ diff --git a/cpld/db/GR8RAM.sld_design_entry_dsc.sci b/cpld/db/GR8RAM.sld_design_entry_dsc.sci deleted file mode 100755 index 1d6d60f..0000000 Binary files a/cpld/db/GR8RAM.sld_design_entry_dsc.sci and /dev/null differ diff --git a/cpld/db/GR8RAM.smart_action.txt b/cpld/db/GR8RAM.smart_action.txt deleted file mode 100755 index c8e8a13..0000000 --- a/cpld/db/GR8RAM.smart_action.txt +++ /dev/null @@ -1 +0,0 @@ -DONE diff --git a/cpld/db/GR8RAM.sta 2.rdb b/cpld/db/GR8RAM.sta 2.rdb deleted file mode 100755 index 2703b56..0000000 Binary files a/cpld/db/GR8RAM.sta 2.rdb and /dev/null differ diff --git a/cpld/db/GR8RAM.sta.qmsg b/cpld/db/GR8RAM.sta.qmsg deleted file mode 100755 index a978006..0000000 --- a/cpld/db/GR8RAM.sta.qmsg +++ /dev/null @@ -1,22 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1581829848408 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1581829848408 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Feb 16 00:10:48 2020 " "Processing started: Sun Feb 16 00:10:48 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1581829848408 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1581829848408 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1581829848408 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1581829848468 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1581829848558 ""} -{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1581829848568 ""} -{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1581829848568 ""} -{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." { } { } 0 335095 "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." 0 0 "Quartus II" 0 -1 1581829848588 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1581829848613 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1581829848614 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M C7M " "create_clock -period 1.000 -name C7M C7M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1581829848614 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1581829848614 ""} -{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1581829848616 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1581829848627 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -47.500 " "Worst-case setup slack is -47.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1581829848630 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1581829848630 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -47.500 -2116.500 C7M " " -47.500 -2116.500 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1581829848630 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1581829848630 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 5.000 " "Worst-case hold slack is 5.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1581829848633 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1581829848633 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 5.000 0.000 C7M " " 5.000 0.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1581829848633 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1581829848633 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1581829848637 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1581829848640 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -4.500 " "Worst-case minimum pulse width slack is -4.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1581829848644 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1581829848644 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.500 -495.000 C7M " " -4.500 -495.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1581829848644 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1581829848644 ""} -{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1581829848693 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1581829848718 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1581829848718 ""} -{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4530 " "Peak virtual memory: 4530 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1581829848889 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Feb 16 00:10:48 2020 " "Processing ended: Sun Feb 16 00:10:48 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1581829848889 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1581829848889 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1581829848889 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1581829848889 ""} diff --git a/cpld/db/GR8RAM.sta.rdb b/cpld/db/GR8RAM.sta.rdb deleted file mode 100755 index 1fea3af..0000000 Binary files a/cpld/db/GR8RAM.sta.rdb and /dev/null differ diff --git a/cpld/db/GR8RAM.sta_cmp.15_slow.tdb b/cpld/db/GR8RAM.sta_cmp.15_slow.tdb deleted file mode 100755 index 220eb03..0000000 Binary files a/cpld/db/GR8RAM.sta_cmp.15_slow.tdb and /dev/null differ diff --git a/cpld/db/GR8RAM.syn_hier_info b/cpld/db/GR8RAM.syn_hier_info deleted file mode 100755 index e69de29..0000000 diff --git a/cpld/db/GR8RAM.tis_db_list.ddb b/cpld/db/GR8RAM.tis_db_list.ddb deleted file mode 100755 index 91bbe10..0000000 Binary files a/cpld/db/GR8RAM.tis_db_list.ddb and /dev/null differ diff --git a/cpld/db/GR8RAM.tmw_info b/cpld/db/GR8RAM.tmw_info deleted file mode 100755 index c91c206..0000000 --- a/cpld/db/GR8RAM.tmw_info +++ /dev/null @@ -1,6 +0,0 @@ -start_full_compilation:s:00:00:06 -start_analysis_synthesis:s:00:00:02-start_full_compilation -start_analysis_elaboration:s-start_full_compilation -start_fitter:s:00:00:01-start_full_compilation -start_assembler:s:00:00:02-start_full_compilation -start_timing_analyzer:s:00:00:01-start_full_compilation diff --git a/cpld/db/add_sub_8ph.tdf b/cpld/db/add_sub_8ph.tdf deleted file mode 100755 index 7cfaee1..0000000 --- a/cpld/db/add_sub_8ph.tdf +++ /dev/null @@ -1,46 +0,0 @@ ---lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="MAX7000S" LPM_DIRECTION="ADD" LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=23 ONE_INPUT_IS_CONSTANT="YES" cin dataa datab result ---VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ VERSION_END - - --- Copyright (C) 1991-2013 Altera Corporation --- Your use of Altera Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Altera Program License --- Subscription Agreement, Altera MegaCore Function License --- Agreement, or other applicable license agreement, including, --- without limitation, that your use is for the sole purpose of --- programming logic devices manufactured by Altera and sold by --- Altera or its authorized distributors. Please refer to the --- applicable agreement for further details. - - -FUNCTION carry_sum (cin, sin) -RETURNS ( cout, sout); - ---synthesis_resources = lut 24 -SUBDESIGN add_sub_8ph -( - cin : input; - dataa[22..0] : input; - datab[22..0] : input; - result[22..0] : output; -) -VARIABLE - add_sub_cella[22..0] : carry_sum; - external_cin_cell : carry_sum; - datab_node[22..0] : WIRE; - main_cin_wire : WIRE; - -BEGIN - add_sub_cella[].cin = ( ((dataa[22..22] & datab_node[22..22]) # ((dataa[22..22] # datab_node[22..22]) & add_sub_cella[21].cout)), ((dataa[21..21] & datab_node[21..21]) # ((dataa[21..21] # datab_node[21..21]) & add_sub_cella[20].cout)), ((dataa[20..20] & datab_node[20..20]) # ((dataa[20..20] # datab_node[20..20]) & add_sub_cella[19].cout)), ((dataa[19..19] & datab_node[19..19]) # ((dataa[19..19] # datab_node[19..19]) & add_sub_cella[18].cout)), ((dataa[18..18] & datab_node[18..18]) # ((dataa[18..18] # datab_node[18..18]) & add_sub_cella[17].cout)), ((dataa[17..17] & datab_node[17..17]) # ((dataa[17..17] # datab_node[17..17]) & add_sub_cella[16].cout)), ((dataa[16..16] & datab_node[16..16]) # ((dataa[16..16] # datab_node[16..16]) & add_sub_cella[15].cout)), ((dataa[15..15] & datab_node[15..15]) # ((dataa[15..15] # datab_node[15..15]) & add_sub_cella[14].cout)), ((dataa[14..14] & datab_node[14..14]) # ((dataa[14..14] # datab_node[14..14]) & add_sub_cella[13].cout)), ((dataa[13..13] & datab_node[13..13]) # ((dataa[13..13] # datab_node[13..13]) & add_sub_cella[12].cout)), ((dataa[12..12] & datab_node[12..12]) # ((dataa[12..12] # datab_node[12..12]) & add_sub_cella[11].cout)), ((dataa[11..11] & datab_node[11..11]) # ((dataa[11..11] # datab_node[11..11]) & add_sub_cella[10].cout)), ((dataa[10..10] & datab_node[10..10]) # ((dataa[10..10] # datab_node[10..10]) & add_sub_cella[9].cout)), ((dataa[9..9] & datab_node[9..9]) # ((dataa[9..9] # datab_node[9..9]) & add_sub_cella[8].cout)), ((dataa[8..8] & datab_node[8..8]) # ((dataa[8..8] # datab_node[8..8]) & add_sub_cella[7].cout)), ((dataa[7..7] & datab_node[7..7]) # ((dataa[7..7] # datab_node[7..7]) & add_sub_cella[6].cout)), ((dataa[6..6] & datab_node[6..6]) # ((dataa[6..6] # datab_node[6..6]) & add_sub_cella[5].cout)), ((dataa[5..5] & datab_node[5..5]) # ((dataa[5..5] # datab_node[5..5]) & add_sub_cella[4].cout)), ((dataa[4..4] & datab_node[4..4]) # ((dataa[4..4] # datab_node[4..4]) & add_sub_cella[3].cout)), ((dataa[3..3] & datab_node[3..3]) # ((dataa[3..3] # datab_node[3..3]) & add_sub_cella[2].cout)), ((dataa[2..2] & datab_node[2..2]) # ((dataa[2..2] # datab_node[2..2]) & add_sub_cella[1].cout)), ((dataa[1..1] & datab_node[1..1]) # ((dataa[1..1] # datab_node[1..1]) & add_sub_cella[0].cout)), ((dataa[0..0] & datab_node[0..0]) # ((dataa[0..0] # datab_node[0..0]) & main_cin_wire))); - add_sub_cella[].sin = ( ((dataa[22..22] $ datab_node[22..22]) $ add_sub_cella[21].cout), ((dataa[21..21] $ datab_node[21..21]) $ add_sub_cella[20].cout), ((dataa[20..20] $ datab_node[20..20]) $ add_sub_cella[19].cout), ((dataa[19..19] $ datab_node[19..19]) $ add_sub_cella[18].cout), ((dataa[18..18] $ datab_node[18..18]) $ add_sub_cella[17].cout), ((dataa[17..17] $ datab_node[17..17]) $ add_sub_cella[16].cout), ((dataa[16..16] $ datab_node[16..16]) $ add_sub_cella[15].cout), ((dataa[15..15] $ datab_node[15..15]) $ add_sub_cella[14].cout), ((dataa[14..14] $ datab_node[14..14]) $ add_sub_cella[13].cout), ((dataa[13..13] $ datab_node[13..13]) $ add_sub_cella[12].cout), ((dataa[12..12] $ datab_node[12..12]) $ add_sub_cella[11].cout), ((dataa[11..11] $ datab_node[11..11]) $ add_sub_cella[10].cout), ((dataa[10..10] $ datab_node[10..10]) $ add_sub_cella[9].cout), ((dataa[9..9] $ datab_node[9..9]) $ add_sub_cella[8].cout), ((dataa[8..8] $ datab_node[8..8]) $ add_sub_cella[7].cout), ((dataa[7..7] $ datab_node[7..7]) $ add_sub_cella[6].cout), ((dataa[6..6] $ datab_node[6..6]) $ add_sub_cella[5].cout), ((dataa[5..5] $ datab_node[5..5]) $ add_sub_cella[4].cout), ((dataa[4..4] $ datab_node[4..4]) $ add_sub_cella[3].cout), ((dataa[3..3] $ datab_node[3..3]) $ add_sub_cella[2].cout), ((dataa[2..2] $ datab_node[2..2]) $ add_sub_cella[1].cout), ((dataa[1..1] $ datab_node[1..1]) $ add_sub_cella[0].cout), ((dataa[0..0] $ datab_node[0..0]) $ main_cin_wire)); - external_cin_cell.cin = cin; - external_cin_cell.sin = B"0"; - datab_node[] = datab[]; - main_cin_wire = external_cin_cell.cout; - result[] = add_sub_cella[].sout; -END; ---VALID FILE diff --git a/cpld/db/add_sub_9ph.tdf b/cpld/db/add_sub_9ph.tdf deleted file mode 100644 index b488188..0000000 --- a/cpld/db/add_sub_9ph.tdf +++ /dev/null @@ -1,46 +0,0 @@ ---lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="MAX7000S" LPM_DIRECTION="ADD" LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=15 ONE_INPUT_IS_CONSTANT="YES" cin dataa datab result ---VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ VERSION_END - - --- Copyright (C) 1991-2013 Altera Corporation --- Your use of Altera Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Altera Program License --- Subscription Agreement, Altera MegaCore Function License --- Agreement, or other applicable license agreement, including, --- without limitation, that your use is for the sole purpose of --- programming logic devices manufactured by Altera and sold by --- Altera or its authorized distributors. Please refer to the --- applicable agreement for further details. - - -FUNCTION carry_sum (cin, sin) -RETURNS ( cout, sout); - ---synthesis_resources = lut 16 -SUBDESIGN add_sub_9ph -( - cin : input; - dataa[14..0] : input; - datab[14..0] : input; - result[14..0] : output; -) -VARIABLE - add_sub_cella[14..0] : carry_sum; - external_cin_cell : carry_sum; - datab_node[14..0] : WIRE; - main_cin_wire : WIRE; - -BEGIN - add_sub_cella[].cin = ( ((dataa[14..14] & datab_node[14..14]) # ((dataa[14..14] # datab_node[14..14]) & add_sub_cella[13].cout)), ((dataa[13..13] & datab_node[13..13]) # ((dataa[13..13] # datab_node[13..13]) & add_sub_cella[12].cout)), ((dataa[12..12] & datab_node[12..12]) # ((dataa[12..12] # datab_node[12..12]) & add_sub_cella[11].cout)), ((dataa[11..11] & datab_node[11..11]) # ((dataa[11..11] # datab_node[11..11]) & add_sub_cella[10].cout)), ((dataa[10..10] & datab_node[10..10]) # ((dataa[10..10] # datab_node[10..10]) & add_sub_cella[9].cout)), ((dataa[9..9] & datab_node[9..9]) # ((dataa[9..9] # datab_node[9..9]) & add_sub_cella[8].cout)), ((dataa[8..8] & datab_node[8..8]) # ((dataa[8..8] # datab_node[8..8]) & add_sub_cella[7].cout)), ((dataa[7..7] & datab_node[7..7]) # ((dataa[7..7] # datab_node[7..7]) & add_sub_cella[6].cout)), ((dataa[6..6] & datab_node[6..6]) # ((dataa[6..6] # datab_node[6..6]) & add_sub_cella[5].cout)), ((dataa[5..5] & datab_node[5..5]) # ((dataa[5..5] # datab_node[5..5]) & add_sub_cella[4].cout)), ((dataa[4..4] & datab_node[4..4]) # ((dataa[4..4] # datab_node[4..4]) & add_sub_cella[3].cout)), ((dataa[3..3] & datab_node[3..3]) # ((dataa[3..3] # datab_node[3..3]) & add_sub_cella[2].cout)), ((dataa[2..2] & datab_node[2..2]) # ((dataa[2..2] # datab_node[2..2]) & add_sub_cella[1].cout)), ((dataa[1..1] & datab_node[1..1]) # ((dataa[1..1] # datab_node[1..1]) & add_sub_cella[0].cout)), ((dataa[0..0] & datab_node[0..0]) # ((dataa[0..0] # datab_node[0..0]) & main_cin_wire))); - add_sub_cella[].sin = ( ((dataa[14..14] $ datab_node[14..14]) $ add_sub_cella[13].cout), ((dataa[13..13] $ datab_node[13..13]) $ add_sub_cella[12].cout), ((dataa[12..12] $ datab_node[12..12]) $ add_sub_cella[11].cout), ((dataa[11..11] $ datab_node[11..11]) $ add_sub_cella[10].cout), ((dataa[10..10] $ datab_node[10..10]) $ add_sub_cella[9].cout), ((dataa[9..9] $ datab_node[9..9]) $ add_sub_cella[8].cout), ((dataa[8..8] $ datab_node[8..8]) $ add_sub_cella[7].cout), ((dataa[7..7] $ datab_node[7..7]) $ add_sub_cella[6].cout), ((dataa[6..6] $ datab_node[6..6]) $ add_sub_cella[5].cout), ((dataa[5..5] $ datab_node[5..5]) $ add_sub_cella[4].cout), ((dataa[4..4] $ datab_node[4..4]) $ add_sub_cella[3].cout), ((dataa[3..3] $ datab_node[3..3]) $ add_sub_cella[2].cout), ((dataa[2..2] $ datab_node[2..2]) $ add_sub_cella[1].cout), ((dataa[1..1] $ datab_node[1..1]) $ add_sub_cella[0].cout), ((dataa[0..0] $ datab_node[0..0]) $ main_cin_wire)); - external_cin_cell.cin = cin; - external_cin_cell.sin = B"0"; - datab_node[] = datab[]; - main_cin_wire = external_cin_cell.cout; - result[] = add_sub_cella[].sout; -END; ---VALID FILE diff --git a/cpld/db/add_sub_aph.tdf b/cpld/db/add_sub_aph.tdf deleted file mode 100755 index 9065fb1..0000000 --- a/cpld/db/add_sub_aph.tdf +++ /dev/null @@ -1,46 +0,0 @@ ---lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="MAX7000S" LPM_DIRECTION="ADD" LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=16 ONE_INPUT_IS_CONSTANT="YES" cin dataa datab result ---VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:40:SJ cbx_lpm_add_sub 2013:06:12:18:03:40:SJ cbx_mgl 2013:06:12:18:04:42:SJ cbx_stratix 2013:06:12:18:03:40:SJ cbx_stratixii 2013:06:12:18:03:40:SJ VERSION_END - - --- Copyright (C) 1991-2013 Altera Corporation --- Your use of Altera Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Altera Program License --- Subscription Agreement, Altera MegaCore Function License --- Agreement, or other applicable license agreement, including, --- without limitation, that your use is for the sole purpose of --- programming logic devices manufactured by Altera and sold by --- Altera or its authorized distributors. Please refer to the --- applicable agreement for further details. - - -FUNCTION carry_sum (cin, sin) -RETURNS ( cout, sout); - ---synthesis_resources = lut 17 -SUBDESIGN add_sub_aph -( - cin : input; - dataa[15..0] : input; - datab[15..0] : input; - result[15..0] : output; -) -VARIABLE - add_sub_cella[15..0] : carry_sum; - external_cin_cell : carry_sum; - datab_node[15..0] : WIRE; - main_cin_wire : WIRE; - -BEGIN - add_sub_cella[].cin = ( ((dataa[15..15] & datab_node[15..15]) # ((dataa[15..15] # datab_node[15..15]) & add_sub_cella[14].cout)), ((dataa[14..14] & datab_node[14..14]) # ((dataa[14..14] # datab_node[14..14]) & add_sub_cella[13].cout)), ((dataa[13..13] & datab_node[13..13]) # ((dataa[13..13] # datab_node[13..13]) & add_sub_cella[12].cout)), ((dataa[12..12] & datab_node[12..12]) # ((dataa[12..12] # datab_node[12..12]) & add_sub_cella[11].cout)), ((dataa[11..11] & datab_node[11..11]) # ((dataa[11..11] # datab_node[11..11]) & add_sub_cella[10].cout)), ((dataa[10..10] & datab_node[10..10]) # ((dataa[10..10] # datab_node[10..10]) & add_sub_cella[9].cout)), ((dataa[9..9] & datab_node[9..9]) # ((dataa[9..9] # datab_node[9..9]) & add_sub_cella[8].cout)), ((dataa[8..8] & datab_node[8..8]) # ((dataa[8..8] # datab_node[8..8]) & add_sub_cella[7].cout)), ((dataa[7..7] & datab_node[7..7]) # ((dataa[7..7] # datab_node[7..7]) & add_sub_cella[6].cout)), ((dataa[6..6] & datab_node[6..6]) # ((dataa[6..6] # datab_node[6..6]) & add_sub_cella[5].cout)), ((dataa[5..5] & datab_node[5..5]) # ((dataa[5..5] # datab_node[5..5]) & add_sub_cella[4].cout)), ((dataa[4..4] & datab_node[4..4]) # ((dataa[4..4] # datab_node[4..4]) & add_sub_cella[3].cout)), ((dataa[3..3] & datab_node[3..3]) # ((dataa[3..3] # datab_node[3..3]) & add_sub_cella[2].cout)), ((dataa[2..2] & datab_node[2..2]) # ((dataa[2..2] # datab_node[2..2]) & add_sub_cella[1].cout)), ((dataa[1..1] & datab_node[1..1]) # ((dataa[1..1] # datab_node[1..1]) & add_sub_cella[0].cout)), ((dataa[0..0] & datab_node[0..0]) # ((dataa[0..0] # datab_node[0..0]) & main_cin_wire))); - add_sub_cella[].sin = ( ((dataa[15..15] $ datab_node[15..15]) $ add_sub_cella[14].cout), ((dataa[14..14] $ datab_node[14..14]) $ add_sub_cella[13].cout), ((dataa[13..13] $ datab_node[13..13]) $ add_sub_cella[12].cout), ((dataa[12..12] $ datab_node[12..12]) $ add_sub_cella[11].cout), ((dataa[11..11] $ datab_node[11..11]) $ add_sub_cella[10].cout), ((dataa[10..10] $ datab_node[10..10]) $ add_sub_cella[9].cout), ((dataa[9..9] $ datab_node[9..9]) $ add_sub_cella[8].cout), ((dataa[8..8] $ datab_node[8..8]) $ add_sub_cella[7].cout), ((dataa[7..7] $ datab_node[7..7]) $ add_sub_cella[6].cout), ((dataa[6..6] $ datab_node[6..6]) $ add_sub_cella[5].cout), ((dataa[5..5] $ datab_node[5..5]) $ add_sub_cella[4].cout), ((dataa[4..4] $ datab_node[4..4]) $ add_sub_cella[3].cout), ((dataa[3..3] $ datab_node[3..3]) $ add_sub_cella[2].cout), ((dataa[2..2] $ datab_node[2..2]) $ add_sub_cella[1].cout), ((dataa[1..1] $ datab_node[1..1]) $ add_sub_cella[0].cout), ((dataa[0..0] $ datab_node[0..0]) $ main_cin_wire)); - external_cin_cell.cin = cin; - external_cin_cell.sin = B"0"; - datab_node[] = datab[]; - main_cin_wire = external_cin_cell.cout; - result[] = add_sub_cella[].sout; -END; ---VALID FILE diff --git a/cpld/db/add_sub_qnh.tdf b/cpld/db/add_sub_qnh.tdf deleted file mode 100644 index e863563..0000000 --- a/cpld/db/add_sub_qnh.tdf +++ /dev/null @@ -1,46 +0,0 @@ ---lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="MAX7000S" LPM_DIRECTION="ADD" LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=7 ONE_INPUT_IS_CONSTANT="YES" cin dataa datab result ---VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ VERSION_END - - --- Copyright (C) 1991-2013 Altera Corporation --- Your use of Altera Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Altera Program License --- Subscription Agreement, Altera MegaCore Function License --- Agreement, or other applicable license agreement, including, --- without limitation, that your use is for the sole purpose of --- programming logic devices manufactured by Altera and sold by --- Altera or its authorized distributors. Please refer to the --- applicable agreement for further details. - - -FUNCTION carry_sum (cin, sin) -RETURNS ( cout, sout); - ---synthesis_resources = lut 8 -SUBDESIGN add_sub_qnh -( - cin : input; - dataa[6..0] : input; - datab[6..0] : input; - result[6..0] : output; -) -VARIABLE - add_sub_cella[6..0] : carry_sum; - external_cin_cell : carry_sum; - datab_node[6..0] : WIRE; - main_cin_wire : WIRE; - -BEGIN - add_sub_cella[].cin = ( ((dataa[6..6] & datab_node[6..6]) # ((dataa[6..6] # datab_node[6..6]) & add_sub_cella[5].cout)), ((dataa[5..5] & datab_node[5..5]) # ((dataa[5..5] # datab_node[5..5]) & add_sub_cella[4].cout)), ((dataa[4..4] & datab_node[4..4]) # ((dataa[4..4] # datab_node[4..4]) & add_sub_cella[3].cout)), ((dataa[3..3] & datab_node[3..3]) # ((dataa[3..3] # datab_node[3..3]) & add_sub_cella[2].cout)), ((dataa[2..2] & datab_node[2..2]) # ((dataa[2..2] # datab_node[2..2]) & add_sub_cella[1].cout)), ((dataa[1..1] & datab_node[1..1]) # ((dataa[1..1] # datab_node[1..1]) & add_sub_cella[0].cout)), ((dataa[0..0] & datab_node[0..0]) # ((dataa[0..0] # datab_node[0..0]) & main_cin_wire))); - add_sub_cella[].sin = ( ((dataa[6..6] $ datab_node[6..6]) $ add_sub_cella[5].cout), ((dataa[5..5] $ datab_node[5..5]) $ add_sub_cella[4].cout), ((dataa[4..4] $ datab_node[4..4]) $ add_sub_cella[3].cout), ((dataa[3..3] $ datab_node[3..3]) $ add_sub_cella[2].cout), ((dataa[2..2] $ datab_node[2..2]) $ add_sub_cella[1].cout), ((dataa[1..1] $ datab_node[1..1]) $ add_sub_cella[0].cout), ((dataa[0..0] $ datab_node[0..0]) $ main_cin_wire)); - external_cin_cell.cin = cin; - external_cin_cell.sin = B"0"; - datab_node[] = datab[]; - main_cin_wire = external_cin_cell.cout; - result[] = add_sub_cella[].sout; -END; ---VALID FILE diff --git a/cpld/db/add_sub_rnh.tdf b/cpld/db/add_sub_rnh.tdf deleted file mode 100644 index 9106a37..0000000 --- a/cpld/db/add_sub_rnh.tdf +++ /dev/null @@ -1,46 +0,0 @@ ---lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="MAX7000S" LPM_DIRECTION="ADD" LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=8 ONE_INPUT_IS_CONSTANT="YES" cin dataa datab result ---VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ VERSION_END - - --- Copyright (C) 1991-2013 Altera Corporation --- Your use of Altera Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Altera Program License --- Subscription Agreement, Altera MegaCore Function License --- Agreement, or other applicable license agreement, including, --- without limitation, that your use is for the sole purpose of --- programming logic devices manufactured by Altera and sold by --- Altera or its authorized distributors. Please refer to the --- applicable agreement for further details. - - -FUNCTION carry_sum (cin, sin) -RETURNS ( cout, sout); - ---synthesis_resources = lut 9 -SUBDESIGN add_sub_rnh -( - cin : input; - dataa[7..0] : input; - datab[7..0] : input; - result[7..0] : output; -) -VARIABLE - add_sub_cella[7..0] : carry_sum; - external_cin_cell : carry_sum; - datab_node[7..0] : WIRE; - main_cin_wire : WIRE; - -BEGIN - add_sub_cella[].cin = ( ((dataa[7..7] & datab_node[7..7]) # ((dataa[7..7] # datab_node[7..7]) & add_sub_cella[6].cout)), ((dataa[6..6] & datab_node[6..6]) # ((dataa[6..6] # datab_node[6..6]) & add_sub_cella[5].cout)), ((dataa[5..5] & datab_node[5..5]) # ((dataa[5..5] # datab_node[5..5]) & add_sub_cella[4].cout)), ((dataa[4..4] & datab_node[4..4]) # ((dataa[4..4] # datab_node[4..4]) & add_sub_cella[3].cout)), ((dataa[3..3] & datab_node[3..3]) # ((dataa[3..3] # datab_node[3..3]) & add_sub_cella[2].cout)), ((dataa[2..2] & datab_node[2..2]) # ((dataa[2..2] # datab_node[2..2]) & add_sub_cella[1].cout)), ((dataa[1..1] & datab_node[1..1]) # ((dataa[1..1] # datab_node[1..1]) & add_sub_cella[0].cout)), ((dataa[0..0] & datab_node[0..0]) # ((dataa[0..0] # datab_node[0..0]) & main_cin_wire))); - add_sub_cella[].sin = ( ((dataa[7..7] $ datab_node[7..7]) $ add_sub_cella[6].cout), ((dataa[6..6] $ datab_node[6..6]) $ add_sub_cella[5].cout), ((dataa[5..5] $ datab_node[5..5]) $ add_sub_cella[4].cout), ((dataa[4..4] $ datab_node[4..4]) $ add_sub_cella[3].cout), ((dataa[3..3] $ datab_node[3..3]) $ add_sub_cella[2].cout), ((dataa[2..2] $ datab_node[2..2]) $ add_sub_cella[1].cout), ((dataa[1..1] $ datab_node[1..1]) $ add_sub_cella[0].cout), ((dataa[0..0] $ datab_node[0..0]) $ main_cin_wire)); - external_cin_cell.cin = cin; - external_cin_cell.sin = B"0"; - datab_node[] = datab[]; - main_cin_wire = external_cin_cell.cout; - result[] = add_sub_cella[].sout; -END; ---VALID FILE diff --git a/cpld/db/logic_util_heursitic.dat b/cpld/db/logic_util_heursitic.dat deleted file mode 100755 index e69de29..0000000 diff --git a/cpld/db/prev_cmp_GR8RAM.qmsg b/cpld/db/prev_cmp_GR8RAM.qmsg deleted file mode 100755 index 4710847..0000000 --- a/cpld/db/prev_cmp_GR8RAM.qmsg +++ /dev/null @@ -1,71 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1581827612363 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1581827612363 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Feb 15 23:33:32 2020 " "Processing started: Sat Feb 15 23:33:32 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1581827612363 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1581827612363 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1581827612363 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1581827612572 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(52) " "Verilog HDL warning at GR8RAM.v(52): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 52 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1581827612602 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(60) " "Verilog HDL warning at GR8RAM.v(60): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 60 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1581827612602 ""} -{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "GR8RAM.v(200) " "Verilog HDL information at GR8RAM.v(200): always construct contains both blocking and non-blocking assignments" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 200 0 0 } } } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Quartus II" 0 -1 1581827612602 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1581827612607 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1581827612607 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1581827612642 ""} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(30) " "Verilog HDL assignment warning at GR8RAM.v(30): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1581827612642 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 GR8RAM.v(115) " "Verilog HDL assignment warning at GR8RAM.v(115): truncated value with size 32 to match size of target (3)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 115 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1581827612642 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(120) " "Verilog HDL assignment warning at GR8RAM.v(120): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 120 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1581827612642 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(169) " "Verilog HDL assignment warning at GR8RAM.v(169): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 169 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1581827612642 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(174) " "Verilog HDL assignment warning at GR8RAM.v(174): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 174 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1581827612642 "|GR8RAM"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(180) " "Verilog HDL assignment warning at GR8RAM.v(180): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 180 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1581827612642 "|GR8RAM"} -{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "Ref_rtl_0 4 " "Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"Ref_rtl_0\"" { } { } 0 19001 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581827612737 ""} } { } 0 19000 "Inferred %1!d! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1581827612737 ""} -{ "Info" "ILPMS_INFERENCING_SUMMARY" "4 " "Inferred 4 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add0 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add0\"" { } { { "GR8RAM.v" "Add0" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581827612743 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add4 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add4\"" { } { { "GR8RAM.v" "Add4" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581827612743 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add3 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add3\"" { } { { "GR8RAM.v" "Add3" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 169 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581827612743 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add5 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add5\"" { } { { "GR8RAM.v" "Add5" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 180 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581827612743 ""} } { } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1581827612743 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter:Ref_rtl_0 " "Elaborated megafunction instantiation \"lpm_counter:Ref_rtl_0\"" { } { } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581827612763 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_counter:Ref_rtl_0 " "Instantiated megafunction \"lpm_counter:Ref_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 4 " "Parameter \"LPM_WIDTH\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1581827612763 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION UP " "Parameter \"LPM_DIRECTION\" = \"UP\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1581827612763 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_COUNTER " "Parameter \"LPM_TYPE\" = \"LPM_COUNTER\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1581827612763 ""} } { } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1581827612763 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581827612787 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add0 " "Instantiated megafunction \"lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 8 " "Parameter \"LPM_WIDTH\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1581827612787 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Parameter \"LPM_DIRECTION\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1581827612787 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1581827612787 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1581827612787 ""} } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1581827612787 ""} -{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\] lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 260 9 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1581827612802 ""} -{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 86 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1581827612813 ""} -{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 178 5 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1581827612813 ""} -{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|look_add:look_ahead_unit lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|look_add:look_ahead_unit\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 263 4 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1581827612827 ""} -{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:result_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1581827612832 ""} -{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 270 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1581827612832 ""} -{ "Info" "IMLS_MLS_IGNORED_SUMMARY" "32 " "Ignored 32 buffer(s)" { { "Info" "IMLS_MLS_IGNORED_SOFT" "32 " "Ignored 32 SOFT buffer(s)" { } { } 0 13019 "Ignored %1!d! SOFT buffer(s)" 0 0 "Quartus II" 0 -1 1581827612902 ""} } { } 0 13014 "Ignored %1!d! buffer(s)" 0 0 "Quartus II" 0 -1 1581827612902 ""} -{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "C7M " "Promoted clock signal driven by pin \"C7M\" to global clock signal" { } { } 0 280014 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0 "Quartus II" 0 -1 1581827613002 ""} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "nRES " "Promoted clear signal driven by pin \"nRES\" to global clear signal" { } { } 0 280015 "Promoted clear signal driven by pin \"%1!s!\" to global clear signal" 0 0 "Quartus II" 0 -1 1581827613002 ""} } { } 0 280013 "Promoted pin-driven signal(s) to global signal" 0 0 "Quartus II" 0 -1 1581827613002 ""} -{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "9 " "Design contains 9 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "C7M_2 " "No output dependent on input pin \"C7M_2\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581827613192 "|GR8RAM|C7M_2"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "Q3 " "No output dependent on input pin \"Q3\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581827613192 "|GR8RAM|Q3"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "PHI0in " "No output dependent on input pin \"PHI0in\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581827613192 "|GR8RAM|PHI0in"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "nMode " "No output dependent on input pin \"nMode\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 8 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581827613192 "|GR8RAM|nMode"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[11\] " "No output dependent on input pin \"A\[11\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581827613192 "|GR8RAM|A[11]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[12\] " "No output dependent on input pin \"A\[12\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581827613192 "|GR8RAM|A[12]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[13\] " "No output dependent on input pin \"A\[13\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581827613192 "|GR8RAM|A[13]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[14\] " "No output dependent on input pin \"A\[14\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581827613192 "|GR8RAM|A[14]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[15\] " "No output dependent on input pin \"A\[15\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1581827613192 "|GR8RAM|A[15]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1581827613192 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "169 " "Implemented 169 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "27 " "Implemented 27 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1581827613192 ""} { "Info" "ICUT_CUT_TM_OPINS" "18 " "Implemented 18 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1581827613192 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Implemented 16 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1581827613192 ""} { "Info" "ICUT_CUT_TM_MCELLS" "107 " "Implemented 107 macrocells" { } { } 0 21063 "Implemented %1!d! macrocells" 0 0 "Quartus II" 0 -1 1581827613192 ""} { "Info" "ICUT_CUT_TM_SEXPS" "1 " "Implemented 1 shareable expanders" { } { } 0 21073 "Implemented %1!d! shareable expanders" 0 0 "Quartus II" 0 -1 1581827613192 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1581827613192 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1581827613227 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 17 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 17 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4588 " "Peak virtual memory: 4588 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1581827613272 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Feb 15 23:33:33 2020 " "Processing ended: Sat Feb 15 23:33:33 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1581827613272 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1581827613272 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1581827613272 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1581827613272 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1581827614218 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 64-Bit " "Running Quartus II 64-Bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1581827614218 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Feb 15 23:33:33 2020 " "Processing started: Sat Feb 15 23:33:33 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1581827614218 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1581827614218 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1581827614218 ""} -{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1581827614268 ""} -{ "Info" "0" "" "Project = GR8RAM" { } { } 0 0 "Project = GR8RAM" 0 0 "Fitter" 0 0 1581827614278 ""} -{ "Info" "0" "" "Revision = GR8RAM" { } { } 0 0 "Revision = GR8RAM" 0 0 "Fitter" 0 0 1581827614278 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1581827614308 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1581827614318 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4708 " "Peak virtual memory: 4708 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1581827614528 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Feb 15 23:33:34 2020 " "Processing ended: Sat Feb 15 23:33:34 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1581827614528 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1581827614528 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1581827614528 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1581827614528 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1581827615368 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1581827615368 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Feb 15 23:33:35 2020 " "Processing started: Sat Feb 15 23:33:35 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1581827615368 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1581827615368 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1581827615368 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1581827615488 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4522 " "Peak virtual memory: 4522 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1581827615618 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Feb 15 23:33:35 2020 " "Processing ended: Sat Feb 15 23:33:35 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1581827615618 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1581827615618 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1581827615618 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1581827615618 ""} -{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1581827616228 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1581827616568 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1581827616568 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Feb 15 23:33:36 2020 " "Processing started: Sat Feb 15 23:33:36 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1581827616568 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1581827616568 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1581827616568 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1581827616618 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1581827616718 ""} -{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1581827616718 ""} -{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1581827616718 ""} -{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." { } { } 0 335095 "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." 0 0 "Quartus II" 0 -1 1581827616748 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1581827616758 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1581827616758 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M C7M " "create_clock -period 1.000 -name C7M C7M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1581827616758 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1581827616758 ""} -{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1581827616758 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1581827616768 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -47.500 " "Worst-case setup slack is -47.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1581827616778 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1581827616778 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -47.500 -2116.500 C7M " " -47.500 -2116.500 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1581827616778 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1581827616778 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 5.000 " "Worst-case hold slack is 5.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1581827616778 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1581827616778 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 5.000 0.000 C7M " " 5.000 0.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1581827616778 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1581827616778 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1581827616778 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1581827616788 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -4.500 " "Worst-case minimum pulse width slack is -4.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1581827616788 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1581827616788 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.500 -495.000 C7M " " -4.500 -495.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1581827616788 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1581827616788 ""} -{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1581827616828 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1581827616848 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1581827616848 ""} -{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4530 " "Peak virtual memory: 4530 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1581827617058 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Feb 15 23:33:37 2020 " "Processing ended: Sat Feb 15 23:33:37 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1581827617058 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1581827617058 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1581827617058 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1581827617058 ""} -{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 22 s " "Quartus II Full Compilation was successful. 0 errors, 22 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1581827617678 ""} diff --git a/cpld/incremental_db/README b/cpld/incremental_db/README deleted file mode 100755 index 9f62dcd..0000000 --- a/cpld/incremental_db/README +++ /dev/null @@ -1,11 +0,0 @@ -This folder contains data for incremental compilation. - -The compiled_partitions sub-folder contains previous compilation results for each partition. -As long as this folder is preserved, incremental compilation results from earlier compiles -can be re-used. To perform a clean compilation from source files for all partitions, both -the db and incremental_db folder should be removed. - -The imported_partitions sub-folder contains the last imported QXP for each imported partition. -As long as this folder is preserved, imported partitions will be automatically re-imported -when the db or incremental_db/compiled_partitions folders are removed. - diff --git a/cpld/incremental_db/compiled_partitions/GR8RAM.db_info b/cpld/incremental_db/compiled_partitions/GR8RAM.db_info deleted file mode 100755 index 9fc0c8b..0000000 --- a/cpld/incremental_db/compiled_partitions/GR8RAM.db_info +++ /dev/null @@ -1,3 +0,0 @@ -Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition -Version_Index = 302049280 -Creation_Time = Thu Aug 08 14:59:29 2019 diff --git a/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt b/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt deleted file mode 100755 index 87e67ad..0000000 Binary files a/cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt and /dev/null differ diff --git a/cpld/output_files/GR8RAM.asm.rpt b/cpld/output_files/GR8RAM.asm.rpt deleted file mode 100755 index 2805c21..0000000 --- a/cpld/output_files/GR8RAM.asm.rpt +++ /dev/null @@ -1,111 +0,0 @@ -Assembler report for GR8RAM -Sun Feb 16 00:10:47 2020 -Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Assembler Summary - 3. Assembler Settings - 4. Assembler Generated Files - 5. Assembler Device Options: C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.pof - 6. Assembler Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2013 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+---------------------------------------------------------------+ -; Assembler Summary ; -+-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Sun Feb 16 00:10:47 2020 ; -; Revision Name ; GR8RAM ; -; Top-level Entity Name ; GR8RAM ; -; Family ; MAX7000S ; -; Device ; EPM7128SLC84-15 ; -+-----------------------+---------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------+ -; Assembler Settings ; -+-----------------------------------------------------------------------------+----------+---------------+ -; Option ; Setting ; Default Value ; -+-----------------------------------------------------------------------------+----------+---------------+ -; Use smart compilation ; Off ; Off ; -; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; -; Enable compact report table ; Off ; Off ; -; Compression mode ; Off ; Off ; -; Clock source for configuration device ; Internal ; Internal ; -; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ; -; Divide clock frequency by ; 1 ; 1 ; -; Auto user code ; Off ; Off ; -; Security bit ; Off ; Off ; -; Use configuration device ; On ; On ; -; Configuration device auto user code ; Off ; Off ; -; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ; -; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ; -; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ; -; Hexadecimal Output File start address ; 0 ; 0 ; -; Hexadecimal Output File count direction ; Up ; Up ; -; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ; -; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ; -; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ; -; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ; -+-----------------------------------------------------------------------------+----------+---------------+ - - -+--------------------------------------------------------------------+ -; Assembler Generated Files ; -+--------------------------------------------------------------------+ -; File Name ; -+--------------------------------------------------------------------+ -; C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.pof ; -+--------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------+ -; Assembler Device Options: C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.pof ; -+----------------+-----------------------------------------------------------------------------+ -; Option ; Setting ; -+----------------+-----------------------------------------------------------------------------+ -; Device ; EPM7128SLC84-15 ; -; JTAG usercode ; 0x00000000 ; -; Checksum ; 0x0017BCCA ; -+----------------+-----------------------------------------------------------------------------+ - - -+--------------------+ -; Assembler Messages ; -+--------------------+ -Info: ******************************************************************* -Info: Running Quartus II 64-Bit Assembler - Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - Info: Processing started: Sun Feb 16 00:10:47 2020 -Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM -Info (115030): Assembler is generating device programming files -Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 4522 megabytes - Info: Processing ended: Sun Feb 16 00:10:47 2020 - Info: Elapsed time: 00:00:00 - Info: Total CPU time (on all processors): 00:00:00 - - diff --git a/cpld/output_files/GR8RAM.cdf b/cpld/output_files/GR8RAM.cdf deleted file mode 100644 index 41503fd..0000000 --- a/cpld/output_files/GR8RAM.cdf +++ /dev/null @@ -1,13 +0,0 @@ -/* Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition */ -JedecChain; - FileRevision(JESD32A); - DefaultMfr(6E); - - P ActionCode(Vfy) - Device PartName(EPM7128SL84) Path("C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/") File("GR8RAM.pof") MfrSpec(OpMask(2)); - -ChainEnd; - -AlteraBegin; - ChainType(JTAG); -AlteraEnd; diff --git a/cpld/output_files/GR8RAM.done b/cpld/output_files/GR8RAM.done deleted file mode 100755 index e3a5ff0..0000000 --- a/cpld/output_files/GR8RAM.done +++ /dev/null @@ -1 +0,0 @@ -Sun Feb 16 00:10:49 2020 diff --git a/cpld/output_files/GR8RAM.fit.rpt b/cpld/output_files/GR8RAM.fit.rpt deleted file mode 100755 index 43b5c3f..0000000 --- a/cpld/output_files/GR8RAM.fit.rpt +++ /dev/null @@ -1,733 +0,0 @@ -Fitter report for GR8RAM -Sun Feb 16 00:10:46 2020 -Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Fitter Summary - 3. Fitter Settings - 4. Parallel Compilation - 5. Pin-Out File - 6. Fitter Resource Usage Summary - 7. Input Pins - 8. Output Pins - 9. Bidir Pins - 10. All Package Pins - 11. I/O Standard - 12. Dedicated Inputs I/O - 13. Output Pin Default Load For Reported TCO - 14. Fitter Resource Utilization by Entity - 15. Control Signals - 16. Global & Other Fast Signals - 17. Non-Global High Fan-Out Signals - 18. Other Routing Usage Summary - 19. LAB External Interconnect - 20. LAB Macrocells - 21. Shareable Expander - 22. Logic Cell Interconnection - 23. Fitter Device Options - 24. Fitter Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2013 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+-----------------------------------------------------------------------------+ -; Fitter Summary ; -+---------------------------+-------------------------------------------------+ -; Fitter Status ; Successful - Sun Feb 16 00:10:46 2020 ; -; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; -; Revision Name ; GR8RAM ; -; Top-level Entity Name ; GR8RAM ; -; Family ; MAX7000S ; -; Device ; EPM7128SLC84-15 ; -; Timing Models ; Final ; -; Total macrocells ; 107 / 128 ( 84 % ) ; -; Total pins ; 65 / 68 ( 96 % ) ; -+---------------------------+-------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------+ -; Fitter Settings ; -+----------------------------------------------------------------------------+-----------------------+---------------+ -; Option ; Setting ; Default Value ; -+----------------------------------------------------------------------------+-----------------------+---------------+ -; Device ; EPM7128SLC84-15 ; ; -; Optimize Timing for ECOs ; On ; Off ; -; Regenerate full fit report during ECO compiles ; On ; Off ; -; Optimize IOC Register Placement for Timing ; Pack All IO Registers ; Normal ; -; Slow Slew Rate ; On ; Off ; -; Fitter Effort ; Standard Fit ; Auto Fit ; -; Use smart compilation ; Off ; Off ; -; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; -; Enable compact report table ; Off ; Off ; -; Optimize Multi-Corner Timing ; Off ; Off ; -; Fitter Initial Placement Seed ; 1 ; 1 ; -; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; -+----------------------------------------------------------------------------+-----------------------+---------------+ - - -Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. -+-------------------------------------+ -; Parallel Compilation ; -+----------------------------+--------+ -; Processors ; Number ; -+----------------------------+--------+ -; Number detected on machine ; 8 ; -; Maximum allowed ; 1 ; -+----------------------------+--------+ - - -+--------------+ -; Pin-Out File ; -+--------------+ -The pin-out file can be found in C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.pin. - - -+---------------------------------------------------+ -; Fitter Resource Usage Summary ; -+------------------------------+--------------------+ -; Resource ; Usage ; -+------------------------------+--------------------+ -; Logic cells ; 107 / 128 ( 84 % ) ; -; Registers ; 55 / 128 ( 43 % ) ; -; Number of pterms used ; 281 ; -; I/O pins ; 65 / 68 ( 96 % ) ; -; -- Clock pins ; 2 / 2 ( 100 % ) ; -; -- Dedicated input pins ; 2 / 2 ( 100 % ) ; -; ; ; -; Global signals ; 2 ; -; Shareable expanders ; 1 / 128 ( < 1 % ) ; -; Parallel expanders ; 0 / 120 ( 0 % ) ; -; Cells using turbo bit ; 17 / 128 ( 13 % ) ; -; Maximum fan-out ; 55 ; -; Highest non-global fan-out ; 54 ; -; Total fan-out ; 855 ; -; Average fan-out ; 4.94 ; -+------------------------------+--------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------+ -; Input Pins ; -+---------+-------+----------+-----+-----------------------+--------------------+--------+----------------+--------------+----------------------+ -; Name ; Pin # ; I/O Bank ; LAB ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; I/O Standard ; Location assigned by ; -+---------+-------+----------+-----+-----------------------+--------------------+--------+----------------+--------------+----------------------+ -; A[0] ; 75 ; -- ; 8 ; 15 ; 0 ; no ; no ; TTL ; User ; -; A[10] ; 11 ; -- ; 1 ; 1 ; 0 ; no ; no ; TTL ; User ; -; A[11] ; 12 ; -- ; 1 ; 0 ; 0 ; no ; no ; TTL ; User ; -; A[12] ; 15 ; -- ; 2 ; 0 ; 0 ; no ; no ; TTL ; User ; -; A[13] ; 16 ; -- ; 2 ; 0 ; 0 ; no ; no ; TTL ; User ; -; A[14] ; 17 ; -- ; 2 ; 0 ; 0 ; no ; no ; TTL ; User ; -; A[15] ; 18 ; -- ; 2 ; 0 ; 0 ; no ; no ; TTL ; User ; -; A[1] ; 76 ; -- ; 8 ; 15 ; 0 ; no ; no ; TTL ; User ; -; A[2] ; 77 ; -- ; 8 ; 15 ; 0 ; no ; no ; TTL ; User ; -; A[3] ; 79 ; -- ; 8 ; 15 ; 0 ; no ; no ; TTL ; User ; -; A[4] ; 80 ; -- ; 8 ; 1 ; 0 ; no ; no ; TTL ; User ; -; A[5] ; 81 ; -- ; 8 ; 1 ; 0 ; no ; no ; TTL ; User ; -; A[6] ; 4 ; -- ; 1 ; 1 ; 0 ; no ; no ; TTL ; User ; -; A[7] ; 5 ; -- ; 1 ; 1 ; 0 ; no ; no ; TTL ; User ; -; A[8] ; 9 ; -- ; 1 ; 1 ; 0 ; no ; no ; TTL ; User ; -; A[9] ; 10 ; -- ; 1 ; 1 ; 0 ; no ; no ; TTL ; User ; -; C7M ; 83 ; -- ; -- ; 55 ; 0 ; yes ; no ; TTL ; User ; -; C7M_2 ; 84 ; -- ; -- ; 0 ; 0 ; no ; no ; TTL ; User ; -; PHI0in ; 8 ; -- ; 1 ; 0 ; 0 ; no ; no ; TTL ; User ; -; PHI1in ; 2 ; -- ; -- ; 2 ; 0 ; no ; no ; TTL ; User ; -; Q3 ; 6 ; -- ; 1 ; 0 ; 0 ; no ; no ; TTL ; User ; -; nDEVSEL ; 21 ; -- ; 2 ; 15 ; 0 ; no ; no ; TTL ; User ; -; nIOSEL ; 74 ; -- ; 8 ; 12 ; 0 ; no ; no ; TTL ; User ; -; nIOSTRB ; 24 ; -- ; 3 ; 11 ; 0 ; no ; no ; TTL ; User ; -; nMode ; 44 ; -- ; 5 ; 0 ; 0 ; no ; no ; TTL ; User ; -; nRES ; 1 ; -- ; -- ; 40 ; 0 ; yes ; no ; TTL ; User ; -; nWE ; 20 ; -- ; 2 ; 16 ; 0 ; no ; no ; TTL ; User ; -+---------+-------+----------+-----+-----------------------+--------------------+--------+----------------+--------------+----------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Output Pins ; -+--------+-------+----------+-----+-----------------+----------------+------------+---------------+--------------+----------------------+-------+----------------------+---------------------+ -; Name ; Pin # ; I/O Bank ; LAB ; Output Register ; Slow Slew Rate ; Open Drain ; TRI Primitive ; I/O Standard ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ; -+--------+-------+----------+-----+-----------------+----------------+------------+---------------+--------------+----------------------+-------+----------------------+---------------------+ -; RA[0] ; 52 ; -- ; 5 ; no ; yes ; no ; no ; TTL ; User ; 10 pF ; - ; - ; -; RA[10] ; 48 ; -- ; 5 ; no ; yes ; no ; no ; TTL ; User ; 10 pF ; - ; - ; -; RA[1] ; 54 ; -- ; 6 ; no ; yes ; no ; no ; TTL ; User ; 10 pF ; - ; - ; -; RA[2] ; 50 ; -- ; 5 ; no ; yes ; no ; no ; TTL ; User ; 10 pF ; - ; - ; -; RA[3] ; 49 ; -- ; 5 ; no ; yes ; no ; no ; TTL ; User ; 10 pF ; - ; - ; -; RA[4] ; 55 ; -- ; 6 ; no ; yes ; no ; no ; TTL ; User ; 10 pF ; - ; - ; -; RA[5] ; 51 ; -- ; 5 ; no ; yes ; no ; no ; TTL ; User ; 10 pF ; - ; - ; -; RA[6] ; 57 ; -- ; 6 ; no ; yes ; no ; no ; TTL ; User ; 10 pF ; - ; - ; -; RA[7] ; 56 ; -- ; 6 ; no ; yes ; no ; no ; TTL ; User ; 10 pF ; - ; - ; -; RA[8] ; 58 ; -- ; 6 ; no ; yes ; no ; no ; TTL ; User ; 10 pF ; - ; - ; -; RA[9] ; 46 ; -- ; 5 ; no ; yes ; no ; no ; TTL ; User ; 10 pF ; - ; - ; -; nCAS0 ; 39 ; -- ; 4 ; no ; yes ; no ; no ; TTL ; User ; 10 pF ; - ; - ; -; nCAS1 ; 40 ; -- ; 4 ; no ; yes ; no ; no ; TTL ; User ; 10 pF ; - ; - ; -; nINH ; 22 ; -- ; 2 ; no ; yes ; yes ; no ; TTL ; User ; 10 pF ; - ; - ; -; nRAS ; 60 ; -- ; 6 ; no ; yes ; no ; no ; TTL ; User ; 10 pF ; - ; - ; -; nRCS ; 41 ; -- ; 4 ; no ; yes ; no ; no ; TTL ; User ; 10 pF ; - ; - ; -; nROE ; 45 ; -- ; 5 ; no ; yes ; no ; no ; TTL ; User ; 10 pF ; - ; - ; -; nRWE ; 67 ; -- ; 7 ; no ; yes ; no ; no ; TTL ; User ; 10 pF ; - ; - ; -+--------+-------+----------+-----+-----------------+----------------+------------+---------------+--------------+----------------------+-------+----------------------+---------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Bidir Pins ; -+-------+-------+----------+-----+-----------------------+--------------------+--------+----------------+-----------------+----------------+------------+--------------+----------------------+-------+----------------------+---------------------+ -; Name ; Pin # ; I/O Bank ; LAB ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Output Register ; Slow Slew Rate ; Open Drain ; I/O Standard ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ; -+-------+-------+----------+-----+-----------------------+--------------------+--------+----------------+-----------------+----------------+------------+--------------+----------------------+-------+----------------------+---------------------+ -; D[0] ; 36 ; -- ; 4 ; 6 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; DOE~5 ; - ; -; D[1] ; 35 ; -- ; 4 ; 6 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; DOE~5 ; - ; -; D[2] ; 34 ; -- ; 4 ; 6 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; DOE~5 ; - ; -; D[3] ; 33 ; -- ; 4 ; 6 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; DOE~5 ; - ; -; D[4] ; 29 ; -- ; 3 ; 6 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; DOE~5 ; - ; -; D[5] ; 28 ; -- ; 3 ; 6 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; DOE~5 ; - ; -; D[6] ; 27 ; -- ; 3 ; 6 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; DOE~5 ; - ; -; D[7] ; 25 ; -- ; 3 ; 8 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; DOE~5 ; - ; -; RD[0] ; 73 ; -- ; 8 ; 1 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; RDOE~1 ; - ; -; RD[1] ; 70 ; -- ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; RDOE~1 ; - ; -; RD[2] ; 69 ; -- ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; RDOE~1 ; - ; -; RD[3] ; 68 ; -- ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; RDOE~1 ; - ; -; RD[4] ; 65 ; -- ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; RDOE~1 ; - ; -; RD[5] ; 63 ; -- ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; RDOE~1 ; - ; -; RD[6] ; 64 ; -- ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; RDOE~1 ; - ; -; RD[7] ; 61 ; -- ; 6 ; 1 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; RDOE~1 ; - ; -+-------+-------+----------+-----+-----------------------+--------------------+--------+----------------+-----------------+----------------+------------+--------------+----------------------+-------+----------------------+---------------------+ - - -+-------------------------------------------------------------------------------------------------------+ -; All Package Pins ; -+----------+------------+----------+----------------+--------+--------------+---------+-----------------+ -; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; User Assignment ; -+----------+------------+----------+----------------+--------+--------------+---------+-----------------+ -; 1 ; 0 ; -- ; nRES ; input ; TTL ; ; Y ; -; 2 ; 1 ; -- ; PHI1in ; input ; TTL ; ; Y ; -; 3 ; 2 ; -- ; VCCINT ; power ; ; 5.0V ; ; -; 4 ; 3 ; -- ; A[6] ; input ; TTL ; ; Y ; -; 5 ; 4 ; -- ; A[7] ; input ; TTL ; ; Y ; -; 6 ; 5 ; -- ; Q3 ; input ; TTL ; ; Y ; -; 7 ; 6 ; -- ; GND ; gnd ; ; ; ; -; 8 ; 7 ; -- ; PHI0in ; input ; TTL ; ; Y ; -; 9 ; 8 ; -- ; A[8] ; input ; TTL ; ; Y ; -; 10 ; 9 ; -- ; A[9] ; input ; TTL ; ; Y ; -; 11 ; 10 ; -- ; A[10] ; input ; TTL ; ; Y ; -; 12 ; 11 ; -- ; A[11] ; input ; TTL ; ; Y ; -; 13 ; 12 ; -- ; VCCIO ; power ; ; 5.0V ; ; -; 14 ; 13 ; -- ; TDI ; input ; TTL ; ; N ; -; 15 ; 14 ; -- ; A[12] ; input ; TTL ; ; Y ; -; 16 ; 15 ; -- ; A[13] ; input ; TTL ; ; Y ; -; 17 ; 16 ; -- ; A[14] ; input ; TTL ; ; Y ; -; 18 ; 17 ; -- ; A[15] ; input ; TTL ; ; Y ; -; 19 ; 18 ; -- ; GND ; gnd ; ; ; ; -; 20 ; 19 ; -- ; nWE ; input ; TTL ; ; Y ; -; 21 ; 20 ; -- ; nDEVSEL ; input ; TTL ; ; Y ; -; 22 ; 21 ; -- ; nINH ; output ; TTL ; ; Y ; -; 23 ; 22 ; -- ; TMS ; input ; TTL ; ; N ; -; 24 ; 23 ; -- ; nIOSTRB ; input ; TTL ; ; Y ; -; 25 ; 24 ; -- ; D[7] ; bidir ; TTL ; ; Y ; -; 26 ; 25 ; -- ; VCCIO ; power ; ; 5.0V ; ; -; 27 ; 26 ; -- ; D[6] ; bidir ; TTL ; ; Y ; -; 28 ; 27 ; -- ; D[5] ; bidir ; TTL ; ; Y ; -; 29 ; 28 ; -- ; D[4] ; bidir ; TTL ; ; Y ; -; 30 ; 29 ; -- ; RESERVED ; ; ; ; ; -; 31 ; 30 ; -- ; RESERVED ; ; ; ; ; -; 32 ; 31 ; -- ; GND ; gnd ; ; ; ; -; 33 ; 32 ; -- ; D[3] ; bidir ; TTL ; ; Y ; -; 34 ; 33 ; -- ; D[2] ; bidir ; TTL ; ; Y ; -; 35 ; 34 ; -- ; D[1] ; bidir ; TTL ; ; Y ; -; 36 ; 35 ; -- ; D[0] ; bidir ; TTL ; ; Y ; -; 37 ; 36 ; -- ; RESERVED ; ; ; ; ; -; 38 ; 37 ; -- ; VCCIO ; power ; ; 5.0V ; ; -; 39 ; 38 ; -- ; nCAS0 ; output ; TTL ; ; Y ; -; 40 ; 39 ; -- ; nCAS1 ; output ; TTL ; ; Y ; -; 41 ; 40 ; -- ; nRCS ; output ; TTL ; ; Y ; -; 42 ; 41 ; -- ; GND ; gnd ; ; ; ; -; 43 ; 42 ; -- ; VCCINT ; power ; ; 5.0V ; ; -; 44 ; 43 ; -- ; nMode ; input ; TTL ; ; Y ; -; 45 ; 44 ; -- ; nROE ; output ; TTL ; ; Y ; -; 46 ; 45 ; -- ; RA[9] ; output ; TTL ; ; Y ; -; 47 ; 46 ; -- ; GND ; gnd ; ; ; ; -; 48 ; 47 ; -- ; RA[10] ; output ; TTL ; ; Y ; -; 49 ; 48 ; -- ; RA[3] ; output ; TTL ; ; Y ; -; 50 ; 49 ; -- ; RA[2] ; output ; TTL ; ; Y ; -; 51 ; 50 ; -- ; RA[5] ; output ; TTL ; ; Y ; -; 52 ; 51 ; -- ; RA[0] ; output ; TTL ; ; Y ; -; 53 ; 52 ; -- ; VCCIO ; power ; ; 5.0V ; ; -; 54 ; 53 ; -- ; RA[1] ; output ; TTL ; ; Y ; -; 55 ; 54 ; -- ; RA[4] ; output ; TTL ; ; Y ; -; 56 ; 55 ; -- ; RA[7] ; output ; TTL ; ; Y ; -; 57 ; 56 ; -- ; RA[6] ; output ; TTL ; ; Y ; -; 58 ; 57 ; -- ; RA[8] ; output ; TTL ; ; Y ; -; 59 ; 58 ; -- ; GND ; gnd ; ; ; ; -; 60 ; 59 ; -- ; nRAS ; output ; TTL ; ; Y ; -; 61 ; 60 ; -- ; RD[7] ; bidir ; TTL ; ; Y ; -; 62 ; 61 ; -- ; TCK ; input ; TTL ; ; N ; -; 63 ; 62 ; -- ; RD[5] ; bidir ; TTL ; ; Y ; -; 64 ; 63 ; -- ; RD[6] ; bidir ; TTL ; ; Y ; -; 65 ; 64 ; -- ; RD[4] ; bidir ; TTL ; ; Y ; -; 66 ; 65 ; -- ; VCCIO ; power ; ; 5.0V ; ; -; 67 ; 66 ; -- ; nRWE ; output ; TTL ; ; Y ; -; 68 ; 67 ; -- ; RD[3] ; bidir ; TTL ; ; Y ; -; 69 ; 68 ; -- ; RD[2] ; bidir ; TTL ; ; Y ; -; 70 ; 69 ; -- ; RD[1] ; bidir ; TTL ; ; Y ; -; 71 ; 70 ; -- ; TDO ; output ; TTL ; ; N ; -; 72 ; 71 ; -- ; GND ; gnd ; ; ; ; -; 73 ; 72 ; -- ; RD[0] ; bidir ; TTL ; ; Y ; -; 74 ; 73 ; -- ; nIOSEL ; input ; TTL ; ; Y ; -; 75 ; 74 ; -- ; A[0] ; input ; TTL ; ; Y ; -; 76 ; 75 ; -- ; A[1] ; input ; TTL ; ; Y ; -; 77 ; 76 ; -- ; A[2] ; input ; TTL ; ; Y ; -; 78 ; 77 ; -- ; VCCIO ; power ; ; 5.0V ; ; -; 79 ; 78 ; -- ; A[3] ; input ; TTL ; ; Y ; -; 80 ; 79 ; -- ; A[4] ; input ; TTL ; ; Y ; -; 81 ; 80 ; -- ; A[5] ; input ; TTL ; ; Y ; -; 82 ; 81 ; -- ; GND ; gnd ; ; ; ; -; 83 ; 82 ; -- ; C7M ; input ; TTL ; ; Y ; -; 84 ; 83 ; -- ; C7M_2 ; input ; TTL ; ; Y ; -+----------+------------+----------+----------------+--------+--------------+---------+-----------------+ -Note: Pin directions (input, output or bidir) are based on device operating in user mode. - - -+--------------------------------------------------------------------------------------------------+ -; I/O Standard ; -+--------------+------------+----------------------+-------------------+-------------------+-------+ -; I/O Standard ; Input Vref ; Dedicated Input Pins ; Pins in I/O Bank1 ; Pins in I/O Bank2 ; Total ; -+--------------+------------+----------------------+-------------------+-------------------+-------+ -; TTL ; - ; 4 ; 0 ; 0 ; 4 ; -+--------------+------------+----------------------+-------------------+-------------------+-------+ - - -+----------------------------------------------------------------------+ -; Dedicated Inputs I/O ; -+--------+-------+-------+-------+--------------+------------+---------+ -; Name ; Pin # ; Type ; VCCIO ; I/O Standard ; Input Vref ; Current ; -+--------+-------+-------+-------+--------------+------------+---------+ -; C7M ; 83 ; Input ; -- ; TTL ; - ; 0 mA ; -; C7M_2 ; 84 ; Input ; -- ; TTL ; - ; 0 mA ; -; PHI1in ; 2 ; Input ; -- ; TTL ; - ; 0 mA ; -; nRES ; 1 ; Input ; -- ; TTL ; - ; 0 mA ; -+--------+-------+-------+-------+--------------+------------+---------+ - - -+-----------------------------------------------+ -; Output Pin Default Load For Reported TCO ; -+--------------+-------+------------------------+ -; I/O Standard ; Load ; Termination Resistance ; -+--------------+-------+------------------------+ -; 3.3-V LVTTL ; 10 pF ; Not Available ; -; 3.3-V LVCMOS ; 10 pF ; Not Available ; -; TTL ; 10 pF ; Not Available ; -+--------------+-------+------------------------+ -Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables. - - -+-----------------------------------------------------------------------------------------------+ -; Fitter Resource Utilization by Entity ; -+----------------------------+------------+------+-------------------------------+--------------+ -; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ; Library Name ; -+----------------------------+------------+------+-------------------------------+--------------+ -; |GR8RAM ; 107 ; 65 ; |GR8RAM ; work ; -; |lpm_counter:Ref_rtl_0| ; 4 ; 0 ; |GR8RAM|lpm_counter:Ref_rtl_0 ; work ; -+----------------------------+------------+------+-------------------------------+--------------+ - - -+--------------------------------------------------------------------------------------------------+ -; Control Signals ; -+-----------+----------+---------+--------------+--------+----------------------+------------------+ -; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; -+-----------+----------+---------+--------------+--------+----------------------+------------------+ -; BankWR_MC ; LC33 ; 8 ; Clock enable ; no ; -- ; -- ; -; C7M ; PIN_83 ; 55 ; Clock ; yes ; On ; -- ; -; PHI1b9_MC ; LC46 ; 5 ; Clock enable ; no ; -- ; -- ; -; S[0] ; LC114 ; 52 ; Clock enable ; no ; -- ; -- ; -; S[1] ; LC118 ; 53 ; Clock enable ; no ; -- ; -- ; -; S[2] ; LC113 ; 54 ; Clock enable ; no ; -- ; -- ; -; SetWR_MC ; LC42 ; 1 ; Clock enable ; no ; -- ; -- ; -; nIOSEL ; PIN_74 ; 12 ; Clock enable ; no ; -- ; -- ; -; nRES ; PIN_1 ; 40 ; Async. clear ; yes ; On ; -- ; -+-----------+----------+---------+--------------+--------+----------------------+------------------+ - - -+---------------------------------------------------------------------+ -; Global & Other Fast Signals ; -+------+----------+---------+----------------------+------------------+ -; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; -+------+----------+---------+----------------------+------------------+ -; C7M ; PIN_83 ; 55 ; On ; -- ; -; nRES ; PIN_1 ; 40 ; On ; -- ; -+------+----------+---------+----------------------+------------------+ - - -+-----------------------------------------+ -; Non-Global High Fan-Out Signals ; -+-------------------------------+---------+ -; Name ; Fan-Out ; -+-------------------------------+---------+ -; S[2] ; 54 ; -; S[1] ; 53 ; -; S[0] ; 52 ; -; nWE ; 16 ; -; nDEVSEL ; 15 ; -; A[3] ; 15 ; -; A[2] ; 15 ; -; A[1] ; 15 ; -; A[0] ; 15 ; -; nIOSEL ; 12 ; -; CASel ; 12 ; -; nIOSTRB ; 11 ; -; Addr[8] ; 11 ; -; Addr[0] ; 11 ; -; IncAddrL ; 11 ; -; IncAddrM ; 10 ; -; Addr[9] ; 10 ; -; Addr[1] ; 10 ; -; Addr[16] ; 10 ; -; IncAddrH ; 9 ; -; Addr[10] ; 9 ; -; Addr[17] ; 9 ; -; Addr[2] ; 9 ; -; AddrLWR_MC ; 9 ; -; AddrMWR_MC ; 9 ; -; D[7]~7 ; 8 ; -; FullIOEN ; 8 ; -; Addr[11] ; 8 ; -; Addr[18] ; 8 ; -; Addr[3] ; 8 ; -; Bank[0] ; 8 ; -; AddrHWR_MC ; 8 ; -; BankWR_MC ; 8 ; -; RAMSEL_MC ; 8 ; -; RDOE~1 ; 8 ; -; DOE~5 ; 8 ; -; Addr[22] ; 7 ; -; Addr[12] ; 7 ; -; Addr[19] ; 7 ; -; Addr[4] ; 7 ; -; Bank[1] ; 7 ; -; lpm_counter:Ref_rtl_0|dffs[3] ; 7 ; -; lpm_counter:Ref_rtl_0|dffs[2] ; 7 ; -; REGEN ; 7 ; -; lpm_counter:Ref_rtl_0|dffs[0] ; 7 ; -; D[6]~6 ; 6 ; -; D[5]~5 ; 6 ; -; D[4]~4 ; 6 ; -; D[3]~3 ; 6 ; -; D[2]~2 ; 6 ; -; D[1]~1 ; 6 ; -; D[0]~0 ; 6 ; -; Addr[13] ; 6 ; -; Addr[20] ; 6 ; -; Bank[2] ; 6 ; -; Addr[5] ; 6 ; -; lpm_counter:Ref_rtl_0|dffs[1] ; 6 ; -; Addr[6] ; 5 ; -; Addr[21] ; 5 ; -; Addr[14] ; 5 ; -; Bank[3] ; 5 ; -; PHI1b9_MC ; 5 ; -; Addr[15] ; 4 ; -; Addr[7] ; 4 ; -; Bank[4] ; 4 ; -; Bank[5] ; 3 ; -; IOROMEN ; 3 ; -; PHI1reg ; 3 ; -; PHI0seen ; 3 ; -; PHI1in ; 2 ; -; Addr[23] ; 2 ; -; Bank[6] ; 2 ; -; CASr ; 2 ; -; DBEN ; 2 ; -; RD[7]~7 ; 1 ; -; RD[6]~6 ; 1 ; -; RD[5]~5 ; 1 ; -; RD[4]~4 ; 1 ; -; RD[3]~3 ; 1 ; -; RD[2]~2 ; 1 ; -; RD[1]~1 ; 1 ; -; RD[0]~0 ; 1 ; -; A[10] ; 1 ; -; A[9] ; 1 ; -; A[8] ; 1 ; -; A[7] ; 1 ; -; A[6] ; 1 ; -; A[5] ; 1 ; -; A[4] ; 1 ; -; ~VCC~0 ; 1 ; -; RA~121 ; 1 ; -; RA~109 ; 1 ; -; RA~102 ; 1 ; -; RA~95 ; 1 ; -; RA~88 ; 1 ; -; RA~81 ; 1 ; -; RA~80 ; 1 ; -; RA~74 ; 1 ; -; Bank[7] ; 1 ; -; IncAddrM~9 ; 1 ; -; comb~38 ; 1 ; -; comb~34 ; 1 ; -; CAS1f ; 1 ; -; CAS0f ; 1 ; -; RA~69 ; 1 ; -; RA~66 ; 1 ; -; RA~63 ; 1 ; -; comb~31 ; 1 ; -; RASr ; 1 ; -; comb~28 ; 1 ; -; RASf ; 1 ; -; comb~26 ; 1 ; -; SetWR_MC ; 1 ; -; CSEN ; 1 ; -; PHI1b8_MC ; 1 ; -; PHI1b7_MC ; 1 ; -; PHI1b6_MC ; 1 ; -; PHI1b5_MC ; 1 ; -; PHI1b4_MC ; 1 ; -; PHI1b3_MC ; 1 ; -; PHI1b2_MC ; 1 ; -; PHI1b1_MC ; 1 ; -; nWE~1 ; 1 ; -; PHI1b0_MC ; 1 ; -; D[7]~38 ; 1 ; -; D[6]~36 ; 1 ; -; D[5]~34 ; 1 ; -; D[4]~32 ; 1 ; -; D[3]~30 ; 1 ; -; D[2]~28 ; 1 ; -; D[1]~26 ; 1 ; -; D[0]~24 ; 1 ; -; Dout[7]~120 ; 1 ; -; Dout[6]~114 ; 1 ; -; Dout[5]~108 ; 1 ; -; Dout[4]~102 ; 1 ; -; Dout[3]~96 ; 1 ; -; Dout[2]~90 ; 1 ; -; Dout[1]~84 ; 1 ; -; Dout[0]~78 ; 1 ; -+-------------------------------+---------+ - - -+--------------------------------------------------+ -; Other Routing Usage Summary ; -+-----------------------------+--------------------+ -; Other Routing Resource Type ; Usage ; -+-----------------------------+--------------------+ -; Output enables ; 2 / 6 ( 33 % ) ; -; PIA buffers ; 219 / 288 ( 76 % ) ; -; PIAs ; 246 / 288 ( 85 % ) ; -+-----------------------------+--------------------+ - - -+-----------------------------------------------------------------------------+ -; LAB External Interconnect ; -+-----------------------------------------------+-----------------------------+ -; LAB External Interconnects (Average = 30.75) ; Number of LABs (Total = 8) ; -+-----------------------------------------------+-----------------------------+ -; 0 - 2 ; 0 ; -; 3 - 5 ; 0 ; -; 6 - 8 ; 0 ; -; 9 - 11 ; 0 ; -; 12 - 14 ; 0 ; -; 15 - 17 ; 0 ; -; 18 - 20 ; 0 ; -; 21 - 23 ; 1 ; -; 24 - 26 ; 0 ; -; 27 - 29 ; 1 ; -; 30 - 32 ; 3 ; -; 33 - 35 ; 3 ; -+-----------------------------------------------+-----------------------------+ - - -+-----------------------------------------------------------------------+ -; LAB Macrocells ; -+-----------------------------------------+-----------------------------+ -; Number of Macrocells (Average = 13.38) ; Number of LABs (Total = 8) ; -+-----------------------------------------+-----------------------------+ -; 0 ; 0 ; -; 1 ; 0 ; -; 2 ; 0 ; -; 3 ; 0 ; -; 4 ; 0 ; -; 5 ; 0 ; -; 6 ; 0 ; -; 7 ; 0 ; -; 8 ; 1 ; -; 9 ; 1 ; -; 10 ; 1 ; -; 11 ; 0 ; -; 12 ; 0 ; -; 13 ; 0 ; -; 14 ; 0 ; -; 15 ; 0 ; -; 16 ; 5 ; -+-----------------------------------------+-----------------------------+ - - -+-------------------------------------------------------------------------------+ -; Shareable Expander ; -+-------------------------------------------------+-----------------------------+ -; Number of shareable expanders (Average = 0.13) ; Number of LABs (Total = 1) ; -+-------------------------------------------------+-----------------------------+ -; 0 ; 7 ; -; 1 ; 1 ; -+-------------------------------------------------+-----------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Logic Cell Interconnection ; -+-----+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; LAB ; Logic Cell ; Input ; Output ; -+-----+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; A ; LC6 ; C7M, nRES, D[5], AddrLWR_MC, S[0], S[2], S[1], Addr[5], IncAddrL, Addr[4], Addr[3], Addr[2], Addr[1], Addr[0] ; Dout[5]~108, Addr[5], Addr[6], Addr[7], IncAddrM, RA~95 ; -; A ; LC4 ; C7M, nRES, D[3], AddrLWR_MC, S[0], S[2], S[1], Addr[3], IncAddrL, Addr[2], Addr[1], Addr[0] ; Dout[3]~96, Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM, RA~81 ; -; A ; LC10 ; C7M, nRES, D[1], AddrMWR_MC, S[1], S[0], S[2], Addr[9], IncAddrM, Addr[8] ; Dout[1]~84, Addr[9], Addr[10], Addr[11], RA~66, Addr[12], Addr[13], Addr[14], Addr[15], IncAddrH ; -; A ; LC3 ; C7M, nRES, D[2], AddrLWR_MC, S[0], S[2], S[1], Addr[2], IncAddrL, Addr[1], Addr[0] ; Dout[2]~90, Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM, RA~80 ; -; A ; LC9 ; C7M, nRES, D[0], AddrMWR_MC, S[2], S[0], S[1], Addr[8], IncAddrM ; Dout[0]~78, Addr[8], Addr[9], Addr[10], Addr[11], RA~63, Addr[12], Addr[13], Addr[14], Addr[15], IncAddrH ; -; A ; LC2 ; C7M, nRES, D[1], AddrLWR_MC, S[0], S[2], S[1], Addr[1], IncAddrL, Addr[0] ; Dout[1]~84, Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM, RA~121 ; -; A ; LC1 ; C7M, nRES, D[0], AddrLWR_MC, S[0], S[2], S[1], Addr[0], IncAddrL ; Dout[0]~78, Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM, RA~74 ; -; A ; LC8 ; C7M, nRES, D[7], AddrLWR_MC, S[0], S[2], S[1], Addr[7], IncAddrL, Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0] ; Dout[7]~120, Addr[7], IncAddrM, RA~109 ; -; A ; LC7 ; C7M, nRES, D[6], AddrLWR_MC, S[0], S[2], S[1], Addr[6], IncAddrL, Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0] ; Dout[6]~114, Addr[6], Addr[7], IncAddrM, RA~102 ; -; A ; LC5 ; C7M, nRES, D[4], AddrLWR_MC, S[0], S[2], S[1], Addr[4], IncAddrL, Addr[3], Addr[2], Addr[1], Addr[0] ; Dout[4]~102, Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM, RA~88 ; -; A ; LC15 ; C7M, nRES, D[6], AddrMWR_MC, S[1], S[0], S[2], Addr[14], IncAddrM, Addr[8], Addr[9], Addr[10], Addr[11], Addr[12], Addr[13] ; Dout[6]~114, Addr[14], Addr[15], IncAddrH, RA~81 ; -; A ; LC14 ; C7M, nRES, D[5], AddrMWR_MC, S[1], S[0], S[2], Addr[13], IncAddrM, Addr[8], Addr[9], Addr[10], Addr[11], Addr[12] ; Dout[5]~108, Addr[13], Addr[14], Addr[15], IncAddrH, RA~80 ; -; A ; LC13 ; C7M, nRES, D[4], AddrMWR_MC, S[1], S[0], S[2], Addr[12], IncAddrM, Addr[8], Addr[9], Addr[10], Addr[11] ; Dout[4]~102, Addr[12], Addr[13], Addr[14], Addr[15], IncAddrH, RA~121 ; -; A ; LC16 ; C7M, nRES, D[7], AddrMWR_MC, S[1], S[0], S[2], Addr[15], IncAddrM, Addr[8], Addr[9], Addr[10], Addr[11], Addr[12], Addr[13], Addr[14] ; Dout[7]~120, Addr[15], IncAddrH, RA~88 ; -; A ; LC12 ; C7M, nRES, D[3], AddrMWR_MC, S[1], S[0], S[2], Addr[11], IncAddrM, Addr[8], Addr[9], Addr[10] ; Dout[3]~96, Addr[11], Addr[12], Addr[13], Addr[14], Addr[15], IncAddrH, RA~74 ; -; A ; LC11 ; C7M, nRES, D[2], AddrMWR_MC, S[1], S[0], S[2], Addr[10], IncAddrM, Addr[8], Addr[9] ; Dout[2]~90, Addr[10], Addr[11], Addr[12], Addr[13], Addr[14], RA~69, Addr[15], IncAddrH ; -; B ; LC19 ; C7M, nRES, D[6], AddrHWR_MC, S[2], S[0], S[1], Addr[22], IncAddrH, Addr[21], Addr[20], Addr[19], Addr[18], Addr[17], Addr[16] ; Dout[6]~114, Addr[22], CAS0f, CAS1f, comb~34, comb~38, Addr[23] ; -; B ; LC27 ; C7M, nRES, D[6], BankWR_MC, S[0], S[1], S[2] ; RA~102, RA~109 ; -; B ; LC20 ; C7M, nRES, D[7], AddrHWR_MC, S[2], S[0], S[1], Addr[23], IncAddrH, Addr[22], Addr[21], Addr[20], Addr[19], Addr[18], Addr[17], Addr[16] ; Dout[7]~120, Addr[23] ; -; B ; LC22 ; C7M, nRES, D[7], D[6], D[5], D[4], D[3], D[2], D[1], D[0], SetWR_MC, S[0], S[1], S[2] ; RA~74, RA~80, RA~81, RA~88, RA~95, RA~102, RA~109, RA~121 ; -; B ; LC17 ; ; nINH ; -; B ; LC24 ; C7M, nRES, D[0], AddrHWR_MC, S[2], S[0], S[1], Addr[16], IncAddrH ; Dout[0]~78, Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[23], RA~95 ; -; B ; LC30 ; C7M, nRES, D[1], BankWR_MC, S[0], S[1], S[2] ; RA~80, RA~81, RA~88, RA~95, RA~102, RA~109, RA~121 ; -; B ; LC21 ; C7M, nRES, D[1], AddrHWR_MC, S[2], S[0], S[1], Addr[17], IncAddrH, Addr[16] ; Dout[1]~84, Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[23], RA~102 ; -; B ; LC26 ; C7M, nRES, D[2], AddrHWR_MC, S[2], S[0], S[1], Addr[18], IncAddrH, Addr[17], Addr[16] ; Dout[2]~90, Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[23], RA~109 ; -; B ; LC18 ; C7M, nRES, D[2], BankWR_MC, S[0], S[1], S[2] ; RA~80, RA~81, RA~88, RA~95, RA~102, RA~109 ; -; B ; LC28 ; C7M, nRES, D[3], BankWR_MC, S[0], S[1], S[2] ; RA~81, RA~88, RA~95, RA~102, RA~109 ; -; B ; LC23 ; C7M, nRES, D[3], AddrHWR_MC, S[2], S[0], S[1], Addr[19], IncAddrH, Addr[18], Addr[17], Addr[16] ; Dout[3]~96, Addr[19], RA~63, Addr[20], Addr[21], Addr[22], Addr[23] ; -; B ; LC25 ; C7M, nRES, D[4], AddrHWR_MC, S[2], S[0], S[1], Addr[20], IncAddrH, Addr[19], Addr[18], Addr[17], Addr[16] ; Dout[4]~102, Addr[20], RA~66, Addr[21], Addr[22], Addr[23] ; -; B ; LC32 ; C7M, nRES, D[4], BankWR_MC, S[0], S[1], S[2] ; RA~88, RA~95, RA~102, RA~109 ; -; B ; LC31 ; C7M, nRES, D[5], BankWR_MC, S[0], S[1], S[2] ; RA~95, RA~102, RA~109 ; -; B ; LC29 ; C7M, nRES, D[5], AddrHWR_MC, S[2], S[0], S[1], Addr[21], IncAddrH, Addr[20], Addr[19], Addr[18], Addr[17], Addr[16] ; Dout[5]~108, Addr[21], RA~69, Addr[22], Addr[23] ; -; C ; LC42 ; A[0], nWE, REGEN, nDEVSEL, A[1], A[2], A[3] ; FullIOEN ; -; C ; LC37 ; C7M, nRES, nIOSEL, S[2], S[0], S[1] ; DOE~5, RAMSEL_MC, BankWR_MC, SetWR_MC, AddrHWR_MC, AddrMWR_MC, AddrLWR_MC ; -; C ; LC34 ; REGEN, nDEVSEL, A[0], A[1], A[2], A[3] ; IncAddrL, CASel, RASf, RASr, CAS0f, CAS1f, comb~34, comb~38 ; -; C ; LC33 ; nWE, REGEN, nDEVSEL, A[0], A[1], A[2], A[3] ; Bank[0], Bank[1], Bank[2], Bank[3], Bank[4], Bank[5], Bank[6], Bank[7] ; -; C ; LC39 ; A[0], A[1], A[2], A[3], nWE, REGEN, nDEVSEL ; Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[23] ; -; C ; LC38 ; RD[4], nDEVSEL, A[1], A[0], A[2], A[3], Addr[20], Addr[12], Addr[4] ; D[4] ; -; C ; LC40 ; RD[5], nDEVSEL, A[1], A[0], A[2], A[3], Addr[21], Addr[13], Addr[5] ; D[5] ; -; C ; LC43 ; RD[6], nDEVSEL, A[1], A[0], A[2], A[3], Addr[22], Addr[14], Addr[6] ; D[6] ; -; C ; LC45 ; RD[7], nDEVSEL, A[1], A[0], A[2], A[3], Addr[23], Addr[15], Addr[7] ; D[7] ; -; C ; LC36 ; C7M, nRES, S[2] ; DOE~5, RDOE~1 ; -; C ; LC44 ; C7M, nRES, nWE, S[2], S[0], S[1] ; comb~26 ; -; C ; LC47 ; A[0], A[1], A[2], A[3], nWE, REGEN, nDEVSEL ; Addr[8], Addr[9], Addr[10], Addr[11], Addr[12], Addr[13], Addr[14], Addr[15], IncAddrH ; -; C ; LC48 ; C7M, S[0], S[2], nWE, S[1] ; comb~34, comb~38 ; -; C ; LC35 ; A[0], A[1], A[2], A[3], nWE, REGEN, nDEVSEL ; Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM ; -; C ; LC41 ; C7M, nRES, RAMSEL_MC, S[0], S[2], S[1], IncAddrL ; IncAddrL, Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM~9, IncAddrM ; -; C ; LC46 ; PHI1in, PHI1b8_MC ; PHI0seen, PHI1reg, S[1], S[0], S[2] ; -; D ; LC57 ; RD[0], nDEVSEL, A[1], A[0], A[2], A[3], Addr[16], Addr[8], Addr[0] ; D[0] ; -; D ; LC56 ; REGEN, nDEVSEL, DBEN, nWE, nIOSEL, IOROMEN, nIOSTRB ; D[0], D[1], D[2], D[3], D[4], D[5], D[6], D[7] ; -; D ; LC59 ; RD[1], nDEVSEL, A[1], A[0], A[2], A[3], Addr[17], Addr[9], Addr[1] ; D[1] ; -; D ; LC61 ; RD[2], nDEVSEL, A[1], A[0], A[2], A[3], Addr[18], Addr[10], Addr[2] ; D[2] ; -; D ; LC64 ; RD[3], nDEVSEL, A[1], A[0], A[2], A[3], Addr[19], Addr[11], Addr[3] ; D[3] ; -; D ; LC52 ; C7M, PHI1b9_MC ; S[1], S[0], S[2] ; -; D ; LC49 ; CSEN, nIOSEL, IOROMEN, nIOSTRB ; nRCS ; -; D ; LC53 ; CASr, Addr[22], RAMSEL_MC, CAS0f ; nCAS0 ; -; D ; LC58 ; C7M, PHI1b9_MC ; S[1], S[0], S[2] ; -; D ; LC51 ; CASr, Addr[22], RAMSEL_MC, CAS1f ; nCAS1 ; -; E ; LC72 ; Addr[21], CASel, Addr[10] ; RA[10] ; -; E ; LC69 ; Addr[20], CASel, Addr[9] ; RA[9] ; -; E ; LC73 ; FullIOEN, Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[14], CASel, nIOSEL, Addr[3], Bank[3] ; RA[3] ; -; E ; LC77 ; FullIOEN, Bank[4], Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[16], CASel, nIOSEL, Addr[5], Bank[5] ; RA[5] ; -; E ; LC75 ; FullIOEN, Bank[2], Bank[1], nIOSTRB, Bank[0], Addr[13], CASel, nIOSEL, Addr[2] ; RA[2] ; -; E ; LC80 ; Bank[0], FullIOEN, nIOSTRB, Addr[11], CASel, nIOSEL, Addr[0] ; RA[0] ; -; E ; LC67 ; nWE ; nROE ; -; E ; LC79 ; C7M, nRES, D[7], AddrLWR_MC, Addr[7], S[2], S[1], S[0], IncAddrM, Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], IncAddrL, IncAddrM~9 ; Addr[8], Addr[9], Addr[10], Addr[11], Addr[12], Addr[13], Addr[14], IncAddrM, Addr[15], IncAddrH ; -; F ; LC94 ; D[7] ; RD[7] ; -; F ; LC91 ; Addr[19], CASel, Addr[8] ; RA[8] ; -; F ; LC96 ; C7M, nWE, S[0], RAMSEL_MC, S[2], S[1] ; comb~28, RA~63, RA~66, RA~69, RA~74, RA~80, RA~81, RA~88, RA~95, RA~102, RA~109, RA~121 ; -; F ; LC93 ; RASr, RASf ; nRAS ; -; F ; LC86 ; FullIOEN, Bank[6], Bank[5], Bank[4], Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[18], CASel, nIOSEL, Addr[7], Bank[7] ; RA[7] ; -; F ; LC88 ; FullIOEN, Bank[5], Bank[4], Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[17], CASel, nIOSEL, Addr[6], Bank[6] ; RA[6] ; -; F ; LC85 ; FullIOEN, Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[15], CASel, nIOSEL, Addr[4], Bank[4] ; RA[4] ; -; F ; LC87 ; C7M, nRES, D[7], BankWR_MC, S[0], S[1], S[2] ; RA~109 ; -; F ; LC83 ; Addr[12], CASel, nIOSEL, nIOSTRB, Addr[1], FullIOEN, Bank[1], Bank[0] ; RA[1] ; -; G ; LC107 ; D[2] ; RD[2] ; -; G ; LC101 ; D[4] ; RD[4] ; -; G ; LC97 ; D[5] ; RD[5] ; -; G ; LC99 ; D[6] ; RD[6] ; -; G ; LC103 ; C7M, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[0], S[2], S[0], S[1] ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], RASr, CAS0f, CAS1f ; -; G ; LC110 ; C7M, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], S[2], S[0], S[1] ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], RASr, CAS0f, CAS1f ; -; G ; LC112 ; C7M, nWE, S[0], RAMSEL_MC, S[2], S[1] ; comb~31 ; -; G ; LC98 ; C7M, nRES, D[7], AddrMWR_MC, Addr[15], S[0], S[2], S[1], IncAddrH, Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], IncAddrM ; Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], IncAddrH, Addr[23] ; -; G ; LC100 ; C7M, lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], S[2], S[0], S[1] ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], RASr, CAS0f, CAS1f ; -; G ; LC106 ; C7M, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], S[0], S[1], S[2], nWE, Addr[22], RAMSEL_MC ; comb~34 ; -; G ; LC111 ; C7M, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], S[0], S[1], S[2], nWE, Addr[22], RAMSEL_MC ; comb~38 ; -; G ; LC104 ; CASel, nWE ; nRWE ; -; G ; LC105 ; D[3] ; RD[3] ; -; G ; LC108 ; C7M, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], S[2], S[0], S[1] ; lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], RASr, CAS0f, CAS1f ; -; G ; LC109 ; D[1] ; RD[1] ; -; G ; LC102 ; C7M, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], S[2], S[0], S[1], nWE, RAMSEL_MC ; comb~31 ; -; H ; LC123 ; PHI1b5_MC ; PHI1b7_MC ; -; H ; LC118 ; C7M, PHI0seen, PHI1reg, PHI1b9_MC, S[1], S[0], S[2] ; S[1], S[0], S[2], CSEN, lpm_counter:Ref_rtl_0|dffs[0], REGEN, CASr, IOROMEN, lpm_counter:Ref_rtl_0|dffs[1], IncAddrL, CASel, RASf, lpm_counter:Ref_rtl_0|dffs[2], Addr[16], lpm_counter:Ref_rtl_0|dffs[3], Addr[0], RASr, Addr[1], Bank[0], Addr[8], Addr[2], Addr[9], Addr[3], Bank[1], Addr[17], Addr[4], Addr[18], Addr[5], Bank[2], Addr[10], Addr[11], Bank[3], Addr[19], Addr[20], Bank[4], Addr[12], Addr[13], Addr[14], Bank[5], Addr[21], Addr[22], CAS0f, CAS1f, Bank[6], Addr[6], Addr[7], IncAddrM~9, IncAddrM, Addr[15], IncAddrH, Addr[23], Bank[7], FullIOEN ; -; H ; LC113 ; C7M, PHI0seen, PHI1reg, PHI1b9_MC, S[0], S[2], S[1] ; S[1], S[0], S[2], DBEN, CSEN, lpm_counter:Ref_rtl_0|dffs[0], REGEN, CASr, IOROMEN, lpm_counter:Ref_rtl_0|dffs[1], IncAddrL, CASel, RASf, lpm_counter:Ref_rtl_0|dffs[2], Addr[16], lpm_counter:Ref_rtl_0|dffs[3], Addr[0], RASr, Addr[1], Bank[0], Addr[8], Addr[2], Addr[9], Addr[3], Bank[1], Addr[17], Addr[4], Addr[18], Addr[5], Bank[2], Addr[10], Addr[11], Bank[3], Addr[19], Addr[20], Bank[4], Addr[12], Addr[13], Addr[14], Bank[5], Addr[21], Addr[22], CAS0f, CAS1f, Bank[6], Addr[6], Addr[7], IncAddrM~9, IncAddrM, Addr[15], IncAddrH, Addr[23], Bank[7], FullIOEN ; -; H ; LC114 ; C7M, PHI0seen, PHI1reg, PHI1b9_MC, S[0], S[2], S[1] ; S[1], S[0], S[2], CSEN, lpm_counter:Ref_rtl_0|dffs[0], REGEN, CASr, IOROMEN, lpm_counter:Ref_rtl_0|dffs[1], IncAddrL, CASel, RASf, lpm_counter:Ref_rtl_0|dffs[2], Addr[16], lpm_counter:Ref_rtl_0|dffs[3], Addr[0], RASr, Addr[1], Bank[0], Addr[8], Addr[2], Addr[9], Addr[3], Bank[1], Addr[17], Addr[4], Addr[18], Addr[5], Bank[2], Addr[10], Addr[11], Bank[3], Addr[19], Addr[20], Bank[4], Addr[12], Addr[13], Addr[14], Bank[5], Addr[21], Addr[22], CAS0f, CAS1f, Bank[6], Addr[6], Addr[7], IncAddrM, Addr[15], IncAddrH, Addr[23], Bank[7], FullIOEN ; -; H ; LC122 ; PHI1b6_MC ; PHI1b8_MC ; -; H ; LC125 ; C7M, nRES, D[0], BankWR_MC, S[0], S[1], S[2] ; RA~74, RA~80, RA~81, RA~88, RA~95, RA~102, RA~109, RA~121 ; -; H ; LC124 ; PHI1b4_MC ; PHI1b6_MC ; -; H ; LC127 ; PHI1b3_MC ; PHI1b5_MC ; -; H ; LC128 ; PHI1b2_MC ; PHI1b4_MC ; -; H ; LC120 ; DBEN, nWE ; RD[0], RD[1], RD[2], RD[3], RD[4], RD[5], RD[6], RD[7] ; -; H ; LC116 ; PHI1b1_MC ; PHI1b3_MC ; -; H ; LC126 ; PHI1b0_MC ; PHI1b2_MC ; -; H ; LC115 ; D[0] ; RD[0] ; -; H ; LC121 ; PHI1in ; PHI1b1_MC ; -; H ; LC119 ; PHI1b7_MC ; PHI1b9_MC ; -; H ; LC117 ; C7M, nRES, A[4], A[5], A[6], A[7], A[8], A[9], A[10], nIOSTRB, A[0], A[1], A[2], A[3], S[2], S[0], S[1], IOROMEN, nIOSEL ; DOE~5, IOROMEN, comb~26 ; -+-----+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------+ -; Fitter Device Options ; -+----------------------------------------------+----------------+ -; Option ; Setting ; -+----------------------------------------------+----------------+ -; Enable user-supplied start-up clock (CLKUSR) ; Off ; -; Enable device-wide reset (DEV_CLRn) ; Off ; -; Enable device-wide output enable (DEV_OE) ; Off ; -; Enable INIT_DONE output ; Off ; -; Configuration scheme ; Passive Serial ; -; Security bit ; Off ; -; Base pin-out file on sameframe device ; Off ; -+----------------------------------------------+----------------+ - - -+-----------------+ -; Fitter Messages ; -+-----------------+ -Warning (20028): Parallel compilation is not licensed and has been disabled -Info (119006): Selected device EPM7128SLC84-15 for design "GR8RAM" -Info: Quartus II 64-Bit Fitter was successful. 0 errors, 1 warning - Info: Peak virtual memory: 4708 megabytes - Info: Processing ended: Sun Feb 16 00:10:46 2020 - Info: Elapsed time: 00:00:01 - Info: Total CPU time (on all processors): 00:00:01 - - diff --git a/cpld/output_files/GR8RAM.fit.summary b/cpld/output_files/GR8RAM.fit.summary deleted file mode 100755 index 043716b..0000000 --- a/cpld/output_files/GR8RAM.fit.summary +++ /dev/null @@ -1,9 +0,0 @@ -Fitter Status : Successful - Sun Feb 16 00:10:46 2020 -Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition -Revision Name : GR8RAM -Top-level Entity Name : GR8RAM -Family : MAX7000S -Device : EPM7128SLC84-15 -Timing Models : Final -Total macrocells : 107 / 128 ( 84 % ) -Total pins : 65 / 68 ( 96 % ) diff --git a/cpld/output_files/GR8RAM.flow.rpt b/cpld/output_files/GR8RAM.flow.rpt deleted file mode 100755 index a56d795..0000000 --- a/cpld/output_files/GR8RAM.flow.rpt +++ /dev/null @@ -1,130 +0,0 @@ -Flow report for GR8RAM -Sun Feb 16 00:10:48 2020 -Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Flow Summary - 3. Flow Settings - 4. Flow Non-Default Global Settings - 5. Flow Elapsed Time - 6. Flow OS Summary - 7. Flow Log - 8. Flow Messages - 9. Flow Suppressed Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2013 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+-----------------------------------------------------------------------------+ -; Flow Summary ; -+---------------------------+-------------------------------------------------+ -; Flow Status ; Successful - Sun Feb 16 00:10:47 2020 ; -; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; -; Revision Name ; GR8RAM ; -; Top-level Entity Name ; GR8RAM ; -; Family ; MAX7000S ; -; Device ; EPM7128SLC84-15 ; -; Timing Models ; Final ; -; Total macrocells ; 107 / 128 ( 84 % ) ; -; Total pins ; 65 / 68 ( 96 % ) ; -+---------------------------+-------------------------------------------------+ - - -+-----------------------------------------+ -; Flow Settings ; -+-------------------+---------------------+ -; Option ; Setting ; -+-------------------+---------------------+ -; Start date & time ; 02/16/2020 00:10:44 ; -; Main task ; Compilation ; -; Revision Name ; GR8RAM ; -+-------------------+---------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------+ -; Flow Non-Default Global Settings ; -+--------------------------------------------+---------------------------------+---------------+-------------+------------+ -; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; -+--------------------------------------------+---------------------------------+---------------+-------------+------------+ -; ALM_REGISTER_PACKING_EFFORT ; High ; Medium ; -- ; -- ; -; AUTO_LCELL_INSERTION ; Off ; On ; -- ; -- ; -; AUTO_PARALLEL_EXPANDERS ; Off ; On ; -- ; -- ; -; AUTO_TURBO_BIT ; Off ; On ; -- ; -- ; -; COMPILER_SIGNATURE_ID ; 207120313862967.158182984416660 ; -- ; -- ; -- ; -; ECO_OPTIMIZE_TIMING ; On ; Off ; -- ; -- ; -; ECO_REGENERATE_REPORT ; On ; Off ; -- ; -- ; -; EXTRACT_VERILOG_STATE_MACHINES ; Off ; On ; -- ; -- ; -; EXTRACT_VHDL_STATE_MACHINES ; Off ; On ; -- ; -- ; -; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ; -; MAX7000_IGNORE_LCELL_BUFFERS ; Off ; Auto ; -- ; -- ; -; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; -; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; -; OPTIMIZE_HOLD_TIMING ; Off ; -- ; -- ; -- ; -; OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING ; Pack All IO Registers ; Normal ; -- ; -- ; -; PARALLEL_SYNTHESIS ; Off ; On ; -- ; -- ; -; PRE_MAPPING_RESYNTHESIS ; On ; Off ; -- ; -- ; -; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; -; SLOW_SLEW_RATE ; On ; Off ; -- ; -- ; -; STATE_MACHINE_PROCESSING ; User-Encoded ; Auto ; -- ; -- ; -; SYNTH_MESSAGE_LEVEL ; High ; Medium ; -- ; -- ; -; SYNTH_TIMING_DRIVEN_SYNTHESIS ; Off ; -- ; -- ; -- ; -+--------------------------------------------+---------------------------------+---------------+-------------+------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------+ -; Flow Elapsed Time ; -+---------------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; -+---------------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:01 ; 1.0 ; 4587 MB ; 00:00:01 ; -; Fitter ; 00:00:01 ; 1.0 ; 4708 MB ; 00:00:00 ; -; Assembler ; 00:00:00 ; 1.0 ; 4522 MB ; 00:00:00 ; -; TimeQuest Timing Analyzer ; 00:00:00 ; 1.0 ; 4530 MB ; 00:00:00 ; -; Total ; 00:00:02 ; -- ; -- ; 00:00:01 ; -+---------------------------+--------------+-------------------------+---------------------+------------------------------------+ - - -+----------------------------------------------------------------------------------------+ -; Flow OS Summary ; -+---------------------------+------------------+-----------+------------+----------------+ -; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; -+---------------------------+------------------+-----------+------------+----------------+ -; Analysis & Synthesis ; DESKTOP-G62HNQS ; Windows 7 ; 6.2 ; x86_64 ; -; Fitter ; DESKTOP-G62HNQS ; Windows 7 ; 6.2 ; x86_64 ; -; Assembler ; DESKTOP-G62HNQS ; Windows 7 ; 6.2 ; x86_64 ; -; TimeQuest Timing Analyzer ; DESKTOP-G62HNQS ; Windows 7 ; 6.2 ; x86_64 ; -+---------------------------+------------------+-----------+------------+----------------+ - - ------------- -; Flow Log ; ------------- -quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM -quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM -quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM -quartus_sta GR8RAM -c GR8RAM - - - diff --git a/cpld/output_files/GR8RAM.jdi b/cpld/output_files/GR8RAM.jdi deleted file mode 100755 index 0d28391..0000000 --- a/cpld/output_files/GR8RAM.jdi +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/cpld/output_files/GR8RAM.map.rpt b/cpld/output_files/GR8RAM.map.rpt deleted file mode 100755 index 7c6b4c0..0000000 --- a/cpld/output_files/GR8RAM.map.rpt +++ /dev/null @@ -1,404 +0,0 @@ -Analysis & Synthesis report for GR8RAM -Sun Feb 16 00:10:45 2020 -Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Analysis & Synthesis Summary - 3. Analysis & Synthesis Settings - 4. Parallel Compilation - 5. Analysis & Synthesis Source Files Read - 6. Analysis & Synthesis Resource Usage Summary - 7. Analysis & Synthesis Resource Utilization by Entity - 8. Parameter Settings for Inferred Entity Instance: lpm_counter:Ref_rtl_0 - 9. Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add0 - 10. Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add4 - 11. Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add3 - 12. Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add5 - 13. Analysis & Synthesis Messages - 14. Analysis & Synthesis Suppressed Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2013 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+-------------------------------------------------------------------------------+ -; Analysis & Synthesis Summary ; -+-----------------------------+-------------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Sun Feb 16 00:10:45 2020 ; -; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; -; Revision Name ; GR8RAM ; -; Top-level Entity Name ; GR8RAM ; -; Family ; MAX7000S ; -; Total macrocells ; 107 ; -; Total pins ; 61 ; -+-----------------------------+-------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Settings ; -+----------------------------------------------------------------------------+-----------------+---------------+ -; Option ; Setting ; Default Value ; -+----------------------------------------------------------------------------+-----------------+---------------+ -; Device ; EPM7128SLC84-15 ; ; -; Top-level entity name ; GR8RAM ; GR8RAM ; -; Family name ; MAX7000S ; Cyclone IV GX ; -; State Machine Processing ; User-Encoded ; Auto ; -; Extract Verilog State Machines ; Off ; On ; -; Extract VHDL State Machines ; Off ; On ; -; Parallel Synthesis ; Off ; On ; -; Ignore LCELL Buffers ; Off ; Auto ; -; Auto Logic Cell Insertion ; Off ; On ; -; Auto Parallel Expanders ; Off ; On ; -; Pre-Mapping Resynthesis Optimization ; On ; Off ; -; Analysis & Synthesis Message Level ; High ; Medium ; -; Use smart compilation ; Off ; Off ; -; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; -; Enable compact report table ; Off ; Off ; -; Create Debugging Nodes for IP Cores ; Off ; Off ; -; Preserve fewer node names ; On ; On ; -; Disable OpenCore Plus hardware evaluation ; Off ; Off ; -; Verilog Version ; Verilog_2001 ; Verilog_2001 ; -; VHDL Version ; VHDL_1993 ; VHDL_1993 ; -; Safe State Machine ; Off ; Off ; -; Ignore Verilog initial constructs ; Off ; Off ; -; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; -; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; -; Add Pass-Through Logic to Inferred RAMs ; On ; On ; -; Infer RAMs from Raw Logic ; On ; On ; -; NOT Gate Push-Back ; On ; On ; -; Power-Up Don't Care ; On ; On ; -; Remove Duplicate Registers ; On ; On ; -; Ignore CARRY Buffers ; Off ; Off ; -; Ignore CASCADE Buffers ; Off ; Off ; -; Ignore GLOBAL Buffers ; Off ; Off ; -; Ignore ROW GLOBAL Buffers ; Off ; Off ; -; Ignore SOFT Buffers ; Off ; Off ; -; Limit AHDL Integers to 32 Bits ; Off ; Off ; -; Optimization Technique ; Speed ; Speed ; -; Allow XOR Gate Usage ; On ; On ; -; Parallel Expander Chain Length ; 4 ; 4 ; -; Auto Open-Drain Pins ; On ; On ; -; Auto Resource Sharing ; Off ; Off ; -; Maximum Fan-in Per Macrocell ; 100 ; 100 ; -; Use LogicLock Constraints during Resource Balancing ; On ; On ; -; Ignore translate_off and synthesis_off directives ; Off ; Off ; -; Report Parameter Settings ; On ; On ; -; Report Source Assignments ; On ; On ; -; Report Connectivity Checks ; On ; On ; -; HDL message level ; Level2 ; Level2 ; -; Suppress Register Optimization Related Messages ; Off ; Off ; -; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; -; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; -; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; -; Block Design Naming ; Auto ; Auto ; -; Synthesis Effort ; Auto ; Auto ; -; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; -; Disable Register Merging Across Hierarchies ; Auto ; Auto ; -; Synthesis Seed ; 1 ; 1 ; -+----------------------------------------------------------------------------+-----------------+---------------+ - - -Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. -+-------------------------------------+ -; Parallel Compilation ; -+----------------------------+--------+ -; Processors ; Number ; -+----------------------------+--------+ -; Number detected on machine ; 8 ; -; Maximum allowed ; 1 ; -+----------------------------+--------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Source Files Read ; -+----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------+---------+ -; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; -+----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------+---------+ -; GR8RAM.v ; yes ; User Verilog HDL File ; C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v ; ; -; lpm_counter.tdf ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_counter.tdf ; ; -; lpm_constant.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_constant.inc ; ; -; lpm_decode.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_decode.inc ; ; -; lpm_add_sub.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.inc ; ; -; cmpconst.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/cmpconst.inc ; ; -; lpm_compare.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_compare.inc ; ; -; lpm_counter.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_counter.inc ; ; -; dffeea.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/dffeea.inc ; ; -; alt_counter_stratix.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/alt_counter_stratix.inc ; ; -; aglobal130.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/aglobal130.inc ; ; -; lpm_add_sub.tdf ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf ; ; -; addcore.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.inc ; ; -; look_add.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/look_add.inc ; ; -; bypassff.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/bypassff.inc ; ; -; altshift.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift.inc ; ; -; alt_stratix_add_sub.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/alt_stratix_add_sub.inc ; ; -; addcore.tdf ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf ; ; -; a_csnbuffer.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/a_csnbuffer.inc ; ; -; a_csnbuffer.tdf ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/a_csnbuffer.tdf ; ; -; look_add.tdf ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/look_add.tdf ; ; -; altshift.tdf ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift.tdf ; ; -+----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------+---------+ - - -+---------------------------------------------+ -; Analysis & Synthesis Resource Usage Summary ; -+----------------------+----------------------+ -; Resource ; Usage ; -+----------------------+----------------------+ -; Logic cells ; 107 ; -; Total registers ; 55 ; -; I/O pins ; 61 ; -; Shareable expanders ; 1 ; -; Maximum fan-out node ; C7M ; -; Maximum fan-out ; 55 ; -; Total fan-out ; 855 ; -; Average fan-out ; 5.06 ; -+----------------------+----------------------+ - - -+-----------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Resource Utilization by Entity ; -+----------------------------+------------+------+-------------------------------+--------------+ -; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ; Library Name ; -+----------------------------+------------+------+-------------------------------+--------------+ -; |GR8RAM ; 107 ; 61 ; |GR8RAM ; work ; -; |lpm_counter:Ref_rtl_0| ; 4 ; 0 ; |GR8RAM|lpm_counter:Ref_rtl_0 ; work ; -+----------------------------+------------+------+-------------------------------+--------------+ - - -+------------------------------------------------------------------------+ -; Parameter Settings for Inferred Entity Instance: lpm_counter:Ref_rtl_0 ; -+------------------------+-------------------+---------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+-------------------+---------------------------+ -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -; LPM_WIDTH ; 4 ; Untyped ; -; LPM_DIRECTION ; UP ; Untyped ; -; LPM_MODULUS ; 0 ; Untyped ; -; LPM_AVALUE ; UNUSED ; Untyped ; -; LPM_SVALUE ; UNUSED ; Untyped ; -; LPM_PORT_UPDOWN ; PORT_CONNECTIVITY ; Untyped ; -; DEVICE_FAMILY ; MAX7000S ; Untyped ; -; CARRY_CHAIN ; MANUAL ; Untyped ; -; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ; -; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ; -; CARRY_CNT_EN ; SMART ; Untyped ; -; LABWIDE_SCLR ; ON ; Untyped ; -; USE_NEW_VERSION ; TRUE ; Untyped ; -; CBXI_PARAMETER ; NOTHING ; Untyped ; -+------------------------+-------------------+---------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------+ -; Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add0 ; -+------------------------+-------------+----------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+-------------+----------------------------+ -; LPM_WIDTH ; 8 ; Untyped ; -; LPM_REPRESENTATION ; UNSIGNED ; Untyped ; -; LPM_DIRECTION ; ADD ; Untyped ; -; ONE_INPUT_IS_CONSTANT ; YES ; Untyped ; -; LPM_PIPELINE ; 0 ; Untyped ; -; MAXIMIZE_SPEED ; 5 ; Untyped ; -; REGISTERED_AT_END ; 0 ; Untyped ; -; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ; -; USE_CS_BUFFERS ; 1 ; Untyped ; -; CARRY_CHAIN ; MANUAL ; Untyped ; -; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ; -; DEVICE_FAMILY ; MAX7000S ; Untyped ; -; USE_WYS ; OFF ; Untyped ; -; STYLE ; FAST ; Untyped ; -; CBXI_PARAMETER ; add_sub_rnh ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -+------------------------+-------------+----------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------+ -; Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add4 ; -+------------------------+-------------+----------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+-------------+----------------------------+ -; LPM_WIDTH ; 8 ; Untyped ; -; LPM_REPRESENTATION ; UNSIGNED ; Untyped ; -; LPM_DIRECTION ; ADD ; Untyped ; -; ONE_INPUT_IS_CONSTANT ; YES ; Untyped ; -; LPM_PIPELINE ; 0 ; Untyped ; -; MAXIMIZE_SPEED ; 5 ; Untyped ; -; REGISTERED_AT_END ; 0 ; Untyped ; -; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ; -; USE_CS_BUFFERS ; 1 ; Untyped ; -; CARRY_CHAIN ; MANUAL ; Untyped ; -; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ; -; DEVICE_FAMILY ; MAX7000S ; Untyped ; -; USE_WYS ; OFF ; Untyped ; -; STYLE ; FAST ; Untyped ; -; CBXI_PARAMETER ; add_sub_rnh ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -+------------------------+-------------+----------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------+ -; Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add3 ; -+------------------------+-------------+----------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+-------------+----------------------------+ -; LPM_WIDTH ; 8 ; Untyped ; -; LPM_REPRESENTATION ; UNSIGNED ; Untyped ; -; LPM_DIRECTION ; ADD ; Untyped ; -; ONE_INPUT_IS_CONSTANT ; YES ; Untyped ; -; LPM_PIPELINE ; 0 ; Untyped ; -; MAXIMIZE_SPEED ; 5 ; Untyped ; -; REGISTERED_AT_END ; 0 ; Untyped ; -; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ; -; USE_CS_BUFFERS ; 1 ; Untyped ; -; CARRY_CHAIN ; MANUAL ; Untyped ; -; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ; -; DEVICE_FAMILY ; MAX7000S ; Untyped ; -; USE_WYS ; OFF ; Untyped ; -; STYLE ; FAST ; Untyped ; -; CBXI_PARAMETER ; add_sub_rnh ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -+------------------------+-------------+----------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------+ -; Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add5 ; -+------------------------+-------------+----------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+-------------+----------------------------+ -; LPM_WIDTH ; 8 ; Untyped ; -; LPM_REPRESENTATION ; UNSIGNED ; Untyped ; -; LPM_DIRECTION ; ADD ; Untyped ; -; ONE_INPUT_IS_CONSTANT ; YES ; Untyped ; -; LPM_PIPELINE ; 0 ; Untyped ; -; MAXIMIZE_SPEED ; 5 ; Untyped ; -; REGISTERED_AT_END ; 0 ; Untyped ; -; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ; -; USE_CS_BUFFERS ; 1 ; Untyped ; -; CARRY_CHAIN ; MANUAL ; Untyped ; -; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ; -; DEVICE_FAMILY ; MAX7000S ; Untyped ; -; USE_WYS ; OFF ; Untyped ; -; STYLE ; FAST ; Untyped ; -; CBXI_PARAMETER ; add_sub_rnh ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -+------------------------+-------------+----------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------+ -; Analysis & Synthesis Messages ; -+-------------------------------+ -Info: ******************************************************************* -Info: Running Quartus II 64-Bit Analysis & Synthesis - Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - Info: Processing started: Sun Feb 16 00:10:44 2020 -Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM -Warning (20028): Parallel compilation is not licensed and has been disabled -Info (12021): Found 1 design units, including 1 entities, in source file gr8ram.v - Info (12023): Found entity 1: GR8RAM -Info (12127): Elaborating entity "GR8RAM" for the top level hierarchy -Warning (10230): Verilog HDL assignment warning at GR8RAM.v(30): truncated value with size 32 to match size of target (8) -Warning (10230): Verilog HDL assignment warning at GR8RAM.v(115): truncated value with size 32 to match size of target (3) -Warning (10230): Verilog HDL assignment warning at GR8RAM.v(120): truncated value with size 32 to match size of target (4) -Warning (10230): Verilog HDL assignment warning at GR8RAM.v(169): truncated value with size 32 to match size of target (8) -Warning (10230): Verilog HDL assignment warning at GR8RAM.v(174): truncated value with size 32 to match size of target (8) -Warning (10230): Verilog HDL assignment warning at GR8RAM.v(180): truncated value with size 32 to match size of target (8) -Info (19000): Inferred 1 megafunctions from design logic - Info (19001): Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "Ref_rtl_0" -Info (278001): Inferred 4 megafunctions from design logic - Info (278002): Inferred adder/subtractor megafunction ("lpm_add_sub") from the following logic: "Add0" - Info (278002): Inferred adder/subtractor megafunction ("lpm_add_sub") from the following logic: "Add4" - Info (278002): Inferred adder/subtractor megafunction ("lpm_add_sub") from the following logic: "Add3" - Info (278002): Inferred adder/subtractor megafunction ("lpm_add_sub") from the following logic: "Add5" -Info (12130): Elaborated megafunction instantiation "lpm_counter:Ref_rtl_0" -Info (12133): Instantiated megafunction "lpm_counter:Ref_rtl_0" with the following parameter: - Info (12134): Parameter "LPM_WIDTH" = "4" - Info (12134): Parameter "LPM_DIRECTION" = "UP" - Info (12134): Parameter "LPM_TYPE" = "LPM_COUNTER" -Info (12130): Elaborated megafunction instantiation "lpm_add_sub:Add0" -Info (12133): Instantiated megafunction "lpm_add_sub:Add0" with the following parameter: - Info (12134): Parameter "LPM_WIDTH" = "8" - Info (12134): Parameter "LPM_DIRECTION" = "ADD" - Info (12134): Parameter "LPM_REPRESENTATION" = "UNSIGNED" - Info (12134): Parameter "ONE_INPUT_IS_CONSTANT" = "YES" -Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add0|addcore:adder[0]", which is child of megafunction instantiation "lpm_add_sub:Add0" -Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add0|addcore:adder[0]|a_csnbuffer:oflow_node", which is child of megafunction instantiation "lpm_add_sub:Add0" -Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add0|addcore:adder[0]|a_csnbuffer:result_node", which is child of megafunction instantiation "lpm_add_sub:Add0" -Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add0|look_add:look_ahead_unit", which is child of megafunction instantiation "lpm_add_sub:Add0" -Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add0|altshift:result_ext_latency_ffs", which is child of megafunction instantiation "lpm_add_sub:Add0" -Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add0|altshift:carry_ext_latency_ffs", which is child of megafunction instantiation "lpm_add_sub:Add0" -Info (13014): Ignored 32 buffer(s) - Info (13019): Ignored 32 SOFT buffer(s) -Info (280013): Promoted pin-driven signal(s) to global signal - Info (280014): Promoted clock signal driven by pin "C7M" to global clock signal - Info (280015): Promoted clear signal driven by pin "nRES" to global clear signal -Warning (21074): Design contains 9 input pin(s) that do not drive logic - Warning (15610): No output dependent on input pin "C7M_2" - Warning (15610): No output dependent on input pin "Q3" - Warning (15610): No output dependent on input pin "PHI0in" - Warning (15610): No output dependent on input pin "nMode" - Warning (15610): No output dependent on input pin "A[11]" - Warning (15610): No output dependent on input pin "A[12]" - Warning (15610): No output dependent on input pin "A[13]" - Warning (15610): No output dependent on input pin "A[14]" - Warning (15610): No output dependent on input pin "A[15]" -Info (21057): Implemented 169 device resources after synthesis - the final resource count might be different - Info (21058): Implemented 27 input pins - Info (21059): Implemented 18 output pins - Info (21060): Implemented 16 bidirectional pins - Info (21063): Implemented 107 macrocells - Info (21073): Implemented 1 shareable expanders -Info (144001): Generated suppressed messages file C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg -Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 17 warnings - Info: Peak virtual memory: 4587 megabytes - Info: Processing ended: Sun Feb 16 00:10:45 2020 - Info: Elapsed time: 00:00:01 - Info: Total CPU time (on all processors): 00:00:01 - - -+------------------------------------------+ -; Analysis & Synthesis Suppressed Messages ; -+------------------------------------------+ -The suppressed messages can be found in C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg. - - diff --git a/cpld/output_files/GR8RAM.map.smsg b/cpld/output_files/GR8RAM.map.smsg deleted file mode 100755 index 8f822b8..0000000 --- a/cpld/output_files/GR8RAM.map.smsg +++ /dev/null @@ -1,3 +0,0 @@ -Warning (10273): Verilog HDL warning at GR8RAM.v(52): extended using "x" or "z" -Warning (10273): Verilog HDL warning at GR8RAM.v(60): extended using "x" or "z" -Warning (10268): Verilog HDL information at GR8RAM.v(200): always construct contains both blocking and non-blocking assignments diff --git a/cpld/output_files/GR8RAM.map.summary b/cpld/output_files/GR8RAM.map.summary deleted file mode 100755 index c2e5fd1..0000000 --- a/cpld/output_files/GR8RAM.map.summary +++ /dev/null @@ -1,7 +0,0 @@ -Analysis & Synthesis Status : Successful - Sun Feb 16 00:10:45 2020 -Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition -Revision Name : GR8RAM -Top-level Entity Name : GR8RAM -Family : MAX7000S -Total macrocells : 107 -Total pins : 61 diff --git a/cpld/output_files/GR8RAM.pin b/cpld/output_files/GR8RAM.pin deleted file mode 100755 index 5e6034e..0000000 --- a/cpld/output_files/GR8RAM.pin +++ /dev/null @@ -1,147 +0,0 @@ - -- Copyright (C) 1991-2013 Altera Corporation - -- Your use of Altera Corporation's design tools, logic functions - -- and other software and tools, and its AMPP partner logic - -- functions, and any output files from any of the foregoing - -- (including device programming or simulation files), and any - -- associated documentation or information are expressly subject - -- to the terms and conditions of the Altera Program License - -- Subscription Agreement, Altera MegaCore Function License - -- Agreement, or other applicable license agreement, including, - -- without limitation, that your use is for the sole purpose of - -- programming logic devices manufactured by Altera and sold by - -- Altera or its authorized distributors. Please refer to the - -- applicable agreement for further details. - -- - -- This is a Quartus II output file. It is for reporting purposes only, and is - -- not intended for use as a Quartus II input file. This file cannot be used - -- to make Quartus II pin assignments - for instructions on how to make pin - -- assignments, please see Quartus II help. - --------------------------------------------------------------------------------- - - - - --------------------------------------------------------------------------------- - -- NC : No Connect. This pin has no internal connection to the device. - -- DNU : Do Not Use. This pin MUST NOT be connected. - -- VCC : Dedicated power pin, which MUST be connected to VCC. - -- VCCIO : Dedicated power pin, which MUST be connected to VCC - -- of its bank. - -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. - -- It can also be used to report unused dedicated pins. The connection - -- on the board for unused dedicated pins depends on whether this will - -- be used in a future design. One example is device migration. When - -- using device migration, refer to the device pin-tables. If it is a - -- GND pin in the pin table or if it will not be used in a future design - -- for another purpose the it MUST be connected to GND. If it is an unused - -- dedicated pin, then it can be connected to a valid signal on the board - -- (low, high, or toggling) if that signal is required for a different - -- revision of the design. - -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. - -- This pin should be connected to GND. It may also be connected to a - -- valid signal on the board (low, high, or toggling) if that signal - -- is required for a different revision of the design. - -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND - -- or leave it unconnected. - -- RESERVED : Unused I/O pin, which MUST be left unconnected. - -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. - -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. - -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. - -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. - -- NON_MIGRATABLE: This pin cannot be migrated. - --------------------------------------------------------------------------------- - - - - --------------------------------------------------------------------------------- - -- Pin directions (input, output or bidir) are based on device operating in user mode. - --------------------------------------------------------------------------------- - -Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition -CHIP "GR8RAM" ASSIGNED TO AN: EPM7128SLC84-15 - -Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment -------------------------------------------------------------------------------------------------------------- -nRES : 1 : input : TTL : : : Y -PHI1in : 2 : input : TTL : : : Y -VCCINT : 3 : power : : 5.0V : : -A[6] : 4 : input : TTL : : : Y -A[7] : 5 : input : TTL : : : Y -Q3 : 6 : input : TTL : : : Y -GND : 7 : gnd : : : : -PHI0in : 8 : input : TTL : : : Y -A[8] : 9 : input : TTL : : : Y -A[9] : 10 : input : TTL : : : Y -A[10] : 11 : input : TTL : : : Y -A[11] : 12 : input : TTL : : : Y -VCCIO : 13 : power : : 5.0V : : -TDI : 14 : input : TTL : : : N -A[12] : 15 : input : TTL : : : Y -A[13] : 16 : input : TTL : : : Y -A[14] : 17 : input : TTL : : : Y -A[15] : 18 : input : TTL : : : Y -GND : 19 : gnd : : : : -nWE : 20 : input : TTL : : : Y -nDEVSEL : 21 : input : TTL : : : Y -nINH : 22 : output : TTL : : : Y -TMS : 23 : input : TTL : : : N -nIOSTRB : 24 : input : TTL : : : Y -D[7] : 25 : bidir : TTL : : : Y -VCCIO : 26 : power : : 5.0V : : -D[6] : 27 : bidir : TTL : : : Y -D[5] : 28 : bidir : TTL : : : Y -D[4] : 29 : bidir : TTL : : : Y -RESERVED : 30 : : : : : -RESERVED : 31 : : : : : -GND : 32 : gnd : : : : -D[3] : 33 : bidir : TTL : : : Y -D[2] : 34 : bidir : TTL : : : Y -D[1] : 35 : bidir : TTL : : : Y -D[0] : 36 : bidir : TTL : : : Y -RESERVED : 37 : : : : : -VCCIO : 38 : power : : 5.0V : : -nCAS0 : 39 : output : TTL : : : Y -nCAS1 : 40 : output : TTL : : : Y -nRCS : 41 : output : TTL : : : Y -GND : 42 : gnd : : : : -VCCINT : 43 : power : : 5.0V : : -nMode : 44 : input : TTL : : : Y -nROE : 45 : output : TTL : : : Y -RA[9] : 46 : output : TTL : : : Y -GND : 47 : gnd : : : : -RA[10] : 48 : output : TTL : : : Y -RA[3] : 49 : output : TTL : : : Y -RA[2] : 50 : output : TTL : : : Y -RA[5] : 51 : output : TTL : : : Y -RA[0] : 52 : output : TTL : : : Y -VCCIO : 53 : power : : 5.0V : : -RA[1] : 54 : output : TTL : : : Y -RA[4] : 55 : output : TTL : : : Y -RA[7] : 56 : output : TTL : : : Y -RA[6] : 57 : output : TTL : : : Y -RA[8] : 58 : output : TTL : : : Y -GND : 59 : gnd : : : : -nRAS : 60 : output : TTL : : : Y -RD[7] : 61 : bidir : TTL : : : Y -TCK : 62 : input : TTL : : : N -RD[5] : 63 : bidir : TTL : : : Y -RD[6] : 64 : bidir : TTL : : : Y -RD[4] : 65 : bidir : TTL : : : Y -VCCIO : 66 : power : : 5.0V : : -nRWE : 67 : output : TTL : : : Y -RD[3] : 68 : bidir : TTL : : : Y -RD[2] : 69 : bidir : TTL : : : Y -RD[1] : 70 : bidir : TTL : : : Y -TDO : 71 : output : TTL : : : N -GND : 72 : gnd : : : : -RD[0] : 73 : bidir : TTL : : : Y -nIOSEL : 74 : input : TTL : : : Y -A[0] : 75 : input : TTL : : : Y -A[1] : 76 : input : TTL : : : Y -A[2] : 77 : input : TTL : : : Y -VCCIO : 78 : power : : 5.0V : : -A[3] : 79 : input : TTL : : : Y -A[4] : 80 : input : TTL : : : Y -A[5] : 81 : input : TTL : : : Y -GND : 82 : gnd : : : : -C7M : 83 : input : TTL : : : Y -C7M_2 : 84 : input : TTL : : : Y diff --git a/cpld/output_files/GR8RAM.pof b/cpld/output_files/GR8RAM.pof deleted file mode 100755 index 5c4887d..0000000 Binary files a/cpld/output_files/GR8RAM.pof and /dev/null differ diff --git a/cpld/output_files/GR8RAM.sta.rpt b/cpld/output_files/GR8RAM.sta.rpt deleted file mode 100755 index fa27dc1..0000000 --- a/cpld/output_files/GR8RAM.sta.rpt +++ /dev/null @@ -1,1090 +0,0 @@ -TimeQuest Timing Analyzer report for GR8RAM -Sun Feb 16 00:10:48 2020 -Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. TimeQuest Timing Analyzer Summary - 3. Parallel Compilation - 4. Clocks - 5. Fmax Summary - 6. Setup Summary - 7. Hold Summary - 8. Recovery Summary - 9. Removal Summary - 10. Minimum Pulse Width Summary - 11. Setup: 'C7M' - 12. Hold: 'C7M' - 13. Minimum Pulse Width: 'C7M' - 14. Setup Times - 15. Hold Times - 16. Clock to Output Times - 17. Minimum Clock to Output Times - 18. Propagation Delay - 19. Minimum Propagation Delay - 20. Output Enable Times - 21. Minimum Output Enable Times - 22. Output Disable Times - 23. Minimum Output Disable Times - 24. Setup Transfers - 25. Hold Transfers - 26. Report TCCS - 27. Report RSKM - 28. Unconstrained Paths - 29. TimeQuest Timing Analyzer Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2013 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+----------------------------------------------------------------------------------------+ -; TimeQuest Timing Analyzer Summary ; -+--------------------+-------------------------------------------------------------------+ -; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ; -; Revision Name ; GR8RAM ; -; Device Family ; MAX7000S ; -; Device Name ; EPM7128SLC84-15 ; -; Timing Models ; Final ; -; Delay Model ; Slow Model ; -; Rise/Fall Delays ; Unavailable ; -+--------------------+-------------------------------------------------------------------+ - - -Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. -+-------------------------------------+ -; Parallel Compilation ; -+----------------------------+--------+ -; Processors ; Number ; -+----------------------------+--------+ -; Number detected on machine ; 8 ; -; Maximum allowed ; 1 ; -+----------------------------+--------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Clocks ; -+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+ -; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; -+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+ -; C7M ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { C7M } ; -+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+ - - -+-------------------------------------------------+ -; Fmax Summary ; -+-----------+-----------------+------------+------+ -; Fmax ; Restricted Fmax ; Clock Name ; Note ; -+-----------+-----------------+------------+------+ -; 10.42 MHz ; 10.42 MHz ; C7M ; ; -+-----------+-----------------+------------+------+ -This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. - - -+---------------------------------+ -; Setup Summary ; -+-------+---------+---------------+ -; Clock ; Slack ; End Point TNS ; -+-------+---------+---------------+ -; C7M ; -47.500 ; -2116.500 ; -+-------+---------+---------------+ - - -+-------------------------------+ -; Hold Summary ; -+-------+-------+---------------+ -; Clock ; Slack ; End Point TNS ; -+-------+-------+---------------+ -; C7M ; 5.000 ; 0.000 ; -+-------+-------+---------------+ - - --------------------- -; Recovery Summary ; --------------------- -No paths to report. - - -------------------- -; Removal Summary ; -------------------- -No paths to report. - - -+--------------------------------+ -; Minimum Pulse Width Summary ; -+-------+--------+---------------+ -; Clock ; Slack ; End Point TNS ; -+-------+--------+---------------+ -; C7M ; -4.500 ; -495.000 ; -+-------+--------+---------------+ - - -+------------------------------------------------------------------------------------------------------+ -; Setup: 'C7M' ; -+---------+-----------+----------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+---------+-----------+----------+--------------+-------------+--------------+------------+------------+ -; -47.500 ; REGEN ; Addr[0] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; -; -47.500 ; REGEN ; Addr[1] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; -; -47.500 ; REGEN ; IncAddrM ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; -; -47.500 ; REGEN ; Addr[8] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; -; -47.500 ; REGEN ; Addr[9] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; -; -47.500 ; REGEN ; Addr[17] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; -; -47.500 ; REGEN ; Addr[18] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; -; -47.500 ; REGEN ; Addr[10] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; -; -47.500 ; REGEN ; Addr[2] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; -; -47.500 ; REGEN ; Addr[3] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; -; -47.500 ; REGEN ; Addr[11] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; -; -47.500 ; REGEN ; Addr[19] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; -; -47.500 ; REGEN ; Addr[20] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; -; -47.500 ; REGEN ; Addr[12] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; -; -47.500 ; REGEN ; Addr[4] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; -; -47.500 ; REGEN ; Addr[5] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; -; -47.500 ; REGEN ; Addr[13] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; -; -47.500 ; REGEN ; Addr[21] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; -; -47.500 ; REGEN ; Addr[22] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; -; -47.500 ; REGEN ; Addr[14] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; -; -47.500 ; REGEN ; Addr[6] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; -; -47.500 ; REGEN ; Addr[7] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; -; -47.500 ; REGEN ; Addr[23] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; -; -47.500 ; REGEN ; Addr[15] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; -; -47.500 ; REGEN ; IncAddrH ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; -; -47.500 ; REGEN ; Addr[16] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; -; -47.500 ; REGEN ; Bank[0] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; -; -47.500 ; REGEN ; Bank[1] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; -; -47.500 ; REGEN ; Bank[2] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; -; -47.500 ; REGEN ; Bank[3] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; -; -47.500 ; REGEN ; Bank[4] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; -; -47.500 ; REGEN ; Bank[5] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; -; -47.500 ; REGEN ; Bank[6] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; -; -47.500 ; REGEN ; Bank[7] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; -; -47.500 ; REGEN ; FullIOEN ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ; -; -46.500 ; S[2] ; IncAddrM ; C7M ; C7M ; 0.500 ; 0.000 ; 43.000 ; -; -46.500 ; S[1] ; IncAddrM ; C7M ; C7M ; 0.500 ; 0.000 ; 43.000 ; -; -46.000 ; IncAddrL ; IncAddrM ; C7M ; C7M ; 1.000 ; 0.000 ; 43.000 ; -; -34.500 ; REGEN ; IncAddrL ; C7M ; C7M ; 0.500 ; 0.000 ; 31.000 ; -; -34.500 ; REGEN ; RASf ; C7M ; C7M ; 0.500 ; 0.000 ; 31.000 ; -; -34.500 ; REGEN ; CAS0f ; C7M ; C7M ; 0.500 ; 0.000 ; 31.000 ; -; -34.500 ; REGEN ; CAS1f ; C7M ; C7M ; 0.500 ; 0.000 ; 31.000 ; -; -34.000 ; REGEN ; CASel ; C7M ; C7M ; 1.000 ; 0.000 ; 31.000 ; -; -34.000 ; REGEN ; RASr ; C7M ; C7M ; 1.000 ; 0.000 ; 31.000 ; -; -25.500 ; S[0] ; IncAddrL ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[2] ; IncAddrL ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[1] ; IncAddrL ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[0] ; Addr[0] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[2] ; Addr[0] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[1] ; Addr[0] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[0] ; Addr[1] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[2] ; Addr[1] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[1] ; Addr[1] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[0] ; IncAddrM ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[2] ; Addr[8] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[0] ; Addr[8] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[1] ; Addr[8] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[1] ; Addr[9] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[0] ; Addr[9] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[2] ; Addr[9] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[2] ; Addr[17] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[0] ; Addr[17] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[1] ; Addr[17] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[2] ; Addr[18] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[0] ; Addr[18] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[1] ; Addr[18] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[1] ; Addr[10] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[0] ; Addr[10] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[2] ; Addr[10] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[0] ; Addr[2] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[2] ; Addr[2] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[1] ; Addr[2] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[0] ; Addr[3] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[2] ; Addr[3] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[1] ; Addr[3] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[1] ; Addr[11] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[0] ; Addr[11] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[2] ; Addr[11] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[2] ; Addr[19] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[0] ; Addr[19] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[1] ; Addr[19] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[2] ; Addr[20] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[0] ; Addr[20] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[1] ; Addr[20] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[1] ; Addr[12] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[0] ; Addr[12] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[2] ; Addr[12] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[0] ; Addr[4] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[2] ; Addr[4] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[1] ; Addr[4] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[0] ; Addr[5] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[2] ; Addr[5] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[1] ; Addr[5] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[1] ; Addr[13] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[0] ; Addr[13] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[2] ; Addr[13] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[2] ; Addr[21] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[0] ; Addr[21] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[1] ; Addr[21] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -; -25.500 ; S[2] ; Addr[22] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ; -+---------+-----------+----------+--------------+-------------+--------------+------------+------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------+ -; Hold: 'C7M' ; -+--------+-------------------------------+-------------------------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+--------+-------------------------------+-------------------------------+--------------+-------------+--------------+------------+------------+ -; 5.000 ; PHI0seen ; S[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; PHI1reg ; S[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; S[1] ; S[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; S[0] ; S[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; S[2] ; S[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; PHI0seen ; S[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; PHI1reg ; S[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; S[0] ; S[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; S[2] ; S[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; S[1] ; S[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; PHI0seen ; S[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; PHI1reg ; S[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; S[0] ; S[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; S[2] ; S[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; S[1] ; S[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; S[1] ; IOROMEN ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; IOROMEN ; IOROMEN ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; S[2] ; IOROMEN ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; S[0] ; IOROMEN ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; lpm_counter:Ref_rtl_0|dffs[2] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; lpm_counter:Ref_rtl_0|dffs[1] ; lpm_counter:Ref_rtl_0|dffs[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; lpm_counter:Ref_rtl_0|dffs[0] ; lpm_counter:Ref_rtl_0|dffs[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; IncAddrL ; IncAddrL ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[0] ; Addr[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[1] ; Addr[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[8] ; Addr[8] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[9] ; Addr[9] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[17] ; Addr[17] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[18] ; Addr[18] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[10] ; Addr[10] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[2] ; Addr[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[3] ; Addr[3] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[11] ; Addr[11] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[19] ; Addr[19] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[20] ; Addr[20] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[12] ; Addr[12] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[4] ; Addr[4] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[5] ; Addr[5] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[13] ; Addr[13] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[21] ; Addr[21] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[22] ; Addr[22] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[14] ; Addr[14] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[6] ; Addr[6] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[7] ; Addr[7] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[23] ; Addr[23] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[15] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 5.000 ; Addr[16] ; Addr[16] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ; -; 18.000 ; S[2] ; REGEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; S[0] ; REGEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; S[1] ; REGEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; S[2] ; DBEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; S[2] ; CSEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; S[0] ; CSEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; S[1] ; CSEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; lpm_counter:Ref_rtl_0|dffs[3] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; lpm_counter:Ref_rtl_0|dffs[1] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; lpm_counter:Ref_rtl_0|dffs[0] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; S[2] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; S[0] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; S[1] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; lpm_counter:Ref_rtl_0|dffs[3] ; lpm_counter:Ref_rtl_0|dffs[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; lpm_counter:Ref_rtl_0|dffs[0] ; lpm_counter:Ref_rtl_0|dffs[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; lpm_counter:Ref_rtl_0|dffs[2] ; lpm_counter:Ref_rtl_0|dffs[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; S[2] ; lpm_counter:Ref_rtl_0|dffs[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; S[0] ; lpm_counter:Ref_rtl_0|dffs[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; S[1] ; lpm_counter:Ref_rtl_0|dffs[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; lpm_counter:Ref_rtl_0|dffs[1] ; lpm_counter:Ref_rtl_0|dffs[3] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; lpm_counter:Ref_rtl_0|dffs[0] ; lpm_counter:Ref_rtl_0|dffs[3] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; lpm_counter:Ref_rtl_0|dffs[2] ; lpm_counter:Ref_rtl_0|dffs[3] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; lpm_counter:Ref_rtl_0|dffs[3] ; lpm_counter:Ref_rtl_0|dffs[3] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; S[2] ; lpm_counter:Ref_rtl_0|dffs[3] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; S[0] ; lpm_counter:Ref_rtl_0|dffs[3] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; S[1] ; lpm_counter:Ref_rtl_0|dffs[3] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; lpm_counter:Ref_rtl_0|dffs[3] ; lpm_counter:Ref_rtl_0|dffs[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; lpm_counter:Ref_rtl_0|dffs[2] ; lpm_counter:Ref_rtl_0|dffs[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; S[2] ; lpm_counter:Ref_rtl_0|dffs[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; S[0] ; lpm_counter:Ref_rtl_0|dffs[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; S[1] ; lpm_counter:Ref_rtl_0|dffs[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; S[0] ; CASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; S[2] ; CASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; S[1] ; CASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; S[1] ; CASel ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; S[0] ; CASel ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; S[2] ; CASel ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; lpm_counter:Ref_rtl_0|dffs[3] ; RASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; lpm_counter:Ref_rtl_0|dffs[2] ; RASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; lpm_counter:Ref_rtl_0|dffs[1] ; RASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; lpm_counter:Ref_rtl_0|dffs[0] ; RASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; S[2] ; RASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; S[0] ; RASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; S[1] ; RASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; IncAddrL ; Addr[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; IncAddrL ; Addr[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; Addr[0] ; Addr[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; IncAddrM ; IncAddrM ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; Addr[7] ; IncAddrM ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; Addr[6] ; IncAddrM ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; Addr[5] ; IncAddrM ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; Addr[4] ; IncAddrM ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -; 18.000 ; Addr[3] ; IncAddrM ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ; -+--------+-------------------------------+-------------------------------+--------------+-------------+--------------+------------+------------+ - - -+-------------------------------------------------------------------------------------------+ -; Minimum Pulse Width: 'C7M' ; -+--------+--------------+----------------+------------------+-------+------------+----------+ -; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; -+--------+--------------+----------------+------------------+-------+------------+----------+ -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[0] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[0] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[10] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[10] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[11] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[11] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[12] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[12] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[13] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[13] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[14] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[14] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[15] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[15] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[16] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[16] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[17] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[17] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[18] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[18] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[19] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[19] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[1] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[1] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[20] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[20] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[21] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[21] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[22] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[22] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[23] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[23] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[2] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[2] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[3] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[3] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[4] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[4] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[5] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[5] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[6] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[6] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[7] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[7] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[8] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[8] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[9] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[9] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Bank[0] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Bank[0] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Bank[1] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Bank[1] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Bank[2] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Bank[2] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Bank[3] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Bank[3] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Bank[4] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Bank[4] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Bank[5] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Bank[5] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Bank[6] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Bank[6] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Bank[7] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Bank[7] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; CAS0f ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; CAS0f ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; CAS1f ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; CAS1f ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; CASel ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; CASel ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; CASr ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; CASr ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; CSEN ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; CSEN ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; DBEN ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; DBEN ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; FullIOEN ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; FullIOEN ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; IOROMEN ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; IOROMEN ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; IncAddrH ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; IncAddrH ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; IncAddrL ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; IncAddrL ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; IncAddrM ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; IncAddrM ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; PHI0seen ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; PHI0seen ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; PHI1reg ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; PHI1reg ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; RASf ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; RASf ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; RASr ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; RASr ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; REGEN ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; REGEN ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; S[0] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; S[0] ; -; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; S[1] ; -; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; S[1] ; -+--------+--------------+----------------+------------------+-------+------------+----------+ - - -+---------------------------------------------------------------------------+ -; Setup Times ; -+-----------+------------+---------+---------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-----------+------------+---------+---------+------------+-----------------+ -; A[*] ; C7M ; 33.000 ; 33.000 ; Rise ; C7M ; -; A[0] ; C7M ; 33.000 ; 33.000 ; Rise ; C7M ; -; A[1] ; C7M ; 33.000 ; 33.000 ; Rise ; C7M ; -; A[2] ; C7M ; 33.000 ; 33.000 ; Rise ; C7M ; -; A[3] ; C7M ; 33.000 ; 33.000 ; Rise ; C7M ; -; A[4] ; C7M ; 11.000 ; 11.000 ; Rise ; C7M ; -; A[5] ; C7M ; 11.000 ; 11.000 ; Rise ; C7M ; -; A[6] ; C7M ; 11.000 ; 11.000 ; Rise ; C7M ; -; A[7] ; C7M ; 11.000 ; 11.000 ; Rise ; C7M ; -; A[8] ; C7M ; 11.000 ; 11.000 ; Rise ; C7M ; -; A[9] ; C7M ; 11.000 ; 11.000 ; Rise ; C7M ; -; A[10] ; C7M ; 11.000 ; 11.000 ; Rise ; C7M ; -; PHI1in ; C7M ; 101.000 ; 101.000 ; Rise ; C7M ; -; nDEVSEL ; C7M ; 33.000 ; 33.000 ; Rise ; C7M ; -; nIOSEL ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ; -; nIOSTRB ; C7M ; 11.000 ; 11.000 ; Rise ; C7M ; -; nWE ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ; -; A[*] ; C7M ; 46.000 ; 46.000 ; Fall ; C7M ; -; A[0] ; C7M ; 46.000 ; 46.000 ; Fall ; C7M ; -; A[1] ; C7M ; 46.000 ; 46.000 ; Fall ; C7M ; -; A[2] ; C7M ; 46.000 ; 46.000 ; Fall ; C7M ; -; A[3] ; C7M ; 46.000 ; 46.000 ; Fall ; C7M ; -; D[*] ; C7M ; 24.000 ; 24.000 ; Fall ; C7M ; -; D[0] ; C7M ; 24.000 ; 24.000 ; Fall ; C7M ; -; D[1] ; C7M ; 24.000 ; 24.000 ; Fall ; C7M ; -; D[2] ; C7M ; 24.000 ; 24.000 ; Fall ; C7M ; -; D[3] ; C7M ; 24.000 ; 24.000 ; Fall ; C7M ; -; D[4] ; C7M ; 24.000 ; 24.000 ; Fall ; C7M ; -; D[5] ; C7M ; 24.000 ; 24.000 ; Fall ; C7M ; -; D[6] ; C7M ; 24.000 ; 24.000 ; Fall ; C7M ; -; D[7] ; C7M ; 24.000 ; 24.000 ; Fall ; C7M ; -; nDEVSEL ; C7M ; 46.000 ; 46.000 ; Fall ; C7M ; -; nWE ; C7M ; 46.000 ; 46.000 ; Fall ; C7M ; -+-----------+------------+---------+---------+------------+-----------------+ - - -+---------------------------------------------------------------------------+ -; Hold Times ; -+-----------+------------+---------+---------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-----------+------------+---------+---------+------------+-----------------+ -; A[*] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ; -; A[0] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ; -; A[1] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ; -; A[2] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ; -; A[3] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ; -; A[4] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ; -; A[5] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ; -; A[6] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ; -; A[7] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ; -; A[8] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ; -; A[9] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ; -; A[10] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ; -; PHI1in ; C7M ; -12.000 ; -12.000 ; Rise ; C7M ; -; nDEVSEL ; C7M ; -25.000 ; -25.000 ; Rise ; C7M ; -; nIOSEL ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ; -; nIOSTRB ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ; -; nWE ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ; -; A[*] ; C7M ; -25.000 ; -25.000 ; Fall ; C7M ; -; A[0] ; C7M ; -25.000 ; -25.000 ; Fall ; C7M ; -; A[1] ; C7M ; -25.000 ; -25.000 ; Fall ; C7M ; -; A[2] ; C7M ; -25.000 ; -25.000 ; Fall ; C7M ; -; A[3] ; C7M ; -25.000 ; -25.000 ; Fall ; C7M ; -; D[*] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ; -; D[0] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ; -; D[1] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ; -; D[2] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ; -; D[3] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ; -; D[4] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ; -; D[5] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ; -; D[6] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ; -; D[7] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ; -; nDEVSEL ; C7M ; -25.000 ; -25.000 ; Fall ; C7M ; -; nWE ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ; -+-----------+------------+---------+---------+------------+-----------------+ - - -+-------------------------------------------------------------------------+ -; Clock to Output Times ; -+-----------+------------+--------+--------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-----------+------------+--------+--------+------------+-----------------+ -; RA[*] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; -; RA[0] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; -; RA[1] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; -; RA[2] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; -; RA[3] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; -; RA[4] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; -; RA[5] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; -; RA[6] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; -; RA[7] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; -; RA[8] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; -; RA[9] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; -; RA[10] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; -; nCAS0 ; C7M ; 43.000 ; 43.000 ; Rise ; C7M ; -; nCAS1 ; C7M ; 43.000 ; 43.000 ; Rise ; C7M ; -; nRAS ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; -; nRCS ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; -; nRWE ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; -; D[*] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; -; D[0] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; -; D[1] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; -; D[2] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; -; D[3] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; -; D[4] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; -; D[5] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; -; D[6] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; -; D[7] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; -; RA[*] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; -; RA[0] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; -; RA[1] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; -; RA[2] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; -; RA[3] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; -; RA[4] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; -; RA[5] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; -; RA[6] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; -; RA[7] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; -; RA[8] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; -; RA[9] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; -; RA[10] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; -; nCAS0 ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; -; nCAS1 ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; -; nRAS ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; -+-----------+------------+--------+--------+------------+-----------------+ - - -+-------------------------------------------------------------------------+ -; Minimum Clock to Output Times ; -+-----------+------------+--------+--------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-----------+------------+--------+--------+------------+-----------------+ -; RA[*] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; -; RA[0] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; -; RA[1] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; -; RA[2] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; -; RA[3] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; -; RA[4] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; -; RA[5] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; -; RA[6] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; -; RA[7] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; -; RA[8] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; -; RA[9] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; -; RA[10] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; -; nCAS0 ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; -; nCAS1 ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; -; nRAS ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; -; nRCS ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; -; nRWE ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ; -; D[*] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; -; D[0] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; -; D[1] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; -; D[2] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; -; D[3] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; -; D[4] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; -; D[5] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; -; D[6] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; -; D[7] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; -; RA[*] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; -; RA[0] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; -; RA[1] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; -; RA[2] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; -; RA[3] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; -; RA[4] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; -; RA[5] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; -; RA[6] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; -; RA[7] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; -; RA[8] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; -; RA[9] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; -; RA[10] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; -; nCAS0 ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; -; nCAS1 ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; -; nRAS ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ; -+-----------+------------+--------+--------+------------+-----------------+ - - -+--------------------------------------------------------------+ -; Propagation Delay ; -+------------+-------------+--------+--------+--------+--------+ -; Input Port ; Output Port ; RR ; RF ; FR ; FF ; -+------------+-------------+--------+--------+--------+--------+ -; A[0] ; D[0] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ; -; A[0] ; D[1] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ; -; A[0] ; D[2] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ; -; A[0] ; D[3] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ; -; A[0] ; D[4] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ; -; A[0] ; D[5] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ; -; A[0] ; D[6] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ; -; A[0] ; D[7] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ; -; A[0] ; nCAS0 ; 41.000 ; ; ; 41.000 ; -; A[0] ; nCAS1 ; 41.000 ; ; ; 41.000 ; -; A[1] ; D[0] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ; -; A[1] ; D[1] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ; -; A[1] ; D[2] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ; -; A[1] ; D[3] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ; -; A[1] ; D[4] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ; -; A[1] ; D[5] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ; -; A[1] ; D[6] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ; -; A[1] ; D[7] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ; -; A[1] ; nCAS0 ; 41.000 ; ; ; 41.000 ; -; A[1] ; nCAS1 ; 41.000 ; ; ; 41.000 ; -; A[2] ; D[0] ; ; 32.000 ; 32.000 ; ; -; A[2] ; D[1] ; ; 32.000 ; 32.000 ; ; -; A[2] ; D[2] ; ; 32.000 ; 32.000 ; ; -; A[2] ; D[3] ; ; 32.000 ; 32.000 ; ; -; A[2] ; D[4] ; ; 32.000 ; 32.000 ; ; -; A[2] ; D[5] ; ; 32.000 ; 32.000 ; ; -; A[2] ; D[6] ; ; 32.000 ; 32.000 ; ; -; A[2] ; D[7] ; ; 32.000 ; 32.000 ; ; -; A[2] ; nCAS0 ; ; 41.000 ; 41.000 ; ; -; A[2] ; nCAS1 ; ; 41.000 ; 41.000 ; ; -; A[3] ; D[0] ; ; 32.000 ; 32.000 ; ; -; A[3] ; D[1] ; ; 32.000 ; 32.000 ; ; -; A[3] ; D[2] ; ; 32.000 ; 32.000 ; ; -; A[3] ; D[3] ; ; 32.000 ; 32.000 ; ; -; A[3] ; D[4] ; ; 32.000 ; 32.000 ; ; -; A[3] ; D[5] ; ; 32.000 ; 32.000 ; ; -; A[3] ; D[6] ; ; 32.000 ; 32.000 ; ; -; A[3] ; D[7] ; ; 32.000 ; 32.000 ; ; -; A[3] ; nCAS0 ; ; 41.000 ; 41.000 ; ; -; A[3] ; nCAS1 ; ; 41.000 ; 41.000 ; ; -; D[0] ; RD[0] ; 32.000 ; ; ; 32.000 ; -; D[1] ; RD[1] ; 32.000 ; ; ; 32.000 ; -; D[2] ; RD[2] ; 32.000 ; ; ; 32.000 ; -; D[3] ; RD[3] ; 32.000 ; ; ; 32.000 ; -; D[4] ; RD[4] ; 32.000 ; ; ; 32.000 ; -; D[5] ; RD[5] ; 32.000 ; ; ; 32.000 ; -; D[6] ; RD[6] ; 32.000 ; ; ; 32.000 ; -; D[7] ; RD[7] ; 32.000 ; ; ; 32.000 ; -; RD[0] ; D[0] ; 32.000 ; ; ; 32.000 ; -; RD[1] ; D[1] ; 32.000 ; ; ; 32.000 ; -; RD[2] ; D[2] ; 32.000 ; ; ; 32.000 ; -; RD[3] ; D[3] ; 32.000 ; ; ; 32.000 ; -; RD[4] ; D[4] ; 32.000 ; ; ; 32.000 ; -; RD[5] ; D[5] ; 32.000 ; ; ; 32.000 ; -; RD[6] ; D[6] ; 32.000 ; ; ; 32.000 ; -; RD[7] ; D[7] ; 32.000 ; ; ; 32.000 ; -; nDEVSEL ; D[0] ; 32.000 ; 39.000 ; 39.000 ; 32.000 ; -; nDEVSEL ; D[1] ; 32.000 ; 39.000 ; 39.000 ; 32.000 ; -; nDEVSEL ; D[2] ; 32.000 ; 39.000 ; 39.000 ; 32.000 ; -; nDEVSEL ; D[3] ; 32.000 ; 39.000 ; 39.000 ; 32.000 ; -; nDEVSEL ; D[4] ; 32.000 ; 39.000 ; 39.000 ; 32.000 ; -; nDEVSEL ; D[5] ; 32.000 ; 39.000 ; 39.000 ; 32.000 ; -; nDEVSEL ; D[6] ; 32.000 ; 39.000 ; 39.000 ; 32.000 ; -; nDEVSEL ; D[7] ; 32.000 ; 39.000 ; 39.000 ; 32.000 ; -; nDEVSEL ; nCAS0 ; ; 41.000 ; 41.000 ; ; -; nDEVSEL ; nCAS1 ; ; 41.000 ; 41.000 ; ; -; nIOSEL ; D[0] ; ; 39.000 ; 39.000 ; ; -; nIOSEL ; D[1] ; ; 39.000 ; 39.000 ; ; -; nIOSEL ; D[2] ; ; 39.000 ; 39.000 ; ; -; nIOSEL ; D[3] ; ; 39.000 ; 39.000 ; ; -; nIOSEL ; D[4] ; ; 39.000 ; 39.000 ; ; -; nIOSEL ; D[5] ; ; 39.000 ; 39.000 ; ; -; nIOSEL ; D[6] ; ; 39.000 ; 39.000 ; ; -; nIOSEL ; D[7] ; ; 39.000 ; 39.000 ; ; -; nIOSEL ; RA[0] ; 32.000 ; ; ; 32.000 ; -; nIOSEL ; RA[1] ; 32.000 ; ; ; 32.000 ; -; nIOSEL ; RA[2] ; 32.000 ; ; ; 32.000 ; -; nIOSEL ; RA[3] ; 32.000 ; ; ; 32.000 ; -; nIOSEL ; RA[4] ; 32.000 ; ; ; 32.000 ; -; nIOSEL ; RA[5] ; 32.000 ; ; ; 32.000 ; -; nIOSEL ; RA[6] ; 32.000 ; ; ; 32.000 ; -; nIOSEL ; RA[7] ; 32.000 ; ; ; 32.000 ; -; nIOSEL ; nRCS ; ; 32.000 ; 32.000 ; ; -; nIOSTRB ; D[0] ; ; 39.000 ; 39.000 ; ; -; nIOSTRB ; D[1] ; ; 39.000 ; 39.000 ; ; -; nIOSTRB ; D[2] ; ; 39.000 ; 39.000 ; ; -; nIOSTRB ; D[3] ; ; 39.000 ; 39.000 ; ; -; nIOSTRB ; D[4] ; ; 39.000 ; 39.000 ; ; -; nIOSTRB ; D[5] ; ; 39.000 ; 39.000 ; ; -; nIOSTRB ; D[6] ; ; 39.000 ; 39.000 ; ; -; nIOSTRB ; D[7] ; ; 39.000 ; 39.000 ; ; -; nIOSTRB ; RA[0] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ; -; nIOSTRB ; RA[1] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ; -; nIOSTRB ; RA[2] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ; -; nIOSTRB ; RA[3] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ; -; nIOSTRB ; RA[4] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ; -; nIOSTRB ; RA[5] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ; -; nIOSTRB ; RA[6] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ; -; nIOSTRB ; RA[7] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ; -; nIOSTRB ; nRCS ; ; 32.000 ; 32.000 ; ; -; nWE ; D[0] ; 39.000 ; ; ; 39.000 ; -; nWE ; D[1] ; 39.000 ; ; ; 39.000 ; -; nWE ; D[2] ; 39.000 ; ; ; 39.000 ; -; nWE ; D[3] ; 39.000 ; ; ; 39.000 ; -; nWE ; D[4] ; 39.000 ; ; ; 39.000 ; -; nWE ; D[5] ; 39.000 ; ; ; 39.000 ; -; nWE ; D[6] ; 39.000 ; ; ; 39.000 ; -; nWE ; D[7] ; 39.000 ; ; ; 39.000 ; -; nWE ; RD[0] ; ; 39.000 ; 39.000 ; ; -; nWE ; RD[1] ; ; 39.000 ; 39.000 ; ; -; nWE ; RD[2] ; ; 39.000 ; 39.000 ; ; -; nWE ; RD[3] ; ; 39.000 ; 39.000 ; ; -; nWE ; RD[4] ; ; 39.000 ; 39.000 ; ; -; nWE ; RD[5] ; ; 39.000 ; 39.000 ; ; -; nWE ; RD[6] ; ; 39.000 ; 39.000 ; ; -; nWE ; RD[7] ; ; 39.000 ; 39.000 ; ; -; nWE ; nROE ; ; 32.000 ; 32.000 ; ; -; nWE ; nRWE ; ; 32.000 ; 32.000 ; ; -+------------+-------------+--------+--------+--------+--------+ - - -+--------------------------------------------------------------+ -; Minimum Propagation Delay ; -+------------+-------------+--------+--------+--------+--------+ -; Input Port ; Output Port ; RR ; RF ; FR ; FF ; -+------------+-------------+--------+--------+--------+--------+ -; A[0] ; D[0] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ; -; A[0] ; D[1] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ; -; A[0] ; D[2] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ; -; A[0] ; D[3] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ; -; A[0] ; D[4] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ; -; A[0] ; D[5] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ; -; A[0] ; D[6] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ; -; A[0] ; D[7] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ; -; A[0] ; nCAS0 ; 41.000 ; ; ; 41.000 ; -; A[0] ; nCAS1 ; 41.000 ; ; ; 41.000 ; -; A[1] ; D[0] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ; -; A[1] ; D[1] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ; -; A[1] ; D[2] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ; -; A[1] ; D[3] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ; -; A[1] ; D[4] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ; -; A[1] ; D[5] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ; -; A[1] ; D[6] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ; -; A[1] ; D[7] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ; -; A[1] ; nCAS0 ; 41.000 ; ; ; 41.000 ; -; A[1] ; nCAS1 ; 41.000 ; ; ; 41.000 ; -; A[2] ; D[0] ; ; 32.000 ; 32.000 ; ; -; A[2] ; D[1] ; ; 32.000 ; 32.000 ; ; -; A[2] ; D[2] ; ; 32.000 ; 32.000 ; ; -; A[2] ; D[3] ; ; 32.000 ; 32.000 ; ; -; A[2] ; D[4] ; ; 32.000 ; 32.000 ; ; -; A[2] ; D[5] ; ; 32.000 ; 32.000 ; ; -; A[2] ; D[6] ; ; 32.000 ; 32.000 ; ; -; A[2] ; D[7] ; ; 32.000 ; 32.000 ; ; -; A[2] ; nCAS0 ; ; 41.000 ; 41.000 ; ; -; A[2] ; nCAS1 ; ; 41.000 ; 41.000 ; ; -; A[3] ; D[0] ; ; 32.000 ; 32.000 ; ; -; A[3] ; D[1] ; ; 32.000 ; 32.000 ; ; -; A[3] ; D[2] ; ; 32.000 ; 32.000 ; ; -; A[3] ; D[3] ; ; 32.000 ; 32.000 ; ; -; A[3] ; D[4] ; ; 32.000 ; 32.000 ; ; -; A[3] ; D[5] ; ; 32.000 ; 32.000 ; ; -; A[3] ; D[6] ; ; 32.000 ; 32.000 ; ; -; A[3] ; D[7] ; ; 32.000 ; 32.000 ; ; -; A[3] ; nCAS0 ; ; 41.000 ; 41.000 ; ; -; A[3] ; nCAS1 ; ; 41.000 ; 41.000 ; ; -; D[0] ; RD[0] ; 32.000 ; ; ; 32.000 ; -; D[1] ; RD[1] ; 32.000 ; ; ; 32.000 ; -; D[2] ; RD[2] ; 32.000 ; ; ; 32.000 ; -; D[3] ; RD[3] ; 32.000 ; ; ; 32.000 ; -; D[4] ; RD[4] ; 32.000 ; ; ; 32.000 ; -; D[5] ; RD[5] ; 32.000 ; ; ; 32.000 ; -; D[6] ; RD[6] ; 32.000 ; ; ; 32.000 ; -; D[7] ; RD[7] ; 32.000 ; ; ; 32.000 ; -; RD[0] ; D[0] ; 32.000 ; ; ; 32.000 ; -; RD[1] ; D[1] ; 32.000 ; ; ; 32.000 ; -; RD[2] ; D[2] ; 32.000 ; ; ; 32.000 ; -; RD[3] ; D[3] ; 32.000 ; ; ; 32.000 ; -; RD[4] ; D[4] ; 32.000 ; ; ; 32.000 ; -; RD[5] ; D[5] ; 32.000 ; ; ; 32.000 ; -; RD[6] ; D[6] ; 32.000 ; ; ; 32.000 ; -; RD[7] ; D[7] ; 32.000 ; ; ; 32.000 ; -; nDEVSEL ; D[0] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ; -; nDEVSEL ; D[1] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ; -; nDEVSEL ; D[2] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ; -; nDEVSEL ; D[3] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ; -; nDEVSEL ; D[4] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ; -; nDEVSEL ; D[5] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ; -; nDEVSEL ; D[6] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ; -; nDEVSEL ; D[7] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ; -; nDEVSEL ; nCAS0 ; ; 41.000 ; 41.000 ; ; -; nDEVSEL ; nCAS1 ; ; 41.000 ; 41.000 ; ; -; nIOSEL ; D[0] ; ; 39.000 ; 39.000 ; ; -; nIOSEL ; D[1] ; ; 39.000 ; 39.000 ; ; -; nIOSEL ; D[2] ; ; 39.000 ; 39.000 ; ; -; nIOSEL ; D[3] ; ; 39.000 ; 39.000 ; ; -; nIOSEL ; D[4] ; ; 39.000 ; 39.000 ; ; -; nIOSEL ; D[5] ; ; 39.000 ; 39.000 ; ; -; nIOSEL ; D[6] ; ; 39.000 ; 39.000 ; ; -; nIOSEL ; D[7] ; ; 39.000 ; 39.000 ; ; -; nIOSEL ; RA[0] ; 32.000 ; ; ; 32.000 ; -; nIOSEL ; RA[1] ; 32.000 ; ; ; 32.000 ; -; nIOSEL ; RA[2] ; 32.000 ; ; ; 32.000 ; -; nIOSEL ; RA[3] ; 32.000 ; ; ; 32.000 ; -; nIOSEL ; RA[4] ; 32.000 ; ; ; 32.000 ; -; nIOSEL ; RA[5] ; 32.000 ; ; ; 32.000 ; -; nIOSEL ; RA[6] ; 32.000 ; ; ; 32.000 ; -; nIOSEL ; RA[7] ; 32.000 ; ; ; 32.000 ; -; nIOSEL ; nRCS ; ; 32.000 ; 32.000 ; ; -; nIOSTRB ; D[0] ; ; 39.000 ; 39.000 ; ; -; nIOSTRB ; D[1] ; ; 39.000 ; 39.000 ; ; -; nIOSTRB ; D[2] ; ; 39.000 ; 39.000 ; ; -; nIOSTRB ; D[3] ; ; 39.000 ; 39.000 ; ; -; nIOSTRB ; D[4] ; ; 39.000 ; 39.000 ; ; -; nIOSTRB ; D[5] ; ; 39.000 ; 39.000 ; ; -; nIOSTRB ; D[6] ; ; 39.000 ; 39.000 ; ; -; nIOSTRB ; D[7] ; ; 39.000 ; 39.000 ; ; -; nIOSTRB ; RA[0] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ; -; nIOSTRB ; RA[1] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ; -; nIOSTRB ; RA[2] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ; -; nIOSTRB ; RA[3] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ; -; nIOSTRB ; RA[4] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ; -; nIOSTRB ; RA[5] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ; -; nIOSTRB ; RA[6] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ; -; nIOSTRB ; RA[7] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ; -; nIOSTRB ; nRCS ; ; 32.000 ; 32.000 ; ; -; nWE ; D[0] ; 39.000 ; ; ; 39.000 ; -; nWE ; D[1] ; 39.000 ; ; ; 39.000 ; -; nWE ; D[2] ; 39.000 ; ; ; 39.000 ; -; nWE ; D[3] ; 39.000 ; ; ; 39.000 ; -; nWE ; D[4] ; 39.000 ; ; ; 39.000 ; -; nWE ; D[5] ; 39.000 ; ; ; 39.000 ; -; nWE ; D[6] ; 39.000 ; ; ; 39.000 ; -; nWE ; D[7] ; 39.000 ; ; ; 39.000 ; -; nWE ; RD[0] ; ; 39.000 ; 39.000 ; ; -; nWE ; RD[1] ; ; 39.000 ; 39.000 ; ; -; nWE ; RD[2] ; ; 39.000 ; 39.000 ; ; -; nWE ; RD[3] ; ; 39.000 ; 39.000 ; ; -; nWE ; RD[4] ; ; 39.000 ; 39.000 ; ; -; nWE ; RD[5] ; ; 39.000 ; 39.000 ; ; -; nWE ; RD[6] ; ; 39.000 ; 39.000 ; ; -; nWE ; RD[7] ; ; 39.000 ; 39.000 ; ; -; nWE ; nROE ; ; 32.000 ; 32.000 ; ; -; nWE ; nRWE ; ; 32.000 ; 32.000 ; ; -+------------+-------------+--------+--------+--------+--------+ - - -+-----------------------------------------------------------------------+ -; Output Enable Times ; -+-----------+------------+--------+------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-----------+------------+--------+------+------------+-----------------+ -; D[*] ; C7M ; 41.000 ; ; Rise ; C7M ; -; D[0] ; C7M ; 41.000 ; ; Rise ; C7M ; -; D[1] ; C7M ; 41.000 ; ; Rise ; C7M ; -; D[2] ; C7M ; 41.000 ; ; Rise ; C7M ; -; D[3] ; C7M ; 41.000 ; ; Rise ; C7M ; -; D[4] ; C7M ; 41.000 ; ; Rise ; C7M ; -; D[5] ; C7M ; 41.000 ; ; Rise ; C7M ; -; D[6] ; C7M ; 41.000 ; ; Rise ; C7M ; -; D[7] ; C7M ; 41.000 ; ; Rise ; C7M ; -; RD[*] ; C7M ; 41.000 ; ; Rise ; C7M ; -; RD[0] ; C7M ; 41.000 ; ; Rise ; C7M ; -; RD[1] ; C7M ; 41.000 ; ; Rise ; C7M ; -; RD[2] ; C7M ; 41.000 ; ; Rise ; C7M ; -; RD[3] ; C7M ; 41.000 ; ; Rise ; C7M ; -; RD[4] ; C7M ; 41.000 ; ; Rise ; C7M ; -; RD[5] ; C7M ; 41.000 ; ; Rise ; C7M ; -; RD[6] ; C7M ; 41.000 ; ; Rise ; C7M ; -; RD[7] ; C7M ; 41.000 ; ; Rise ; C7M ; -+-----------+------------+--------+------+------------+-----------------+ - - -+-----------------------------------------------------------------------+ -; Minimum Output Enable Times ; -+-----------+------------+--------+------+------------+-----------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+-----------+------------+--------+------+------------+-----------------+ -; D[*] ; C7M ; 41.000 ; ; Rise ; C7M ; -; D[0] ; C7M ; 41.000 ; ; Rise ; C7M ; -; D[1] ; C7M ; 41.000 ; ; Rise ; C7M ; -; D[2] ; C7M ; 41.000 ; ; Rise ; C7M ; -; D[3] ; C7M ; 41.000 ; ; Rise ; C7M ; -; D[4] ; C7M ; 41.000 ; ; Rise ; C7M ; -; D[5] ; C7M ; 41.000 ; ; Rise ; C7M ; -; D[6] ; C7M ; 41.000 ; ; Rise ; C7M ; -; D[7] ; C7M ; 41.000 ; ; Rise ; C7M ; -; RD[*] ; C7M ; 41.000 ; ; Rise ; C7M ; -; RD[0] ; C7M ; 41.000 ; ; Rise ; C7M ; -; RD[1] ; C7M ; 41.000 ; ; Rise ; C7M ; -; RD[2] ; C7M ; 41.000 ; ; Rise ; C7M ; -; RD[3] ; C7M ; 41.000 ; ; Rise ; C7M ; -; RD[4] ; C7M ; 41.000 ; ; Rise ; C7M ; -; RD[5] ; C7M ; 41.000 ; ; Rise ; C7M ; -; RD[6] ; C7M ; 41.000 ; ; Rise ; C7M ; -; RD[7] ; C7M ; 41.000 ; ; Rise ; C7M ; -+-----------+------------+--------+------+------------+-----------------+ - - -+-------------------------------------------------------------------------------+ -; Output Disable Times ; -+-----------+------------+-----------+-----------+------------+-----------------+ -; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; -+-----------+------------+-----------+-----------+------------+-----------------+ -; D[*] ; C7M ; 41.000 ; ; Rise ; C7M ; -; D[0] ; C7M ; 41.000 ; ; Rise ; C7M ; -; D[1] ; C7M ; 41.000 ; ; Rise ; C7M ; -; D[2] ; C7M ; 41.000 ; ; Rise ; C7M ; -; D[3] ; C7M ; 41.000 ; ; Rise ; C7M ; -; D[4] ; C7M ; 41.000 ; ; Rise ; C7M ; -; D[5] ; C7M ; 41.000 ; ; Rise ; C7M ; -; D[6] ; C7M ; 41.000 ; ; Rise ; C7M ; -; D[7] ; C7M ; 41.000 ; ; Rise ; C7M ; -; RD[*] ; C7M ; 41.000 ; ; Rise ; C7M ; -; RD[0] ; C7M ; 41.000 ; ; Rise ; C7M ; -; RD[1] ; C7M ; 41.000 ; ; Rise ; C7M ; -; RD[2] ; C7M ; 41.000 ; ; Rise ; C7M ; -; RD[3] ; C7M ; 41.000 ; ; Rise ; C7M ; -; RD[4] ; C7M ; 41.000 ; ; Rise ; C7M ; -; RD[5] ; C7M ; 41.000 ; ; Rise ; C7M ; -; RD[6] ; C7M ; 41.000 ; ; Rise ; C7M ; -; RD[7] ; C7M ; 41.000 ; ; Rise ; C7M ; -+-----------+------------+-----------+-----------+------------+-----------------+ - - -+-------------------------------------------------------------------------------+ -; Minimum Output Disable Times ; -+-----------+------------+-----------+-----------+------------+-----------------+ -; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; -+-----------+------------+-----------+-----------+------------+-----------------+ -; D[*] ; C7M ; 41.000 ; ; Rise ; C7M ; -; D[0] ; C7M ; 41.000 ; ; Rise ; C7M ; -; D[1] ; C7M ; 41.000 ; ; Rise ; C7M ; -; D[2] ; C7M ; 41.000 ; ; Rise ; C7M ; -; D[3] ; C7M ; 41.000 ; ; Rise ; C7M ; -; D[4] ; C7M ; 41.000 ; ; Rise ; C7M ; -; D[5] ; C7M ; 41.000 ; ; Rise ; C7M ; -; D[6] ; C7M ; 41.000 ; ; Rise ; C7M ; -; D[7] ; C7M ; 41.000 ; ; Rise ; C7M ; -; RD[*] ; C7M ; 41.000 ; ; Rise ; C7M ; -; RD[0] ; C7M ; 41.000 ; ; Rise ; C7M ; -; RD[1] ; C7M ; 41.000 ; ; Rise ; C7M ; -; RD[2] ; C7M ; 41.000 ; ; Rise ; C7M ; -; RD[3] ; C7M ; 41.000 ; ; Rise ; C7M ; -; RD[4] ; C7M ; 41.000 ; ; Rise ; C7M ; -; RD[5] ; C7M ; 41.000 ; ; Rise ; C7M ; -; RD[6] ; C7M ; 41.000 ; ; Rise ; C7M ; -; RD[7] ; C7M ; 41.000 ; ; Rise ; C7M ; -+-----------+------------+-----------+-----------+------------+-----------------+ - - -+-------------------------------------------------------------------+ -; Setup Transfers ; -+------------+----------+----------+----------+----------+----------+ -; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; -+------------+----------+----------+----------+----------+----------+ -; C7M ; C7M ; 99 ; 0 ; 371 ; 224 ; -+------------+----------+----------+----------+----------+----------+ -Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. - - -+-------------------------------------------------------------------+ -; Hold Transfers ; -+------------+----------+----------+----------+----------+----------+ -; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; -+------------+----------+----------+----------+----------+----------+ -; C7M ; C7M ; 99 ; 0 ; 371 ; 224 ; -+------------+----------+----------+----------+----------+----------+ -Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. - - ---------------- -; Report TCCS ; ---------------- -No dedicated SERDES Transmitter circuitry present in device or used in design - - ---------------- -; Report RSKM ; ---------------- -No dedicated SERDES Receiver circuitry present in device or used in design - - -+------------------------------------------------+ -; Unconstrained Paths ; -+---------------------------------+-------+------+ -; Property ; Setup ; Hold ; -+---------------------------------+-------+------+ -; Illegal Clocks ; 0 ; 0 ; -; Unconstrained Clocks ; 0 ; 0 ; -; Unconstrained Input Ports ; 33 ; 33 ; -; Unconstrained Input Port Paths ; 466 ; 466 ; -; Unconstrained Output Ports ; 33 ; 33 ; -; Unconstrained Output Port Paths ; 264 ; 264 ; -+---------------------------------+-------+------+ - - -+------------------------------------+ -; TimeQuest Timing Analyzer Messages ; -+------------------------------------+ -Info: ******************************************************************* -Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer - Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - Info: Processing started: Sun Feb 16 00:10:48 2020 -Info: Command: quartus_sta GR8RAM -c GR8RAM -Info: qsta_default_script.tcl version: #1 -Warning (20028): Parallel compilation is not licensed and has been disabled -Info (306004): Started post-fitting delay annotation -Info (306005): Delay annotation completed successfully -Warning (335095): TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family. -Critical Warning (332012): Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. -Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" -Info (332105): Deriving Clocks - Info (332105): create_clock -period 1.000 -name C7M C7M -Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON -Critical Warning (332148): Timing requirements not met -Info (332146): Worst-case setup slack is -47.500 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= ============= ===================== - Info (332119): -47.500 -2116.500 C7M -Info (332146): Worst-case hold slack is 5.000 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= ============= ===================== - Info (332119): 5.000 0.000 C7M -Info (332140): No Recovery paths to report -Info (332140): No Removal paths to report -Info (332146): Worst-case minimum pulse width slack is -4.500 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= ============= ===================== - Info (332119): -4.500 -495.000 C7M -Info (332001): The selected device family is not supported by the report_metastability command. -Info (332102): Design is not fully constrained for setup requirements -Info (332102): Design is not fully constrained for hold requirements -Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings - Info: Peak virtual memory: 4530 megabytes - Info: Processing ended: Sun Feb 16 00:10:48 2020 - Info: Elapsed time: 00:00:00 - Info: Total CPU time (on all processors): 00:00:00 - - diff --git a/cpld/output_files/GR8RAM.sta.summary b/cpld/output_files/GR8RAM.sta.summary deleted file mode 100755 index 4062f7c..0000000 --- a/cpld/output_files/GR8RAM.sta.summary +++ /dev/null @@ -1,17 +0,0 @@ ------------------------------------------------------------- -TimeQuest Timing Analyzer Summary ------------------------------------------------------------- - -Type : Setup 'C7M' -Slack : -47.500 -TNS : -2116.500 - -Type : Hold 'C7M' -Slack : 5.000 -TNS : 0.000 - -Type : Minimum Pulse Width 'C7M' -Slack : -4.500 -TNS : -495.000 - -------------------------------------------------------------