Zane Kaminski
fc2e875ac2
Works?
2021-04-03 03:44:42 -04:00
Zane Kaminski
763861e444
ugh
2021-03-19 16:38:48 -04:00
Zane Kaminski
e4bfc93b1f
before remove UFM
2021-03-19 14:23:33 -04:00
Zane Kaminski
a336f5969b
hmm
2021-03-19 06:59:22 -04:00
Zane Kaminski
4defba0f50
better
2021-03-19 06:45:31 -04:00
Zane Kaminski
72851cefc5
ugh
2021-03-19 02:56:20 -04:00
Zane Kaminski
686fac229e
idk
2021-03-15 13:40:59 -04:00
Zane Kaminski
fdbc92725a
Remove old CPLD stuff
2021-03-15 13:40:41 -04:00
Zane Kaminski
0a649d68ac
Fabbed
2021-02-17 19:29:24 -05:00
Zane Kaminski
e2a3901004
reset button detect
2020-10-25 05:22:14 -04:00
Zane Kaminski
13c6a59278
Sketch of verilog
2020-10-07 23:32:29 -04:00
Zane Kaminski
0ad3b4640a
Many changes
2020-03-10 18:54:44 -04:00
Zane Kaminski
ac8cf35610
Put FullIOEN back
2020-02-26 03:37:20 -05:00
Zane Kaminski
ef9b5852fb
Added transfer counters
2020-02-26 03:34:33 -05:00
Zane Kaminski
fe0a092924
Added separate configuration section
2020-02-26 03:31:20 -05:00
Zane Kaminski
490fcfb8e7
Cleanup
2020-02-26 03:15:36 -05:00
Zane Kaminski
04be5a0257
Removed inhibit output
2020-02-26 03:14:33 -05:00
Zane Kaminski
92cde65a9d
Moved REGEN and IOROMEN (no functional change)
2020-02-26 03:14:13 -05:00
Zane Kaminski
a4f29ea751
Removed SetWR and FullIOEN
2020-02-26 02:13:35 -05:00
Zane Kaminski
764b09ba6a
Comments, no actual changes to CPLD verilog
2020-02-16 22:03:57 -05:00
Zane Kaminski
88a4169ab6
Fixed previous problem, working again
2020-02-16 00:11:12 -05:00
Zane Kaminski
c5f1e637ac
Doesn't work but committing for posterity
2020-02-15 23:15:54 -05:00
Zane Kaminski
6e6813786d
Merge branch 'dev' of https://github.com/ZaneKaminski/GR8RAM into dev
2020-01-26 15:15:07 -05:00
Zane Kaminski
a2eecf4475
Separated CSDBEN
2020-01-26 15:13:37 -05:00
Zane Kaminski
85e3eb627d
Removed state counter reset
2019-12-21 01:46:05 -05:00
Zane Kaminski
3e06d30382
Fixed bugs in new PLD stuff
2019-10-20 22:41:24 -04:00
Zane Kaminski
79dd794f45
New PLD revision
...
For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 15:07:38 -04:00
Zane Kaminski
21f18c14db
Recompiled just to be sure
2019-10-13 21:18:41 -04:00
Zane Kaminski
4d8af3b074
Merge branch 'dev' of https://github.com/ZaneKaminski/GR8RAM into dev
2019-10-13 01:42:28 -04:00
Zane Kaminski
67399312b6
Register reset/initial values set syntax changed
2019-10-13 01:40:25 -04:00
Zane Kaminski
cf16763591
24-bit counter, CAS fixed
2019-10-11 20:34:51 -04:00
Zane Kaminski
2382fdfda6
Made AddrH high bit variable with mode input
2019-09-07 21:16:23 -04:00
Zane Kaminski
b0a001aa58
Clarified assignments
2019-09-06 17:26:42 -04:00
Zane Kaminski
47a4c012d7
Pipelined addition
2019-09-04 21:45:56 -04:00
Zane Kaminski
106df31f52
Trying again with RamFactor firmware
2019-09-02 20:56:37 -04:00
Zane Kaminski
a73cbf10ef
Clarifications and bugfixes, will try again
2019-09-02 01:42:07 -04:00
Zane Kaminski
5b230c0966
1MB CPLD design seems to work, fails Apple BIST
2019-09-01 21:18:44 -04:00
Zane Kaminski
e78807ce85
CPLD firmware compiles
2019-08-31 22:55:04 -04:00